arch/powerpc/boot/dts/fsl/t4240qds.dts

   1 /*
   2  * T4240QDS Device Tree Source
   3  *
   4  * Copyright 2012 - 2014 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "t4240si-pre.dtsi"
  36
  37 / {
  38         model = "fsl,T4240QDS";
  39         compatible = "fsl,T4240QDS";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         ifc: localbus@ffe124000 {
  45                 reg = <0xf 0xfe124000 0 0x2000>;
  46                 ranges = <0 0 0xf 0xe8000000 0x08000000
  47                           2 0 0xf 0xff800000 0x00010000
  48                           3 0 0xf 0xffdf0000 0x00008000>;
  49
  50                 nor@0,0 {
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53                         compatible = "cfi-flash";
  54                         reg = <0x0 0x0 0x8000000>;
  55
  56                         bank-width = <2>;
  57                         device-width = <1>;
  58                 };
  59
  60                 nand@2,0 {
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63                         compatible = "fsl,ifc-nand";
  64                         reg = <0x2 0x0 0x10000>;
  65
  66                         partition@0 {
  67                                 /* This location must not be altered  */
  68                                 /* 1MB for u-boot Bootloader Image */
  69                                 reg = <0x0 0x00100000>;
  70                                 label = "NAND U-Boot Image";
  71                                 read-only;
  72                         };
  73
  74                         partition@100000 {
  75                                 /* 1MB for DTB Image */
  76                                 reg = <0x00100000 0x00100000>;
  77                                 label = "NAND DTB Image";
  78                         };
  79
  80                         partition@200000 {
  81                                 /* 10MB for Linux Kernel Image */
  82                                 reg = <0x00200000 0x00A00000>;
  83                                 label = "NAND Linux Kernel Image";
  84                         };
  85
  86                         partition@C00000 {
  87                                 /* 500MB for Root file System Image */
  88                                 reg = <0x00c00000 0x1F400000>;
  89                                 label = "NAND RFS Image";
  90                         };
  91                 };
  92
  93                 board-control@3,0 {
  94                         compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
  95                         reg = <3 0 0x300>;
  96                 };
  97         };
  98
  99         memory {
 100                 device_type = "memory";
 101         };
 102
 103         reserved-memory {
 104                 #address-cells = <2>;
 105                 #size-cells = <2>;
 106                 ranges;
 107
 108                 bman_fbpr: bman-fbpr {
 109                         size = <0 0x1000000>;
 110                         alignment = <0 0x1000000>;
 111                 };
 112                 qman_fqd: qman-fqd {
 113                         size = <0 0x400000>;
 114                         alignment = <0 0x400000>;
 115                 };
 116                 qman_pfdr: qman-pfdr {
 117                         size = <0 0x2000000>;
 118                         alignment = <0 0x2000000>;
 119                 };
 120         };
 121
 122         dcsr: dcsr@f00000000 {
 123                 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
 124         };
 125
 126         bportals: bman-portals@ff4000000 {
 127                 ranges = <0x0 0xf 0xf4000000 0x2000000>;
 128         };
 129
 130         qportals: qman-portals@ff6000000 {
 131                 ranges = <0x0 0xf 0xf6000000 0x2000000>;
 132         };
 133
 134         soc: soc@ffe000000 {
 135                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 136                 reg = <0xf 0xfe000000 0 0x00001000>;
 137                 spi@110000 {
 138                         flash@0 {
 139                                 #address-cells = <1>;
 140                                 #size-cells = <1>;
 141                                 compatible = "sst,sst25wf040";
 142                                 reg = <0>;
 143                                 spi-max-frequency = <40000000>; /* input clock */
 144                         };
 145                 };
 146
 147                 i2c@118000 {
 148                         mux@77 {
 149                                 compatible = "nxp,pca9547";
 150                                 reg = <0x77>;
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153
 154                                 i2c@0 {
 155                                         #address-cells = <1>;
 156                                         #size-cells = <0>;
 157                                         reg = <0>;
 158
 159                                         eeprom@51 {
 160                                                 compatible = "at24,24c256";
 161                                                 reg = <0x51>;
 162                                         };
 163                                         eeprom@52 {
 164                                                 compatible = "at24,24c256";
 165                                                 reg = <0x52>;
 166                                         };
 167                                         eeprom@53 {
 168                                                 compatible = "at24,24c256";
 169                                                 reg = <0x53>;
 170                                         };
 171                                         eeprom@54 {
 172                                                 compatible = "at24,24c256";
 173                                                 reg = <0x54>;
 174                                         };
 175                                         eeprom@55 {
 176                                                 compatible = "at24,24c256";
 177                                                 reg = <0x55>;
 178                                         };
 179                                         eeprom@56 {
 180                                                 compatible = "at24,24c256";
 181                                                 reg = <0x56>;
 182                                         };
 183                                         rtc@68 {
 184                                                 compatible = "dallas,ds3232";
 185                                                 reg = <0x68>;
 186                                                 interrupts = <0x1 0x1 0 0>;
 187                                         };
 188                                 };
 189
 190                                 i2c@2 {
 191                                         #address-cells = <1>;
 192                                         #size-cells = <0>;
 193                                         reg = <0x2>;
 194
 195                                         ina220@40 {
 196                                                 compatible = "ti,ina220";
 197                                                 reg = <0x40>;
 198                                                 shunt-resistor = <1000>;
 199                                         };
 200
 201                                         ina220@41 {
 202                                                 compatible = "ti,ina220";
 203                                                 reg = <0x41>;
 204                                                 shunt-resistor = <1000>;
 205                                         };
 206
 207                                         ina220@44 {
 208                                                 compatible = "ti,ina220";
 209                                                 reg = <0x44>;
 210                                                 shunt-resistor = <1000>;
 211                                         };
 212
 213                                         ina220@45 {
 214                                                 compatible = "ti,ina220";
 215                                                 reg = <0x45>;
 216                                                 shunt-resistor = <1000>;
 217                                         };
 218
 219                                         ina220@46 {
 220                                                 compatible = "ti,ina220";
 221                                                 reg = <0x46>;
 222                                                 shunt-resistor = <1000>;
 223                                         };
 224
 225                                         ina220@47 {
 226                                                 compatible = "ti,ina220";
 227                                                 reg = <0x47>;
 228                                                 shunt-resistor = <1000>;
 229                                         };
 230                                 };
 231                         };
 232                 };
 233
 234                 sdhc@114000 {
 235                         voltage-ranges = <1800 1800 3300 3300>;
 236                 };
 237         };
 238
 239         pci0: pcie@ffe240000 {
 240                 reg = <0xf 0xfe240000 0 0x10000>;
 241                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 242                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 243                 pcie@0 {
 244                         ranges = <0x02000000 0 0xe0000000
 245                                   0x02000000 0 0xe0000000
 246                                   0 0x20000000
 247
 248                                   0x01000000 0 0x00000000
 249                                   0x01000000 0 0x00000000
 250                                   0 0x00010000>;
 251                 };
 252         };
 253
 254         pci1: pcie@ffe250000 {
 255                 reg = <0xf 0xfe250000 0 0x10000>;
 256                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 257                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 258                 pcie@0 {
 259                         ranges = <0x02000000 0 0xe0000000
 260                                   0x02000000 0 0xe0000000
 261                                   0 0x20000000
 262
 263                                   0x01000000 0 0x00000000
 264                                   0x01000000 0 0x00000000
 265                                   0 0x00010000>;
 266                 };
 267         };
 268
 269         pci2: pcie@ffe260000 {
 270                 reg = <0xf 0xfe260000 0 0x1000>;
 271                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 272                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 273                 pcie@0 {
 274                         ranges = <0x02000000 0 0xe0000000
 275                                   0x02000000 0 0xe0000000
 276                                   0 0x20000000
 277
 278                                   0x01000000 0 0x00000000
 279                                   0x01000000 0 0x00000000
 280                                   0 0x00010000>;
 281                 };
 282         };
 283
 284         pci3: pcie@ffe270000 {
 285                 reg = <0xf 0xfe270000 0 0x10000>;
 286                 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
 287                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 288                 pcie@0 {
 289                         ranges = <0x02000000 0 0xe0000000
 290                                   0x02000000 0 0xe0000000
 291                                   0 0x20000000
 292
 293                                   0x01000000 0 0x00000000
 294                                   0x01000000 0 0x00000000
 295                                   0 0x00010000>;
 296                 };
 297         };
 298         rio: rapidio@ffe0c0000 {
 299                 reg = <0xf 0xfe0c0000 0 0x11000>;
 300
 301                 port1 {
 302                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
 303                 };
 304                 port2 {
 305                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
 306                 };
 307         };
 308 };
 309
 310 /include/ "t4240si-post.dtsi"