arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008, 2011 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /include/ "fsl/mpc8548si-pre.dtsi"
  13
  14 / {
  15         model = "MPC8548CDS";
  16         compatible = "MPC8548CDS", "MPC85xxCDS";
  17
  18         aliases {
  19                 ethernet0 = &enet0;
  20                 ethernet1 = &enet1;
  21                 ethernet2 = &enet2;
  22                 ethernet3 = &enet3;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         memory {
  31                 device_type = "memory";
  32                 reg = <0 0 0x0 0x8000000>;      // 128M at 0x0
  33         };
  34
  35         lbc: localbus@e0005000 {
  36                 reg = <0 0xe0005000 0 0x1000>;
  37
  38                 ranges = <0x0 0x0 0x0 0xff000000 0x01000000>;
  39
  40                 nor@0,0 {
  41                         #address-cells = <1>;
  42                         #size-cells = <1>;
  43                         compatible = "cfi-flash";
  44                         reg = <0x0 0x0 0x01000000>;
  45                         bank-width = <2>;
  46                         device-width = <2>;
  47
  48                         partition@0 {
  49                                 reg = <0x0 0x0b00000>;
  50                                 label = "ramdisk-nor";
  51                         };
  52
  53                         partition@300000 {
  54                                 reg = <0x0b00000 0x0400000>;
  55                                 label = "kernel-nor";
  56                         };
  57
  58                         partition@700000 {
  59                                 reg = <0x0f00000 0x060000>;
  60                                 label = "dtb-nor";
  61                         };
  62
  63                         partition@760000 {
  64                                 reg = <0x0f60000 0x020000>;
  65                                 label = "env-nor";
  66                                 read-only;
  67                         };
  68
  69                         partition@780000 {
  70                                 reg = <0x0f80000 0x080000>;
  71                                 label = "u-boot-nor";
  72                                 read-only;
  73                         };
  74                 };
  75         };
  76
  77         soc: soc8548@e0000000 {
  78                 ranges = <0 0x0 0xe0000000 0x100000>;
  79
  80                 i2c@3000 {
  81                         eeprom@50 {
  82                                 compatible = "atmel,24c64";
  83                                 reg = <0x50>;
  84                         };
  85
  86                         eeprom@56 {
  87                                 compatible = "atmel,24c64";
  88                                 reg = <0x56>;
  89                         };
  90
  91                         eeprom@57 {
  92                                 compatible = "atmel,24c64";
  93                                 reg = <0x57>;
  94                         };
  95                 };
  96
  97                 i2c@3100 {
  98                         eeprom@50 {
  99                                 compatible = "atmel,24c64";
 100                                 reg = <0x50>;
 101                         };
 102                 };
 103
 104                 enet0: ethernet@24000 {
 105                         tbi-handle = <&tbi0>;
 106                         phy-handle = <&phy0>;
 107                 };
 108
 109                 mdio@24520 {
 110                         phy0: ethernet-phy@0 {
 111                                 interrupts = <5 1 0 0>;
 112                                 reg = <0x0>;
 113                                 device_type = "ethernet-phy";
 114                         };
 115                         phy1: ethernet-phy@1 {
 116                                 interrupts = <5 1 0 0>;
 117                                 reg = <0x1>;
 118                                 device_type = "ethernet-phy";
 119                         };
 120                         phy2: ethernet-phy@2 {
 121                                 interrupts = <5 1 0 0>;
 122                                 reg = <0x2>;
 123                                 device_type = "ethernet-phy";
 124                         };
 125                         phy3: ethernet-phy@3 {
 126                                 interrupts = <5 1 0 0>;
 127                                 reg = <0x3>;
 128                                 device_type = "ethernet-phy";
 129                         };
 130                         tbi0: tbi-phy@11 {
 131                                 reg = <0x11>;
 132                                 device_type = "tbi-phy";
 133                         };
 134                 };
 135
 136                 enet1: ethernet@25000 {
 137                         tbi-handle = <&tbi1>;
 138                         phy-handle = <&phy1>;
 139                 };
 140
 141                 mdio@25520 {
 142                         tbi1: tbi-phy@11 {
 143                                 reg = <0x11>;
 144                                 device_type = "tbi-phy";
 145                         };
 146                 };
 147
 148                 enet2: ethernet@26000 {
 149                         tbi-handle = <&tbi2>;
 150                         phy-handle = <&phy2>;
 151                 };
 152
 153                 mdio@26520 {
 154                         tbi2: tbi-phy@11 {
 155                                 reg = <0x11>;
 156                                 device_type = "tbi-phy";
 157                         };
 158                 };
 159
 160                 enet3: ethernet@27000 {
 161                         tbi-handle = <&tbi3>;
 162                         phy-handle = <&phy3>;
 163                 };
 164
 165                 mdio@27520 {
 166                         tbi3: tbi-phy@11 {
 167                                 reg = <0x11>;
 168                                 device_type = "tbi-phy";
 169                         };
 170                 };
 171         };
 172
 173         pci0: pci@e0008000 {
 174                 reg = <0 0xe0008000 0 0x1000>;
 175                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
 176                           0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
 177                 clock-frequency = <66666666>;
 178                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 179                 interrupt-map = <
 180                         /* IDSEL 0x4 (PCIX Slot 2) */
 181                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 182                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 183                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 184                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 185
 186                         /* IDSEL 0x5 (PCIX Slot 3) */
 187                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 188                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
 189                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
 190                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
 191
 192                         /* IDSEL 0x6 (PCIX Slot 4) */
 193                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 194                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 195                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 196                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 197
 198                         /* IDSEL 0x8 (PCIX Slot 5) */
 199                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 200                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 201                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 202                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 203
 204                         /* IDSEL 0xC (Tsi310 bridge) */
 205                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 206                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 207                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 208                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 209
 210                         /* IDSEL 0x14 (Slot 2) */
 211                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 212                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 213                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 214                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 215
 216                         /* IDSEL 0x15 (Slot 3) */
 217                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 218                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
 219                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
 220                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
 221
 222                         /* IDSEL 0x16 (Slot 4) */
 223                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 224                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 225                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 226                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 227
 228                         /* IDSEL 0x18 (Slot 5) */
 229                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 230                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 231                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 232                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 233
 234                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 235                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 236                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 237                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 238                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
 239
 240                 pci_bridge@1c {
 241                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 242                         interrupt-map = <
 243
 244                                 /* IDSEL 0x00 (PrPMC Site) */
 245                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 246                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 247                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 248                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 249
 250                                 /* IDSEL 0x04 (VIA chip) */
 251                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
 252                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 253                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 254                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
 255
 256                                 /* IDSEL 0x05 (8139) */
 257                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
 258
 259                                 /* IDSEL 0x06 (Slot 6) */
 260                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
 261                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
 262                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
 263                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
 264
 265                                 /* IDESL 0x07 (Slot 7) */
 266                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
 267                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
 268                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
 269                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
 270
 271                         reg = <0xe000 0x0 0x0 0x0 0x0>;
 272                         #interrupt-cells = <1>;
 273                         #size-cells = <2>;
 274                         #address-cells = <3>;
 275                         ranges = <0x2000000 0x0 0x80000000
 276                                   0x2000000 0x0 0x80000000
 277                                   0x0 0x20000000
 278                                   0x1000000 0x0 0x0
 279                                   0x1000000 0x0 0x0
 280                                   0x0 0x80000>;
 281                         clock-frequency = <33333333>;
 282
 283                         isa@4 {
 284                                 device_type = "isa";
 285                                 #interrupt-cells = <2>;
 286                                 #size-cells = <1>;
 287                                 #address-cells = <2>;
 288                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
 289                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 290                                 interrupt-parent = <&i8259>;
 291
 292                                 i8259: interrupt-controller@20 {
 293                                         interrupt-controller;
 294                                         device_type = "interrupt-controller";
 295                                         reg = <0x1 0x20 0x2
 296                                                0x1 0xa0 0x2
 297                                                0x1 0x4d0 0x2>;
 298                                         #address-cells = <0>;
 299                                         #interrupt-cells = <2>;
 300                                         compatible = "chrp,iic";
 301                                         interrupts = <0 1 0 0>;
 302                                         interrupt-parent = <&mpic>;
 303                                 };
 304
 305                                 rtc@70 {
 306                                         compatible = "pnpPNP,b00";
 307                                         reg = <0x1 0x70 0x2>;
 308                                 };
 309                         };
 310                 };
 311         };
 312
 313         pci1: pci@e0009000 {
 314                 reg = <0 0xe0009000 0 0x1000>;
 315                 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
 316                           0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
 317                 clock-frequency = <66666666>;
 318                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 319                 interrupt-map = <
 320
 321                         /* IDSEL 0x15 */
 322                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
 323                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
 324                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
 325                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
 326         };
 327
 328         pci2: pcie@e000a000 {
 329                 reg = <0 0xe000a000 0 0x1000>;
 330                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 331                           0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
 332                 pcie@0 {
 333                         ranges = <0x2000000 0x0 0xa0000000
 334                                   0x2000000 0x0 0xa0000000
 335                                   0x0 0x20000000
 336
 337                                   0x1000000 0x0 0x0
 338                                   0x1000000 0x0 0x0
 339                                   0x0 0x100000>;
 340                 };
 341         };
 342 };
 343
 344 /include/ "fsl/mpc8548si-post.dtsi"