1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
2 #define _ASM_POWERPC_MMU_HASH64_H_
4 * PowerPC64 memory management structures
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <asm/asm-compat.h>
22 #define STE_ESID_V 0x80
23 #define STE_ESID_KS 0x20
24 #define STE_ESID_KP 0x10
25 #define STE_ESID_N 0x08
27 #define STE_VSID_SHIFT 12
29 /* Location of cpu0's segment table */
30 #define STAB0_PAGE 0x8
31 #define STAB0_OFFSET (STAB0_PAGE << 12)
32 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
35 extern char initial_stab[];
36 #endif /* ! __ASSEMBLY */
42 #define SLB_NUM_BOLTED 3
43 #define SLB_CACHE_ENTRIES 8
44 #define SLB_MIN_SIZE 32
46 /* Bits in the SLB ESID word */
47 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
49 /* Bits in the SLB VSID word */
50 #define SLB_VSID_SHIFT 12
51 #define SLB_VSID_SHIFT_1T 24
52 #define SLB_VSID_SSIZE_SHIFT 62
53 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
54 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
55 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
56 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
57 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
58 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
59 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
60 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
61 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
62 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
63 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
64 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
65 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
66 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
68 #define SLB_VSID_KERNEL (SLB_VSID_KP)
69 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
71 #define SLBIE_C (0x08000000)
72 #define SLBIE_SSIZE_SHIFT 25
78 #define HPTES_PER_GROUP 8
80 #define HPTE_V_SSIZE_SHIFT 62
81 #define HPTE_V_AVPN_SHIFT 7
82 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
83 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
84 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
85 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
86 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
87 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
88 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
89 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
91 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
92 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
93 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
94 #define HPTE_R_RPN_SHIFT 12
95 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
96 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
97 #define HPTE_R_N ASM_CONST(0x0000000000000004)
98 #define HPTE_R_G ASM_CONST(0x0000000000000008)
99 #define HPTE_R_M ASM_CONST(0x0000000000000010)
100 #define HPTE_R_I ASM_CONST(0x0000000000000020)
101 #define HPTE_R_W ASM_CONST(0x0000000000000040)
102 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
103 #define HPTE_R_C ASM_CONST(0x0000000000000080)
104 #define HPTE_R_R ASM_CONST(0x0000000000000100)
105 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
107 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
108 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
110 /* Values for PP (assumes Ks=0, Kp=1) */
111 #define PP_RWXX 0 /* Supervisor read/write, User none */
112 #define PP_RWRX 1 /* Supervisor read/write, User read */
113 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
114 #define PP_RXRX 3 /* Supervisor read, User read */
115 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
124 extern struct hash_pte *htab_address;
125 extern unsigned long htab_size_bytes;
126 extern unsigned long htab_hash_mask;
129 * Page size definition
131 * shift : is the "PAGE_SHIFT" value for that page size
132 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
133 * directly to a slbmte "vsid" value
134 * penc : is the HPTE encoding mask for the "LP" field:
139 unsigned int shift; /* number of bits */
140 unsigned int penc; /* HPTE encoding */
141 unsigned int tlbiel; /* tlbiel supported for that page size */
142 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
143 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
146 #endif /* __ASSEMBLY__ */
150 * These are the values used by hardware in the B field of
151 * SLB entries and the first dword of MMU hashtable entries.
152 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
154 #define MMU_SEGSIZE_256M 0
155 #define MMU_SEGSIZE_1T 1
158 * encode page number shift.
159 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
160 * 12 bits. This enable us to address upto 76 bit va.
161 * For hpt hash from a va we can ignore the page size bits of va and for
162 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
163 * we work in all cases including 4k page size.
169 static inline int segment_shift(int ssize)
171 if (ssize == MMU_SEGSIZE_256M)
177 * The current system page and segment sizes
179 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
180 extern int mmu_linear_psize;
181 extern int mmu_virtual_psize;
182 extern int mmu_vmalloc_psize;
183 extern int mmu_vmemmap_psize;
184 extern int mmu_io_psize;
185 extern int mmu_kernel_ssize;
186 extern int mmu_highuser_ssize;
187 extern u16 mmu_slb_size;
188 extern unsigned long tce_alloc_start, tce_alloc_end;
191 * If the processor supports 64k normal pages but not 64k cache
192 * inhibited pages, we have to be prepared to switch processes
193 * to use 4k pages when they create cache-inhibited mappings.
194 * If this is the case, mmu_ci_restrictions will be set to 1.
196 extern int mmu_ci_restrictions;
199 * This computes the AVPN and B fields of the first dword of a HPTE,
200 * for use when we want to match an existing PTE. The bottom 7 bits
201 * of the returned value are zero.
203 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
208 * The AVA field omits the low-order 23 bits of the 78 bits VA.
209 * These bits are not needed in the PTE, because the
210 * low-order b of these bits are part of the byte offset
211 * into the virtual page and, if b < 23, the high-order
212 * 23-b of these bits are always used in selecting the
213 * PTEGs to be searched
215 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
216 v <<= HPTE_V_AVPN_SHIFT;
217 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
222 * This function sets the AVPN and L fields of the HPTE appropriately
225 static inline unsigned long hpte_encode_v(unsigned long vpn,
226 int psize, int ssize)
229 v = hpte_encode_avpn(vpn, psize, ssize);
230 if (psize != MMU_PAGE_4K)
236 * This function sets the ARPN, and LP fields of the HPTE appropriately
237 * for the page size. We assume the pa is already "clean" that is properly
238 * aligned for the requested page size
240 static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
244 /* A 4K page needs no special encoding */
245 if (psize == MMU_PAGE_4K)
246 return pa & HPTE_R_RPN;
248 unsigned int penc = mmu_psize_defs[psize].penc;
249 unsigned int shift = mmu_psize_defs[psize].shift;
250 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
256 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
258 static inline unsigned long hpt_vpn(unsigned long ea,
259 unsigned long vsid, int ssize)
262 int s_shift = segment_shift(ssize);
264 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
265 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
269 * This hashes a virtual address
271 static inline unsigned long hpt_hash(unsigned long vpn,
272 unsigned int shift, int ssize)
275 unsigned long hash, vsid;
277 /* VPN_SHIFT can be atmost 12 */
278 if (ssize == MMU_SEGSIZE_256M) {
279 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
280 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
281 ((vpn & mask) >> (shift - VPN_SHIFT));
283 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
284 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
285 hash = vsid ^ (vsid << 25) ^
286 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
288 return hash & 0x7fffffffffUL;
291 extern int __hash_page_4K(unsigned long ea, unsigned long access,
292 unsigned long vsid, pte_t *ptep, unsigned long trap,
293 unsigned int local, int ssize, int subpage_prot);
294 extern int __hash_page_64K(unsigned long ea, unsigned long access,
295 unsigned long vsid, pte_t *ptep, unsigned long trap,
296 unsigned int local, int ssize);
298 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
299 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
300 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
301 pte_t *ptep, unsigned long trap, int local, int ssize,
302 unsigned int shift, unsigned int mmu_psize);
303 extern void hash_failure_debug(unsigned long ea, unsigned long access,
304 unsigned long vsid, unsigned long trap,
305 int ssize, int psize, unsigned long pte);
306 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
307 unsigned long pstart, unsigned long prot,
308 int psize, int ssize);
309 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
310 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
312 extern void hpte_init_native(void);
313 extern void hpte_init_lpar(void);
314 extern void hpte_init_beat(void);
315 extern void hpte_init_beat_v3(void);
317 extern void stabs_alloc(void);
318 extern void slb_initialize(void);
319 extern void slb_flush_and_rebolt(void);
320 extern void stab_initialize(unsigned long stab);
322 extern void slb_vmalloc_update(void);
323 extern void slb_set_size(u16 size);
324 #endif /* __ASSEMBLY__ */
329 * We first generate a 36-bit "proto-VSID". For kernel addresses this
330 * is equal to the ESID, for user addresses it is:
331 * (context << 15) | (esid & 0x7fff)
333 * The two forms are distinguishable because the top bit is 0 for user
334 * addresses, whereas the top two bits are 1 for kernel addresses.
335 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
338 * The proto-VSIDs are then scrambled into real VSIDs with the
339 * multiplicative hash:
341 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
342 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
343 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
345 * This scramble is only well defined for proto-VSIDs below
346 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
347 * reserved. VSID_MULTIPLIER is prime, so in particular it is
348 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
349 * Because the modulus is 2^n-1 we can compute it efficiently without
350 * a divide or extra multiply (see below).
352 * This scheme has several advantages over older methods:
354 * - We have VSIDs allocated for every kernel address
355 * (i.e. everything above 0xC000000000000000), except the very top
356 * segment, which simplifies several things.
358 * - We allow for 16 significant bits of ESID and 19 bits of
359 * context for user addresses. i.e. 16T (44 bits) of address space for
360 * up to half a million contexts.
362 * - The scramble function gives robust scattering in the hash
363 * table (at least based on some initial results). The previous
364 * method was more susceptible to pathological cases giving excessive
368 * WARNING - If you change these you must make sure the asm
369 * implementations in slb_allocate (slb_low.S), do_stab_bolted
370 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
373 #define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
374 #define VSID_BITS_256M 36
375 #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
377 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
378 #define VSID_BITS_1T 24
379 #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
381 #define CONTEXT_BITS 19
382 #define USER_ESID_BITS 16
383 #define USER_ESID_BITS_1T 4
385 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
388 * This macro generates asm code to compute the VSID scramble
389 * function. Used in slb_allocate() and do_stab_bolted. The function
390 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
392 * rt = register continaing the proto-VSID and into which the
393 * VSID will be stored
394 * rx = scratch register (clobbered)
396 * - rt and rx must be different registers
397 * - The answer will end up in the low VSID_BITS bits of rt. The higher
398 * bits may contain other garbage, so you may need to mask the
401 #define ASM_VSID_SCRAMBLE(rt, rx, size) \
402 lis rx,VSID_MULTIPLIER_##size@h; \
403 ori rx,rx,VSID_MULTIPLIER_##size@l; \
404 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
406 srdi rx,rt,VSID_BITS_##size; \
407 clrldi rt,rt,(64-VSID_BITS_##size); \
408 add rt,rt,rx; /* add high and low bits */ \
409 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
410 * 2^36-1+2^28-1. That in particular means that if r3 >= \
411 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
412 * the bit clear, r3 already has the answer we want, if it \
413 * doesn't, the answer is the low 36 bits of r3+1. So in all \
414 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
416 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
422 #ifdef CONFIG_PPC_SUBPAGE_PROT
424 * For the sub-page protection option, we extend the PGD with one of
425 * these. Basically we have a 3-level tree, with the top level being
426 * the protptrs array. To optimize speed and memory consumption when
427 * only addresses < 4GB are being protected, pointers to the first
428 * four pages of sub-page protection words are stored in the low_prot
430 * Each page of sub-page protection words protects 1GB (4 bytes
431 * protects 64k). For the 3-level tree, each page of pointers then
434 struct subpage_prot_table {
435 unsigned long maxaddr; /* only addresses < this are protected */
436 unsigned int **protptrs[2];
437 unsigned int *low_prot[4];
440 #define SBP_L1_BITS (PAGE_SHIFT - 2)
441 #define SBP_L2_BITS (PAGE_SHIFT - 3)
442 #define SBP_L1_COUNT (1 << SBP_L1_BITS)
443 #define SBP_L2_COUNT (1 << SBP_L2_BITS)
444 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
445 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
447 extern void subpage_prot_free(struct mm_struct *mm);
448 extern void subpage_prot_init_new_context(struct mm_struct *mm);
450 static inline void subpage_prot_free(struct mm_struct *mm) {}
451 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
452 #endif /* CONFIG_PPC_SUBPAGE_PROT */
454 typedef unsigned long mm_context_id_t;
459 u16 user_psize; /* page size index */
461 #ifdef CONFIG_PPC_MM_SLICES
462 u64 low_slices_psize; /* SLB page size encodings */
464 * Right now we support 64TB and 4 bits for each
465 * 1TB slice we need 32 bytes for 64TB.
467 unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
469 u16 sllp; /* SLB page size encoding */
471 unsigned long vdso_base;
472 #ifdef CONFIG_PPC_SUBPAGE_PROT
473 struct subpage_prot_table spt;
474 #endif /* CONFIG_PPC_SUBPAGE_PROT */
475 #ifdef CONFIG_PPC_ICSWX
476 struct spinlock *cop_lockp; /* guard acop and cop_pid */
477 unsigned long acop; /* mask of enabled coprocessor types */
478 unsigned int cop_pid; /* pid value used with coprocessors */
479 #endif /* CONFIG_PPC_ICSWX */
485 * The code below is equivalent to this function for arguments
486 * < 2^VSID_BITS, which is all this should ever be called
487 * with. However gcc is not clever enough to compute the
488 * modulus (2^n-1) without a second multiply.
490 #define vsid_scramble(protovsid, size) \
491 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
494 #define vsid_scramble(protovsid, size) \
497 x = (protovsid) * VSID_MULTIPLIER_##size; \
498 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
499 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
503 /* This is only valid for addresses >= PAGE_OFFSET */
504 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
506 if (ssize == MMU_SEGSIZE_256M)
507 return vsid_scramble(ea >> SID_SHIFT, 256M);
508 return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
511 /* Returns the segment size indicator for a user address */
512 static inline int user_segment_size(unsigned long addr)
514 /* Use 1T segments if possible for addresses >= 1T */
515 if (addr >= (1UL << SID_SHIFT_1T))
516 return mmu_highuser_ssize;
517 return MMU_SEGSIZE_256M;
520 /* This is only valid for user addresses (which are below 2^44) */
521 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
524 if (ssize == MMU_SEGSIZE_256M)
525 return vsid_scramble((context << USER_ESID_BITS)
526 | (ea >> SID_SHIFT), 256M);
527 return vsid_scramble((context << USER_ESID_BITS_1T)
528 | (ea >> SID_SHIFT_1T), 1T);
531 #endif /* __ASSEMBLY__ */
533 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */