1 menu "Platform support"
3 source "arch/powerpc/platforms/powernv/Kconfig"
4 source "arch/powerpc/platforms/pseries/Kconfig"
5 source "arch/powerpc/platforms/chrp/Kconfig"
6 source "arch/powerpc/platforms/512x/Kconfig"
7 source "arch/powerpc/platforms/52xx/Kconfig"
8 source "arch/powerpc/platforms/powermac/Kconfig"
9 source "arch/powerpc/platforms/prep/Kconfig"
10 source "arch/powerpc/platforms/maple/Kconfig"
11 source "arch/powerpc/platforms/pasemi/Kconfig"
12 source "arch/powerpc/platforms/ps3/Kconfig"
13 source "arch/powerpc/platforms/cell/Kconfig"
14 source "arch/powerpc/platforms/8xx/Kconfig"
15 source "arch/powerpc/platforms/82xx/Kconfig"
16 source "arch/powerpc/platforms/83xx/Kconfig"
17 source "arch/powerpc/platforms/85xx/Kconfig"
18 source "arch/powerpc/platforms/86xx/Kconfig"
19 source "arch/powerpc/platforms/embedded6xx/Kconfig"
20 source "arch/powerpc/platforms/44x/Kconfig"
21 source "arch/powerpc/platforms/40x/Kconfig"
22 source "arch/powerpc/platforms/amigaone/Kconfig"
23 source "arch/powerpc/platforms/wsp/Kconfig"
26 bool "KVM Guest support"
29 This option enables various optimizations for running under the KVM
30 hypervisor. Overhead for the kernel when not running inside KVM should
33 In case of doubt, say Y
37 depends on 6xx || PPC64
39 Support for running natively on the hardware, i.e. without
40 a hypervisor. This option is not user-selectable but should
41 be selected by all platforms that need it.
43 config PPC_OF_BOOT_TRAMPOLINE
44 bool "Support booting from Open Firmware or yaboot"
45 depends on 6xx || PPC64
48 Support from booting from Open Firmware or yaboot using an
49 Open Firmware client interface. This enables the kernel to
50 communicate with open firmware to retrieve system information
51 such as the device tree.
53 In case of doubt, say Y
55 config UDBG_RTAS_CONSOLE
56 bool "RTAS based debug console"
60 config PPC_SMP_MUXED_IPI
63 Select this opton if your platform supports SMP and your
64 interrupt controller provides less than 4 interrupts to each
65 cpu. This will enable the generic code to multiplex the 4
66 messages on to one ipi.
69 bool "BEAT based debug console"
81 config PPC_EPAPR_HV_PIC
102 config RTAS_ERROR_LOGGING
107 config PPC_RTAS_DAEMON
113 bool "Proc interface to RTAS"
118 tristate "Firmware flash interface"
119 depends on PPC64 && RTAS_PROC
125 config MPIC_U3_HT_IRQS
129 config MPIC_BROKEN_REGREAD
133 This option enables a MPIC driver workaround for some chips
134 that have a bug that causes some interrupt source information
135 to not read back properly. It is safe to use on other chips as
136 well, but enabling it uses about 8KB of memory to keep copies
137 of the register contents in software.
140 depends on PPC_PSERIES
145 depends on PPC_PSERIES
146 bool "Support for GX bus based adapters"
148 Bus device driver for GX bus based adapters.
162 config PPC_INDIRECT_IO
166 config PPC_INDIRECT_PIO
168 select PPC_INDIRECT_IO
170 config PPC_INDIRECT_MMIO
172 select PPC_INDIRECT_IO
174 config PPC_IO_WORKAROUNDS
177 source "drivers/cpufreq/Kconfig"
179 menu "CPU Frequency drivers"
183 bool "Support for Apple PowerBooks"
184 depends on ADB_PMU && PPC32
185 select CPU_FREQ_TABLE
187 This adds support for frequency switching on Apple PowerBooks,
188 this currently includes some models of iBook & Titanium
191 config CPU_FREQ_PMAC64
192 bool "Support for some Apple G5s"
193 depends on PPC_PMAC && PPC64
194 select CPU_FREQ_TABLE
196 This adds support for frequency switching on Apple iMac G5,
197 and some of the more recent desktop G5 machines as well.
199 config PPC_PASEMI_CPUFREQ
200 bool "Support for PA Semi PWRficient"
201 depends on PPC_PASEMI
203 select CPU_FREQ_TABLE
205 This adds the support for frequency switching on PA Semi
206 PWRficient processors.
210 menu "CPUIdle driver"
212 source "drivers/cpuidle/Kconfig"
216 config PPC601_SYNC_FIX
217 bool "Workarounds for PPC601 bugs"
218 depends on 6xx && (PPC_PREP || PPC_PMAC)
220 Some versions of the PPC601 (the first PowerPC chip) have bugs which
221 mean that extra synchronization instructions are required near
222 certain instructions, typically those that make major changes to the
223 CPU state. These extra instructions reduce performance slightly.
224 If you say N here, these extra instructions will not be included,
225 resulting in a kernel which will run faster but may not run at all
226 on some systems with the PPC601 chip.
228 If in doubt, say Y here.
231 bool "On-chip CPU temperature sensor support"
234 G3 and G4 processors have an on-chip temperature sensor called the
235 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
236 temperature within 2-4 degrees Celsius. This option shows the current
237 on-die temperature in /proc/cpuinfo if the cpu supports it.
239 Unfortunately, on some chip revisions, this sensor is very inaccurate
240 and in many cases, does not work at all, so don't assume the cpu
241 temp is actually what /proc/cpuinfo says it is.
244 bool "Interrupt driven TAU driver (DANGEROUS)"
247 The TAU supports an interrupt driven mode which causes an interrupt
248 whenever the temperature goes out of range. This is the fastest way
249 to get notified the temp has exceeded a range. With this option off,
250 a timer is used to re-check the temperature periodically.
252 However, on some cpus it appears that the TAU interrupt hardware
253 is buggy and can cause a situation which would lead unexplained hard
256 Unless you are extending the TAU driver, or enjoy kernel/hardware
257 debugging, leave this option off.
260 bool "Average high and low temp"
263 The TAU hardware can compare the temperature to an upper and lower
264 bound. The default behavior is to show both the upper and lower
265 bound in /proc/cpuinfo. If the range is large, the temperature is
266 either changing a lot, or the TAU hardware is broken (likely on some
267 G4's). If the range is small (around 4 degrees), the temperature is
268 relatively stable. If you say Y here, a single temperature value,
269 halfway between the upper and lower bounds, will be reported in
272 If in doubt, say N here.
275 bool "Freescale QUICC Engine (QE) Support"
276 depends on FSL_SOC && PPC32
280 The QUICC Engine (QE) is a new generation of communications
281 coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
282 Selecting this option means that you wish to build a kernel
283 for a machine with a QE coprocessor.
286 bool "QE GPIO support"
287 depends on QUICC_ENGINE
289 select ARCH_REQUIRE_GPIOLIB
291 Say Y here if you're going to use hardware that connects to the
295 bool "Enable support for the CPM2 (Communications Processor Module)"
296 depends on (FSL_SOC_BOOKE && PPC32) || 8260
299 select PPC_PCI_CHOICE
300 select ARCH_REQUIRE_GPIOLIB
303 The CPM2 (Communications Processor Module) is a coprocessor on
304 embedded CPUs made by Freescale. Selecting this option means that
305 you wish to build a kernel for a machine with a CPM2 coprocessor
306 on it (826x, 827x, 8560).
309 tristate "Axon DDR2 memory device driver"
310 depends on PPC_IBM_CELL_BLADE && BLOCK
313 It registers one block device per Axon's DDR2 memory bank found
314 on a system. Block devices are called axonram?, their major and
315 minor numbers are available in /proc/devices, /proc/partitions or
316 in /sys/block/axonram?/dev.
321 select GENERIC_ISA_DMA
323 Supports for the ULI1575 PCIe south bridge that exists on some
324 Freescale reference boards. The boards all use the ULI in pretty
334 Uses information from the OF or flattened device tree to instantiate
335 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
337 source "arch/powerpc/sysdev/bestcomm/Kconfig"
340 bool "Support for simple, memory-mapped GPIO controllers"
343 select ARCH_REQUIRE_GPIOLIB
345 Say Y here to support simple, memory-mapped GPIO controllers.
346 These are usually BCSRs used to control board's switches, LEDs,
347 chip-selects, Ethernet/USB PHY's power and various other small
348 on-board peripherals.
350 config MCU_MPC8349EMITX
351 bool "MPC8349E-mITX MCU driver"
352 depends on I2C=y && PPC_83xx
354 select ARCH_REQUIRE_GPIOLIB
356 Say Y here to enable soft power-off functionality on the Freescale
357 boards with the MPC8349E-mITX-compatible MCU chips. This driver will
358 also register MCU GPIOs with the generic GPIO API, so you'll able
359 to use MCU pins as GPIOs.
362 bool "Xilinx PCI host bridge support"
363 depends on PCI && XILINX_VIRTEX