2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
4 * iSeries specific routines for PCI.
6 * Based on code from pci.c and iSeries_pci.c 32bit
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/ide.h>
28 #include <linux/pci.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/iommu.h>
36 #include <asm/abs_addr.h>
38 #include <asm/iseries/hv_call_xm.h>
39 #include <asm/iseries/mf.h>
40 #include <asm/iseries/iommu.h>
42 #include <asm/ppc-pci.h>
49 * Forward declares of prototypes.
51 static struct device_node *find_Device_Node(int bus, int devfn);
53 LIST_HEAD(iSeries_Global_Device_List);
55 static int Pci_Retry_Max = 3; /* Only retry 3 times */
56 static int Pci_Error_Flag = 1; /* Set Retry Error on. */
58 static struct pci_ops iSeries_pci_ops;
62 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
64 #define IOMM_TABLE_MAX_ENTRIES 1024
65 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
66 #define BASE_IO_MEMORY 0xE000000000000000UL
68 static unsigned long max_io_memory = BASE_IO_MEMORY;
69 static long current_iomm_table_entry;
74 static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
75 static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES];
77 static const char pci_io_text[] = "iSeries PCI I/O";
78 static DEFINE_SPINLOCK(iomm_table_lock);
81 * iomm_table_allocate_entry
83 * Adds pci_dev entry in address translation table
85 * - Allocates the number of entries required in table base on BAR
87 * - Allocates starting at BASE_IO_MEMORY and increases.
88 * - The size is round up to be a multiple of entry size.
89 * - CurrentIndex is incremented to keep track of the last entry.
90 * - Builds the resource entry for allocated BARs.
92 static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
94 struct resource *bar_res = &dev->resource[bar_num];
95 long bar_size = pci_resource_len(dev, bar_num);
98 * No space to allocate, quick exit, skip Allocation.
103 * Set Resource values.
105 spin_lock(&iomm_table_lock);
106 bar_res->name = pci_io_text;
107 bar_res->start = BASE_IO_MEMORY +
108 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
109 bar_res->end = bar_res->start + bar_size - 1;
111 * Allocate the number of table entries needed for BAR.
113 while (bar_size > 0 ) {
114 iomm_table[current_iomm_table_entry] = dev->sysdata;
115 iobar_table[current_iomm_table_entry] = bar_num;
116 bar_size -= IOMM_TABLE_ENTRY_SIZE;
117 ++current_iomm_table_entry;
119 max_io_memory = BASE_IO_MEMORY +
120 IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
121 spin_unlock(&iomm_table_lock);
125 * allocate_device_bars
127 * - Allocates ALL pci_dev BAR's and updates the resources with the
128 * BAR value. BARS with zero length will have the resources
129 * The HvCallPci_getBarParms is used to get the size of the BAR
130 * space. It calls iomm_table_allocate_entry to allocate
132 * - Loops through The Bar resources(0 - 5) including the ROM
135 static void allocate_device_bars(struct pci_dev *dev)
139 for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
140 iomm_table_allocate_entry(dev, bar_num);
144 * Log error information to system console.
145 * Filter out the device not there errors.
146 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
147 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
148 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
150 static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
151 int AgentId, int HvRc)
155 printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
156 Error_Text, Bus, SubBus, AgentId, HvRc);
160 * iSeries_pcibios_init
163 * This function checks for all possible system PCI host bridges that connect
164 * PCI buses. The system hypervisor is queried as to the guest partition
165 * ownership status. A pci_controller is built for any bus which is partially
166 * owned or fully owned by this guest partition.
168 void iSeries_pcibios_init(void)
170 struct pci_controller *phb;
171 struct device_node *node;
172 struct device_node *dn;
174 for_each_node_by_type(node, "pci") {
178 busp = (u32 *)get_property(node, "bus-range", NULL);
182 printk("bus %d appears to exist\n", bus);
183 phb = pcibios_alloc_controller(node);
187 phb->pci_mem_offset = phb->local_number = bus;
188 phb->first_busno = bus;
189 phb->last_busno = bus;
190 phb->ops = &iSeries_pci_ops;
192 /* Find and connect the devices. */
193 for (dn = NULL; (dn = of_get_next_child(node, dn)) != NULL;) {
201 reg = (u32 *)get_property(dn, "reg", NULL);
203 printk(KERN_DEBUG "no reg property!\n");
206 busp = (u32 *)get_property(dn, "linux,subbus", NULL);
208 printk(KERN_DEBUG "no subbus property!\n");
211 agent = (u32 *)get_property(dn, "linux,agent-id", NULL);
213 printk(KERN_DEBUG "no agent-id\n");
216 lsn = (u32 *)get_property(dn,
217 "linux,logical-slot-number", NULL);
219 printk(KERN_DEBUG "no logical-slot-number\n");
223 irq = iSeries_allocate_IRQ(bus, 0, *busp);
224 err = HvCallXm_connectBusUnit(bus, *busp, *agent, irq);
226 pci_Log_Error("Connect Bus Unit",
227 bus, *busp, *agent, err);
230 err = HvCallPci_configStore8(bus, *busp, *agent,
231 PCI_INTERRUPT_LINE, irq);
233 pci_Log_Error("PciCfgStore Irq Failed!",
234 bus, *busp, *agent, err);
238 pdn = kzalloc(sizeof(*pdn), GFP_KERNEL);
244 pdn->devfn = (reg[0] >> 8) & 0xff;
245 pdn->bussubno = *busp;
247 pdn->LogicalSlot = *lsn;
248 list_add_tail(&pdn->Device_List,
249 &iSeries_Global_Device_List);
255 * iSeries_pci_final_fixup(void)
257 void __init iSeries_pci_final_fixup(void)
259 struct pci_dev *pdev = NULL;
260 struct device_node *node;
263 /* Fix up at the device node and pci_dev relationship */
264 mf_display_src(0xC9000100);
266 printk("pcibios_final_fixup\n");
267 for_each_pci_dev(pdev) {
268 node = find_Device_Node(pdev->bus->number, pdev->devfn);
269 printk("pci dev %p (%x.%x), node %p\n", pdev,
270 pdev->bus->number, pdev->devfn, node);
274 pdev->sysdata = (void *)node;
275 PCI_DN(node)->pcidev = pdev;
276 allocate_device_bars(pdev);
277 iSeries_Device_Information(pdev, DeviceCount);
278 iommu_devnode_init_iSeries(node);
280 printk("PCI: Device Tree not found for 0x%016lX\n",
281 (unsigned long)pdev);
282 pdev->irq = PCI_DN(node)->Irq;
284 iSeries_activate_IRQs();
285 mf_display_src(0xC9000200);
288 void pcibios_fixup_bus(struct pci_bus *PciBus)
292 void pcibios_fixup_resources(struct pci_dev *pdev)
297 * I/0 Memory copy MUST use mmio commands on iSeries
298 * To do; For performance, include the hv call directly
300 void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
303 long NumberOfBytes = Count;
305 while (NumberOfBytes > 0) {
306 iSeries_Write_Byte(ByteValue, dest++);
310 EXPORT_SYMBOL(iSeries_memset_io);
312 void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
315 long NumberOfBytes = count;
317 while (NumberOfBytes > 0) {
318 iSeries_Write_Byte(*src++, dest++);
322 EXPORT_SYMBOL(iSeries_memcpy_toio);
324 void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
327 long NumberOfBytes = count;
329 while (NumberOfBytes > 0) {
330 *dst++ = iSeries_Read_Byte(src++);
334 EXPORT_SYMBOL(iSeries_memcpy_fromio);
337 * Look down the chain to find the matching Device Device
339 static struct device_node *find_Device_Node(int bus, int devfn)
343 list_for_each_entry(pdn, &iSeries_Global_Device_List, Device_List) {
344 if ((bus == pdn->busno) && (devfn == pdn->devfn))
352 * Returns the device node for the passed pci_dev
353 * Sanity Check Node PciDev to passed pci_dev
354 * If none is found, returns a NULL which the client must handle.
356 static struct device_node *get_Device_Node(struct pci_dev *pdev)
358 struct device_node *node;
360 node = pdev->sysdata;
361 if (node == NULL || PCI_DN(node)->pcidev != pdev)
362 node = find_Device_Node(pdev->bus->number, pdev->devfn);
368 * Config space read and write functions.
369 * For now at least, we look for the device node for the bus and devfn
370 * that we are asked to access. It may be possible to translate the devfn
371 * to a subbus and deviceid more directly.
373 static u64 hv_cfg_read_func[4] = {
374 HvCallPciConfigLoad8, HvCallPciConfigLoad16,
375 HvCallPciConfigLoad32, HvCallPciConfigLoad32
378 static u64 hv_cfg_write_func[4] = {
379 HvCallPciConfigStore8, HvCallPciConfigStore16,
380 HvCallPciConfigStore32, HvCallPciConfigStore32
384 * Read PCI config space
386 static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
387 int offset, int size, u32 *val)
389 struct device_node *node = find_Device_Node(bus->number, devfn);
391 struct HvCallPci_LoadReturn ret;
394 return PCIBIOS_DEVICE_NOT_FOUND;
397 return PCIBIOS_BAD_REGISTER_NUMBER;
400 fn = hv_cfg_read_func[(size - 1) & 3];
401 HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
405 return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
413 * Write PCI config space
416 static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
417 int offset, int size, u32 val)
419 struct device_node *node = find_Device_Node(bus->number, devfn);
424 return PCIBIOS_DEVICE_NOT_FOUND;
426 return PCIBIOS_BAD_REGISTER_NUMBER;
428 fn = hv_cfg_write_func[(size - 1) & 3];
429 ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
432 return PCIBIOS_DEVICE_NOT_FOUND;
437 static struct pci_ops iSeries_pci_ops = {
438 .read = iSeries_pci_read_config,
439 .write = iSeries_pci_write_config
444 * -> On Failure, print and log information.
445 * Increment Retry Count, if exceeds max, panic partition.
447 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
448 * PCI: Device 23.90 ReadL Retry( 1)
449 * PCI: Device 23.90 ReadL Retry Successful(1)
451 static int CheckReturnCode(char *TextHdr, struct device_node *DevNode,
455 struct pci_dn *pdn = PCI_DN(DevNode);
458 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
459 TextHdr, pdn->busno, pdn->devfn,
462 * Bump the retry and check for retry count exceeded.
463 * If, Exceeded, panic the system.
465 if (((*retry) > Pci_Retry_Max) &&
466 (Pci_Error_Flag > 0)) {
467 mf_display_src(0xB6000103);
469 panic("PCI: Hardware I/O Error, SRC B6000103, "
470 "Automatic Reboot Disabled.\n");
472 return -1; /* Retry Try */
478 * Translate the I/O Address into a device node, bar, and bar offset.
479 * Note: Make sure the passed variable end up on the stack to avoid
480 * the exposure of being device global.
482 static inline struct device_node *xlate_iomm_address(
483 const volatile void __iomem *IoAddress,
484 u64 *dsaptr, u64 *BarOffsetPtr)
486 unsigned long OrigIoAddr;
487 unsigned long BaseIoAddr;
488 unsigned long TableIndex;
489 struct device_node *DevNode;
491 OrigIoAddr = (unsigned long __force)IoAddress;
492 if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
494 BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
495 TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
496 DevNode = iomm_table[TableIndex];
498 if (DevNode != NULL) {
499 int barnum = iobar_table[TableIndex];
500 *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24);
501 *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
503 panic("PCI: Invalid PCI IoAddress detected!\n");
508 * Read MM I/O Instructions for the iSeries
509 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
510 * else, data is returned in big Endian format.
512 * iSeries_Read_Byte = Read Byte ( 8 bit)
513 * iSeries_Read_Word = Read Word (16 bit)
514 * iSeries_Read_Long = Read Long (32 bit)
516 u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
521 struct HvCallPci_LoadReturn ret;
522 struct device_node *DevNode =
523 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
525 if (DevNode == NULL) {
526 static unsigned long last_jiffies;
527 static int num_printed;
529 if ((jiffies - last_jiffies) > 60 * HZ) {
530 last_jiffies = jiffies;
533 if (num_printed++ < 10)
534 printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
538 HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
539 } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0);
541 return (u8)ret.value;
543 EXPORT_SYMBOL(iSeries_Read_Byte);
545 u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
550 struct HvCallPci_LoadReturn ret;
551 struct device_node *DevNode =
552 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
554 if (DevNode == NULL) {
555 static unsigned long last_jiffies;
556 static int num_printed;
558 if ((jiffies - last_jiffies) > 60 * HZ) {
559 last_jiffies = jiffies;
562 if (num_printed++ < 10)
563 printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
567 HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
569 } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0);
571 return swab16((u16)ret.value);
573 EXPORT_SYMBOL(iSeries_Read_Word);
575 u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
580 struct HvCallPci_LoadReturn ret;
581 struct device_node *DevNode =
582 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
584 if (DevNode == NULL) {
585 static unsigned long last_jiffies;
586 static int num_printed;
588 if ((jiffies - last_jiffies) > 60 * HZ) {
589 last_jiffies = jiffies;
592 if (num_printed++ < 10)
593 printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
597 HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
599 } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0);
601 return swab32((u32)ret.value);
603 EXPORT_SYMBOL(iSeries_Read_Long);
606 * Write MM I/O Instructions for the iSeries
608 * iSeries_Write_Byte = Write Byte (8 bit)
609 * iSeries_Write_Word = Write Word(16 bit)
610 * iSeries_Write_Long = Write Long(32 bit)
612 void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
618 struct device_node *DevNode =
619 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
621 if (DevNode == NULL) {
622 static unsigned long last_jiffies;
623 static int num_printed;
625 if ((jiffies - last_jiffies) > 60 * HZ) {
626 last_jiffies = jiffies;
629 if (num_printed++ < 10)
630 printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
634 rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
635 } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0);
637 EXPORT_SYMBOL(iSeries_Write_Byte);
639 void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
645 struct device_node *DevNode =
646 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
648 if (DevNode == NULL) {
649 static unsigned long last_jiffies;
650 static int num_printed;
652 if ((jiffies - last_jiffies) > 60 * HZ) {
653 last_jiffies = jiffies;
656 if (num_printed++ < 10)
657 printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
661 rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
662 } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0);
664 EXPORT_SYMBOL(iSeries_Write_Word);
666 void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
672 struct device_node *DevNode =
673 xlate_iomm_address(IoAddress, &dsa, &BarOffset);
675 if (DevNode == NULL) {
676 static unsigned long last_jiffies;
677 static int num_printed;
679 if ((jiffies - last_jiffies) > 60 * HZ) {
680 last_jiffies = jiffies;
683 if (num_printed++ < 10)
684 printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
688 rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
689 } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0);
691 EXPORT_SYMBOL(iSeries_Write_Long);