powerpc: merge irq.c
[karo-tx-linux.git] / arch / powerpc / platforms / powermac / pic.c
1 /*
2  *  Support for the interrupt controllers found on Power Macintosh,
3  *  currently Apple's "Grand Central" interrupt controller in all
4  *  it's incarnations. OpenPIC support used on newer machines is
5  *  in a separate file
6  *
7  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8  *
9  *  Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
10  *
11  *  This program is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU General Public License
13  *  as published by the Free Software Foundation; either version
14  *  2 of the License, or (at your option) any later version.
15  *
16  */
17
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/signal.h>
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/adb.h>
27 #include <linux/pmu.h>
28 #include <linux/module.h>
29
30 #include <asm/sections.h>
31 #include <asm/io.h>
32 #include <asm/smp.h>
33 #include <asm/prom.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/time.h>
36 #include <asm/pmac_feature.h>
37 #include <asm/mpic.h>
38
39 #include "pmac.h"
40
41 /*
42  * XXX this should be in xmon.h, but putting it there means xmon.h
43  * has to include <linux/interrupt.h> (to get irqreturn_t), which
44  * causes all sorts of problems.  -- paulus
45  */
46 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
47
48 #ifdef CONFIG_PPC32
49 struct pmac_irq_hw {
50         unsigned int    event;
51         unsigned int    enable;
52         unsigned int    ack;
53         unsigned int    level;
54 };
55
56 /* Default addresses */
57 static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
58         (struct pmac_irq_hw *) 0xf3000020,
59         (struct pmac_irq_hw *) 0xf3000010,
60         (struct pmac_irq_hw *) 0xf4000020,
61         (struct pmac_irq_hw *) 0xf4000010,
62 };
63
64 #define GC_LEVEL_MASK           0x3ff00000
65 #define OHARE_LEVEL_MASK        0x1ff00000
66 #define HEATHROW_LEVEL_MASK     0x1ff00000
67
68 static int max_irqs;
69 static int max_real_irqs;
70 static u32 level_mask[4];
71
72 static DEFINE_SPINLOCK(pmac_pic_lock);
73
74 #define GATWICK_IRQ_POOL_SIZE        10
75 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
76
77 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
78 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
79
80 /*
81  * Mark an irq as "lost".  This is only used on the pmac
82  * since it can lose interrupts (see pmac_set_irq_mask).
83  * -- Cort
84  */
85 void
86 __set_lost(unsigned long irq_nr, int nokick)
87 {
88         if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
89                 atomic_inc(&ppc_n_lost_interrupts);
90                 if (!nokick)
91                         set_dec(1);
92         }
93 }
94
95 static void
96 pmac_mask_and_ack_irq(unsigned int irq_nr)
97 {
98         unsigned long bit = 1UL << (irq_nr & 0x1f);
99         int i = irq_nr >> 5;
100         unsigned long flags;
101
102         if ((unsigned)irq_nr >= max_irqs)
103                 return;
104
105         clear_bit(irq_nr, ppc_cached_irq_mask);
106         if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
107                 atomic_dec(&ppc_n_lost_interrupts);
108         spin_lock_irqsave(&pmac_pic_lock, flags);
109         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
110         out_le32(&pmac_irq_hw[i]->ack, bit);
111         do {
112                 /* make sure ack gets to controller before we enable
113                    interrupts */
114                 mb();
115         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
116                 != (ppc_cached_irq_mask[i] & bit));
117         spin_unlock_irqrestore(&pmac_pic_lock, flags);
118 }
119
120 static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
121 {
122         unsigned long bit = 1UL << (irq_nr & 0x1f);
123         int i = irq_nr >> 5;
124         unsigned long flags;
125
126         if ((unsigned)irq_nr >= max_irqs)
127                 return;
128
129         spin_lock_irqsave(&pmac_pic_lock, flags);
130         /* enable unmasked interrupts */
131         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
132
133         do {
134                 /* make sure mask gets to controller before we
135                    return to user */
136                 mb();
137         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
138                 != (ppc_cached_irq_mask[i] & bit));
139
140         /*
141          * Unfortunately, setting the bit in the enable register
142          * when the device interrupt is already on *doesn't* set
143          * the bit in the flag register or request another interrupt.
144          */
145         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
146                 __set_lost((ulong)irq_nr, nokicklost);
147         spin_unlock_irqrestore(&pmac_pic_lock, flags);
148 }
149
150 /* When an irq gets requested for the first client, if it's an
151  * edge interrupt, we clear any previous one on the controller
152  */
153 static unsigned int pmac_startup_irq(unsigned int irq_nr)
154 {
155         unsigned long bit = 1UL << (irq_nr & 0x1f);
156         int i = irq_nr >> 5;
157
158         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
159                 out_le32(&pmac_irq_hw[i]->ack, bit);
160         set_bit(irq_nr, ppc_cached_irq_mask);
161         pmac_set_irq_mask(irq_nr, 0);
162
163         return 0;
164 }
165
166 static void pmac_mask_irq(unsigned int irq_nr)
167 {
168         clear_bit(irq_nr, ppc_cached_irq_mask);
169         pmac_set_irq_mask(irq_nr, 0);
170         mb();
171 }
172
173 static void pmac_unmask_irq(unsigned int irq_nr)
174 {
175         set_bit(irq_nr, ppc_cached_irq_mask);
176         pmac_set_irq_mask(irq_nr, 0);
177 }
178
179 static void pmac_end_irq(unsigned int irq_nr)
180 {
181         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
182             && irq_desc[irq_nr].action) {
183                 set_bit(irq_nr, ppc_cached_irq_mask);
184                 pmac_set_irq_mask(irq_nr, 1);
185         }
186 }
187
188
189 struct hw_interrupt_type pmac_pic = {
190         .typename       = " PMAC-PIC ",
191         .startup        = pmac_startup_irq,
192         .enable         = pmac_unmask_irq,
193         .disable        = pmac_mask_irq,
194         .ack            = pmac_mask_and_ack_irq,
195         .end            = pmac_end_irq,
196 };
197
198 struct hw_interrupt_type gatwick_pic = {
199         .typename       = " GATWICK  ",
200         .startup        = pmac_startup_irq,
201         .enable         = pmac_unmask_irq,
202         .disable        = pmac_mask_irq,
203         .ack            = pmac_mask_and_ack_irq,
204         .end            = pmac_end_irq,
205 };
206
207 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
208 {
209         int irq, bits;
210
211         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
212                 int i = irq >> 5;
213                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
214                 /* We must read level interrupts from the level register */
215                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
216                 bits &= ppc_cached_irq_mask[i];
217                 if (bits == 0)
218                         continue;
219                 irq += __ilog2(bits);
220                 __do_IRQ(irq, regs);
221                 return IRQ_HANDLED;
222         }
223         printk("gatwick irq not from gatwick pic\n");
224         return IRQ_NONE;
225 }
226
227 int
228 pmac_get_irq(struct pt_regs *regs)
229 {
230         int irq;
231         unsigned long bits = 0;
232
233 #ifdef CONFIG_SMP
234         void psurge_smp_message_recv(struct pt_regs *);
235
236         /* IPI's are a hack on the powersurge -- Cort */
237         if ( smp_processor_id() != 0 ) {
238                 psurge_smp_message_recv(regs);
239                 return -2;      /* ignore, already handled */
240         }
241 #endif /* CONFIG_SMP */
242         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
243                 int i = irq >> 5;
244                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
245                 /* We must read level interrupts from the level register */
246                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
247                 bits &= ppc_cached_irq_mask[i];
248                 if (bits == 0)
249                         continue;
250                 irq += __ilog2(bits);
251                 break;
252         }
253
254         return irq;
255 }
256
257 /* This routine will fix some missing interrupt values in the device tree
258  * on the gatwick mac-io controller used by some PowerBooks
259  */
260 static void __init
261 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
262 {
263         struct device_node *node;
264         int count;
265
266         memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
267         node = gw->child;
268         count = 0;
269         while(node)
270         {
271                 /* Fix SCC */
272                 if (strcasecmp(node->name, "escc") == 0)
273                         if (node->child) {
274                                 if (node->child->n_intrs < 3) {
275                                         node->child->intrs = &gatwick_int_pool[count];
276                                         count += 3;
277                                 }
278                                 node->child->n_intrs = 3;
279                                 node->child->intrs[0].line = 15+irq_base;
280                                 node->child->intrs[1].line =  4+irq_base;
281                                 node->child->intrs[2].line =  5+irq_base;
282                                 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
283                                         node->child->intrs[0].line,
284                                         node->child->intrs[1].line,
285                                         node->child->intrs[2].line);
286                         }
287                 /* Fix media-bay & left SWIM */
288                 if (strcasecmp(node->name, "media-bay") == 0) {
289                         struct device_node* ya_node;
290
291                         if (node->n_intrs == 0)
292                                 node->intrs = &gatwick_int_pool[count++];
293                         node->n_intrs = 1;
294                         node->intrs[0].line = 29+irq_base;
295                         printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
296                                         node->intrs[0].line);
297
298                         ya_node = node->child;
299                         while(ya_node)
300                         {
301                                 if (strcasecmp(ya_node->name, "floppy") == 0) {
302                                         if (ya_node->n_intrs < 2) {
303                                                 ya_node->intrs = &gatwick_int_pool[count];
304                                                 count += 2;
305                                         }
306                                         ya_node->n_intrs = 2;
307                                         ya_node->intrs[0].line = 19+irq_base;
308                                         ya_node->intrs[1].line =  1+irq_base;
309                                         printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
310                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
311                                 }
312                                 if (strcasecmp(ya_node->name, "ata4") == 0) {
313                                         if (ya_node->n_intrs < 2) {
314                                                 ya_node->intrs = &gatwick_int_pool[count];
315                                                 count += 2;
316                                         }
317                                         ya_node->n_intrs = 2;
318                                         ya_node->intrs[0].line = 14+irq_base;
319                                         ya_node->intrs[1].line =  3+irq_base;
320                                         printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
321                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
322                                 }
323                                 ya_node = ya_node->sibling;
324                         }
325                 }
326                 node = node->sibling;
327         }
328         if (count > 10) {
329                 printk("WARNING !! Gatwick interrupt pool overflow\n");
330                 printk("  GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
331                 printk("              requested = %d\n", count);
332         }
333 }
334
335 /*
336  * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
337  * card which includes an ohare chip that acts as a second interrupt
338  * controller.  If we find this second ohare, set it up and fix the
339  * interrupt value in the device tree for the ethernet chip.
340  */
341 static int __init enable_second_ohare(void)
342 {
343         unsigned char bus, devfn;
344         unsigned short cmd;
345         unsigned long addr;
346         struct device_node *irqctrler = find_devices("pci106b,7");
347         struct device_node *ether;
348
349         if (irqctrler == NULL || irqctrler->n_addrs <= 0)
350                 return -1;
351         addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
352         pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
353         max_irqs = 64;
354         if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
355                 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
356                 if (!hose)
357                     printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
358                 else {
359                     early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
360                     cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
361                     cmd &= ~PCI_COMMAND_IO;
362                     early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
363                 }
364         }
365
366         /* Fix interrupt for the modem/ethernet combo controller. The number
367            in the device tree (27) is bogus (correct for the ethernet-only
368            board but not the combo ethernet/modem board).
369            The real interrupt is 28 on the second controller -> 28+32 = 60.
370         */
371         ether = find_devices("pci1011,14");
372         if (ether && ether->n_intrs > 0) {
373                 ether->intrs[0].line = 60;
374                 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
375                        ether->intrs[0].line);
376         }
377
378         /* Return the interrupt number of the cascade */
379         return irqctrler->intrs[0].line;
380 }
381
382 #ifdef CONFIG_XMON
383 static struct irqaction xmon_action = {
384         .handler        = xmon_irq,
385         .flags          = 0,
386         .mask           = CPU_MASK_NONE,
387         .name           = "NMI - XMON"
388 };
389 #endif
390
391 static struct irqaction gatwick_cascade_action = {
392         .handler        = gatwick_action,
393         .flags          = SA_INTERRUPT,
394         .mask           = CPU_MASK_NONE,
395         .name           = "cascade",
396 };
397 #endif /* CONFIG_PPC32 */
398
399 static int pmac_u3_cascade(struct pt_regs *regs, void *data)
400 {
401         return mpic_get_one_irq((struct mpic *)data, regs);
402 }
403
404 void __init pmac_pic_init(void)
405 {
406         struct device_node *irqctrler  = NULL;
407         struct device_node *irqctrler2 = NULL;
408         struct device_node *np;
409 #ifdef CONFIG_PPC32
410         int i;
411         unsigned long addr;
412         int irq_cascade = -1;
413 #endif
414         struct mpic *mpic1, *mpic2;
415
416         /* We first try to detect Apple's new Core99 chipset, since mac-io
417          * is quite different on those machines and contains an IBM MPIC2.
418          */
419         np = find_type_devices("open-pic");
420         while (np) {
421                 if (np->parent && !strcmp(np->parent->name, "u3"))
422                         irqctrler2 = np;
423                 else
424                         irqctrler = np;
425                 np = np->next;
426         }
427         if (irqctrler != NULL && irqctrler->n_addrs > 0) {
428                 unsigned char senses[128];
429
430                 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
431                        (unsigned int)irqctrler->addrs[0].address);
432                 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
433
434                 prom_get_irq_senses(senses, 0, 128);
435                 mpic1 = mpic_alloc(irqctrler->addrs[0].address,
436                                    MPIC_PRIMARY | MPIC_WANTS_RESET,
437                                    0, 0, 128, 252, senses, 128, " OpenPIC  ");
438                 BUG_ON(mpic1 == NULL);
439                 mpic_init(mpic1);               
440
441                 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
442                     irqctrler2->n_addrs > 0) {
443                         printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
444                                (u32)irqctrler2->addrs[0].address,
445                                irqctrler2->intrs[0].line);
446
447                         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
448                         prom_get_irq_senses(senses, 128, 128 + 124);
449
450                         /* We don't need to set MPIC_BROKEN_U3 here since we don't have
451                          * hypertransport interrupts routed to it
452                          */
453                         mpic2 = mpic_alloc(irqctrler2->addrs[0].address,
454                                            MPIC_BIG_ENDIAN | MPIC_WANTS_RESET,
455                                            0, 128, 124, 0, senses, 124,
456                                            " U3-MPIC  ");
457                         BUG_ON(mpic2 == NULL);
458                         mpic_init(mpic2);
459                         mpic_setup_cascade(irqctrler2->intrs[0].line,
460                                            pmac_u3_cascade, mpic2);
461                 }
462 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
463                 {
464                         struct device_node* pswitch;
465                         int nmi_irq;
466
467                         pswitch = find_devices("programmer-switch");
468                         if (pswitch && pswitch->n_intrs) {
469                                 nmi_irq = pswitch->intrs[0].line;
470                                 mpic_irq_set_priority(nmi_irq, 9);
471                                 setup_irq(nmi_irq, &xmon_action);
472                         }
473                 }
474 #endif  /* CONFIG_XMON */
475                 return;
476         }
477         irqctrler = NULL;
478
479 #ifdef CONFIG_PPC32
480         /* Get the level/edge settings, assume if it's not
481          * a Grand Central nor an OHare, then it's an Heathrow
482          * (or Paddington).
483          */
484         ppc_md.get_irq = pmac_get_irq;
485         if (find_devices("gc"))
486                 level_mask[0] = GC_LEVEL_MASK;
487         else if (find_devices("ohare")) {
488                 level_mask[0] = OHARE_LEVEL_MASK;
489                 /* We might have a second cascaded ohare */
490                 level_mask[1] = OHARE_LEVEL_MASK;
491         } else {
492                 level_mask[0] = HEATHROW_LEVEL_MASK;
493                 level_mask[1] = 0;
494                 /* We might have a second cascaded heathrow */
495                 level_mask[2] = HEATHROW_LEVEL_MASK;
496                 level_mask[3] = 0;
497         }
498
499         /*
500          * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
501          * 1998 G3 Series PowerBooks have 128,
502          * other powermacs have 32.
503          * The combo ethernet/modem card for the Powerstar powerbooks
504          * (2400/3400/3500, ohare based) has a second ohare chip
505          * effectively making a total of 64.
506          */
507         max_irqs = max_real_irqs = 32;
508         irqctrler = find_devices("mac-io");
509         if (irqctrler)
510         {
511                 max_real_irqs = 64;
512                 if (irqctrler->next)
513                         max_irqs = 128;
514                 else
515                         max_irqs = 64;
516         }
517         for ( i = 0; i < max_real_irqs ; i++ )
518                 irq_desc[i].handler = &pmac_pic;
519
520         /* get addresses of first controller */
521         if (irqctrler) {
522                 if  (irqctrler->n_addrs > 0) {
523                         addr = (unsigned long)
524                                 ioremap(irqctrler->addrs[0].address, 0x40);
525                         for (i = 0; i < 2; ++i)
526                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
527                                         (addr + (2 - i) * 0x10);
528                 }
529
530                 /* get addresses of second controller */
531                 irqctrler = irqctrler->next;
532                 if (irqctrler && irqctrler->n_addrs > 0) {
533                         addr = (unsigned long)
534                                 ioremap(irqctrler->addrs[0].address, 0x40);
535                         for (i = 2; i < 4; ++i)
536                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
537                                         (addr + (4 - i) * 0x10);
538                         irq_cascade = irqctrler->intrs[0].line;
539                         if (device_is_compatible(irqctrler, "gatwick"))
540                                 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
541                 }
542         } else {
543                 /* older powermacs have a GC (grand central) or ohare at
544                    f3000000, with interrupt control registers at f3000020. */
545                 addr = (unsigned long) ioremap(0xf3000000, 0x40);
546                 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
547         }
548
549         /* PowerBooks 3400 and 3500 can have a second controller in a second
550            ohare chip, on the combo ethernet/modem card */
551         if (machine_is_compatible("AAPL,3400/2400")
552              || machine_is_compatible("AAPL,3500"))
553                 irq_cascade = enable_second_ohare();
554
555         /* disable all interrupts in all controllers */
556         for (i = 0; i * 32 < max_irqs; ++i)
557                 out_le32(&pmac_irq_hw[i]->enable, 0);
558         /* mark level interrupts */
559         for (i = 0; i < max_irqs; i++)
560                 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
561                         irq_desc[i].status = IRQ_LEVEL;
562
563         /* get interrupt line of secondary interrupt controller */
564         if (irq_cascade >= 0) {
565                 printk(KERN_INFO "irq: secondary controller on irq %d\n",
566                         (int)irq_cascade);
567                 for ( i = max_real_irqs ; i < max_irqs ; i++ )
568                         irq_desc[i].handler = &gatwick_pic;
569                 setup_irq(irq_cascade, &gatwick_cascade_action);
570         }
571         printk("System has %d possible interrupts\n", max_irqs);
572         if (max_irqs != max_real_irqs)
573                 printk(KERN_DEBUG "%d interrupts on main controller\n",
574                         max_real_irqs);
575
576 #ifdef CONFIG_XMON
577         setup_irq(20, &xmon_action);
578 #endif  /* CONFIG_XMON */
579 #endif  /* CONFIG_PPC32 */
580 }
581
582 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
583 /*
584  * These procedures are used in implementing sleep on the powerbooks.
585  * sleep_save_intrs() saves the states of all interrupt enables
586  * and disables all interrupts except for the nominated one.
587  * sleep_restore_intrs() restores the states of all interrupt enables.
588  */
589 unsigned long sleep_save_mask[2];
590
591 /* This used to be passed by the PMU driver but that link got
592  * broken with the new driver model. We use this tweak for now...
593  */
594 static int pmacpic_find_viaint(void)
595 {
596         int viaint = -1;
597
598 #ifdef CONFIG_ADB_PMU
599         struct device_node *np;
600
601         if (pmu_get_model() != PMU_OHARE_BASED)
602                 goto not_found;
603         np = of_find_node_by_name(NULL, "via-pmu");
604         if (np == NULL)
605                 goto not_found;
606         viaint = np->intrs[0].line;
607 #endif /* CONFIG_ADB_PMU */
608
609 not_found:
610         return viaint;
611 }
612
613 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
614 {
615         int viaint = pmacpic_find_viaint();
616
617         sleep_save_mask[0] = ppc_cached_irq_mask[0];
618         sleep_save_mask[1] = ppc_cached_irq_mask[1];
619         ppc_cached_irq_mask[0] = 0;
620         ppc_cached_irq_mask[1] = 0;
621         if (viaint > 0)
622                 set_bit(viaint, ppc_cached_irq_mask);
623         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
624         if (max_real_irqs > 32)
625                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
626         (void)in_le32(&pmac_irq_hw[0]->event);
627         /* make sure mask gets to controller before we return to caller */
628         mb();
629         (void)in_le32(&pmac_irq_hw[0]->enable);
630
631         return 0;
632 }
633
634 static int pmacpic_resume(struct sys_device *sysdev)
635 {
636         int i;
637
638         out_le32(&pmac_irq_hw[0]->enable, 0);
639         if (max_real_irqs > 32)
640                 out_le32(&pmac_irq_hw[1]->enable, 0);
641         mb();
642         for (i = 0; i < max_real_irqs; ++i)
643                 if (test_bit(i, sleep_save_mask))
644                         pmac_unmask_irq(i);
645
646         return 0;
647 }
648
649 #endif /* CONFIG_PM && CONFIG_PPC32 */
650
651 static struct sysdev_class pmacpic_sysclass = {
652         set_kset_name("pmac_pic"),
653 };
654
655 static struct sys_device device_pmacpic = {
656         .id             = 0,
657         .cls            = &pmacpic_sysclass,
658 };
659
660 static struct sysdev_driver driver_pmacpic = {
661 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
662         .suspend        = &pmacpic_suspend,
663         .resume         = &pmacpic_resume,
664 #endif /* CONFIG_PM && CONFIG_PPC32 */
665 };
666
667 static int __init init_pmacpic_sysfs(void)
668 {
669 #ifdef CONFIG_PPC32
670         if (max_irqs == 0)
671                 return -ENODEV;
672 #endif
673         printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
674         sysdev_class_register(&pmacpic_sysclass);
675         sysdev_register(&device_pmacpic);
676         sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
677         return 0;
678 }
679
680 subsys_initcall(init_pmacpic_sysfs);
681