arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27 #include <linux/device.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/stacktrace.h>
  31 #include <asm/nmi.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/tlbflush.h>
  36 #include <asm/timer.h>
  37 #include <asm/desc.h>
  38 #include <asm/ldt.h>
  39
  40 #include "perf_event.h"
  41
  42 struct x86_pmu x86_pmu __read_mostly;
  43
  44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  45         .enabled = 1,
  46 };
  47
  48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
  49
  50 u64 __read_mostly hw_cache_event_ids
  51                                 [PERF_COUNT_HW_CACHE_MAX]
  52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  54 u64 __read_mostly hw_cache_extra_regs
  55                                 [PERF_COUNT_HW_CACHE_MAX]
  56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  58
  59 /*
  60  * Propagate event elapsed time into the generic event.
  61  * Can only be executed on the CPU where the event is active.
  62  * Returns the delta events processed.
  63  */
  64 u64 x86_perf_event_update(struct perf_event *event)
  65 {
  66         struct hw_perf_event *hwc = &event->hw;
  67         int shift = 64 - x86_pmu.cntval_bits;
  68         u64 prev_raw_count, new_raw_count;
  69         int idx = hwc->idx;
  70         s64 delta;
  71
  72         if (idx == INTEL_PMC_IDX_FIXED_BTS)
  73                 return 0;
  74
  75         /*
  76          * Careful: an NMI might modify the previous event value.
  77          *
  78          * Our tactic to handle this is to first atomically read and
  79          * exchange a new raw count - then add that new-prev delta
  80          * count to the generic event atomically:
  81          */
  82 again:
  83         prev_raw_count = local64_read(&hwc->prev_count);
  84         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  85
  86         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  87                                         new_raw_count) != prev_raw_count)
  88                 goto again;
  89
  90         /*
  91          * Now we have the new raw value and have updated the prev
  92          * timestamp already. We can now calculate the elapsed delta
  93          * (event-)time and add that to the generic event.
  94          *
  95          * Careful, not all hw sign-extends above the physical width
  96          * of the count.
  97          */
  98         delta = (new_raw_count << shift) - (prev_raw_count << shift);
  99         delta >>= shift;
 100
 101         local64_add(delta, &event->count);
 102         local64_sub(delta, &hwc->period_left);
 103
 104         return new_raw_count;
 105 }
 106
 107 /*
 108  * Find and validate any extra registers to set up.
 109  */
 110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 111 {
 112         struct hw_perf_event_extra *reg;
 113         struct extra_reg *er;
 114
 115         reg = &event->hw.extra_reg;
 116
 117         if (!x86_pmu.extra_regs)
 118                 return 0;
 119
 120         for (er = x86_pmu.extra_regs; er->msr; er++) {
 121                 if (er->event != (config & er->config_mask))
 122                         continue;
 123                 if (event->attr.config1 & ~er->valid_mask)
 124                         return -EINVAL;
 125                 /* Check if the extra msrs can be safely accessed*/
 126                 if (!er->extra_msr_access)
 127                         return -ENXIO;
 128
 129                 reg->idx = er->idx;
 130                 reg->config = event->attr.config1;
 131                 reg->reg = er->msr;
 132                 break;
 133         }
 134         return 0;
 135 }
 136
 137 static atomic_t active_events;
 138 static atomic_t pmc_refcount;
 139 static DEFINE_MUTEX(pmc_reserve_mutex);
 140
 141 #ifdef CONFIG_X86_LOCAL_APIC
 142
 143 static bool reserve_pmc_hardware(void)
 144 {
 145         int i;
 146
 147         for (i = 0; i < x86_pmu.num_counters; i++) {
 148                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 149                         goto perfctr_fail;
 150         }
 151
 152         for (i = 0; i < x86_pmu.num_counters; i++) {
 153                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 154                         goto eventsel_fail;
 155         }
 156
 157         return true;
 158
 159 eventsel_fail:
 160         for (i--; i >= 0; i--)
 161                 release_evntsel_nmi(x86_pmu_config_addr(i));
 162
 163         i = x86_pmu.num_counters;
 164
 165 perfctr_fail:
 166         for (i--; i >= 0; i--)
 167                 release_perfctr_nmi(x86_pmu_event_addr(i));
 168
 169         return false;
 170 }
 171
 172 static void release_pmc_hardware(void)
 173 {
 174         int i;
 175
 176         for (i = 0; i < x86_pmu.num_counters; i++) {
 177                 release_perfctr_nmi(x86_pmu_event_addr(i));
 178                 release_evntsel_nmi(x86_pmu_config_addr(i));
 179         }
 180 }
 181
 182 #else
 183
 184 static bool reserve_pmc_hardware(void) { return true; }
 185 static void release_pmc_hardware(void) {}
 186
 187 #endif
 188
 189 static bool check_hw_exists(void)
 190 {
 191         u64 val, val_fail, val_new= ~0;
 192         int i, reg, reg_fail, ret = 0;
 193         int bios_fail = 0;
 194         int reg_safe = -1;
 195
 196         /*
 197          * Check to see if the BIOS enabled any of the counters, if so
 198          * complain and bail.
 199          */
 200         for (i = 0; i < x86_pmu.num_counters; i++) {
 201                 reg = x86_pmu_config_addr(i);
 202                 ret = rdmsrl_safe(reg, &val);
 203                 if (ret)
 204                         goto msr_fail;
 205                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
 206                         bios_fail = 1;
 207                         val_fail = val;
 208                         reg_fail = reg;
 209                 } else {
 210                         reg_safe = i;
 211                 }
 212         }
 213
 214         if (x86_pmu.num_counters_fixed) {
 215                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 216                 ret = rdmsrl_safe(reg, &val);
 217                 if (ret)
 218                         goto msr_fail;
 219                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 220                         if (val & (0x03 << i*4)) {
 221                                 bios_fail = 1;
 222                                 val_fail = val;
 223                                 reg_fail = reg;
 224                         }
 225                 }
 226         }
 227
 228         /*
 229          * If all the counters are enabled, the below test will always
 230          * fail.  The tools will also become useless in this scenario.
 231          * Just fail and disable the hardware counters.
 232          */
 233
 234         if (reg_safe == -1) {
 235                 reg = reg_safe;
 236                 goto msr_fail;
 237         }
 238
 239         /*
 240          * Read the current value, change it and read it back to see if it
 241          * matches, this is needed to detect certain hardware emulators
 242          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
 243          */
 244         reg = x86_pmu_event_addr(reg_safe);
 245         if (rdmsrl_safe(reg, &val))
 246                 goto msr_fail;
 247         val ^= 0xffffUL;
 248         ret = wrmsrl_safe(reg, val);
 249         ret |= rdmsrl_safe(reg, &val_new);
 250         if (ret || val != val_new)
 251                 goto msr_fail;
 252
 253         /*
 254          * We still allow the PMU driver to operate:
 255          */
 256         if (bios_fail) {
 257                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 258                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
 259         }
 260
 261         return true;
 262
 263 msr_fail:
 264         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 265         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
 266                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
 267                 reg, val_new);
 268
 269         return false;
 270 }
 271
 272 static void hw_perf_event_destroy(struct perf_event *event)
 273 {
 274         x86_release_hardware();
 275         atomic_dec(&active_events);
 276 }
 277
 278 void hw_perf_lbr_event_destroy(struct perf_event *event)
 279 {
 280         hw_perf_event_destroy(event);
 281
 282         /* undo the lbr/bts event accounting */
 283         x86_del_exclusive(x86_lbr_exclusive_lbr);
 284 }
 285
 286 static inline int x86_pmu_initialized(void)
 287 {
 288         return x86_pmu.handle_irq != NULL;
 289 }
 290
 291 static inline int
 292 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 293 {
 294         struct perf_event_attr *attr = &event->attr;
 295         unsigned int cache_type, cache_op, cache_result;
 296         u64 config, val;
 297
 298         config = attr->config;
 299
 300         cache_type = (config >>  0) & 0xff;
 301         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 302                 return -EINVAL;
 303
 304         cache_op = (config >>  8) & 0xff;
 305         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 306                 return -EINVAL;
 307
 308         cache_result = (config >> 16) & 0xff;
 309         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 310                 return -EINVAL;
 311
 312         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 313
 314         if (val == 0)
 315                 return -ENOENT;
 316
 317         if (val == -1)
 318                 return -EINVAL;
 319
 320         hwc->config |= val;
 321         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 322         return x86_pmu_extra_regs(val, event);
 323 }
 324
 325 int x86_reserve_hardware(void)
 326 {
 327         int err = 0;
 328
 329         if (!atomic_inc_not_zero(&pmc_refcount)) {
 330                 mutex_lock(&pmc_reserve_mutex);
 331                 if (atomic_read(&pmc_refcount) == 0) {
 332                         if (!reserve_pmc_hardware())
 333                                 err = -EBUSY;
 334                         else
 335                                 reserve_ds_buffers();
 336                 }
 337                 if (!err)
 338                         atomic_inc(&pmc_refcount);
 339                 mutex_unlock(&pmc_reserve_mutex);
 340         }
 341
 342         return err;
 343 }
 344
 345 void x86_release_hardware(void)
 346 {
 347         if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
 348                 release_pmc_hardware();
 349                 release_ds_buffers();
 350                 mutex_unlock(&pmc_reserve_mutex);
 351         }
 352 }
 353
 354 /*
 355  * Check if we can create event of a certain type (that no conflicting events
 356  * are present).
 357  */
 358 int x86_add_exclusive(unsigned int what)
 359 {
 360         int i;
 361
 362         if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
 363                 mutex_lock(&pmc_reserve_mutex);
 364                 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
 365                         if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
 366                                 goto fail_unlock;
 367                 }
 368                 atomic_inc(&x86_pmu.lbr_exclusive[what]);
 369                 mutex_unlock(&pmc_reserve_mutex);
 370         }
 371
 372         atomic_inc(&active_events);
 373         return 0;
 374
 375 fail_unlock:
 376         mutex_unlock(&pmc_reserve_mutex);
 377         return -EBUSY;
 378 }
 379
 380 void x86_del_exclusive(unsigned int what)
 381 {
 382         atomic_dec(&x86_pmu.lbr_exclusive[what]);
 383         atomic_dec(&active_events);
 384 }
 385
 386 int x86_setup_perfctr(struct perf_event *event)
 387 {
 388         struct perf_event_attr *attr = &event->attr;
 389         struct hw_perf_event *hwc = &event->hw;
 390         u64 config;
 391
 392         if (!is_sampling_event(event)) {
 393                 hwc->sample_period = x86_pmu.max_period;
 394                 hwc->last_period = hwc->sample_period;
 395                 local64_set(&hwc->period_left, hwc->sample_period);
 396         }
 397
 398         if (attr->type == PERF_TYPE_RAW)
 399                 return x86_pmu_extra_regs(event->attr.config, event);
 400
 401         if (attr->type == PERF_TYPE_HW_CACHE)
 402                 return set_ext_hw_attr(hwc, event);
 403
 404         if (attr->config >= x86_pmu.max_events)
 405                 return -EINVAL;
 406
 407         /*
 408          * The generic map:
 409          */
 410         config = x86_pmu.event_map(attr->config);
 411
 412         if (config == 0)
 413                 return -ENOENT;
 414
 415         if (config == -1LL)
 416                 return -EINVAL;
 417
 418         /*
 419          * Branch tracing:
 420          */
 421         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 422             !attr->freq && hwc->sample_period == 1) {
 423                 /* BTS is not supported by this architecture. */
 424                 if (!x86_pmu.bts_active)
 425                         return -EOPNOTSUPP;
 426
 427                 /* BTS is currently only allowed for user-mode. */
 428                 if (!attr->exclude_kernel)
 429                         return -EOPNOTSUPP;
 430
 431                 /* disallow bts if conflicting events are present */
 432                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
 433                         return -EBUSY;
 434
 435                 event->destroy = hw_perf_lbr_event_destroy;
 436         }
 437
 438         hwc->config |= config;
 439
 440         return 0;
 441 }
 442
 443 /*
 444  * check that branch_sample_type is compatible with
 445  * settings needed for precise_ip > 1 which implies
 446  * using the LBR to capture ALL taken branches at the
 447  * priv levels of the measurement
 448  */
 449 static inline int precise_br_compat(struct perf_event *event)
 450 {
 451         u64 m = event->attr.branch_sample_type;
 452         u64 b = 0;
 453
 454         /* must capture all branches */
 455         if (!(m & PERF_SAMPLE_BRANCH_ANY))
 456                 return 0;
 457
 458         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
 459
 460         if (!event->attr.exclude_user)
 461                 b |= PERF_SAMPLE_BRANCH_USER;
 462
 463         if (!event->attr.exclude_kernel)
 464                 b |= PERF_SAMPLE_BRANCH_KERNEL;
 465
 466         /*
 467          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
 468          */
 469
 470         return m == b;
 471 }
 472
 473 int x86_pmu_hw_config(struct perf_event *event)
 474 {
 475         if (event->attr.precise_ip) {
 476                 int precise = 0;
 477
 478                 /* Support for constant skid */
 479                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
 480                         precise++;
 481
 482                         /* Support for IP fixup */
 483                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
 484                                 precise++;
 485                 }
 486
 487                 if (event->attr.precise_ip > precise)
 488                         return -EOPNOTSUPP;
 489         }
 490         /*
 491          * check that PEBS LBR correction does not conflict with
 492          * whatever the user is asking with attr->branch_sample_type
 493          */
 494         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
 495                 u64 *br_type = &event->attr.branch_sample_type;
 496
 497                 if (has_branch_stack(event)) {
 498                         if (!precise_br_compat(event))
 499                                 return -EOPNOTSUPP;
 500
 501                         /* branch_sample_type is compatible */
 502
 503                 } else {
 504                         /*
 505                          * user did not specify  branch_sample_type
 506                          *
 507                          * For PEBS fixups, we capture all
 508                          * the branches at the priv level of the
 509                          * event.
 510                          */
 511                         *br_type = PERF_SAMPLE_BRANCH_ANY;
 512
 513                         if (!event->attr.exclude_user)
 514                                 *br_type |= PERF_SAMPLE_BRANCH_USER;
 515
 516                         if (!event->attr.exclude_kernel)
 517                                 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
 518                 }
 519         }
 520
 521         if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
 522                 event->attach_state |= PERF_ATTACH_TASK_DATA;
 523
 524         /*
 525          * Generate PMC IRQs:
 526          * (keep 'enabled' bit clear for now)
 527          */
 528         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 529
 530         /*
 531          * Count user and OS events unless requested not to
 532          */
 533         if (!event->attr.exclude_user)
 534                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 535         if (!event->attr.exclude_kernel)
 536                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 537
 538         if (event->attr.type == PERF_TYPE_RAW)
 539                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 540
 541         if (event->attr.sample_period && x86_pmu.limit_period) {
 542                 if (x86_pmu.limit_period(event, event->attr.sample_period) >
 543                                 event->attr.sample_period)
 544                         return -EINVAL;
 545         }
 546
 547         return x86_setup_perfctr(event);
 548 }
 549
 550 /*
 551  * Setup the hardware configuration for a given attr_type
 552  */
 553 static int __x86_pmu_event_init(struct perf_event *event)
 554 {
 555         int err;
 556
 557         if (!x86_pmu_initialized())
 558                 return -ENODEV;
 559
 560         err = x86_reserve_hardware();
 561         if (err)
 562                 return err;
 563
 564         atomic_inc(&active_events);
 565         event->destroy = hw_perf_event_destroy;
 566
 567         event->hw.idx = -1;
 568         event->hw.last_cpu = -1;
 569         event->hw.last_tag = ~0ULL;
 570
 571         /* mark unused */
 572         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 573         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 574
 575         return x86_pmu.hw_config(event);
 576 }
 577
 578 void x86_pmu_disable_all(void)
 579 {
 580         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 581         int idx;
 582
 583         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 584                 u64 val;
 585
 586                 if (!test_bit(idx, cpuc->active_mask))
 587                         continue;
 588                 rdmsrl(x86_pmu_config_addr(idx), val);
 589                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 590                         continue;
 591                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 592                 wrmsrl(x86_pmu_config_addr(idx), val);
 593         }
 594 }
 595
 596 static void x86_pmu_disable(struct pmu *pmu)
 597 {
 598         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 599
 600         if (!x86_pmu_initialized())
 601                 return;
 602
 603         if (!cpuc->enabled)
 604                 return;
 605
 606         cpuc->n_added = 0;
 607         cpuc->enabled = 0;
 608         barrier();
 609
 610         x86_pmu.disable_all();
 611 }
 612
 613 void x86_pmu_enable_all(int added)
 614 {
 615         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 616         int idx;
 617
 618         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 619                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 620
 621                 if (!test_bit(idx, cpuc->active_mask))
 622                         continue;
 623
 624                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 625         }
 626 }
 627
 628 static struct pmu pmu;
 629
 630 static inline int is_x86_event(struct perf_event *event)
 631 {
 632         return event->pmu == &pmu;
 633 }
 634
 635 /*
 636  * Event scheduler state:
 637  *
 638  * Assign events iterating over all events and counters, beginning
 639  * with events with least weights first. Keep the current iterator
 640  * state in struct sched_state.
 641  */
 642 struct sched_state {
 643         int     weight;
 644         int     event;          /* event index */
 645         int     counter;        /* counter index */
 646         int     unassigned;     /* number of events to be assigned left */
 647         int     nr_gp;          /* number of GP counters used */
 648         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 649 };
 650
 651 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
 652 #define SCHED_STATES_MAX        2
 653
 654 struct perf_sched {
 655         int                     max_weight;
 656         int                     max_events;
 657         int                     max_gp;
 658         int                     saved_states;
 659         struct event_constraint **constraints;
 660         struct sched_state      state;
 661         struct sched_state      saved[SCHED_STATES_MAX];
 662 };
 663
 664 /*
 665  * Initialize interator that runs through all events and counters.
 666  */
 667 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
 668                             int num, int wmin, int wmax, int gpmax)
 669 {
 670         int idx;
 671
 672         memset(sched, 0, sizeof(*sched));
 673         sched->max_events       = num;
 674         sched->max_weight       = wmax;
 675         sched->max_gp           = gpmax;
 676         sched->constraints      = constraints;
 677
 678         for (idx = 0; idx < num; idx++) {
 679                 if (constraints[idx]->weight == wmin)
 680                         break;
 681         }
 682
 683         sched->state.event      = idx;          /* start with min weight */
 684         sched->state.weight     = wmin;
 685         sched->state.unassigned = num;
 686 }
 687
 688 static void perf_sched_save_state(struct perf_sched *sched)
 689 {
 690         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
 691                 return;
 692
 693         sched->saved[sched->saved_states] = sched->state;
 694         sched->saved_states++;
 695 }
 696
 697 static bool perf_sched_restore_state(struct perf_sched *sched)
 698 {
 699         if (!sched->saved_states)
 700                 return false;
 701
 702         sched->saved_states--;
 703         sched->state = sched->saved[sched->saved_states];
 704
 705         /* continue with next counter: */
 706         clear_bit(sched->state.counter++, sched->state.used);
 707
 708         return true;
 709 }
 710
 711 /*
 712  * Select a counter for the current event to schedule. Return true on
 713  * success.
 714  */
 715 static bool __perf_sched_find_counter(struct perf_sched *sched)
 716 {
 717         struct event_constraint *c;
 718         int idx;
 719
 720         if (!sched->state.unassigned)
 721                 return false;
 722
 723         if (sched->state.event >= sched->max_events)
 724                 return false;
 725
 726         c = sched->constraints[sched->state.event];
 727         /* Prefer fixed purpose counters */
 728         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
 729                 idx = INTEL_PMC_IDX_FIXED;
 730                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
 731                         if (!__test_and_set_bit(idx, sched->state.used))
 732                                 goto done;
 733                 }
 734         }
 735
 736         /* Grab the first unused counter starting with idx */
 737         idx = sched->state.counter;
 738         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
 739                 if (!__test_and_set_bit(idx, sched->state.used)) {
 740                         if (sched->state.nr_gp++ >= sched->max_gp)
 741                                 return false;
 742
 743                         goto done;
 744                 }
 745         }
 746
 747         return false;
 748
 749 done:
 750         sched->state.counter = idx;
 751
 752         if (c->overlap)
 753                 perf_sched_save_state(sched);
 754
 755         return true;
 756 }
 757
 758 static bool perf_sched_find_counter(struct perf_sched *sched)
 759 {
 760         while (!__perf_sched_find_counter(sched)) {
 761                 if (!perf_sched_restore_state(sched))
 762                         return false;
 763         }
 764
 765         return true;
 766 }
 767
 768 /*
 769  * Go through all unassigned events and find the next one to schedule.
 770  * Take events with the least weight first. Return true on success.
 771  */
 772 static bool perf_sched_next_event(struct perf_sched *sched)
 773 {
 774         struct event_constraint *c;
 775
 776         if (!sched->state.unassigned || !--sched->state.unassigned)
 777                 return false;
 778
 779         do {
 780                 /* next event */
 781                 sched->state.event++;
 782                 if (sched->state.event >= sched->max_events) {
 783                         /* next weight */
 784                         sched->state.event = 0;
 785                         sched->state.weight++;
 786                         if (sched->state.weight > sched->max_weight)
 787                                 return false;
 788                 }
 789                 c = sched->constraints[sched->state.event];
 790         } while (c->weight != sched->state.weight);
 791
 792         sched->state.counter = 0;       /* start with first counter */
 793
 794         return true;
 795 }
 796
 797 /*
 798  * Assign a counter for each event.
 799  */
 800 int perf_assign_events(struct event_constraint **constraints, int n,
 801                         int wmin, int wmax, int gpmax, int *assign)
 802 {
 803         struct perf_sched sched;
 804
 805         perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
 806
 807         do {
 808                 if (!perf_sched_find_counter(&sched))
 809                         break;  /* failed */
 810                 if (assign)
 811                         assign[sched.state.event] = sched.state.counter;
 812         } while (perf_sched_next_event(&sched));
 813
 814         return sched.state.unassigned;
 815 }
 816 EXPORT_SYMBOL_GPL(perf_assign_events);
 817
 818 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 819 {
 820         struct event_constraint *c;
 821         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 822         struct perf_event *e;
 823         int i, wmin, wmax, unsched = 0;
 824         struct hw_perf_event *hwc;
 825
 826         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 827
 828         if (x86_pmu.start_scheduling)
 829                 x86_pmu.start_scheduling(cpuc);
 830
 831         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 832                 cpuc->event_constraint[i] = NULL;
 833                 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
 834                 cpuc->event_constraint[i] = c;
 835
 836                 wmin = min(wmin, c->weight);
 837                 wmax = max(wmax, c->weight);
 838         }
 839
 840         /*
 841          * fastpath, try to reuse previous register
 842          */
 843         for (i = 0; i < n; i++) {
 844                 hwc = &cpuc->event_list[i]->hw;
 845                 c = cpuc->event_constraint[i];
 846
 847                 /* never assigned */
 848                 if (hwc->idx == -1)
 849                         break;
 850
 851                 /* constraint still honored */
 852                 if (!test_bit(hwc->idx, c->idxmsk))
 853                         break;
 854
 855                 /* not already used */
 856                 if (test_bit(hwc->idx, used_mask))
 857                         break;
 858
 859                 __set_bit(hwc->idx, used_mask);
 860                 if (assign)
 861                         assign[i] = hwc->idx;
 862         }
 863
 864         /* slow path */
 865         if (i != n) {
 866                 int gpmax = x86_pmu.num_counters;
 867
 868                 /*
 869                  * Do not allow scheduling of more than half the available
 870                  * generic counters.
 871                  *
 872                  * This helps avoid counter starvation of sibling thread by
 873                  * ensuring at most half the counters cannot be in exclusive
 874                  * mode. There is no designated counters for the limits. Any
 875                  * N/2 counters can be used. This helps with events with
 876                  * specific counter constraints.
 877                  */
 878                 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
 879                     READ_ONCE(cpuc->excl_cntrs->exclusive_present))
 880                         gpmax /= 2;
 881
 882                 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
 883                                              wmax, gpmax, assign);
 884         }
 885
 886         /*
 887          * In case of success (unsched = 0), mark events as committed,
 888          * so we do not put_constraint() in case new events are added
 889          * and fail to be scheduled
 890          *
 891          * We invoke the lower level commit callback to lock the resource
 892          *
 893          * We do not need to do all of this in case we are called to
 894          * validate an event group (assign == NULL)
 895          */
 896         if (!unsched && assign) {
 897                 for (i = 0; i < n; i++) {
 898                         e = cpuc->event_list[i];
 899                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
 900                         if (x86_pmu.commit_scheduling)
 901                                 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
 902                 }
 903         } else {
 904                 for (i = 0; i < n; i++) {
 905                         e = cpuc->event_list[i];
 906                         /*
 907                          * do not put_constraint() on comitted events,
 908                          * because they are good to go
 909                          */
 910                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
 911                                 continue;
 912
 913                         /*
 914                          * release events that failed scheduling
 915                          */
 916                         if (x86_pmu.put_event_constraints)
 917                                 x86_pmu.put_event_constraints(cpuc, e);
 918                 }
 919         }
 920
 921         if (x86_pmu.stop_scheduling)
 922                 x86_pmu.stop_scheduling(cpuc);
 923
 924         return unsched ? -EINVAL : 0;
 925 }
 926
 927 /*
 928  * dogrp: true if must collect siblings events (group)
 929  * returns total number of events and error code
 930  */
 931 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 932 {
 933         struct perf_event *event;
 934         int n, max_count;
 935
 936         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 937
 938         /* current number of events already accepted */
 939         n = cpuc->n_events;
 940
 941         if (is_x86_event(leader)) {
 942                 if (n >= max_count)
 943                         return -EINVAL;
 944                 cpuc->event_list[n] = leader;
 945                 n++;
 946         }
 947         if (!dogrp)
 948                 return n;
 949
 950         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 951                 if (!is_x86_event(event) ||
 952                     event->state <= PERF_EVENT_STATE_OFF)
 953                         continue;
 954
 955                 if (n >= max_count)
 956                         return -EINVAL;
 957
 958                 cpuc->event_list[n] = event;
 959                 n++;
 960         }
 961         return n;
 962 }
 963
 964 static inline void x86_assign_hw_event(struct perf_event *event,
 965                                 struct cpu_hw_events *cpuc, int i)
 966 {
 967         struct hw_perf_event *hwc = &event->hw;
 968
 969         hwc->idx = cpuc->assign[i];
 970         hwc->last_cpu = smp_processor_id();
 971         hwc->last_tag = ++cpuc->tags[i];
 972
 973         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
 974                 hwc->config_base = 0;
 975                 hwc->event_base = 0;
 976         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
 977                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 978                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
 979                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
 980         } else {
 981                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 982                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 983                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
 984         }
 985 }
 986
 987 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 988                                         struct cpu_hw_events *cpuc,
 989                                         int i)
 990 {
 991         return hwc->idx == cpuc->assign[i] &&
 992                 hwc->last_cpu == smp_processor_id() &&
 993                 hwc->last_tag == cpuc->tags[i];
 994 }
 995
 996 static void x86_pmu_start(struct perf_event *event, int flags);
 997
 998 static void x86_pmu_enable(struct pmu *pmu)
 999 {
1000         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1001         struct perf_event *event;
1002         struct hw_perf_event *hwc;
1003         int i, added = cpuc->n_added;
1004
1005         if (!x86_pmu_initialized())
1006                 return;
1007
1008         if (cpuc->enabled)
1009                 return;
1010
1011         if (cpuc->n_added) {
1012                 int n_running = cpuc->n_events - cpuc->n_added;
1013                 /*
1014                  * apply assignment obtained either from
1015                  * hw_perf_group_sched_in() or x86_pmu_enable()
1016                  *
1017                  * step1: save events moving to new counters
1018                  */
1019                 for (i = 0; i < n_running; i++) {
1020                         event = cpuc->event_list[i];
1021                         hwc = &event->hw;
1022
1023                         /*
1024                          * we can avoid reprogramming counter if:
1025                          * - assigned same counter as last time
1026                          * - running on same CPU as last time
1027                          * - no other event has used the counter since
1028                          */
1029                         if (hwc->idx == -1 ||
1030                             match_prev_assignment(hwc, cpuc, i))
1031                                 continue;
1032
1033                         /*
1034                          * Ensure we don't accidentally enable a stopped
1035                          * counter simply because we rescheduled.
1036                          */
1037                         if (hwc->state & PERF_HES_STOPPED)
1038                                 hwc->state |= PERF_HES_ARCH;
1039
1040                         x86_pmu_stop(event, PERF_EF_UPDATE);
1041                 }
1042
1043                 /*
1044                  * step2: reprogram moved events into new counters
1045                  */
1046                 for (i = 0; i < cpuc->n_events; i++) {
1047                         event = cpuc->event_list[i];
1048                         hwc = &event->hw;
1049
1050                         if (!match_prev_assignment(hwc, cpuc, i))
1051                                 x86_assign_hw_event(event, cpuc, i);
1052                         else if (i < n_running)
1053                                 continue;
1054
1055                         if (hwc->state & PERF_HES_ARCH)
1056                                 continue;
1057
1058                         x86_pmu_start(event, PERF_EF_RELOAD);
1059                 }
1060                 cpuc->n_added = 0;
1061                 perf_events_lapic_init();
1062         }
1063
1064         cpuc->enabled = 1;
1065         barrier();
1066
1067         x86_pmu.enable_all(added);
1068 }
1069
1070 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1071
1072 /*
1073  * Set the next IRQ period, based on the hwc->period_left value.
1074  * To be called with the event disabled in hw:
1075  */
1076 int x86_perf_event_set_period(struct perf_event *event)
1077 {
1078         struct hw_perf_event *hwc = &event->hw;
1079         s64 left = local64_read(&hwc->period_left);
1080         s64 period = hwc->sample_period;
1081         int ret = 0, idx = hwc->idx;
1082
1083         if (idx == INTEL_PMC_IDX_FIXED_BTS)
1084                 return 0;
1085
1086         /*
1087          * If we are way outside a reasonable range then just skip forward:
1088          */
1089         if (unlikely(left <= -period)) {
1090                 left = period;
1091                 local64_set(&hwc->period_left, left);
1092                 hwc->last_period = period;
1093                 ret = 1;
1094         }
1095
1096         if (unlikely(left <= 0)) {
1097                 left += period;
1098                 local64_set(&hwc->period_left, left);
1099                 hwc->last_period = period;
1100                 ret = 1;
1101         }
1102         /*
1103          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1104          */
1105         if (unlikely(left < 2))
1106                 left = 2;
1107
1108         if (left > x86_pmu.max_period)
1109                 left = x86_pmu.max_period;
1110
1111         if (x86_pmu.limit_period)
1112                 left = x86_pmu.limit_period(event, left);
1113
1114         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1115
1116         if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
1117             local64_read(&hwc->prev_count) != (u64)-left) {
1118                 /*
1119                  * The hw event starts counting from this event offset,
1120                  * mark it to be able to extra future deltas:
1121                  */
1122                 local64_set(&hwc->prev_count, (u64)-left);
1123
1124                 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1125         }
1126
1127         /*
1128          * Due to erratum on certan cpu we need
1129          * a second write to be sure the register
1130          * is updated properly
1131          */
1132         if (x86_pmu.perfctr_second_write) {
1133                 wrmsrl(hwc->event_base,
1134                         (u64)(-left) & x86_pmu.cntval_mask);
1135         }
1136
1137         perf_event_update_userpage(event);
1138
1139         return ret;
1140 }
1141
1142 void x86_pmu_enable_event(struct perf_event *event)
1143 {
1144         if (__this_cpu_read(cpu_hw_events.enabled))
1145                 __x86_pmu_enable_event(&event->hw,
1146                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1147 }
1148
1149 /*
1150  * Add a single event to the PMU.
1151  *
1152  * The event is added to the group of enabled events
1153  * but only if it can be scehduled with existing events.
1154  */
1155 static int x86_pmu_add(struct perf_event *event, int flags)
1156 {
1157         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1158         struct hw_perf_event *hwc;
1159         int assign[X86_PMC_IDX_MAX];
1160         int n, n0, ret;
1161
1162         hwc = &event->hw;
1163
1164         n0 = cpuc->n_events;
1165         ret = n = collect_events(cpuc, event, false);
1166         if (ret < 0)
1167                 goto out;
1168
1169         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1170         if (!(flags & PERF_EF_START))
1171                 hwc->state |= PERF_HES_ARCH;
1172
1173         /*
1174          * If group events scheduling transaction was started,
1175          * skip the schedulability test here, it will be performed
1176          * at commit time (->commit_txn) as a whole.
1177          */
1178         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1179                 goto done_collect;
1180
1181         ret = x86_pmu.schedule_events(cpuc, n, assign);
1182         if (ret)
1183                 goto out;
1184         /*
1185          * copy new assignment, now we know it is possible
1186          * will be used by hw_perf_enable()
1187          */
1188         memcpy(cpuc->assign, assign, n*sizeof(int));
1189
1190 done_collect:
1191         /*
1192          * Commit the collect_events() state. See x86_pmu_del() and
1193          * x86_pmu_*_txn().
1194          */
1195         cpuc->n_events = n;
1196         cpuc->n_added += n - n0;
1197         cpuc->n_txn += n - n0;
1198
1199         ret = 0;
1200 out:
1201         return ret;
1202 }
1203
1204 static void x86_pmu_start(struct perf_event *event, int flags)
1205 {
1206         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1207         int idx = event->hw.idx;
1208
1209         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1210                 return;
1211
1212         if (WARN_ON_ONCE(idx == -1))
1213                 return;
1214
1215         if (flags & PERF_EF_RELOAD) {
1216                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1217                 x86_perf_event_set_period(event);
1218         }
1219
1220         event->hw.state = 0;
1221
1222         cpuc->events[idx] = event;
1223         __set_bit(idx, cpuc->active_mask);
1224         __set_bit(idx, cpuc->running);
1225         x86_pmu.enable(event);
1226         perf_event_update_userpage(event);
1227 }
1228
1229 void perf_event_print_debug(void)
1230 {
1231         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1232         u64 pebs, debugctl;
1233         struct cpu_hw_events *cpuc;
1234         unsigned long flags;
1235         int cpu, idx;
1236
1237         if (!x86_pmu.num_counters)
1238                 return;
1239
1240         local_irq_save(flags);
1241
1242         cpu = smp_processor_id();
1243         cpuc = &per_cpu(cpu_hw_events, cpu);
1244
1245         if (x86_pmu.version >= 2) {
1246                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1247                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1248                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1249                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1250
1251                 pr_info("\n");
1252                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1253                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1254                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1255                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1256                 if (x86_pmu.pebs_constraints) {
1257                         rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1258                         pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1259                 }
1260                 if (x86_pmu.lbr_nr) {
1261                         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1262                         pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
1263                 }
1264         }
1265         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1266
1267         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1268                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1269                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1270
1271                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1272
1273                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1274                         cpu, idx, pmc_ctrl);
1275                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1276                         cpu, idx, pmc_count);
1277                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1278                         cpu, idx, prev_left);
1279         }
1280         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1281                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1282
1283                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1284                         cpu, idx, pmc_count);
1285         }
1286         local_irq_restore(flags);
1287 }
1288
1289 void x86_pmu_stop(struct perf_event *event, int flags)
1290 {
1291         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1292         struct hw_perf_event *hwc = &event->hw;
1293
1294         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1295                 x86_pmu.disable(event);
1296                 cpuc->events[hwc->idx] = NULL;
1297                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1298                 hwc->state |= PERF_HES_STOPPED;
1299         }
1300
1301         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1302                 /*
1303                  * Drain the remaining delta count out of a event
1304                  * that we are disabling:
1305                  */
1306                 x86_perf_event_update(event);
1307                 hwc->state |= PERF_HES_UPTODATE;
1308         }
1309 }
1310
1311 static void x86_pmu_del(struct perf_event *event, int flags)
1312 {
1313         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1314         int i;
1315
1316         /*
1317          * event is descheduled
1318          */
1319         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1320
1321         /*
1322          * If we're called during a txn, we don't need to do anything.
1323          * The events never got scheduled and ->cancel_txn will truncate
1324          * the event_list.
1325          *
1326          * XXX assumes any ->del() called during a TXN will only be on
1327          * an event added during that same TXN.
1328          */
1329         if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1330                 return;
1331
1332         /*
1333          * Not a TXN, therefore cleanup properly.
1334          */
1335         x86_pmu_stop(event, PERF_EF_UPDATE);
1336
1337         for (i = 0; i < cpuc->n_events; i++) {
1338                 if (event == cpuc->event_list[i])
1339                         break;
1340         }
1341
1342         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1343                 return;
1344
1345         /* If we have a newly added event; make sure to decrease n_added. */
1346         if (i >= cpuc->n_events - cpuc->n_added)
1347                 --cpuc->n_added;
1348
1349         if (x86_pmu.put_event_constraints)
1350                 x86_pmu.put_event_constraints(cpuc, event);
1351
1352         /* Delete the array entry. */
1353         while (++i < cpuc->n_events) {
1354                 cpuc->event_list[i-1] = cpuc->event_list[i];
1355                 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1356         }
1357         --cpuc->n_events;
1358
1359         perf_event_update_userpage(event);
1360 }
1361
1362 int x86_pmu_handle_irq(struct pt_regs *regs)
1363 {
1364         struct perf_sample_data data;
1365         struct cpu_hw_events *cpuc;
1366         struct perf_event *event;
1367         int idx, handled = 0;
1368         u64 val;
1369
1370         cpuc = this_cpu_ptr(&cpu_hw_events);
1371
1372         /*
1373          * Some chipsets need to unmask the LVTPC in a particular spot
1374          * inside the nmi handler.  As a result, the unmasking was pushed
1375          * into all the nmi handlers.
1376          *
1377          * This generic handler doesn't seem to have any issues where the
1378          * unmasking occurs so it was left at the top.
1379          */
1380         apic_write(APIC_LVTPC, APIC_DM_NMI);
1381
1382         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1383                 if (!test_bit(idx, cpuc->active_mask)) {
1384                         /*
1385                          * Though we deactivated the counter some cpus
1386                          * might still deliver spurious interrupts still
1387                          * in flight. Catch them:
1388                          */
1389                         if (__test_and_clear_bit(idx, cpuc->running))
1390                                 handled++;
1391                         continue;
1392                 }
1393
1394                 event = cpuc->events[idx];
1395
1396                 val = x86_perf_event_update(event);
1397                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1398                         continue;
1399
1400                 /*
1401                  * event overflow
1402                  */
1403                 handled++;
1404                 perf_sample_data_init(&data, 0, event->hw.last_period);
1405
1406                 if (!x86_perf_event_set_period(event))
1407                         continue;
1408
1409                 if (perf_event_overflow(event, &data, regs))
1410                         x86_pmu_stop(event, 0);
1411         }
1412
1413         if (handled)
1414                 inc_irq_stat(apic_perf_irqs);
1415
1416         return handled;
1417 }
1418
1419 void perf_events_lapic_init(void)
1420 {
1421         if (!x86_pmu.apic || !x86_pmu_initialized())
1422                 return;
1423
1424         /*
1425          * Always use NMI for PMU
1426          */
1427         apic_write(APIC_LVTPC, APIC_DM_NMI);
1428 }
1429
1430 static int
1431 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1432 {
1433         u64 start_clock;
1434         u64 finish_clock;
1435         int ret;
1436
1437         /*
1438          * All PMUs/events that share this PMI handler should make sure to
1439          * increment active_events for their events.
1440          */
1441         if (!atomic_read(&active_events))
1442                 return NMI_DONE;
1443
1444         start_clock = sched_clock();
1445         ret = x86_pmu.handle_irq(regs);
1446         finish_clock = sched_clock();
1447
1448         perf_sample_event_took(finish_clock - start_clock);
1449
1450         return ret;
1451 }
1452 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1453
1454 struct event_constraint emptyconstraint;
1455 struct event_constraint unconstrained;
1456
1457 static int
1458 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1459 {
1460         unsigned int cpu = (long)hcpu;
1461         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1462         int i, ret = NOTIFY_OK;
1463
1464         switch (action & ~CPU_TASKS_FROZEN) {
1465         case CPU_UP_PREPARE:
1466                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1467                         cpuc->kfree_on_online[i] = NULL;
1468                 if (x86_pmu.cpu_prepare)
1469                         ret = x86_pmu.cpu_prepare(cpu);
1470                 break;
1471
1472         case CPU_STARTING:
1473                 if (x86_pmu.cpu_starting)
1474                         x86_pmu.cpu_starting(cpu);
1475                 break;
1476
1477         case CPU_ONLINE:
1478                 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1479                         kfree(cpuc->kfree_on_online[i]);
1480                         cpuc->kfree_on_online[i] = NULL;
1481                 }
1482                 break;
1483
1484         case CPU_DYING:
1485                 if (x86_pmu.cpu_dying)
1486                         x86_pmu.cpu_dying(cpu);
1487                 break;
1488
1489         case CPU_UP_CANCELED:
1490         case CPU_DEAD:
1491                 if (x86_pmu.cpu_dead)
1492                         x86_pmu.cpu_dead(cpu);
1493                 break;
1494
1495         default:
1496                 break;
1497         }
1498
1499         return ret;
1500 }
1501
1502 static void __init pmu_check_apic(void)
1503 {
1504         if (cpu_has_apic)
1505                 return;
1506
1507         x86_pmu.apic = 0;
1508         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1509         pr_info("no hardware sampling interrupt available.\n");
1510
1511         /*
1512          * If we have a PMU initialized but no APIC
1513          * interrupts, we cannot sample hardware
1514          * events (user-space has to fall back and
1515          * sample via a hrtimer based software event):
1516          */
1517         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1518
1519 }
1520
1521 static struct attribute_group x86_pmu_format_group = {
1522         .name = "format",
1523         .attrs = NULL,
1524 };
1525
1526 /*
1527  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1528  * out of events_attr attributes.
1529  */
1530 static void __init filter_events(struct attribute **attrs)
1531 {
1532         struct device_attribute *d;
1533         struct perf_pmu_events_attr *pmu_attr;
1534         int i, j;
1535
1536         for (i = 0; attrs[i]; i++) {
1537                 d = (struct device_attribute *)attrs[i];
1538                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1539                 /* str trumps id */
1540                 if (pmu_attr->event_str)
1541                         continue;
1542                 if (x86_pmu.event_map(i))
1543                         continue;
1544
1545                 for (j = i; attrs[j]; j++)
1546                         attrs[j] = attrs[j + 1];
1547
1548                 /* Check the shifted attr. */
1549                 i--;
1550         }
1551 }
1552
1553 /* Merge two pointer arrays */
1554 __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1555 {
1556         struct attribute **new;
1557         int j, i;
1558
1559         for (j = 0; a[j]; j++)
1560                 ;
1561         for (i = 0; b[i]; i++)
1562                 j++;
1563         j++;
1564
1565         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1566         if (!new)
1567                 return NULL;
1568
1569         j = 0;
1570         for (i = 0; a[i]; i++)
1571                 new[j++] = a[i];
1572         for (i = 0; b[i]; i++)
1573                 new[j++] = b[i];
1574         new[j] = NULL;
1575
1576         return new;
1577 }
1578
1579 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1580                           char *page)
1581 {
1582         struct perf_pmu_events_attr *pmu_attr = \
1583                 container_of(attr, struct perf_pmu_events_attr, attr);
1584         u64 config = x86_pmu.event_map(pmu_attr->id);
1585
1586         /* string trumps id */
1587         if (pmu_attr->event_str)
1588                 return sprintf(page, "%s", pmu_attr->event_str);
1589
1590         return x86_pmu.events_sysfs_show(page, config);
1591 }
1592
1593 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1594 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1595 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1596 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1597 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1598 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1599 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1600 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1601 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1602 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1603
1604 static struct attribute *empty_attrs;
1605
1606 static struct attribute *events_attr[] = {
1607         EVENT_PTR(CPU_CYCLES),
1608         EVENT_PTR(INSTRUCTIONS),
1609         EVENT_PTR(CACHE_REFERENCES),
1610         EVENT_PTR(CACHE_MISSES),
1611         EVENT_PTR(BRANCH_INSTRUCTIONS),
1612         EVENT_PTR(BRANCH_MISSES),
1613         EVENT_PTR(BUS_CYCLES),
1614         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1615         EVENT_PTR(STALLED_CYCLES_BACKEND),
1616         EVENT_PTR(REF_CPU_CYCLES),
1617         NULL,
1618 };
1619
1620 static struct attribute_group x86_pmu_events_group = {
1621         .name = "events",
1622         .attrs = events_attr,
1623 };
1624
1625 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1626 {
1627         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1628         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1629         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1630         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1631         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1632         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1633         ssize_t ret;
1634
1635         /*
1636         * We have whole page size to spend and just little data
1637         * to write, so we can safely use sprintf.
1638         */
1639         ret = sprintf(page, "event=0x%02llx", event);
1640
1641         if (umask)
1642                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1643
1644         if (edge)
1645                 ret += sprintf(page + ret, ",edge");
1646
1647         if (pc)
1648                 ret += sprintf(page + ret, ",pc");
1649
1650         if (any)
1651                 ret += sprintf(page + ret, ",any");
1652
1653         if (inv)
1654                 ret += sprintf(page + ret, ",inv");
1655
1656         if (cmask)
1657                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1658
1659         ret += sprintf(page + ret, "\n");
1660
1661         return ret;
1662 }
1663
1664 static int __init init_hw_perf_events(void)
1665 {
1666         struct x86_pmu_quirk *quirk;
1667         int err;
1668
1669         pr_info("Performance Events: ");
1670
1671         switch (boot_cpu_data.x86_vendor) {
1672         case X86_VENDOR_INTEL:
1673                 err = intel_pmu_init();
1674                 break;
1675         case X86_VENDOR_AMD:
1676                 err = amd_pmu_init();
1677                 break;
1678         default:
1679                 err = -ENOTSUPP;
1680         }
1681         if (err != 0) {
1682                 pr_cont("no PMU driver, software events only.\n");
1683                 return 0;
1684         }
1685
1686         pmu_check_apic();
1687
1688         /* sanity check that the hardware exists or is emulated */
1689         if (!check_hw_exists())
1690                 return 0;
1691
1692         pr_cont("%s PMU driver.\n", x86_pmu.name);
1693
1694         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1695
1696         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1697                 quirk->func();
1698
1699         if (!x86_pmu.intel_ctrl)
1700                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1701
1702         perf_events_lapic_init();
1703         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1704
1705         unconstrained = (struct event_constraint)
1706                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1707                                    0, x86_pmu.num_counters, 0, 0);
1708
1709         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1710
1711         if (x86_pmu.event_attrs)
1712                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1713
1714         if (!x86_pmu.events_sysfs_show)
1715                 x86_pmu_events_group.attrs = &empty_attrs;
1716         else
1717                 filter_events(x86_pmu_events_group.attrs);
1718
1719         if (x86_pmu.cpu_events) {
1720                 struct attribute **tmp;
1721
1722                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1723                 if (!WARN_ON(!tmp))
1724                         x86_pmu_events_group.attrs = tmp;
1725         }
1726
1727         pr_info("... version:                %d\n",     x86_pmu.version);
1728         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1729         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1730         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1731         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1732         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1733         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1734
1735         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1736         perf_cpu_notifier(x86_pmu_notifier);
1737
1738         return 0;
1739 }
1740 early_initcall(init_hw_perf_events);
1741
1742 static inline void x86_pmu_read(struct perf_event *event)
1743 {
1744         x86_perf_event_update(event);
1745 }
1746
1747 /*
1748  * Start group events scheduling transaction
1749  * Set the flag to make pmu::enable() not perform the
1750  * schedulability test, it will be performed at commit time
1751  *
1752  * We only support PERF_PMU_TXN_ADD transactions. Save the
1753  * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1754  * transactions.
1755  */
1756 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1757 {
1758         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1759
1760         WARN_ON_ONCE(cpuc->txn_flags);          /* txn already in flight */
1761
1762         cpuc->txn_flags = txn_flags;
1763         if (txn_flags & ~PERF_PMU_TXN_ADD)
1764                 return;
1765
1766         perf_pmu_disable(pmu);
1767         __this_cpu_write(cpu_hw_events.n_txn, 0);
1768 }
1769
1770 /*
1771  * Stop group events scheduling transaction
1772  * Clear the flag and pmu::enable() will perform the
1773  * schedulability test.
1774  */
1775 static void x86_pmu_cancel_txn(struct pmu *pmu)
1776 {
1777         unsigned int txn_flags;
1778         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1779
1780         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1781
1782         txn_flags = cpuc->txn_flags;
1783         cpuc->txn_flags = 0;
1784         if (txn_flags & ~PERF_PMU_TXN_ADD)
1785                 return;
1786
1787         /*
1788          * Truncate collected array by the number of events added in this
1789          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1790          */
1791         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1792         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1793         perf_pmu_enable(pmu);
1794 }
1795
1796 /*
1797  * Commit group events scheduling transaction
1798  * Perform the group schedulability test as a whole
1799  * Return 0 if success
1800  *
1801  * Does not cancel the transaction on failure; expects the caller to do this.
1802  */
1803 static int x86_pmu_commit_txn(struct pmu *pmu)
1804 {
1805         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1806         int assign[X86_PMC_IDX_MAX];
1807         int n, ret;
1808
1809         WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
1810
1811         if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1812                 cpuc->txn_flags = 0;
1813                 return 0;
1814         }
1815
1816         n = cpuc->n_events;
1817
1818         if (!x86_pmu_initialized())
1819                 return -EAGAIN;
1820
1821         ret = x86_pmu.schedule_events(cpuc, n, assign);
1822         if (ret)
1823                 return ret;
1824
1825         /*
1826          * copy new assignment, now we know it is possible
1827          * will be used by hw_perf_enable()
1828          */
1829         memcpy(cpuc->assign, assign, n*sizeof(int));
1830
1831         cpuc->txn_flags = 0;
1832         perf_pmu_enable(pmu);
1833         return 0;
1834 }
1835 /*
1836  * a fake_cpuc is used to validate event groups. Due to
1837  * the extra reg logic, we need to also allocate a fake
1838  * per_core and per_cpu structure. Otherwise, group events
1839  * using extra reg may conflict without the kernel being
1840  * able to catch this when the last event gets added to
1841  * the group.
1842  */
1843 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1844 {
1845         kfree(cpuc->shared_regs);
1846         kfree(cpuc);
1847 }
1848
1849 static struct cpu_hw_events *allocate_fake_cpuc(void)
1850 {
1851         struct cpu_hw_events *cpuc;
1852         int cpu = raw_smp_processor_id();
1853
1854         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1855         if (!cpuc)
1856                 return ERR_PTR(-ENOMEM);
1857
1858         /* only needed, if we have extra_regs */
1859         if (x86_pmu.extra_regs) {
1860                 cpuc->shared_regs = allocate_shared_regs(cpu);
1861                 if (!cpuc->shared_regs)
1862                         goto error;
1863         }
1864         cpuc->is_fake = 1;
1865         return cpuc;
1866 error:
1867         free_fake_cpuc(cpuc);
1868         return ERR_PTR(-ENOMEM);
1869 }
1870
1871 /*
1872  * validate that we can schedule this event
1873  */
1874 static int validate_event(struct perf_event *event)
1875 {
1876         struct cpu_hw_events *fake_cpuc;
1877         struct event_constraint *c;
1878         int ret = 0;
1879
1880         fake_cpuc = allocate_fake_cpuc();
1881         if (IS_ERR(fake_cpuc))
1882                 return PTR_ERR(fake_cpuc);
1883
1884         c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1885
1886         if (!c || !c->weight)
1887                 ret = -EINVAL;
1888
1889         if (x86_pmu.put_event_constraints)
1890                 x86_pmu.put_event_constraints(fake_cpuc, event);
1891
1892         free_fake_cpuc(fake_cpuc);
1893
1894         return ret;
1895 }
1896
1897 /*
1898  * validate a single event group
1899  *
1900  * validation include:
1901  *      - check events are compatible which each other
1902  *      - events do not compete for the same counter
1903  *      - number of events <= number of counters
1904  *
1905  * validation ensures the group can be loaded onto the
1906  * PMU if it was the only group available.
1907  */
1908 static int validate_group(struct perf_event *event)
1909 {
1910         struct perf_event *leader = event->group_leader;
1911         struct cpu_hw_events *fake_cpuc;
1912         int ret = -EINVAL, n;
1913
1914         fake_cpuc = allocate_fake_cpuc();
1915         if (IS_ERR(fake_cpuc))
1916                 return PTR_ERR(fake_cpuc);
1917         /*
1918          * the event is not yet connected with its
1919          * siblings therefore we must first collect
1920          * existing siblings, then add the new event
1921          * before we can simulate the scheduling
1922          */
1923         n = collect_events(fake_cpuc, leader, true);
1924         if (n < 0)
1925                 goto out;
1926
1927         fake_cpuc->n_events = n;
1928         n = collect_events(fake_cpuc, event, false);
1929         if (n < 0)
1930                 goto out;
1931
1932         fake_cpuc->n_events = n;
1933
1934         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1935
1936 out:
1937         free_fake_cpuc(fake_cpuc);
1938         return ret;
1939 }
1940
1941 static int x86_pmu_event_init(struct perf_event *event)
1942 {
1943         struct pmu *tmp;
1944         int err;
1945
1946         switch (event->attr.type) {
1947         case PERF_TYPE_RAW:
1948         case PERF_TYPE_HARDWARE:
1949         case PERF_TYPE_HW_CACHE:
1950                 break;
1951
1952         default:
1953                 return -ENOENT;
1954         }
1955
1956         err = __x86_pmu_event_init(event);
1957         if (!err) {
1958                 /*
1959                  * we temporarily connect event to its pmu
1960                  * such that validate_group() can classify
1961                  * it as an x86 event using is_x86_event()
1962                  */
1963                 tmp = event->pmu;
1964                 event->pmu = &pmu;
1965
1966                 if (event->group_leader != event)
1967                         err = validate_group(event);
1968                 else
1969                         err = validate_event(event);
1970
1971                 event->pmu = tmp;
1972         }
1973         if (err) {
1974                 if (event->destroy)
1975                         event->destroy(event);
1976         }
1977
1978         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1979                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1980
1981         return err;
1982 }
1983
1984 static void refresh_pce(void *ignored)
1985 {
1986         if (current->mm)
1987                 load_mm_cr4(current->mm);
1988 }
1989
1990 static void x86_pmu_event_mapped(struct perf_event *event)
1991 {
1992         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1993                 return;
1994
1995         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
1996                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1997 }
1998
1999 static void x86_pmu_event_unmapped(struct perf_event *event)
2000 {
2001         if (!current->mm)
2002                 return;
2003
2004         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2005                 return;
2006
2007         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
2008                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
2009 }
2010
2011 static int x86_pmu_event_idx(struct perf_event *event)
2012 {
2013         int idx = event->hw.idx;
2014
2015         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2016                 return 0;
2017
2018         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2019                 idx -= INTEL_PMC_IDX_FIXED;
2020                 idx |= 1 << 30;
2021         }
2022
2023         return idx + 1;
2024 }
2025
2026 static ssize_t get_attr_rdpmc(struct device *cdev,
2027                               struct device_attribute *attr,
2028                               char *buf)
2029 {
2030         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2031 }
2032
2033 static ssize_t set_attr_rdpmc(struct device *cdev,
2034                               struct device_attribute *attr,
2035                               const char *buf, size_t count)
2036 {
2037         unsigned long val;
2038         ssize_t ret;
2039
2040         ret = kstrtoul(buf, 0, &val);
2041         if (ret)
2042                 return ret;
2043
2044         if (val > 2)
2045                 return -EINVAL;
2046
2047         if (x86_pmu.attr_rdpmc_broken)
2048                 return -ENOTSUPP;
2049
2050         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2051                 /*
2052                  * Changing into or out of always available, aka
2053                  * perf-event-bypassing mode.  This path is extremely slow,
2054                  * but only root can trigger it, so it's okay.
2055                  */
2056                 if (val == 2)
2057                         static_key_slow_inc(&rdpmc_always_available);
2058                 else
2059                         static_key_slow_dec(&rdpmc_always_available);
2060                 on_each_cpu(refresh_pce, NULL, 1);
2061         }
2062
2063         x86_pmu.attr_rdpmc = val;
2064
2065         return count;
2066 }
2067
2068 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2069
2070 static struct attribute *x86_pmu_attrs[] = {
2071         &dev_attr_rdpmc.attr,
2072         NULL,
2073 };
2074
2075 static struct attribute_group x86_pmu_attr_group = {
2076         .attrs = x86_pmu_attrs,
2077 };
2078
2079 static const struct attribute_group *x86_pmu_attr_groups[] = {
2080         &x86_pmu_attr_group,
2081         &x86_pmu_format_group,
2082         &x86_pmu_events_group,
2083         NULL,
2084 };
2085
2086 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2087 {
2088         if (x86_pmu.sched_task)
2089                 x86_pmu.sched_task(ctx, sched_in);
2090 }
2091
2092 void perf_check_microcode(void)
2093 {
2094         if (x86_pmu.check_microcode)
2095                 x86_pmu.check_microcode();
2096 }
2097 EXPORT_SYMBOL_GPL(perf_check_microcode);
2098
2099 static struct pmu pmu = {
2100         .pmu_enable             = x86_pmu_enable,
2101         .pmu_disable            = x86_pmu_disable,
2102
2103         .attr_groups            = x86_pmu_attr_groups,
2104
2105         .event_init             = x86_pmu_event_init,
2106
2107         .event_mapped           = x86_pmu_event_mapped,
2108         .event_unmapped         = x86_pmu_event_unmapped,
2109
2110         .add                    = x86_pmu_add,
2111         .del                    = x86_pmu_del,
2112         .start                  = x86_pmu_start,
2113         .stop                   = x86_pmu_stop,
2114         .read                   = x86_pmu_read,
2115
2116         .start_txn              = x86_pmu_start_txn,
2117         .cancel_txn             = x86_pmu_cancel_txn,
2118         .commit_txn             = x86_pmu_commit_txn,
2119
2120         .event_idx              = x86_pmu_event_idx,
2121         .sched_task             = x86_pmu_sched_task,
2122         .task_ctx_size          = sizeof(struct x86_perf_task_context),
2123 };
2124
2125 void arch_perf_update_userpage(struct perf_event *event,
2126                                struct perf_event_mmap_page *userpg, u64 now)
2127 {
2128         struct cyc2ns_data *data;
2129
2130         userpg->cap_user_time = 0;
2131         userpg->cap_user_time_zero = 0;
2132         userpg->cap_user_rdpmc =
2133                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2134         userpg->pmc_width = x86_pmu.cntval_bits;
2135
2136         if (!sched_clock_stable())
2137                 return;
2138
2139         data = cyc2ns_read_begin();
2140
2141         /*
2142          * Internal timekeeping for enabled/running/stopped times
2143          * is always in the local_clock domain.
2144          */
2145         userpg->cap_user_time = 1;
2146         userpg->time_mult = data->cyc2ns_mul;
2147         userpg->time_shift = data->cyc2ns_shift;
2148         userpg->time_offset = data->cyc2ns_offset - now;
2149
2150         /*
2151          * cap_user_time_zero doesn't make sense when we're using a different
2152          * time base for the records.
2153          */
2154         if (event->clock == &local_clock) {
2155                 userpg->cap_user_time_zero = 1;
2156                 userpg->time_zero = data->cyc2ns_offset;
2157         }
2158
2159         cyc2ns_read_end(data);
2160 }
2161
2162 /*
2163  * callchain support
2164  */
2165
2166 static int backtrace_stack(void *data, char *name)
2167 {
2168         return 0;
2169 }
2170
2171 static void backtrace_address(void *data, unsigned long addr, int reliable)
2172 {
2173         struct perf_callchain_entry *entry = data;
2174
2175         perf_callchain_store(entry, addr);
2176 }
2177
2178 static const struct stacktrace_ops backtrace_ops = {
2179         .stack                  = backtrace_stack,
2180         .address                = backtrace_address,
2181         .walk_stack             = print_context_stack_bp,
2182 };
2183
2184 void
2185 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2186 {
2187         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2188                 /* TODO: We don't support guest os callchain now */
2189                 return;
2190         }
2191
2192         perf_callchain_store(entry, regs->ip);
2193
2194         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2195 }
2196
2197 static inline int
2198 valid_user_frame(const void __user *fp, unsigned long size)
2199 {
2200         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2201 }
2202
2203 static unsigned long get_segment_base(unsigned int segment)
2204 {
2205         struct desc_struct *desc;
2206         int idx = segment >> 3;
2207
2208         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2209 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2210                 struct ldt_struct *ldt;
2211
2212                 if (idx > LDT_ENTRIES)
2213                         return 0;
2214
2215                 /* IRQs are off, so this synchronizes with smp_store_release */
2216                 ldt = lockless_dereference(current->active_mm->context.ldt);
2217                 if (!ldt || idx > ldt->size)
2218                         return 0;
2219
2220                 desc = &ldt->entries[idx];
2221 #else
2222                 return 0;
2223 #endif
2224         } else {
2225                 if (idx > GDT_ENTRIES)
2226                         return 0;
2227
2228                 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2229         }
2230
2231         return get_desc_base(desc);
2232 }
2233
2234 #ifdef CONFIG_IA32_EMULATION
2235
2236 #include <asm/compat.h>
2237
2238 static inline int
2239 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2240 {
2241         /* 32-bit process in 64-bit kernel. */
2242         unsigned long ss_base, cs_base;
2243         struct stack_frame_ia32 frame;
2244         const void __user *fp;
2245
2246         if (!test_thread_flag(TIF_IA32))
2247                 return 0;
2248
2249         cs_base = get_segment_base(regs->cs);
2250         ss_base = get_segment_base(regs->ss);
2251
2252         fp = compat_ptr(ss_base + regs->bp);
2253         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2254                 unsigned long bytes;
2255                 frame.next_frame     = 0;
2256                 frame.return_address = 0;
2257
2258                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2259                 if (bytes != 0)
2260                         break;
2261
2262                 if (!valid_user_frame(fp, sizeof(frame)))
2263                         break;
2264
2265                 perf_callchain_store(entry, cs_base + frame.return_address);
2266                 fp = compat_ptr(ss_base + frame.next_frame);
2267         }
2268         return 1;
2269 }
2270 #else
2271 static inline int
2272 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2273 {
2274     return 0;
2275 }
2276 #endif
2277
2278 void
2279 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2280 {
2281         struct stack_frame frame;
2282         const void __user *fp;
2283
2284         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2285                 /* TODO: We don't support guest os callchain now */
2286                 return;
2287         }
2288
2289         /*
2290          * We don't know what to do with VM86 stacks.. ignore them for now.
2291          */
2292         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2293                 return;
2294
2295         fp = (void __user *)regs->bp;
2296
2297         perf_callchain_store(entry, regs->ip);
2298
2299         if (!current->mm)
2300                 return;
2301
2302         if (perf_callchain_user32(regs, entry))
2303                 return;
2304
2305         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2306                 unsigned long bytes;
2307                 frame.next_frame             = NULL;
2308                 frame.return_address = 0;
2309
2310                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2311                 if (bytes != 0)
2312                         break;
2313
2314                 if (!valid_user_frame(fp, sizeof(frame)))
2315                         break;
2316
2317                 perf_callchain_store(entry, frame.return_address);
2318                 fp = frame.next_frame;
2319         }
2320 }
2321
2322 /*
2323  * Deal with code segment offsets for the various execution modes:
2324  *
2325  *   VM86 - the good olde 16 bit days, where the linear address is
2326  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2327  *
2328  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2329  *          to figure out what the 32bit base address is.
2330  *
2331  *    X32 - has TIF_X32 set, but is running in x86_64
2332  *
2333  * X86_64 - CS,DS,SS,ES are all zero based.
2334  */
2335 static unsigned long code_segment_base(struct pt_regs *regs)
2336 {
2337         /*
2338          * For IA32 we look at the GDT/LDT segment base to convert the
2339          * effective IP to a linear address.
2340          */
2341
2342 #ifdef CONFIG_X86_32
2343         /*
2344          * If we are in VM86 mode, add the segment offset to convert to a
2345          * linear address.
2346          */
2347         if (regs->flags & X86_VM_MASK)
2348                 return 0x10 * regs->cs;
2349
2350         if (user_mode(regs) && regs->cs != __USER_CS)
2351                 return get_segment_base(regs->cs);
2352 #else
2353         if (user_mode(regs) && !user_64bit_mode(regs) &&
2354             regs->cs != __USER32_CS)
2355                 return get_segment_base(regs->cs);
2356 #endif
2357         return 0;
2358 }
2359
2360 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2361 {
2362         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2363                 return perf_guest_cbs->get_guest_ip();
2364
2365         return regs->ip + code_segment_base(regs);
2366 }
2367
2368 unsigned long perf_misc_flags(struct pt_regs *regs)
2369 {
2370         int misc = 0;
2371
2372         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2373                 if (perf_guest_cbs->is_user_mode())
2374                         misc |= PERF_RECORD_MISC_GUEST_USER;
2375                 else
2376                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2377         } else {
2378                 if (user_mode(regs))
2379                         misc |= PERF_RECORD_MISC_USER;
2380                 else
2381                         misc |= PERF_RECORD_MISC_KERNEL;
2382         }
2383
2384         if (regs->flags & PERF_EFLAGS_EXACT)
2385                 misc |= PERF_RECORD_MISC_EXACT_IP;
2386
2387         return misc;
2388 }
2389
2390 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2391 {
2392         cap->version            = x86_pmu.version;
2393         cap->num_counters_gp    = x86_pmu.num_counters;
2394         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2395         cap->bit_width_gp       = x86_pmu.cntval_bits;
2396         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2397         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2398         cap->events_mask_len    = x86_pmu.events_mask_len;
2399 }
2400 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);