arch/x86/kernel/cpu/perf_event.c

   1 /*
   2  * Performance events x86 architecture code
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/capability.h>
  17 #include <linux/notifier.h>
  18 #include <linux/hardirq.h>
  19 #include <linux/kprobes.h>
  20 #include <linux/module.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/sched.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/cpu.h>
  26 #include <linux/bitops.h>
  27
  28 #include <asm/apic.h>
  29 #include <asm/stacktrace.h>
  30 #include <asm/nmi.h>
  31 #include <asm/compat.h>
  32 #include <asm/smp.h>
  33 #include <asm/alternative.h>
  34
  35 #include "perf_event.h"
  36
  37 #if 0
  38 #undef wrmsrl
  39 #define wrmsrl(msr, val)                                        \
  40 do {                                                            \
  41         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
  42                         (unsigned long)(val));                  \
  43         native_write_msr((msr), (u32)((u64)(val)),              \
  44                         (u32)((u64)(val) >> 32));               \
  45 } while (0)
  46 #endif
  47
  48 struct x86_pmu x86_pmu __read_mostly;
  49
  50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  51         .enabled = 1,
  52 };
  53
  54 u64 __read_mostly hw_cache_event_ids
  55                                 [PERF_COUNT_HW_CACHE_MAX]
  56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  58 u64 __read_mostly hw_cache_extra_regs
  59                                 [PERF_COUNT_HW_CACHE_MAX]
  60                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  61                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  62
  63 /*
  64  * Propagate event elapsed time into the generic event.
  65  * Can only be executed on the CPU where the event is active.
  66  * Returns the delta events processed.
  67  */
  68 u64 x86_perf_event_update(struct perf_event *event)
  69 {
  70         struct hw_perf_event *hwc = &event->hw;
  71         int shift = 64 - x86_pmu.cntval_bits;
  72         u64 prev_raw_count, new_raw_count;
  73         int idx = hwc->idx;
  74         s64 delta;
  75
  76         if (idx == X86_PMC_IDX_FIXED_BTS)
  77                 return 0;
  78
  79         /*
  80          * Careful: an NMI might modify the previous event value.
  81          *
  82          * Our tactic to handle this is to first atomically read and
  83          * exchange a new raw count - then add that new-prev delta
  84          * count to the generic event atomically:
  85          */
  86 again:
  87         prev_raw_count = local64_read(&hwc->prev_count);
  88         rdmsrl(hwc->event_base, new_raw_count);
  89
  90         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  91                                         new_raw_count) != prev_raw_count)
  92                 goto again;
  93
  94         /*
  95          * Now we have the new raw value and have updated the prev
  96          * timestamp already. We can now calculate the elapsed delta
  97          * (event-)time and add that to the generic event.
  98          *
  99          * Careful, not all hw sign-extends above the physical width
 100          * of the count.
 101          */
 102         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 103         delta >>= shift;
 104
 105         local64_add(delta, &event->count);
 106         local64_sub(delta, &hwc->period_left);
 107
 108         return new_raw_count;
 109 }
 110
 111 /*
 112  * Find and validate any extra registers to set up.
 113  */
 114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
 115 {
 116         struct hw_perf_event_extra *reg;
 117         struct extra_reg *er;
 118
 119         reg = &event->hw.extra_reg;
 120
 121         if (!x86_pmu.extra_regs)
 122                 return 0;
 123
 124         for (er = x86_pmu.extra_regs; er->msr; er++) {
 125                 if (er->event != (config & er->config_mask))
 126                         continue;
 127                 if (event->attr.config1 & ~er->valid_mask)
 128                         return -EINVAL;
 129
 130                 reg->idx = er->idx;
 131                 reg->config = event->attr.config1;
 132                 reg->reg = er->msr;
 133                 break;
 134         }
 135         return 0;
 136 }
 137
 138 static atomic_t active_events;
 139 static DEFINE_MUTEX(pmc_reserve_mutex);
 140
 141 #ifdef CONFIG_X86_LOCAL_APIC
 142
 143 static bool reserve_pmc_hardware(void)
 144 {
 145         int i;
 146
 147         for (i = 0; i < x86_pmu.num_counters; i++) {
 148                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 149                         goto perfctr_fail;
 150         }
 151
 152         for (i = 0; i < x86_pmu.num_counters; i++) {
 153                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 154                         goto eventsel_fail;
 155         }
 156
 157         return true;
 158
 159 eventsel_fail:
 160         for (i--; i >= 0; i--)
 161                 release_evntsel_nmi(x86_pmu_config_addr(i));
 162
 163         i = x86_pmu.num_counters;
 164
 165 perfctr_fail:
 166         for (i--; i >= 0; i--)
 167                 release_perfctr_nmi(x86_pmu_event_addr(i));
 168
 169         return false;
 170 }
 171
 172 static void release_pmc_hardware(void)
 173 {
 174         int i;
 175
 176         for (i = 0; i < x86_pmu.num_counters; i++) {
 177                 release_perfctr_nmi(x86_pmu_event_addr(i));
 178                 release_evntsel_nmi(x86_pmu_config_addr(i));
 179         }
 180 }
 181
 182 #else
 183
 184 static bool reserve_pmc_hardware(void) { return true; }
 185 static void release_pmc_hardware(void) {}
 186
 187 #endif
 188
 189 static bool check_hw_exists(void)
 190 {
 191         u64 val, val_new = 0;
 192         int i, reg, ret = 0;
 193
 194         /*
 195          * Check to see if the BIOS enabled any of the counters, if so
 196          * complain and bail.
 197          */
 198         for (i = 0; i < x86_pmu.num_counters; i++) {
 199                 reg = x86_pmu_config_addr(i);
 200                 ret = rdmsrl_safe(reg, &val);
 201                 if (ret)
 202                         goto msr_fail;
 203                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
 204                         goto bios_fail;
 205         }
 206
 207         if (x86_pmu.num_counters_fixed) {
 208                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 209                 ret = rdmsrl_safe(reg, &val);
 210                 if (ret)
 211                         goto msr_fail;
 212                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
 213                         if (val & (0x03 << i*4))
 214                                 goto bios_fail;
 215                 }
 216         }
 217
 218         /*
 219          * Now write a value and read it back to see if it matches,
 220          * this is needed to detect certain hardware emulators (qemu/kvm)
 221          * that don't trap on the MSR access and always return 0s.
 222          */
 223         val = 0xabcdUL;
 224         ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
 225         ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
 226         if (ret || val != val_new)
 227                 goto msr_fail;
 228
 229         return true;
 230
 231 bios_fail:
 232         /*
 233          * We still allow the PMU driver to operate:
 234          */
 235         printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
 236         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
 237
 238         return true;
 239
 240 msr_fail:
 241         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
 242
 243         return false;
 244 }
 245
 246 static void hw_perf_event_destroy(struct perf_event *event)
 247 {
 248         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
 249                 release_pmc_hardware();
 250                 release_ds_buffers();
 251                 mutex_unlock(&pmc_reserve_mutex);
 252         }
 253 }
 254
 255 static inline int x86_pmu_initialized(void)
 256 {
 257         return x86_pmu.handle_irq != NULL;
 258 }
 259
 260 static inline int
 261 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
 262 {
 263         struct perf_event_attr *attr = &event->attr;
 264         unsigned int cache_type, cache_op, cache_result;
 265         u64 config, val;
 266
 267         config = attr->config;
 268
 269         cache_type = (config >>  0) & 0xff;
 270         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 271                 return -EINVAL;
 272
 273         cache_op = (config >>  8) & 0xff;
 274         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 275                 return -EINVAL;
 276
 277         cache_result = (config >> 16) & 0xff;
 278         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 279                 return -EINVAL;
 280
 281         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
 282
 283         if (val == 0)
 284                 return -ENOENT;
 285
 286         if (val == -1)
 287                 return -EINVAL;
 288
 289         hwc->config |= val;
 290         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
 291         return x86_pmu_extra_regs(val, event);
 292 }
 293
 294 int x86_setup_perfctr(struct perf_event *event)
 295 {
 296         struct perf_event_attr *attr = &event->attr;
 297         struct hw_perf_event *hwc = &event->hw;
 298         u64 config;
 299
 300         if (!is_sampling_event(event)) {
 301                 hwc->sample_period = x86_pmu.max_period;
 302                 hwc->last_period = hwc->sample_period;
 303                 local64_set(&hwc->period_left, hwc->sample_period);
 304         } else {
 305                 /*
 306                  * If we have a PMU initialized but no APIC
 307                  * interrupts, we cannot sample hardware
 308                  * events (user-space has to fall back and
 309                  * sample via a hrtimer based software event):
 310                  */
 311                 if (!x86_pmu.apic)
 312                         return -EOPNOTSUPP;
 313         }
 314
 315         /*
 316          * Do not allow config1 (extended registers) to propagate,
 317          * there's no sane user-space generalization yet:
 318          */
 319         if (attr->type == PERF_TYPE_RAW)
 320                 return 0;
 321
 322         if (attr->type == PERF_TYPE_HW_CACHE)
 323                 return set_ext_hw_attr(hwc, event);
 324
 325         if (attr->config >= x86_pmu.max_events)
 326                 return -EINVAL;
 327
 328         /*
 329          * The generic map:
 330          */
 331         config = x86_pmu.event_map(attr->config);
 332
 333         if (config == 0)
 334                 return -ENOENT;
 335
 336         if (config == -1LL)
 337                 return -EINVAL;
 338
 339         /*
 340          * Branch tracing:
 341          */
 342         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 343             !attr->freq && hwc->sample_period == 1) {
 344                 /* BTS is not supported by this architecture. */
 345                 if (!x86_pmu.bts_active)
 346                         return -EOPNOTSUPP;
 347
 348                 /* BTS is currently only allowed for user-mode. */
 349                 if (!attr->exclude_kernel)
 350                         return -EOPNOTSUPP;
 351         }
 352
 353         hwc->config |= config;
 354
 355         return 0;
 356 }
 357
 358 int x86_pmu_hw_config(struct perf_event *event)
 359 {
 360         if (event->attr.precise_ip) {
 361                 int precise = 0;
 362
 363                 /* Support for constant skid */
 364                 if (x86_pmu.pebs_active) {
 365                         precise++;
 366
 367                         /* Support for IP fixup */
 368                         if (x86_pmu.lbr_nr)
 369                                 precise++;
 370                 }
 371
 372                 if (event->attr.precise_ip > precise)
 373                         return -EOPNOTSUPP;
 374         }
 375
 376         /*
 377          * Generate PMC IRQs:
 378          * (keep 'enabled' bit clear for now)
 379          */
 380         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
 381
 382         /*
 383          * Count user and OS events unless requested not to
 384          */
 385         if (!event->attr.exclude_user)
 386                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
 387         if (!event->attr.exclude_kernel)
 388                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
 389
 390         if (event->attr.type == PERF_TYPE_RAW)
 391                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
 392
 393         return x86_setup_perfctr(event);
 394 }
 395
 396 /*
 397  * Setup the hardware configuration for a given attr_type
 398  */
 399 static int __x86_pmu_event_init(struct perf_event *event)
 400 {
 401         int err;
 402
 403         if (!x86_pmu_initialized())
 404                 return -ENODEV;
 405
 406         err = 0;
 407         if (!atomic_inc_not_zero(&active_events)) {
 408                 mutex_lock(&pmc_reserve_mutex);
 409                 if (atomic_read(&active_events) == 0) {
 410                         if (!reserve_pmc_hardware())
 411                                 err = -EBUSY;
 412                         else
 413                                 reserve_ds_buffers();
 414                 }
 415                 if (!err)
 416                         atomic_inc(&active_events);
 417                 mutex_unlock(&pmc_reserve_mutex);
 418         }
 419         if (err)
 420                 return err;
 421
 422         event->destroy = hw_perf_event_destroy;
 423
 424         event->hw.idx = -1;
 425         event->hw.last_cpu = -1;
 426         event->hw.last_tag = ~0ULL;
 427
 428         /* mark unused */
 429         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 430
 431         return x86_pmu.hw_config(event);
 432 }
 433
 434 void x86_pmu_disable_all(void)
 435 {
 436         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 437         int idx;
 438
 439         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 440                 u64 val;
 441
 442                 if (!test_bit(idx, cpuc->active_mask))
 443                         continue;
 444                 rdmsrl(x86_pmu_config_addr(idx), val);
 445                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
 446                         continue;
 447                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
 448                 wrmsrl(x86_pmu_config_addr(idx), val);
 449         }
 450 }
 451
 452 static void x86_pmu_disable(struct pmu *pmu)
 453 {
 454         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 455
 456         if (!x86_pmu_initialized())
 457                 return;
 458
 459         if (!cpuc->enabled)
 460                 return;
 461
 462         cpuc->n_added = 0;
 463         cpuc->enabled = 0;
 464         barrier();
 465
 466         x86_pmu.disable_all();
 467 }
 468
 469 void x86_pmu_enable_all(int added)
 470 {
 471         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 472         int idx;
 473
 474         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 475                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
 476
 477                 if (!test_bit(idx, cpuc->active_mask))
 478                         continue;
 479
 480                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 481         }
 482 }
 483
 484 static struct pmu pmu;
 485
 486 static inline int is_x86_event(struct perf_event *event)
 487 {
 488         return event->pmu == &pmu;
 489 }
 490
 491 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 492 {
 493         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
 494         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 495         int i, j, w, wmax, num = 0;
 496         struct hw_perf_event *hwc;
 497
 498         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 499
 500         for (i = 0; i < n; i++) {
 501                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
 502                 constraints[i] = c;
 503         }
 504
 505         /*
 506          * fastpath, try to reuse previous register
 507          */
 508         for (i = 0; i < n; i++) {
 509                 hwc = &cpuc->event_list[i]->hw;
 510                 c = constraints[i];
 511
 512                 /* never assigned */
 513                 if (hwc->idx == -1)
 514                         break;
 515
 516                 /* constraint still honored */
 517                 if (!test_bit(hwc->idx, c->idxmsk))
 518                         break;
 519
 520                 /* not already used */
 521                 if (test_bit(hwc->idx, used_mask))
 522                         break;
 523
 524                 __set_bit(hwc->idx, used_mask);
 525                 if (assign)
 526                         assign[i] = hwc->idx;
 527         }
 528         if (i == n)
 529                 goto done;
 530
 531         /*
 532          * begin slow path
 533          */
 534
 535         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 536
 537         /*
 538          * weight = number of possible counters
 539          *
 540          * 1    = most constrained, only works on one counter
 541          * wmax = least constrained, works on any counter
 542          *
 543          * assign events to counters starting with most
 544          * constrained events.
 545          */
 546         wmax = x86_pmu.num_counters;
 547
 548         /*
 549          * when fixed event counters are present,
 550          * wmax is incremented by 1 to account
 551          * for one more choice
 552          */
 553         if (x86_pmu.num_counters_fixed)
 554                 wmax++;
 555
 556         for (w = 1, num = n; num && w <= wmax; w++) {
 557                 /* for each event */
 558                 for (i = 0; num && i < n; i++) {
 559                         c = constraints[i];
 560                         hwc = &cpuc->event_list[i]->hw;
 561
 562                         if (c->weight != w)
 563                                 continue;
 564
 565                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
 566                                 if (!test_bit(j, used_mask))
 567                                         break;
 568                         }
 569
 570                         if (j == X86_PMC_IDX_MAX)
 571                                 break;
 572
 573                         __set_bit(j, used_mask);
 574
 575                         if (assign)
 576                                 assign[i] = j;
 577                         num--;
 578                 }
 579         }
 580 done:
 581         /*
 582          * scheduling failed or is just a simulation,
 583          * free resources if necessary
 584          */
 585         if (!assign || num) {
 586                 for (i = 0; i < n; i++) {
 587                         if (x86_pmu.put_event_constraints)
 588                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
 589                 }
 590         }
 591         return num ? -ENOSPC : 0;
 592 }
 593
 594 /*
 595  * dogrp: true if must collect siblings events (group)
 596  * returns total number of events and error code
 597  */
 598 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 599 {
 600         struct perf_event *event;
 601         int n, max_count;
 602
 603         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
 604
 605         /* current number of events already accepted */
 606         n = cpuc->n_events;
 607
 608         if (is_x86_event(leader)) {
 609                 if (n >= max_count)
 610                         return -ENOSPC;
 611                 cpuc->event_list[n] = leader;
 612                 n++;
 613         }
 614         if (!dogrp)
 615                 return n;
 616
 617         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 618                 if (!is_x86_event(event) ||
 619                     event->state <= PERF_EVENT_STATE_OFF)
 620                         continue;
 621
 622                 if (n >= max_count)
 623                         return -ENOSPC;
 624
 625                 cpuc->event_list[n] = event;
 626                 n++;
 627         }
 628         return n;
 629 }
 630
 631 static inline void x86_assign_hw_event(struct perf_event *event,
 632                                 struct cpu_hw_events *cpuc, int i)
 633 {
 634         struct hw_perf_event *hwc = &event->hw;
 635
 636         hwc->idx = cpuc->assign[i];
 637         hwc->last_cpu = smp_processor_id();
 638         hwc->last_tag = ++cpuc->tags[i];
 639
 640         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
 641                 hwc->config_base = 0;
 642                 hwc->event_base = 0;
 643         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
 644                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
 645                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
 646         } else {
 647                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
 648                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
 649         }
 650 }
 651
 652 static inline int match_prev_assignment(struct hw_perf_event *hwc,
 653                                         struct cpu_hw_events *cpuc,
 654                                         int i)
 655 {
 656         return hwc->idx == cpuc->assign[i] &&
 657                 hwc->last_cpu == smp_processor_id() &&
 658                 hwc->last_tag == cpuc->tags[i];
 659 }
 660
 661 static void x86_pmu_start(struct perf_event *event, int flags);
 662
 663 static void x86_pmu_enable(struct pmu *pmu)
 664 {
 665         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 666         struct perf_event *event;
 667         struct hw_perf_event *hwc;
 668         int i, added = cpuc->n_added;
 669
 670         if (!x86_pmu_initialized())
 671                 return;
 672
 673         if (cpuc->enabled)
 674                 return;
 675
 676         if (cpuc->n_added) {
 677                 int n_running = cpuc->n_events - cpuc->n_added;
 678                 /*
 679                  * apply assignment obtained either from
 680                  * hw_perf_group_sched_in() or x86_pmu_enable()
 681                  *
 682                  * step1: save events moving to new counters
 683                  * step2: reprogram moved events into new counters
 684                  */
 685                 for (i = 0; i < n_running; i++) {
 686                         event = cpuc->event_list[i];
 687                         hwc = &event->hw;
 688
 689                         /*
 690                          * we can avoid reprogramming counter if:
 691                          * - assigned same counter as last time
 692                          * - running on same CPU as last time
 693                          * - no other event has used the counter since
 694                          */
 695                         if (hwc->idx == -1 ||
 696                             match_prev_assignment(hwc, cpuc, i))
 697                                 continue;
 698
 699                         /*
 700                          * Ensure we don't accidentally enable a stopped
 701                          * counter simply because we rescheduled.
 702                          */
 703                         if (hwc->state & PERF_HES_STOPPED)
 704                                 hwc->state |= PERF_HES_ARCH;
 705
 706                         x86_pmu_stop(event, PERF_EF_UPDATE);
 707                 }
 708
 709                 for (i = 0; i < cpuc->n_events; i++) {
 710                         event = cpuc->event_list[i];
 711                         hwc = &event->hw;
 712
 713                         if (!match_prev_assignment(hwc, cpuc, i))
 714                                 x86_assign_hw_event(event, cpuc, i);
 715                         else if (i < n_running)
 716                                 continue;
 717
 718                         if (hwc->state & PERF_HES_ARCH)
 719                                 continue;
 720
 721                         x86_pmu_start(event, PERF_EF_RELOAD);
 722                 }
 723                 cpuc->n_added = 0;
 724                 perf_events_lapic_init();
 725         }
 726
 727         cpuc->enabled = 1;
 728         barrier();
 729
 730         x86_pmu.enable_all(added);
 731 }
 732
 733 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 734
 735 /*
 736  * Set the next IRQ period, based on the hwc->period_left value.
 737  * To be called with the event disabled in hw:
 738  */
 739 int x86_perf_event_set_period(struct perf_event *event)
 740 {
 741         struct hw_perf_event *hwc = &event->hw;
 742         s64 left = local64_read(&hwc->period_left);
 743         s64 period = hwc->sample_period;
 744         int ret = 0, idx = hwc->idx;
 745
 746         if (idx == X86_PMC_IDX_FIXED_BTS)
 747                 return 0;
 748
 749         /*
 750          * If we are way outside a reasonable range then just skip forward:
 751          */
 752         if (unlikely(left <= -period)) {
 753                 left = period;
 754                 local64_set(&hwc->period_left, left);
 755                 hwc->last_period = period;
 756                 ret = 1;
 757         }
 758
 759         if (unlikely(left <= 0)) {
 760                 left += period;
 761                 local64_set(&hwc->period_left, left);
 762                 hwc->last_period = period;
 763                 ret = 1;
 764         }
 765         /*
 766          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
 767          */
 768         if (unlikely(left < 2))
 769                 left = 2;
 770
 771         if (left > x86_pmu.max_period)
 772                 left = x86_pmu.max_period;
 773
 774         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
 775
 776         /*
 777          * The hw event starts counting from this event offset,
 778          * mark it to be able to extra future deltas:
 779          */
 780         local64_set(&hwc->prev_count, (u64)-left);
 781
 782         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
 783
 784         /*
 785          * Due to erratum on certan cpu we need
 786          * a second write to be sure the register
 787          * is updated properly
 788          */
 789         if (x86_pmu.perfctr_second_write) {
 790                 wrmsrl(hwc->event_base,
 791                         (u64)(-left) & x86_pmu.cntval_mask);
 792         }
 793
 794         perf_event_update_userpage(event);
 795
 796         return ret;
 797 }
 798
 799 void x86_pmu_enable_event(struct perf_event *event)
 800 {
 801         if (__this_cpu_read(cpu_hw_events.enabled))
 802                 __x86_pmu_enable_event(&event->hw,
 803                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 804 }
 805
 806 /*
 807  * Add a single event to the PMU.
 808  *
 809  * The event is added to the group of enabled events
 810  * but only if it can be scehduled with existing events.
 811  */
 812 static int x86_pmu_add(struct perf_event *event, int flags)
 813 {
 814         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 815         struct hw_perf_event *hwc;
 816         int assign[X86_PMC_IDX_MAX];
 817         int n, n0, ret;
 818
 819         hwc = &event->hw;
 820
 821         perf_pmu_disable(event->pmu);
 822         n0 = cpuc->n_events;
 823         ret = n = collect_events(cpuc, event, false);
 824         if (ret < 0)
 825                 goto out;
 826
 827         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 828         if (!(flags & PERF_EF_START))
 829                 hwc->state |= PERF_HES_ARCH;
 830
 831         /*
 832          * If group events scheduling transaction was started,
 833          * skip the schedulability test here, it will be performed
 834          * at commit time (->commit_txn) as a whole
 835          */
 836         if (cpuc->group_flag & PERF_EVENT_TXN)
 837                 goto done_collect;
 838
 839         ret = x86_pmu.schedule_events(cpuc, n, assign);
 840         if (ret)
 841                 goto out;
 842         /*
 843          * copy new assignment, now we know it is possible
 844          * will be used by hw_perf_enable()
 845          */
 846         memcpy(cpuc->assign, assign, n*sizeof(int));
 847
 848 done_collect:
 849         cpuc->n_events = n;
 850         cpuc->n_added += n - n0;
 851         cpuc->n_txn += n - n0;
 852
 853         ret = 0;
 854 out:
 855         perf_pmu_enable(event->pmu);
 856         return ret;
 857 }
 858
 859 static void x86_pmu_start(struct perf_event *event, int flags)
 860 {
 861         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 862         int idx = event->hw.idx;
 863
 864         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
 865                 return;
 866
 867         if (WARN_ON_ONCE(idx == -1))
 868                 return;
 869
 870         if (flags & PERF_EF_RELOAD) {
 871                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
 872                 x86_perf_event_set_period(event);
 873         }
 874
 875         event->hw.state = 0;
 876
 877         cpuc->events[idx] = event;
 878         __set_bit(idx, cpuc->active_mask);
 879         __set_bit(idx, cpuc->running);
 880         x86_pmu.enable(event);
 881         perf_event_update_userpage(event);
 882 }
 883
 884 void perf_event_print_debug(void)
 885 {
 886         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 887         u64 pebs;
 888         struct cpu_hw_events *cpuc;
 889         unsigned long flags;
 890         int cpu, idx;
 891
 892         if (!x86_pmu.num_counters)
 893                 return;
 894
 895         local_irq_save(flags);
 896
 897         cpu = smp_processor_id();
 898         cpuc = &per_cpu(cpu_hw_events, cpu);
 899
 900         if (x86_pmu.version >= 2) {
 901                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 902                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 903                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
 904                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
 905                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
 906
 907                 pr_info("\n");
 908                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
 909                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
 910                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
 911                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
 912                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
 913         }
 914         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
 915
 916         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 917                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
 918                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
 919
 920                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
 921
 922                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
 923                         cpu, idx, pmc_ctrl);
 924                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
 925                         cpu, idx, pmc_count);
 926                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
 927                         cpu, idx, prev_left);
 928         }
 929         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
 930                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
 931
 932                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
 933                         cpu, idx, pmc_count);
 934         }
 935         local_irq_restore(flags);
 936 }
 937
 938 void x86_pmu_stop(struct perf_event *event, int flags)
 939 {
 940         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 941         struct hw_perf_event *hwc = &event->hw;
 942
 943         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
 944                 x86_pmu.disable(event);
 945                 cpuc->events[hwc->idx] = NULL;
 946                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 947                 hwc->state |= PERF_HES_STOPPED;
 948         }
 949
 950         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
 951                 /*
 952                  * Drain the remaining delta count out of a event
 953                  * that we are disabling:
 954                  */
 955                 x86_perf_event_update(event);
 956                 hwc->state |= PERF_HES_UPTODATE;
 957         }
 958 }
 959
 960 static void x86_pmu_del(struct perf_event *event, int flags)
 961 {
 962         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 963         int i;
 964
 965         /*
 966          * If we're called during a txn, we don't need to do anything.
 967          * The events never got scheduled and ->cancel_txn will truncate
 968          * the event_list.
 969          */
 970         if (cpuc->group_flag & PERF_EVENT_TXN)
 971                 return;
 972
 973         x86_pmu_stop(event, PERF_EF_UPDATE);
 974
 975         for (i = 0; i < cpuc->n_events; i++) {
 976                 if (event == cpuc->event_list[i]) {
 977
 978                         if (x86_pmu.put_event_constraints)
 979                                 x86_pmu.put_event_constraints(cpuc, event);
 980
 981                         while (++i < cpuc->n_events)
 982                                 cpuc->event_list[i-1] = cpuc->event_list[i];
 983
 984                         --cpuc->n_events;
 985                         break;
 986                 }
 987         }
 988         perf_event_update_userpage(event);
 989 }
 990
 991 int x86_pmu_handle_irq(struct pt_regs *regs)
 992 {
 993         struct perf_sample_data data;
 994         struct cpu_hw_events *cpuc;
 995         struct perf_event *event;
 996         int idx, handled = 0;
 997         u64 val;
 998
 999         perf_sample_data_init(&data, 0);
1000
1001         cpuc = &__get_cpu_var(cpu_hw_events);
1002
1003         /*
1004          * Some chipsets need to unmask the LVTPC in a particular spot
1005          * inside the nmi handler.  As a result, the unmasking was pushed
1006          * into all the nmi handlers.
1007          *
1008          * This generic handler doesn't seem to have any issues where the
1009          * unmasking occurs so it was left at the top.
1010          */
1011         apic_write(APIC_LVTPC, APIC_DM_NMI);
1012
1013         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1014                 if (!test_bit(idx, cpuc->active_mask)) {
1015                         /*
1016                          * Though we deactivated the counter some cpus
1017                          * might still deliver spurious interrupts still
1018                          * in flight. Catch them:
1019                          */
1020                         if (__test_and_clear_bit(idx, cpuc->running))
1021                                 handled++;
1022                         continue;
1023                 }
1024
1025                 event = cpuc->events[idx];
1026
1027                 val = x86_perf_event_update(event);
1028                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1029                         continue;
1030
1031                 /*
1032                  * event overflow
1033                  */
1034                 handled++;
1035                 data.period     = event->hw.last_period;
1036
1037                 if (!x86_perf_event_set_period(event))
1038                         continue;
1039
1040                 if (perf_event_overflow(event, &data, regs))
1041                         x86_pmu_stop(event, 0);
1042         }
1043
1044         if (handled)
1045                 inc_irq_stat(apic_perf_irqs);
1046
1047         return handled;
1048 }
1049
1050 void perf_events_lapic_init(void)
1051 {
1052         if (!x86_pmu.apic || !x86_pmu_initialized())
1053                 return;
1054
1055         /*
1056          * Always use NMI for PMU
1057          */
1058         apic_write(APIC_LVTPC, APIC_DM_NMI);
1059 }
1060
1061 struct pmu_nmi_state {
1062         unsigned int    marked;
1063         int             handled;
1064 };
1065
1066 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1067
1068 static int __kprobes
1069 perf_event_nmi_handler(struct notifier_block *self,
1070                          unsigned long cmd, void *__args)
1071 {
1072         struct die_args *args = __args;
1073         unsigned int this_nmi;
1074         int handled;
1075
1076         if (!atomic_read(&active_events))
1077                 return NOTIFY_DONE;
1078
1079         switch (cmd) {
1080         case DIE_NMI:
1081                 break;
1082         case DIE_NMIUNKNOWN:
1083                 this_nmi = percpu_read(irq_stat.__nmi_count);
1084                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1085                         /* let the kernel handle the unknown nmi */
1086                         return NOTIFY_DONE;
1087                 /*
1088                  * This one is a PMU back-to-back nmi. Two events
1089                  * trigger 'simultaneously' raising two back-to-back
1090                  * NMIs. If the first NMI handles both, the latter
1091                  * will be empty and daze the CPU. So, we drop it to
1092                  * avoid false-positive 'unknown nmi' messages.
1093                  */
1094                 return NOTIFY_STOP;
1095         default:
1096                 return NOTIFY_DONE;
1097         }
1098
1099         handled = x86_pmu.handle_irq(args->regs);
1100         if (!handled)
1101                 return NOTIFY_DONE;
1102
1103         this_nmi = percpu_read(irq_stat.__nmi_count);
1104         if ((handled > 1) ||
1105                 /* the next nmi could be a back-to-back nmi */
1106             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1107              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1108                 /*
1109                  * We could have two subsequent back-to-back nmis: The
1110                  * first handles more than one counter, the 2nd
1111                  * handles only one counter and the 3rd handles no
1112                  * counter.
1113                  *
1114                  * This is the 2nd nmi because the previous was
1115                  * handling more than one counter. We will mark the
1116                  * next (3rd) and then drop it if unhandled.
1117                  */
1118                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1119                 __this_cpu_write(pmu_nmi.handled, handled);
1120         }
1121
1122         return NOTIFY_STOP;
1123 }
1124
1125 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1126         .notifier_call          = perf_event_nmi_handler,
1127         .next                   = NULL,
1128         .priority               = NMI_LOCAL_LOW_PRIOR,
1129 };
1130
1131 struct event_constraint emptyconstraint;
1132 struct event_constraint unconstrained;
1133
1134 static int __cpuinit
1135 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1136 {
1137         unsigned int cpu = (long)hcpu;
1138         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1139         int ret = NOTIFY_OK;
1140
1141         switch (action & ~CPU_TASKS_FROZEN) {
1142         case CPU_UP_PREPARE:
1143                 cpuc->kfree_on_online = NULL;
1144                 if (x86_pmu.cpu_prepare)
1145                         ret = x86_pmu.cpu_prepare(cpu);
1146                 break;
1147
1148         case CPU_STARTING:
1149                 if (x86_pmu.cpu_starting)
1150                         x86_pmu.cpu_starting(cpu);
1151                 break;
1152
1153         case CPU_ONLINE:
1154                 kfree(cpuc->kfree_on_online);
1155                 break;
1156
1157         case CPU_DYING:
1158                 if (x86_pmu.cpu_dying)
1159                         x86_pmu.cpu_dying(cpu);
1160                 break;
1161
1162         case CPU_UP_CANCELED:
1163         case CPU_DEAD:
1164                 if (x86_pmu.cpu_dead)
1165                         x86_pmu.cpu_dead(cpu);
1166                 break;
1167
1168         default:
1169                 break;
1170         }
1171
1172         return ret;
1173 }
1174
1175 static void __init pmu_check_apic(void)
1176 {
1177         if (cpu_has_apic)
1178                 return;
1179
1180         x86_pmu.apic = 0;
1181         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1182         pr_info("no hardware sampling interrupt available.\n");
1183 }
1184
1185 static int __init init_hw_perf_events(void)
1186 {
1187         struct event_constraint *c;
1188         int err;
1189
1190         pr_info("Performance Events: ");
1191
1192         switch (boot_cpu_data.x86_vendor) {
1193         case X86_VENDOR_INTEL:
1194                 err = intel_pmu_init();
1195                 break;
1196         case X86_VENDOR_AMD:
1197                 err = amd_pmu_init();
1198                 break;
1199         default:
1200                 return 0;
1201         }
1202         if (err != 0) {
1203                 pr_cont("no PMU driver, software events only.\n");
1204                 return 0;
1205         }
1206
1207         pmu_check_apic();
1208
1209         /* sanity check that the hardware exists or is emulated */
1210         if (!check_hw_exists())
1211                 return 0;
1212
1213         pr_cont("%s PMU driver.\n", x86_pmu.name);
1214
1215         if (x86_pmu.quirks)
1216                 x86_pmu.quirks();
1217
1218         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1219                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1220                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1221                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1222         }
1223         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1224
1225         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1226                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1227                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1228                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1229         }
1230
1231         x86_pmu.intel_ctrl |=
1232                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1233
1234         perf_events_lapic_init();
1235         register_die_notifier(&perf_event_nmi_notifier);
1236
1237         unconstrained = (struct event_constraint)
1238                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1239                                    0, x86_pmu.num_counters);
1240
1241         if (x86_pmu.event_constraints) {
1242                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1243                         if (c->cmask != X86_RAW_EVENT_MASK)
1244                                 continue;
1245
1246                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1247                         c->weight += x86_pmu.num_counters;
1248                 }
1249         }
1250
1251         pr_info("... version:                %d\n",     x86_pmu.version);
1252         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1253         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1254         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1255         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1256         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1257         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1258
1259         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1260         perf_cpu_notifier(x86_pmu_notifier);
1261
1262         return 0;
1263 }
1264 early_initcall(init_hw_perf_events);
1265
1266 static inline void x86_pmu_read(struct perf_event *event)
1267 {
1268         x86_perf_event_update(event);
1269 }
1270
1271 /*
1272  * Start group events scheduling transaction
1273  * Set the flag to make pmu::enable() not perform the
1274  * schedulability test, it will be performed at commit time
1275  */
1276 static void x86_pmu_start_txn(struct pmu *pmu)
1277 {
1278         perf_pmu_disable(pmu);
1279         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1280         __this_cpu_write(cpu_hw_events.n_txn, 0);
1281 }
1282
1283 /*
1284  * Stop group events scheduling transaction
1285  * Clear the flag and pmu::enable() will perform the
1286  * schedulability test.
1287  */
1288 static void x86_pmu_cancel_txn(struct pmu *pmu)
1289 {
1290         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1291         /*
1292          * Truncate the collected events.
1293          */
1294         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1295         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1296         perf_pmu_enable(pmu);
1297 }
1298
1299 /*
1300  * Commit group events scheduling transaction
1301  * Perform the group schedulability test as a whole
1302  * Return 0 if success
1303  */
1304 static int x86_pmu_commit_txn(struct pmu *pmu)
1305 {
1306         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1307         int assign[X86_PMC_IDX_MAX];
1308         int n, ret;
1309
1310         n = cpuc->n_events;
1311
1312         if (!x86_pmu_initialized())
1313                 return -EAGAIN;
1314
1315         ret = x86_pmu.schedule_events(cpuc, n, assign);
1316         if (ret)
1317                 return ret;
1318
1319         /*
1320          * copy new assignment, now we know it is possible
1321          * will be used by hw_perf_enable()
1322          */
1323         memcpy(cpuc->assign, assign, n*sizeof(int));
1324
1325         cpuc->group_flag &= ~PERF_EVENT_TXN;
1326         perf_pmu_enable(pmu);
1327         return 0;
1328 }
1329 /*
1330  * a fake_cpuc is used to validate event groups. Due to
1331  * the extra reg logic, we need to also allocate a fake
1332  * per_core and per_cpu structure. Otherwise, group events
1333  * using extra reg may conflict without the kernel being
1334  * able to catch this when the last event gets added to
1335  * the group.
1336  */
1337 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1338 {
1339         kfree(cpuc->shared_regs);
1340         kfree(cpuc);
1341 }
1342
1343 static struct cpu_hw_events *allocate_fake_cpuc(void)
1344 {
1345         struct cpu_hw_events *cpuc;
1346         int cpu = raw_smp_processor_id();
1347
1348         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1349         if (!cpuc)
1350                 return ERR_PTR(-ENOMEM);
1351
1352         /* only needed, if we have extra_regs */
1353         if (x86_pmu.extra_regs) {
1354                 cpuc->shared_regs = allocate_shared_regs(cpu);
1355                 if (!cpuc->shared_regs)
1356                         goto error;
1357         }
1358         return cpuc;
1359 error:
1360         free_fake_cpuc(cpuc);
1361         return ERR_PTR(-ENOMEM);
1362 }
1363
1364 /*
1365  * validate that we can schedule this event
1366  */
1367 static int validate_event(struct perf_event *event)
1368 {
1369         struct cpu_hw_events *fake_cpuc;
1370         struct event_constraint *c;
1371         int ret = 0;
1372
1373         fake_cpuc = allocate_fake_cpuc();
1374         if (IS_ERR(fake_cpuc))
1375                 return PTR_ERR(fake_cpuc);
1376
1377         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1378
1379         if (!c || !c->weight)
1380                 ret = -ENOSPC;
1381
1382         if (x86_pmu.put_event_constraints)
1383                 x86_pmu.put_event_constraints(fake_cpuc, event);
1384
1385         free_fake_cpuc(fake_cpuc);
1386
1387         return ret;
1388 }
1389
1390 /*
1391  * validate a single event group
1392  *
1393  * validation include:
1394  *      - check events are compatible which each other
1395  *      - events do not compete for the same counter
1396  *      - number of events <= number of counters
1397  *
1398  * validation ensures the group can be loaded onto the
1399  * PMU if it was the only group available.
1400  */
1401 static int validate_group(struct perf_event *event)
1402 {
1403         struct perf_event *leader = event->group_leader;
1404         struct cpu_hw_events *fake_cpuc;
1405         int ret = -ENOSPC, n;
1406
1407         fake_cpuc = allocate_fake_cpuc();
1408         if (IS_ERR(fake_cpuc))
1409                 return PTR_ERR(fake_cpuc);
1410         /*
1411          * the event is not yet connected with its
1412          * siblings therefore we must first collect
1413          * existing siblings, then add the new event
1414          * before we can simulate the scheduling
1415          */
1416         n = collect_events(fake_cpuc, leader, true);
1417         if (n < 0)
1418                 goto out;
1419
1420         fake_cpuc->n_events = n;
1421         n = collect_events(fake_cpuc, event, false);
1422         if (n < 0)
1423                 goto out;
1424
1425         fake_cpuc->n_events = n;
1426
1427         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1428
1429 out:
1430         free_fake_cpuc(fake_cpuc);
1431         return ret;
1432 }
1433
1434 static int x86_pmu_event_init(struct perf_event *event)
1435 {
1436         struct pmu *tmp;
1437         int err;
1438
1439         switch (event->attr.type) {
1440         case PERF_TYPE_RAW:
1441         case PERF_TYPE_HARDWARE:
1442         case PERF_TYPE_HW_CACHE:
1443                 break;
1444
1445         default:
1446                 return -ENOENT;
1447         }
1448
1449         err = __x86_pmu_event_init(event);
1450         if (!err) {
1451                 /*
1452                  * we temporarily connect event to its pmu
1453                  * such that validate_group() can classify
1454                  * it as an x86 event using is_x86_event()
1455                  */
1456                 tmp = event->pmu;
1457                 event->pmu = &pmu;
1458
1459                 if (event->group_leader != event)
1460                         err = validate_group(event);
1461                 else
1462                         err = validate_event(event);
1463
1464                 event->pmu = tmp;
1465         }
1466         if (err) {
1467                 if (event->destroy)
1468                         event->destroy(event);
1469         }
1470
1471         return err;
1472 }
1473
1474 static struct pmu pmu = {
1475         .pmu_enable     = x86_pmu_enable,
1476         .pmu_disable    = x86_pmu_disable,
1477
1478         .event_init     = x86_pmu_event_init,
1479
1480         .add            = x86_pmu_add,
1481         .del            = x86_pmu_del,
1482         .start          = x86_pmu_start,
1483         .stop           = x86_pmu_stop,
1484         .read           = x86_pmu_read,
1485
1486         .start_txn      = x86_pmu_start_txn,
1487         .cancel_txn     = x86_pmu_cancel_txn,
1488         .commit_txn     = x86_pmu_commit_txn,
1489 };
1490
1491 /*
1492  * callchain support
1493  */
1494
1495 static int backtrace_stack(void *data, char *name)
1496 {
1497         return 0;
1498 }
1499
1500 static void backtrace_address(void *data, unsigned long addr, int reliable)
1501 {
1502         struct perf_callchain_entry *entry = data;
1503
1504         perf_callchain_store(entry, addr);
1505 }
1506
1507 static const struct stacktrace_ops backtrace_ops = {
1508         .stack                  = backtrace_stack,
1509         .address                = backtrace_address,
1510         .walk_stack             = print_context_stack_bp,
1511 };
1512
1513 void
1514 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1515 {
1516         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1517                 /* TODO: We don't support guest os callchain now */
1518                 return;
1519         }
1520
1521         perf_callchain_store(entry, regs->ip);
1522
1523         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1524 }
1525
1526 #ifdef CONFIG_COMPAT
1527 static inline int
1528 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1529 {
1530         /* 32-bit process in 64-bit kernel. */
1531         struct stack_frame_ia32 frame;
1532         const void __user *fp;
1533
1534         if (!test_thread_flag(TIF_IA32))
1535                 return 0;
1536
1537         fp = compat_ptr(regs->bp);
1538         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1539                 unsigned long bytes;
1540                 frame.next_frame     = 0;
1541                 frame.return_address = 0;
1542
1543                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1544                 if (bytes != sizeof(frame))
1545                         break;
1546
1547                 if (fp < compat_ptr(regs->sp))
1548                         break;
1549
1550                 perf_callchain_store(entry, frame.return_address);
1551                 fp = compat_ptr(frame.next_frame);
1552         }
1553         return 1;
1554 }
1555 #else
1556 static inline int
1557 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1558 {
1559     return 0;
1560 }
1561 #endif
1562
1563 void
1564 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1565 {
1566         struct stack_frame frame;
1567         const void __user *fp;
1568
1569         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1570                 /* TODO: We don't support guest os callchain now */
1571                 return;
1572         }
1573
1574         fp = (void __user *)regs->bp;
1575
1576         perf_callchain_store(entry, regs->ip);
1577
1578         if (!current->mm)
1579                 return;
1580
1581         if (perf_callchain_user32(regs, entry))
1582                 return;
1583
1584         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1585                 unsigned long bytes;
1586                 frame.next_frame             = NULL;
1587                 frame.return_address = 0;
1588
1589                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1590                 if (bytes != sizeof(frame))
1591                         break;
1592
1593                 if ((unsigned long)fp < regs->sp)
1594                         break;
1595
1596                 perf_callchain_store(entry, frame.return_address);
1597                 fp = frame.next_frame;
1598         }
1599 }
1600
1601 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1602 {
1603         unsigned long ip;
1604
1605         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1606                 ip = perf_guest_cbs->get_guest_ip();
1607         else
1608                 ip = instruction_pointer(regs);
1609
1610         return ip;
1611 }
1612
1613 unsigned long perf_misc_flags(struct pt_regs *regs)
1614 {
1615         int misc = 0;
1616
1617         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1618                 if (perf_guest_cbs->is_user_mode())
1619                         misc |= PERF_RECORD_MISC_GUEST_USER;
1620                 else
1621                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1622         } else {
1623                 if (user_mode(regs))
1624                         misc |= PERF_RECORD_MISC_USER;
1625                 else
1626                         misc |= PERF_RECORD_MISC_KERNEL;
1627         }
1628
1629         if (regs->flags & PERF_EFLAGS_EXACT)
1630                 misc |= PERF_RECORD_MISC_EXACT_IP;
1631
1632         return misc;
1633 }