arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        (PAGE_SIZE << 4)
  15 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  16
  17 /*
  18  * pebs_record_32 for p4 and core not supported
  19
  20 struct pebs_record_32 {
  21         u32 flags, ip;
  22         u32 ax, bc, cx, dx;
  23         u32 si, di, bp, sp;
  24 };
  25
  26  */
  27
  28 union intel_x86_pebs_dse {
  29         u64 val;
  30         struct {
  31                 unsigned int ld_dse:4;
  32                 unsigned int ld_stlb_miss:1;
  33                 unsigned int ld_locked:1;
  34                 unsigned int ld_reserved:26;
  35         };
  36         struct {
  37                 unsigned int st_l1d_hit:1;
  38                 unsigned int st_reserved1:3;
  39                 unsigned int st_stlb_miss:1;
  40                 unsigned int st_locked:1;
  41                 unsigned int st_reserved2:26;
  42         };
  43 };
  44
  45
  46 /*
  47  * Map PEBS Load Latency Data Source encodings to generic
  48  * memory data source information
  49  */
  50 #define P(a, b) PERF_MEM_S(a, b)
  51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  53
  54 static const u64 pebs_data_source[] = {
  55         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  56         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  57         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  58         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  62         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  64         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  65         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  66         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  67         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  68         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  69         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  70         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  71 };
  72
  73 static u64 precise_store_data(u64 status)
  74 {
  75         union intel_x86_pebs_dse dse;
  76         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  77
  78         dse.val = status;
  79
  80         /*
  81          * bit 4: TLB access
  82          * 1 = stored missed 2nd level TLB
  83          *
  84          * so it either hit the walker or the OS
  85          * otherwise hit 2nd level TLB
  86          */
  87         if (dse.st_stlb_miss)
  88                 val |= P(TLB, MISS);
  89         else
  90                 val |= P(TLB, HIT);
  91
  92         /*
  93          * bit 0: hit L1 data cache
  94          * if not set, then all we know is that
  95          * it missed L1D
  96          */
  97         if (dse.st_l1d_hit)
  98                 val |= P(LVL, HIT);
  99         else
 100                 val |= P(LVL, MISS);
 101
 102         /*
 103          * bit 5: Locked prefix
 104          */
 105         if (dse.st_locked)
 106                 val |= P(LOCK, LOCKED);
 107
 108         return val;
 109 }
 110
 111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 112 {
 113         union perf_mem_data_src dse;
 114
 115         dse.val = PERF_MEM_NA;
 116
 117         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 118                 dse.mem_op = PERF_MEM_OP_STORE;
 119         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 120                 dse.mem_op = PERF_MEM_OP_LOAD;
 121
 122         /*
 123          * L1 info only valid for following events:
 124          *
 125          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 126          * MEM_UOPS_RETIRED.LOCK_STORES
 127          * MEM_UOPS_RETIRED.SPLIT_STORES
 128          * MEM_UOPS_RETIRED.ALL_STORES
 129          */
 130         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 131                 if (status & 1)
 132                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 133                 else
 134                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 135         }
 136         return dse.val;
 137 }
 138
 139 static u64 load_latency_data(u64 status)
 140 {
 141         union intel_x86_pebs_dse dse;
 142         u64 val;
 143         int model = boot_cpu_data.x86_model;
 144         int fam = boot_cpu_data.x86;
 145
 146         dse.val = status;
 147
 148         /*
 149          * use the mapping table for bit 0-3
 150          */
 151         val = pebs_data_source[dse.ld_dse];
 152
 153         /*
 154          * Nehalem models do not support TLB, Lock infos
 155          */
 156         if (fam == 0x6 && (model == 26 || model == 30
 157             || model == 31 || model == 46)) {
 158                 val |= P(TLB, NA) | P(LOCK, NA);
 159                 return val;
 160         }
 161         /*
 162          * bit 4: TLB access
 163          * 0 = did not miss 2nd level TLB
 164          * 1 = missed 2nd level TLB
 165          */
 166         if (dse.ld_stlb_miss)
 167                 val |= P(TLB, MISS) | P(TLB, L2);
 168         else
 169                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 170
 171         /*
 172          * bit 5: locked prefix
 173          */
 174         if (dse.ld_locked)
 175                 val |= P(LOCK, LOCKED);
 176
 177         return val;
 178 }
 179
 180 struct pebs_record_core {
 181         u64 flags, ip;
 182         u64 ax, bx, cx, dx;
 183         u64 si, di, bp, sp;
 184         u64 r8,  r9,  r10, r11;
 185         u64 r12, r13, r14, r15;
 186 };
 187
 188 struct pebs_record_nhm {
 189         u64 flags, ip;
 190         u64 ax, bx, cx, dx;
 191         u64 si, di, bp, sp;
 192         u64 r8,  r9,  r10, r11;
 193         u64 r12, r13, r14, r15;
 194         u64 status, dla, dse, lat;
 195 };
 196
 197 /*
 198  * Same as pebs_record_nhm, with two additional fields.
 199  */
 200 struct pebs_record_hsw {
 201         u64 flags, ip;
 202         u64 ax, bx, cx, dx;
 203         u64 si, di, bp, sp;
 204         u64 r8,  r9,  r10, r11;
 205         u64 r12, r13, r14, r15;
 206         u64 status, dla, dse, lat;
 207         u64 real_ip, tsx_tuning;
 208 };
 209
 210 union hsw_tsx_tuning {
 211         struct {
 212                 u32 cycles_last_block     : 32,
 213                     hle_abort             : 1,
 214                     rtm_abort             : 1,
 215                     instruction_abort     : 1,
 216                     non_instruction_abort : 1,
 217                     retry                 : 1,
 218                     data_conflict         : 1,
 219                     capacity_writes       : 1,
 220                     capacity_reads        : 1;
 221         };
 222         u64         value;
 223 };
 224
 225 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 226
 227 /* Same as HSW, plus TSC */
 228
 229 struct pebs_record_skl {
 230         u64 flags, ip;
 231         u64 ax, bx, cx, dx;
 232         u64 si, di, bp, sp;
 233         u64 r8,  r9,  r10, r11;
 234         u64 r12, r13, r14, r15;
 235         u64 status, dla, dse, lat;
 236         u64 real_ip, tsx_tuning;
 237         u64 tsc;
 238 };
 239
 240 void init_debug_store_on_cpu(int cpu)
 241 {
 242         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 243
 244         if (!ds)
 245                 return;
 246
 247         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 248                      (u32)((u64)(unsigned long)ds),
 249                      (u32)((u64)(unsigned long)ds >> 32));
 250 }
 251
 252 void fini_debug_store_on_cpu(int cpu)
 253 {
 254         if (!per_cpu(cpu_hw_events, cpu).ds)
 255                 return;
 256
 257         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 258 }
 259
 260 static DEFINE_PER_CPU(void *, insn_buffer);
 261
 262 static int alloc_pebs_buffer(int cpu)
 263 {
 264         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 265         int node = cpu_to_node(cpu);
 266         int max;
 267         void *buffer, *ibuffer;
 268
 269         if (!x86_pmu.pebs)
 270                 return 0;
 271
 272         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 273         if (unlikely(!buffer))
 274                 return -ENOMEM;
 275
 276         /*
 277          * HSW+ already provides us the eventing ip; no need to allocate this
 278          * buffer then.
 279          */
 280         if (x86_pmu.intel_cap.pebs_format < 2) {
 281                 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 282                 if (!ibuffer) {
 283                         kfree(buffer);
 284                         return -ENOMEM;
 285                 }
 286                 per_cpu(insn_buffer, cpu) = ibuffer;
 287         }
 288
 289         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 290
 291         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 292         ds->pebs_index = ds->pebs_buffer_base;
 293         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 294                 max * x86_pmu.pebs_record_size;
 295
 296         return 0;
 297 }
 298
 299 static void release_pebs_buffer(int cpu)
 300 {
 301         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 302
 303         if (!ds || !x86_pmu.pebs)
 304                 return;
 305
 306         kfree(per_cpu(insn_buffer, cpu));
 307         per_cpu(insn_buffer, cpu) = NULL;
 308
 309         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 310         ds->pebs_buffer_base = 0;
 311 }
 312
 313 static int alloc_bts_buffer(int cpu)
 314 {
 315         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 316         int node = cpu_to_node(cpu);
 317         int max, thresh;
 318         void *buffer;
 319
 320         if (!x86_pmu.bts)
 321                 return 0;
 322
 323         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
 324         if (unlikely(!buffer)) {
 325                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 326                 return -ENOMEM;
 327         }
 328
 329         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 330         thresh = max / 16;
 331
 332         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 333         ds->bts_index = ds->bts_buffer_base;
 334         ds->bts_absolute_maximum = ds->bts_buffer_base +
 335                 max * BTS_RECORD_SIZE;
 336         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 337                 thresh * BTS_RECORD_SIZE;
 338
 339         return 0;
 340 }
 341
 342 static void release_bts_buffer(int cpu)
 343 {
 344         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 345
 346         if (!ds || !x86_pmu.bts)
 347                 return;
 348
 349         kfree((void *)(unsigned long)ds->bts_buffer_base);
 350         ds->bts_buffer_base = 0;
 351 }
 352
 353 static int alloc_ds_buffer(int cpu)
 354 {
 355         int node = cpu_to_node(cpu);
 356         struct debug_store *ds;
 357
 358         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 359         if (unlikely(!ds))
 360                 return -ENOMEM;
 361
 362         per_cpu(cpu_hw_events, cpu).ds = ds;
 363
 364         return 0;
 365 }
 366
 367 static void release_ds_buffer(int cpu)
 368 {
 369         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 370
 371         if (!ds)
 372                 return;
 373
 374         per_cpu(cpu_hw_events, cpu).ds = NULL;
 375         kfree(ds);
 376 }
 377
 378 void release_ds_buffers(void)
 379 {
 380         int cpu;
 381
 382         if (!x86_pmu.bts && !x86_pmu.pebs)
 383                 return;
 384
 385         get_online_cpus();
 386         for_each_online_cpu(cpu)
 387                 fini_debug_store_on_cpu(cpu);
 388
 389         for_each_possible_cpu(cpu) {
 390                 release_pebs_buffer(cpu);
 391                 release_bts_buffer(cpu);
 392                 release_ds_buffer(cpu);
 393         }
 394         put_online_cpus();
 395 }
 396
 397 void reserve_ds_buffers(void)
 398 {
 399         int bts_err = 0, pebs_err = 0;
 400         int cpu;
 401
 402         x86_pmu.bts_active = 0;
 403         x86_pmu.pebs_active = 0;
 404
 405         if (!x86_pmu.bts && !x86_pmu.pebs)
 406                 return;
 407
 408         if (!x86_pmu.bts)
 409                 bts_err = 1;
 410
 411         if (!x86_pmu.pebs)
 412                 pebs_err = 1;
 413
 414         get_online_cpus();
 415
 416         for_each_possible_cpu(cpu) {
 417                 if (alloc_ds_buffer(cpu)) {
 418                         bts_err = 1;
 419                         pebs_err = 1;
 420                 }
 421
 422                 if (!bts_err && alloc_bts_buffer(cpu))
 423                         bts_err = 1;
 424
 425                 if (!pebs_err && alloc_pebs_buffer(cpu))
 426                         pebs_err = 1;
 427
 428                 if (bts_err && pebs_err)
 429                         break;
 430         }
 431
 432         if (bts_err) {
 433                 for_each_possible_cpu(cpu)
 434                         release_bts_buffer(cpu);
 435         }
 436
 437         if (pebs_err) {
 438                 for_each_possible_cpu(cpu)
 439                         release_pebs_buffer(cpu);
 440         }
 441
 442         if (bts_err && pebs_err) {
 443                 for_each_possible_cpu(cpu)
 444                         release_ds_buffer(cpu);
 445         } else {
 446                 if (x86_pmu.bts && !bts_err)
 447                         x86_pmu.bts_active = 1;
 448
 449                 if (x86_pmu.pebs && !pebs_err)
 450                         x86_pmu.pebs_active = 1;
 451
 452                 for_each_online_cpu(cpu)
 453                         init_debug_store_on_cpu(cpu);
 454         }
 455
 456         put_online_cpus();
 457 }
 458
 459 /*
 460  * BTS
 461  */
 462
 463 struct event_constraint bts_constraint =
 464         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 465
 466 void intel_pmu_enable_bts(u64 config)
 467 {
 468         unsigned long debugctlmsr;
 469
 470         debugctlmsr = get_debugctlmsr();
 471
 472         debugctlmsr |= DEBUGCTLMSR_TR;
 473         debugctlmsr |= DEBUGCTLMSR_BTS;
 474         if (config & ARCH_PERFMON_EVENTSEL_INT)
 475                 debugctlmsr |= DEBUGCTLMSR_BTINT;
 476
 477         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 478                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 479
 480         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 481                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 482
 483         update_debugctlmsr(debugctlmsr);
 484 }
 485
 486 void intel_pmu_disable_bts(void)
 487 {
 488         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 489         unsigned long debugctlmsr;
 490
 491         if (!cpuc->ds)
 492                 return;
 493
 494         debugctlmsr = get_debugctlmsr();
 495
 496         debugctlmsr &=
 497                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 498                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 499
 500         update_debugctlmsr(debugctlmsr);
 501 }
 502
 503 int intel_pmu_drain_bts_buffer(void)
 504 {
 505         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 506         struct debug_store *ds = cpuc->ds;
 507         struct bts_record {
 508                 u64     from;
 509                 u64     to;
 510                 u64     flags;
 511         };
 512         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 513         struct bts_record *at, *base, *top;
 514         struct perf_output_handle handle;
 515         struct perf_event_header header;
 516         struct perf_sample_data data;
 517         unsigned long skip = 0;
 518         struct pt_regs regs;
 519
 520         if (!event)
 521                 return 0;
 522
 523         if (!x86_pmu.bts_active)
 524                 return 0;
 525
 526         base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 527         top  = (struct bts_record *)(unsigned long)ds->bts_index;
 528
 529         if (top <= base)
 530                 return 0;
 531
 532         memset(&regs, 0, sizeof(regs));
 533
 534         ds->bts_index = ds->bts_buffer_base;
 535
 536         perf_sample_data_init(&data, 0, event->hw.last_period);
 537
 538         /*
 539          * BTS leaks kernel addresses in branches across the cpl boundary,
 540          * such as traps or system calls, so unless the user is asking for
 541          * kernel tracing (and right now it's not possible), we'd need to
 542          * filter them out. But first we need to count how many of those we
 543          * have in the current batch. This is an extra O(n) pass, however,
 544          * it's much faster than the other one especially considering that
 545          * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
 546          * alloc_bts_buffer()).
 547          */
 548         for (at = base; at < top; at++) {
 549                 /*
 550                  * Note that right now *this* BTS code only works if
 551                  * attr::exclude_kernel is set, but let's keep this extra
 552                  * check here in case that changes.
 553                  */
 554                 if (event->attr.exclude_kernel &&
 555                     (kernel_ip(at->from) || kernel_ip(at->to)))
 556                         skip++;
 557         }
 558
 559         /*
 560          * Prepare a generic sample, i.e. fill in the invariant fields.
 561          * We will overwrite the from and to address before we output
 562          * the sample.
 563          */
 564         perf_prepare_sample(&header, &data, event, &regs);
 565
 566         if (perf_output_begin(&handle, event, header.size *
 567                               (top - base - skip)))
 568                 return 1;
 569
 570         for (at = base; at < top; at++) {
 571                 /* Filter out any records that contain kernel addresses. */
 572                 if (event->attr.exclude_kernel &&
 573                     (kernel_ip(at->from) || kernel_ip(at->to)))
 574                         continue;
 575
 576                 data.ip         = at->from;
 577                 data.addr       = at->to;
 578
 579                 perf_output_sample(&handle, &header, &data, event);
 580         }
 581
 582         perf_output_end(&handle);
 583
 584         /* There's new data available. */
 585         event->hw.interrupts++;
 586         event->pending_kill = POLL_IN;
 587         return 1;
 588 }
 589
 590 static inline void intel_pmu_drain_pebs_buffer(void)
 591 {
 592         struct pt_regs regs;
 593
 594         x86_pmu.drain_pebs(&regs);
 595 }
 596
 597 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
 598 {
 599         if (!sched_in)
 600                 intel_pmu_drain_pebs_buffer();
 601 }
 602
 603 /*
 604  * PEBS
 605  */
 606 struct event_constraint intel_core2_pebs_event_constraints[] = {
 607         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 608         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 609         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 610         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 611         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 612         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 613         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
 614         EVENT_CONSTRAINT_END
 615 };
 616
 617 struct event_constraint intel_atom_pebs_event_constraints[] = {
 618         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 619         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 620         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 621         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 622         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
 623         EVENT_CONSTRAINT_END
 624 };
 625
 626 struct event_constraint intel_slm_pebs_event_constraints[] = {
 627         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 628         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
 629         /* Allow all events as PEBS with no flags */
 630         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 631         EVENT_CONSTRAINT_END
 632 };
 633
 634 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 635         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 636         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 637         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 638         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 639         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 640         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 641         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 642         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 643         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 644         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 645         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 646         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 647         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 648         EVENT_CONSTRAINT_END
 649 };
 650
 651 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 652         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 653         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 654         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 655         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 656         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 657         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 658         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 659         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 660         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 661         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 662         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 663         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 664         INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
 665         EVENT_CONSTRAINT_END
 666 };
 667
 668 struct event_constraint intel_snb_pebs_event_constraints[] = {
 669         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 670         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 671         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 672         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 673         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 674         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 675         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 676         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 677         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 678         /* Allow all events as PEBS with no flags */
 679         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 680         EVENT_CONSTRAINT_END
 681 };
 682
 683 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 684         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 685         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 686         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 687         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 688         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 689         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 690         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 691         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 692         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 693         /* Allow all events as PEBS with no flags */
 694         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 695         EVENT_CONSTRAINT_END
 696 };
 697
 698 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 699         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 700         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 701         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 702         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 703         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 704         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 705         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 706         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 707         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 708         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 709         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 710         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 711         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 712         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 713         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 714         /* Allow all events as PEBS with no flags */
 715         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 716         EVENT_CONSTRAINT_END
 717 };
 718
 719 struct event_constraint intel_skl_pebs_event_constraints[] = {
 720         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),      /* INST_RETIRED.PREC_DIST */
 721         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 722         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 723         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 724         INTEL_PLD_CONSTRAINT(0x1cd, 0xf),                     /* MEM_TRANS_RETIRED.* */
 725         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 726         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
 727         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
 728         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
 729         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
 730         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
 731         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
 732         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
 733         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
 734         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
 735         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
 736         /* Allow all events as PEBS with no flags */
 737         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 738         EVENT_CONSTRAINT_END
 739 };
 740
 741 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 742 {
 743         struct event_constraint *c;
 744
 745         if (!event->attr.precise_ip)
 746                 return NULL;
 747
 748         if (x86_pmu.pebs_constraints) {
 749                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 750                         if ((event->hw.config & c->cmask) == c->code) {
 751                                 event->hw.flags |= c->flags;
 752                                 return c;
 753                         }
 754                 }
 755         }
 756
 757         return &emptyconstraint;
 758 }
 759
 760 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
 761 {
 762         return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
 763 }
 764
 765 void intel_pmu_pebs_enable(struct perf_event *event)
 766 {
 767         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 768         struct hw_perf_event *hwc = &event->hw;
 769         struct debug_store *ds = cpuc->ds;
 770         bool first_pebs;
 771         u64 threshold;
 772
 773         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 774
 775         first_pebs = !pebs_is_enabled(cpuc);
 776         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 777
 778         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 779                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 780         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 781                 cpuc->pebs_enabled |= 1ULL << 63;
 782
 783         /*
 784          * When the event is constrained enough we can use a larger
 785          * threshold and run the event with less frequent PMI.
 786          */
 787         if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
 788                 threshold = ds->pebs_absolute_maximum -
 789                         x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
 790
 791                 if (first_pebs)
 792                         perf_sched_cb_inc(event->ctx->pmu);
 793         } else {
 794                 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
 795
 796                 /*
 797                  * If not all events can use larger buffer,
 798                  * roll back to threshold = 1
 799                  */
 800                 if (!first_pebs &&
 801                     (ds->pebs_interrupt_threshold > threshold))
 802                         perf_sched_cb_dec(event->ctx->pmu);
 803         }
 804
 805         /* Use auto-reload if possible to save a MSR write in the PMI */
 806         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
 807                 ds->pebs_event_reset[hwc->idx] =
 808                         (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
 809         }
 810
 811         if (first_pebs || ds->pebs_interrupt_threshold > threshold)
 812                 ds->pebs_interrupt_threshold = threshold;
 813 }
 814
 815 void intel_pmu_pebs_disable(struct perf_event *event)
 816 {
 817         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 818         struct hw_perf_event *hwc = &event->hw;
 819         struct debug_store *ds = cpuc->ds;
 820         bool large_pebs = ds->pebs_interrupt_threshold >
 821                 ds->pebs_buffer_base + x86_pmu.pebs_record_size;
 822
 823         if (large_pebs)
 824                 intel_pmu_drain_pebs_buffer();
 825
 826         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 827
 828         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 829                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 830         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 831                 cpuc->pebs_enabled &= ~(1ULL << 63);
 832
 833         if (large_pebs && !pebs_is_enabled(cpuc))
 834                 perf_sched_cb_dec(event->ctx->pmu);
 835
 836         if (cpuc->enabled)
 837                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 838
 839         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 840 }
 841
 842 void intel_pmu_pebs_enable_all(void)
 843 {
 844         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 845
 846         if (cpuc->pebs_enabled)
 847                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 848 }
 849
 850 void intel_pmu_pebs_disable_all(void)
 851 {
 852         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 853
 854         if (cpuc->pebs_enabled)
 855                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 856 }
 857
 858 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 859 {
 860         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 861         unsigned long from = cpuc->lbr_entries[0].from;
 862         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 863         unsigned long ip = regs->ip;
 864         int is_64bit = 0;
 865         void *kaddr;
 866         int size;
 867
 868         /*
 869          * We don't need to fixup if the PEBS assist is fault like
 870          */
 871         if (!x86_pmu.intel_cap.pebs_trap)
 872                 return 1;
 873
 874         /*
 875          * No LBR entry, no basic block, no rewinding
 876          */
 877         if (!cpuc->lbr_stack.nr || !from || !to)
 878                 return 0;
 879
 880         /*
 881          * Basic blocks should never cross user/kernel boundaries
 882          */
 883         if (kernel_ip(ip) != kernel_ip(to))
 884                 return 0;
 885
 886         /*
 887          * unsigned math, either ip is before the start (impossible) or
 888          * the basic block is larger than 1 page (sanity)
 889          */
 890         if ((ip - to) > PEBS_FIXUP_SIZE)
 891                 return 0;
 892
 893         /*
 894          * We sampled a branch insn, rewind using the LBR stack
 895          */
 896         if (ip == to) {
 897                 set_linear_ip(regs, from);
 898                 return 1;
 899         }
 900
 901         size = ip - to;
 902         if (!kernel_ip(ip)) {
 903                 int bytes;
 904                 u8 *buf = this_cpu_read(insn_buffer);
 905
 906                 /* 'size' must fit our buffer, see above */
 907                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 908                 if (bytes != 0)
 909                         return 0;
 910
 911                 kaddr = buf;
 912         } else {
 913                 kaddr = (void *)to;
 914         }
 915
 916         do {
 917                 struct insn insn;
 918
 919                 old_to = to;
 920
 921 #ifdef CONFIG_X86_64
 922                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 923 #endif
 924                 insn_init(&insn, kaddr, size, is_64bit);
 925                 insn_get_length(&insn);
 926                 /*
 927                  * Make sure there was not a problem decoding the
 928                  * instruction and getting the length.  This is
 929                  * doubly important because we have an infinite
 930                  * loop if insn.length=0.
 931                  */
 932                 if (!insn.length)
 933                         break;
 934
 935                 to += insn.length;
 936                 kaddr += insn.length;
 937                 size -= insn.length;
 938         } while (to < ip);
 939
 940         if (to == ip) {
 941                 set_linear_ip(regs, old_to);
 942                 return 1;
 943         }
 944
 945         /*
 946          * Even though we decoded the basic block, the instruction stream
 947          * never matched the given IP, either the TO or the IP got corrupted.
 948          */
 949         return 0;
 950 }
 951
 952 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
 953 {
 954         if (pebs->tsx_tuning) {
 955                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 956                 return tsx.cycles_last_block;
 957         }
 958         return 0;
 959 }
 960
 961 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
 962 {
 963         u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
 964
 965         /* For RTM XABORTs also log the abort code from AX */
 966         if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
 967                 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
 968         return txn;
 969 }
 970
 971 static void setup_pebs_sample_data(struct perf_event *event,
 972                                    struct pt_regs *iregs, void *__pebs,
 973                                    struct perf_sample_data *data,
 974                                    struct pt_regs *regs)
 975 {
 976 #define PERF_X86_EVENT_PEBS_HSW_PREC \
 977                 (PERF_X86_EVENT_PEBS_ST_HSW | \
 978                  PERF_X86_EVENT_PEBS_LD_HSW | \
 979                  PERF_X86_EVENT_PEBS_NA_HSW)
 980         /*
 981          * We cast to the biggest pebs_record but are careful not to
 982          * unconditionally access the 'extra' entries.
 983          */
 984         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 985         struct pebs_record_skl *pebs = __pebs;
 986         u64 sample_type;
 987         int fll, fst, dsrc;
 988         int fl = event->hw.flags;
 989
 990         if (pebs == NULL)
 991                 return;
 992
 993         sample_type = event->attr.sample_type;
 994         dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
 995
 996         fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
 997         fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
 998
 999         perf_sample_data_init(data, 0, event->hw.last_period);
1000
1001         data->period = event->hw.last_period;
1002
1003         /*
1004          * Use latency for weight (only avail with PEBS-LL)
1005          */
1006         if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1007                 data->weight = pebs->lat;
1008
1009         /*
1010          * data.data_src encodes the data source
1011          */
1012         if (dsrc) {
1013                 u64 val = PERF_MEM_NA;
1014                 if (fll)
1015                         val = load_latency_data(pebs->dse);
1016                 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1017                         val = precise_datala_hsw(event, pebs->dse);
1018                 else if (fst)
1019                         val = precise_store_data(pebs->dse);
1020                 data->data_src.val = val;
1021         }
1022
1023         /*
1024          * We use the interrupt regs as a base because the PEBS record
1025          * does not contain a full regs set, specifically it seems to
1026          * lack segment descriptors, which get used by things like
1027          * user_mode().
1028          *
1029          * In the simple case fix up only the IP and BP,SP regs, for
1030          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1031          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1032          */
1033         *regs = *iregs;
1034         regs->flags = pebs->flags;
1035         set_linear_ip(regs, pebs->ip);
1036         regs->bp = pebs->bp;
1037         regs->sp = pebs->sp;
1038
1039         if (sample_type & PERF_SAMPLE_REGS_INTR) {
1040                 regs->ax = pebs->ax;
1041                 regs->bx = pebs->bx;
1042                 regs->cx = pebs->cx;
1043                 regs->dx = pebs->dx;
1044                 regs->si = pebs->si;
1045                 regs->di = pebs->di;
1046                 regs->bp = pebs->bp;
1047                 regs->sp = pebs->sp;
1048
1049                 regs->flags = pebs->flags;
1050 #ifndef CONFIG_X86_32
1051                 regs->r8 = pebs->r8;
1052                 regs->r9 = pebs->r9;
1053                 regs->r10 = pebs->r10;
1054                 regs->r11 = pebs->r11;
1055                 regs->r12 = pebs->r12;
1056                 regs->r13 = pebs->r13;
1057                 regs->r14 = pebs->r14;
1058                 regs->r15 = pebs->r15;
1059 #endif
1060         }
1061
1062         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1063                 regs->ip = pebs->real_ip;
1064                 regs->flags |= PERF_EFLAGS_EXACT;
1065         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1066                 regs->flags |= PERF_EFLAGS_EXACT;
1067         else
1068                 regs->flags &= ~PERF_EFLAGS_EXACT;
1069
1070         if ((sample_type & PERF_SAMPLE_ADDR) &&
1071             x86_pmu.intel_cap.pebs_format >= 1)
1072                 data->addr = pebs->dla;
1073
1074         if (x86_pmu.intel_cap.pebs_format >= 2) {
1075                 /* Only set the TSX weight when no memory weight. */
1076                 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1077                         data->weight = intel_hsw_weight(pebs);
1078
1079                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1080                         data->txn = intel_hsw_transaction(pebs);
1081         }
1082
1083         /*
1084          * v3 supplies an accurate time stamp, so we use that
1085          * for the time stamp.
1086          *
1087          * We can only do this for the default trace clock.
1088          */
1089         if (x86_pmu.intel_cap.pebs_format >= 3 &&
1090                 event->attr.use_clockid == 0)
1091                 data->time = native_sched_clock_from_tsc(pebs->tsc);
1092
1093         if (has_branch_stack(event))
1094                 data->br_stack = &cpuc->lbr_stack;
1095 }
1096
1097 static inline void *
1098 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1099 {
1100         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1101         void *at;
1102         u64 pebs_status;
1103
1104         if (base == NULL)
1105                 return NULL;
1106
1107         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1108                 struct pebs_record_nhm *p = at;
1109
1110                 if (test_bit(bit, (unsigned long *)&p->status)) {
1111                         /* PEBS v3 has accurate status bits */
1112                         if (x86_pmu.intel_cap.pebs_format >= 3)
1113                                 return at;
1114
1115                         if (p->status == (1 << bit))
1116                                 return at;
1117
1118                         /* clear non-PEBS bit and re-check */
1119                         pebs_status = p->status & cpuc->pebs_enabled;
1120                         pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1121                         if (pebs_status == (1 << bit))
1122                                 return at;
1123                 }
1124         }
1125         return NULL;
1126 }
1127
1128 static void __intel_pmu_pebs_event(struct perf_event *event,
1129                                    struct pt_regs *iregs,
1130                                    void *base, void *top,
1131                                    int bit, int count)
1132 {
1133         struct perf_sample_data data;
1134         struct pt_regs regs;
1135         void *at = get_next_pebs_record_by_bit(base, top, bit);
1136
1137         if (!intel_pmu_save_and_restart(event) &&
1138             !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1139                 return;
1140
1141         while (count > 1) {
1142                 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1143                 perf_event_output(event, &data, &regs);
1144                 at += x86_pmu.pebs_record_size;
1145                 at = get_next_pebs_record_by_bit(at, top, bit);
1146                 count--;
1147         }
1148
1149         setup_pebs_sample_data(event, iregs, at, &data, &regs);
1150
1151         /*
1152          * All but the last records are processed.
1153          * The last one is left to be able to call the overflow handler.
1154          */
1155         if (perf_event_overflow(event, &data, &regs)) {
1156                 x86_pmu_stop(event, 0);
1157                 return;
1158         }
1159
1160 }
1161
1162 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1163 {
1164         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1165         struct debug_store *ds = cpuc->ds;
1166         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1167         struct pebs_record_core *at, *top;
1168         int n;
1169
1170         if (!x86_pmu.pebs_active)
1171                 return;
1172
1173         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1174         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1175
1176         /*
1177          * Whatever else happens, drain the thing
1178          */
1179         ds->pebs_index = ds->pebs_buffer_base;
1180
1181         if (!test_bit(0, cpuc->active_mask))
1182                 return;
1183
1184         WARN_ON_ONCE(!event);
1185
1186         if (!event->attr.precise_ip)
1187                 return;
1188
1189         n = (top - at) / x86_pmu.pebs_record_size;
1190         if (n <= 0)
1191                 return;
1192
1193         __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1194 }
1195
1196 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1197 {
1198         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1199         struct debug_store *ds = cpuc->ds;
1200         struct perf_event *event;
1201         void *base, *at, *top;
1202         short counts[MAX_PEBS_EVENTS] = {};
1203         short error[MAX_PEBS_EVENTS] = {};
1204         int bit, i;
1205
1206         if (!x86_pmu.pebs_active)
1207                 return;
1208
1209         base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1210         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1211
1212         ds->pebs_index = ds->pebs_buffer_base;
1213
1214         if (unlikely(base >= top))
1215                 return;
1216
1217         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1218                 struct pebs_record_nhm *p = at;
1219                 u64 pebs_status;
1220
1221                 /* PEBS v3 has accurate status bits */
1222                 if (x86_pmu.intel_cap.pebs_format >= 3) {
1223                         for_each_set_bit(bit, (unsigned long *)&p->status,
1224                                          MAX_PEBS_EVENTS)
1225                                 counts[bit]++;
1226
1227                         continue;
1228                 }
1229
1230                 pebs_status = p->status & cpuc->pebs_enabled;
1231                 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1232
1233                 bit = find_first_bit((unsigned long *)&pebs_status,
1234                                         x86_pmu.max_pebs_events);
1235                 if (WARN(bit >= x86_pmu.max_pebs_events,
1236                          "PEBS record without PEBS event! status=%Lx pebs_enabled=%Lx active_mask=%Lx",
1237                          (unsigned long long)p->status, (unsigned long long)cpuc->pebs_enabled,
1238                          *(unsigned long long *)cpuc->active_mask))
1239                         continue;
1240
1241                 /*
1242                  * The PEBS hardware does not deal well with the situation
1243                  * when events happen near to each other and multiple bits
1244                  * are set. But it should happen rarely.
1245                  *
1246                  * If these events include one PEBS and multiple non-PEBS
1247                  * events, it doesn't impact PEBS record. The record will
1248                  * be handled normally. (slow path)
1249                  *
1250                  * If these events include two or more PEBS events, the
1251                  * records for the events can be collapsed into a single
1252                  * one, and it's not possible to reconstruct all events
1253                  * that caused the PEBS record. It's called collision.
1254                  * If collision happened, the record will be dropped.
1255                  */
1256                 if (p->status != (1ULL << bit)) {
1257                         for_each_set_bit(i, (unsigned long *)&pebs_status,
1258                                          x86_pmu.max_pebs_events)
1259                                 error[i]++;
1260                         continue;
1261                 }
1262
1263                 counts[bit]++;
1264         }
1265
1266         for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1267                 if ((counts[bit] == 0) && (error[bit] == 0))
1268                         continue;
1269
1270                 event = cpuc->events[bit];
1271                 WARN_ON_ONCE(!event);
1272                 WARN_ON_ONCE(!event->attr.precise_ip);
1273
1274                 /* log dropped samples number */
1275                 if (error[bit])
1276                         perf_log_lost_samples(event, error[bit]);
1277
1278                 if (counts[bit]) {
1279                         __intel_pmu_pebs_event(event, iregs, base,
1280                                                top, bit, counts[bit]);
1281                 }
1282         }
1283 }
1284
1285 /*
1286  * BTS, PEBS probe and setup
1287  */
1288
1289 void __init intel_ds_init(void)
1290 {
1291         /*
1292          * No support for 32bit formats
1293          */
1294         if (!boot_cpu_has(X86_FEATURE_DTES64))
1295                 return;
1296
1297         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1298         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1299         if (x86_pmu.pebs) {
1300                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1301                 int format = x86_pmu.intel_cap.pebs_format;
1302
1303                 switch (format) {
1304                 case 0:
1305                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1306                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1307                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1308                         break;
1309
1310                 case 1:
1311                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1312                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1313                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1314                         break;
1315
1316                 case 2:
1317                         pr_cont("PEBS fmt2%c, ", pebs_type);
1318                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1319                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1320                         break;
1321
1322                 case 3:
1323                         pr_cont("PEBS fmt3%c, ", pebs_type);
1324                         x86_pmu.pebs_record_size =
1325                                                 sizeof(struct pebs_record_skl);
1326                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1327                         x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1328                         break;
1329
1330                 default:
1331                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1332                         x86_pmu.pebs = 0;
1333                 }
1334         }
1335 }
1336
1337 void perf_restore_debug_store(void)
1338 {
1339         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1340
1341         if (!x86_pmu.bts && !x86_pmu.pebs)
1342                 return;
1343
1344         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1345 }