arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c

   1 /* Nehalem/SandBridge/Haswell uncore support */
   2 #include "perf_event_intel_uncore.h"
   3
   4 /* Uncore IMC PCI IDs */
   5 #define PCI_DEVICE_ID_INTEL_SNB_IMC     0x0100
   6 #define PCI_DEVICE_ID_INTEL_IVB_IMC     0x0154
   7 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC  0x0150
   8 #define PCI_DEVICE_ID_INTEL_HSW_IMC     0x0c00
   9 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC   0x0a04
  10 #define PCI_DEVICE_ID_INTEL_BDW_IMC     0x1604
  11
  12 /* SNB event control */
  13 #define SNB_UNC_CTL_EV_SEL_MASK                 0x000000ff
  14 #define SNB_UNC_CTL_UMASK_MASK                  0x0000ff00
  15 #define SNB_UNC_CTL_EDGE_DET                    (1 << 18)
  16 #define SNB_UNC_CTL_EN                          (1 << 22)
  17 #define SNB_UNC_CTL_INVERT                      (1 << 23)
  18 #define SNB_UNC_CTL_CMASK_MASK                  0x1f000000
  19 #define NHM_UNC_CTL_CMASK_MASK                  0xff000000
  20 #define NHM_UNC_FIXED_CTR_CTL_EN                (1 << 0)
  21
  22 #define SNB_UNC_RAW_EVENT_MASK                  (SNB_UNC_CTL_EV_SEL_MASK | \
  23                                                  SNB_UNC_CTL_UMASK_MASK | \
  24                                                  SNB_UNC_CTL_EDGE_DET | \
  25                                                  SNB_UNC_CTL_INVERT | \
  26                                                  SNB_UNC_CTL_CMASK_MASK)
  27
  28 #define NHM_UNC_RAW_EVENT_MASK                  (SNB_UNC_CTL_EV_SEL_MASK | \
  29                                                  SNB_UNC_CTL_UMASK_MASK | \
  30                                                  SNB_UNC_CTL_EDGE_DET | \
  31                                                  SNB_UNC_CTL_INVERT | \
  32                                                  NHM_UNC_CTL_CMASK_MASK)
  33
  34 /* SNB global control register */
  35 #define SNB_UNC_PERF_GLOBAL_CTL                 0x391
  36 #define SNB_UNC_FIXED_CTR_CTRL                  0x394
  37 #define SNB_UNC_FIXED_CTR                       0x395
  38
  39 /* SNB uncore global control */
  40 #define SNB_UNC_GLOBAL_CTL_CORE_ALL             ((1 << 4) - 1)
  41 #define SNB_UNC_GLOBAL_CTL_EN                   (1 << 29)
  42
  43 /* SNB Cbo register */
  44 #define SNB_UNC_CBO_0_PERFEVTSEL0               0x700
  45 #define SNB_UNC_CBO_0_PER_CTR0                  0x706
  46 #define SNB_UNC_CBO_MSR_OFFSET                  0x10
  47
  48 /* SNB ARB register */
  49 #define SNB_UNC_ARB_PER_CTR0                    0x3b0
  50 #define SNB_UNC_ARB_PERFEVTSEL0                 0x3b2
  51 #define SNB_UNC_ARB_MSR_OFFSET                  0x10
  52
  53 /* NHM global control register */
  54 #define NHM_UNC_PERF_GLOBAL_CTL                 0x391
  55 #define NHM_UNC_FIXED_CTR                       0x394
  56 #define NHM_UNC_FIXED_CTR_CTRL                  0x395
  57
  58 /* NHM uncore global control */
  59 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL            ((1ULL << 8) - 1)
  60 #define NHM_UNC_GLOBAL_CTL_EN_FC                (1ULL << 32)
  61
  62 /* NHM uncore register */
  63 #define NHM_UNC_PERFEVTSEL0                     0x3c0
  64 #define NHM_UNC_UNCORE_PMC0                     0x3b0
  65
  66 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
  67 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
  68 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
  69 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
  70 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
  71 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
  72
  73 /* Sandy Bridge uncore support */
  74 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
  75 {
  76         struct hw_perf_event *hwc = &event->hw;
  77
  78         if (hwc->idx < UNCORE_PMC_IDX_FIXED)
  79                 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
  80         else
  81                 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
  82 }
  83
  84 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
  85 {
  86         wrmsrl(event->hw.config_base, 0);
  87 }
  88
  89 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
  90 {
  91         if (box->pmu->pmu_idx == 0) {
  92                 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
  93                         SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
  94         }
  95 }
  96
  97 static struct uncore_event_desc snb_uncore_events[] = {
  98         INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
  99         { /* end: all zeroes */ },
 100 };
 101
 102 static struct attribute *snb_uncore_formats_attr[] = {
 103         &format_attr_event.attr,
 104         &format_attr_umask.attr,
 105         &format_attr_edge.attr,
 106         &format_attr_inv.attr,
 107         &format_attr_cmask5.attr,
 108         NULL,
 109 };
 110
 111 static struct attribute_group snb_uncore_format_group = {
 112         .name           = "format",
 113         .attrs          = snb_uncore_formats_attr,
 114 };
 115
 116 static struct intel_uncore_ops snb_uncore_msr_ops = {
 117         .init_box       = snb_uncore_msr_init_box,
 118         .disable_event  = snb_uncore_msr_disable_event,
 119         .enable_event   = snb_uncore_msr_enable_event,
 120         .read_counter   = uncore_msr_read_counter,
 121 };
 122
 123 static struct event_constraint snb_uncore_arb_constraints[] = {
 124         UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
 125         UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
 126         EVENT_CONSTRAINT_END
 127 };
 128
 129 static struct intel_uncore_type snb_uncore_cbox = {
 130         .name           = "cbox",
 131         .num_counters   = 2,
 132         .num_boxes      = 4,
 133         .perf_ctr_bits  = 44,
 134         .fixed_ctr_bits = 48,
 135         .perf_ctr       = SNB_UNC_CBO_0_PER_CTR0,
 136         .event_ctl      = SNB_UNC_CBO_0_PERFEVTSEL0,
 137         .fixed_ctr      = SNB_UNC_FIXED_CTR,
 138         .fixed_ctl      = SNB_UNC_FIXED_CTR_CTRL,
 139         .single_fixed   = 1,
 140         .event_mask     = SNB_UNC_RAW_EVENT_MASK,
 141         .msr_offset     = SNB_UNC_CBO_MSR_OFFSET,
 142         .ops            = &snb_uncore_msr_ops,
 143         .format_group   = &snb_uncore_format_group,
 144         .event_descs    = snb_uncore_events,
 145 };
 146
 147 static struct intel_uncore_type snb_uncore_arb = {
 148         .name           = "arb",
 149         .num_counters   = 2,
 150         .num_boxes      = 1,
 151         .perf_ctr_bits  = 44,
 152         .perf_ctr       = SNB_UNC_ARB_PER_CTR0,
 153         .event_ctl      = SNB_UNC_ARB_PERFEVTSEL0,
 154         .event_mask     = SNB_UNC_RAW_EVENT_MASK,
 155         .msr_offset     = SNB_UNC_ARB_MSR_OFFSET,
 156         .constraints    = snb_uncore_arb_constraints,
 157         .ops            = &snb_uncore_msr_ops,
 158         .format_group   = &snb_uncore_format_group,
 159 };
 160
 161 static struct intel_uncore_type *snb_msr_uncores[] = {
 162         &snb_uncore_cbox,
 163         &snb_uncore_arb,
 164         NULL,
 165 };
 166
 167 void snb_uncore_cpu_init(void)
 168 {
 169         uncore_msr_uncores = snb_msr_uncores;
 170         if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
 171                 snb_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
 172 }
 173
 174 enum {
 175         SNB_PCI_UNCORE_IMC,
 176 };
 177
 178 static struct uncore_event_desc snb_uncore_imc_events[] = {
 179         INTEL_UNCORE_EVENT_DESC(data_reads,  "event=0x01"),
 180         INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"),
 181         INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"),
 182
 183         INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
 184         INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
 185         INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
 186
 187         { /* end: all zeroes */ },
 188 };
 189
 190 #define SNB_UNCORE_PCI_IMC_EVENT_MASK           0xff
 191 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET           0x48
 192
 193 /* page size multiple covering all config regs */
 194 #define SNB_UNCORE_PCI_IMC_MAP_SIZE             0x6000
 195
 196 #define SNB_UNCORE_PCI_IMC_DATA_READS           0x1
 197 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE      0x5050
 198 #define SNB_UNCORE_PCI_IMC_DATA_WRITES          0x2
 199 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE     0x5054
 200 #define SNB_UNCORE_PCI_IMC_CTR_BASE             SNB_UNCORE_PCI_IMC_DATA_READS_BASE
 201
 202 static struct attribute *snb_uncore_imc_formats_attr[] = {
 203         &format_attr_event.attr,
 204         NULL,
 205 };
 206
 207 static struct attribute_group snb_uncore_imc_format_group = {
 208         .name = "format",
 209         .attrs = snb_uncore_imc_formats_attr,
 210 };
 211
 212 static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
 213 {
 214         struct pci_dev *pdev = box->pci_dev;
 215         int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET;
 216         resource_size_t addr;
 217         u32 pci_dword;
 218
 219         pci_read_config_dword(pdev, where, &pci_dword);
 220         addr = pci_dword;
 221
 222 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 223         pci_read_config_dword(pdev, where + 4, &pci_dword);
 224         addr |= ((resource_size_t)pci_dword << 32);
 225 #endif
 226
 227         addr &= ~(PAGE_SIZE - 1);
 228
 229         box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
 230         box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
 231 }
 232
 233 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
 234 {}
 235
 236 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
 237 {}
 238
 239 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 240 {}
 241
 242 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
 243 {}
 244
 245 static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
 246 {
 247         struct hw_perf_event *hwc = &event->hw;
 248
 249         return (u64)*(unsigned int *)(box->io_addr + hwc->event_base);
 250 }
 251
 252 /*
 253  * custom event_init() function because we define our own fixed, free
 254  * running counters, so we do not want to conflict with generic uncore
 255  * logic. Also simplifies processing
 256  */
 257 static int snb_uncore_imc_event_init(struct perf_event *event)
 258 {
 259         struct intel_uncore_pmu *pmu;
 260         struct intel_uncore_box *box;
 261         struct hw_perf_event *hwc = &event->hw;
 262         u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
 263         int idx, base;
 264
 265         if (event->attr.type != event->pmu->type)
 266                 return -ENOENT;
 267
 268         pmu = uncore_event_to_pmu(event);
 269         /* no device found for this pmu */
 270         if (pmu->func_id < 0)
 271                 return -ENOENT;
 272
 273         /* Sampling not supported yet */
 274         if (hwc->sample_period)
 275                 return -EINVAL;
 276
 277         /* unsupported modes and filters */
 278         if (event->attr.exclude_user   ||
 279             event->attr.exclude_kernel ||
 280             event->attr.exclude_hv     ||
 281             event->attr.exclude_idle   ||
 282             event->attr.exclude_host   ||
 283             event->attr.exclude_guest  ||
 284             event->attr.sample_period) /* no sampling */
 285                 return -EINVAL;
 286
 287         /*
 288          * Place all uncore events for a particular physical package
 289          * onto a single cpu
 290          */
 291         if (event->cpu < 0)
 292                 return -EINVAL;
 293
 294         /* check only supported bits are set */
 295         if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
 296                 return -EINVAL;
 297
 298         box = uncore_pmu_to_box(pmu, event->cpu);
 299         if (!box || box->cpu < 0)
 300                 return -EINVAL;
 301
 302         event->cpu = box->cpu;
 303
 304         event->hw.idx = -1;
 305         event->hw.last_tag = ~0ULL;
 306         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 307         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 308         /*
 309          * check event is known (whitelist, determines counter)
 310          */
 311         switch (cfg) {
 312         case SNB_UNCORE_PCI_IMC_DATA_READS:
 313                 base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
 314                 idx = UNCORE_PMC_IDX_FIXED;
 315                 break;
 316         case SNB_UNCORE_PCI_IMC_DATA_WRITES:
 317                 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
 318                 idx = UNCORE_PMC_IDX_FIXED + 1;
 319                 break;
 320         default:
 321                 return -EINVAL;
 322         }
 323
 324         /* must be done before validate_group */
 325         event->hw.event_base = base;
 326         event->hw.config = cfg;
 327         event->hw.idx = idx;
 328
 329         /* no group validation needed, we have free running counters */
 330
 331         return 0;
 332 }
 333
 334 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
 335 {
 336         return 0;
 337 }
 338
 339 static void snb_uncore_imc_event_start(struct perf_event *event, int flags)
 340 {
 341         struct intel_uncore_box *box = uncore_event_to_box(event);
 342         u64 count;
 343
 344         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
 345                 return;
 346
 347         event->hw.state = 0;
 348         box->n_active++;
 349
 350         list_add_tail(&event->active_entry, &box->active_list);
 351
 352         count = snb_uncore_imc_read_counter(box, event);
 353         local64_set(&event->hw.prev_count, count);
 354
 355         if (box->n_active == 1)
 356                 uncore_pmu_start_hrtimer(box);
 357 }
 358
 359 static void snb_uncore_imc_event_stop(struct perf_event *event, int flags)
 360 {
 361         struct intel_uncore_box *box = uncore_event_to_box(event);
 362         struct hw_perf_event *hwc = &event->hw;
 363
 364         if (!(hwc->state & PERF_HES_STOPPED)) {
 365                 box->n_active--;
 366
 367                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 368                 hwc->state |= PERF_HES_STOPPED;
 369
 370                 list_del(&event->active_entry);
 371
 372                 if (box->n_active == 0)
 373                         uncore_pmu_cancel_hrtimer(box);
 374         }
 375
 376         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
 377                 /*
 378                  * Drain the remaining delta count out of a event
 379                  * that we are disabling:
 380                  */
 381                 uncore_perf_event_update(box, event);
 382                 hwc->state |= PERF_HES_UPTODATE;
 383         }
 384 }
 385
 386 static int snb_uncore_imc_event_add(struct perf_event *event, int flags)
 387 {
 388         struct intel_uncore_box *box = uncore_event_to_box(event);
 389         struct hw_perf_event *hwc = &event->hw;
 390
 391         if (!box)
 392                 return -ENODEV;
 393
 394         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 395         if (!(flags & PERF_EF_START))
 396                 hwc->state |= PERF_HES_ARCH;
 397
 398         snb_uncore_imc_event_start(event, 0);
 399
 400         box->n_events++;
 401
 402         return 0;
 403 }
 404
 405 static void snb_uncore_imc_event_del(struct perf_event *event, int flags)
 406 {
 407         struct intel_uncore_box *box = uncore_event_to_box(event);
 408         int i;
 409
 410         snb_uncore_imc_event_stop(event, PERF_EF_UPDATE);
 411
 412         for (i = 0; i < box->n_events; i++) {
 413                 if (event == box->event_list[i]) {
 414                         --box->n_events;
 415                         break;
 416                 }
 417         }
 418 }
 419
 420 static int snb_pci2phy_map_init(int devid)
 421 {
 422         struct pci_dev *dev = NULL;
 423         int bus;
 424
 425         dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
 426         if (!dev)
 427                 return -ENOTTY;
 428
 429         bus = dev->bus->number;
 430
 431         uncore_pcibus_to_physid[bus] = 0;
 432
 433         pci_dev_put(dev);
 434
 435         return 0;
 436 }
 437
 438 static struct pmu snb_uncore_imc_pmu = {
 439         .task_ctx_nr    = perf_invalid_context,
 440         .event_init     = snb_uncore_imc_event_init,
 441         .add            = snb_uncore_imc_event_add,
 442         .del            = snb_uncore_imc_event_del,
 443         .start          = snb_uncore_imc_event_start,
 444         .stop           = snb_uncore_imc_event_stop,
 445         .read           = uncore_pmu_event_read,
 446 };
 447
 448 static struct intel_uncore_ops snb_uncore_imc_ops = {
 449         .init_box       = snb_uncore_imc_init_box,
 450         .enable_box     = snb_uncore_imc_enable_box,
 451         .disable_box    = snb_uncore_imc_disable_box,
 452         .disable_event  = snb_uncore_imc_disable_event,
 453         .enable_event   = snb_uncore_imc_enable_event,
 454         .hw_config      = snb_uncore_imc_hw_config,
 455         .read_counter   = snb_uncore_imc_read_counter,
 456 };
 457
 458 static struct intel_uncore_type snb_uncore_imc = {
 459         .name           = "imc",
 460         .num_counters   = 2,
 461         .num_boxes      = 1,
 462         .fixed_ctr_bits = 32,
 463         .fixed_ctr      = SNB_UNCORE_PCI_IMC_CTR_BASE,
 464         .event_descs    = snb_uncore_imc_events,
 465         .format_group   = &snb_uncore_imc_format_group,
 466         .perf_ctr       = SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
 467         .event_mask     = SNB_UNCORE_PCI_IMC_EVENT_MASK,
 468         .ops            = &snb_uncore_imc_ops,
 469         .pmu            = &snb_uncore_imc_pmu,
 470 };
 471
 472 static struct intel_uncore_type *snb_pci_uncores[] = {
 473         [SNB_PCI_UNCORE_IMC]    = &snb_uncore_imc,
 474         NULL,
 475 };
 476
 477 static const struct pci_device_id snb_uncore_pci_ids[] = {
 478         { /* IMC */
 479                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC),
 480                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 481         },
 482         { /* end: all zeroes */ },
 483 };
 484
 485 static const struct pci_device_id ivb_uncore_pci_ids[] = {
 486         { /* IMC */
 487                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
 488                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 489         },
 490         { /* IMC */
 491                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_E3_IMC),
 492                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 493         },
 494         { /* end: all zeroes */ },
 495 };
 496
 497 static const struct pci_device_id hsw_uncore_pci_ids[] = {
 498         { /* IMC */
 499                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
 500                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 501         },
 502         { /* IMC */
 503                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC),
 504                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 505         },
 506         { /* end: all zeroes */ },
 507 };
 508
 509 static const struct pci_device_id bdw_uncore_pci_ids[] = {
 510         { /* IMC */
 511                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_IMC),
 512                 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 513         },
 514         { /* end: all zeroes */ },
 515 };
 516
 517 static struct pci_driver snb_uncore_pci_driver = {
 518         .name           = "snb_uncore",
 519         .id_table       = snb_uncore_pci_ids,
 520 };
 521
 522 static struct pci_driver ivb_uncore_pci_driver = {
 523         .name           = "ivb_uncore",
 524         .id_table       = ivb_uncore_pci_ids,
 525 };
 526
 527 static struct pci_driver hsw_uncore_pci_driver = {
 528         .name           = "hsw_uncore",
 529         .id_table       = hsw_uncore_pci_ids,
 530 };
 531
 532 static struct pci_driver bdw_uncore_pci_driver = {
 533         .name           = "bdw_uncore",
 534         .id_table       = bdw_uncore_pci_ids,
 535 };
 536
 537 struct imc_uncore_pci_dev {
 538         __u32 pci_id;
 539         struct pci_driver *driver;
 540 };
 541 #define IMC_DEV(a, d) \
 542         { .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) }
 543
 544 static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
 545         IMC_DEV(SNB_IMC, &snb_uncore_pci_driver),
 546         IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver),    /* 3rd Gen Core processor */
 547         IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
 548         IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver),    /* 4th Gen Core Processor */
 549         IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver),  /* 4th Gen Core ULT Mobile Processor */
 550         IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver),    /* 5th Gen Core U */
 551         {  /* end marker */ }
 552 };
 553
 554
 555 #define for_each_imc_pci_id(x, t) \
 556         for (x = (t); (x)->pci_id; x++)
 557
 558 static struct pci_driver *imc_uncore_find_dev(void)
 559 {
 560         const struct imc_uncore_pci_dev *p;
 561         int ret;
 562
 563         for_each_imc_pci_id(p, desktop_imc_pci_ids) {
 564                 ret = snb_pci2phy_map_init(p->pci_id);
 565                 if (ret == 0)
 566                         return p->driver;
 567         }
 568         return NULL;
 569 }
 570
 571 static int imc_uncore_pci_init(void)
 572 {
 573         struct pci_driver *imc_drv = imc_uncore_find_dev();
 574
 575         if (!imc_drv)
 576                 return -ENODEV;
 577
 578         uncore_pci_uncores = snb_pci_uncores;
 579         uncore_pci_driver = imc_drv;
 580
 581         return 0;
 582 }
 583
 584 int snb_uncore_pci_init(void)
 585 {
 586         return imc_uncore_pci_init();
 587 }
 588
 589 int ivb_uncore_pci_init(void)
 590 {
 591         return imc_uncore_pci_init();
 592 }
 593 int hsw_uncore_pci_init(void)
 594 {
 595         return imc_uncore_pci_init();
 596 }
 597
 598 int bdw_uncore_pci_init(void)
 599 {
 600         return imc_uncore_pci_init();
 601 }
 602
 603 /* end of Sandy Bridge uncore support */
 604
 605 /* Nehalem uncore support */
 606 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
 607 {
 608         wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
 609 }
 610
 611 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
 612 {
 613         wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
 614 }
 615
 616 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 617 {
 618         struct hw_perf_event *hwc = &event->hw;
 619
 620         if (hwc->idx < UNCORE_PMC_IDX_FIXED)
 621                 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
 622         else
 623                 wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
 624 }
 625
 626 static struct attribute *nhm_uncore_formats_attr[] = {
 627         &format_attr_event.attr,
 628         &format_attr_umask.attr,
 629         &format_attr_edge.attr,
 630         &format_attr_inv.attr,
 631         &format_attr_cmask8.attr,
 632         NULL,
 633 };
 634
 635 static struct attribute_group nhm_uncore_format_group = {
 636         .name = "format",
 637         .attrs = nhm_uncore_formats_attr,
 638 };
 639
 640 static struct uncore_event_desc nhm_uncore_events[] = {
 641         INTEL_UNCORE_EVENT_DESC(clockticks,                "event=0xff,umask=0x00"),
 642         INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any,       "event=0x2f,umask=0x0f"),
 643         INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any,      "event=0x2c,umask=0x0f"),
 644         INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads,     "event=0x20,umask=0x01"),
 645         INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes,    "event=0x20,umask=0x02"),
 646         INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads,  "event=0x20,umask=0x04"),
 647         INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
 648         INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads,   "event=0x20,umask=0x10"),
 649         INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes,  "event=0x20,umask=0x20"),
 650         { /* end: all zeroes */ },
 651 };
 652
 653 static struct intel_uncore_ops nhm_uncore_msr_ops = {
 654         .disable_box    = nhm_uncore_msr_disable_box,
 655         .enable_box     = nhm_uncore_msr_enable_box,
 656         .disable_event  = snb_uncore_msr_disable_event,
 657         .enable_event   = nhm_uncore_msr_enable_event,
 658         .read_counter   = uncore_msr_read_counter,
 659 };
 660
 661 static struct intel_uncore_type nhm_uncore = {
 662         .name           = "",
 663         .num_counters   = 8,
 664         .num_boxes      = 1,
 665         .perf_ctr_bits  = 48,
 666         .fixed_ctr_bits = 48,
 667         .event_ctl      = NHM_UNC_PERFEVTSEL0,
 668         .perf_ctr       = NHM_UNC_UNCORE_PMC0,
 669         .fixed_ctr      = NHM_UNC_FIXED_CTR,
 670         .fixed_ctl      = NHM_UNC_FIXED_CTR_CTRL,
 671         .event_mask     = NHM_UNC_RAW_EVENT_MASK,
 672         .event_descs    = nhm_uncore_events,
 673         .ops            = &nhm_uncore_msr_ops,
 674         .format_group   = &nhm_uncore_format_group,
 675 };
 676
 677 static struct intel_uncore_type *nhm_msr_uncores[] = {
 678         &nhm_uncore,
 679         NULL,
 680 };
 681
 682 void nhm_uncore_cpu_init(void)
 683 {
 684         uncore_msr_uncores = nhm_msr_uncores;
 685 }
 686
 687 /* end of Nehalem uncore support */