drivers/clk/h8300/clk-div.c

   1 /*
   2  * H8/300 divide clock driver
   3  *
   4  * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11
  12 static DEFINE_SPINLOCK(clklock);
  13
  14 static void __init h8300_div_clk_setup(struct device_node *node)
  15 {
  16         int num_parents;
  17         struct clk *clk;
  18         const char *clk_name = node->name;
  19         const char *parent_name;
  20         void __iomem *divcr = NULL;
  21         int width;
  22
  23         num_parents = of_clk_get_parent_count(node);
  24         if (num_parents < 1) {
  25                 pr_err("%s: no parent found", clk_name);
  26                 return;
  27         }
  28
  29         divcr = of_iomap(node, 0);
  30         if (divcr == NULL) {
  31                 pr_err("%s: failed to map divide register", clk_name);
  32                 goto error;
  33         }
  34
  35         parent_name = of_clk_get_parent_name(node, 0);
  36         of_property_read_u32(node, "renesas,width", &width);
  37         clk = clk_register_divider(NULL, clk_name, parent_name,
  38                                    CLK_SET_RATE_GATE, divcr, 0, width,
  39                                    CLK_DIVIDER_POWER_OF_TWO, &clklock);
  40         if (!IS_ERR(clk)) {
  41                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
  42                 return;
  43         }
  44         pr_err("%s: failed to register %s div clock (%ld)\n",
  45                __func__, clk_name, PTR_ERR(clk));
  46 error:
  47         if (divcr)
  48                 iounmap(divcr);
  49 }
  50
  51 CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);