drivers/clk/sunxi/clk-a10-pll2.c

   1 /*
   2  * Copyright 2013 Emilio López
   3  * Emilio López <emilio@elopez.com.ar>
   4  *
   5  * Copyright 2015 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/clk-provider.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/slab.h>
  23
  24 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  25
  26 #define SUN4I_PLL2_ENABLE               31
  27
  28 #define SUN4I_PLL2_PRE_DIV_SHIFT        0
  29 #define SUN4I_PLL2_PRE_DIV_WIDTH        5
  30 #define SUN4I_PLL2_PRE_DIV_MASK         GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
  31
  32 #define SUN4I_PLL2_N_SHIFT              8
  33 #define SUN4I_PLL2_N_WIDTH              7
  34 #define SUN4I_PLL2_N_MASK               GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
  35
  36 #define SUN4I_PLL2_POST_DIV_SHIFT       26
  37 #define SUN4I_PLL2_POST_DIV_WIDTH       4
  38 #define SUN4I_PLL2_POST_DIV_MASK        GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
  39
  40 #define SUN4I_PLL2_POST_DIV_VALUE       4
  41
  42 #define SUN4I_PLL2_OUTPUTS              4
  43
  44 struct sun4i_pll2_data {
  45         u32     post_div_offset;
  46         u32     pre_div_flags;
  47 };
  48
  49 static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
  50
  51 static void __init sun4i_pll2_setup(struct device_node *node,
  52                                     struct sun4i_pll2_data *data)
  53 {
  54         const char *clk_name = node->name, *parent;
  55         struct clk **clks, *base_clk, *prediv_clk;
  56         struct clk_onecell_data *clk_data;
  57         struct clk_multiplier *mult;
  58         struct clk_gate *gate;
  59         void __iomem *reg;
  60         u32 val;
  61
  62         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
  63         if (IS_ERR(reg))
  64                 return;
  65
  66         clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  67         if (!clk_data)
  68                 goto err_unmap;
  69
  70         clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
  71         if (!clks)
  72                 goto err_free_data;
  73
  74         parent = of_clk_get_parent_name(node, 0);
  75         prediv_clk = clk_register_divider(NULL, "pll2-prediv",
  76                                           parent, 0, reg,
  77                                           SUN4I_PLL2_PRE_DIV_SHIFT,
  78                                           SUN4I_PLL2_PRE_DIV_WIDTH,
  79                                           data->pre_div_flags,
  80                                           &sun4i_a10_pll2_lock);
  81         if (!prediv_clk) {
  82                 pr_err("Couldn't register the prediv clock\n");
  83                 goto err_free_array;
  84         }
  85
  86         /* Setup the gate part of the PLL2 */
  87         gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
  88         if (!gate)
  89                 goto err_unregister_prediv;
  90
  91         gate->reg = reg;
  92         gate->bit_idx = SUN4I_PLL2_ENABLE;
  93         gate->lock = &sun4i_a10_pll2_lock;
  94
  95         /* Setup the multiplier part of the PLL2 */
  96         mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
  97         if (!mult)
  98                 goto err_free_gate;
  99
 100         mult->reg = reg;
 101         mult->shift = SUN4I_PLL2_N_SHIFT;
 102         mult->width = 7;
 103         mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
 104                         CLK_MULTIPLIER_ROUND_CLOSEST;
 105         mult->lock = &sun4i_a10_pll2_lock;
 106
 107         parent = __clk_get_name(prediv_clk);
 108         base_clk = clk_register_composite(NULL, "pll2-base",
 109                                           &parent, 1,
 110                                           NULL, NULL,
 111                                           &mult->hw, &clk_multiplier_ops,
 112                                           &gate->hw, &clk_gate_ops,
 113                                           CLK_SET_RATE_PARENT);
 114         if (!base_clk) {
 115                 pr_err("Couldn't register the base multiplier clock\n");
 116                 goto err_free_multiplier;
 117         }
 118
 119         parent = __clk_get_name(base_clk);
 120
 121         /*
 122          * PLL2-1x
 123          *
 124          * This is supposed to have a post divider, but we won't need
 125          * to use it, we just need to initialise it to 4, and use a
 126          * fixed divider.
 127          */
 128         val = readl(reg);
 129         val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
 130         val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
 131         writel(val, reg);
 132
 133         of_property_read_string_index(node, "clock-output-names",
 134                                       SUN4I_A10_PLL2_1X, &clk_name);
 135         clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
 136                                                             parent,
 137                                                             CLK_SET_RATE_PARENT,
 138                                                             1,
 139                                                             SUN4I_PLL2_POST_DIV_VALUE);
 140         WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
 141
 142         /*
 143          * PLL2-2x
 144          *
 145          * This clock doesn't use the post divider, and really is just
 146          * a fixed divider from the PLL2 base clock.
 147          */
 148         of_property_read_string_index(node, "clock-output-names",
 149                                       SUN4I_A10_PLL2_2X, &clk_name);
 150         clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
 151                                                             parent,
 152                                                             CLK_SET_RATE_PARENT,
 153                                                             1, 2);
 154         WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
 155
 156         /* PLL2-4x */
 157         of_property_read_string_index(node, "clock-output-names",
 158                                       SUN4I_A10_PLL2_4X, &clk_name);
 159         clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
 160                                                             parent,
 161                                                             CLK_SET_RATE_PARENT,
 162                                                             1, 1);
 163         WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
 164
 165         /* PLL2-8x */
 166         of_property_read_string_index(node, "clock-output-names",
 167                                       SUN4I_A10_PLL2_8X, &clk_name);
 168         clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
 169                                                             parent,
 170                                                             CLK_SET_RATE_PARENT,
 171                                                             2, 1);
 172         WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
 173
 174         clk_data->clks = clks;
 175         clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
 176         of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 177
 178         return;
 179
 180 err_free_multiplier:
 181         kfree(mult);
 182 err_free_gate:
 183         kfree(gate);
 184 err_unregister_prediv:
 185         clk_unregister_divider(prediv_clk);
 186 err_free_array:
 187         kfree(clks);
 188 err_free_data:
 189         kfree(clk_data);
 190 err_unmap:
 191         iounmap(reg);
 192 }
 193
 194 static struct sun4i_pll2_data sun4i_a10_pll2_data = {
 195         .pre_div_flags  = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 196 };
 197
 198 static void __init sun4i_a10_pll2_setup(struct device_node *node)
 199 {
 200         sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
 201 }
 202
 203 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
 204                sun4i_a10_pll2_setup);
 205
 206 static struct sun4i_pll2_data sun5i_a13_pll2_data = {
 207         .post_div_offset        = 1,
 208 };
 209
 210 static void __init sun5i_a13_pll2_setup(struct device_node *node)
 211 {
 212         sun4i_pll2_setup(node, &sun5i_a13_pll2_data);
 213 }
 214
 215 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
 216                sun5i_a13_pll2_setup);