drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include <asm/div64.h>
  33
  34 #include <linux/pm_runtime.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37
  38 static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
  39                                    struct fence **f)
  40 {
  41         struct amdgpu_fence *fence;
  42         long r;
  43
  44         if (*f == NULL)
  45                 return;
  46
  47         fence = to_amdgpu_fence(*f);
  48         if (fence) {
  49                 r = fence_wait(&fence->base, false);
  50                 if (r == -EDEADLK) {
  51                         up_read(&adev->exclusive_lock);
  52                         r = amdgpu_gpu_reset(adev);
  53                         down_read(&adev->exclusive_lock);
  54                 }
  55         } else
  56                 r = fence_wait(*f, false);
  57
  58         if (r)
  59                 DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r);
  60
  61         /* We continue with the page flip even if we failed to wait on
  62          * the fence, otherwise the DRM core and userspace will be
  63          * confused about which BO the CRTC is scanning out
  64          */
  65         fence_put(*f);
  66         *f = NULL;
  67 }
  68
  69 static void amdgpu_flip_work_func(struct work_struct *__work)
  70 {
  71         struct amdgpu_flip_work *work =
  72                 container_of(__work, struct amdgpu_flip_work, flip_work);
  73         struct amdgpu_device *adev = work->adev;
  74         struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id];
  75
  76         struct drm_crtc *crtc = &amdgpuCrtc->base;
  77         unsigned long flags;
  78         unsigned i;
  79
  80         down_read(&adev->exclusive_lock);
  81         amdgpu_flip_wait_fence(adev, &work->excl);
  82         for (i = 0; i < work->shared_count; ++i)
  83                 amdgpu_flip_wait_fence(adev, &work->shared[i]);
  84
  85         /* We borrow the event spin lock for protecting flip_status */
  86         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  87
  88         /* do the flip (mmio) */
  89         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
  90         /* set the flip status */
  91         amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
  92
  93         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  94         up_read(&adev->exclusive_lock);
  95 }
  96
  97 /*
  98  * Handle unpin events outside the interrupt handler proper.
  99  */
 100 static void amdgpu_unpin_work_func(struct work_struct *__work)
 101 {
 102         struct amdgpu_flip_work *work =
 103                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 104         int r;
 105
 106         /* unpin of the old buffer */
 107         r = amdgpu_bo_reserve(work->old_rbo, false);
 108         if (likely(r == 0)) {
 109                 r = amdgpu_bo_unpin(work->old_rbo);
 110                 if (unlikely(r != 0)) {
 111                         DRM_ERROR("failed to unpin buffer after flip\n");
 112                 }
 113                 amdgpu_bo_unreserve(work->old_rbo);
 114         } else
 115                 DRM_ERROR("failed to reserve buffer after flip\n");
 116
 117         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 118         kfree(work->shared);
 119         kfree(work);
 120 }
 121
 122 int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
 123                           struct drm_framebuffer *fb,
 124                           struct drm_pending_vblank_event *event,
 125                           uint32_t page_flip_flags)
 126 {
 127         struct drm_device *dev = crtc->dev;
 128         struct amdgpu_device *adev = dev->dev_private;
 129         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 130         struct amdgpu_framebuffer *old_amdgpu_fb;
 131         struct amdgpu_framebuffer *new_amdgpu_fb;
 132         struct drm_gem_object *obj;
 133         struct amdgpu_flip_work *work;
 134         struct amdgpu_bo *new_rbo;
 135         unsigned long flags;
 136         u64 tiling_flags;
 137         u64 base;
 138         int i, r;
 139
 140         work = kzalloc(sizeof *work, GFP_KERNEL);
 141         if (work == NULL)
 142                 return -ENOMEM;
 143
 144         INIT_WORK(&work->flip_work, amdgpu_flip_work_func);
 145         INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
 146
 147         work->event = event;
 148         work->adev = adev;
 149         work->crtc_id = amdgpu_crtc->crtc_id;
 150
 151         /* schedule unpin of the old buffer */
 152         old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 153         obj = old_amdgpu_fb->obj;
 154
 155         /* take a reference to the old object */
 156         drm_gem_object_reference(obj);
 157         work->old_rbo = gem_to_amdgpu_bo(obj);
 158
 159         new_amdgpu_fb = to_amdgpu_framebuffer(fb);
 160         obj = new_amdgpu_fb->obj;
 161         new_rbo = gem_to_amdgpu_bo(obj);
 162
 163         /* pin the new buffer */
 164         r = amdgpu_bo_reserve(new_rbo, false);
 165         if (unlikely(r != 0)) {
 166                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 167                 goto cleanup;
 168         }
 169
 170         r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base);
 171         if (unlikely(r != 0)) {
 172                 amdgpu_bo_unreserve(new_rbo);
 173                 r = -EINVAL;
 174                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 175                 goto cleanup;
 176         }
 177
 178         r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl,
 179                                               &work->shared_count,
 180                                               &work->shared);
 181         if (unlikely(r != 0)) {
 182                 amdgpu_bo_unreserve(new_rbo);
 183                 DRM_ERROR("failed to get fences for buffer\n");
 184                 goto cleanup;
 185         }
 186
 187         fence_get(work->excl);
 188         for (i = 0; i < work->shared_count; ++i)
 189                 fence_get(work->shared[i]);
 190
 191         amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags);
 192         amdgpu_bo_unreserve(new_rbo);
 193
 194         work->base = base;
 195
 196         r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
 197         if (r) {
 198                 DRM_ERROR("failed to get vblank before flip\n");
 199                 goto pflip_cleanup;
 200         }
 201
 202         /* we borrow the event spin lock for protecting flip_wrok */
 203         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 204         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 205                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 206                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 207                 r = -EBUSY;
 208                 goto vblank_cleanup;
 209         }
 210
 211         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 212         amdgpu_crtc->pflip_works = work;
 213
 214         /* update crtc fb */
 215         crtc->primary->fb = fb;
 216         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 217         queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
 218         return 0;
 219
 220 vblank_cleanup:
 221         drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
 222
 223 pflip_cleanup:
 224         if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
 225                 DRM_ERROR("failed to reserve new rbo in error path\n");
 226                 goto cleanup;
 227         }
 228         if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) {
 229                 DRM_ERROR("failed to unpin new rbo in error path\n");
 230         }
 231         amdgpu_bo_unreserve(new_rbo);
 232
 233 cleanup:
 234         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 235         fence_put(work->excl);
 236         for (i = 0; i < work->shared_count; ++i)
 237                 fence_put(work->shared[i]);
 238         kfree(work->shared);
 239         kfree(work);
 240
 241         return r;
 242 }
 243
 244 int amdgpu_crtc_set_config(struct drm_mode_set *set)
 245 {
 246         struct drm_device *dev;
 247         struct amdgpu_device *adev;
 248         struct drm_crtc *crtc;
 249         bool active = false;
 250         int ret;
 251
 252         if (!set || !set->crtc)
 253                 return -EINVAL;
 254
 255         dev = set->crtc->dev;
 256
 257         ret = pm_runtime_get_sync(dev->dev);
 258         if (ret < 0)
 259                 return ret;
 260
 261         ret = drm_crtc_helper_set_config(set);
 262
 263         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 264                 if (crtc->enabled)
 265                         active = true;
 266
 267         pm_runtime_mark_last_busy(dev->dev);
 268
 269         adev = dev->dev_private;
 270         /* if we have active crtcs and we don't have a power ref,
 271            take the current one */
 272         if (active && !adev->have_disp_power_ref) {
 273                 adev->have_disp_power_ref = true;
 274                 return ret;
 275         }
 276         /* if we have no active crtcs, then drop the power ref
 277            we got before */
 278         if (!active && adev->have_disp_power_ref) {
 279                 pm_runtime_put_autosuspend(dev->dev);
 280                 adev->have_disp_power_ref = false;
 281         }
 282
 283         /* drop the power reference we got coming in here */
 284         pm_runtime_put_autosuspend(dev->dev);
 285         return ret;
 286 }
 287
 288 static const char *encoder_names[38] = {
 289         "NONE",
 290         "INTERNAL_LVDS",
 291         "INTERNAL_TMDS1",
 292         "INTERNAL_TMDS2",
 293         "INTERNAL_DAC1",
 294         "INTERNAL_DAC2",
 295         "INTERNAL_SDVOA",
 296         "INTERNAL_SDVOB",
 297         "SI170B",
 298         "CH7303",
 299         "CH7301",
 300         "INTERNAL_DVO1",
 301         "EXTERNAL_SDVOA",
 302         "EXTERNAL_SDVOB",
 303         "TITFP513",
 304         "INTERNAL_LVTM1",
 305         "VT1623",
 306         "HDMI_SI1930",
 307         "HDMI_INTERNAL",
 308         "INTERNAL_KLDSCP_TMDS1",
 309         "INTERNAL_KLDSCP_DVO1",
 310         "INTERNAL_KLDSCP_DAC1",
 311         "INTERNAL_KLDSCP_DAC2",
 312         "SI178",
 313         "MVPU_FPGA",
 314         "INTERNAL_DDI",
 315         "VT1625",
 316         "HDMI_SI1932",
 317         "DP_AN9801",
 318         "DP_DP501",
 319         "INTERNAL_UNIPHY",
 320         "INTERNAL_KLDSCP_LVTMA",
 321         "INTERNAL_UNIPHY1",
 322         "INTERNAL_UNIPHY2",
 323         "NUTMEG",
 324         "TRAVIS",
 325         "INTERNAL_VCE",
 326         "INTERNAL_UNIPHY3",
 327 };
 328
 329 static const char *hpd_names[6] = {
 330         "HPD1",
 331         "HPD2",
 332         "HPD3",
 333         "HPD4",
 334         "HPD5",
 335         "HPD6",
 336 };
 337
 338 void amdgpu_print_display_setup(struct drm_device *dev)
 339 {
 340         struct drm_connector *connector;
 341         struct amdgpu_connector *amdgpu_connector;
 342         struct drm_encoder *encoder;
 343         struct amdgpu_encoder *amdgpu_encoder;
 344         uint32_t devices;
 345         int i = 0;
 346
 347         DRM_INFO("AMDGPU Display Connectors\n");
 348         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 349                 amdgpu_connector = to_amdgpu_connector(connector);
 350                 DRM_INFO("Connector %d:\n", i);
 351                 DRM_INFO("  %s\n", connector->name);
 352                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 353                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 354                 if (amdgpu_connector->ddc_bus) {
 355                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 356                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 357                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 358                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 359                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 360                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 361                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 362                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 363                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 364                         if (amdgpu_connector->router.ddc_valid)
 365                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 366                                          amdgpu_connector->router.ddc_mux_control_pin,
 367                                          amdgpu_connector->router.ddc_mux_state);
 368                         if (amdgpu_connector->router.cd_valid)
 369                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 370                                          amdgpu_connector->router.cd_mux_control_pin,
 371                                          amdgpu_connector->router.cd_mux_state);
 372                 } else {
 373                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 374                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 375                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 376                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 377                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 378                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 379                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 380                 }
 381                 DRM_INFO("  Encoders:\n");
 382                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 383                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 384                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 385                         if (devices) {
 386                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 387                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 388                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 389                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 390                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 391                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 392                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 393                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 394                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 395                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 396                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 397                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 398                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 399                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 400                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 401                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 402                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 403                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 404                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 405                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 406                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 407                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 408                         }
 409                 }
 410                 i++;
 411         }
 412 }
 413
 414 /**
 415  * amdgpu_ddc_probe
 416  *
 417  */
 418 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 419                        bool use_aux)
 420 {
 421         u8 out = 0x0;
 422         u8 buf[8];
 423         int ret;
 424         struct i2c_msg msgs[] = {
 425                 {
 426                         .addr = DDC_ADDR,
 427                         .flags = 0,
 428                         .len = 1,
 429                         .buf = &out,
 430                 },
 431                 {
 432                         .addr = DDC_ADDR,
 433                         .flags = I2C_M_RD,
 434                         .len = 8,
 435                         .buf = buf,
 436                 }
 437         };
 438
 439         /* on hw with routers, select right port */
 440         if (amdgpu_connector->router.ddc_valid)
 441                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 442
 443         if (use_aux) {
 444                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 445         } else {
 446                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 447         }
 448
 449         if (ret != 2)
 450                 /* Couldn't find an accessible DDC on this connector */
 451                 return false;
 452         /* Probe also for valid EDID header
 453          * EDID header starts with:
 454          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 455          * Only the first 6 bytes must be valid as
 456          * drm_edid_block_valid() can fix the last 2 bytes */
 457         if (drm_edid_header_is_valid(buf) < 6) {
 458                 /* Couldn't find an accessible EDID on this
 459                  * connector */
 460                 return false;
 461         }
 462         return true;
 463 }
 464
 465 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
 466 {
 467         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 468
 469         if (amdgpu_fb->obj) {
 470                 drm_gem_object_unreference_unlocked(amdgpu_fb->obj);
 471         }
 472         drm_framebuffer_cleanup(fb);
 473         kfree(amdgpu_fb);
 474 }
 475
 476 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 477                                                   struct drm_file *file_priv,
 478                                                   unsigned int *handle)
 479 {
 480         struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
 481
 482         return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
 483 }
 484
 485 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 486         .destroy = amdgpu_user_framebuffer_destroy,
 487         .create_handle = amdgpu_user_framebuffer_create_handle,
 488 };
 489
 490 int
 491 amdgpu_framebuffer_init(struct drm_device *dev,
 492                         struct amdgpu_framebuffer *rfb,
 493                         struct drm_mode_fb_cmd2 *mode_cmd,
 494                         struct drm_gem_object *obj)
 495 {
 496         int ret;
 497         rfb->obj = obj;
 498         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 499         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 500         if (ret) {
 501                 rfb->obj = NULL;
 502                 return ret;
 503         }
 504         return 0;
 505 }
 506
 507 static struct drm_framebuffer *
 508 amdgpu_user_framebuffer_create(struct drm_device *dev,
 509                                struct drm_file *file_priv,
 510                                struct drm_mode_fb_cmd2 *mode_cmd)
 511 {
 512         struct drm_gem_object *obj;
 513         struct amdgpu_framebuffer *amdgpu_fb;
 514         int ret;
 515
 516         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
 517         if (obj ==  NULL) {
 518                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 519                         "can't create framebuffer\n", mode_cmd->handles[0]);
 520                 return ERR_PTR(-ENOENT);
 521         }
 522
 523         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
 524         if (amdgpu_fb == NULL) {
 525                 drm_gem_object_unreference_unlocked(obj);
 526                 return ERR_PTR(-ENOMEM);
 527         }
 528
 529         ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
 530         if (ret) {
 531                 kfree(amdgpu_fb);
 532                 drm_gem_object_unreference_unlocked(obj);
 533                 return ERR_PTR(ret);
 534         }
 535
 536         return &amdgpu_fb->base;
 537 }
 538
 539 static void amdgpu_output_poll_changed(struct drm_device *dev)
 540 {
 541         struct amdgpu_device *adev = dev->dev_private;
 542         amdgpu_fb_output_poll_changed(adev);
 543 }
 544
 545 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
 546         .fb_create = amdgpu_user_framebuffer_create,
 547         .output_poll_changed = amdgpu_output_poll_changed
 548 };
 549
 550 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
 551 {       { UNDERSCAN_OFF, "off" },
 552         { UNDERSCAN_ON, "on" },
 553         { UNDERSCAN_AUTO, "auto" },
 554 };
 555
 556 static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
 557 {       { AMDGPU_AUDIO_DISABLE, "off" },
 558         { AMDGPU_AUDIO_ENABLE, "on" },
 559         { AMDGPU_AUDIO_AUTO, "auto" },
 560 };
 561
 562 /* XXX support different dither options? spatial, temporal, both, etc. */
 563 static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
 564 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
 565         { AMDGPU_FMT_DITHER_ENABLE, "on" },
 566 };
 567
 568 int amdgpu_modeset_create_props(struct amdgpu_device *adev)
 569 {
 570         int sz;
 571
 572         if (adev->is_atom_bios) {
 573                 adev->mode_info.coherent_mode_property =
 574                         drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
 575                 if (!adev->mode_info.coherent_mode_property)
 576                         return -ENOMEM;
 577         }
 578
 579         adev->mode_info.load_detect_property =
 580                 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
 581         if (!adev->mode_info.load_detect_property)
 582                 return -ENOMEM;
 583
 584         drm_mode_create_scaling_mode_property(adev->ddev);
 585
 586         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
 587         adev->mode_info.underscan_property =
 588                 drm_property_create_enum(adev->ddev, 0,
 589                                     "underscan",
 590                                     amdgpu_underscan_enum_list, sz);
 591
 592         adev->mode_info.underscan_hborder_property =
 593                 drm_property_create_range(adev->ddev, 0,
 594                                         "underscan hborder", 0, 128);
 595         if (!adev->mode_info.underscan_hborder_property)
 596                 return -ENOMEM;
 597
 598         adev->mode_info.underscan_vborder_property =
 599                 drm_property_create_range(adev->ddev, 0,
 600                                         "underscan vborder", 0, 128);
 601         if (!adev->mode_info.underscan_vborder_property)
 602                 return -ENOMEM;
 603
 604         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
 605         adev->mode_info.audio_property =
 606                 drm_property_create_enum(adev->ddev, 0,
 607                                          "audio",
 608                                          amdgpu_audio_enum_list, sz);
 609
 610         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
 611         adev->mode_info.dither_property =
 612                 drm_property_create_enum(adev->ddev, 0,
 613                                          "dither",
 614                                          amdgpu_dither_enum_list, sz);
 615
 616         return 0;
 617 }
 618
 619 void amdgpu_update_display_priority(struct amdgpu_device *adev)
 620 {
 621         /* adjustment options for the display watermarks */
 622         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
 623                 adev->mode_info.disp_priority = 0;
 624         else
 625                 adev->mode_info.disp_priority = amdgpu_disp_priority;
 626
 627 }
 628
 629 static bool is_hdtv_mode(const struct drm_display_mode *mode)
 630 {
 631         /* try and guess if this is a tv or a monitor */
 632         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 633             (mode->vdisplay == 576) || /* 576p */
 634             (mode->vdisplay == 720) || /* 720p */
 635             (mode->vdisplay == 1080)) /* 1080p */
 636                 return true;
 637         else
 638                 return false;
 639 }
 640
 641 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 642                                     const struct drm_display_mode *mode,
 643                                     struct drm_display_mode *adjusted_mode)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         struct drm_encoder *encoder;
 647         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 648         struct amdgpu_encoder *amdgpu_encoder;
 649         struct drm_connector *connector;
 650         struct amdgpu_connector *amdgpu_connector;
 651         u32 src_v = 1, dst_v = 1;
 652         u32 src_h = 1, dst_h = 1;
 653
 654         amdgpu_crtc->h_border = 0;
 655         amdgpu_crtc->v_border = 0;
 656
 657         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 658                 if (encoder->crtc != crtc)
 659                         continue;
 660                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 661                 connector = amdgpu_get_connector_for_encoder(encoder);
 662                 amdgpu_connector = to_amdgpu_connector(connector);
 663
 664                 /* set scaling */
 665                 if (amdgpu_encoder->rmx_type == RMX_OFF)
 666                         amdgpu_crtc->rmx_type = RMX_OFF;
 667                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
 668                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
 669                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
 670                 else
 671                         amdgpu_crtc->rmx_type = RMX_OFF;
 672                 /* copy native mode */
 673                 memcpy(&amdgpu_crtc->native_mode,
 674                        &amdgpu_encoder->native_mode,
 675                        sizeof(struct drm_display_mode));
 676                 src_v = crtc->mode.vdisplay;
 677                 dst_v = amdgpu_crtc->native_mode.vdisplay;
 678                 src_h = crtc->mode.hdisplay;
 679                 dst_h = amdgpu_crtc->native_mode.hdisplay;
 680
 681                 /* fix up for overscan on hdmi */
 682                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
 683                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
 684                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
 685                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
 686                       is_hdtv_mode(mode)))) {
 687                         if (amdgpu_encoder->underscan_hborder != 0)
 688                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
 689                         else
 690                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
 691                         if (amdgpu_encoder->underscan_vborder != 0)
 692                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
 693                         else
 694                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
 695                         amdgpu_crtc->rmx_type = RMX_FULL;
 696                         src_v = crtc->mode.vdisplay;
 697                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
 698                         src_h = crtc->mode.hdisplay;
 699                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
 700                 }
 701         }
 702         if (amdgpu_crtc->rmx_type != RMX_OFF) {
 703                 fixed20_12 a, b;
 704                 a.full = dfixed_const(src_v);
 705                 b.full = dfixed_const(dst_v);
 706                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
 707                 a.full = dfixed_const(src_h);
 708                 b.full = dfixed_const(dst_h);
 709                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
 710         } else {
 711                 amdgpu_crtc->vsc.full = dfixed_const(1);
 712                 amdgpu_crtc->hsc.full = dfixed_const(1);
 713         }
 714         return true;
 715 }
 716
 717 /*
 718  * Retrieve current video scanout position of crtc on a given gpu, and
 719  * an optional accurate timestamp of when query happened.
 720  *
 721  * \param dev Device to query.
 722  * \param crtc Crtc to query.
 723  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
 724  * \param *vpos Location where vertical scanout position should be stored.
 725  * \param *hpos Location where horizontal scanout position should go.
 726  * \param *stime Target location for timestamp taken immediately before
 727  *               scanout position query. Can be NULL to skip timestamp.
 728  * \param *etime Target location for timestamp taken immediately after
 729  *               scanout position query. Can be NULL to skip timestamp.
 730  *
 731  * Returns vpos as a positive number while in active scanout area.
 732  * Returns vpos as a negative number inside vblank, counting the number
 733  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
 734  * until start of active scanout / end of vblank."
 735  *
 736  * \return Flags, or'ed together as follows:
 737  *
 738  * DRM_SCANOUTPOS_VALID = Query successful.
 739  * DRM_SCANOUTPOS_INVBL = Inside vblank.
 740  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
 741  * this flag means that returned position may be offset by a constant but
 742  * unknown small number of scanlines wrt. real scanout position.
 743  *
 744  */
 745 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
 746                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
 747 {
 748         u32 vbl = 0, position = 0;
 749         int vbl_start, vbl_end, vtotal, ret = 0;
 750         bool in_vbl = true;
 751
 752         struct amdgpu_device *adev = dev->dev_private;
 753
 754         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 755
 756         /* Get optional system timestamp before query. */
 757         if (stime)
 758                 *stime = ktime_get();
 759
 760         if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0)
 761                 ret |= DRM_SCANOUTPOS_VALID;
 762
 763         /* Get optional system timestamp after query. */
 764         if (etime)
 765                 *etime = ktime_get();
 766
 767         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 768
 769         /* Decode into vertical and horizontal scanout position. */
 770         *vpos = position & 0x1fff;
 771         *hpos = (position >> 16) & 0x1fff;
 772
 773         /* Valid vblank area boundaries from gpu retrieved? */
 774         if (vbl > 0) {
 775                 /* Yes: Decode. */
 776                 ret |= DRM_SCANOUTPOS_ACCURATE;
 777                 vbl_start = vbl & 0x1fff;
 778                 vbl_end = (vbl >> 16) & 0x1fff;
 779         }
 780         else {
 781                 /* No: Fake something reasonable which gives at least ok results. */
 782                 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
 783                 vbl_end = 0;
 784         }
 785
 786         /* Test scanout position against vblank region. */
 787         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
 788                 in_vbl = false;
 789
 790         /* Check if inside vblank area and apply corrective offsets:
 791          * vpos will then be >=0 in video scanout area, but negative
 792          * within vblank area, counting down the number of lines until
 793          * start of scanout.
 794          */
 795
 796         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
 797         if (in_vbl && (*vpos >= vbl_start)) {
 798                 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
 799                 *vpos = *vpos - vtotal;
 800         }
 801
 802         /* Correct for shifted end of vbl at vbl_end. */
 803         *vpos = *vpos - vbl_end;
 804
 805         /* In vblank? */
 806         if (in_vbl)
 807                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 808
 809         /* Is vpos outside nominal vblank area, but less than
 810          * 1/100 of a frame height away from start of vblank?
 811          * If so, assume this isn't a massively delayed vblank
 812          * interrupt, but a vblank interrupt that fired a few
 813          * microseconds before true start of vblank. Compensate
 814          * by adding a full frame duration to the final timestamp.
 815          * Happens, e.g., on ATI R500, R600.
 816          *
 817          * We only do this if DRM_CALLED_FROM_VBLIRQ.
 818          */
 819         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
 820                 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
 821                 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
 822
 823                 if (vbl_start - *vpos < vtotal / 100) {
 824                         *vpos -= vtotal;
 825
 826                         /* Signal this correction as "applied". */
 827                         ret |= 0x8;
 828                 }
 829         }
 830
 831         return ret;
 832 }
 833
 834 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
 835 {
 836         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 837                 return AMDGPU_CRTC_IRQ_NONE;
 838
 839         switch (crtc) {
 840         case 0:
 841                 return AMDGPU_CRTC_IRQ_VBLANK1;
 842         case 1:
 843                 return AMDGPU_CRTC_IRQ_VBLANK2;
 844         case 2:
 845                 return AMDGPU_CRTC_IRQ_VBLANK3;
 846         case 3:
 847                 return AMDGPU_CRTC_IRQ_VBLANK4;
 848         case 4:
 849                 return AMDGPU_CRTC_IRQ_VBLANK5;
 850         case 5:
 851                 return AMDGPU_CRTC_IRQ_VBLANK6;
 852         default:
 853                 return AMDGPU_CRTC_IRQ_NONE;
 854         }
 855 }