drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct i915_gpu_error *error)
  91 {
  92         int ret;
  93
  94 #define EXIT_COND (!i915_reset_in_progress(error) || \
  95                    i915_terminally_wedged(error))
  96         if (EXIT_COND)
  97                 return 0;
  98
  99         /*
 100          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 101          * userspace. If it takes that long something really bad is going on and
 102          * we should simply try to bail out and fail as gracefully as possible.
 103          */
 104         ret = wait_event_interruptible_timeout(error->reset_queue,
 105                                                EXIT_COND,
 106                                                10*HZ);
 107         if (ret == 0) {
 108                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 109                 return -EIO;
 110         } else if (ret < 0) {
 111                 return ret;
 112         }
 113 #undef EXIT_COND
 114
 115         return 0;
 116 }
 117
 118 int i915_mutex_lock_interruptible(struct drm_device *dev)
 119 {
 120         struct drm_i915_private *dev_priv = dev->dev_private;
 121         int ret;
 122
 123         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 124         if (ret)
 125                 return ret;
 126
 127         ret = mutex_lock_interruptible(&dev->struct_mutex);
 128         if (ret)
 129                 return ret;
 130
 131         WARN_ON(i915_verify_lists(dev));
 132         return 0;
 133 }
 134
 135 static inline bool
 136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 137 {
 138         return obj->gtt_space && !obj->active;
 139 }
 140
 141 int
 142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 143                     struct drm_file *file)
 144 {
 145         struct drm_i915_private *dev_priv = dev->dev_private;
 146         struct drm_i915_gem_init *args = data;
 147
 148         if (drm_core_check_feature(dev, DRIVER_MODESET))
 149                 return -ENODEV;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         /* GEM with user mode setting was never supported on ilk and later. */
 156         if (INTEL_INFO(dev)->gen >= 5)
 157                 return -ENODEV;
 158
 159         mutex_lock(&dev->struct_mutex);
 160         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 161                                   args->gtt_end);
 162         dev_priv->gtt.mappable_end = args->gtt_end;
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         pinned = 0;
 178         mutex_lock(&dev->struct_mutex);
 179         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 180                 if (obj->pin_count)
 181                         pinned += obj->gtt_space->size;
 182         mutex_unlock(&dev->struct_mutex);
 183
 184         args->aper_size = dev_priv->gtt.total;
 185         args->aper_available_size = args->aper_size - pinned;
 186
 187         return 0;
 188 }
 189
 190 void *i915_gem_object_alloc(struct drm_device *dev)
 191 {
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
 194 }
 195
 196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 197 {
 198         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 199         kmem_cache_free(dev_priv->slab, obj);
 200 }
 201
 202 static int
 203 i915_gem_create(struct drm_file *file,
 204                 struct drm_device *dev,
 205                 uint64_t size,
 206                 uint32_t *handle_p)
 207 {
 208         struct drm_i915_gem_object *obj;
 209         int ret;
 210         u32 handle;
 211
 212         size = roundup(size, PAGE_SIZE);
 213         if (size == 0)
 214                 return -EINVAL;
 215
 216         /* Allocate the new object */
 217         obj = i915_gem_alloc_object(dev, size);
 218         if (obj == NULL)
 219                 return -ENOMEM;
 220
 221         ret = drm_gem_handle_create(file, &obj->base, &handle);
 222         if (ret) {
 223                 drm_gem_object_release(&obj->base);
 224                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 225                 i915_gem_object_free(obj);
 226                 return ret;
 227         }
 228
 229         /* drop reference from allocate - handle holds it now */
 230         drm_gem_object_unreference(&obj->base);
 231         trace_i915_gem_object_create(obj);
 232
 233         *handle_p = handle;
 234         return 0;
 235 }
 236
 237 int
 238 i915_gem_dumb_create(struct drm_file *file,
 239                      struct drm_device *dev,
 240                      struct drm_mode_create_dumb *args)
 241 {
 242         /* have to work out size/pitch and return them */
 243         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 244         args->size = args->pitch * args->height;
 245         return i915_gem_create(file, dev,
 246                                args->size, &args->handle);
 247 }
 248
 249 int i915_gem_dumb_destroy(struct drm_file *file,
 250                           struct drm_device *dev,
 251                           uint32_t handle)
 252 {
 253         return drm_gem_handle_delete(file, handle);
 254 }
 255
 256 /**
 257  * Creates a new mm object and returns a handle to it.
 258  */
 259 int
 260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 261                       struct drm_file *file)
 262 {
 263         struct drm_i915_gem_create *args = data;
 264
 265         return i915_gem_create(file, dev,
 266                                args->size, &args->handle);
 267 }
 268
 269 static inline int
 270 __copy_to_user_swizzled(char __user *cpu_vaddr,
 271                         const char *gpu_vaddr, int gpu_offset,
 272                         int length)
 273 {
 274         int ret, cpu_offset = 0;
 275
 276         while (length > 0) {
 277                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 278                 int this_length = min(cacheline_end - gpu_offset, length);
 279                 int swizzled_gpu_offset = gpu_offset ^ 64;
 280
 281                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 282                                      gpu_vaddr + swizzled_gpu_offset,
 283                                      this_length);
 284                 if (ret)
 285                         return ret + length;
 286
 287                 cpu_offset += this_length;
 288                 gpu_offset += this_length;
 289                 length -= this_length;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 297                           const char __user *cpu_vaddr,
 298                           int length)
 299 {
 300         int ret, cpu_offset = 0;
 301
 302         while (length > 0) {
 303                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 304                 int this_length = min(cacheline_end - gpu_offset, length);
 305                 int swizzled_gpu_offset = gpu_offset ^ 64;
 306
 307                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 308                                        cpu_vaddr + cpu_offset,
 309                                        this_length);
 310                 if (ret)
 311                         return ret + length;
 312
 313                 cpu_offset += this_length;
 314                 gpu_offset += this_length;
 315                 length -= this_length;
 316         }
 317
 318         return 0;
 319 }
 320
 321 /* Per-page copy function for the shmem pread fastpath.
 322  * Flushes invalid cachelines before reading the target if
 323  * needs_clflush is set. */
 324 static int
 325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 326                  char __user *user_data,
 327                  bool page_do_bit17_swizzling, bool needs_clflush)
 328 {
 329         char *vaddr;
 330         int ret;
 331
 332         if (unlikely(page_do_bit17_swizzling))
 333                 return -EINVAL;
 334
 335         vaddr = kmap_atomic(page);
 336         if (needs_clflush)
 337                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 338                                        page_length);
 339         ret = __copy_to_user_inatomic(user_data,
 340                                       vaddr + shmem_page_offset,
 341                                       page_length);
 342         kunmap_atomic(vaddr);
 343
 344         return ret ? -EFAULT : 0;
 345 }
 346
 347 static void
 348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 349                              bool swizzled)
 350 {
 351         if (unlikely(swizzled)) {
 352                 unsigned long start = (unsigned long) addr;
 353                 unsigned long end = (unsigned long) addr + length;
 354
 355                 /* For swizzling simply ensure that we always flush both
 356                  * channels. Lame, but simple and it works. Swizzled
 357                  * pwrite/pread is far from a hotpath - current userspace
 358                  * doesn't use it at all. */
 359                 start = round_down(start, 128);
 360                 end = round_up(end, 128);
 361
 362                 drm_clflush_virt_range((void *)start, end - start);
 363         } else {
 364                 drm_clflush_virt_range(addr, length);
 365         }
 366
 367 }
 368
 369 /* Only difference to the fast-path function is that this can handle bit17
 370  * and uses non-atomic copy and kmap functions. */
 371 static int
 372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 373                  char __user *user_data,
 374                  bool page_do_bit17_swizzling, bool needs_clflush)
 375 {
 376         char *vaddr;
 377         int ret;
 378
 379         vaddr = kmap(page);
 380         if (needs_clflush)
 381                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 382                                              page_length,
 383                                              page_do_bit17_swizzling);
 384
 385         if (page_do_bit17_swizzling)
 386                 ret = __copy_to_user_swizzled(user_data,
 387                                               vaddr, shmem_page_offset,
 388                                               page_length);
 389         else
 390                 ret = __copy_to_user(user_data,
 391                                      vaddr + shmem_page_offset,
 392                                      page_length);
 393         kunmap(page);
 394
 395         return ret ? - EFAULT : 0;
 396 }
 397
 398 static int
 399 i915_gem_shmem_pread(struct drm_device *dev,
 400                      struct drm_i915_gem_object *obj,
 401                      struct drm_i915_gem_pread *args,
 402                      struct drm_file *file)
 403 {
 404         char __user *user_data;
 405         ssize_t remain;
 406         loff_t offset;
 407         int shmem_page_offset, page_length, ret = 0;
 408         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 409         int prefaulted = 0;
 410         int needs_clflush = 0;
 411         struct sg_page_iter sg_iter;
 412
 413         user_data = to_user_ptr(args->data_ptr);
 414         remain = args->size;
 415
 416         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 417
 418         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 419                 /* If we're not in the cpu read domain, set ourself into the gtt
 420                  * read domain and manually flush cachelines (if required). This
 421                  * optimizes for the case when the gpu will dirty the data
 422                  * anyway again before the next pread happens. */
 423                 if (obj->cache_level == I915_CACHE_NONE)
 424                         needs_clflush = 1;
 425                 if (obj->gtt_space) {
 426                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 427                         if (ret)
 428                                 return ret;
 429                 }
 430         }
 431
 432         ret = i915_gem_object_get_pages(obj);
 433         if (ret)
 434                 return ret;
 435
 436         i915_gem_object_pin_pages(obj);
 437
 438         offset = args->offset;
 439
 440         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 441                          offset >> PAGE_SHIFT) {
 442                 struct page *page = sg_page_iter_page(&sg_iter);
 443
 444                 if (remain <= 0)
 445                         break;
 446
 447                 /* Operation in this page
 448                  *
 449                  * shmem_page_offset = offset within page in shmem file
 450                  * page_length = bytes to copy for this page
 451                  */
 452                 shmem_page_offset = offset_in_page(offset);
 453                 page_length = remain;
 454                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 455                         page_length = PAGE_SIZE - shmem_page_offset;
 456
 457                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 458                         (page_to_phys(page) & (1 << 17)) != 0;
 459
 460                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 461                                        user_data, page_do_bit17_swizzling,
 462                                        needs_clflush);
 463                 if (ret == 0)
 464                         goto next_page;
 465
 466                 mutex_unlock(&dev->struct_mutex);
 467
 468                 if (!prefaulted) {
 469                         ret = fault_in_multipages_writeable(user_data, remain);
 470                         /* Userspace is tricking us, but we've already clobbered
 471                          * its pages with the prefault and promised to write the
 472                          * data up to the first fault. Hence ignore any errors
 473                          * and just continue. */
 474                         (void)ret;
 475                         prefaulted = 1;
 476                 }
 477
 478                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 479                                        user_data, page_do_bit17_swizzling,
 480                                        needs_clflush);
 481
 482                 mutex_lock(&dev->struct_mutex);
 483
 484 next_page:
 485                 mark_page_accessed(page);
 486
 487                 if (ret)
 488                         goto out;
 489
 490                 remain -= page_length;
 491                 user_data += page_length;
 492                 offset += page_length;
 493         }
 494
 495 out:
 496         i915_gem_object_unpin_pages(obj);
 497
 498         return ret;
 499 }
 500
 501 /**
 502  * Reads data from the object referenced by handle.
 503  *
 504  * On error, the contents of *data are undefined.
 505  */
 506 int
 507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 508                      struct drm_file *file)
 509 {
 510         struct drm_i915_gem_pread *args = data;
 511         struct drm_i915_gem_object *obj;
 512         int ret = 0;
 513
 514         if (args->size == 0)
 515                 return 0;
 516
 517         if (!access_ok(VERIFY_WRITE,
 518                        to_user_ptr(args->data_ptr),
 519                        args->size))
 520                 return -EFAULT;
 521
 522         ret = i915_mutex_lock_interruptible(dev);
 523         if (ret)
 524                 return ret;
 525
 526         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 527         if (&obj->base == NULL) {
 528                 ret = -ENOENT;
 529                 goto unlock;
 530         }
 531
 532         /* Bounds check source.  */
 533         if (args->offset > obj->base.size ||
 534             args->size > obj->base.size - args->offset) {
 535                 ret = -EINVAL;
 536                 goto out;
 537         }
 538
 539         /* prime objects have no backing filp to GEM pread/pwrite
 540          * pages from.
 541          */
 542         if (!obj->base.filp) {
 543                 ret = -EINVAL;
 544                 goto out;
 545         }
 546
 547         trace_i915_gem_object_pread(obj, args->offset, args->size);
 548
 549         ret = i915_gem_shmem_pread(dev, obj, args, file);
 550
 551 out:
 552         drm_gem_object_unreference(&obj->base);
 553 unlock:
 554         mutex_unlock(&dev->struct_mutex);
 555         return ret;
 556 }
 557
 558 /* This is the fast write path which cannot handle
 559  * page faults in the source data
 560  */
 561
 562 static inline int
 563 fast_user_write(struct io_mapping *mapping,
 564                 loff_t page_base, int page_offset,
 565                 char __user *user_data,
 566                 int length)
 567 {
 568         void __iomem *vaddr_atomic;
 569         void *vaddr;
 570         unsigned long unwritten;
 571
 572         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 573         /* We can use the cpu mem copy function because this is X86. */
 574         vaddr = (void __force*)vaddr_atomic + page_offset;
 575         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 576                                                       user_data, length);
 577         io_mapping_unmap_atomic(vaddr_atomic);
 578         return unwritten;
 579 }
 580
 581 /**
 582  * This is the fast pwrite path, where we copy the data directly from the
 583  * user into the GTT, uncached.
 584  */
 585 static int
 586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 587                          struct drm_i915_gem_object *obj,
 588                          struct drm_i915_gem_pwrite *args,
 589                          struct drm_file *file)
 590 {
 591         drm_i915_private_t *dev_priv = dev->dev_private;
 592         ssize_t remain;
 593         loff_t offset, page_base;
 594         char __user *user_data;
 595         int page_offset, page_length, ret;
 596
 597         ret = i915_gem_object_pin(obj, 0, true, true);
 598         if (ret)
 599                 goto out;
 600
 601         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 602         if (ret)
 603                 goto out_unpin;
 604
 605         ret = i915_gem_object_put_fence(obj);
 606         if (ret)
 607                 goto out_unpin;
 608
 609         user_data = to_user_ptr(args->data_ptr);
 610         remain = args->size;
 611
 612         offset = obj->gtt_offset + args->offset;
 613
 614         while (remain > 0) {
 615                 /* Operation in this page
 616                  *
 617                  * page_base = page offset within aperture
 618                  * page_offset = offset within page
 619                  * page_length = bytes to copy for this page
 620                  */
 621                 page_base = offset & PAGE_MASK;
 622                 page_offset = offset_in_page(offset);
 623                 page_length = remain;
 624                 if ((page_offset + remain) > PAGE_SIZE)
 625                         page_length = PAGE_SIZE - page_offset;
 626
 627                 /* If we get a fault while copying data, then (presumably) our
 628                  * source page isn't available.  Return the error and we'll
 629                  * retry in the slow path.
 630                  */
 631                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 632                                     page_offset, user_data, page_length)) {
 633                         ret = -EFAULT;
 634                         goto out_unpin;
 635                 }
 636
 637                 remain -= page_length;
 638                 user_data += page_length;
 639                 offset += page_length;
 640         }
 641
 642 out_unpin:
 643         i915_gem_object_unpin(obj);
 644 out:
 645         return ret;
 646 }
 647
 648 /* Per-page copy function for the shmem pwrite fastpath.
 649  * Flushes invalid cachelines before writing to the target if
 650  * needs_clflush_before is set and flushes out any written cachelines after
 651  * writing if needs_clflush is set. */
 652 static int
 653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 654                   char __user *user_data,
 655                   bool page_do_bit17_swizzling,
 656                   bool needs_clflush_before,
 657                   bool needs_clflush_after)
 658 {
 659         char *vaddr;
 660         int ret;
 661
 662         if (unlikely(page_do_bit17_swizzling))
 663                 return -EINVAL;
 664
 665         vaddr = kmap_atomic(page);
 666         if (needs_clflush_before)
 667                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 668                                        page_length);
 669         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 670                                                 user_data,
 671                                                 page_length);
 672         if (needs_clflush_after)
 673                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 674                                        page_length);
 675         kunmap_atomic(vaddr);
 676
 677         return ret ? -EFAULT : 0;
 678 }
 679
 680 /* Only difference to the fast-path function is that this can handle bit17
 681  * and uses non-atomic copy and kmap functions. */
 682 static int
 683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 684                   char __user *user_data,
 685                   bool page_do_bit17_swizzling,
 686                   bool needs_clflush_before,
 687                   bool needs_clflush_after)
 688 {
 689         char *vaddr;
 690         int ret;
 691
 692         vaddr = kmap(page);
 693         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 694                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 695                                              page_length,
 696                                              page_do_bit17_swizzling);
 697         if (page_do_bit17_swizzling)
 698                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 699                                                 user_data,
 700                                                 page_length);
 701         else
 702                 ret = __copy_from_user(vaddr + shmem_page_offset,
 703                                        user_data,
 704                                        page_length);
 705         if (needs_clflush_after)
 706                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 707                                              page_length,
 708                                              page_do_bit17_swizzling);
 709         kunmap(page);
 710
 711         return ret ? -EFAULT : 0;
 712 }
 713
 714 static int
 715 i915_gem_shmem_pwrite(struct drm_device *dev,
 716                       struct drm_i915_gem_object *obj,
 717                       struct drm_i915_gem_pwrite *args,
 718                       struct drm_file *file)
 719 {
 720         ssize_t remain;
 721         loff_t offset;
 722         char __user *user_data;
 723         int shmem_page_offset, page_length, ret = 0;
 724         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 725         int hit_slowpath = 0;
 726         int needs_clflush_after = 0;
 727         int needs_clflush_before = 0;
 728         struct sg_page_iter sg_iter;
 729
 730         user_data = to_user_ptr(args->data_ptr);
 731         remain = args->size;
 732
 733         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 734
 735         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 736                 /* If we're not in the cpu write domain, set ourself into the gtt
 737                  * write domain and manually flush cachelines (if required). This
 738                  * optimizes for the case when the gpu will use the data
 739                  * right away and we therefore have to clflush anyway. */
 740                 if (obj->cache_level == I915_CACHE_NONE)
 741                         needs_clflush_after = 1;
 742                 if (obj->gtt_space) {
 743                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 744                         if (ret)
 745                                 return ret;
 746                 }
 747         }
 748         /* Same trick applies for invalidate partially written cachelines before
 749          * writing.  */
 750         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 751             && obj->cache_level == I915_CACHE_NONE)
 752                 needs_clflush_before = 1;
 753
 754         ret = i915_gem_object_get_pages(obj);
 755         if (ret)
 756                 return ret;
 757
 758         i915_gem_object_pin_pages(obj);
 759
 760         offset = args->offset;
 761         obj->dirty = 1;
 762
 763         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 764                          offset >> PAGE_SHIFT) {
 765                 struct page *page = sg_page_iter_page(&sg_iter);
 766                 int partial_cacheline_write;
 767
 768                 if (remain <= 0)
 769                         break;
 770
 771                 /* Operation in this page
 772                  *
 773                  * shmem_page_offset = offset within page in shmem file
 774                  * page_length = bytes to copy for this page
 775                  */
 776                 shmem_page_offset = offset_in_page(offset);
 777
 778                 page_length = remain;
 779                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 780                         page_length = PAGE_SIZE - shmem_page_offset;
 781
 782                 /* If we don't overwrite a cacheline completely we need to be
 783                  * careful to have up-to-date data by first clflushing. Don't
 784                  * overcomplicate things and flush the entire patch. */
 785                 partial_cacheline_write = needs_clflush_before &&
 786                         ((shmem_page_offset | page_length)
 787                                 & (boot_cpu_data.x86_clflush_size - 1));
 788
 789                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 790                         (page_to_phys(page) & (1 << 17)) != 0;
 791
 792                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 793                                         user_data, page_do_bit17_swizzling,
 794                                         partial_cacheline_write,
 795                                         needs_clflush_after);
 796                 if (ret == 0)
 797                         goto next_page;
 798
 799                 hit_slowpath = 1;
 800                 mutex_unlock(&dev->struct_mutex);
 801                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 802                                         user_data, page_do_bit17_swizzling,
 803                                         partial_cacheline_write,
 804                                         needs_clflush_after);
 805
 806                 mutex_lock(&dev->struct_mutex);
 807
 808 next_page:
 809                 set_page_dirty(page);
 810                 mark_page_accessed(page);
 811
 812                 if (ret)
 813                         goto out;
 814
 815                 remain -= page_length;
 816                 user_data += page_length;
 817                 offset += page_length;
 818         }
 819
 820 out:
 821         i915_gem_object_unpin_pages(obj);
 822
 823         if (hit_slowpath) {
 824                 /*
 825                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 826                  * cachelines in-line while writing and the object moved
 827                  * out of the cpu write domain while we've dropped the lock.
 828                  */
 829                 if (!needs_clflush_after &&
 830                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 831                         i915_gem_clflush_object(obj);
 832                         i915_gem_chipset_flush(dev);
 833                 }
 834         }
 835
 836         if (needs_clflush_after)
 837                 i915_gem_chipset_flush(dev);
 838
 839         return ret;
 840 }
 841
 842 /**
 843  * Writes data to the object referenced by handle.
 844  *
 845  * On error, the contents of the buffer that were to be modified are undefined.
 846  */
 847 int
 848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 849                       struct drm_file *file)
 850 {
 851         struct drm_i915_gem_pwrite *args = data;
 852         struct drm_i915_gem_object *obj;
 853         int ret;
 854
 855         if (args->size == 0)
 856                 return 0;
 857
 858         if (!access_ok(VERIFY_READ,
 859                        to_user_ptr(args->data_ptr),
 860                        args->size))
 861                 return -EFAULT;
 862
 863         ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
 864                                            args->size);
 865         if (ret)
 866                 return -EFAULT;
 867
 868         ret = i915_mutex_lock_interruptible(dev);
 869         if (ret)
 870                 return ret;
 871
 872         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 873         if (&obj->base == NULL) {
 874                 ret = -ENOENT;
 875                 goto unlock;
 876         }
 877
 878         /* Bounds check destination. */
 879         if (args->offset > obj->base.size ||
 880             args->size > obj->base.size - args->offset) {
 881                 ret = -EINVAL;
 882                 goto out;
 883         }
 884
 885         /* prime objects have no backing filp to GEM pread/pwrite
 886          * pages from.
 887          */
 888         if (!obj->base.filp) {
 889                 ret = -EINVAL;
 890                 goto out;
 891         }
 892
 893         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 894
 895         ret = -EFAULT;
 896         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 897          * it would end up going through the fenced access, and we'll get
 898          * different detiling behavior between reading and writing.
 899          * pread/pwrite currently are reading and writing from the CPU
 900          * perspective, requiring manual detiling by the client.
 901          */
 902         if (obj->phys_obj) {
 903                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 904                 goto out;
 905         }
 906
 907         if (obj->cache_level == I915_CACHE_NONE &&
 908             obj->tiling_mode == I915_TILING_NONE &&
 909             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 910                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 911                 /* Note that the gtt paths might fail with non-page-backed user
 912                  * pointers (e.g. gtt mappings when moving data between
 913                  * textures). Fallback to the shmem path in that case. */
 914         }
 915
 916         if (ret == -EFAULT || ret == -ENOSPC)
 917                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 918
 919 out:
 920         drm_gem_object_unreference(&obj->base);
 921 unlock:
 922         mutex_unlock(&dev->struct_mutex);
 923         return ret;
 924 }
 925
 926 int
 927 i915_gem_check_wedge(struct i915_gpu_error *error,
 928                      bool interruptible)
 929 {
 930         if (i915_reset_in_progress(error)) {
 931                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 932                  * -EIO unconditionally for these. */
 933                 if (!interruptible)
 934                         return -EIO;
 935
 936                 /* Recovery complete, but the reset failed ... */
 937                 if (i915_terminally_wedged(error))
 938                         return -EIO;
 939
 940                 return -EAGAIN;
 941         }
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Compare seqno against outstanding lazy request. Emit a request if they are
 948  * equal.
 949  */
 950 static int
 951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 952 {
 953         int ret;
 954
 955         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 956
 957         ret = 0;
 958         if (seqno == ring->outstanding_lazy_request)
 959                 ret = i915_add_request(ring, NULL);
 960
 961         return ret;
 962 }
 963
 964 /**
 965  * __wait_seqno - wait until execution of seqno has finished
 966  * @ring: the ring expected to report seqno
 967  * @seqno: duh!
 968  * @reset_counter: reset sequence associated with the given seqno
 969  * @interruptible: do an interruptible wait (normally yes)
 970  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 971  *
 972  * Note: It is of utmost importance that the passed in seqno and reset_counter
 973  * values have been read by the caller in an smp safe manner. Where read-side
 974  * locks are involved, it is sufficient to read the reset_counter before
 975  * unlocking the lock that protects the seqno. For lockless tricks, the
 976  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 977  * inserted.
 978  *
 979  * Returns 0 if the seqno was found within the alloted time. Else returns the
 980  * errno with remaining time filled in timeout argument.
 981  */
 982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 983                         unsigned reset_counter,
 984                         bool interruptible, struct timespec *timeout)
 985 {
 986         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 987         struct timespec before, now, wait_time={1,0};
 988         unsigned long timeout_jiffies;
 989         long end;
 990         bool wait_forever = true;
 991         int ret;
 992
 993         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 994                 return 0;
 995
 996         trace_i915_gem_request_wait_begin(ring, seqno);
 997
 998         if (timeout != NULL) {
 999                 wait_time = *timeout;
1000                 wait_forever = false;
1001         }
1002
1003         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1004
1005         if (WARN_ON(!ring->irq_get(ring)))
1006                 return -ENODEV;
1007
1008         /* Record current time in case interrupted by signal, or wedged * */
1009         getrawmonotonic(&before);
1010
1011 #define EXIT_COND \
1012         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013          i915_reset_in_progress(&dev_priv->gpu_error) || \
1014          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1015         do {
1016                 if (interruptible)
1017                         end = wait_event_interruptible_timeout(ring->irq_queue,
1018                                                                EXIT_COND,
1019                                                                timeout_jiffies);
1020                 else
1021                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1022                                                  timeout_jiffies);
1023
1024                 /* We need to check whether any gpu reset happened in between
1025                  * the caller grabbing the seqno and now ... */
1026                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1027                         end = -EAGAIN;
1028
1029                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1030                  * gone. */
1031                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1032                 if (ret)
1033                         end = ret;
1034         } while (end == 0 && wait_forever);
1035
1036         getrawmonotonic(&now);
1037
1038         ring->irq_put(ring);
1039         trace_i915_gem_request_wait_end(ring, seqno);
1040 #undef EXIT_COND
1041
1042         if (timeout) {
1043                 struct timespec sleep_time = timespec_sub(now, before);
1044                 *timeout = timespec_sub(*timeout, sleep_time);
1045                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046                         set_normalized_timespec(timeout, 0, 0);
1047         }
1048
1049         switch (end) {
1050         case -EIO:
1051         case -EAGAIN: /* Wedged */
1052         case -ERESTARTSYS: /* Signal */
1053                 return (int)end;
1054         case 0: /* Timeout */
1055                 return -ETIME;
1056         default: /* Completed */
1057                 WARN_ON(end < 0); /* We're not aware of other errors */
1058                 return 0;
1059         }
1060 }
1061
1062 /**
1063  * Waits for a sequence number to be signaled, and cleans up the
1064  * request and object lists appropriately for that event.
1065  */
1066 int
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1068 {
1069         struct drm_device *dev = ring->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         bool interruptible = dev_priv->mm.interruptible;
1072         int ret;
1073
1074         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1075         BUG_ON(seqno == 0);
1076
1077         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1078         if (ret)
1079                 return ret;
1080
1081         ret = i915_gem_check_olr(ring, seqno);
1082         if (ret)
1083                 return ret;
1084
1085         return __wait_seqno(ring, seqno,
1086                             atomic_read(&dev_priv->gpu_error.reset_counter),
1087                             interruptible, NULL);
1088 }
1089
1090 static int
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1092                                      struct intel_ring_buffer *ring)
1093 {
1094         i915_gem_retire_requests_ring(ring);
1095
1096         /* Manually manage the write flush as we may have not yet
1097          * retired the buffer.
1098          *
1099          * Note that the last_write_seqno is always the earlier of
1100          * the two (read/write) seqno, so if we haved successfully waited,
1101          * we know we have passed the last write.
1102          */
1103         obj->last_write_seqno = 0;
1104         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1105
1106         return 0;
1107 }
1108
1109 /**
1110  * Ensures that all rendering to the object has completed and the object is
1111  * safe to unbind from the GTT or access from the CPU.
1112  */
1113 static __must_check int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1115                                bool readonly)
1116 {
1117         struct intel_ring_buffer *ring = obj->ring;
1118         u32 seqno;
1119         int ret;
1120
1121         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1122         if (seqno == 0)
1123                 return 0;
1124
1125         ret = i915_wait_seqno(ring, seqno);
1126         if (ret)
1127                 return ret;
1128
1129         return i915_gem_object_wait_rendering__tail(obj, ring);
1130 }
1131
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133  * as the object state may change during this call.
1134  */
1135 static __must_check int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1137                                             bool readonly)
1138 {
1139         struct drm_device *dev = obj->base.dev;
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141         struct intel_ring_buffer *ring = obj->ring;
1142         unsigned reset_counter;
1143         u32 seqno;
1144         int ret;
1145
1146         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1147         BUG_ON(!dev_priv->mm.interruptible);
1148
1149         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1150         if (seqno == 0)
1151                 return 0;
1152
1153         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1154         if (ret)
1155                 return ret;
1156
1157         ret = i915_gem_check_olr(ring, seqno);
1158         if (ret)
1159                 return ret;
1160
1161         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1162         mutex_unlock(&dev->struct_mutex);
1163         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1164         mutex_lock(&dev->struct_mutex);
1165         if (ret)
1166                 return ret;
1167
1168         return i915_gem_object_wait_rendering__tail(obj, ring);
1169 }
1170
1171 /**
1172  * Called when user space prepares to use an object with the CPU, either
1173  * through the mmap ioctl's mapping or a GTT mapping.
1174  */
1175 int
1176 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1177                           struct drm_file *file)
1178 {
1179         struct drm_i915_gem_set_domain *args = data;
1180         struct drm_i915_gem_object *obj;
1181         uint32_t read_domains = args->read_domains;
1182         uint32_t write_domain = args->write_domain;
1183         int ret;
1184
1185         /* Only handle setting domains to types used by the CPU. */
1186         if (write_domain & I915_GEM_GPU_DOMAINS)
1187                 return -EINVAL;
1188
1189         if (read_domains & I915_GEM_GPU_DOMAINS)
1190                 return -EINVAL;
1191
1192         /* Having something in the write domain implies it's in the read
1193          * domain, and only that read domain.  Enforce that in the request.
1194          */
1195         if (write_domain != 0 && read_domains != write_domain)
1196                 return -EINVAL;
1197
1198         ret = i915_mutex_lock_interruptible(dev);
1199         if (ret)
1200                 return ret;
1201
1202         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1203         if (&obj->base == NULL) {
1204                 ret = -ENOENT;
1205                 goto unlock;
1206         }
1207
1208         /* Try to flush the object off the GPU without holding the lock.
1209          * We will repeat the flush holding the lock in the normal manner
1210          * to catch cases where we are gazumped.
1211          */
1212         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1213         if (ret)
1214                 goto unref;
1215
1216         if (read_domains & I915_GEM_DOMAIN_GTT) {
1217                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1218
1219                 /* Silently promote "you're not bound, there was nothing to do"
1220                  * to success, since the client was just asking us to
1221                  * make sure everything was done.
1222                  */
1223                 if (ret == -EINVAL)
1224                         ret = 0;
1225         } else {
1226                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1227         }
1228
1229 unref:
1230         drm_gem_object_unreference(&obj->base);
1231 unlock:
1232         mutex_unlock(&dev->struct_mutex);
1233         return ret;
1234 }
1235
1236 /**
1237  * Called when user space has done writes to this buffer
1238  */
1239 int
1240 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1241                          struct drm_file *file)
1242 {
1243         struct drm_i915_gem_sw_finish *args = data;
1244         struct drm_i915_gem_object *obj;
1245         int ret = 0;
1246
1247         ret = i915_mutex_lock_interruptible(dev);
1248         if (ret)
1249                 return ret;
1250
1251         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252         if (&obj->base == NULL) {
1253                 ret = -ENOENT;
1254                 goto unlock;
1255         }
1256
1257         /* Pinned buffers may be scanout, so flush the cache */
1258         if (obj->pin_count)
1259                 i915_gem_object_flush_cpu_write_domain(obj);
1260
1261         drm_gem_object_unreference(&obj->base);
1262 unlock:
1263         mutex_unlock(&dev->struct_mutex);
1264         return ret;
1265 }
1266
1267 /**
1268  * Maps the contents of an object, returning the address it is mapped
1269  * into.
1270  *
1271  * While the mapping holds a reference on the contents of the object, it doesn't
1272  * imply a ref on the object itself.
1273  */
1274 int
1275 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1276                     struct drm_file *file)
1277 {
1278         struct drm_i915_gem_mmap *args = data;
1279         struct drm_gem_object *obj;
1280         unsigned long addr;
1281
1282         obj = drm_gem_object_lookup(dev, file, args->handle);
1283         if (obj == NULL)
1284                 return -ENOENT;
1285
1286         /* prime objects have no backing filp to GEM mmap
1287          * pages from.
1288          */
1289         if (!obj->filp) {
1290                 drm_gem_object_unreference_unlocked(obj);
1291                 return -EINVAL;
1292         }
1293
1294         addr = vm_mmap(obj->filp, 0, args->size,
1295                        PROT_READ | PROT_WRITE, MAP_SHARED,
1296                        args->offset);
1297         drm_gem_object_unreference_unlocked(obj);
1298         if (IS_ERR((void *)addr))
1299                 return addr;
1300
1301         args->addr_ptr = (uint64_t) addr;
1302
1303         return 0;
1304 }
1305
1306 /**
1307  * i915_gem_fault - fault a page into the GTT
1308  * vma: VMA in question
1309  * vmf: fault info
1310  *
1311  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312  * from userspace.  The fault handler takes care of binding the object to
1313  * the GTT (if needed), allocating and programming a fence register (again,
1314  * only if needed based on whether the old reg is still valid or the object
1315  * is tiled) and inserting a new PTE into the faulting process.
1316  *
1317  * Note that the faulting process may involve evicting existing objects
1318  * from the GTT and/or fence registers to make room.  So performance may
1319  * suffer if the GTT working set is large or there are few fence registers
1320  * left.
1321  */
1322 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1323 {
1324         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1325         struct drm_device *dev = obj->base.dev;
1326         drm_i915_private_t *dev_priv = dev->dev_private;
1327         pgoff_t page_offset;
1328         unsigned long pfn;
1329         int ret = 0;
1330         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1331
1332         /* We don't use vmf->pgoff since that has the fake offset */
1333         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1334                 PAGE_SHIFT;
1335
1336         ret = i915_mutex_lock_interruptible(dev);
1337         if (ret)
1338                 goto out;
1339
1340         trace_i915_gem_object_fault(obj, page_offset, true, write);
1341
1342         /* Access to snoopable pages through the GTT is incoherent. */
1343         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1344                 ret = -EINVAL;
1345                 goto unlock;
1346         }
1347
1348         /* Now bind it into the GTT if needed */
1349         ret = i915_gem_object_pin(obj, 0, true, false);
1350         if (ret)
1351                 goto unlock;
1352
1353         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1354         if (ret)
1355                 goto unpin;
1356
1357         ret = i915_gem_object_get_fence(obj);
1358         if (ret)
1359                 goto unpin;
1360
1361         obj->fault_mappable = true;
1362
1363         pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1364                 page_offset;
1365
1366         /* Finally, remap it using the new GTT offset */
1367         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1368 unpin:
1369         i915_gem_object_unpin(obj);
1370 unlock:
1371         mutex_unlock(&dev->struct_mutex);
1372 out:
1373         switch (ret) {
1374         case -EIO:
1375                 /* If this -EIO is due to a gpu hang, give the reset code a
1376                  * chance to clean up the mess. Otherwise return the proper
1377                  * SIGBUS. */
1378                 if (i915_terminally_wedged(&dev_priv->gpu_error))
1379                         return VM_FAULT_SIGBUS;
1380         case -EAGAIN:
1381                 /* Give the error handler a chance to run and move the
1382                  * objects off the GPU active list. Next time we service the
1383                  * fault, we should be able to transition the page into the
1384                  * GTT without touching the GPU (and so avoid further
1385                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1386                  * with coherency, just lost writes.
1387                  */
1388                 set_need_resched();
1389         case 0:
1390         case -ERESTARTSYS:
1391         case -EINTR:
1392         case -EBUSY:
1393                 /*
1394                  * EBUSY is ok: this just means that another thread
1395                  * already did the job.
1396                  */
1397                 return VM_FAULT_NOPAGE;
1398         case -ENOMEM:
1399                 return VM_FAULT_OOM;
1400         case -ENOSPC:
1401                 return VM_FAULT_SIGBUS;
1402         default:
1403                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1404                 return VM_FAULT_SIGBUS;
1405         }
1406 }
1407
1408 /**
1409  * i915_gem_release_mmap - remove physical page mappings
1410  * @obj: obj in question
1411  *
1412  * Preserve the reservation of the mmapping with the DRM core code, but
1413  * relinquish ownership of the pages back to the system.
1414  *
1415  * It is vital that we remove the page mapping if we have mapped a tiled
1416  * object through the GTT and then lose the fence register due to
1417  * resource pressure. Similarly if the object has been moved out of the
1418  * aperture, than pages mapped into userspace must be revoked. Removing the
1419  * mapping will then trigger a page fault on the next user access, allowing
1420  * fixup by i915_gem_fault().
1421  */
1422 void
1423 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1424 {
1425         if (!obj->fault_mappable)
1426                 return;
1427
1428         if (obj->base.dev->dev_mapping)
1429                 unmap_mapping_range(obj->base.dev->dev_mapping,
1430                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1431                                     obj->base.size, 1);
1432
1433         obj->fault_mappable = false;
1434 }
1435
1436 uint32_t
1437 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1438 {
1439         uint32_t gtt_size;
1440
1441         if (INTEL_INFO(dev)->gen >= 4 ||
1442             tiling_mode == I915_TILING_NONE)
1443                 return size;
1444
1445         /* Previous chips need a power-of-two fence region when tiling */
1446         if (INTEL_INFO(dev)->gen == 3)
1447                 gtt_size = 1024*1024;
1448         else
1449                 gtt_size = 512*1024;
1450
1451         while (gtt_size < size)
1452                 gtt_size <<= 1;
1453
1454         return gtt_size;
1455 }
1456
1457 /**
1458  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1459  * @obj: object to check
1460  *
1461  * Return the required GTT alignment for an object, taking into account
1462  * potential fence register mapping.
1463  */
1464 uint32_t
1465 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1466                            int tiling_mode, bool fenced)
1467 {
1468         /*
1469          * Minimum alignment is 4k (GTT page size), but might be greater
1470          * if a fence register is needed for the object.
1471          */
1472         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1473             tiling_mode == I915_TILING_NONE)
1474                 return 4096;
1475
1476         /*
1477          * Previous chips need to be aligned to the size of the smallest
1478          * fence register that can contain the object.
1479          */
1480         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1481 }
1482
1483 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1484 {
1485         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1486         int ret;
1487
1488         if (obj->base.map_list.map)
1489                 return 0;
1490
1491         dev_priv->mm.shrinker_no_lock_stealing = true;
1492
1493         ret = drm_gem_create_mmap_offset(&obj->base);
1494         if (ret != -ENOSPC)
1495                 goto out;
1496
1497         /* Badly fragmented mmap space? The only way we can recover
1498          * space is by destroying unwanted objects. We can't randomly release
1499          * mmap_offsets as userspace expects them to be persistent for the
1500          * lifetime of the objects. The closest we can is to release the
1501          * offsets on purgeable objects by truncating it and marking it purged,
1502          * which prevents userspace from ever using that object again.
1503          */
1504         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1505         ret = drm_gem_create_mmap_offset(&obj->base);
1506         if (ret != -ENOSPC)
1507                 goto out;
1508
1509         i915_gem_shrink_all(dev_priv);
1510         ret = drm_gem_create_mmap_offset(&obj->base);
1511 out:
1512         dev_priv->mm.shrinker_no_lock_stealing = false;
1513
1514         return ret;
1515 }
1516
1517 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1518 {
1519         if (!obj->base.map_list.map)
1520                 return;
1521
1522         drm_gem_free_mmap_offset(&obj->base);
1523 }
1524
1525 int
1526 i915_gem_mmap_gtt(struct drm_file *file,
1527                   struct drm_device *dev,
1528                   uint32_t handle,
1529                   uint64_t *offset)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct drm_i915_gem_object *obj;
1533         int ret;
1534
1535         ret = i915_mutex_lock_interruptible(dev);
1536         if (ret)
1537                 return ret;
1538
1539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1540         if (&obj->base == NULL) {
1541                 ret = -ENOENT;
1542                 goto unlock;
1543         }
1544
1545         if (obj->base.size > dev_priv->gtt.mappable_end) {
1546                 ret = -E2BIG;
1547                 goto out;
1548         }
1549
1550         if (obj->madv != I915_MADV_WILLNEED) {
1551                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1552                 ret = -EINVAL;
1553                 goto out;
1554         }
1555
1556         ret = i915_gem_object_create_mmap_offset(obj);
1557         if (ret)
1558                 goto out;
1559
1560         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1561
1562 out:
1563         drm_gem_object_unreference(&obj->base);
1564 unlock:
1565         mutex_unlock(&dev->struct_mutex);
1566         return ret;
1567 }
1568
1569 /**
1570  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1571  * @dev: DRM device
1572  * @data: GTT mapping ioctl data
1573  * @file: GEM object info
1574  *
1575  * Simply returns the fake offset to userspace so it can mmap it.
1576  * The mmap call will end up in drm_gem_mmap(), which will set things
1577  * up so we can get faults in the handler above.
1578  *
1579  * The fault handler will take care of binding the object into the GTT
1580  * (since it may have been evicted to make room for something), allocating
1581  * a fence register, and mapping the appropriate aperture address into
1582  * userspace.
1583  */
1584 int
1585 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1586                         struct drm_file *file)
1587 {
1588         struct drm_i915_gem_mmap_gtt *args = data;
1589
1590         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1591 }
1592
1593 /* Immediately discard the backing storage */
1594 static void
1595 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1596 {
1597         struct inode *inode;
1598
1599         i915_gem_object_free_mmap_offset(obj);
1600
1601         if (obj->base.filp == NULL)
1602                 return;
1603
1604         /* Our goal here is to return as much of the memory as
1605          * is possible back to the system as we are called from OOM.
1606          * To do this we must instruct the shmfs to drop all of its
1607          * backing pages, *now*.
1608          */
1609         inode = file_inode(obj->base.filp);
1610         shmem_truncate_range(inode, 0, (loff_t)-1);
1611
1612         obj->madv = __I915_MADV_PURGED;
1613 }
1614
1615 static inline int
1616 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1617 {
1618         return obj->madv == I915_MADV_DONTNEED;
1619 }
1620
1621 static void
1622 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1623 {
1624         struct sg_page_iter sg_iter;
1625         int ret;
1626
1627         BUG_ON(obj->madv == __I915_MADV_PURGED);
1628
1629         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1630         if (ret) {
1631                 /* In the event of a disaster, abandon all caches and
1632                  * hope for the best.
1633                  */
1634                 WARN_ON(ret != -EIO);
1635                 i915_gem_clflush_object(obj);
1636                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1637         }
1638
1639         if (i915_gem_object_needs_bit17_swizzle(obj))
1640                 i915_gem_object_save_bit_17_swizzle(obj);
1641
1642         if (obj->madv == I915_MADV_DONTNEED)
1643                 obj->dirty = 0;
1644
1645         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1646                 struct page *page = sg_page_iter_page(&sg_iter);
1647
1648                 if (obj->dirty)
1649                         set_page_dirty(page);
1650
1651                 if (obj->madv == I915_MADV_WILLNEED)
1652                         mark_page_accessed(page);
1653
1654                 page_cache_release(page);
1655         }
1656         obj->dirty = 0;
1657
1658         sg_free_table(obj->pages);
1659         kfree(obj->pages);
1660 }
1661
1662 int
1663 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1664 {
1665         const struct drm_i915_gem_object_ops *ops = obj->ops;
1666
1667         if (obj->pages == NULL)
1668                 return 0;
1669
1670         BUG_ON(obj->gtt_space);
1671
1672         if (obj->pages_pin_count)
1673                 return -EBUSY;
1674
1675         /* ->put_pages might need to allocate memory for the bit17 swizzle
1676          * array, hence protect them from being reaped by removing them from gtt
1677          * lists early. */
1678         list_del(&obj->global_list);
1679
1680         ops->put_pages(obj);
1681         obj->pages = NULL;
1682
1683         if (i915_gem_object_is_purgeable(obj))
1684                 i915_gem_object_truncate(obj);
1685
1686         return 0;
1687 }
1688
1689 static long
1690 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1691                   bool purgeable_only)
1692 {
1693         struct drm_i915_gem_object *obj, *next;
1694         long count = 0;
1695
1696         list_for_each_entry_safe(obj, next,
1697                                  &dev_priv->mm.unbound_list,
1698                                  global_list) {
1699                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1700                     i915_gem_object_put_pages(obj) == 0) {
1701                         count += obj->base.size >> PAGE_SHIFT;
1702                         if (count >= target)
1703                                 return count;
1704                 }
1705         }
1706
1707         list_for_each_entry_safe(obj, next,
1708                                  &dev_priv->mm.inactive_list,
1709                                  mm_list) {
1710                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1711                     i915_gem_object_unbind(obj) == 0 &&
1712                     i915_gem_object_put_pages(obj) == 0) {
1713                         count += obj->base.size >> PAGE_SHIFT;
1714                         if (count >= target)
1715                                 return count;
1716                 }
1717         }
1718
1719         return count;
1720 }
1721
1722 static long
1723 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1724 {
1725         return __i915_gem_shrink(dev_priv, target, true);
1726 }
1727
1728 static void
1729 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1730 {
1731         struct drm_i915_gem_object *obj, *next;
1732
1733         i915_gem_evict_everything(dev_priv->dev);
1734
1735         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1736                                  global_list)
1737                 i915_gem_object_put_pages(obj);
1738 }
1739
1740 static int
1741 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1742 {
1743         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1744         int page_count, i;
1745         struct address_space *mapping;
1746         struct sg_table *st;
1747         struct scatterlist *sg;
1748         struct sg_page_iter sg_iter;
1749         struct page *page;
1750         unsigned long last_pfn = 0;     /* suppress gcc warning */
1751         gfp_t gfp;
1752
1753         /* Assert that the object is not currently in any GPU domain. As it
1754          * wasn't in the GTT, there shouldn't be any way it could have been in
1755          * a GPU cache
1756          */
1757         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1758         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1759
1760         st = kmalloc(sizeof(*st), GFP_KERNEL);
1761         if (st == NULL)
1762                 return -ENOMEM;
1763
1764         page_count = obj->base.size / PAGE_SIZE;
1765         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1766                 sg_free_table(st);
1767                 kfree(st);
1768                 return -ENOMEM;
1769         }
1770
1771         /* Get the list of pages out of our struct file.  They'll be pinned
1772          * at this point until we release them.
1773          *
1774          * Fail silently without starting the shrinker
1775          */
1776         mapping = file_inode(obj->base.filp)->i_mapping;
1777         gfp = mapping_gfp_mask(mapping);
1778         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1779         gfp &= ~(__GFP_IO | __GFP_WAIT);
1780         sg = st->sgl;
1781         st->nents = 0;
1782         for (i = 0; i < page_count; i++) {
1783                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1784                 if (IS_ERR(page)) {
1785                         i915_gem_purge(dev_priv, page_count);
1786                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1787                 }
1788                 if (IS_ERR(page)) {
1789                         /* We've tried hard to allocate the memory by reaping
1790                          * our own buffer, now let the real VM do its job and
1791                          * go down in flames if truly OOM.
1792                          */
1793                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1794                         gfp |= __GFP_IO | __GFP_WAIT;
1795
1796                         i915_gem_shrink_all(dev_priv);
1797                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1798                         if (IS_ERR(page))
1799                                 goto err_pages;
1800
1801                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1802                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1803                 }
1804 #ifdef CONFIG_SWIOTLB
1805                 if (swiotlb_nr_tbl()) {
1806                         st->nents++;
1807                         sg_set_page(sg, page, PAGE_SIZE, 0);
1808                         sg = sg_next(sg);
1809                         continue;
1810                 }
1811 #endif
1812                 if (!i || page_to_pfn(page) != last_pfn + 1) {
1813                         if (i)
1814                                 sg = sg_next(sg);
1815                         st->nents++;
1816                         sg_set_page(sg, page, PAGE_SIZE, 0);
1817                 } else {
1818                         sg->length += PAGE_SIZE;
1819                 }
1820                 last_pfn = page_to_pfn(page);
1821         }
1822 #ifdef CONFIG_SWIOTLB
1823         if (!swiotlb_nr_tbl())
1824 #endif
1825                 sg_mark_end(sg);
1826         obj->pages = st;
1827
1828         if (i915_gem_object_needs_bit17_swizzle(obj))
1829                 i915_gem_object_do_bit_17_swizzle(obj);
1830
1831         return 0;
1832
1833 err_pages:
1834         sg_mark_end(sg);
1835         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1836                 page_cache_release(sg_page_iter_page(&sg_iter));
1837         sg_free_table(st);
1838         kfree(st);
1839         return PTR_ERR(page);
1840 }
1841
1842 /* Ensure that the associated pages are gathered from the backing storage
1843  * and pinned into our object. i915_gem_object_get_pages() may be called
1844  * multiple times before they are released by a single call to
1845  * i915_gem_object_put_pages() - once the pages are no longer referenced
1846  * either as a result of memory pressure (reaping pages under the shrinker)
1847  * or as the object is itself released.
1848  */
1849 int
1850 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1851 {
1852         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1853         const struct drm_i915_gem_object_ops *ops = obj->ops;
1854         int ret;
1855
1856         if (obj->pages)
1857                 return 0;
1858
1859         if (obj->madv != I915_MADV_WILLNEED) {
1860                 DRM_ERROR("Attempting to obtain a purgeable object\n");
1861                 return -EINVAL;
1862         }
1863
1864         BUG_ON(obj->pages_pin_count);
1865
1866         ret = ops->get_pages(obj);
1867         if (ret)
1868                 return ret;
1869
1870         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1871         return 0;
1872 }
1873
1874 void
1875 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1876                                struct intel_ring_buffer *ring)
1877 {
1878         struct drm_device *dev = obj->base.dev;
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         u32 seqno = intel_ring_get_seqno(ring);
1881
1882         BUG_ON(ring == NULL);
1883         obj->ring = ring;
1884
1885         /* Add a reference if we're newly entering the active list. */
1886         if (!obj->active) {
1887                 drm_gem_object_reference(&obj->base);
1888                 obj->active = 1;
1889         }
1890
1891         /* Move from whatever list we were on to the tail of execution. */
1892         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1893         list_move_tail(&obj->ring_list, &ring->active_list);
1894
1895         obj->last_read_seqno = seqno;
1896
1897         if (obj->fenced_gpu_access) {
1898                 obj->last_fenced_seqno = seqno;
1899
1900                 /* Bump MRU to take account of the delayed flush */
1901                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1902                         struct drm_i915_fence_reg *reg;
1903
1904                         reg = &dev_priv->fence_regs[obj->fence_reg];
1905                         list_move_tail(&reg->lru_list,
1906                                        &dev_priv->mm.fence_list);
1907                 }
1908         }
1909 }
1910
1911 static void
1912 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1913 {
1914         struct drm_device *dev = obj->base.dev;
1915         struct drm_i915_private *dev_priv = dev->dev_private;
1916
1917         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1918         BUG_ON(!obj->active);
1919
1920         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1921
1922         list_del_init(&obj->ring_list);
1923         obj->ring = NULL;
1924
1925         obj->last_read_seqno = 0;
1926         obj->last_write_seqno = 0;
1927         obj->base.write_domain = 0;
1928
1929         obj->last_fenced_seqno = 0;
1930         obj->fenced_gpu_access = false;
1931
1932         obj->active = 0;
1933         drm_gem_object_unreference(&obj->base);
1934
1935         WARN_ON(i915_verify_lists(dev));
1936 }
1937
1938 static int
1939 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1940 {
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct intel_ring_buffer *ring;
1943         int ret, i, j;
1944
1945         /* Carefully retire all requests without writing to the rings */
1946         for_each_ring(ring, dev_priv, i) {
1947                 ret = intel_ring_idle(ring);
1948                 if (ret)
1949                         return ret;
1950         }
1951         i915_gem_retire_requests(dev);
1952
1953         /* Finally reset hw state */
1954         for_each_ring(ring, dev_priv, i) {
1955                 intel_ring_init_seqno(ring, seqno);
1956
1957                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1958                         ring->sync_seqno[j] = 0;
1959         }
1960
1961         return 0;
1962 }
1963
1964 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1965 {
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         int ret;
1968
1969         if (seqno == 0)
1970                 return -EINVAL;
1971
1972         /* HWS page needs to be set less than what we
1973          * will inject to ring
1974          */
1975         ret = i915_gem_init_seqno(dev, seqno - 1);
1976         if (ret)
1977                 return ret;
1978
1979         /* Carefully set the last_seqno value so that wrap
1980          * detection still works
1981          */
1982         dev_priv->next_seqno = seqno;
1983         dev_priv->last_seqno = seqno - 1;
1984         if (dev_priv->last_seqno == 0)
1985                 dev_priv->last_seqno--;
1986
1987         return 0;
1988 }
1989
1990 int
1991 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1992 {
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994
1995         /* reserve 0 for non-seqno */
1996         if (dev_priv->next_seqno == 0) {
1997                 int ret = i915_gem_init_seqno(dev, 0);
1998                 if (ret)
1999                         return ret;
2000
2001                 dev_priv->next_seqno = 1;
2002         }
2003
2004         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2005         return 0;
2006 }
2007
2008 int __i915_add_request(struct intel_ring_buffer *ring,
2009                        struct drm_file *file,
2010                        struct drm_i915_gem_object *obj,
2011                        u32 *out_seqno)
2012 {
2013         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2014         struct drm_i915_gem_request *request;
2015         u32 request_ring_position, request_start;
2016         int was_empty;
2017         int ret;
2018
2019         request_start = intel_ring_get_tail(ring);
2020         /*
2021          * Emit any outstanding flushes - execbuf can fail to emit the flush
2022          * after having emitted the batchbuffer command. Hence we need to fix
2023          * things up similar to emitting the lazy request. The difference here
2024          * is that the flush _must_ happen before the next request, no matter
2025          * what.
2026          */
2027         ret = intel_ring_flush_all_caches(ring);
2028         if (ret)
2029                 return ret;
2030
2031         request = kmalloc(sizeof(*request), GFP_KERNEL);
2032         if (request == NULL)
2033                 return -ENOMEM;
2034
2035
2036         /* Record the position of the start of the request so that
2037          * should we detect the updated seqno part-way through the
2038          * GPU processing the request, we never over-estimate the
2039          * position of the head.
2040          */
2041         request_ring_position = intel_ring_get_tail(ring);
2042
2043         ret = ring->add_request(ring);
2044         if (ret) {
2045                 kfree(request);
2046                 return ret;
2047         }
2048
2049         request->seqno = intel_ring_get_seqno(ring);
2050         request->ring = ring;
2051         request->head = request_start;
2052         request->tail = request_ring_position;
2053         request->ctx = ring->last_context;
2054         request->batch_obj = obj;
2055
2056         /* Whilst this request exists, batch_obj will be on the
2057          * active_list, and so will hold the active reference. Only when this
2058          * request is retired will the the batch_obj be moved onto the
2059          * inactive_list and lose its active reference. Hence we do not need
2060          * to explicitly hold another reference here.
2061          */
2062
2063         if (request->ctx)
2064                 i915_gem_context_reference(request->ctx);
2065
2066         request->emitted_jiffies = jiffies;
2067         was_empty = list_empty(&ring->request_list);
2068         list_add_tail(&request->list, &ring->request_list);
2069         request->file_priv = NULL;
2070
2071         if (file) {
2072                 struct drm_i915_file_private *file_priv = file->driver_priv;
2073
2074                 spin_lock(&file_priv->mm.lock);
2075                 request->file_priv = file_priv;
2076                 list_add_tail(&request->client_list,
2077                               &file_priv->mm.request_list);
2078                 spin_unlock(&file_priv->mm.lock);
2079         }
2080
2081         trace_i915_gem_request_add(ring, request->seqno);
2082         ring->outstanding_lazy_request = 0;
2083
2084         if (!dev_priv->mm.suspended) {
2085                 if (i915_enable_hangcheck) {
2086                         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2087                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2088                 }
2089                 if (was_empty) {
2090                         queue_delayed_work(dev_priv->wq,
2091                                            &dev_priv->mm.retire_work,
2092                                            round_jiffies_up_relative(HZ));
2093                         intel_mark_busy(dev_priv->dev);
2094                 }
2095         }
2096
2097         if (out_seqno)
2098                 *out_seqno = request->seqno;
2099         return 0;
2100 }
2101
2102 static inline void
2103 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2104 {
2105         struct drm_i915_file_private *file_priv = request->file_priv;
2106
2107         if (!file_priv)
2108                 return;
2109
2110         spin_lock(&file_priv->mm.lock);
2111         if (request->file_priv) {
2112                 list_del(&request->client_list);
2113                 request->file_priv = NULL;
2114         }
2115         spin_unlock(&file_priv->mm.lock);
2116 }
2117
2118 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2119 {
2120         if (acthd >= obj->gtt_offset &&
2121             acthd < obj->gtt_offset + obj->base.size)
2122                 return true;
2123
2124         return false;
2125 }
2126
2127 static bool i915_head_inside_request(const u32 acthd_unmasked,
2128                                      const u32 request_start,
2129                                      const u32 request_end)
2130 {
2131         const u32 acthd = acthd_unmasked & HEAD_ADDR;
2132
2133         if (request_start < request_end) {
2134                 if (acthd >= request_start && acthd < request_end)
2135                         return true;
2136         } else if (request_start > request_end) {
2137                 if (acthd >= request_start || acthd < request_end)
2138                         return true;
2139         }
2140
2141         return false;
2142 }
2143
2144 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2145                                 const u32 acthd, bool *inside)
2146 {
2147         /* There is a possibility that unmasked head address
2148          * pointing inside the ring, matches the batch_obj address range.
2149          * However this is extremely unlikely.
2150          */
2151
2152         if (request->batch_obj) {
2153                 if (i915_head_inside_object(acthd, request->batch_obj)) {
2154                         *inside = true;
2155                         return true;
2156                 }
2157         }
2158
2159         if (i915_head_inside_request(acthd, request->head, request->tail)) {
2160                 *inside = false;
2161                 return true;
2162         }
2163
2164         return false;
2165 }
2166
2167 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2168                                   struct drm_i915_gem_request *request,
2169                                   u32 acthd)
2170 {
2171         struct i915_ctx_hang_stats *hs = NULL;
2172         bool inside, guilty;
2173
2174         /* Innocent until proven guilty */
2175         guilty = false;
2176
2177         if (ring->hangcheck.action != wait &&
2178             i915_request_guilty(request, acthd, &inside)) {
2179                 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2180                           ring->name,
2181                           inside ? "inside" : "flushing",
2182                           request->batch_obj ?
2183                           request->batch_obj->gtt_offset : 0,
2184                           request->ctx ? request->ctx->id : 0,
2185                           acthd);
2186
2187                 guilty = true;
2188         }
2189
2190         /* If contexts are disabled or this is the default context, use
2191          * file_priv->reset_state
2192          */
2193         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2194                 hs = &request->ctx->hang_stats;
2195         else if (request->file_priv)
2196                 hs = &request->file_priv->hang_stats;
2197
2198         if (hs) {
2199                 if (guilty)
2200                         hs->batch_active++;
2201                 else
2202                         hs->batch_pending++;
2203         }
2204 }
2205
2206 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2207 {
2208         list_del(&request->list);
2209         i915_gem_request_remove_from_client(request);
2210
2211         if (request->ctx)
2212                 i915_gem_context_unreference(request->ctx);
2213
2214         kfree(request);
2215 }
2216
2217 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2218                                       struct intel_ring_buffer *ring)
2219 {
2220         u32 completed_seqno;
2221         u32 acthd;
2222
2223         acthd = intel_ring_get_active_head(ring);
2224         completed_seqno = ring->get_seqno(ring, false);
2225
2226         while (!list_empty(&ring->request_list)) {
2227                 struct drm_i915_gem_request *request;
2228
2229                 request = list_first_entry(&ring->request_list,
2230                                            struct drm_i915_gem_request,
2231                                            list);
2232
2233                 if (request->seqno > completed_seqno)
2234                         i915_set_reset_status(ring, request, acthd);
2235
2236                 i915_gem_free_request(request);
2237         }
2238
2239         while (!list_empty(&ring->active_list)) {
2240                 struct drm_i915_gem_object *obj;
2241
2242                 obj = list_first_entry(&ring->active_list,
2243                                        struct drm_i915_gem_object,
2244                                        ring_list);
2245
2246                 i915_gem_object_move_to_inactive(obj);
2247         }
2248 }
2249
2250 void i915_gem_restore_fences(struct drm_device *dev)
2251 {
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         int i;
2254
2255         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2256                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2257                 i915_gem_write_fence(dev, i, reg->obj);
2258         }
2259 }
2260
2261 void i915_gem_reset(struct drm_device *dev)
2262 {
2263         struct drm_i915_private *dev_priv = dev->dev_private;
2264         struct drm_i915_gem_object *obj;
2265         struct intel_ring_buffer *ring;
2266         int i;
2267
2268         for_each_ring(ring, dev_priv, i)
2269                 i915_gem_reset_ring_lists(dev_priv, ring);
2270
2271         /* Move everything out of the GPU domains to ensure we do any
2272          * necessary invalidation upon reuse.
2273          */
2274         list_for_each_entry(obj,
2275                             &dev_priv->mm.inactive_list,
2276                             mm_list)
2277         {
2278                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2279         }
2280
2281         i915_gem_restore_fences(dev);
2282 }
2283
2284 /**
2285  * This function clears the request list as sequence numbers are passed.
2286  */
2287 void
2288 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2289 {
2290         uint32_t seqno;
2291
2292         if (list_empty(&ring->request_list))
2293                 return;
2294
2295         WARN_ON(i915_verify_lists(ring->dev));
2296
2297         seqno = ring->get_seqno(ring, true);
2298
2299         while (!list_empty(&ring->request_list)) {
2300                 struct drm_i915_gem_request *request;
2301
2302                 request = list_first_entry(&ring->request_list,
2303                                            struct drm_i915_gem_request,
2304                                            list);
2305
2306                 if (!i915_seqno_passed(seqno, request->seqno))
2307                         break;
2308
2309                 trace_i915_gem_request_retire(ring, request->seqno);
2310                 /* We know the GPU must have read the request to have
2311                  * sent us the seqno + interrupt, so use the position
2312                  * of tail of the request to update the last known position
2313                  * of the GPU head.
2314                  */
2315                 ring->last_retired_head = request->tail;
2316
2317                 i915_gem_free_request(request);
2318         }
2319
2320         /* Move any buffers on the active list that are no longer referenced
2321          * by the ringbuffer to the flushing/inactive lists as appropriate.
2322          */
2323         while (!list_empty(&ring->active_list)) {
2324                 struct drm_i915_gem_object *obj;
2325
2326                 obj = list_first_entry(&ring->active_list,
2327                                       struct drm_i915_gem_object,
2328                                       ring_list);
2329
2330                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2331                         break;
2332
2333                 i915_gem_object_move_to_inactive(obj);
2334         }
2335
2336         if (unlikely(ring->trace_irq_seqno &&
2337                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2338                 ring->irq_put(ring);
2339                 ring->trace_irq_seqno = 0;
2340         }
2341
2342         WARN_ON(i915_verify_lists(ring->dev));
2343 }
2344
2345 void
2346 i915_gem_retire_requests(struct drm_device *dev)
2347 {
2348         drm_i915_private_t *dev_priv = dev->dev_private;
2349         struct intel_ring_buffer *ring;
2350         int i;
2351
2352         for_each_ring(ring, dev_priv, i)
2353                 i915_gem_retire_requests_ring(ring);
2354 }
2355
2356 static void
2357 i915_gem_retire_work_handler(struct work_struct *work)
2358 {
2359         drm_i915_private_t *dev_priv;
2360         struct drm_device *dev;
2361         struct intel_ring_buffer *ring;
2362         bool idle;
2363         int i;
2364
2365         dev_priv = container_of(work, drm_i915_private_t,
2366                                 mm.retire_work.work);
2367         dev = dev_priv->dev;
2368
2369         /* Come back later if the device is busy... */
2370         if (!mutex_trylock(&dev->struct_mutex)) {
2371                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2372                                    round_jiffies_up_relative(HZ));
2373                 return;
2374         }
2375
2376         i915_gem_retire_requests(dev);
2377
2378         /* Send a periodic flush down the ring so we don't hold onto GEM
2379          * objects indefinitely.
2380          */
2381         idle = true;
2382         for_each_ring(ring, dev_priv, i) {
2383                 if (ring->gpu_caches_dirty)
2384                         i915_add_request(ring, NULL);
2385
2386                 idle &= list_empty(&ring->request_list);
2387         }
2388
2389         if (!dev_priv->mm.suspended && !idle)
2390                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2391                                    round_jiffies_up_relative(HZ));
2392         if (idle)
2393                 intel_mark_idle(dev);
2394
2395         mutex_unlock(&dev->struct_mutex);
2396 }
2397
2398 /**
2399  * Ensures that an object will eventually get non-busy by flushing any required
2400  * write domains, emitting any outstanding lazy request and retiring and
2401  * completed requests.
2402  */
2403 static int
2404 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2405 {
2406         int ret;
2407
2408         if (obj->active) {
2409                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2410                 if (ret)
2411                         return ret;
2412
2413                 i915_gem_retire_requests_ring(obj->ring);
2414         }
2415
2416         return 0;
2417 }
2418
2419 /**
2420  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2421  * @DRM_IOCTL_ARGS: standard ioctl arguments
2422  *
2423  * Returns 0 if successful, else an error is returned with the remaining time in
2424  * the timeout parameter.
2425  *  -ETIME: object is still busy after timeout
2426  *  -ERESTARTSYS: signal interrupted the wait
2427  *  -ENONENT: object doesn't exist
2428  * Also possible, but rare:
2429  *  -EAGAIN: GPU wedged
2430  *  -ENOMEM: damn
2431  *  -ENODEV: Internal IRQ fail
2432  *  -E?: The add request failed
2433  *
2434  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2435  * non-zero timeout parameter the wait ioctl will wait for the given number of
2436  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2437  * without holding struct_mutex the object may become re-busied before this
2438  * function completes. A similar but shorter * race condition exists in the busy
2439  * ioctl
2440  */
2441 int
2442 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2443 {
2444         drm_i915_private_t *dev_priv = dev->dev_private;
2445         struct drm_i915_gem_wait *args = data;
2446         struct drm_i915_gem_object *obj;
2447         struct intel_ring_buffer *ring = NULL;
2448         struct timespec timeout_stack, *timeout = NULL;
2449         unsigned reset_counter;
2450         u32 seqno = 0;
2451         int ret = 0;
2452
2453         if (args->timeout_ns >= 0) {
2454                 timeout_stack = ns_to_timespec(args->timeout_ns);
2455                 timeout = &timeout_stack;
2456         }
2457
2458         ret = i915_mutex_lock_interruptible(dev);
2459         if (ret)
2460                 return ret;
2461
2462         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2463         if (&obj->base == NULL) {
2464                 mutex_unlock(&dev->struct_mutex);
2465                 return -ENOENT;
2466         }
2467
2468         /* Need to make sure the object gets inactive eventually. */
2469         ret = i915_gem_object_flush_active(obj);
2470         if (ret)
2471                 goto out;
2472
2473         if (obj->active) {
2474                 seqno = obj->last_read_seqno;
2475                 ring = obj->ring;
2476         }
2477
2478         if (seqno == 0)
2479                  goto out;
2480
2481         /* Do this after OLR check to make sure we make forward progress polling
2482          * on this IOCTL with a 0 timeout (like busy ioctl)
2483          */
2484         if (!args->timeout_ns) {
2485                 ret = -ETIME;
2486                 goto out;
2487         }
2488
2489         drm_gem_object_unreference(&obj->base);
2490         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2491         mutex_unlock(&dev->struct_mutex);
2492
2493         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2494         if (timeout)
2495                 args->timeout_ns = timespec_to_ns(timeout);
2496         return ret;
2497
2498 out:
2499         drm_gem_object_unreference(&obj->base);
2500         mutex_unlock(&dev->struct_mutex);
2501         return ret;
2502 }
2503
2504 /**
2505  * i915_gem_object_sync - sync an object to a ring.
2506  *
2507  * @obj: object which may be in use on another ring.
2508  * @to: ring we wish to use the object on. May be NULL.
2509  *
2510  * This code is meant to abstract object synchronization with the GPU.
2511  * Calling with NULL implies synchronizing the object with the CPU
2512  * rather than a particular GPU ring.
2513  *
2514  * Returns 0 if successful, else propagates up the lower layer error.
2515  */
2516 int
2517 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2518                      struct intel_ring_buffer *to)
2519 {
2520         struct intel_ring_buffer *from = obj->ring;
2521         u32 seqno;
2522         int ret, idx;
2523
2524         if (from == NULL || to == from)
2525                 return 0;
2526
2527         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2528                 return i915_gem_object_wait_rendering(obj, false);
2529
2530         idx = intel_ring_sync_index(from, to);
2531
2532         seqno = obj->last_read_seqno;
2533         if (seqno <= from->sync_seqno[idx])
2534                 return 0;
2535
2536         ret = i915_gem_check_olr(obj->ring, seqno);
2537         if (ret)
2538                 return ret;
2539
2540         ret = to->sync_to(to, from, seqno);
2541         if (!ret)
2542                 /* We use last_read_seqno because sync_to()
2543                  * might have just caused seqno wrap under
2544                  * the radar.
2545                  */
2546                 from->sync_seqno[idx] = obj->last_read_seqno;
2547
2548         return ret;
2549 }
2550
2551 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2552 {
2553         u32 old_write_domain, old_read_domains;
2554
2555         /* Force a pagefault for domain tracking on next user access */
2556         i915_gem_release_mmap(obj);
2557
2558         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2559                 return;
2560
2561         /* Wait for any direct GTT access to complete */
2562         mb();
2563
2564         old_read_domains = obj->base.read_domains;
2565         old_write_domain = obj->base.write_domain;
2566
2567         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2568         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2569
2570         trace_i915_gem_object_change_domain(obj,
2571                                             old_read_domains,
2572                                             old_write_domain);
2573 }
2574
2575 /**
2576  * Unbinds an object from the GTT aperture.
2577  */
2578 int
2579 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2580 {
2581         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2582         int ret;
2583
2584         if (obj->gtt_space == NULL)
2585                 return 0;
2586
2587         if (obj->pin_count)
2588                 return -EBUSY;
2589
2590         BUG_ON(obj->pages == NULL);
2591
2592         ret = i915_gem_object_finish_gpu(obj);
2593         if (ret)
2594                 return ret;
2595         /* Continue on if we fail due to EIO, the GPU is hung so we
2596          * should be safe and we need to cleanup or else we might
2597          * cause memory corruption through use-after-free.
2598          */
2599
2600         i915_gem_object_finish_gtt(obj);
2601
2602         /* release the fence reg _after_ flushing */
2603         ret = i915_gem_object_put_fence(obj);
2604         if (ret)
2605                 return ret;
2606
2607         trace_i915_gem_object_unbind(obj);
2608
2609         if (obj->has_global_gtt_mapping)
2610                 i915_gem_gtt_unbind_object(obj);
2611         if (obj->has_aliasing_ppgtt_mapping) {
2612                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2613                 obj->has_aliasing_ppgtt_mapping = 0;
2614         }
2615         i915_gem_gtt_finish_object(obj);
2616         i915_gem_object_unpin_pages(obj);
2617
2618         list_del(&obj->mm_list);
2619         list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2620         /* Avoid an unnecessary call to unbind on rebind. */
2621         obj->map_and_fenceable = true;
2622
2623         drm_mm_put_block(obj->gtt_space);
2624         obj->gtt_space = NULL;
2625         obj->gtt_offset = 0;
2626
2627         return 0;
2628 }
2629
2630 int i915_gpu_idle(struct drm_device *dev)
2631 {
2632         drm_i915_private_t *dev_priv = dev->dev_private;
2633         struct intel_ring_buffer *ring;
2634         int ret, i;
2635
2636         /* Flush everything onto the inactive list. */
2637         for_each_ring(ring, dev_priv, i) {
2638                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2639                 if (ret)
2640                         return ret;
2641
2642                 ret = intel_ring_idle(ring);
2643                 if (ret)
2644                         return ret;
2645         }
2646
2647         return 0;
2648 }
2649
2650 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2651                                  struct drm_i915_gem_object *obj)
2652 {
2653         drm_i915_private_t *dev_priv = dev->dev_private;
2654         int fence_reg;
2655         int fence_pitch_shift;
2656         uint64_t val;
2657
2658         if (INTEL_INFO(dev)->gen >= 6) {
2659                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2660                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2661         } else {
2662                 fence_reg = FENCE_REG_965_0;
2663                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2664         }
2665
2666         if (obj) {
2667                 u32 size = obj->gtt_space->size;
2668
2669                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2670                                  0xfffff000) << 32;
2671                 val |= obj->gtt_offset & 0xfffff000;
2672                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2673                 if (obj->tiling_mode == I915_TILING_Y)
2674                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2675                 val |= I965_FENCE_REG_VALID;
2676         } else
2677                 val = 0;
2678
2679         fence_reg += reg * 8;
2680         I915_WRITE64(fence_reg, val);
2681         POSTING_READ(fence_reg);
2682 }
2683
2684 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2685                                  struct drm_i915_gem_object *obj)
2686 {
2687         drm_i915_private_t *dev_priv = dev->dev_private;
2688         u32 val;
2689
2690         if (obj) {
2691                 u32 size = obj->gtt_space->size;
2692                 int pitch_val;
2693                 int tile_width;
2694
2695                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2696                      (size & -size) != size ||
2697                      (obj->gtt_offset & (size - 1)),
2698                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2699                      obj->gtt_offset, obj->map_and_fenceable, size);
2700
2701                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2702                         tile_width = 128;
2703                 else
2704                         tile_width = 512;
2705
2706                 /* Note: pitch better be a power of two tile widths */
2707                 pitch_val = obj->stride / tile_width;
2708                 pitch_val = ffs(pitch_val) - 1;
2709
2710                 val = obj->gtt_offset;
2711                 if (obj->tiling_mode == I915_TILING_Y)
2712                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2713                 val |= I915_FENCE_SIZE_BITS(size);
2714                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2715                 val |= I830_FENCE_REG_VALID;
2716         } else
2717                 val = 0;
2718
2719         if (reg < 8)
2720                 reg = FENCE_REG_830_0 + reg * 4;
2721         else
2722                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2723
2724         I915_WRITE(reg, val);
2725         POSTING_READ(reg);
2726 }
2727
2728 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2729                                 struct drm_i915_gem_object *obj)
2730 {
2731         drm_i915_private_t *dev_priv = dev->dev_private;
2732         uint32_t val;
2733
2734         if (obj) {
2735                 u32 size = obj->gtt_space->size;
2736                 uint32_t pitch_val;
2737
2738                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2739                      (size & -size) != size ||
2740                      (obj->gtt_offset & (size - 1)),
2741                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2742                      obj->gtt_offset, size);
2743
2744                 pitch_val = obj->stride / 128;
2745                 pitch_val = ffs(pitch_val) - 1;
2746
2747                 val = obj->gtt_offset;
2748                 if (obj->tiling_mode == I915_TILING_Y)
2749                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2750                 val |= I830_FENCE_SIZE_BITS(size);
2751                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2752                 val |= I830_FENCE_REG_VALID;
2753         } else
2754                 val = 0;
2755
2756         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2757         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2758 }
2759
2760 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2761 {
2762         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2763 }
2764
2765 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2766                                  struct drm_i915_gem_object *obj)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769
2770         /* Ensure that all CPU reads are completed before installing a fence
2771          * and all writes before removing the fence.
2772          */
2773         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2774                 mb();
2775
2776         switch (INTEL_INFO(dev)->gen) {
2777         case 7:
2778         case 6:
2779         case 5:
2780         case 4: i965_write_fence_reg(dev, reg, obj); break;
2781         case 3: i915_write_fence_reg(dev, reg, obj); break;
2782         case 2: i830_write_fence_reg(dev, reg, obj); break;
2783         default: BUG();
2784         }
2785
2786         /* And similarly be paranoid that no direct access to this region
2787          * is reordered to before the fence is installed.
2788          */
2789         if (i915_gem_object_needs_mb(obj))
2790                 mb();
2791 }
2792
2793 static inline int fence_number(struct drm_i915_private *dev_priv,
2794                                struct drm_i915_fence_reg *fence)
2795 {
2796         return fence - dev_priv->fence_regs;
2797 }
2798
2799 struct write_fence {
2800         struct drm_device *dev;
2801         struct drm_i915_gem_object *obj;
2802         int fence;
2803 };
2804
2805 static void i915_gem_write_fence__ipi(void *data)
2806 {
2807         struct write_fence *args = data;
2808
2809         /* Required for SNB+ with LLC */
2810         wbinvd();
2811
2812         /* Required for VLV */
2813         i915_gem_write_fence(args->dev, args->fence, args->obj);
2814 }
2815
2816 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2817                                          struct drm_i915_fence_reg *fence,
2818                                          bool enable)
2819 {
2820         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2821         struct write_fence args = {
2822                 .dev = obj->base.dev,
2823                 .fence = fence_number(dev_priv, fence),
2824                 .obj = enable ? obj : NULL,
2825         };
2826
2827         /* In order to fully serialize access to the fenced region and
2828          * the update to the fence register we need to take extreme
2829          * measures on SNB+. In theory, the write to the fence register
2830          * flushes all memory transactions before, and coupled with the
2831          * mb() placed around the register write we serialise all memory
2832          * operations with respect to the changes in the tiler. Yet, on
2833          * SNB+ we need to take a step further and emit an explicit wbinvd()
2834          * on each processor in order to manually flush all memory
2835          * transactions before updating the fence register.
2836          *
2837          * However, Valleyview complicates matter. There the wbinvd is
2838          * insufficient and unlike SNB/IVB requires the serialising
2839          * register write. (Note that that register write by itself is
2840          * conversely not sufficient for SNB+.) To compromise, we do both.
2841          */
2842         if (INTEL_INFO(args.dev)->gen >= 6)
2843                 on_each_cpu(i915_gem_write_fence__ipi, &args, 1);
2844         else
2845                 i915_gem_write_fence(args.dev, args.fence, args.obj);
2846
2847         if (enable) {
2848                 obj->fence_reg = args.fence;
2849                 fence->obj = obj;
2850                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2851         } else {
2852                 obj->fence_reg = I915_FENCE_REG_NONE;
2853                 fence->obj = NULL;
2854                 list_del_init(&fence->lru_list);
2855         }
2856 }
2857
2858 static int
2859 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2860 {
2861         if (obj->last_fenced_seqno) {
2862                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2863                 if (ret)
2864                         return ret;
2865
2866                 obj->last_fenced_seqno = 0;
2867         }
2868
2869         obj->fenced_gpu_access = false;
2870         return 0;
2871 }
2872
2873 int
2874 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2875 {
2876         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2877         struct drm_i915_fence_reg *fence;
2878         int ret;
2879
2880         ret = i915_gem_object_wait_fence(obj);
2881         if (ret)
2882                 return ret;
2883
2884         if (obj->fence_reg == I915_FENCE_REG_NONE)
2885                 return 0;
2886
2887         fence = &dev_priv->fence_regs[obj->fence_reg];
2888
2889         i915_gem_object_fence_lost(obj);
2890         i915_gem_object_update_fence(obj, fence, false);
2891
2892         return 0;
2893 }
2894
2895 static struct drm_i915_fence_reg *
2896 i915_find_fence_reg(struct drm_device *dev)
2897 {
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct drm_i915_fence_reg *reg, *avail;
2900         int i;
2901
2902         /* First try to find a free reg */
2903         avail = NULL;
2904         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2905                 reg = &dev_priv->fence_regs[i];
2906                 if (!reg->obj)
2907                         return reg;
2908
2909                 if (!reg->pin_count)
2910                         avail = reg;
2911         }
2912
2913         if (avail == NULL)
2914                 return NULL;
2915
2916         /* None available, try to steal one or wait for a user to finish */
2917         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2918                 if (reg->pin_count)
2919                         continue;
2920
2921                 return reg;
2922         }
2923
2924         return NULL;
2925 }
2926
2927 /**
2928  * i915_gem_object_get_fence - set up fencing for an object
2929  * @obj: object to map through a fence reg
2930  *
2931  * When mapping objects through the GTT, userspace wants to be able to write
2932  * to them without having to worry about swizzling if the object is tiled.
2933  * This function walks the fence regs looking for a free one for @obj,
2934  * stealing one if it can't find any.
2935  *
2936  * It then sets up the reg based on the object's properties: address, pitch
2937  * and tiling format.
2938  *
2939  * For an untiled surface, this removes any existing fence.
2940  */
2941 int
2942 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2943 {
2944         struct drm_device *dev = obj->base.dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         bool enable = obj->tiling_mode != I915_TILING_NONE;
2947         struct drm_i915_fence_reg *reg;
2948         int ret;
2949
2950         /* Have we updated the tiling parameters upon the object and so
2951          * will need to serialise the write to the associated fence register?
2952          */
2953         if (obj->fence_dirty) {
2954                 ret = i915_gem_object_wait_fence(obj);
2955                 if (ret)
2956                         return ret;
2957         }
2958
2959         /* Just update our place in the LRU if our fence is getting reused. */
2960         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2961                 reg = &dev_priv->fence_regs[obj->fence_reg];
2962                 if (!obj->fence_dirty) {
2963                         list_move_tail(&reg->lru_list,
2964                                        &dev_priv->mm.fence_list);
2965                         return 0;
2966                 }
2967         } else if (enable) {
2968                 reg = i915_find_fence_reg(dev);
2969                 if (reg == NULL)
2970                         return -EDEADLK;
2971
2972                 if (reg->obj) {
2973                         struct drm_i915_gem_object *old = reg->obj;
2974
2975                         ret = i915_gem_object_wait_fence(old);
2976                         if (ret)
2977                                 return ret;
2978
2979                         i915_gem_object_fence_lost(old);
2980                 }
2981         } else
2982                 return 0;
2983
2984         i915_gem_object_update_fence(obj, reg, enable);
2985         obj->fence_dirty = false;
2986
2987         return 0;
2988 }
2989
2990 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2991                                      struct drm_mm_node *gtt_space,
2992                                      unsigned long cache_level)
2993 {
2994         struct drm_mm_node *other;
2995
2996         /* On non-LLC machines we have to be careful when putting differing
2997          * types of snoopable memory together to avoid the prefetcher
2998          * crossing memory domains and dying.
2999          */
3000         if (HAS_LLC(dev))
3001                 return true;
3002
3003         if (gtt_space == NULL)
3004                 return true;
3005
3006         if (list_empty(&gtt_space->node_list))
3007                 return true;
3008
3009         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3010         if (other->allocated && !other->hole_follows && other->color != cache_level)
3011                 return false;
3012
3013         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3014         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3015                 return false;
3016
3017         return true;
3018 }
3019
3020 static void i915_gem_verify_gtt(struct drm_device *dev)
3021 {
3022 #if WATCH_GTT
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024         struct drm_i915_gem_object *obj;
3025         int err = 0;
3026
3027         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3028                 if (obj->gtt_space == NULL) {
3029                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3030                         err++;
3031                         continue;
3032                 }
3033
3034                 if (obj->cache_level != obj->gtt_space->color) {
3035                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3036                                obj->gtt_space->start,
3037                                obj->gtt_space->start + obj->gtt_space->size,
3038                                obj->cache_level,
3039                                obj->gtt_space->color);
3040                         err++;
3041                         continue;
3042                 }
3043
3044                 if (!i915_gem_valid_gtt_space(dev,
3045                                               obj->gtt_space,
3046                                               obj->cache_level)) {
3047                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3048                                obj->gtt_space->start,
3049                                obj->gtt_space->start + obj->gtt_space->size,
3050                                obj->cache_level);
3051                         err++;
3052                         continue;
3053                 }
3054         }
3055
3056         WARN_ON(err);
3057 #endif
3058 }
3059
3060 /**
3061  * Finds free space in the GTT aperture and binds the object there.
3062  */
3063 static int
3064 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3065                             unsigned alignment,
3066                             bool map_and_fenceable,
3067                             bool nonblocking)
3068 {
3069         struct drm_device *dev = obj->base.dev;
3070         drm_i915_private_t *dev_priv = dev->dev_private;
3071         struct drm_mm_node *node;
3072         u32 size, fence_size, fence_alignment, unfenced_alignment;
3073         bool mappable, fenceable;
3074         size_t gtt_max = map_and_fenceable ?
3075                 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3076         int ret;
3077
3078         fence_size = i915_gem_get_gtt_size(dev,
3079                                            obj->base.size,
3080                                            obj->tiling_mode);
3081         fence_alignment = i915_gem_get_gtt_alignment(dev,
3082                                                      obj->base.size,
3083                                                      obj->tiling_mode, true);
3084         unfenced_alignment =
3085                 i915_gem_get_gtt_alignment(dev,
3086                                                     obj->base.size,
3087                                                     obj->tiling_mode, false);
3088
3089         if (alignment == 0)
3090                 alignment = map_and_fenceable ? fence_alignment :
3091                                                 unfenced_alignment;
3092         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3093                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3094                 return -EINVAL;
3095         }
3096
3097         size = map_and_fenceable ? fence_size : obj->base.size;
3098
3099         /* If the object is bigger than the entire aperture, reject it early
3100          * before evicting everything in a vain attempt to find space.
3101          */
3102         if (obj->base.size > gtt_max) {
3103                 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3104                           obj->base.size,
3105                           map_and_fenceable ? "mappable" : "total",
3106                           gtt_max);
3107                 return -E2BIG;
3108         }
3109
3110         ret = i915_gem_object_get_pages(obj);
3111         if (ret)
3112                 return ret;
3113
3114         i915_gem_object_pin_pages(obj);
3115
3116         node = kzalloc(sizeof(*node), GFP_KERNEL);
3117         if (node == NULL) {
3118                 i915_gem_object_unpin_pages(obj);
3119                 return -ENOMEM;
3120         }
3121
3122 search_free:
3123         ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3124                                                   size, alignment,
3125                                                   obj->cache_level, 0, gtt_max);
3126         if (ret) {
3127                 ret = i915_gem_evict_something(dev, size, alignment,
3128                                                obj->cache_level,
3129                                                map_and_fenceable,
3130                                                nonblocking);
3131                 if (ret == 0)
3132                         goto search_free;
3133
3134                 i915_gem_object_unpin_pages(obj);
3135                 kfree(node);
3136                 return ret;
3137         }
3138         if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3139                 i915_gem_object_unpin_pages(obj);
3140                 drm_mm_put_block(node);
3141                 return -EINVAL;
3142         }
3143
3144         ret = i915_gem_gtt_prepare_object(obj);
3145         if (ret) {
3146                 i915_gem_object_unpin_pages(obj);
3147                 drm_mm_put_block(node);
3148                 return ret;
3149         }
3150
3151         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3152         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3153
3154         obj->gtt_space = node;
3155         obj->gtt_offset = node->start;
3156
3157         fenceable =
3158                 node->size == fence_size &&
3159                 (node->start & (fence_alignment - 1)) == 0;
3160
3161         mappable =
3162                 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3163
3164         obj->map_and_fenceable = mappable && fenceable;
3165
3166         trace_i915_gem_object_bind(obj, map_and_fenceable);
3167         i915_gem_verify_gtt(dev);
3168         return 0;
3169 }
3170
3171 void
3172 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3173 {
3174         /* If we don't have a page list set up, then we're not pinned
3175          * to GPU, and we can ignore the cache flush because it'll happen
3176          * again at bind time.
3177          */
3178         if (obj->pages == NULL)
3179                 return;
3180
3181         /*
3182          * Stolen memory is always coherent with the GPU as it is explicitly
3183          * marked as wc by the system, or the system is cache-coherent.
3184          */
3185         if (obj->stolen)
3186                 return;
3187
3188         /* If the GPU is snooping the contents of the CPU cache,
3189          * we do not need to manually clear the CPU cache lines.  However,
3190          * the caches are only snooped when the render cache is
3191          * flushed/invalidated.  As we always have to emit invalidations
3192          * and flushes when moving into and out of the RENDER domain, correct
3193          * snooping behaviour occurs naturally as the result of our domain
3194          * tracking.
3195          */
3196         if (obj->cache_level != I915_CACHE_NONE)
3197                 return;
3198
3199         trace_i915_gem_object_clflush(obj);
3200
3201         drm_clflush_sg(obj->pages);
3202 }
3203
3204 /** Flushes the GTT write domain for the object if it's dirty. */
3205 static void
3206 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3207 {
3208         uint32_t old_write_domain;
3209
3210         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3211                 return;
3212
3213         /* No actual flushing is required for the GTT write domain.  Writes
3214          * to it immediately go to main memory as far as we know, so there's
3215          * no chipset flush.  It also doesn't land in render cache.
3216          *
3217          * However, we do have to enforce the order so that all writes through
3218          * the GTT land before any writes to the device, such as updates to
3219          * the GATT itself.
3220          */
3221         wmb();
3222
3223         old_write_domain = obj->base.write_domain;
3224         obj->base.write_domain = 0;
3225
3226         trace_i915_gem_object_change_domain(obj,
3227                                             obj->base.read_domains,
3228                                             old_write_domain);
3229 }
3230
3231 /** Flushes the CPU write domain for the object if it's dirty. */
3232 static void
3233 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3234 {
3235         uint32_t old_write_domain;
3236
3237         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3238                 return;
3239
3240         i915_gem_clflush_object(obj);
3241         i915_gem_chipset_flush(obj->base.dev);
3242         old_write_domain = obj->base.write_domain;
3243         obj->base.write_domain = 0;
3244
3245         trace_i915_gem_object_change_domain(obj,
3246                                             obj->base.read_domains,
3247                                             old_write_domain);
3248 }
3249
3250 /**
3251  * Moves a single object to the GTT read, and possibly write domain.
3252  *
3253  * This function returns when the move is complete, including waiting on
3254  * flushes to occur.
3255  */
3256 int
3257 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3258 {
3259         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3260         uint32_t old_write_domain, old_read_domains;
3261         int ret;
3262
3263         /* Not valid to be called on unbound objects. */
3264         if (obj->gtt_space == NULL)
3265                 return -EINVAL;
3266
3267         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3268                 return 0;
3269
3270         ret = i915_gem_object_wait_rendering(obj, !write);
3271         if (ret)
3272                 return ret;
3273
3274         i915_gem_object_flush_cpu_write_domain(obj);
3275
3276         /* Serialise direct access to this object with the barriers for
3277          * coherent writes from the GPU, by effectively invalidating the
3278          * GTT domain upon first access.
3279          */
3280         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3281                 mb();
3282
3283         old_write_domain = obj->base.write_domain;
3284         old_read_domains = obj->base.read_domains;
3285
3286         /* It should now be out of any other write domains, and we can update
3287          * the domain values for our changes.
3288          */
3289         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3290         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3291         if (write) {
3292                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3293                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3294                 obj->dirty = 1;
3295         }
3296
3297         trace_i915_gem_object_change_domain(obj,
3298                                             old_read_domains,
3299                                             old_write_domain);
3300
3301         /* And bump the LRU for this access */
3302         if (i915_gem_object_is_inactive(obj))
3303                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3304
3305         return 0;
3306 }
3307
3308 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3309                                     enum i915_cache_level cache_level)
3310 {
3311         struct drm_device *dev = obj->base.dev;
3312         drm_i915_private_t *dev_priv = dev->dev_private;
3313         int ret;
3314
3315         if (obj->cache_level == cache_level)
3316                 return 0;
3317
3318         if (obj->pin_count) {
3319                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3320                 return -EBUSY;
3321         }
3322
3323         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3324                 ret = i915_gem_object_unbind(obj);
3325                 if (ret)
3326                         return ret;
3327         }
3328
3329         if (obj->gtt_space) {
3330                 ret = i915_gem_object_finish_gpu(obj);
3331                 if (ret)
3332                         return ret;
3333
3334                 i915_gem_object_finish_gtt(obj);
3335
3336                 /* Before SandyBridge, you could not use tiling or fence
3337                  * registers with snooped memory, so relinquish any fences
3338                  * currently pointing to our region in the aperture.
3339                  */
3340                 if (INTEL_INFO(dev)->gen < 6) {
3341                         ret = i915_gem_object_put_fence(obj);
3342                         if (ret)
3343                                 return ret;
3344                 }
3345
3346                 if (obj->has_global_gtt_mapping)
3347                         i915_gem_gtt_bind_object(obj, cache_level);
3348                 if (obj->has_aliasing_ppgtt_mapping)
3349                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3350                                                obj, cache_level);
3351
3352                 obj->gtt_space->color = cache_level;
3353         }
3354
3355         if (cache_level == I915_CACHE_NONE) {
3356                 u32 old_read_domains, old_write_domain;
3357
3358                 /* If we're coming from LLC cached, then we haven't
3359                  * actually been tracking whether the data is in the
3360                  * CPU cache or not, since we only allow one bit set
3361                  * in obj->write_domain and have been skipping the clflushes.
3362                  * Just set it to the CPU cache for now.
3363                  */
3364                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3365                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3366
3367                 old_read_domains = obj->base.read_domains;
3368                 old_write_domain = obj->base.write_domain;
3369
3370                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3371                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3372
3373                 trace_i915_gem_object_change_domain(obj,
3374                                                     old_read_domains,
3375                                                     old_write_domain);
3376         }
3377
3378         obj->cache_level = cache_level;
3379         i915_gem_verify_gtt(dev);
3380         return 0;
3381 }
3382
3383 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3384                                struct drm_file *file)
3385 {
3386         struct drm_i915_gem_caching *args = data;
3387         struct drm_i915_gem_object *obj;
3388         int ret;
3389
3390         ret = i915_mutex_lock_interruptible(dev);
3391         if (ret)
3392                 return ret;
3393
3394         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3395         if (&obj->base == NULL) {
3396                 ret = -ENOENT;
3397                 goto unlock;
3398         }
3399
3400         args->caching = obj->cache_level != I915_CACHE_NONE;
3401
3402         drm_gem_object_unreference(&obj->base);
3403 unlock:
3404         mutex_unlock(&dev->struct_mutex);
3405         return ret;
3406 }
3407
3408 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3409                                struct drm_file *file)
3410 {
3411         struct drm_i915_gem_caching *args = data;
3412         struct drm_i915_gem_object *obj;
3413         enum i915_cache_level level;
3414         int ret;
3415
3416         switch (args->caching) {
3417         case I915_CACHING_NONE:
3418                 level = I915_CACHE_NONE;
3419                 break;
3420         case I915_CACHING_CACHED:
3421                 level = I915_CACHE_LLC;
3422                 break;
3423         default:
3424                 return -EINVAL;
3425         }
3426
3427         ret = i915_mutex_lock_interruptible(dev);
3428         if (ret)
3429                 return ret;
3430
3431         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3432         if (&obj->base == NULL) {
3433                 ret = -ENOENT;
3434                 goto unlock;
3435         }
3436
3437         ret = i915_gem_object_set_cache_level(obj, level);
3438
3439         drm_gem_object_unreference(&obj->base);
3440 unlock:
3441         mutex_unlock(&dev->struct_mutex);
3442         return ret;
3443 }
3444
3445 /*
3446  * Prepare buffer for display plane (scanout, cursors, etc).
3447  * Can be called from an uninterruptible phase (modesetting) and allows
3448  * any flushes to be pipelined (for pageflips).
3449  */
3450 int
3451 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3452                                      u32 alignment,
3453                                      struct intel_ring_buffer *pipelined)
3454 {
3455         u32 old_read_domains, old_write_domain;
3456         int ret;
3457
3458         if (pipelined != obj->ring) {
3459                 ret = i915_gem_object_sync(obj, pipelined);
3460                 if (ret)
3461                         return ret;
3462         }
3463
3464         /* The display engine is not coherent with the LLC cache on gen6.  As
3465          * a result, we make sure that the pinning that is about to occur is
3466          * done with uncached PTEs. This is lowest common denominator for all
3467          * chipsets.
3468          *
3469          * However for gen6+, we could do better by using the GFDT bit instead
3470          * of uncaching, which would allow us to flush all the LLC-cached data
3471          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3472          */
3473         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3474         if (ret)
3475                 return ret;
3476
3477         /* As the user may map the buffer once pinned in the display plane
3478          * (e.g. libkms for the bootup splash), we have to ensure that we
3479          * always use map_and_fenceable for all scanout buffers.
3480          */
3481         ret = i915_gem_object_pin(obj, alignment, true, false);
3482         if (ret)
3483                 return ret;
3484
3485         i915_gem_object_flush_cpu_write_domain(obj);
3486
3487         old_write_domain = obj->base.write_domain;
3488         old_read_domains = obj->base.read_domains;
3489
3490         /* It should now be out of any other write domains, and we can update
3491          * the domain values for our changes.
3492          */
3493         obj->base.write_domain = 0;
3494         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3495
3496         trace_i915_gem_object_change_domain(obj,
3497                                             old_read_domains,
3498                                             old_write_domain);
3499
3500         return 0;
3501 }
3502
3503 int
3504 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3505 {
3506         int ret;
3507
3508         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3509                 return 0;
3510
3511         ret = i915_gem_object_wait_rendering(obj, false);
3512         if (ret)
3513                 return ret;
3514
3515         /* Ensure that we invalidate the GPU's caches and TLBs. */
3516         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3517         return 0;
3518 }
3519
3520 /**
3521  * Moves a single object to the CPU read, and possibly write domain.
3522  *
3523  * This function returns when the move is complete, including waiting on
3524  * flushes to occur.
3525  */
3526 int
3527 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3528 {
3529         uint32_t old_write_domain, old_read_domains;
3530         int ret;
3531
3532         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3533                 return 0;
3534
3535         ret = i915_gem_object_wait_rendering(obj, !write);
3536         if (ret)
3537                 return ret;
3538
3539         i915_gem_object_flush_gtt_write_domain(obj);
3540
3541         old_write_domain = obj->base.write_domain;
3542         old_read_domains = obj->base.read_domains;
3543
3544         /* Flush the CPU cache if it's still invalid. */
3545         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3546                 i915_gem_clflush_object(obj);
3547
3548                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3549         }
3550
3551         /* It should now be out of any other write domains, and we can update
3552          * the domain values for our changes.
3553          */
3554         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3555
3556         /* If we're writing through the CPU, then the GPU read domains will
3557          * need to be invalidated at next use.
3558          */
3559         if (write) {
3560                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3561                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3562         }
3563
3564         trace_i915_gem_object_change_domain(obj,
3565                                             old_read_domains,
3566                                             old_write_domain);
3567
3568         return 0;
3569 }
3570
3571 /* Throttle our rendering by waiting until the ring has completed our requests
3572  * emitted over 20 msec ago.
3573  *
3574  * Note that if we were to use the current jiffies each time around the loop,
3575  * we wouldn't escape the function with any frames outstanding if the time to
3576  * render a frame was over 20ms.
3577  *
3578  * This should get us reasonable parallelism between CPU and GPU but also
3579  * relatively low latency when blocking on a particular request to finish.
3580  */
3581 static int
3582 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3583 {
3584         struct drm_i915_private *dev_priv = dev->dev_private;
3585         struct drm_i915_file_private *file_priv = file->driver_priv;
3586         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3587         struct drm_i915_gem_request *request;
3588         struct intel_ring_buffer *ring = NULL;
3589         unsigned reset_counter;
3590         u32 seqno = 0;
3591         int ret;
3592
3593         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3594         if (ret)
3595                 return ret;
3596
3597         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3598         if (ret)
3599                 return ret;
3600
3601         spin_lock(&file_priv->mm.lock);
3602         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3603                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3604                         break;
3605
3606                 ring = request->ring;
3607                 seqno = request->seqno;
3608         }
3609         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3610         spin_unlock(&file_priv->mm.lock);
3611
3612         if (seqno == 0)
3613                 return 0;
3614
3615         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3616         if (ret == 0)
3617                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3618
3619         return ret;
3620 }
3621
3622 int
3623 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3624                     uint32_t alignment,
3625                     bool map_and_fenceable,
3626                     bool nonblocking)
3627 {
3628         int ret;
3629
3630         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3631                 return -EBUSY;
3632
3633         if (obj->gtt_space != NULL) {
3634                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3635                     (map_and_fenceable && !obj->map_and_fenceable)) {
3636                         WARN(obj->pin_count,
3637                              "bo is already pinned with incorrect alignment:"
3638                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3639                              " obj->map_and_fenceable=%d\n",
3640                              obj->gtt_offset, alignment,
3641                              map_and_fenceable,
3642                              obj->map_and_fenceable);
3643                         ret = i915_gem_object_unbind(obj);
3644                         if (ret)
3645                                 return ret;
3646                 }
3647         }
3648
3649         if (obj->gtt_space == NULL) {
3650                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3651
3652                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3653                                                   map_and_fenceable,
3654                                                   nonblocking);
3655                 if (ret)
3656                         return ret;
3657
3658                 if (!dev_priv->mm.aliasing_ppgtt)
3659                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3660         }
3661
3662         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3663                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3664
3665         obj->pin_count++;
3666         obj->pin_mappable |= map_and_fenceable;
3667
3668         return 0;
3669 }
3670
3671 void
3672 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3673 {
3674         BUG_ON(obj->pin_count == 0);
3675         BUG_ON(obj->gtt_space == NULL);
3676
3677         if (--obj->pin_count == 0)
3678                 obj->pin_mappable = false;
3679 }
3680
3681 int
3682 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3683                    struct drm_file *file)
3684 {
3685         struct drm_i915_gem_pin *args = data;
3686         struct drm_i915_gem_object *obj;
3687         int ret;
3688
3689         ret = i915_mutex_lock_interruptible(dev);
3690         if (ret)
3691                 return ret;
3692
3693         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3694         if (&obj->base == NULL) {
3695                 ret = -ENOENT;
3696                 goto unlock;
3697         }
3698
3699         if (obj->madv != I915_MADV_WILLNEED) {
3700                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3701                 ret = -EINVAL;
3702                 goto out;
3703         }
3704
3705         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3706                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3707                           args->handle);
3708                 ret = -EINVAL;
3709                 goto out;
3710         }
3711
3712         if (obj->user_pin_count == 0) {
3713                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3714                 if (ret)
3715                         goto out;
3716         }
3717
3718         obj->user_pin_count++;
3719         obj->pin_filp = file;
3720
3721         /* XXX - flush the CPU caches for pinned objects
3722          * as the X server doesn't manage domains yet
3723          */
3724         i915_gem_object_flush_cpu_write_domain(obj);
3725         args->offset = obj->gtt_offset;
3726 out:
3727         drm_gem_object_unreference(&obj->base);
3728 unlock:
3729         mutex_unlock(&dev->struct_mutex);
3730         return ret;
3731 }
3732
3733 int
3734 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3735                      struct drm_file *file)
3736 {
3737         struct drm_i915_gem_pin *args = data;
3738         struct drm_i915_gem_object *obj;
3739         int ret;
3740
3741         ret = i915_mutex_lock_interruptible(dev);
3742         if (ret)
3743                 return ret;
3744
3745         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3746         if (&obj->base == NULL) {
3747                 ret = -ENOENT;
3748                 goto unlock;
3749         }
3750
3751         if (obj->pin_filp != file) {
3752                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3753                           args->handle);
3754                 ret = -EINVAL;
3755                 goto out;
3756         }
3757         obj->user_pin_count--;
3758         if (obj->user_pin_count == 0) {
3759                 obj->pin_filp = NULL;
3760                 i915_gem_object_unpin(obj);
3761         }
3762
3763 out:
3764         drm_gem_object_unreference(&obj->base);
3765 unlock:
3766         mutex_unlock(&dev->struct_mutex);
3767         return ret;
3768 }
3769
3770 int
3771 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3772                     struct drm_file *file)
3773 {
3774         struct drm_i915_gem_busy *args = data;
3775         struct drm_i915_gem_object *obj;
3776         int ret;
3777
3778         ret = i915_mutex_lock_interruptible(dev);
3779         if (ret)
3780                 return ret;
3781
3782         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3783         if (&obj->base == NULL) {
3784                 ret = -ENOENT;
3785                 goto unlock;
3786         }
3787
3788         /* Count all active objects as busy, even if they are currently not used
3789          * by the gpu. Users of this interface expect objects to eventually
3790          * become non-busy without any further actions, therefore emit any
3791          * necessary flushes here.
3792          */
3793         ret = i915_gem_object_flush_active(obj);
3794
3795         args->busy = obj->active;
3796         if (obj->ring) {
3797                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3798                 args->busy |= intel_ring_flag(obj->ring) << 16;
3799         }
3800
3801         drm_gem_object_unreference(&obj->base);
3802 unlock:
3803         mutex_unlock(&dev->struct_mutex);
3804         return ret;
3805 }
3806
3807 int
3808 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3809                         struct drm_file *file_priv)
3810 {
3811         return i915_gem_ring_throttle(dev, file_priv);
3812 }
3813
3814 int
3815 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3816                        struct drm_file *file_priv)
3817 {
3818         struct drm_i915_gem_madvise *args = data;
3819         struct drm_i915_gem_object *obj;
3820         int ret;
3821
3822         switch (args->madv) {
3823         case I915_MADV_DONTNEED:
3824         case I915_MADV_WILLNEED:
3825             break;
3826         default:
3827             return -EINVAL;
3828         }
3829
3830         ret = i915_mutex_lock_interruptible(dev);
3831         if (ret)
3832                 return ret;
3833
3834         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3835         if (&obj->base == NULL) {
3836                 ret = -ENOENT;
3837                 goto unlock;
3838         }
3839
3840         if (obj->pin_count) {
3841                 ret = -EINVAL;
3842                 goto out;
3843         }
3844
3845         if (obj->madv != __I915_MADV_PURGED)
3846                 obj->madv = args->madv;
3847
3848         /* if the object is no longer attached, discard its backing storage */
3849         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3850                 i915_gem_object_truncate(obj);
3851
3852         args->retained = obj->madv != __I915_MADV_PURGED;
3853
3854 out:
3855         drm_gem_object_unreference(&obj->base);
3856 unlock:
3857         mutex_unlock(&dev->struct_mutex);
3858         return ret;
3859 }
3860
3861 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3862                           const struct drm_i915_gem_object_ops *ops)
3863 {
3864         INIT_LIST_HEAD(&obj->mm_list);
3865         INIT_LIST_HEAD(&obj->global_list);
3866         INIT_LIST_HEAD(&obj->ring_list);
3867         INIT_LIST_HEAD(&obj->exec_list);
3868
3869         obj->ops = ops;
3870
3871         obj->fence_reg = I915_FENCE_REG_NONE;
3872         obj->madv = I915_MADV_WILLNEED;
3873         /* Avoid an unnecessary call to unbind on the first bind. */
3874         obj->map_and_fenceable = true;
3875
3876         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3877 }
3878
3879 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3880         .get_pages = i915_gem_object_get_pages_gtt,
3881         .put_pages = i915_gem_object_put_pages_gtt,
3882 };
3883
3884 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3885                                                   size_t size)
3886 {
3887         struct drm_i915_gem_object *obj;
3888         struct address_space *mapping;
3889         gfp_t mask;
3890
3891         obj = i915_gem_object_alloc(dev);
3892         if (obj == NULL)
3893                 return NULL;
3894
3895         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3896                 i915_gem_object_free(obj);
3897                 return NULL;
3898         }
3899
3900         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3901         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3902                 /* 965gm cannot relocate objects above 4GiB. */
3903                 mask &= ~__GFP_HIGHMEM;
3904                 mask |= __GFP_DMA32;
3905         }
3906
3907         mapping = file_inode(obj->base.filp)->i_mapping;
3908         mapping_set_gfp_mask(mapping, mask);
3909
3910         i915_gem_object_init(obj, &i915_gem_object_ops);
3911
3912         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3913         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3914
3915         if (HAS_LLC(dev)) {
3916                 /* On some devices, we can have the GPU use the LLC (the CPU
3917                  * cache) for about a 10% performance improvement
3918                  * compared to uncached.  Graphics requests other than
3919                  * display scanout are coherent with the CPU in
3920                  * accessing this cache.  This means in this mode we
3921                  * don't need to clflush on the CPU side, and on the
3922                  * GPU side we only need to flush internal caches to
3923                  * get data visible to the CPU.
3924                  *
3925                  * However, we maintain the display planes as UC, and so
3926                  * need to rebind when first used as such.
3927                  */
3928                 obj->cache_level = I915_CACHE_LLC;
3929         } else
3930                 obj->cache_level = I915_CACHE_NONE;
3931
3932         return obj;
3933 }
3934
3935 int i915_gem_init_object(struct drm_gem_object *obj)
3936 {
3937         BUG();
3938
3939         return 0;
3940 }
3941
3942 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3943 {
3944         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3945         struct drm_device *dev = obj->base.dev;
3946         drm_i915_private_t *dev_priv = dev->dev_private;
3947
3948         trace_i915_gem_object_destroy(obj);
3949
3950         if (obj->phys_obj)
3951                 i915_gem_detach_phys_object(dev, obj);
3952
3953         obj->pin_count = 0;
3954         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3955                 bool was_interruptible;
3956
3957                 was_interruptible = dev_priv->mm.interruptible;
3958                 dev_priv->mm.interruptible = false;
3959
3960                 WARN_ON(i915_gem_object_unbind(obj));
3961
3962                 dev_priv->mm.interruptible = was_interruptible;
3963         }
3964
3965         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3966          * before progressing. */
3967         if (obj->stolen)
3968                 i915_gem_object_unpin_pages(obj);
3969
3970         if (WARN_ON(obj->pages_pin_count))
3971                 obj->pages_pin_count = 0;
3972         i915_gem_object_put_pages(obj);
3973         i915_gem_object_free_mmap_offset(obj);
3974         i915_gem_object_release_stolen(obj);
3975
3976         BUG_ON(obj->pages);
3977
3978         if (obj->base.import_attach)
3979                 drm_prime_gem_destroy(&obj->base, NULL);
3980
3981         drm_gem_object_release(&obj->base);
3982         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3983
3984         kfree(obj->bit_17);
3985         i915_gem_object_free(obj);
3986 }
3987
3988 int
3989 i915_gem_idle(struct drm_device *dev)
3990 {
3991         drm_i915_private_t *dev_priv = dev->dev_private;
3992         int ret;
3993
3994         mutex_lock(&dev->struct_mutex);
3995
3996         if (dev_priv->mm.suspended) {
3997                 mutex_unlock(&dev->struct_mutex);
3998                 return 0;
3999         }
4000
4001         ret = i915_gpu_idle(dev);
4002         if (ret) {
4003                 mutex_unlock(&dev->struct_mutex);
4004                 return ret;
4005         }
4006         i915_gem_retire_requests(dev);
4007
4008         /* Under UMS, be paranoid and evict. */
4009         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4010                 i915_gem_evict_everything(dev);
4011
4012         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4013          * We need to replace this with a semaphore, or something.
4014          * And not confound mm.suspended!
4015          */
4016         dev_priv->mm.suspended = 1;
4017         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4018
4019         i915_kernel_lost_context(dev);
4020         i915_gem_cleanup_ringbuffer(dev);
4021
4022         mutex_unlock(&dev->struct_mutex);
4023
4024         /* Cancel the retire work handler, which should be idle now. */
4025         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4026
4027         return 0;
4028 }
4029
4030 void i915_gem_l3_remap(struct drm_device *dev)
4031 {
4032         drm_i915_private_t *dev_priv = dev->dev_private;
4033         u32 misccpctl;
4034         int i;
4035
4036         if (!HAS_L3_GPU_CACHE(dev))
4037                 return;
4038
4039         if (!dev_priv->l3_parity.remap_info)
4040                 return;
4041
4042         misccpctl = I915_READ(GEN7_MISCCPCTL);
4043         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4044         POSTING_READ(GEN7_MISCCPCTL);
4045
4046         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4047                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4048                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4049                         DRM_DEBUG("0x%x was already programmed to %x\n",
4050                                   GEN7_L3LOG_BASE + i, remap);
4051                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4052                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
4053                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4054         }
4055
4056         /* Make sure all the writes land before disabling dop clock gating */
4057         POSTING_READ(GEN7_L3LOG_BASE);
4058
4059         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4060 }
4061
4062 void i915_gem_init_swizzling(struct drm_device *dev)
4063 {
4064         drm_i915_private_t *dev_priv = dev->dev_private;
4065
4066         if (INTEL_INFO(dev)->gen < 5 ||
4067             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4068                 return;
4069
4070         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4071                                  DISP_TILE_SURFACE_SWIZZLING);
4072
4073         if (IS_GEN5(dev))
4074                 return;
4075
4076         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4077         if (IS_GEN6(dev))
4078                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4079         else if (IS_GEN7(dev))
4080                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4081         else
4082                 BUG();
4083 }
4084
4085 static bool
4086 intel_enable_blt(struct drm_device *dev)
4087 {
4088         if (!HAS_BLT(dev))
4089                 return false;
4090
4091         /* The blitter was dysfunctional on early prototypes */
4092         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4093                 DRM_INFO("BLT not supported on this pre-production hardware;"
4094                          " graphics performance will be degraded.\n");
4095                 return false;
4096         }
4097
4098         return true;
4099 }
4100
4101 static int i915_gem_init_rings(struct drm_device *dev)
4102 {
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         int ret;
4105
4106         ret = intel_init_render_ring_buffer(dev);
4107         if (ret)
4108                 return ret;
4109
4110         if (HAS_BSD(dev)) {
4111                 ret = intel_init_bsd_ring_buffer(dev);
4112                 if (ret)
4113                         goto cleanup_render_ring;
4114         }
4115
4116         if (intel_enable_blt(dev)) {
4117                 ret = intel_init_blt_ring_buffer(dev);
4118                 if (ret)
4119                         goto cleanup_bsd_ring;
4120         }
4121
4122         if (HAS_VEBOX(dev)) {
4123                 ret = intel_init_vebox_ring_buffer(dev);
4124                 if (ret)
4125                         goto cleanup_blt_ring;
4126         }
4127
4128
4129         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4130         if (ret)
4131                 goto cleanup_vebox_ring;
4132
4133         return 0;
4134
4135 cleanup_vebox_ring:
4136         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4137 cleanup_blt_ring:
4138         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4139 cleanup_bsd_ring:
4140         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4141 cleanup_render_ring:
4142         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4143
4144         return ret;
4145 }
4146
4147 int
4148 i915_gem_init_hw(struct drm_device *dev)
4149 {
4150         drm_i915_private_t *dev_priv = dev->dev_private;
4151         int ret;
4152
4153         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4154                 return -EIO;
4155
4156         if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4157                 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4158
4159         if (HAS_PCH_NOP(dev)) {
4160                 u32 temp = I915_READ(GEN7_MSG_CTL);
4161                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4162                 I915_WRITE(GEN7_MSG_CTL, temp);
4163         }
4164
4165         i915_gem_l3_remap(dev);
4166
4167         i915_gem_init_swizzling(dev);
4168
4169         ret = i915_gem_init_rings(dev);
4170         if (ret)
4171                 return ret;
4172
4173         /*
4174          * XXX: There was some w/a described somewhere suggesting loading
4175          * contexts before PPGTT.
4176          */
4177         i915_gem_context_init(dev);
4178         if (dev_priv->mm.aliasing_ppgtt) {
4179                 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4180                 if (ret) {
4181                         i915_gem_cleanup_aliasing_ppgtt(dev);
4182                         DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4183                 }
4184         }
4185
4186         return 0;
4187 }
4188
4189 int i915_gem_init(struct drm_device *dev)
4190 {
4191         struct drm_i915_private *dev_priv = dev->dev_private;
4192         int ret;
4193
4194         mutex_lock(&dev->struct_mutex);
4195
4196         if (IS_VALLEYVIEW(dev)) {
4197                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4198                 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4199                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4200                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4201         }
4202
4203         i915_gem_init_global_gtt(dev);
4204
4205         ret = i915_gem_init_hw(dev);
4206         mutex_unlock(&dev->struct_mutex);
4207         if (ret) {
4208                 i915_gem_cleanup_aliasing_ppgtt(dev);
4209                 return ret;
4210         }
4211
4212         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4213         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4214                 dev_priv->dri1.allow_batchbuffer = 1;
4215         return 0;
4216 }
4217
4218 void
4219 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4220 {
4221         drm_i915_private_t *dev_priv = dev->dev_private;
4222         struct intel_ring_buffer *ring;
4223         int i;
4224
4225         for_each_ring(ring, dev_priv, i)
4226                 intel_cleanup_ring_buffer(ring);
4227 }
4228
4229 int
4230 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4231                        struct drm_file *file_priv)
4232 {
4233         drm_i915_private_t *dev_priv = dev->dev_private;
4234         int ret;
4235
4236         if (drm_core_check_feature(dev, DRIVER_MODESET))
4237                 return 0;
4238
4239         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4240                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4241                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4242         }
4243
4244         mutex_lock(&dev->struct_mutex);
4245         dev_priv->mm.suspended = 0;
4246
4247         ret = i915_gem_init_hw(dev);
4248         if (ret != 0) {
4249                 mutex_unlock(&dev->struct_mutex);
4250                 return ret;
4251         }
4252
4253         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4254         mutex_unlock(&dev->struct_mutex);
4255
4256         ret = drm_irq_install(dev);
4257         if (ret)
4258                 goto cleanup_ringbuffer;
4259
4260         return 0;
4261
4262 cleanup_ringbuffer:
4263         mutex_lock(&dev->struct_mutex);
4264         i915_gem_cleanup_ringbuffer(dev);
4265         dev_priv->mm.suspended = 1;
4266         mutex_unlock(&dev->struct_mutex);
4267
4268         return ret;
4269 }
4270
4271 int
4272 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4273                        struct drm_file *file_priv)
4274 {
4275         if (drm_core_check_feature(dev, DRIVER_MODESET))
4276                 return 0;
4277
4278         drm_irq_uninstall(dev);
4279         return i915_gem_idle(dev);
4280 }
4281
4282 void
4283 i915_gem_lastclose(struct drm_device *dev)
4284 {
4285         int ret;
4286
4287         if (drm_core_check_feature(dev, DRIVER_MODESET))
4288                 return;
4289
4290         ret = i915_gem_idle(dev);
4291         if (ret)
4292                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4293 }
4294
4295 static void
4296 init_ring_lists(struct intel_ring_buffer *ring)
4297 {
4298         INIT_LIST_HEAD(&ring->active_list);
4299         INIT_LIST_HEAD(&ring->request_list);
4300 }
4301
4302 void
4303 i915_gem_load(struct drm_device *dev)
4304 {
4305         drm_i915_private_t *dev_priv = dev->dev_private;
4306         int i;
4307
4308         dev_priv->slab =
4309                 kmem_cache_create("i915_gem_object",
4310                                   sizeof(struct drm_i915_gem_object), 0,
4311                                   SLAB_HWCACHE_ALIGN,
4312                                   NULL);
4313
4314         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4315         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4316         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4317         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4318         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4319         for (i = 0; i < I915_NUM_RINGS; i++)
4320                 init_ring_lists(&dev_priv->ring[i]);
4321         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4322                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4323         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4324                           i915_gem_retire_work_handler);
4325         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4326
4327         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4328         if (IS_GEN3(dev)) {
4329                 I915_WRITE(MI_ARB_STATE,
4330                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4331         }
4332
4333         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4334
4335         /* Old X drivers will take 0-2 for front, back, depth buffers */
4336         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4337                 dev_priv->fence_reg_start = 3;
4338
4339         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4340                 dev_priv->num_fence_regs = 32;
4341         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4342                 dev_priv->num_fence_regs = 16;
4343         else
4344                 dev_priv->num_fence_regs = 8;
4345
4346         /* Initialize fence registers to zero */
4347         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4348         i915_gem_restore_fences(dev);
4349
4350         i915_gem_detect_bit_6_swizzle(dev);
4351         init_waitqueue_head(&dev_priv->pending_flip_queue);
4352
4353         dev_priv->mm.interruptible = true;
4354
4355         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4356         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4357         register_shrinker(&dev_priv->mm.inactive_shrinker);
4358 }
4359
4360 /*
4361  * Create a physically contiguous memory object for this object
4362  * e.g. for cursor + overlay regs
4363  */
4364 static int i915_gem_init_phys_object(struct drm_device *dev,
4365                                      int id, int size, int align)
4366 {
4367         drm_i915_private_t *dev_priv = dev->dev_private;
4368         struct drm_i915_gem_phys_object *phys_obj;
4369         int ret;
4370
4371         if (dev_priv->mm.phys_objs[id - 1] || !size)
4372                 return 0;
4373
4374         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4375         if (!phys_obj)
4376                 return -ENOMEM;
4377
4378         phys_obj->id = id;
4379
4380         phys_obj->handle = drm_pci_alloc(dev, size, align);
4381         if (!phys_obj->handle) {
4382                 ret = -ENOMEM;
4383                 goto kfree_obj;
4384         }
4385 #ifdef CONFIG_X86
4386         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4387 #endif
4388
4389         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4390
4391         return 0;
4392 kfree_obj:
4393         kfree(phys_obj);
4394         return ret;
4395 }
4396
4397 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4398 {
4399         drm_i915_private_t *dev_priv = dev->dev_private;
4400         struct drm_i915_gem_phys_object *phys_obj;
4401
4402         if (!dev_priv->mm.phys_objs[id - 1])
4403                 return;
4404
4405         phys_obj = dev_priv->mm.phys_objs[id - 1];
4406         if (phys_obj->cur_obj) {
4407                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4408         }
4409
4410 #ifdef CONFIG_X86
4411         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4412 #endif
4413         drm_pci_free(dev, phys_obj->handle);
4414         kfree(phys_obj);
4415         dev_priv->mm.phys_objs[id - 1] = NULL;
4416 }
4417
4418 void i915_gem_free_all_phys_object(struct drm_device *dev)
4419 {
4420         int i;
4421
4422         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4423                 i915_gem_free_phys_object(dev, i);
4424 }
4425
4426 void i915_gem_detach_phys_object(struct drm_device *dev,
4427                                  struct drm_i915_gem_object *obj)
4428 {
4429         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4430         char *vaddr;
4431         int i;
4432         int page_count;
4433
4434         if (!obj->phys_obj)
4435                 return;
4436         vaddr = obj->phys_obj->handle->vaddr;
4437
4438         page_count = obj->base.size / PAGE_SIZE;
4439         for (i = 0; i < page_count; i++) {
4440                 struct page *page = shmem_read_mapping_page(mapping, i);
4441                 if (!IS_ERR(page)) {
4442                         char *dst = kmap_atomic(page);
4443                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4444                         kunmap_atomic(dst);
4445
4446                         drm_clflush_pages(&page, 1);
4447
4448                         set_page_dirty(page);
4449                         mark_page_accessed(page);
4450                         page_cache_release(page);
4451                 }
4452         }
4453         i915_gem_chipset_flush(dev);
4454
4455         obj->phys_obj->cur_obj = NULL;
4456         obj->phys_obj = NULL;
4457 }
4458
4459 int
4460 i915_gem_attach_phys_object(struct drm_device *dev,
4461                             struct drm_i915_gem_object *obj,
4462                             int id,
4463                             int align)
4464 {
4465         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4466         drm_i915_private_t *dev_priv = dev->dev_private;
4467         int ret = 0;
4468         int page_count;
4469         int i;
4470
4471         if (id > I915_MAX_PHYS_OBJECT)
4472                 return -EINVAL;
4473
4474         if (obj->phys_obj) {
4475                 if (obj->phys_obj->id == id)
4476                         return 0;
4477                 i915_gem_detach_phys_object(dev, obj);
4478         }
4479
4480         /* create a new object */
4481         if (!dev_priv->mm.phys_objs[id - 1]) {
4482                 ret = i915_gem_init_phys_object(dev, id,
4483                                                 obj->base.size, align);
4484                 if (ret) {
4485                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4486                                   id, obj->base.size);
4487                         return ret;
4488                 }
4489         }
4490
4491         /* bind to the object */
4492         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4493         obj->phys_obj->cur_obj = obj;
4494
4495         page_count = obj->base.size / PAGE_SIZE;
4496
4497         for (i = 0; i < page_count; i++) {
4498                 struct page *page;
4499                 char *dst, *src;
4500
4501                 page = shmem_read_mapping_page(mapping, i);
4502                 if (IS_ERR(page))
4503                         return PTR_ERR(page);
4504
4505                 src = kmap_atomic(page);
4506                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4507                 memcpy(dst, src, PAGE_SIZE);
4508                 kunmap_atomic(src);
4509
4510                 mark_page_accessed(page);
4511                 page_cache_release(page);
4512         }
4513
4514         return 0;
4515 }
4516
4517 static int
4518 i915_gem_phys_pwrite(struct drm_device *dev,
4519                      struct drm_i915_gem_object *obj,
4520                      struct drm_i915_gem_pwrite *args,
4521                      struct drm_file *file_priv)
4522 {
4523         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4524         char __user *user_data = to_user_ptr(args->data_ptr);
4525
4526         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4527                 unsigned long unwritten;
4528
4529                 /* The physical object once assigned is fixed for the lifetime
4530                  * of the obj, so we can safely drop the lock and continue
4531                  * to access vaddr.
4532                  */
4533                 mutex_unlock(&dev->struct_mutex);
4534                 unwritten = copy_from_user(vaddr, user_data, args->size);
4535                 mutex_lock(&dev->struct_mutex);
4536                 if (unwritten)
4537                         return -EFAULT;
4538         }
4539
4540         i915_gem_chipset_flush(dev);
4541         return 0;
4542 }
4543
4544 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4545 {
4546         struct drm_i915_file_private *file_priv = file->driver_priv;
4547
4548         /* Clean up our request list when the client is going away, so that
4549          * later retire_requests won't dereference our soon-to-be-gone
4550          * file_priv.
4551          */
4552         spin_lock(&file_priv->mm.lock);
4553         while (!list_empty(&file_priv->mm.request_list)) {
4554                 struct drm_i915_gem_request *request;
4555
4556                 request = list_first_entry(&file_priv->mm.request_list,
4557                                            struct drm_i915_gem_request,
4558                                            client_list);
4559                 list_del(&request->client_list);
4560                 request->file_priv = NULL;
4561         }
4562         spin_unlock(&file_priv->mm.lock);
4563 }
4564
4565 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4566 {
4567         if (!mutex_is_locked(mutex))
4568                 return false;
4569
4570 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4571         return mutex->owner == task;
4572 #else
4573         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4574         return false;
4575 #endif
4576 }
4577
4578 static int
4579 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4580 {
4581         struct drm_i915_private *dev_priv =
4582                 container_of(shrinker,
4583                              struct drm_i915_private,
4584                              mm.inactive_shrinker);
4585         struct drm_device *dev = dev_priv->dev;
4586         struct drm_i915_gem_object *obj;
4587         int nr_to_scan = sc->nr_to_scan;
4588         bool unlock = true;
4589         int cnt;
4590
4591         if (!mutex_trylock(&dev->struct_mutex)) {
4592                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4593                         return 0;
4594
4595                 if (dev_priv->mm.shrinker_no_lock_stealing)
4596                         return 0;
4597
4598                 unlock = false;
4599         }
4600
4601         if (nr_to_scan) {
4602                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4603                 if (nr_to_scan > 0)
4604                         nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4605                                                         false);
4606                 if (nr_to_scan > 0)
4607                         i915_gem_shrink_all(dev_priv);
4608         }
4609
4610         cnt = 0;
4611         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4612                 if (obj->pages_pin_count == 0)
4613                         cnt += obj->base.size >> PAGE_SHIFT;
4614         list_for_each_entry(obj, &dev_priv->mm.inactive_list, global_list)
4615                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4616                         cnt += obj->base.size >> PAGE_SHIFT;
4617
4618         if (unlock)
4619                 mutex_unlock(&dev->struct_mutex);
4620         return cnt;
4621 }