drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33 #include <linux/shmem_fs.h>
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-buf.h>
  38
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  42                                                     unsigned alignment,
  43                                                     bool map_and_fenceable,
  44                                                     bool nonblocking);
  45 static int i915_gem_phys_pwrite(struct drm_device *dev,
  46                                 struct drm_i915_gem_object *obj,
  47                                 struct drm_i915_gem_pwrite *args,
  48                                 struct drm_file *file);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
  57                                     struct shrink_control *sc);
  58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  61
  62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  63 {
  64         if (obj->tiling_mode)
  65                 i915_gem_release_mmap(obj);
  66
  67         /* As we do not have an associated fence register, we will force
  68          * a tiling change if we ever need to acquire one.
  69          */
  70         obj->fence_dirty = false;
  71         obj->fence_reg = I915_FENCE_REG_NONE;
  72 }
  73
  74 /* some bookkeeping */
  75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  76                                   size_t size)
  77 {
  78         dev_priv->mm.object_count++;
  79         dev_priv->mm.object_memory += size;
  80 }
  81
  82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  83                                      size_t size)
  84 {
  85         dev_priv->mm.object_count--;
  86         dev_priv->mm.object_memory -= size;
  87 }
  88
  89 static int
  90 i915_gem_wait_for_error(struct i915_gpu_error *error)
  91 {
  92         int ret;
  93
  94 #define EXIT_COND (!i915_reset_in_progress(error) || \
  95                    i915_terminally_wedged(error))
  96         if (EXIT_COND)
  97                 return 0;
  98
  99         /*
 100          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 101          * userspace. If it takes that long something really bad is going on and
 102          * we should simply try to bail out and fail as gracefully as possible.
 103          */
 104         ret = wait_event_interruptible_timeout(error->reset_queue,
 105                                                EXIT_COND,
 106                                                10*HZ);
 107         if (ret == 0) {
 108                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 109                 return -EIO;
 110         } else if (ret < 0) {
 111                 return ret;
 112         }
 113 #undef EXIT_COND
 114
 115         return 0;
 116 }
 117
 118 int i915_mutex_lock_interruptible(struct drm_device *dev)
 119 {
 120         struct drm_i915_private *dev_priv = dev->dev_private;
 121         int ret;
 122
 123         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 124         if (ret)
 125                 return ret;
 126
 127         ret = mutex_lock_interruptible(&dev->struct_mutex);
 128         if (ret)
 129                 return ret;
 130
 131         WARN_ON(i915_verify_lists(dev));
 132         return 0;
 133 }
 134
 135 static inline bool
 136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 137 {
 138         return obj->gtt_space && !obj->active;
 139 }
 140
 141 int
 142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 143                     struct drm_file *file)
 144 {
 145         struct drm_i915_private *dev_priv = dev->dev_private;
 146         struct drm_i915_gem_init *args = data;
 147
 148         if (drm_core_check_feature(dev, DRIVER_MODESET))
 149                 return -ENODEV;
 150
 151         if (args->gtt_start >= args->gtt_end ||
 152             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 153                 return -EINVAL;
 154
 155         /* GEM with user mode setting was never supported on ilk and later. */
 156         if (INTEL_INFO(dev)->gen >= 5)
 157                 return -ENODEV;
 158
 159         mutex_lock(&dev->struct_mutex);
 160         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 161                                   args->gtt_end);
 162         dev_priv->gtt.mappable_end = args->gtt_end;
 163         mutex_unlock(&dev->struct_mutex);
 164
 165         return 0;
 166 }
 167
 168 int
 169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 170                             struct drm_file *file)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         struct drm_i915_gem_get_aperture *args = data;
 174         struct drm_i915_gem_object *obj;
 175         size_t pinned;
 176
 177         pinned = 0;
 178         mutex_lock(&dev->struct_mutex);
 179         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 180                 if (obj->pin_count)
 181                         pinned += obj->gtt_space->size;
 182         mutex_unlock(&dev->struct_mutex);
 183
 184         args->aper_size = dev_priv->gtt.total;
 185         args->aper_available_size = args->aper_size - pinned;
 186
 187         return 0;
 188 }
 189
 190 void *i915_gem_object_alloc(struct drm_device *dev)
 191 {
 192         struct drm_i915_private *dev_priv = dev->dev_private;
 193         return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
 194 }
 195
 196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 197 {
 198         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 199         kmem_cache_free(dev_priv->slab, obj);
 200 }
 201
 202 static int
 203 i915_gem_create(struct drm_file *file,
 204                 struct drm_device *dev,
 205                 uint64_t size,
 206                 uint32_t *handle_p)
 207 {
 208         struct drm_i915_gem_object *obj;
 209         int ret;
 210         u32 handle;
 211
 212         size = roundup(size, PAGE_SIZE);
 213         if (size == 0)
 214                 return -EINVAL;
 215
 216         /* Allocate the new object */
 217         obj = i915_gem_alloc_object(dev, size);
 218         if (obj == NULL)
 219                 return -ENOMEM;
 220
 221         ret = drm_gem_handle_create(file, &obj->base, &handle);
 222         if (ret) {
 223                 drm_gem_object_release(&obj->base);
 224                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 225                 i915_gem_object_free(obj);
 226                 return ret;
 227         }
 228
 229         /* drop reference from allocate - handle holds it now */
 230         drm_gem_object_unreference(&obj->base);
 231         trace_i915_gem_object_create(obj);
 232
 233         *handle_p = handle;
 234         return 0;
 235 }
 236
 237 int
 238 i915_gem_dumb_create(struct drm_file *file,
 239                      struct drm_device *dev,
 240                      struct drm_mode_create_dumb *args)
 241 {
 242         /* have to work out size/pitch and return them */
 243         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
 244         args->size = args->pitch * args->height;
 245         return i915_gem_create(file, dev,
 246                                args->size, &args->handle);
 247 }
 248
 249 int i915_gem_dumb_destroy(struct drm_file *file,
 250                           struct drm_device *dev,
 251                           uint32_t handle)
 252 {
 253         return drm_gem_handle_delete(file, handle);
 254 }
 255
 256 /**
 257  * Creates a new mm object and returns a handle to it.
 258  */
 259 int
 260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 261                       struct drm_file *file)
 262 {
 263         struct drm_i915_gem_create *args = data;
 264
 265         return i915_gem_create(file, dev,
 266                                args->size, &args->handle);
 267 }
 268
 269 static inline int
 270 __copy_to_user_swizzled(char __user *cpu_vaddr,
 271                         const char *gpu_vaddr, int gpu_offset,
 272                         int length)
 273 {
 274         int ret, cpu_offset = 0;
 275
 276         while (length > 0) {
 277                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 278                 int this_length = min(cacheline_end - gpu_offset, length);
 279                 int swizzled_gpu_offset = gpu_offset ^ 64;
 280
 281                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 282                                      gpu_vaddr + swizzled_gpu_offset,
 283                                      this_length);
 284                 if (ret)
 285                         return ret + length;
 286
 287                 cpu_offset += this_length;
 288                 gpu_offset += this_length;
 289                 length -= this_length;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static inline int
 296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 297                           const char __user *cpu_vaddr,
 298                           int length)
 299 {
 300         int ret, cpu_offset = 0;
 301
 302         while (length > 0) {
 303                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 304                 int this_length = min(cacheline_end - gpu_offset, length);
 305                 int swizzled_gpu_offset = gpu_offset ^ 64;
 306
 307                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 308                                        cpu_vaddr + cpu_offset,
 309                                        this_length);
 310                 if (ret)
 311                         return ret + length;
 312
 313                 cpu_offset += this_length;
 314                 gpu_offset += this_length;
 315                 length -= this_length;
 316         }
 317
 318         return 0;
 319 }
 320
 321 /* Per-page copy function for the shmem pread fastpath.
 322  * Flushes invalid cachelines before reading the target if
 323  * needs_clflush is set. */
 324 static int
 325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 326                  char __user *user_data,
 327                  bool page_do_bit17_swizzling, bool needs_clflush)
 328 {
 329         char *vaddr;
 330         int ret;
 331
 332         if (unlikely(page_do_bit17_swizzling))
 333                 return -EINVAL;
 334
 335         vaddr = kmap_atomic(page);
 336         if (needs_clflush)
 337                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 338                                        page_length);
 339         ret = __copy_to_user_inatomic(user_data,
 340                                       vaddr + shmem_page_offset,
 341                                       page_length);
 342         kunmap_atomic(vaddr);
 343
 344         return ret ? -EFAULT : 0;
 345 }
 346
 347 static void
 348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 349                              bool swizzled)
 350 {
 351         if (unlikely(swizzled)) {
 352                 unsigned long start = (unsigned long) addr;
 353                 unsigned long end = (unsigned long) addr + length;
 354
 355                 /* For swizzling simply ensure that we always flush both
 356                  * channels. Lame, but simple and it works. Swizzled
 357                  * pwrite/pread is far from a hotpath - current userspace
 358                  * doesn't use it at all. */
 359                 start = round_down(start, 128);
 360                 end = round_up(end, 128);
 361
 362                 drm_clflush_virt_range((void *)start, end - start);
 363         } else {
 364                 drm_clflush_virt_range(addr, length);
 365         }
 366
 367 }
 368
 369 /* Only difference to the fast-path function is that this can handle bit17
 370  * and uses non-atomic copy and kmap functions. */
 371 static int
 372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 373                  char __user *user_data,
 374                  bool page_do_bit17_swizzling, bool needs_clflush)
 375 {
 376         char *vaddr;
 377         int ret;
 378
 379         vaddr = kmap(page);
 380         if (needs_clflush)
 381                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 382                                              page_length,
 383                                              page_do_bit17_swizzling);
 384
 385         if (page_do_bit17_swizzling)
 386                 ret = __copy_to_user_swizzled(user_data,
 387                                               vaddr, shmem_page_offset,
 388                                               page_length);
 389         else
 390                 ret = __copy_to_user(user_data,
 391                                      vaddr + shmem_page_offset,
 392                                      page_length);
 393         kunmap(page);
 394
 395         return ret ? - EFAULT : 0;
 396 }
 397
 398 static int
 399 i915_gem_shmem_pread(struct drm_device *dev,
 400                      struct drm_i915_gem_object *obj,
 401                      struct drm_i915_gem_pread *args,
 402                      struct drm_file *file)
 403 {
 404         char __user *user_data;
 405         ssize_t remain;
 406         loff_t offset;
 407         int shmem_page_offset, page_length, ret = 0;
 408         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 409         int prefaulted = 0;
 410         int needs_clflush = 0;
 411         struct sg_page_iter sg_iter;
 412
 413         user_data = to_user_ptr(args->data_ptr);
 414         remain = args->size;
 415
 416         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 417
 418         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 419                 /* If we're not in the cpu read domain, set ourself into the gtt
 420                  * read domain and manually flush cachelines (if required). This
 421                  * optimizes for the case when the gpu will dirty the data
 422                  * anyway again before the next pread happens. */
 423                 if (obj->cache_level == I915_CACHE_NONE)
 424                         needs_clflush = 1;
 425                 if (obj->gtt_space) {
 426                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 427                         if (ret)
 428                                 return ret;
 429                 }
 430         }
 431
 432         ret = i915_gem_object_get_pages(obj);
 433         if (ret)
 434                 return ret;
 435
 436         i915_gem_object_pin_pages(obj);
 437
 438         offset = args->offset;
 439
 440         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 441                          offset >> PAGE_SHIFT) {
 442                 struct page *page = sg_page_iter_page(&sg_iter);
 443
 444                 if (remain <= 0)
 445                         break;
 446
 447                 /* Operation in this page
 448                  *
 449                  * shmem_page_offset = offset within page in shmem file
 450                  * page_length = bytes to copy for this page
 451                  */
 452                 shmem_page_offset = offset_in_page(offset);
 453                 page_length = remain;
 454                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 455                         page_length = PAGE_SIZE - shmem_page_offset;
 456
 457                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 458                         (page_to_phys(page) & (1 << 17)) != 0;
 459
 460                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 461                                        user_data, page_do_bit17_swizzling,
 462                                        needs_clflush);
 463                 if (ret == 0)
 464                         goto next_page;
 465
 466                 mutex_unlock(&dev->struct_mutex);
 467
 468                 if (!prefaulted) {
 469                         ret = fault_in_multipages_writeable(user_data, remain);
 470                         /* Userspace is tricking us, but we've already clobbered
 471                          * its pages with the prefault and promised to write the
 472                          * data up to the first fault. Hence ignore any errors
 473                          * and just continue. */
 474                         (void)ret;
 475                         prefaulted = 1;
 476                 }
 477
 478                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 479                                        user_data, page_do_bit17_swizzling,
 480                                        needs_clflush);
 481
 482                 mutex_lock(&dev->struct_mutex);
 483
 484 next_page:
 485                 mark_page_accessed(page);
 486
 487                 if (ret)
 488                         goto out;
 489
 490                 remain -= page_length;
 491                 user_data += page_length;
 492                 offset += page_length;
 493         }
 494
 495 out:
 496         i915_gem_object_unpin_pages(obj);
 497
 498         return ret;
 499 }
 500
 501 /**
 502  * Reads data from the object referenced by handle.
 503  *
 504  * On error, the contents of *data are undefined.
 505  */
 506 int
 507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 508                      struct drm_file *file)
 509 {
 510         struct drm_i915_gem_pread *args = data;
 511         struct drm_i915_gem_object *obj;
 512         int ret = 0;
 513
 514         if (args->size == 0)
 515                 return 0;
 516
 517         if (!access_ok(VERIFY_WRITE,
 518                        to_user_ptr(args->data_ptr),
 519                        args->size))
 520                 return -EFAULT;
 521
 522         ret = i915_mutex_lock_interruptible(dev);
 523         if (ret)
 524                 return ret;
 525
 526         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 527         if (&obj->base == NULL) {
 528                 ret = -ENOENT;
 529                 goto unlock;
 530         }
 531
 532         /* Bounds check source.  */
 533         if (args->offset > obj->base.size ||
 534             args->size > obj->base.size - args->offset) {
 535                 ret = -EINVAL;
 536                 goto out;
 537         }
 538
 539         /* prime objects have no backing filp to GEM pread/pwrite
 540          * pages from.
 541          */
 542         if (!obj->base.filp) {
 543                 ret = -EINVAL;
 544                 goto out;
 545         }
 546
 547         trace_i915_gem_object_pread(obj, args->offset, args->size);
 548
 549         ret = i915_gem_shmem_pread(dev, obj, args, file);
 550
 551 out:
 552         drm_gem_object_unreference(&obj->base);
 553 unlock:
 554         mutex_unlock(&dev->struct_mutex);
 555         return ret;
 556 }
 557
 558 /* This is the fast write path which cannot handle
 559  * page faults in the source data
 560  */
 561
 562 static inline int
 563 fast_user_write(struct io_mapping *mapping,
 564                 loff_t page_base, int page_offset,
 565                 char __user *user_data,
 566                 int length)
 567 {
 568         void __iomem *vaddr_atomic;
 569         void *vaddr;
 570         unsigned long unwritten;
 571
 572         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 573         /* We can use the cpu mem copy function because this is X86. */
 574         vaddr = (void __force*)vaddr_atomic + page_offset;
 575         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 576                                                       user_data, length);
 577         io_mapping_unmap_atomic(vaddr_atomic);
 578         return unwritten;
 579 }
 580
 581 /**
 582  * This is the fast pwrite path, where we copy the data directly from the
 583  * user into the GTT, uncached.
 584  */
 585 static int
 586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 587                          struct drm_i915_gem_object *obj,
 588                          struct drm_i915_gem_pwrite *args,
 589                          struct drm_file *file)
 590 {
 591         drm_i915_private_t *dev_priv = dev->dev_private;
 592         ssize_t remain;
 593         loff_t offset, page_base;
 594         char __user *user_data;
 595         int page_offset, page_length, ret;
 596
 597         ret = i915_gem_object_pin(obj, 0, true, true);
 598         if (ret)
 599                 goto out;
 600
 601         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 602         if (ret)
 603                 goto out_unpin;
 604
 605         ret = i915_gem_object_put_fence(obj);
 606         if (ret)
 607                 goto out_unpin;
 608
 609         user_data = to_user_ptr(args->data_ptr);
 610         remain = args->size;
 611
 612         offset = obj->gtt_offset + args->offset;
 613
 614         while (remain > 0) {
 615                 /* Operation in this page
 616                  *
 617                  * page_base = page offset within aperture
 618                  * page_offset = offset within page
 619                  * page_length = bytes to copy for this page
 620                  */
 621                 page_base = offset & PAGE_MASK;
 622                 page_offset = offset_in_page(offset);
 623                 page_length = remain;
 624                 if ((page_offset + remain) > PAGE_SIZE)
 625                         page_length = PAGE_SIZE - page_offset;
 626
 627                 /* If we get a fault while copying data, then (presumably) our
 628                  * source page isn't available.  Return the error and we'll
 629                  * retry in the slow path.
 630                  */
 631                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 632                                     page_offset, user_data, page_length)) {
 633                         ret = -EFAULT;
 634                         goto out_unpin;
 635                 }
 636
 637                 remain -= page_length;
 638                 user_data += page_length;
 639                 offset += page_length;
 640         }
 641
 642 out_unpin:
 643         i915_gem_object_unpin(obj);
 644 out:
 645         return ret;
 646 }
 647
 648 /* Per-page copy function for the shmem pwrite fastpath.
 649  * Flushes invalid cachelines before writing to the target if
 650  * needs_clflush_before is set and flushes out any written cachelines after
 651  * writing if needs_clflush is set. */
 652 static int
 653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 654                   char __user *user_data,
 655                   bool page_do_bit17_swizzling,
 656                   bool needs_clflush_before,
 657                   bool needs_clflush_after)
 658 {
 659         char *vaddr;
 660         int ret;
 661
 662         if (unlikely(page_do_bit17_swizzling))
 663                 return -EINVAL;
 664
 665         vaddr = kmap_atomic(page);
 666         if (needs_clflush_before)
 667                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 668                                        page_length);
 669         ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
 670                                                 user_data,
 671                                                 page_length);
 672         if (needs_clflush_after)
 673                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 674                                        page_length);
 675         kunmap_atomic(vaddr);
 676
 677         return ret ? -EFAULT : 0;
 678 }
 679
 680 /* Only difference to the fast-path function is that this can handle bit17
 681  * and uses non-atomic copy and kmap functions. */
 682 static int
 683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 684                   char __user *user_data,
 685                   bool page_do_bit17_swizzling,
 686                   bool needs_clflush_before,
 687                   bool needs_clflush_after)
 688 {
 689         char *vaddr;
 690         int ret;
 691
 692         vaddr = kmap(page);
 693         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 694                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 695                                              page_length,
 696                                              page_do_bit17_swizzling);
 697         if (page_do_bit17_swizzling)
 698                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 699                                                 user_data,
 700                                                 page_length);
 701         else
 702                 ret = __copy_from_user(vaddr + shmem_page_offset,
 703                                        user_data,
 704                                        page_length);
 705         if (needs_clflush_after)
 706                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 707                                              page_length,
 708                                              page_do_bit17_swizzling);
 709         kunmap(page);
 710
 711         return ret ? -EFAULT : 0;
 712 }
 713
 714 static int
 715 i915_gem_shmem_pwrite(struct drm_device *dev,
 716                       struct drm_i915_gem_object *obj,
 717                       struct drm_i915_gem_pwrite *args,
 718                       struct drm_file *file)
 719 {
 720         ssize_t remain;
 721         loff_t offset;
 722         char __user *user_data;
 723         int shmem_page_offset, page_length, ret = 0;
 724         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 725         int hit_slowpath = 0;
 726         int needs_clflush_after = 0;
 727         int needs_clflush_before = 0;
 728         struct sg_page_iter sg_iter;
 729
 730         user_data = to_user_ptr(args->data_ptr);
 731         remain = args->size;
 732
 733         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 734
 735         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 736                 /* If we're not in the cpu write domain, set ourself into the gtt
 737                  * write domain and manually flush cachelines (if required). This
 738                  * optimizes for the case when the gpu will use the data
 739                  * right away and we therefore have to clflush anyway. */
 740                 if (obj->cache_level == I915_CACHE_NONE)
 741                         needs_clflush_after = 1;
 742                 if (obj->gtt_space) {
 743                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 744                         if (ret)
 745                                 return ret;
 746                 }
 747         }
 748         /* Same trick applies for invalidate partially written cachelines before
 749          * writing.  */
 750         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
 751             && obj->cache_level == I915_CACHE_NONE)
 752                 needs_clflush_before = 1;
 753
 754         ret = i915_gem_object_get_pages(obj);
 755         if (ret)
 756                 return ret;
 757
 758         i915_gem_object_pin_pages(obj);
 759
 760         offset = args->offset;
 761         obj->dirty = 1;
 762
 763         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 764                          offset >> PAGE_SHIFT) {
 765                 struct page *page = sg_page_iter_page(&sg_iter);
 766                 int partial_cacheline_write;
 767
 768                 if (remain <= 0)
 769                         break;
 770
 771                 /* Operation in this page
 772                  *
 773                  * shmem_page_offset = offset within page in shmem file
 774                  * page_length = bytes to copy for this page
 775                  */
 776                 shmem_page_offset = offset_in_page(offset);
 777
 778                 page_length = remain;
 779                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 780                         page_length = PAGE_SIZE - shmem_page_offset;
 781
 782                 /* If we don't overwrite a cacheline completely we need to be
 783                  * careful to have up-to-date data by first clflushing. Don't
 784                  * overcomplicate things and flush the entire patch. */
 785                 partial_cacheline_write = needs_clflush_before &&
 786                         ((shmem_page_offset | page_length)
 787                                 & (boot_cpu_data.x86_clflush_size - 1));
 788
 789                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 790                         (page_to_phys(page) & (1 << 17)) != 0;
 791
 792                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 793                                         user_data, page_do_bit17_swizzling,
 794                                         partial_cacheline_write,
 795                                         needs_clflush_after);
 796                 if (ret == 0)
 797                         goto next_page;
 798
 799                 hit_slowpath = 1;
 800                 mutex_unlock(&dev->struct_mutex);
 801                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 802                                         user_data, page_do_bit17_swizzling,
 803                                         partial_cacheline_write,
 804                                         needs_clflush_after);
 805
 806                 mutex_lock(&dev->struct_mutex);
 807
 808 next_page:
 809                 set_page_dirty(page);
 810                 mark_page_accessed(page);
 811
 812                 if (ret)
 813                         goto out;
 814
 815                 remain -= page_length;
 816                 user_data += page_length;
 817                 offset += page_length;
 818         }
 819
 820 out:
 821         i915_gem_object_unpin_pages(obj);
 822
 823         if (hit_slowpath) {
 824                 /*
 825                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 826                  * cachelines in-line while writing and the object moved
 827                  * out of the cpu write domain while we've dropped the lock.
 828                  */
 829                 if (!needs_clflush_after &&
 830                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 831                         i915_gem_clflush_object(obj);
 832                         i915_gem_chipset_flush(dev);
 833                 }
 834         }
 835
 836         if (needs_clflush_after)
 837                 i915_gem_chipset_flush(dev);
 838
 839         return ret;
 840 }
 841
 842 /**
 843  * Writes data to the object referenced by handle.
 844  *
 845  * On error, the contents of the buffer that were to be modified are undefined.
 846  */
 847 int
 848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 849                       struct drm_file *file)
 850 {
 851         struct drm_i915_gem_pwrite *args = data;
 852         struct drm_i915_gem_object *obj;
 853         int ret;
 854
 855         if (args->size == 0)
 856                 return 0;
 857
 858         if (!access_ok(VERIFY_READ,
 859                        to_user_ptr(args->data_ptr),
 860                        args->size))
 861                 return -EFAULT;
 862
 863         ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
 864                                            args->size);
 865         if (ret)
 866                 return -EFAULT;
 867
 868         ret = i915_mutex_lock_interruptible(dev);
 869         if (ret)
 870                 return ret;
 871
 872         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 873         if (&obj->base == NULL) {
 874                 ret = -ENOENT;
 875                 goto unlock;
 876         }
 877
 878         /* Bounds check destination. */
 879         if (args->offset > obj->base.size ||
 880             args->size > obj->base.size - args->offset) {
 881                 ret = -EINVAL;
 882                 goto out;
 883         }
 884
 885         /* prime objects have no backing filp to GEM pread/pwrite
 886          * pages from.
 887          */
 888         if (!obj->base.filp) {
 889                 ret = -EINVAL;
 890                 goto out;
 891         }
 892
 893         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
 894
 895         ret = -EFAULT;
 896         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 897          * it would end up going through the fenced access, and we'll get
 898          * different detiling behavior between reading and writing.
 899          * pread/pwrite currently are reading and writing from the CPU
 900          * perspective, requiring manual detiling by the client.
 901          */
 902         if (obj->phys_obj) {
 903                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
 904                 goto out;
 905         }
 906
 907         if (obj->cache_level == I915_CACHE_NONE &&
 908             obj->tiling_mode == I915_TILING_NONE &&
 909             obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 910                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
 911                 /* Note that the gtt paths might fail with non-page-backed user
 912                  * pointers (e.g. gtt mappings when moving data between
 913                  * textures). Fallback to the shmem path in that case. */
 914         }
 915
 916         if (ret == -EFAULT || ret == -ENOSPC)
 917                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
 918
 919 out:
 920         drm_gem_object_unreference(&obj->base);
 921 unlock:
 922         mutex_unlock(&dev->struct_mutex);
 923         return ret;
 924 }
 925
 926 int
 927 i915_gem_check_wedge(struct i915_gpu_error *error,
 928                      bool interruptible)
 929 {
 930         if (i915_reset_in_progress(error)) {
 931                 /* Non-interruptible callers can't handle -EAGAIN, hence return
 932                  * -EIO unconditionally for these. */
 933                 if (!interruptible)
 934                         return -EIO;
 935
 936                 /* Recovery complete, but the reset failed ... */
 937                 if (i915_terminally_wedged(error))
 938                         return -EIO;
 939
 940                 return -EAGAIN;
 941         }
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Compare seqno against outstanding lazy request. Emit a request if they are
 948  * equal.
 949  */
 950 static int
 951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
 952 {
 953         int ret;
 954
 955         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
 956
 957         ret = 0;
 958         if (seqno == ring->outstanding_lazy_request)
 959                 ret = i915_add_request(ring, NULL);
 960
 961         return ret;
 962 }
 963
 964 /**
 965  * __wait_seqno - wait until execution of seqno has finished
 966  * @ring: the ring expected to report seqno
 967  * @seqno: duh!
 968  * @reset_counter: reset sequence associated with the given seqno
 969  * @interruptible: do an interruptible wait (normally yes)
 970  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
 971  *
 972  * Note: It is of utmost importance that the passed in seqno and reset_counter
 973  * values have been read by the caller in an smp safe manner. Where read-side
 974  * locks are involved, it is sufficient to read the reset_counter before
 975  * unlocking the lock that protects the seqno. For lockless tricks, the
 976  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
 977  * inserted.
 978  *
 979  * Returns 0 if the seqno was found within the alloted time. Else returns the
 980  * errno with remaining time filled in timeout argument.
 981  */
 982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
 983                         unsigned reset_counter,
 984                         bool interruptible, struct timespec *timeout)
 985 {
 986         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 987         struct timespec before, now, wait_time={1,0};
 988         unsigned long timeout_jiffies;
 989         long end;
 990         bool wait_forever = true;
 991         int ret;
 992
 993         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 994                 return 0;
 995
 996         trace_i915_gem_request_wait_begin(ring, seqno);
 997
 998         if (timeout != NULL) {
 999                 wait_time = *timeout;
1000                 wait_forever = false;
1001         }
1002
1003         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1004
1005         if (WARN_ON(!ring->irq_get(ring)))
1006                 return -ENODEV;
1007
1008         /* Record current time in case interrupted by signal, or wedged * */
1009         getrawmonotonic(&before);
1010
1011 #define EXIT_COND \
1012         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013          i915_reset_in_progress(&dev_priv->gpu_error) || \
1014          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1015         do {
1016                 if (interruptible)
1017                         end = wait_event_interruptible_timeout(ring->irq_queue,
1018                                                                EXIT_COND,
1019                                                                timeout_jiffies);
1020                 else
1021                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1022                                                  timeout_jiffies);
1023
1024                 /* We need to check whether any gpu reset happened in between
1025                  * the caller grabbing the seqno and now ... */
1026                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1027                         end = -EAGAIN;
1028
1029                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1030                  * gone. */
1031                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1032                 if (ret)
1033                         end = ret;
1034         } while (end == 0 && wait_forever);
1035
1036         getrawmonotonic(&now);
1037
1038         ring->irq_put(ring);
1039         trace_i915_gem_request_wait_end(ring, seqno);
1040 #undef EXIT_COND
1041
1042         if (timeout) {
1043                 struct timespec sleep_time = timespec_sub(now, before);
1044                 *timeout = timespec_sub(*timeout, sleep_time);
1045                 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046                         set_normalized_timespec(timeout, 0, 0);
1047         }
1048
1049         switch (end) {
1050         case -EIO:
1051         case -EAGAIN: /* Wedged */
1052         case -ERESTARTSYS: /* Signal */
1053                 return (int)end;
1054         case 0: /* Timeout */
1055                 return -ETIME;
1056         default: /* Completed */
1057                 WARN_ON(end < 0); /* We're not aware of other errors */
1058                 return 0;
1059         }
1060 }
1061
1062 /**
1063  * Waits for a sequence number to be signaled, and cleans up the
1064  * request and object lists appropriately for that event.
1065  */
1066 int
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1068 {
1069         struct drm_device *dev = ring->dev;
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         bool interruptible = dev_priv->mm.interruptible;
1072         int ret;
1073
1074         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1075         BUG_ON(seqno == 0);
1076
1077         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1078         if (ret)
1079                 return ret;
1080
1081         ret = i915_gem_check_olr(ring, seqno);
1082         if (ret)
1083                 return ret;
1084
1085         return __wait_seqno(ring, seqno,
1086                             atomic_read(&dev_priv->gpu_error.reset_counter),
1087                             interruptible, NULL);
1088 }
1089
1090 static int
1091 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1092                                      struct intel_ring_buffer *ring)
1093 {
1094         i915_gem_retire_requests_ring(ring);
1095
1096         /* Manually manage the write flush as we may have not yet
1097          * retired the buffer.
1098          *
1099          * Note that the last_write_seqno is always the earlier of
1100          * the two (read/write) seqno, so if we haved successfully waited,
1101          * we know we have passed the last write.
1102          */
1103         obj->last_write_seqno = 0;
1104         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1105
1106         return 0;
1107 }
1108
1109 /**
1110  * Ensures that all rendering to the object has completed and the object is
1111  * safe to unbind from the GTT or access from the CPU.
1112  */
1113 static __must_check int
1114 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1115                                bool readonly)
1116 {
1117         struct intel_ring_buffer *ring = obj->ring;
1118         u32 seqno;
1119         int ret;
1120
1121         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1122         if (seqno == 0)
1123                 return 0;
1124
1125         ret = i915_wait_seqno(ring, seqno);
1126         if (ret)
1127                 return ret;
1128
1129         return i915_gem_object_wait_rendering__tail(obj, ring);
1130 }
1131
1132 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1133  * as the object state may change during this call.
1134  */
1135 static __must_check int
1136 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1137                                             bool readonly)
1138 {
1139         struct drm_device *dev = obj->base.dev;
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141         struct intel_ring_buffer *ring = obj->ring;
1142         unsigned reset_counter;
1143         u32 seqno;
1144         int ret;
1145
1146         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1147         BUG_ON(!dev_priv->mm.interruptible);
1148
1149         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1150         if (seqno == 0)
1151                 return 0;
1152
1153         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1154         if (ret)
1155                 return ret;
1156
1157         ret = i915_gem_check_olr(ring, seqno);
1158         if (ret)
1159                 return ret;
1160
1161         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1162         mutex_unlock(&dev->struct_mutex);
1163         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1164         mutex_lock(&dev->struct_mutex);
1165         if (ret)
1166                 return ret;
1167
1168         return i915_gem_object_wait_rendering__tail(obj, ring);
1169 }
1170
1171 /**
1172  * Called when user space prepares to use an object with the CPU, either
1173  * through the mmap ioctl's mapping or a GTT mapping.
1174  */
1175 int
1176 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1177                           struct drm_file *file)
1178 {
1179         struct drm_i915_gem_set_domain *args = data;
1180         struct drm_i915_gem_object *obj;
1181         uint32_t read_domains = args->read_domains;
1182         uint32_t write_domain = args->write_domain;
1183         int ret;
1184
1185         /* Only handle setting domains to types used by the CPU. */
1186         if (write_domain & I915_GEM_GPU_DOMAINS)
1187                 return -EINVAL;
1188
1189         if (read_domains & I915_GEM_GPU_DOMAINS)
1190                 return -EINVAL;
1191
1192         /* Having something in the write domain implies it's in the read
1193          * domain, and only that read domain.  Enforce that in the request.
1194          */
1195         if (write_domain != 0 && read_domains != write_domain)
1196                 return -EINVAL;
1197
1198         ret = i915_mutex_lock_interruptible(dev);
1199         if (ret)
1200                 return ret;
1201
1202         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1203         if (&obj->base == NULL) {
1204                 ret = -ENOENT;
1205                 goto unlock;
1206         }
1207
1208         /* Try to flush the object off the GPU without holding the lock.
1209          * We will repeat the flush holding the lock in the normal manner
1210          * to catch cases where we are gazumped.
1211          */
1212         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1213         if (ret)
1214                 goto unref;
1215
1216         if (read_domains & I915_GEM_DOMAIN_GTT) {
1217                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1218
1219                 /* Silently promote "you're not bound, there was nothing to do"
1220                  * to success, since the client was just asking us to
1221                  * make sure everything was done.
1222                  */
1223                 if (ret == -EINVAL)
1224                         ret = 0;
1225         } else {
1226                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1227         }
1228
1229 unref:
1230         drm_gem_object_unreference(&obj->base);
1231 unlock:
1232         mutex_unlock(&dev->struct_mutex);
1233         return ret;
1234 }
1235
1236 /**
1237  * Called when user space has done writes to this buffer
1238  */
1239 int
1240 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1241                          struct drm_file *file)
1242 {
1243         struct drm_i915_gem_sw_finish *args = data;
1244         struct drm_i915_gem_object *obj;
1245         int ret = 0;
1246
1247         ret = i915_mutex_lock_interruptible(dev);
1248         if (ret)
1249                 return ret;
1250
1251         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1252         if (&obj->base == NULL) {
1253                 ret = -ENOENT;
1254                 goto unlock;
1255         }
1256
1257         /* Pinned buffers may be scanout, so flush the cache */
1258         if (obj->pin_count)
1259                 i915_gem_object_flush_cpu_write_domain(obj);
1260
1261         drm_gem_object_unreference(&obj->base);
1262 unlock:
1263         mutex_unlock(&dev->struct_mutex);
1264         return ret;
1265 }
1266
1267 /**
1268  * Maps the contents of an object, returning the address it is mapped
1269  * into.
1270  *
1271  * While the mapping holds a reference on the contents of the object, it doesn't
1272  * imply a ref on the object itself.
1273  */
1274 int
1275 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1276                     struct drm_file *file)
1277 {
1278         struct drm_i915_gem_mmap *args = data;
1279         struct drm_gem_object *obj;
1280         unsigned long addr;
1281
1282         obj = drm_gem_object_lookup(dev, file, args->handle);
1283         if (obj == NULL)
1284                 return -ENOENT;
1285
1286         /* prime objects have no backing filp to GEM mmap
1287          * pages from.
1288          */
1289         if (!obj->filp) {
1290                 drm_gem_object_unreference_unlocked(obj);
1291                 return -EINVAL;
1292         }
1293
1294         addr = vm_mmap(obj->filp, 0, args->size,
1295                        PROT_READ | PROT_WRITE, MAP_SHARED,
1296                        args->offset);
1297         drm_gem_object_unreference_unlocked(obj);
1298         if (IS_ERR((void *)addr))
1299                 return addr;
1300
1301         args->addr_ptr = (uint64_t) addr;
1302
1303         return 0;
1304 }
1305
1306 /**
1307  * i915_gem_fault - fault a page into the GTT
1308  * vma: VMA in question
1309  * vmf: fault info
1310  *
1311  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1312  * from userspace.  The fault handler takes care of binding the object to
1313  * the GTT (if needed), allocating and programming a fence register (again,
1314  * only if needed based on whether the old reg is still valid or the object
1315  * is tiled) and inserting a new PTE into the faulting process.
1316  *
1317  * Note that the faulting process may involve evicting existing objects
1318  * from the GTT and/or fence registers to make room.  So performance may
1319  * suffer if the GTT working set is large or there are few fence registers
1320  * left.
1321  */
1322 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1323 {
1324         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1325         struct drm_device *dev = obj->base.dev;
1326         drm_i915_private_t *dev_priv = dev->dev_private;
1327         pgoff_t page_offset;
1328         unsigned long pfn;
1329         int ret = 0;
1330         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1331
1332         /* We don't use vmf->pgoff since that has the fake offset */
1333         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1334                 PAGE_SHIFT;
1335
1336         ret = i915_mutex_lock_interruptible(dev);
1337         if (ret)
1338                 goto out;
1339
1340         trace_i915_gem_object_fault(obj, page_offset, true, write);
1341
1342         /* Access to snoopable pages through the GTT is incoherent. */
1343         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1344                 ret = -EINVAL;
1345                 goto unlock;
1346         }
1347
1348         /* Now bind it into the GTT if needed */
1349         ret = i915_gem_object_pin(obj, 0, true, false);
1350         if (ret)
1351                 goto unlock;
1352
1353         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1354         if (ret)
1355                 goto unpin;
1356
1357         ret = i915_gem_object_get_fence(obj);
1358         if (ret)
1359                 goto unpin;
1360
1361         obj->fault_mappable = true;
1362
1363         pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1364                 page_offset;
1365
1366         /* Finally, remap it using the new GTT offset */
1367         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1368 unpin:
1369         i915_gem_object_unpin(obj);
1370 unlock:
1371         mutex_unlock(&dev->struct_mutex);
1372 out:
1373         switch (ret) {
1374         case -EIO:
1375                 /* If this -EIO is due to a gpu hang, give the reset code a
1376                  * chance to clean up the mess. Otherwise return the proper
1377                  * SIGBUS. */
1378                 if (i915_terminally_wedged(&dev_priv->gpu_error))
1379                         return VM_FAULT_SIGBUS;
1380         case -EAGAIN:
1381                 /* Give the error handler a chance to run and move the
1382                  * objects off the GPU active list. Next time we service the
1383                  * fault, we should be able to transition the page into the
1384                  * GTT without touching the GPU (and so avoid further
1385                  * EIO/EGAIN). If the GPU is wedged, then there is no issue
1386                  * with coherency, just lost writes.
1387                  */
1388                 set_need_resched();
1389         case 0:
1390         case -ERESTARTSYS:
1391         case -EINTR:
1392         case -EBUSY:
1393                 /*
1394                  * EBUSY is ok: this just means that another thread
1395                  * already did the job.
1396                  */
1397                 return VM_FAULT_NOPAGE;
1398         case -ENOMEM:
1399                 return VM_FAULT_OOM;
1400         case -ENOSPC:
1401                 return VM_FAULT_SIGBUS;
1402         default:
1403                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1404                 return VM_FAULT_SIGBUS;
1405         }
1406 }
1407
1408 /**
1409  * i915_gem_release_mmap - remove physical page mappings
1410  * @obj: obj in question
1411  *
1412  * Preserve the reservation of the mmapping with the DRM core code, but
1413  * relinquish ownership of the pages back to the system.
1414  *
1415  * It is vital that we remove the page mapping if we have mapped a tiled
1416  * object through the GTT and then lose the fence register due to
1417  * resource pressure. Similarly if the object has been moved out of the
1418  * aperture, than pages mapped into userspace must be revoked. Removing the
1419  * mapping will then trigger a page fault on the next user access, allowing
1420  * fixup by i915_gem_fault().
1421  */
1422 void
1423 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1424 {
1425         if (!obj->fault_mappable)
1426                 return;
1427
1428         if (obj->base.dev->dev_mapping)
1429                 unmap_mapping_range(obj->base.dev->dev_mapping,
1430                                     (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1431                                     obj->base.size, 1);
1432
1433         obj->fault_mappable = false;
1434 }
1435
1436 uint32_t
1437 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1438 {
1439         uint32_t gtt_size;
1440
1441         if (INTEL_INFO(dev)->gen >= 4 ||
1442             tiling_mode == I915_TILING_NONE)
1443                 return size;
1444
1445         /* Previous chips need a power-of-two fence region when tiling */
1446         if (INTEL_INFO(dev)->gen == 3)
1447                 gtt_size = 1024*1024;
1448         else
1449                 gtt_size = 512*1024;
1450
1451         while (gtt_size < size)
1452                 gtt_size <<= 1;
1453
1454         return gtt_size;
1455 }
1456
1457 /**
1458  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1459  * @obj: object to check
1460  *
1461  * Return the required GTT alignment for an object, taking into account
1462  * potential fence register mapping.
1463  */
1464 uint32_t
1465 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1466                            int tiling_mode, bool fenced)
1467 {
1468         /*
1469          * Minimum alignment is 4k (GTT page size), but might be greater
1470          * if a fence register is needed for the object.
1471          */
1472         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1473             tiling_mode == I915_TILING_NONE)
1474                 return 4096;
1475
1476         /*
1477          * Previous chips need to be aligned to the size of the smallest
1478          * fence register that can contain the object.
1479          */
1480         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1481 }
1482
1483 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1484 {
1485         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1486         int ret;
1487
1488         if (obj->base.map_list.map)
1489                 return 0;
1490
1491         dev_priv->mm.shrinker_no_lock_stealing = true;
1492
1493         ret = drm_gem_create_mmap_offset(&obj->base);
1494         if (ret != -ENOSPC)
1495                 goto out;
1496
1497         /* Badly fragmented mmap space? The only way we can recover
1498          * space is by destroying unwanted objects. We can't randomly release
1499          * mmap_offsets as userspace expects them to be persistent for the
1500          * lifetime of the objects. The closest we can is to release the
1501          * offsets on purgeable objects by truncating it and marking it purged,
1502          * which prevents userspace from ever using that object again.
1503          */
1504         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1505         ret = drm_gem_create_mmap_offset(&obj->base);
1506         if (ret != -ENOSPC)
1507                 goto out;
1508
1509         i915_gem_shrink_all(dev_priv);
1510         ret = drm_gem_create_mmap_offset(&obj->base);
1511 out:
1512         dev_priv->mm.shrinker_no_lock_stealing = false;
1513
1514         return ret;
1515 }
1516
1517 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1518 {
1519         if (!obj->base.map_list.map)
1520                 return;
1521
1522         drm_gem_free_mmap_offset(&obj->base);
1523 }
1524
1525 int
1526 i915_gem_mmap_gtt(struct drm_file *file,
1527                   struct drm_device *dev,
1528                   uint32_t handle,
1529                   uint64_t *offset)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct drm_i915_gem_object *obj;
1533         int ret;
1534
1535         ret = i915_mutex_lock_interruptible(dev);
1536         if (ret)
1537                 return ret;
1538
1539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1540         if (&obj->base == NULL) {
1541                 ret = -ENOENT;
1542                 goto unlock;
1543         }
1544
1545         if (obj->base.size > dev_priv->gtt.mappable_end) {
1546                 ret = -E2BIG;
1547                 goto out;
1548         }
1549
1550         if (obj->madv != I915_MADV_WILLNEED) {
1551                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1552                 ret = -EINVAL;
1553                 goto out;
1554         }
1555
1556         ret = i915_gem_object_create_mmap_offset(obj);
1557         if (ret)
1558                 goto out;
1559
1560         *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1561
1562 out:
1563         drm_gem_object_unreference(&obj->base);
1564 unlock:
1565         mutex_unlock(&dev->struct_mutex);
1566         return ret;
1567 }
1568
1569 /**
1570  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1571  * @dev: DRM device
1572  * @data: GTT mapping ioctl data
1573  * @file: GEM object info
1574  *
1575  * Simply returns the fake offset to userspace so it can mmap it.
1576  * The mmap call will end up in drm_gem_mmap(), which will set things
1577  * up so we can get faults in the handler above.
1578  *
1579  * The fault handler will take care of binding the object into the GTT
1580  * (since it may have been evicted to make room for something), allocating
1581  * a fence register, and mapping the appropriate aperture address into
1582  * userspace.
1583  */
1584 int
1585 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1586                         struct drm_file *file)
1587 {
1588         struct drm_i915_gem_mmap_gtt *args = data;
1589
1590         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1591 }
1592
1593 /* Immediately discard the backing storage */
1594 static void
1595 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1596 {
1597         struct inode *inode;
1598
1599         i915_gem_object_free_mmap_offset(obj);
1600
1601         if (obj->base.filp == NULL)
1602                 return;
1603
1604         /* Our goal here is to return as much of the memory as
1605          * is possible back to the system as we are called from OOM.
1606          * To do this we must instruct the shmfs to drop all of its
1607          * backing pages, *now*.
1608          */
1609         inode = file_inode(obj->base.filp);
1610         shmem_truncate_range(inode, 0, (loff_t)-1);
1611
1612         obj->madv = __I915_MADV_PURGED;
1613 }
1614
1615 static inline int
1616 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1617 {
1618         return obj->madv == I915_MADV_DONTNEED;
1619 }
1620
1621 static void
1622 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1623 {
1624         struct sg_page_iter sg_iter;
1625         int ret;
1626
1627         BUG_ON(obj->madv == __I915_MADV_PURGED);
1628
1629         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1630         if (ret) {
1631                 /* In the event of a disaster, abandon all caches and
1632                  * hope for the best.
1633                  */
1634                 WARN_ON(ret != -EIO);
1635                 i915_gem_clflush_object(obj);
1636                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1637         }
1638
1639         if (i915_gem_object_needs_bit17_swizzle(obj))
1640                 i915_gem_object_save_bit_17_swizzle(obj);
1641
1642         if (obj->madv == I915_MADV_DONTNEED)
1643                 obj->dirty = 0;
1644
1645         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1646                 struct page *page = sg_page_iter_page(&sg_iter);
1647
1648                 if (obj->dirty)
1649                         set_page_dirty(page);
1650
1651                 if (obj->madv == I915_MADV_WILLNEED)
1652                         mark_page_accessed(page);
1653
1654                 page_cache_release(page);
1655         }
1656         obj->dirty = 0;
1657
1658         sg_free_table(obj->pages);
1659         kfree(obj->pages);
1660 }
1661
1662 int
1663 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1664 {
1665         const struct drm_i915_gem_object_ops *ops = obj->ops;
1666
1667         if (obj->pages == NULL)
1668                 return 0;
1669
1670         BUG_ON(obj->gtt_space);
1671
1672         if (obj->pages_pin_count)
1673                 return -EBUSY;
1674
1675         /* ->put_pages might need to allocate memory for the bit17 swizzle
1676          * array, hence protect them from being reaped by removing them from gtt
1677          * lists early. */
1678         list_del(&obj->global_list);
1679
1680         ops->put_pages(obj);
1681         obj->pages = NULL;
1682
1683         if (i915_gem_object_is_purgeable(obj))
1684                 i915_gem_object_truncate(obj);
1685
1686         return 0;
1687 }
1688
1689 static long
1690 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1691                   bool purgeable_only)
1692 {
1693         struct drm_i915_gem_object *obj, *next;
1694         long count = 0;
1695
1696         list_for_each_entry_safe(obj, next,
1697                                  &dev_priv->mm.unbound_list,
1698                                  global_list) {
1699                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1700                     i915_gem_object_put_pages(obj) == 0) {
1701                         count += obj->base.size >> PAGE_SHIFT;
1702                         if (count >= target)
1703                                 return count;
1704                 }
1705         }
1706
1707         list_for_each_entry_safe(obj, next,
1708                                  &dev_priv->mm.inactive_list,
1709                                  mm_list) {
1710                 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1711                     i915_gem_object_unbind(obj) == 0 &&
1712                     i915_gem_object_put_pages(obj) == 0) {
1713                         count += obj->base.size >> PAGE_SHIFT;
1714                         if (count >= target)
1715                                 return count;
1716                 }
1717         }
1718
1719         return count;
1720 }
1721
1722 static long
1723 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1724 {
1725         return __i915_gem_shrink(dev_priv, target, true);
1726 }
1727
1728 static void
1729 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1730 {
1731         struct drm_i915_gem_object *obj, *next;
1732
1733         i915_gem_evict_everything(dev_priv->dev);
1734
1735         list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1736                                  global_list)
1737                 i915_gem_object_put_pages(obj);
1738 }
1739
1740 static int
1741 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1742 {
1743         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1744         int page_count, i;
1745         struct address_space *mapping;
1746         struct sg_table *st;
1747         struct scatterlist *sg;
1748         struct sg_page_iter sg_iter;
1749         struct page *page;
1750         unsigned long last_pfn = 0;     /* suppress gcc warning */
1751         gfp_t gfp;
1752
1753         /* Assert that the object is not currently in any GPU domain. As it
1754          * wasn't in the GTT, there shouldn't be any way it could have been in
1755          * a GPU cache
1756          */
1757         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1758         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1759
1760         st = kmalloc(sizeof(*st), GFP_KERNEL);
1761         if (st == NULL)
1762                 return -ENOMEM;
1763
1764         page_count = obj->base.size / PAGE_SIZE;
1765         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1766                 sg_free_table(st);
1767                 kfree(st);
1768                 return -ENOMEM;
1769         }
1770
1771         /* Get the list of pages out of our struct file.  They'll be pinned
1772          * at this point until we release them.
1773          *
1774          * Fail silently without starting the shrinker
1775          */
1776         mapping = file_inode(obj->base.filp)->i_mapping;
1777         gfp = mapping_gfp_mask(mapping);
1778         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1779         gfp &= ~(__GFP_IO | __GFP_WAIT);
1780         sg = st->sgl;
1781         st->nents = 0;
1782         for (i = 0; i < page_count; i++) {
1783                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1784                 if (IS_ERR(page)) {
1785                         i915_gem_purge(dev_priv, page_count);
1786                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1787                 }
1788                 if (IS_ERR(page)) {
1789                         /* We've tried hard to allocate the memory by reaping
1790                          * our own buffer, now let the real VM do its job and
1791                          * go down in flames if truly OOM.
1792                          */
1793                         gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1794                         gfp |= __GFP_IO | __GFP_WAIT;
1795
1796                         i915_gem_shrink_all(dev_priv);
1797                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1798                         if (IS_ERR(page))
1799                                 goto err_pages;
1800
1801                         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1802                         gfp &= ~(__GFP_IO | __GFP_WAIT);
1803                 }
1804 #ifdef CONFIG_SWIOTLB
1805                 if (swiotlb_nr_tbl()) {
1806                         st->nents++;
1807                         sg_set_page(sg, page, PAGE_SIZE, 0);
1808                         sg = sg_next(sg);
1809                         continue;
1810                 }
1811 #endif
1812                 if (!i || page_to_pfn(page) != last_pfn + 1) {
1813                         if (i)
1814                                 sg = sg_next(sg);
1815                         st->nents++;
1816                         sg_set_page(sg, page, PAGE_SIZE, 0);
1817                 } else {
1818                         sg->length += PAGE_SIZE;
1819                 }
1820                 last_pfn = page_to_pfn(page);
1821         }
1822 #ifdef CONFIG_SWIOTLB
1823         if (!swiotlb_nr_tbl())
1824 #endif
1825                 sg_mark_end(sg);
1826         obj->pages = st;
1827
1828         if (i915_gem_object_needs_bit17_swizzle(obj))
1829                 i915_gem_object_do_bit_17_swizzle(obj);
1830
1831         return 0;
1832
1833 err_pages:
1834         sg_mark_end(sg);
1835         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1836                 page_cache_release(sg_page_iter_page(&sg_iter));
1837         sg_free_table(st);
1838         kfree(st);
1839         return PTR_ERR(page);
1840 }
1841
1842 /* Ensure that the associated pages are gathered from the backing storage
1843  * and pinned into our object. i915_gem_object_get_pages() may be called
1844  * multiple times before they are released by a single call to
1845  * i915_gem_object_put_pages() - once the pages are no longer referenced
1846  * either as a result of memory pressure (reaping pages under the shrinker)
1847  * or as the object is itself released.
1848  */
1849 int
1850 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1851 {
1852         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1853         const struct drm_i915_gem_object_ops *ops = obj->ops;
1854         int ret;
1855
1856         if (obj->pages)
1857                 return 0;
1858
1859         if (obj->madv != I915_MADV_WILLNEED) {
1860                 DRM_ERROR("Attempting to obtain a purgeable object\n");
1861                 return -EINVAL;
1862         }
1863
1864         BUG_ON(obj->pages_pin_count);
1865
1866         ret = ops->get_pages(obj);
1867         if (ret)
1868                 return ret;
1869
1870         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1871         return 0;
1872 }
1873
1874 void
1875 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1876                                struct intel_ring_buffer *ring)
1877 {
1878         struct drm_device *dev = obj->base.dev;
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         u32 seqno = intel_ring_get_seqno(ring);
1881
1882         BUG_ON(ring == NULL);
1883         obj->ring = ring;
1884
1885         /* Add a reference if we're newly entering the active list. */
1886         if (!obj->active) {
1887                 drm_gem_object_reference(&obj->base);
1888                 obj->active = 1;
1889         }
1890
1891         /* Move from whatever list we were on to the tail of execution. */
1892         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1893         list_move_tail(&obj->ring_list, &ring->active_list);
1894
1895         obj->last_read_seqno = seqno;
1896
1897         if (obj->fenced_gpu_access) {
1898                 obj->last_fenced_seqno = seqno;
1899
1900                 /* Bump MRU to take account of the delayed flush */
1901                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1902                         struct drm_i915_fence_reg *reg;
1903
1904                         reg = &dev_priv->fence_regs[obj->fence_reg];
1905                         list_move_tail(&reg->lru_list,
1906                                        &dev_priv->mm.fence_list);
1907                 }
1908         }
1909 }
1910
1911 static void
1912 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1913 {
1914         struct drm_device *dev = obj->base.dev;
1915         struct drm_i915_private *dev_priv = dev->dev_private;
1916
1917         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1918         BUG_ON(!obj->active);
1919
1920         list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1921
1922         list_del_init(&obj->ring_list);
1923         obj->ring = NULL;
1924
1925         obj->last_read_seqno = 0;
1926         obj->last_write_seqno = 0;
1927         obj->base.write_domain = 0;
1928
1929         obj->last_fenced_seqno = 0;
1930         obj->fenced_gpu_access = false;
1931
1932         obj->active = 0;
1933         drm_gem_object_unreference(&obj->base);
1934
1935         WARN_ON(i915_verify_lists(dev));
1936 }
1937
1938 static int
1939 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1940 {
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         struct intel_ring_buffer *ring;
1943         int ret, i, j;
1944
1945         /* Carefully retire all requests without writing to the rings */
1946         for_each_ring(ring, dev_priv, i) {
1947                 ret = intel_ring_idle(ring);
1948                 if (ret)
1949                         return ret;
1950         }
1951         i915_gem_retire_requests(dev);
1952
1953         /* Finally reset hw state */
1954         for_each_ring(ring, dev_priv, i) {
1955                 intel_ring_init_seqno(ring, seqno);
1956
1957                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1958                         ring->sync_seqno[j] = 0;
1959         }
1960
1961         return 0;
1962 }
1963
1964 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1965 {
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         int ret;
1968
1969         if (seqno == 0)
1970                 return -EINVAL;
1971
1972         /* HWS page needs to be set less than what we
1973          * will inject to ring
1974          */
1975         ret = i915_gem_init_seqno(dev, seqno - 1);
1976         if (ret)
1977                 return ret;
1978
1979         /* Carefully set the last_seqno value so that wrap
1980          * detection still works
1981          */
1982         dev_priv->next_seqno = seqno;
1983         dev_priv->last_seqno = seqno - 1;
1984         if (dev_priv->last_seqno == 0)
1985                 dev_priv->last_seqno--;
1986
1987         return 0;
1988 }
1989
1990 int
1991 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1992 {
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994
1995         /* reserve 0 for non-seqno */
1996         if (dev_priv->next_seqno == 0) {
1997                 int ret = i915_gem_init_seqno(dev, 0);
1998                 if (ret)
1999                         return ret;
2000
2001                 dev_priv->next_seqno = 1;
2002         }
2003
2004         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2005         return 0;
2006 }
2007
2008 int __i915_add_request(struct intel_ring_buffer *ring,
2009                        struct drm_file *file,
2010                        struct drm_i915_gem_object *obj,
2011                        u32 *out_seqno)
2012 {
2013         drm_i915_private_t *dev_priv = ring->dev->dev_private;
2014         struct drm_i915_gem_request *request;
2015         u32 request_ring_position, request_start;
2016         int was_empty;
2017         int ret;
2018
2019         request_start = intel_ring_get_tail(ring);
2020         /*
2021          * Emit any outstanding flushes - execbuf can fail to emit the flush
2022          * after having emitted the batchbuffer command. Hence we need to fix
2023          * things up similar to emitting the lazy request. The difference here
2024          * is that the flush _must_ happen before the next request, no matter
2025          * what.
2026          */
2027         ret = intel_ring_flush_all_caches(ring);
2028         if (ret)
2029                 return ret;
2030
2031         request = kmalloc(sizeof(*request), GFP_KERNEL);
2032         if (request == NULL)
2033                 return -ENOMEM;
2034
2035
2036         /* Record the position of the start of the request so that
2037          * should we detect the updated seqno part-way through the
2038          * GPU processing the request, we never over-estimate the
2039          * position of the head.
2040          */
2041         request_ring_position = intel_ring_get_tail(ring);
2042
2043         ret = ring->add_request(ring);
2044         if (ret) {
2045                 kfree(request);
2046                 return ret;
2047         }
2048
2049         request->seqno = intel_ring_get_seqno(ring);
2050         request->ring = ring;
2051         request->head = request_start;
2052         request->tail = request_ring_position;
2053         request->ctx = ring->last_context;
2054         request->batch_obj = obj;
2055
2056         /* Whilst this request exists, batch_obj will be on the
2057          * active_list, and so will hold the active reference. Only when this
2058          * request is retired will the the batch_obj be moved onto the
2059          * inactive_list and lose its active reference. Hence we do not need
2060          * to explicitly hold another reference here.
2061          */
2062
2063         if (request->ctx)
2064                 i915_gem_context_reference(request->ctx);
2065
2066         request->emitted_jiffies = jiffies;
2067         was_empty = list_empty(&ring->request_list);
2068         list_add_tail(&request->list, &ring->request_list);
2069         request->file_priv = NULL;
2070
2071         if (file) {
2072                 struct drm_i915_file_private *file_priv = file->driver_priv;
2073
2074                 spin_lock(&file_priv->mm.lock);
2075                 request->file_priv = file_priv;
2076                 list_add_tail(&request->client_list,
2077                               &file_priv->mm.request_list);
2078                 spin_unlock(&file_priv->mm.lock);
2079         }
2080
2081         trace_i915_gem_request_add(ring, request->seqno);
2082         ring->outstanding_lazy_request = 0;
2083
2084         if (!dev_priv->mm.suspended) {
2085                 if (i915_enable_hangcheck) {
2086                         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2087                                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2088                 }
2089                 if (was_empty) {
2090                         queue_delayed_work(dev_priv->wq,
2091                                            &dev_priv->mm.retire_work,
2092                                            round_jiffies_up_relative(HZ));
2093                         intel_mark_busy(dev_priv->dev);
2094                 }
2095         }
2096
2097         if (out_seqno)
2098                 *out_seqno = request->seqno;
2099         return 0;
2100 }
2101
2102 static inline void
2103 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2104 {
2105         struct drm_i915_file_private *file_priv = request->file_priv;
2106
2107         if (!file_priv)
2108                 return;
2109
2110         spin_lock(&file_priv->mm.lock);
2111         if (request->file_priv) {
2112                 list_del(&request->client_list);
2113                 request->file_priv = NULL;
2114         }
2115         spin_unlock(&file_priv->mm.lock);
2116 }
2117
2118 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2119 {
2120         if (acthd >= obj->gtt_offset &&
2121             acthd < obj->gtt_offset + obj->base.size)
2122                 return true;
2123
2124         return false;
2125 }
2126
2127 static bool i915_head_inside_request(const u32 acthd_unmasked,
2128                                      const u32 request_start,
2129                                      const u32 request_end)
2130 {
2131         const u32 acthd = acthd_unmasked & HEAD_ADDR;
2132
2133         if (request_start < request_end) {
2134                 if (acthd >= request_start && acthd < request_end)
2135                         return true;
2136         } else if (request_start > request_end) {
2137                 if (acthd >= request_start || acthd < request_end)
2138                         return true;
2139         }
2140
2141         return false;
2142 }
2143
2144 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2145                                 const u32 acthd, bool *inside)
2146 {
2147         /* There is a possibility that unmasked head address
2148          * pointing inside the ring, matches the batch_obj address range.
2149          * However this is extremely unlikely.
2150          */
2151
2152         if (request->batch_obj) {
2153                 if (i915_head_inside_object(acthd, request->batch_obj)) {
2154                         *inside = true;
2155                         return true;
2156                 }
2157         }
2158
2159         if (i915_head_inside_request(acthd, request->head, request->tail)) {
2160                 *inside = false;
2161                 return true;
2162         }
2163
2164         return false;
2165 }
2166
2167 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2168                                   struct drm_i915_gem_request *request,
2169                                   u32 acthd)
2170 {
2171         struct i915_ctx_hang_stats *hs = NULL;
2172         bool inside, guilty;
2173
2174         /* Innocent until proven guilty */
2175         guilty = false;
2176
2177         if (ring->hangcheck.action != wait &&
2178             i915_request_guilty(request, acthd, &inside)) {
2179                 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2180                           ring->name,
2181                           inside ? "inside" : "flushing",
2182                           request->batch_obj ?
2183                           request->batch_obj->gtt_offset : 0,
2184                           request->ctx ? request->ctx->id : 0,
2185                           acthd);
2186
2187                 guilty = true;
2188         }
2189
2190         /* If contexts are disabled or this is the default context, use
2191          * file_priv->reset_state
2192          */
2193         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2194                 hs = &request->ctx->hang_stats;
2195         else if (request->file_priv)
2196                 hs = &request->file_priv->hang_stats;
2197
2198         if (hs) {
2199                 if (guilty)
2200                         hs->batch_active++;
2201                 else
2202                         hs->batch_pending++;
2203         }
2204 }
2205
2206 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2207 {
2208         list_del(&request->list);
2209         i915_gem_request_remove_from_client(request);
2210
2211         if (request->ctx)
2212                 i915_gem_context_unreference(request->ctx);
2213
2214         kfree(request);
2215 }
2216
2217 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2218                                       struct intel_ring_buffer *ring)
2219 {
2220         u32 completed_seqno;
2221         u32 acthd;
2222
2223         acthd = intel_ring_get_active_head(ring);
2224         completed_seqno = ring->get_seqno(ring, false);
2225
2226         while (!list_empty(&ring->request_list)) {
2227                 struct drm_i915_gem_request *request;
2228
2229                 request = list_first_entry(&ring->request_list,
2230                                            struct drm_i915_gem_request,
2231                                            list);
2232
2233                 if (request->seqno > completed_seqno)
2234                         i915_set_reset_status(ring, request, acthd);
2235
2236                 i915_gem_free_request(request);
2237         }
2238
2239         while (!list_empty(&ring->active_list)) {
2240                 struct drm_i915_gem_object *obj;
2241
2242                 obj = list_first_entry(&ring->active_list,
2243                                        struct drm_i915_gem_object,
2244                                        ring_list);
2245
2246                 i915_gem_object_move_to_inactive(obj);
2247         }
2248 }
2249
2250 static void i915_gem_reset_fences(struct drm_device *dev)
2251 {
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         int i;
2254
2255         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2256                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2257
2258                 if (reg->obj)
2259                         i915_gem_object_fence_lost(reg->obj);
2260
2261                 i915_gem_write_fence(dev, i, NULL);
2262
2263                 reg->pin_count = 0;
2264                 reg->obj = NULL;
2265                 INIT_LIST_HEAD(&reg->lru_list);
2266         }
2267
2268         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2269 }
2270
2271 void i915_gem_reset(struct drm_device *dev)
2272 {
2273         struct drm_i915_private *dev_priv = dev->dev_private;
2274         struct drm_i915_gem_object *obj;
2275         struct intel_ring_buffer *ring;
2276         int i;
2277
2278         for_each_ring(ring, dev_priv, i)
2279                 i915_gem_reset_ring_lists(dev_priv, ring);
2280
2281         /* Move everything out of the GPU domains to ensure we do any
2282          * necessary invalidation upon reuse.
2283          */
2284         list_for_each_entry(obj,
2285                             &dev_priv->mm.inactive_list,
2286                             mm_list)
2287         {
2288                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2289         }
2290
2291         /* The fence registers are invalidated so clear them out */
2292         i915_gem_reset_fences(dev);
2293 }
2294
2295 /**
2296  * This function clears the request list as sequence numbers are passed.
2297  */
2298 void
2299 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2300 {
2301         uint32_t seqno;
2302
2303         if (list_empty(&ring->request_list))
2304                 return;
2305
2306         WARN_ON(i915_verify_lists(ring->dev));
2307
2308         seqno = ring->get_seqno(ring, true);
2309
2310         while (!list_empty(&ring->request_list)) {
2311                 struct drm_i915_gem_request *request;
2312
2313                 request = list_first_entry(&ring->request_list,
2314                                            struct drm_i915_gem_request,
2315                                            list);
2316
2317                 if (!i915_seqno_passed(seqno, request->seqno))
2318                         break;
2319
2320                 trace_i915_gem_request_retire(ring, request->seqno);
2321                 /* We know the GPU must have read the request to have
2322                  * sent us the seqno + interrupt, so use the position
2323                  * of tail of the request to update the last known position
2324                  * of the GPU head.
2325                  */
2326                 ring->last_retired_head = request->tail;
2327
2328                 i915_gem_free_request(request);
2329         }
2330
2331         /* Move any buffers on the active list that are no longer referenced
2332          * by the ringbuffer to the flushing/inactive lists as appropriate.
2333          */
2334         while (!list_empty(&ring->active_list)) {
2335                 struct drm_i915_gem_object *obj;
2336
2337                 obj = list_first_entry(&ring->active_list,
2338                                       struct drm_i915_gem_object,
2339                                       ring_list);
2340
2341                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2342                         break;
2343
2344                 i915_gem_object_move_to_inactive(obj);
2345         }
2346
2347         if (unlikely(ring->trace_irq_seqno &&
2348                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2349                 ring->irq_put(ring);
2350                 ring->trace_irq_seqno = 0;
2351         }
2352
2353         WARN_ON(i915_verify_lists(ring->dev));
2354 }
2355
2356 void
2357 i915_gem_retire_requests(struct drm_device *dev)
2358 {
2359         drm_i915_private_t *dev_priv = dev->dev_private;
2360         struct intel_ring_buffer *ring;
2361         int i;
2362
2363         for_each_ring(ring, dev_priv, i)
2364                 i915_gem_retire_requests_ring(ring);
2365 }
2366
2367 static void
2368 i915_gem_retire_work_handler(struct work_struct *work)
2369 {
2370         drm_i915_private_t *dev_priv;
2371         struct drm_device *dev;
2372         struct intel_ring_buffer *ring;
2373         bool idle;
2374         int i;
2375
2376         dev_priv = container_of(work, drm_i915_private_t,
2377                                 mm.retire_work.work);
2378         dev = dev_priv->dev;
2379
2380         /* Come back later if the device is busy... */
2381         if (!mutex_trylock(&dev->struct_mutex)) {
2382                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2383                                    round_jiffies_up_relative(HZ));
2384                 return;
2385         }
2386
2387         i915_gem_retire_requests(dev);
2388
2389         /* Send a periodic flush down the ring so we don't hold onto GEM
2390          * objects indefinitely.
2391          */
2392         idle = true;
2393         for_each_ring(ring, dev_priv, i) {
2394                 if (ring->gpu_caches_dirty)
2395                         i915_add_request(ring, NULL);
2396
2397                 idle &= list_empty(&ring->request_list);
2398         }
2399
2400         if (!dev_priv->mm.suspended && !idle)
2401                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2402                                    round_jiffies_up_relative(HZ));
2403         if (idle)
2404                 intel_mark_idle(dev);
2405
2406         mutex_unlock(&dev->struct_mutex);
2407 }
2408
2409 /**
2410  * Ensures that an object will eventually get non-busy by flushing any required
2411  * write domains, emitting any outstanding lazy request and retiring and
2412  * completed requests.
2413  */
2414 static int
2415 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2416 {
2417         int ret;
2418
2419         if (obj->active) {
2420                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2421                 if (ret)
2422                         return ret;
2423
2424                 i915_gem_retire_requests_ring(obj->ring);
2425         }
2426
2427         return 0;
2428 }
2429
2430 /**
2431  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2432  * @DRM_IOCTL_ARGS: standard ioctl arguments
2433  *
2434  * Returns 0 if successful, else an error is returned with the remaining time in
2435  * the timeout parameter.
2436  *  -ETIME: object is still busy after timeout
2437  *  -ERESTARTSYS: signal interrupted the wait
2438  *  -ENONENT: object doesn't exist
2439  * Also possible, but rare:
2440  *  -EAGAIN: GPU wedged
2441  *  -ENOMEM: damn
2442  *  -ENODEV: Internal IRQ fail
2443  *  -E?: The add request failed
2444  *
2445  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2446  * non-zero timeout parameter the wait ioctl will wait for the given number of
2447  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2448  * without holding struct_mutex the object may become re-busied before this
2449  * function completes. A similar but shorter * race condition exists in the busy
2450  * ioctl
2451  */
2452 int
2453 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2454 {
2455         drm_i915_private_t *dev_priv = dev->dev_private;
2456         struct drm_i915_gem_wait *args = data;
2457         struct drm_i915_gem_object *obj;
2458         struct intel_ring_buffer *ring = NULL;
2459         struct timespec timeout_stack, *timeout = NULL;
2460         unsigned reset_counter;
2461         u32 seqno = 0;
2462         int ret = 0;
2463
2464         if (args->timeout_ns >= 0) {
2465                 timeout_stack = ns_to_timespec(args->timeout_ns);
2466                 timeout = &timeout_stack;
2467         }
2468
2469         ret = i915_mutex_lock_interruptible(dev);
2470         if (ret)
2471                 return ret;
2472
2473         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2474         if (&obj->base == NULL) {
2475                 mutex_unlock(&dev->struct_mutex);
2476                 return -ENOENT;
2477         }
2478
2479         /* Need to make sure the object gets inactive eventually. */
2480         ret = i915_gem_object_flush_active(obj);
2481         if (ret)
2482                 goto out;
2483
2484         if (obj->active) {
2485                 seqno = obj->last_read_seqno;
2486                 ring = obj->ring;
2487         }
2488
2489         if (seqno == 0)
2490                  goto out;
2491
2492         /* Do this after OLR check to make sure we make forward progress polling
2493          * on this IOCTL with a 0 timeout (like busy ioctl)
2494          */
2495         if (!args->timeout_ns) {
2496                 ret = -ETIME;
2497                 goto out;
2498         }
2499
2500         drm_gem_object_unreference(&obj->base);
2501         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2502         mutex_unlock(&dev->struct_mutex);
2503
2504         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2505         if (timeout)
2506                 args->timeout_ns = timespec_to_ns(timeout);
2507         return ret;
2508
2509 out:
2510         drm_gem_object_unreference(&obj->base);
2511         mutex_unlock(&dev->struct_mutex);
2512         return ret;
2513 }
2514
2515 /**
2516  * i915_gem_object_sync - sync an object to a ring.
2517  *
2518  * @obj: object which may be in use on another ring.
2519  * @to: ring we wish to use the object on. May be NULL.
2520  *
2521  * This code is meant to abstract object synchronization with the GPU.
2522  * Calling with NULL implies synchronizing the object with the CPU
2523  * rather than a particular GPU ring.
2524  *
2525  * Returns 0 if successful, else propagates up the lower layer error.
2526  */
2527 int
2528 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2529                      struct intel_ring_buffer *to)
2530 {
2531         struct intel_ring_buffer *from = obj->ring;
2532         u32 seqno;
2533         int ret, idx;
2534
2535         if (from == NULL || to == from)
2536                 return 0;
2537
2538         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2539                 return i915_gem_object_wait_rendering(obj, false);
2540
2541         idx = intel_ring_sync_index(from, to);
2542
2543         seqno = obj->last_read_seqno;
2544         if (seqno <= from->sync_seqno[idx])
2545                 return 0;
2546
2547         ret = i915_gem_check_olr(obj->ring, seqno);
2548         if (ret)
2549                 return ret;
2550
2551         ret = to->sync_to(to, from, seqno);
2552         if (!ret)
2553                 /* We use last_read_seqno because sync_to()
2554                  * might have just caused seqno wrap under
2555                  * the radar.
2556                  */
2557                 from->sync_seqno[idx] = obj->last_read_seqno;
2558
2559         return ret;
2560 }
2561
2562 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2563 {
2564         u32 old_write_domain, old_read_domains;
2565
2566         /* Force a pagefault for domain tracking on next user access */
2567         i915_gem_release_mmap(obj);
2568
2569         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2570                 return;
2571
2572         /* Wait for any direct GTT access to complete */
2573         mb();
2574
2575         old_read_domains = obj->base.read_domains;
2576         old_write_domain = obj->base.write_domain;
2577
2578         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2579         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2580
2581         trace_i915_gem_object_change_domain(obj,
2582                                             old_read_domains,
2583                                             old_write_domain);
2584 }
2585
2586 /**
2587  * Unbinds an object from the GTT aperture.
2588  */
2589 int
2590 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2591 {
2592         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2593         int ret;
2594
2595         if (obj->gtt_space == NULL)
2596                 return 0;
2597
2598         if (obj->pin_count)
2599                 return -EBUSY;
2600
2601         BUG_ON(obj->pages == NULL);
2602
2603         ret = i915_gem_object_finish_gpu(obj);
2604         if (ret)
2605                 return ret;
2606         /* Continue on if we fail due to EIO, the GPU is hung so we
2607          * should be safe and we need to cleanup or else we might
2608          * cause memory corruption through use-after-free.
2609          */
2610
2611         i915_gem_object_finish_gtt(obj);
2612
2613         /* release the fence reg _after_ flushing */
2614         ret = i915_gem_object_put_fence(obj);
2615         if (ret)
2616                 return ret;
2617
2618         trace_i915_gem_object_unbind(obj);
2619
2620         if (obj->has_global_gtt_mapping)
2621                 i915_gem_gtt_unbind_object(obj);
2622         if (obj->has_aliasing_ppgtt_mapping) {
2623                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2624                 obj->has_aliasing_ppgtt_mapping = 0;
2625         }
2626         i915_gem_gtt_finish_object(obj);
2627         i915_gem_object_unpin_pages(obj);
2628
2629         list_del(&obj->mm_list);
2630         list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2631         /* Avoid an unnecessary call to unbind on rebind. */
2632         obj->map_and_fenceable = true;
2633
2634         drm_mm_put_block(obj->gtt_space);
2635         obj->gtt_space = NULL;
2636         obj->gtt_offset = 0;
2637
2638         return 0;
2639 }
2640
2641 int i915_gpu_idle(struct drm_device *dev)
2642 {
2643         drm_i915_private_t *dev_priv = dev->dev_private;
2644         struct intel_ring_buffer *ring;
2645         int ret, i;
2646
2647         /* Flush everything onto the inactive list. */
2648         for_each_ring(ring, dev_priv, i) {
2649                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2650                 if (ret)
2651                         return ret;
2652
2653                 ret = intel_ring_idle(ring);
2654                 if (ret)
2655                         return ret;
2656         }
2657
2658         return 0;
2659 }
2660
2661 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2662                                  struct drm_i915_gem_object *obj)
2663 {
2664         drm_i915_private_t *dev_priv = dev->dev_private;
2665         int fence_reg;
2666         int fence_pitch_shift;
2667         uint64_t val;
2668
2669         if (INTEL_INFO(dev)->gen >= 6) {
2670                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2671                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2672         } else {
2673                 fence_reg = FENCE_REG_965_0;
2674                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2675         }
2676
2677         if (obj) {
2678                 u32 size = obj->gtt_space->size;
2679
2680                 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2681                                  0xfffff000) << 32;
2682                 val |= obj->gtt_offset & 0xfffff000;
2683                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2684                 if (obj->tiling_mode == I915_TILING_Y)
2685                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2686                 val |= I965_FENCE_REG_VALID;
2687         } else
2688                 val = 0;
2689
2690         fence_reg += reg * 8;
2691         I915_WRITE64(fence_reg, val);
2692         POSTING_READ(fence_reg);
2693 }
2694
2695 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2696                                  struct drm_i915_gem_object *obj)
2697 {
2698         drm_i915_private_t *dev_priv = dev->dev_private;
2699         u32 val;
2700
2701         if (obj) {
2702                 u32 size = obj->gtt_space->size;
2703                 int pitch_val;
2704                 int tile_width;
2705
2706                 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2707                      (size & -size) != size ||
2708                      (obj->gtt_offset & (size - 1)),
2709                      "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2710                      obj->gtt_offset, obj->map_and_fenceable, size);
2711
2712                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2713                         tile_width = 128;
2714                 else
2715                         tile_width = 512;
2716
2717                 /* Note: pitch better be a power of two tile widths */
2718                 pitch_val = obj->stride / tile_width;
2719                 pitch_val = ffs(pitch_val) - 1;
2720
2721                 val = obj->gtt_offset;
2722                 if (obj->tiling_mode == I915_TILING_Y)
2723                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2724                 val |= I915_FENCE_SIZE_BITS(size);
2725                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2726                 val |= I830_FENCE_REG_VALID;
2727         } else
2728                 val = 0;
2729
2730         if (reg < 8)
2731                 reg = FENCE_REG_830_0 + reg * 4;
2732         else
2733                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2734
2735         I915_WRITE(reg, val);
2736         POSTING_READ(reg);
2737 }
2738
2739 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2740                                 struct drm_i915_gem_object *obj)
2741 {
2742         drm_i915_private_t *dev_priv = dev->dev_private;
2743         uint32_t val;
2744
2745         if (obj) {
2746                 u32 size = obj->gtt_space->size;
2747                 uint32_t pitch_val;
2748
2749                 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2750                      (size & -size) != size ||
2751                      (obj->gtt_offset & (size - 1)),
2752                      "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2753                      obj->gtt_offset, size);
2754
2755                 pitch_val = obj->stride / 128;
2756                 pitch_val = ffs(pitch_val) - 1;
2757
2758                 val = obj->gtt_offset;
2759                 if (obj->tiling_mode == I915_TILING_Y)
2760                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2761                 val |= I830_FENCE_SIZE_BITS(size);
2762                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2763                 val |= I830_FENCE_REG_VALID;
2764         } else
2765                 val = 0;
2766
2767         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2768         POSTING_READ(FENCE_REG_830_0 + reg * 4);
2769 }
2770
2771 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2772 {
2773         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2774 }
2775
2776 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2777                                  struct drm_i915_gem_object *obj)
2778 {
2779         struct drm_i915_private *dev_priv = dev->dev_private;
2780
2781         /* Ensure that all CPU reads are completed before installing a fence
2782          * and all writes before removing the fence.
2783          */
2784         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2785                 mb();
2786
2787         switch (INTEL_INFO(dev)->gen) {
2788         case 7:
2789         case 6:
2790         case 5:
2791         case 4: i965_write_fence_reg(dev, reg, obj); break;
2792         case 3: i915_write_fence_reg(dev, reg, obj); break;
2793         case 2: i830_write_fence_reg(dev, reg, obj); break;
2794         default: BUG();
2795         }
2796
2797         /* And similarly be paranoid that no direct access to this region
2798          * is reordered to before the fence is installed.
2799          */
2800         if (i915_gem_object_needs_mb(obj))
2801                 mb();
2802 }
2803
2804 static inline int fence_number(struct drm_i915_private *dev_priv,
2805                                struct drm_i915_fence_reg *fence)
2806 {
2807         return fence - dev_priv->fence_regs;
2808 }
2809
2810 struct write_fence {
2811         struct drm_device *dev;
2812         struct drm_i915_gem_object *obj;
2813         int fence;
2814 };
2815
2816 static void i915_gem_write_fence__ipi(void *data)
2817 {
2818         struct write_fence *args = data;
2819
2820         /* Required for SNB+ with LLC */
2821         wbinvd();
2822
2823         /* Required for VLV */
2824         i915_gem_write_fence(args->dev, args->fence, args->obj);
2825 }
2826
2827 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2828                                          struct drm_i915_fence_reg *fence,
2829                                          bool enable)
2830 {
2831         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2832         struct write_fence args = {
2833                 .dev = obj->base.dev,
2834                 .fence = fence_number(dev_priv, fence),
2835                 .obj = enable ? obj : NULL,
2836         };
2837
2838         /* In order to fully serialize access to the fenced region and
2839          * the update to the fence register we need to take extreme
2840          * measures on SNB+. In theory, the write to the fence register
2841          * flushes all memory transactions before, and coupled with the
2842          * mb() placed around the register write we serialise all memory
2843          * operations with respect to the changes in the tiler. Yet, on
2844          * SNB+ we need to take a step further and emit an explicit wbinvd()
2845          * on each processor in order to manually flush all memory
2846          * transactions before updating the fence register.
2847          *
2848          * However, Valleyview complicates matter. There the wbinvd is
2849          * insufficient and unlike SNB/IVB requires the serialising
2850          * register write. (Note that that register write by itself is
2851          * conversely not sufficient for SNB+.) To compromise, we do both.
2852          */
2853         if (INTEL_INFO(args.dev)->gen >= 6)
2854                 on_each_cpu(i915_gem_write_fence__ipi, &args, 1);
2855         else
2856                 i915_gem_write_fence(args.dev, args.fence, args.obj);
2857
2858         if (enable) {
2859                 obj->fence_reg = args.fence;
2860                 fence->obj = obj;
2861                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2862         } else {
2863                 obj->fence_reg = I915_FENCE_REG_NONE;
2864                 fence->obj = NULL;
2865                 list_del_init(&fence->lru_list);
2866         }
2867 }
2868
2869 static int
2870 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2871 {
2872         if (obj->last_fenced_seqno) {
2873                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2874                 if (ret)
2875                         return ret;
2876
2877                 obj->last_fenced_seqno = 0;
2878         }
2879
2880         obj->fenced_gpu_access = false;
2881         return 0;
2882 }
2883
2884 int
2885 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2886 {
2887         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2888         struct drm_i915_fence_reg *fence;
2889         int ret;
2890
2891         ret = i915_gem_object_wait_fence(obj);
2892         if (ret)
2893                 return ret;
2894
2895         if (obj->fence_reg == I915_FENCE_REG_NONE)
2896                 return 0;
2897
2898         fence = &dev_priv->fence_regs[obj->fence_reg];
2899
2900         i915_gem_object_fence_lost(obj);
2901         i915_gem_object_update_fence(obj, fence, false);
2902
2903         return 0;
2904 }
2905
2906 static struct drm_i915_fence_reg *
2907 i915_find_fence_reg(struct drm_device *dev)
2908 {
2909         struct drm_i915_private *dev_priv = dev->dev_private;
2910         struct drm_i915_fence_reg *reg, *avail;
2911         int i;
2912
2913         /* First try to find a free reg */
2914         avail = NULL;
2915         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2916                 reg = &dev_priv->fence_regs[i];
2917                 if (!reg->obj)
2918                         return reg;
2919
2920                 if (!reg->pin_count)
2921                         avail = reg;
2922         }
2923
2924         if (avail == NULL)
2925                 return NULL;
2926
2927         /* None available, try to steal one or wait for a user to finish */
2928         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2929                 if (reg->pin_count)
2930                         continue;
2931
2932                 return reg;
2933         }
2934
2935         return NULL;
2936 }
2937
2938 /**
2939  * i915_gem_object_get_fence - set up fencing for an object
2940  * @obj: object to map through a fence reg
2941  *
2942  * When mapping objects through the GTT, userspace wants to be able to write
2943  * to them without having to worry about swizzling if the object is tiled.
2944  * This function walks the fence regs looking for a free one for @obj,
2945  * stealing one if it can't find any.
2946  *
2947  * It then sets up the reg based on the object's properties: address, pitch
2948  * and tiling format.
2949  *
2950  * For an untiled surface, this removes any existing fence.
2951  */
2952 int
2953 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2954 {
2955         struct drm_device *dev = obj->base.dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         bool enable = obj->tiling_mode != I915_TILING_NONE;
2958         struct drm_i915_fence_reg *reg;
2959         int ret;
2960
2961         /* Have we updated the tiling parameters upon the object and so
2962          * will need to serialise the write to the associated fence register?
2963          */
2964         if (obj->fence_dirty) {
2965                 ret = i915_gem_object_wait_fence(obj);
2966                 if (ret)
2967                         return ret;
2968         }
2969
2970         /* Just update our place in the LRU if our fence is getting reused. */
2971         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2972                 reg = &dev_priv->fence_regs[obj->fence_reg];
2973                 if (!obj->fence_dirty) {
2974                         list_move_tail(&reg->lru_list,
2975                                        &dev_priv->mm.fence_list);
2976                         return 0;
2977                 }
2978         } else if (enable) {
2979                 reg = i915_find_fence_reg(dev);
2980                 if (reg == NULL)
2981                         return -EDEADLK;
2982
2983                 if (reg->obj) {
2984                         struct drm_i915_gem_object *old = reg->obj;
2985
2986                         ret = i915_gem_object_wait_fence(old);
2987                         if (ret)
2988                                 return ret;
2989
2990                         i915_gem_object_fence_lost(old);
2991                 }
2992         } else
2993                 return 0;
2994
2995         i915_gem_object_update_fence(obj, reg, enable);
2996         obj->fence_dirty = false;
2997
2998         return 0;
2999 }
3000
3001 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3002                                      struct drm_mm_node *gtt_space,
3003                                      unsigned long cache_level)
3004 {
3005         struct drm_mm_node *other;
3006
3007         /* On non-LLC machines we have to be careful when putting differing
3008          * types of snoopable memory together to avoid the prefetcher
3009          * crossing memory domains and dying.
3010          */
3011         if (HAS_LLC(dev))
3012                 return true;
3013
3014         if (gtt_space == NULL)
3015                 return true;
3016
3017         if (list_empty(&gtt_space->node_list))
3018                 return true;
3019
3020         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3021         if (other->allocated && !other->hole_follows && other->color != cache_level)
3022                 return false;
3023
3024         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3025         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3026                 return false;
3027
3028         return true;
3029 }
3030
3031 static void i915_gem_verify_gtt(struct drm_device *dev)
3032 {
3033 #if WATCH_GTT
3034         struct drm_i915_private *dev_priv = dev->dev_private;
3035         struct drm_i915_gem_object *obj;
3036         int err = 0;
3037
3038         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3039                 if (obj->gtt_space == NULL) {
3040                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3041                         err++;
3042                         continue;
3043                 }
3044
3045                 if (obj->cache_level != obj->gtt_space->color) {
3046                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3047                                obj->gtt_space->start,
3048                                obj->gtt_space->start + obj->gtt_space->size,
3049                                obj->cache_level,
3050                                obj->gtt_space->color);
3051                         err++;
3052                         continue;
3053                 }
3054
3055                 if (!i915_gem_valid_gtt_space(dev,
3056                                               obj->gtt_space,
3057                                               obj->cache_level)) {
3058                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3059                                obj->gtt_space->start,
3060                                obj->gtt_space->start + obj->gtt_space->size,
3061                                obj->cache_level);
3062                         err++;
3063                         continue;
3064                 }
3065         }
3066
3067         WARN_ON(err);
3068 #endif
3069 }
3070
3071 /**
3072  * Finds free space in the GTT aperture and binds the object there.
3073  */
3074 static int
3075 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3076                             unsigned alignment,
3077                             bool map_and_fenceable,
3078                             bool nonblocking)
3079 {
3080         struct drm_device *dev = obj->base.dev;
3081         drm_i915_private_t *dev_priv = dev->dev_private;
3082         struct drm_mm_node *node;
3083         u32 size, fence_size, fence_alignment, unfenced_alignment;
3084         bool mappable, fenceable;
3085         size_t gtt_max = map_and_fenceable ?
3086                 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3087         int ret;
3088
3089         fence_size = i915_gem_get_gtt_size(dev,
3090                                            obj->base.size,
3091                                            obj->tiling_mode);
3092         fence_alignment = i915_gem_get_gtt_alignment(dev,
3093                                                      obj->base.size,
3094                                                      obj->tiling_mode, true);
3095         unfenced_alignment =
3096                 i915_gem_get_gtt_alignment(dev,
3097                                                     obj->base.size,
3098                                                     obj->tiling_mode, false);
3099
3100         if (alignment == 0)
3101                 alignment = map_and_fenceable ? fence_alignment :
3102                                                 unfenced_alignment;
3103         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3104                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3105                 return -EINVAL;
3106         }
3107
3108         size = map_and_fenceable ? fence_size : obj->base.size;
3109
3110         /* If the object is bigger than the entire aperture, reject it early
3111          * before evicting everything in a vain attempt to find space.
3112          */
3113         if (obj->base.size > gtt_max) {
3114                 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3115                           obj->base.size,
3116                           map_and_fenceable ? "mappable" : "total",
3117                           gtt_max);
3118                 return -E2BIG;
3119         }
3120
3121         ret = i915_gem_object_get_pages(obj);
3122         if (ret)
3123                 return ret;
3124
3125         i915_gem_object_pin_pages(obj);
3126
3127         node = kzalloc(sizeof(*node), GFP_KERNEL);
3128         if (node == NULL) {
3129                 i915_gem_object_unpin_pages(obj);
3130                 return -ENOMEM;
3131         }
3132
3133 search_free:
3134         ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3135                                                   size, alignment,
3136                                                   obj->cache_level, 0, gtt_max);
3137         if (ret) {
3138                 ret = i915_gem_evict_something(dev, size, alignment,
3139                                                obj->cache_level,
3140                                                map_and_fenceable,
3141                                                nonblocking);
3142                 if (ret == 0)
3143                         goto search_free;
3144
3145                 i915_gem_object_unpin_pages(obj);
3146                 kfree(node);
3147                 return ret;
3148         }
3149         if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3150                 i915_gem_object_unpin_pages(obj);
3151                 drm_mm_put_block(node);
3152                 return -EINVAL;
3153         }
3154
3155         ret = i915_gem_gtt_prepare_object(obj);
3156         if (ret) {
3157                 i915_gem_object_unpin_pages(obj);
3158                 drm_mm_put_block(node);
3159                 return ret;
3160         }
3161
3162         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3163         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3164
3165         obj->gtt_space = node;
3166         obj->gtt_offset = node->start;
3167
3168         fenceable =
3169                 node->size == fence_size &&
3170                 (node->start & (fence_alignment - 1)) == 0;
3171
3172         mappable =
3173                 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3174
3175         obj->map_and_fenceable = mappable && fenceable;
3176
3177         trace_i915_gem_object_bind(obj, map_and_fenceable);
3178         i915_gem_verify_gtt(dev);
3179         return 0;
3180 }
3181
3182 void
3183 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3184 {
3185         /* If we don't have a page list set up, then we're not pinned
3186          * to GPU, and we can ignore the cache flush because it'll happen
3187          * again at bind time.
3188          */
3189         if (obj->pages == NULL)
3190                 return;
3191
3192         /*
3193          * Stolen memory is always coherent with the GPU as it is explicitly
3194          * marked as wc by the system, or the system is cache-coherent.
3195          */
3196         if (obj->stolen)
3197                 return;
3198
3199         /* If the GPU is snooping the contents of the CPU cache,
3200          * we do not need to manually clear the CPU cache lines.  However,
3201          * the caches are only snooped when the render cache is
3202          * flushed/invalidated.  As we always have to emit invalidations
3203          * and flushes when moving into and out of the RENDER domain, correct
3204          * snooping behaviour occurs naturally as the result of our domain
3205          * tracking.
3206          */
3207         if (obj->cache_level != I915_CACHE_NONE)
3208                 return;
3209
3210         trace_i915_gem_object_clflush(obj);
3211
3212         drm_clflush_sg(obj->pages);
3213 }
3214
3215 /** Flushes the GTT write domain for the object if it's dirty. */
3216 static void
3217 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3218 {
3219         uint32_t old_write_domain;
3220
3221         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3222                 return;
3223
3224         /* No actual flushing is required for the GTT write domain.  Writes
3225          * to it immediately go to main memory as far as we know, so there's
3226          * no chipset flush.  It also doesn't land in render cache.
3227          *
3228          * However, we do have to enforce the order so that all writes through
3229          * the GTT land before any writes to the device, such as updates to
3230          * the GATT itself.
3231          */
3232         wmb();
3233
3234         old_write_domain = obj->base.write_domain;
3235         obj->base.write_domain = 0;
3236
3237         trace_i915_gem_object_change_domain(obj,
3238                                             obj->base.read_domains,
3239                                             old_write_domain);
3240 }
3241
3242 /** Flushes the CPU write domain for the object if it's dirty. */
3243 static void
3244 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3245 {
3246         uint32_t old_write_domain;
3247
3248         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3249                 return;
3250
3251         i915_gem_clflush_object(obj);
3252         i915_gem_chipset_flush(obj->base.dev);
3253         old_write_domain = obj->base.write_domain;
3254         obj->base.write_domain = 0;
3255
3256         trace_i915_gem_object_change_domain(obj,
3257                                             obj->base.read_domains,
3258                                             old_write_domain);
3259 }
3260
3261 /**
3262  * Moves a single object to the GTT read, and possibly write domain.
3263  *
3264  * This function returns when the move is complete, including waiting on
3265  * flushes to occur.
3266  */
3267 int
3268 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3269 {
3270         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3271         uint32_t old_write_domain, old_read_domains;
3272         int ret;
3273
3274         /* Not valid to be called on unbound objects. */
3275         if (obj->gtt_space == NULL)
3276                 return -EINVAL;
3277
3278         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3279                 return 0;
3280
3281         ret = i915_gem_object_wait_rendering(obj, !write);
3282         if (ret)
3283                 return ret;
3284
3285         i915_gem_object_flush_cpu_write_domain(obj);
3286
3287         /* Serialise direct access to this object with the barriers for
3288          * coherent writes from the GPU, by effectively invalidating the
3289          * GTT domain upon first access.
3290          */
3291         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3292                 mb();
3293
3294         old_write_domain = obj->base.write_domain;
3295         old_read_domains = obj->base.read_domains;
3296
3297         /* It should now be out of any other write domains, and we can update
3298          * the domain values for our changes.
3299          */
3300         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3301         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3302         if (write) {
3303                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3304                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3305                 obj->dirty = 1;
3306         }
3307
3308         trace_i915_gem_object_change_domain(obj,
3309                                             old_read_domains,
3310                                             old_write_domain);
3311
3312         /* And bump the LRU for this access */
3313         if (i915_gem_object_is_inactive(obj))
3314                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3315
3316         return 0;
3317 }
3318
3319 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3320                                     enum i915_cache_level cache_level)
3321 {
3322         struct drm_device *dev = obj->base.dev;
3323         drm_i915_private_t *dev_priv = dev->dev_private;
3324         int ret;
3325
3326         if (obj->cache_level == cache_level)
3327                 return 0;
3328
3329         if (obj->pin_count) {
3330                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3331                 return -EBUSY;
3332         }
3333
3334         if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3335                 ret = i915_gem_object_unbind(obj);
3336                 if (ret)
3337                         return ret;
3338         }
3339
3340         if (obj->gtt_space) {
3341                 ret = i915_gem_object_finish_gpu(obj);
3342                 if (ret)
3343                         return ret;
3344
3345                 i915_gem_object_finish_gtt(obj);
3346
3347                 /* Before SandyBridge, you could not use tiling or fence
3348                  * registers with snooped memory, so relinquish any fences
3349                  * currently pointing to our region in the aperture.
3350                  */
3351                 if (INTEL_INFO(dev)->gen < 6) {
3352                         ret = i915_gem_object_put_fence(obj);
3353                         if (ret)
3354                                 return ret;
3355                 }
3356
3357                 if (obj->has_global_gtt_mapping)
3358                         i915_gem_gtt_bind_object(obj, cache_level);
3359                 if (obj->has_aliasing_ppgtt_mapping)
3360                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3361                                                obj, cache_level);
3362
3363                 obj->gtt_space->color = cache_level;
3364         }
3365
3366         if (cache_level == I915_CACHE_NONE) {
3367                 u32 old_read_domains, old_write_domain;
3368
3369                 /* If we're coming from LLC cached, then we haven't
3370                  * actually been tracking whether the data is in the
3371                  * CPU cache or not, since we only allow one bit set
3372                  * in obj->write_domain and have been skipping the clflushes.
3373                  * Just set it to the CPU cache for now.
3374                  */
3375                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3376                 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3377
3378                 old_read_domains = obj->base.read_domains;
3379                 old_write_domain = obj->base.write_domain;
3380
3381                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3382                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3383
3384                 trace_i915_gem_object_change_domain(obj,
3385                                                     old_read_domains,
3386                                                     old_write_domain);
3387         }
3388
3389         obj->cache_level = cache_level;
3390         i915_gem_verify_gtt(dev);
3391         return 0;
3392 }
3393
3394 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3395                                struct drm_file *file)
3396 {
3397         struct drm_i915_gem_caching *args = data;
3398         struct drm_i915_gem_object *obj;
3399         int ret;
3400
3401         ret = i915_mutex_lock_interruptible(dev);
3402         if (ret)
3403                 return ret;
3404
3405         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3406         if (&obj->base == NULL) {
3407                 ret = -ENOENT;
3408                 goto unlock;
3409         }
3410
3411         args->caching = obj->cache_level != I915_CACHE_NONE;
3412
3413         drm_gem_object_unreference(&obj->base);
3414 unlock:
3415         mutex_unlock(&dev->struct_mutex);
3416         return ret;
3417 }
3418
3419 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3420                                struct drm_file *file)
3421 {
3422         struct drm_i915_gem_caching *args = data;
3423         struct drm_i915_gem_object *obj;
3424         enum i915_cache_level level;
3425         int ret;
3426
3427         switch (args->caching) {
3428         case I915_CACHING_NONE:
3429                 level = I915_CACHE_NONE;
3430                 break;
3431         case I915_CACHING_CACHED:
3432                 level = I915_CACHE_LLC;
3433                 break;
3434         default:
3435                 return -EINVAL;
3436         }
3437
3438         ret = i915_mutex_lock_interruptible(dev);
3439         if (ret)
3440                 return ret;
3441
3442         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3443         if (&obj->base == NULL) {
3444                 ret = -ENOENT;
3445                 goto unlock;
3446         }
3447
3448         ret = i915_gem_object_set_cache_level(obj, level);
3449
3450         drm_gem_object_unreference(&obj->base);
3451 unlock:
3452         mutex_unlock(&dev->struct_mutex);
3453         return ret;
3454 }
3455
3456 /*
3457  * Prepare buffer for display plane (scanout, cursors, etc).
3458  * Can be called from an uninterruptible phase (modesetting) and allows
3459  * any flushes to be pipelined (for pageflips).
3460  */
3461 int
3462 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3463                                      u32 alignment,
3464                                      struct intel_ring_buffer *pipelined)
3465 {
3466         u32 old_read_domains, old_write_domain;
3467         int ret;
3468
3469         if (pipelined != obj->ring) {
3470                 ret = i915_gem_object_sync(obj, pipelined);
3471                 if (ret)
3472                         return ret;
3473         }
3474
3475         /* The display engine is not coherent with the LLC cache on gen6.  As
3476          * a result, we make sure that the pinning that is about to occur is
3477          * done with uncached PTEs. This is lowest common denominator for all
3478          * chipsets.
3479          *
3480          * However for gen6+, we could do better by using the GFDT bit instead
3481          * of uncaching, which would allow us to flush all the LLC-cached data
3482          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3483          */
3484         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3485         if (ret)
3486                 return ret;
3487
3488         /* As the user may map the buffer once pinned in the display plane
3489          * (e.g. libkms for the bootup splash), we have to ensure that we
3490          * always use map_and_fenceable for all scanout buffers.
3491          */
3492         ret = i915_gem_object_pin(obj, alignment, true, false);
3493         if (ret)
3494                 return ret;
3495
3496         i915_gem_object_flush_cpu_write_domain(obj);
3497
3498         old_write_domain = obj->base.write_domain;
3499         old_read_domains = obj->base.read_domains;
3500
3501         /* It should now be out of any other write domains, and we can update
3502          * the domain values for our changes.
3503          */
3504         obj->base.write_domain = 0;
3505         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3506
3507         trace_i915_gem_object_change_domain(obj,
3508                                             old_read_domains,
3509                                             old_write_domain);
3510
3511         return 0;
3512 }
3513
3514 int
3515 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3516 {
3517         int ret;
3518
3519         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3520                 return 0;
3521
3522         ret = i915_gem_object_wait_rendering(obj, false);
3523         if (ret)
3524                 return ret;
3525
3526         /* Ensure that we invalidate the GPU's caches and TLBs. */
3527         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3528         return 0;
3529 }
3530
3531 /**
3532  * Moves a single object to the CPU read, and possibly write domain.
3533  *
3534  * This function returns when the move is complete, including waiting on
3535  * flushes to occur.
3536  */
3537 int
3538 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3539 {
3540         uint32_t old_write_domain, old_read_domains;
3541         int ret;
3542
3543         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3544                 return 0;
3545
3546         ret = i915_gem_object_wait_rendering(obj, !write);
3547         if (ret)
3548                 return ret;
3549
3550         i915_gem_object_flush_gtt_write_domain(obj);
3551
3552         old_write_domain = obj->base.write_domain;
3553         old_read_domains = obj->base.read_domains;
3554
3555         /* Flush the CPU cache if it's still invalid. */
3556         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3557                 i915_gem_clflush_object(obj);
3558
3559                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3560         }
3561
3562         /* It should now be out of any other write domains, and we can update
3563          * the domain values for our changes.
3564          */
3565         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3566
3567         /* If we're writing through the CPU, then the GPU read domains will
3568          * need to be invalidated at next use.
3569          */
3570         if (write) {
3571                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3572                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3573         }
3574
3575         trace_i915_gem_object_change_domain(obj,
3576                                             old_read_domains,
3577                                             old_write_domain);
3578
3579         return 0;
3580 }
3581
3582 /* Throttle our rendering by waiting until the ring has completed our requests
3583  * emitted over 20 msec ago.
3584  *
3585  * Note that if we were to use the current jiffies each time around the loop,
3586  * we wouldn't escape the function with any frames outstanding if the time to
3587  * render a frame was over 20ms.
3588  *
3589  * This should get us reasonable parallelism between CPU and GPU but also
3590  * relatively low latency when blocking on a particular request to finish.
3591  */
3592 static int
3593 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3594 {
3595         struct drm_i915_private *dev_priv = dev->dev_private;
3596         struct drm_i915_file_private *file_priv = file->driver_priv;
3597         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3598         struct drm_i915_gem_request *request;
3599         struct intel_ring_buffer *ring = NULL;
3600         unsigned reset_counter;
3601         u32 seqno = 0;
3602         int ret;
3603
3604         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3605         if (ret)
3606                 return ret;
3607
3608         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3609         if (ret)
3610                 return ret;
3611
3612         spin_lock(&file_priv->mm.lock);
3613         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3614                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3615                         break;
3616
3617                 ring = request->ring;
3618                 seqno = request->seqno;
3619         }
3620         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3621         spin_unlock(&file_priv->mm.lock);
3622
3623         if (seqno == 0)
3624                 return 0;
3625
3626         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3627         if (ret == 0)
3628                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3629
3630         return ret;
3631 }
3632
3633 int
3634 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3635                     uint32_t alignment,
3636                     bool map_and_fenceable,
3637                     bool nonblocking)
3638 {
3639         int ret;
3640
3641         if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3642                 return -EBUSY;
3643
3644         if (obj->gtt_space != NULL) {
3645                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3646                     (map_and_fenceable && !obj->map_and_fenceable)) {
3647                         WARN(obj->pin_count,
3648                              "bo is already pinned with incorrect alignment:"
3649                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3650                              " obj->map_and_fenceable=%d\n",
3651                              obj->gtt_offset, alignment,
3652                              map_and_fenceable,
3653                              obj->map_and_fenceable);
3654                         ret = i915_gem_object_unbind(obj);
3655                         if (ret)
3656                                 return ret;
3657                 }
3658         }
3659
3660         if (obj->gtt_space == NULL) {
3661                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3662
3663                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3664                                                   map_and_fenceable,
3665                                                   nonblocking);
3666                 if (ret)
3667                         return ret;
3668
3669                 if (!dev_priv->mm.aliasing_ppgtt)
3670                         i915_gem_gtt_bind_object(obj, obj->cache_level);
3671         }
3672
3673         if (!obj->has_global_gtt_mapping && map_and_fenceable)
3674                 i915_gem_gtt_bind_object(obj, obj->cache_level);
3675
3676         obj->pin_count++;
3677         obj->pin_mappable |= map_and_fenceable;
3678
3679         return 0;
3680 }
3681
3682 void
3683 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3684 {
3685         BUG_ON(obj->pin_count == 0);
3686         BUG_ON(obj->gtt_space == NULL);
3687
3688         if (--obj->pin_count == 0)
3689                 obj->pin_mappable = false;
3690 }
3691
3692 int
3693 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3694                    struct drm_file *file)
3695 {
3696         struct drm_i915_gem_pin *args = data;
3697         struct drm_i915_gem_object *obj;
3698         int ret;
3699
3700         ret = i915_mutex_lock_interruptible(dev);
3701         if (ret)
3702                 return ret;
3703
3704         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3705         if (&obj->base == NULL) {
3706                 ret = -ENOENT;
3707                 goto unlock;
3708         }
3709
3710         if (obj->madv != I915_MADV_WILLNEED) {
3711                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3712                 ret = -EINVAL;
3713                 goto out;
3714         }
3715
3716         if (obj->pin_filp != NULL && obj->pin_filp != file) {
3717                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3718                           args->handle);
3719                 ret = -EINVAL;
3720                 goto out;
3721         }
3722
3723         if (obj->user_pin_count == 0) {
3724                 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3725                 if (ret)
3726                         goto out;
3727         }
3728
3729         obj->user_pin_count++;
3730         obj->pin_filp = file;
3731
3732         /* XXX - flush the CPU caches for pinned objects
3733          * as the X server doesn't manage domains yet
3734          */
3735         i915_gem_object_flush_cpu_write_domain(obj);
3736         args->offset = obj->gtt_offset;
3737 out:
3738         drm_gem_object_unreference(&obj->base);
3739 unlock:
3740         mutex_unlock(&dev->struct_mutex);
3741         return ret;
3742 }
3743
3744 int
3745 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3746                      struct drm_file *file)
3747 {
3748         struct drm_i915_gem_pin *args = data;
3749         struct drm_i915_gem_object *obj;
3750         int ret;
3751
3752         ret = i915_mutex_lock_interruptible(dev);
3753         if (ret)
3754                 return ret;
3755
3756         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3757         if (&obj->base == NULL) {
3758                 ret = -ENOENT;
3759                 goto unlock;
3760         }
3761
3762         if (obj->pin_filp != file) {
3763                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3764                           args->handle);
3765                 ret = -EINVAL;
3766                 goto out;
3767         }
3768         obj->user_pin_count--;
3769         if (obj->user_pin_count == 0) {
3770                 obj->pin_filp = NULL;
3771                 i915_gem_object_unpin(obj);
3772         }
3773
3774 out:
3775         drm_gem_object_unreference(&obj->base);
3776 unlock:
3777         mutex_unlock(&dev->struct_mutex);
3778         return ret;
3779 }
3780
3781 int
3782 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3783                     struct drm_file *file)
3784 {
3785         struct drm_i915_gem_busy *args = data;
3786         struct drm_i915_gem_object *obj;
3787         int ret;
3788
3789         ret = i915_mutex_lock_interruptible(dev);
3790         if (ret)
3791                 return ret;
3792
3793         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3794         if (&obj->base == NULL) {
3795                 ret = -ENOENT;
3796                 goto unlock;
3797         }
3798
3799         /* Count all active objects as busy, even if they are currently not used
3800          * by the gpu. Users of this interface expect objects to eventually
3801          * become non-busy without any further actions, therefore emit any
3802          * necessary flushes here.
3803          */
3804         ret = i915_gem_object_flush_active(obj);
3805
3806         args->busy = obj->active;
3807         if (obj->ring) {
3808                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3809                 args->busy |= intel_ring_flag(obj->ring) << 16;
3810         }
3811
3812         drm_gem_object_unreference(&obj->base);
3813 unlock:
3814         mutex_unlock(&dev->struct_mutex);
3815         return ret;
3816 }
3817
3818 int
3819 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3820                         struct drm_file *file_priv)
3821 {
3822         return i915_gem_ring_throttle(dev, file_priv);
3823 }
3824
3825 int
3826 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3827                        struct drm_file *file_priv)
3828 {
3829         struct drm_i915_gem_madvise *args = data;
3830         struct drm_i915_gem_object *obj;
3831         int ret;
3832
3833         switch (args->madv) {
3834         case I915_MADV_DONTNEED:
3835         case I915_MADV_WILLNEED:
3836             break;
3837         default:
3838             return -EINVAL;
3839         }
3840
3841         ret = i915_mutex_lock_interruptible(dev);
3842         if (ret)
3843                 return ret;
3844
3845         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3846         if (&obj->base == NULL) {
3847                 ret = -ENOENT;
3848                 goto unlock;
3849         }
3850
3851         if (obj->pin_count) {
3852                 ret = -EINVAL;
3853                 goto out;
3854         }
3855
3856         if (obj->madv != __I915_MADV_PURGED)
3857                 obj->madv = args->madv;
3858
3859         /* if the object is no longer attached, discard its backing storage */
3860         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3861                 i915_gem_object_truncate(obj);
3862
3863         args->retained = obj->madv != __I915_MADV_PURGED;
3864
3865 out:
3866         drm_gem_object_unreference(&obj->base);
3867 unlock:
3868         mutex_unlock(&dev->struct_mutex);
3869         return ret;
3870 }
3871
3872 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3873                           const struct drm_i915_gem_object_ops *ops)
3874 {
3875         INIT_LIST_HEAD(&obj->mm_list);
3876         INIT_LIST_HEAD(&obj->global_list);
3877         INIT_LIST_HEAD(&obj->ring_list);
3878         INIT_LIST_HEAD(&obj->exec_list);
3879
3880         obj->ops = ops;
3881
3882         obj->fence_reg = I915_FENCE_REG_NONE;
3883         obj->madv = I915_MADV_WILLNEED;
3884         /* Avoid an unnecessary call to unbind on the first bind. */
3885         obj->map_and_fenceable = true;
3886
3887         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3888 }
3889
3890 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3891         .get_pages = i915_gem_object_get_pages_gtt,
3892         .put_pages = i915_gem_object_put_pages_gtt,
3893 };
3894
3895 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3896                                                   size_t size)
3897 {
3898         struct drm_i915_gem_object *obj;
3899         struct address_space *mapping;
3900         gfp_t mask;
3901
3902         obj = i915_gem_object_alloc(dev);
3903         if (obj == NULL)
3904                 return NULL;
3905
3906         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3907                 i915_gem_object_free(obj);
3908                 return NULL;
3909         }
3910
3911         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3912         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3913                 /* 965gm cannot relocate objects above 4GiB. */
3914                 mask &= ~__GFP_HIGHMEM;
3915                 mask |= __GFP_DMA32;
3916         }
3917
3918         mapping = file_inode(obj->base.filp)->i_mapping;
3919         mapping_set_gfp_mask(mapping, mask);
3920
3921         i915_gem_object_init(obj, &i915_gem_object_ops);
3922
3923         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3924         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3925
3926         if (HAS_LLC(dev)) {
3927                 /* On some devices, we can have the GPU use the LLC (the CPU
3928                  * cache) for about a 10% performance improvement
3929                  * compared to uncached.  Graphics requests other than
3930                  * display scanout are coherent with the CPU in
3931                  * accessing this cache.  This means in this mode we
3932                  * don't need to clflush on the CPU side, and on the
3933                  * GPU side we only need to flush internal caches to
3934                  * get data visible to the CPU.
3935                  *
3936                  * However, we maintain the display planes as UC, and so
3937                  * need to rebind when first used as such.
3938                  */
3939                 obj->cache_level = I915_CACHE_LLC;
3940         } else
3941                 obj->cache_level = I915_CACHE_NONE;
3942
3943         return obj;
3944 }
3945
3946 int i915_gem_init_object(struct drm_gem_object *obj)
3947 {
3948         BUG();
3949
3950         return 0;
3951 }
3952
3953 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3954 {
3955         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3956         struct drm_device *dev = obj->base.dev;
3957         drm_i915_private_t *dev_priv = dev->dev_private;
3958
3959         trace_i915_gem_object_destroy(obj);
3960
3961         if (obj->phys_obj)
3962                 i915_gem_detach_phys_object(dev, obj);
3963
3964         obj->pin_count = 0;
3965         if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3966                 bool was_interruptible;
3967
3968                 was_interruptible = dev_priv->mm.interruptible;
3969                 dev_priv->mm.interruptible = false;
3970
3971                 WARN_ON(i915_gem_object_unbind(obj));
3972
3973                 dev_priv->mm.interruptible = was_interruptible;
3974         }
3975
3976         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3977          * before progressing. */
3978         if (obj->stolen)
3979                 i915_gem_object_unpin_pages(obj);
3980
3981         if (WARN_ON(obj->pages_pin_count))
3982                 obj->pages_pin_count = 0;
3983         i915_gem_object_put_pages(obj);
3984         i915_gem_object_free_mmap_offset(obj);
3985         i915_gem_object_release_stolen(obj);
3986
3987         BUG_ON(obj->pages);
3988
3989         if (obj->base.import_attach)
3990                 drm_prime_gem_destroy(&obj->base, NULL);
3991
3992         drm_gem_object_release(&obj->base);
3993         i915_gem_info_remove_obj(dev_priv, obj->base.size);
3994
3995         kfree(obj->bit_17);
3996         i915_gem_object_free(obj);
3997 }
3998
3999 int
4000 i915_gem_idle(struct drm_device *dev)
4001 {
4002         drm_i915_private_t *dev_priv = dev->dev_private;
4003         int ret;
4004
4005         mutex_lock(&dev->struct_mutex);
4006
4007         if (dev_priv->mm.suspended) {
4008                 mutex_unlock(&dev->struct_mutex);
4009                 return 0;
4010         }
4011
4012         ret = i915_gpu_idle(dev);
4013         if (ret) {
4014                 mutex_unlock(&dev->struct_mutex);
4015                 return ret;
4016         }
4017         i915_gem_retire_requests(dev);
4018
4019         /* Under UMS, be paranoid and evict. */
4020         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4021                 i915_gem_evict_everything(dev);
4022
4023         i915_gem_reset_fences(dev);
4024
4025         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4026          * We need to replace this with a semaphore, or something.
4027          * And not confound mm.suspended!
4028          */
4029         dev_priv->mm.suspended = 1;
4030         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4031
4032         i915_kernel_lost_context(dev);
4033         i915_gem_cleanup_ringbuffer(dev);
4034
4035         mutex_unlock(&dev->struct_mutex);
4036
4037         /* Cancel the retire work handler, which should be idle now. */
4038         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4039
4040         return 0;
4041 }
4042
4043 void i915_gem_l3_remap(struct drm_device *dev)
4044 {
4045         drm_i915_private_t *dev_priv = dev->dev_private;
4046         u32 misccpctl;
4047         int i;
4048
4049         if (!HAS_L3_GPU_CACHE(dev))
4050                 return;
4051
4052         if (!dev_priv->l3_parity.remap_info)
4053                 return;
4054
4055         misccpctl = I915_READ(GEN7_MISCCPCTL);
4056         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4057         POSTING_READ(GEN7_MISCCPCTL);
4058
4059         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4060                 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4061                 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4062                         DRM_DEBUG("0x%x was already programmed to %x\n",
4063                                   GEN7_L3LOG_BASE + i, remap);
4064                 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4065                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
4066                 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4067         }
4068
4069         /* Make sure all the writes land before disabling dop clock gating */
4070         POSTING_READ(GEN7_L3LOG_BASE);
4071
4072         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4073 }
4074
4075 void i915_gem_init_swizzling(struct drm_device *dev)
4076 {
4077         drm_i915_private_t *dev_priv = dev->dev_private;
4078
4079         if (INTEL_INFO(dev)->gen < 5 ||
4080             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4081                 return;
4082
4083         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4084                                  DISP_TILE_SURFACE_SWIZZLING);
4085
4086         if (IS_GEN5(dev))
4087                 return;
4088
4089         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4090         if (IS_GEN6(dev))
4091                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4092         else if (IS_GEN7(dev))
4093                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4094         else
4095                 BUG();
4096 }
4097
4098 static bool
4099 intel_enable_blt(struct drm_device *dev)
4100 {
4101         if (!HAS_BLT(dev))
4102                 return false;
4103
4104         /* The blitter was dysfunctional on early prototypes */
4105         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4106                 DRM_INFO("BLT not supported on this pre-production hardware;"
4107                          " graphics performance will be degraded.\n");
4108                 return false;
4109         }
4110
4111         return true;
4112 }
4113
4114 static int i915_gem_init_rings(struct drm_device *dev)
4115 {
4116         struct drm_i915_private *dev_priv = dev->dev_private;
4117         int ret;
4118
4119         ret = intel_init_render_ring_buffer(dev);
4120         if (ret)
4121                 return ret;
4122
4123         if (HAS_BSD(dev)) {
4124                 ret = intel_init_bsd_ring_buffer(dev);
4125                 if (ret)
4126                         goto cleanup_render_ring;
4127         }
4128
4129         if (intel_enable_blt(dev)) {
4130                 ret = intel_init_blt_ring_buffer(dev);
4131                 if (ret)
4132                         goto cleanup_bsd_ring;
4133         }
4134
4135         if (HAS_VEBOX(dev)) {
4136                 ret = intel_init_vebox_ring_buffer(dev);
4137                 if (ret)
4138                         goto cleanup_blt_ring;
4139         }
4140
4141
4142         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4143         if (ret)
4144                 goto cleanup_vebox_ring;
4145
4146         return 0;
4147
4148 cleanup_vebox_ring:
4149         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4150 cleanup_blt_ring:
4151         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4152 cleanup_bsd_ring:
4153         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4154 cleanup_render_ring:
4155         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4156
4157         return ret;
4158 }
4159
4160 int
4161 i915_gem_init_hw(struct drm_device *dev)
4162 {
4163         drm_i915_private_t *dev_priv = dev->dev_private;
4164         int ret;
4165
4166         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4167                 return -EIO;
4168
4169         if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4170                 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4171
4172         if (HAS_PCH_NOP(dev)) {
4173                 u32 temp = I915_READ(GEN7_MSG_CTL);
4174                 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4175                 I915_WRITE(GEN7_MSG_CTL, temp);
4176         }
4177
4178         i915_gem_l3_remap(dev);
4179
4180         i915_gem_init_swizzling(dev);
4181
4182         ret = i915_gem_init_rings(dev);
4183         if (ret)
4184                 return ret;
4185
4186         /*
4187          * XXX: There was some w/a described somewhere suggesting loading
4188          * contexts before PPGTT.
4189          */
4190         i915_gem_context_init(dev);
4191         if (dev_priv->mm.aliasing_ppgtt) {
4192                 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4193                 if (ret) {
4194                         i915_gem_cleanup_aliasing_ppgtt(dev);
4195                         DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4196                 }
4197         }
4198
4199         return 0;
4200 }
4201
4202 int i915_gem_init(struct drm_device *dev)
4203 {
4204         struct drm_i915_private *dev_priv = dev->dev_private;
4205         int ret;
4206
4207         mutex_lock(&dev->struct_mutex);
4208
4209         if (IS_VALLEYVIEW(dev)) {
4210                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4211                 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4212                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4213                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4214         }
4215
4216         i915_gem_init_global_gtt(dev);
4217
4218         ret = i915_gem_init_hw(dev);
4219         mutex_unlock(&dev->struct_mutex);
4220         if (ret) {
4221                 i915_gem_cleanup_aliasing_ppgtt(dev);
4222                 return ret;
4223         }
4224
4225         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4226         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4227                 dev_priv->dri1.allow_batchbuffer = 1;
4228         return 0;
4229 }
4230
4231 void
4232 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4233 {
4234         drm_i915_private_t *dev_priv = dev->dev_private;
4235         struct intel_ring_buffer *ring;
4236         int i;
4237
4238         for_each_ring(ring, dev_priv, i)
4239                 intel_cleanup_ring_buffer(ring);
4240 }
4241
4242 int
4243 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4244                        struct drm_file *file_priv)
4245 {
4246         drm_i915_private_t *dev_priv = dev->dev_private;
4247         int ret;
4248
4249         if (drm_core_check_feature(dev, DRIVER_MODESET))
4250                 return 0;
4251
4252         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4253                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4254                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4255         }
4256
4257         mutex_lock(&dev->struct_mutex);
4258         dev_priv->mm.suspended = 0;
4259
4260         ret = i915_gem_init_hw(dev);
4261         if (ret != 0) {
4262                 mutex_unlock(&dev->struct_mutex);
4263                 return ret;
4264         }
4265
4266         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4267         mutex_unlock(&dev->struct_mutex);
4268
4269         ret = drm_irq_install(dev);
4270         if (ret)
4271                 goto cleanup_ringbuffer;
4272
4273         return 0;
4274
4275 cleanup_ringbuffer:
4276         mutex_lock(&dev->struct_mutex);
4277         i915_gem_cleanup_ringbuffer(dev);
4278         dev_priv->mm.suspended = 1;
4279         mutex_unlock(&dev->struct_mutex);
4280
4281         return ret;
4282 }
4283
4284 int
4285 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4286                        struct drm_file *file_priv)
4287 {
4288         if (drm_core_check_feature(dev, DRIVER_MODESET))
4289                 return 0;
4290
4291         drm_irq_uninstall(dev);
4292         return i915_gem_idle(dev);
4293 }
4294
4295 void
4296 i915_gem_lastclose(struct drm_device *dev)
4297 {
4298         int ret;
4299
4300         if (drm_core_check_feature(dev, DRIVER_MODESET))
4301                 return;
4302
4303         ret = i915_gem_idle(dev);
4304         if (ret)
4305                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4306 }
4307
4308 static void
4309 init_ring_lists(struct intel_ring_buffer *ring)
4310 {
4311         INIT_LIST_HEAD(&ring->active_list);
4312         INIT_LIST_HEAD(&ring->request_list);
4313 }
4314
4315 void
4316 i915_gem_load(struct drm_device *dev)
4317 {
4318         drm_i915_private_t *dev_priv = dev->dev_private;
4319         int i;
4320
4321         dev_priv->slab =
4322                 kmem_cache_create("i915_gem_object",
4323                                   sizeof(struct drm_i915_gem_object), 0,
4324                                   SLAB_HWCACHE_ALIGN,
4325                                   NULL);
4326
4327         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4328         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4329         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4330         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4331         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4332         for (i = 0; i < I915_NUM_RINGS; i++)
4333                 init_ring_lists(&dev_priv->ring[i]);
4334         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4335                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4336         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4337                           i915_gem_retire_work_handler);
4338         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4339
4340         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4341         if (IS_GEN3(dev)) {
4342                 I915_WRITE(MI_ARB_STATE,
4343                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4344         }
4345
4346         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4347
4348         /* Old X drivers will take 0-2 for front, back, depth buffers */
4349         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4350                 dev_priv->fence_reg_start = 3;
4351
4352         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4353                 dev_priv->num_fence_regs = 32;
4354         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4355                 dev_priv->num_fence_regs = 16;
4356         else
4357                 dev_priv->num_fence_regs = 8;
4358
4359         /* Initialize fence registers to zero */
4360         i915_gem_reset_fences(dev);
4361
4362         i915_gem_detect_bit_6_swizzle(dev);
4363         init_waitqueue_head(&dev_priv->pending_flip_queue);
4364
4365         dev_priv->mm.interruptible = true;
4366
4367         dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4368         dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4369         register_shrinker(&dev_priv->mm.inactive_shrinker);
4370 }
4371
4372 /*
4373  * Create a physically contiguous memory object for this object
4374  * e.g. for cursor + overlay regs
4375  */
4376 static int i915_gem_init_phys_object(struct drm_device *dev,
4377                                      int id, int size, int align)
4378 {
4379         drm_i915_private_t *dev_priv = dev->dev_private;
4380         struct drm_i915_gem_phys_object *phys_obj;
4381         int ret;
4382
4383         if (dev_priv->mm.phys_objs[id - 1] || !size)
4384                 return 0;
4385
4386         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4387         if (!phys_obj)
4388                 return -ENOMEM;
4389
4390         phys_obj->id = id;
4391
4392         phys_obj->handle = drm_pci_alloc(dev, size, align);
4393         if (!phys_obj->handle) {
4394                 ret = -ENOMEM;
4395                 goto kfree_obj;
4396         }
4397 #ifdef CONFIG_X86
4398         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4399 #endif
4400
4401         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4402
4403         return 0;
4404 kfree_obj:
4405         kfree(phys_obj);
4406         return ret;
4407 }
4408
4409 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4410 {
4411         drm_i915_private_t *dev_priv = dev->dev_private;
4412         struct drm_i915_gem_phys_object *phys_obj;
4413
4414         if (!dev_priv->mm.phys_objs[id - 1])
4415                 return;
4416
4417         phys_obj = dev_priv->mm.phys_objs[id - 1];
4418         if (phys_obj->cur_obj) {
4419                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4420         }
4421
4422 #ifdef CONFIG_X86
4423         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4424 #endif
4425         drm_pci_free(dev, phys_obj->handle);
4426         kfree(phys_obj);
4427         dev_priv->mm.phys_objs[id - 1] = NULL;
4428 }
4429
4430 void i915_gem_free_all_phys_object(struct drm_device *dev)
4431 {
4432         int i;
4433
4434         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4435                 i915_gem_free_phys_object(dev, i);
4436 }
4437
4438 void i915_gem_detach_phys_object(struct drm_device *dev,
4439                                  struct drm_i915_gem_object *obj)
4440 {
4441         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4442         char *vaddr;
4443         int i;
4444         int page_count;
4445
4446         if (!obj->phys_obj)
4447                 return;
4448         vaddr = obj->phys_obj->handle->vaddr;
4449
4450         page_count = obj->base.size / PAGE_SIZE;
4451         for (i = 0; i < page_count; i++) {
4452                 struct page *page = shmem_read_mapping_page(mapping, i);
4453                 if (!IS_ERR(page)) {
4454                         char *dst = kmap_atomic(page);
4455                         memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4456                         kunmap_atomic(dst);
4457
4458                         drm_clflush_pages(&page, 1);
4459
4460                         set_page_dirty(page);
4461                         mark_page_accessed(page);
4462                         page_cache_release(page);
4463                 }
4464         }
4465         i915_gem_chipset_flush(dev);
4466
4467         obj->phys_obj->cur_obj = NULL;
4468         obj->phys_obj = NULL;
4469 }
4470
4471 int
4472 i915_gem_attach_phys_object(struct drm_device *dev,
4473                             struct drm_i915_gem_object *obj,
4474                             int id,
4475                             int align)
4476 {
4477         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4478         drm_i915_private_t *dev_priv = dev->dev_private;
4479         int ret = 0;
4480         int page_count;
4481         int i;
4482
4483         if (id > I915_MAX_PHYS_OBJECT)
4484                 return -EINVAL;
4485
4486         if (obj->phys_obj) {
4487                 if (obj->phys_obj->id == id)
4488                         return 0;
4489                 i915_gem_detach_phys_object(dev, obj);
4490         }
4491
4492         /* create a new object */
4493         if (!dev_priv->mm.phys_objs[id - 1]) {
4494                 ret = i915_gem_init_phys_object(dev, id,
4495                                                 obj->base.size, align);
4496                 if (ret) {
4497                         DRM_ERROR("failed to init phys object %d size: %zu\n",
4498                                   id, obj->base.size);
4499                         return ret;
4500                 }
4501         }
4502
4503         /* bind to the object */
4504         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4505         obj->phys_obj->cur_obj = obj;
4506
4507         page_count = obj->base.size / PAGE_SIZE;
4508
4509         for (i = 0; i < page_count; i++) {
4510                 struct page *page;
4511                 char *dst, *src;
4512
4513                 page = shmem_read_mapping_page(mapping, i);
4514                 if (IS_ERR(page))
4515                         return PTR_ERR(page);
4516
4517                 src = kmap_atomic(page);
4518                 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4519                 memcpy(dst, src, PAGE_SIZE);
4520                 kunmap_atomic(src);
4521
4522                 mark_page_accessed(page);
4523                 page_cache_release(page);
4524         }
4525
4526         return 0;
4527 }
4528
4529 static int
4530 i915_gem_phys_pwrite(struct drm_device *dev,
4531                      struct drm_i915_gem_object *obj,
4532                      struct drm_i915_gem_pwrite *args,
4533                      struct drm_file *file_priv)
4534 {
4535         void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4536         char __user *user_data = to_user_ptr(args->data_ptr);
4537
4538         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4539                 unsigned long unwritten;
4540
4541                 /* The physical object once assigned is fixed for the lifetime
4542                  * of the obj, so we can safely drop the lock and continue
4543                  * to access vaddr.
4544                  */
4545                 mutex_unlock(&dev->struct_mutex);
4546                 unwritten = copy_from_user(vaddr, user_data, args->size);
4547                 mutex_lock(&dev->struct_mutex);
4548                 if (unwritten)
4549                         return -EFAULT;
4550         }
4551
4552         i915_gem_chipset_flush(dev);
4553         return 0;
4554 }
4555
4556 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4557 {
4558         struct drm_i915_file_private *file_priv = file->driver_priv;
4559
4560         /* Clean up our request list when the client is going away, so that
4561          * later retire_requests won't dereference our soon-to-be-gone
4562          * file_priv.
4563          */
4564         spin_lock(&file_priv->mm.lock);
4565         while (!list_empty(&file_priv->mm.request_list)) {
4566                 struct drm_i915_gem_request *request;
4567
4568                 request = list_first_entry(&file_priv->mm.request_list,
4569                                            struct drm_i915_gem_request,
4570                                            client_list);
4571                 list_del(&request->client_list);
4572                 request->file_priv = NULL;
4573         }
4574         spin_unlock(&file_priv->mm.lock);
4575 }
4576
4577 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4578 {
4579         if (!mutex_is_locked(mutex))
4580                 return false;
4581
4582 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4583         return mutex->owner == task;
4584 #else
4585         /* Since UP may be pre-empted, we cannot assume that we own the lock */
4586         return false;
4587 #endif
4588 }
4589
4590 static int
4591 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4592 {
4593         struct drm_i915_private *dev_priv =
4594                 container_of(shrinker,
4595                              struct drm_i915_private,
4596                              mm.inactive_shrinker);
4597         struct drm_device *dev = dev_priv->dev;
4598         struct drm_i915_gem_object *obj;
4599         int nr_to_scan = sc->nr_to_scan;
4600         bool unlock = true;
4601         int cnt;
4602
4603         if (!mutex_trylock(&dev->struct_mutex)) {
4604                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4605                         return 0;
4606
4607                 if (dev_priv->mm.shrinker_no_lock_stealing)
4608                         return 0;
4609
4610                 unlock = false;
4611         }
4612
4613         if (nr_to_scan) {
4614                 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4615                 if (nr_to_scan > 0)
4616                         nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4617                                                         false);
4618                 if (nr_to_scan > 0)
4619                         i915_gem_shrink_all(dev_priv);
4620         }
4621
4622         cnt = 0;
4623         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4624                 if (obj->pages_pin_count == 0)
4625                         cnt += obj->base.size >> PAGE_SHIFT;
4626         list_for_each_entry(obj, &dev_priv->mm.inactive_list, global_list)
4627                 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4628                         cnt += obj->base.size >> PAGE_SHIFT;
4629
4630         if (unlock)
4631                 mutex_unlock(&dev->struct_mutex);
4632         return cnt;
4633 }