drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 int reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         int pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486                         return false;
1487         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489                         return false;
1490         } else {
1491                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492                         return false;
1493         }
1494         return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498                               enum pipe pipe, u32 val)
1499 {
1500         if ((val & SDVO_ENABLE) == 0)
1501                 return false;
1502
1503         if (HAS_PCH_CPT(dev_priv->dev)) {
1504                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505                         return false;
1506         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508                         return false;
1509         } else {
1510                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511                         return false;
1512         }
1513         return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517                               enum pipe pipe, u32 val)
1518 {
1519         if ((val & LVDS_PORT_EN) == 0)
1520                 return false;
1521
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533                               enum pipe pipe, u32 val)
1534 {
1535         if ((val & ADPA_DAC_ENABLE) == 0)
1536                 return false;
1537         if (HAS_PCH_CPT(dev_priv->dev)) {
1538                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539                         return false;
1540         } else {
1541                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542                         return false;
1543         }
1544         return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548                                    enum pipe pipe, int reg, u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              reg, pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, int reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              reg, pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         int reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /*
1717          * Apparently we need to have VGA mode enabled prior to changing
1718          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719          * dividers, even though the register value does change.
1720          */
1721         I915_WRITE(reg, 0);
1722
1723         I915_WRITE(reg, dpll);
1724
1725         /* Wait for the clocks to stabilize. */
1726         POSTING_READ(reg);
1727         udelay(150);
1728
1729         if (INTEL_INFO(dev)->gen >= 4) {
1730                 I915_WRITE(DPLL_MD(crtc->pipe),
1731                            crtc->config->dpll_hw_state.dpll_md);
1732         } else {
1733                 /* The pixel multiplier can only be updated once the
1734                  * DPLL is enabled and the clocks are stable.
1735                  *
1736                  * So write it again.
1737                  */
1738                 I915_WRITE(reg, dpll);
1739         }
1740
1741         /* We do this three times for luck */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748         I915_WRITE(reg, dpll);
1749         POSTING_READ(reg);
1750         udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754  * i9xx_disable_pll - disable a PLL
1755  * @dev_priv: i915 private structure
1756  * @pipe: pipe PLL to disable
1757  *
1758  * Disable the PLL for @pipe, making sure the pipe is off first.
1759  *
1760  * Note!  This is for pre-ILK only.
1761  */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->base.dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         enum pipe pipe = crtc->pipe;
1767
1768         /* Disable DVO 2x clock on both PLLs if necessary */
1769         if (IS_I830(dev) &&
1770             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771             !intel_num_dvo_pipes(dev)) {
1772                 I915_WRITE(DPLL(PIPE_B),
1773                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774                 I915_WRITE(DPLL(PIPE_A),
1775                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776         }
1777
1778         /* Don't disable pipe or pipe PLLs if needed */
1779         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781                 return;
1782
1783         /* Make sure the pipe isn't still relying on us */
1784         assert_pipe_disabled(dev_priv, pipe);
1785
1786         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787         POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792         u32 val;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         /*
1798          * Leave integrated clock source and reference clock enabled for pipe B.
1799          * The latter is needed for VGA hotplug / manual detection.
1800          */
1801         val = DPLL_VGA_MODE_DIS;
1802         if (pipe == PIPE_B)
1803                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804         I915_WRITE(DPLL(pipe), val);
1805         POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812         u32 val;
1813
1814         /* Make sure the pipe isn't still relying on us */
1815         assert_pipe_disabled(dev_priv, pipe);
1816
1817         /* Set PLL en = 0 */
1818         val = DPLL_SSC_REF_CLK_CHV |
1819                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820         if (pipe != PIPE_A)
1821                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822         I915_WRITE(DPLL(pipe), val);
1823         POSTING_READ(DPLL(pipe));
1824
1825         mutex_lock(&dev_priv->sb_lock);
1826
1827         /* Disable 10bit clock to display controller */
1828         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829         val &= ~DPIO_DCLKP_EN;
1830         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         int dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         if (INTEL_INFO(dev)->gen < 5)
1930                 return;
1931
1932         if (pll == NULL)
1933                 return;
1934
1935         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936                 return;
1937
1938         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939                       pll->name, pll->active, pll->on,
1940                       crtc->base.base.id);
1941
1942         if (WARN_ON(pll->active == 0)) {
1943                 assert_shared_dpll_disabled(dev_priv, pll);
1944                 return;
1945         }
1946
1947         assert_shared_dpll_enabled(dev_priv, pll);
1948         WARN_ON(!pll->on);
1949         if (--pll->active)
1950                 return;
1951
1952         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953         pll->disable(dev_priv, pll);
1954         pll->on = false;
1955
1956         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960                                            enum pipe pipe)
1961 {
1962         struct drm_device *dev = dev_priv->dev;
1963         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965         uint32_t reg, val, pipeconf_val;
1966
1967         /* PCH only available on ILK+ */
1968         BUG_ON(!HAS_PCH_SPLIT(dev));
1969
1970         /* Make sure PCH DPLL is enabled */
1971         assert_shared_dpll_enabled(dev_priv,
1972                                    intel_crtc_to_shared_dpll(intel_crtc));
1973
1974         /* FDI must be feeding us bits for PCH ports */
1975         assert_fdi_tx_enabled(dev_priv, pipe);
1976         assert_fdi_rx_enabled(dev_priv, pipe);
1977
1978         if (HAS_PCH_CPT(dev)) {
1979                 /* Workaround: Set the timing override bit before enabling the
1980                  * pch transcoder. */
1981                 reg = TRANS_CHICKEN2(pipe);
1982                 val = I915_READ(reg);
1983                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984                 I915_WRITE(reg, val);
1985         }
1986
1987         reg = PCH_TRANSCONF(pipe);
1988         val = I915_READ(reg);
1989         pipeconf_val = I915_READ(PIPECONF(pipe));
1990
1991         if (HAS_PCH_IBX(dev_priv->dev)) {
1992                 /*
1993                  * Make the BPC in transcoder be consistent with
1994                  * that in pipeconf reg. For HDMI we must use 8bpc
1995                  * here for both 8bpc and 12bpc.
1996                  */
1997                 val &= ~PIPECONF_BPC_MASK;
1998                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999                         val |= PIPECONF_8BPC;
2000                 else
2001                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2002         }
2003
2004         val &= ~TRANS_INTERLACE_MASK;
2005         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006                 if (HAS_PCH_IBX(dev_priv->dev) &&
2007                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008                         val |= TRANS_LEGACY_INTERLACED_ILK;
2009                 else
2010                         val |= TRANS_INTERLACED;
2011         else
2012                 val |= TRANS_PROGRESSIVE;
2013
2014         I915_WRITE(reg, val | TRANS_ENABLE);
2015         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2017 }
2018
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020                                       enum transcoder cpu_transcoder)
2021 {
2022         u32 val, pipeconf_val;
2023
2024         /* PCH only available on ILK+ */
2025         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2026
2027         /* FDI must be feeding us bits for PCH ports */
2028         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
2031         /* Workaround: set timing override bit. */
2032         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2035
2036         val = TRANS_ENABLE;
2037         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2038
2039         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040             PIPECONF_INTERLACED_ILK)
2041                 val |= TRANS_INTERLACED;
2042         else
2043                 val |= TRANS_PROGRESSIVE;
2044
2045         I915_WRITE(LPT_TRANSCONF, val);
2046         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047                 DRM_ERROR("Failed to enable PCH transcoder\n");
2048 }
2049
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051                                             enum pipe pipe)
2052 {
2053         struct drm_device *dev = dev_priv->dev;
2054         uint32_t reg, val;
2055
2056         /* FDI relies on the transcoder */
2057         assert_fdi_tx_disabled(dev_priv, pipe);
2058         assert_fdi_rx_disabled(dev_priv, pipe);
2059
2060         /* Ports must be off as well */
2061         assert_pch_ports_disabled(dev_priv, pipe);
2062
2063         reg = PCH_TRANSCONF(pipe);
2064         val = I915_READ(reg);
2065         val &= ~TRANS_ENABLE;
2066         I915_WRITE(reg, val);
2067         /* wait for PCH transcoder off, transcoder state */
2068         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2069                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2070
2071         if (!HAS_PCH_IBX(dev)) {
2072                 /* Workaround: Clear the timing override chicken bit again. */
2073                 reg = TRANS_CHICKEN2(pipe);
2074                 val = I915_READ(reg);
2075                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2076                 I915_WRITE(reg, val);
2077         }
2078 }
2079
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2081 {
2082         u32 val;
2083
2084         val = I915_READ(LPT_TRANSCONF);
2085         val &= ~TRANS_ENABLE;
2086         I915_WRITE(LPT_TRANSCONF, val);
2087         /* wait for PCH transcoder off, transcoder state */
2088         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089                 DRM_ERROR("Failed to disable PCH transcoder\n");
2090
2091         /* Workaround: clear timing override bit. */
2092         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2093         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2095 }
2096
2097 /**
2098  * intel_enable_pipe - enable a pipe, asserting requirements
2099  * @crtc: crtc responsible for the pipe
2100  *
2101  * Enable @crtc's pipe, making sure that various hardware specific requirements
2102  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2103  */
2104 static void intel_enable_pipe(struct intel_crtc *crtc)
2105 {
2106         struct drm_device *dev = crtc->base.dev;
2107         struct drm_i915_private *dev_priv = dev->dev_private;
2108         enum pipe pipe = crtc->pipe;
2109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2110                                                                       pipe);
2111         enum pipe pch_transcoder;
2112         int reg;
2113         u32 val;
2114
2115         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
2117         assert_planes_disabled(dev_priv, pipe);
2118         assert_cursor_disabled(dev_priv, pipe);
2119         assert_sprites_disabled(dev_priv, pipe);
2120
2121         if (HAS_PCH_LPT(dev_priv->dev))
2122                 pch_transcoder = TRANSCODER_A;
2123         else
2124                 pch_transcoder = pipe;
2125
2126         /*
2127          * A pipe without a PLL won't actually be able to drive bits from
2128          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2129          * need the check.
2130          */
2131         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2133                         assert_dsi_pll_enabled(dev_priv);
2134                 else
2135                         assert_pll_enabled(dev_priv, pipe);
2136         else {
2137                 if (crtc->config->has_pch_encoder) {
2138                         /* if driving the PCH, we need FDI enabled */
2139                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140                         assert_fdi_tx_pll_enabled(dev_priv,
2141                                                   (enum pipe) cpu_transcoder);
2142                 }
2143                 /* FIXME: assert CPU port conditions for SNB+ */
2144         }
2145
2146         reg = PIPECONF(cpu_transcoder);
2147         val = I915_READ(reg);
2148         if (val & PIPECONF_ENABLE) {
2149                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2151                 return;
2152         }
2153
2154         I915_WRITE(reg, val | PIPECONF_ENABLE);
2155         POSTING_READ(reg);
2156 }
2157
2158 /**
2159  * intel_disable_pipe - disable a pipe, asserting requirements
2160  * @crtc: crtc whose pipes is to be disabled
2161  *
2162  * Disable the pipe of @crtc, making sure that various hardware
2163  * specific requirements are met, if applicable, e.g. plane
2164  * disabled, panel fitter off, etc.
2165  *
2166  * Will wait until the pipe has shut down before returning.
2167  */
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2169 {
2170         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172         enum pipe pipe = crtc->pipe;
2173         int reg;
2174         u32 val;
2175
2176         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
2178         /*
2179          * Make sure planes won't keep trying to pump pixels to us,
2180          * or we might hang the display.
2181          */
2182         assert_planes_disabled(dev_priv, pipe);
2183         assert_cursor_disabled(dev_priv, pipe);
2184         assert_sprites_disabled(dev_priv, pipe);
2185
2186         reg = PIPECONF(cpu_transcoder);
2187         val = I915_READ(reg);
2188         if ((val & PIPECONF_ENABLE) == 0)
2189                 return;
2190
2191         /*
2192          * Double wide has implications for planes
2193          * so best keep it disabled when not needed.
2194          */
2195         if (crtc->config->double_wide)
2196                 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198         /* Don't disable pipe or pipe PLLs if needed */
2199         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201                 val &= ~PIPECONF_ENABLE;
2202
2203         I915_WRITE(reg, val);
2204         if ((val & PIPECONF_ENABLE) == 0)
2205                 intel_wait_for_pipe_off(crtc);
2206 }
2207
2208 static bool need_vtd_wa(struct drm_device *dev)
2209 {
2210 #ifdef CONFIG_INTEL_IOMMU
2211         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212                 return true;
2213 #endif
2214         return false;
2215 }
2216
2217 unsigned int
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219                   uint64_t fb_format_modifier, unsigned int plane)
2220 {
2221         unsigned int tile_height;
2222         uint32_t pixel_bytes;
2223
2224         switch (fb_format_modifier) {
2225         case DRM_FORMAT_MOD_NONE:
2226                 tile_height = 1;
2227                 break;
2228         case I915_FORMAT_MOD_X_TILED:
2229                 tile_height = IS_GEN2(dev) ? 16 : 8;
2230                 break;
2231         case I915_FORMAT_MOD_Y_TILED:
2232                 tile_height = 32;
2233                 break;
2234         case I915_FORMAT_MOD_Yf_TILED:
2235                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236                 switch (pixel_bytes) {
2237                 default:
2238                 case 1:
2239                         tile_height = 64;
2240                         break;
2241                 case 2:
2242                 case 4:
2243                         tile_height = 32;
2244                         break;
2245                 case 8:
2246                         tile_height = 16;
2247                         break;
2248                 case 16:
2249                         WARN_ONCE(1,
2250                                   "128-bit pixels are not supported for display!");
2251                         tile_height = 16;
2252                         break;
2253                 }
2254                 break;
2255         default:
2256                 MISSING_CASE(fb_format_modifier);
2257                 tile_height = 1;
2258                 break;
2259         }
2260
2261         return tile_height;
2262 }
2263
2264 unsigned int
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266                       uint32_t pixel_format, uint64_t fb_format_modifier)
2267 {
2268         return ALIGN(height, intel_tile_height(dev, pixel_format,
2269                                                fb_format_modifier, 0));
2270 }
2271
2272 static int
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274                         const struct drm_plane_state *plane_state)
2275 {
2276         struct intel_rotation_info *info = &view->rotation_info;
2277         unsigned int tile_height, tile_pitch;
2278
2279         *view = i915_ggtt_view_normal;
2280
2281         if (!plane_state)
2282                 return 0;
2283
2284         if (!intel_rotation_90_or_270(plane_state->rotation))
2285                 return 0;
2286
2287         *view = i915_ggtt_view_rotated;
2288
2289         info->height = fb->height;
2290         info->pixel_format = fb->pixel_format;
2291         info->pitch = fb->pitches[0];
2292         info->uv_offset = fb->offsets[1];
2293         info->fb_modifier = fb->modifier[0];
2294
2295         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296                                         fb->modifier[0], 0);
2297         tile_pitch = PAGE_SIZE / tile_height;
2298         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
2302         if (info->pixel_format == DRM_FORMAT_NV12) {
2303                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304                                                 fb->modifier[0], 1);
2305                 tile_pitch = PAGE_SIZE / tile_height;
2306                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308                                                      tile_height);
2309                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310                                 PAGE_SIZE;
2311         }
2312
2313         return 0;
2314 }
2315
2316 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2317 {
2318         if (INTEL_INFO(dev_priv)->gen >= 9)
2319                 return 256 * 1024;
2320         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2321                  IS_VALLEYVIEW(dev_priv))
2322                 return 128 * 1024;
2323         else if (INTEL_INFO(dev_priv)->gen >= 4)
2324                 return 4 * 1024;
2325         else
2326                 return 0;
2327 }
2328
2329 int
2330 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331                            struct drm_framebuffer *fb,
2332                            const struct drm_plane_state *plane_state,
2333                            struct intel_engine_cs *pipelined,
2334                            struct drm_i915_gem_request **pipelined_request)
2335 {
2336         struct drm_device *dev = fb->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2339         struct i915_ggtt_view view;
2340         u32 alignment;
2341         int ret;
2342
2343         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2344
2345         switch (fb->modifier[0]) {
2346         case DRM_FORMAT_MOD_NONE:
2347                 alignment = intel_linear_alignment(dev_priv);
2348                 break;
2349         case I915_FORMAT_MOD_X_TILED:
2350                 if (INTEL_INFO(dev)->gen >= 9)
2351                         alignment = 256 * 1024;
2352                 else {
2353                         /* pin() will align the object as required by fence */
2354                         alignment = 0;
2355                 }
2356                 break;
2357         case I915_FORMAT_MOD_Y_TILED:
2358         case I915_FORMAT_MOD_Yf_TILED:
2359                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360                           "Y tiling bo slipped through, driver bug!\n"))
2361                         return -EINVAL;
2362                 alignment = 1 * 1024 * 1024;
2363                 break;
2364         default:
2365                 MISSING_CASE(fb->modifier[0]);
2366                 return -EINVAL;
2367         }
2368
2369         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370         if (ret)
2371                 return ret;
2372
2373         /* Note that the w/a also requires 64 PTE of padding following the
2374          * bo. We currently fill all unused PTE with the shadow page and so
2375          * we should always have valid PTE following the scanout preventing
2376          * the VT-d warning.
2377          */
2378         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379                 alignment = 256 * 1024;
2380
2381         /*
2382          * Global gtt pte registers are special registers which actually forward
2383          * writes to a chunk of system memory. Which means that there is no risk
2384          * that the register values disappear as soon as we call
2385          * intel_runtime_pm_put(), so it is correct to wrap only the
2386          * pin/unpin/fence and not more.
2387          */
2388         intel_runtime_pm_get(dev_priv);
2389
2390         dev_priv->mm.interruptible = false;
2391         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392                                                    pipelined_request, &view);
2393         if (ret)
2394                 goto err_interruptible;
2395
2396         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397          * fence, whereas 965+ only requires a fence if using
2398          * framebuffer compression.  For simplicity, we always install
2399          * a fence as the cost is not that onerous.
2400          */
2401         ret = i915_gem_object_get_fence(obj);
2402         if (ret == -EDEADLK) {
2403                 /*
2404                  * -EDEADLK means there are no free fences
2405                  * no pending flips.
2406                  *
2407                  * This is propagated to atomic, but it uses
2408                  * -EDEADLK to force a locking recovery, so
2409                  * change the returned error to -EBUSY.
2410                  */
2411                 ret = -EBUSY;
2412                 goto err_unpin;
2413         } else if (ret)
2414                 goto err_unpin;
2415
2416         i915_gem_object_pin_fence(obj);
2417
2418         dev_priv->mm.interruptible = true;
2419         intel_runtime_pm_put(dev_priv);
2420         return 0;
2421
2422 err_unpin:
2423         i915_gem_object_unpin_from_display_plane(obj, &view);
2424 err_interruptible:
2425         dev_priv->mm.interruptible = true;
2426         intel_runtime_pm_put(dev_priv);
2427         return ret;
2428 }
2429
2430 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2431                                const struct drm_plane_state *plane_state)
2432 {
2433         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2434         struct i915_ggtt_view view;
2435         int ret;
2436
2437         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2438
2439         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2440         WARN_ONCE(ret, "Couldn't get view from plane state!");
2441
2442         i915_gem_object_unpin_fence(obj);
2443         i915_gem_object_unpin_from_display_plane(obj, &view);
2444 }
2445
2446 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2447  * is assumed to be a power-of-two. */
2448 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2449                                              int *x, int *y,
2450                                              unsigned int tiling_mode,
2451                                              unsigned int cpp,
2452                                              unsigned int pitch)
2453 {
2454         if (tiling_mode != I915_TILING_NONE) {
2455                 unsigned int tile_rows, tiles;
2456
2457                 tile_rows = *y / 8;
2458                 *y %= 8;
2459
2460                 tiles = *x / (512/cpp);
2461                 *x %= 512/cpp;
2462
2463                 return tile_rows * pitch * 8 + tiles * 4096;
2464         } else {
2465                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2466                 unsigned int offset;
2467
2468                 offset = *y * pitch + *x * cpp;
2469                 *y = (offset & alignment) / pitch;
2470                 *x = ((offset & alignment) - *y * pitch) / cpp;
2471                 return offset & ~alignment;
2472         }
2473 }
2474
2475 static int i9xx_format_to_fourcc(int format)
2476 {
2477         switch (format) {
2478         case DISPPLANE_8BPP:
2479                 return DRM_FORMAT_C8;
2480         case DISPPLANE_BGRX555:
2481                 return DRM_FORMAT_XRGB1555;
2482         case DISPPLANE_BGRX565:
2483                 return DRM_FORMAT_RGB565;
2484         default:
2485         case DISPPLANE_BGRX888:
2486                 return DRM_FORMAT_XRGB8888;
2487         case DISPPLANE_RGBX888:
2488                 return DRM_FORMAT_XBGR8888;
2489         case DISPPLANE_BGRX101010:
2490                 return DRM_FORMAT_XRGB2101010;
2491         case DISPPLANE_RGBX101010:
2492                 return DRM_FORMAT_XBGR2101010;
2493         }
2494 }
2495
2496 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2497 {
2498         switch (format) {
2499         case PLANE_CTL_FORMAT_RGB_565:
2500                 return DRM_FORMAT_RGB565;
2501         default:
2502         case PLANE_CTL_FORMAT_XRGB_8888:
2503                 if (rgb_order) {
2504                         if (alpha)
2505                                 return DRM_FORMAT_ABGR8888;
2506                         else
2507                                 return DRM_FORMAT_XBGR8888;
2508                 } else {
2509                         if (alpha)
2510                                 return DRM_FORMAT_ARGB8888;
2511                         else
2512                                 return DRM_FORMAT_XRGB8888;
2513                 }
2514         case PLANE_CTL_FORMAT_XRGB_2101010:
2515                 if (rgb_order)
2516                         return DRM_FORMAT_XBGR2101010;
2517                 else
2518                         return DRM_FORMAT_XRGB2101010;
2519         }
2520 }
2521
2522 static bool
2523 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2524                               struct intel_initial_plane_config *plane_config)
2525 {
2526         struct drm_device *dev = crtc->base.dev;
2527         struct drm_i915_private *dev_priv = to_i915(dev);
2528         struct drm_i915_gem_object *obj = NULL;
2529         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2530         struct drm_framebuffer *fb = &plane_config->fb->base;
2531         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533                                     PAGE_SIZE);
2534
2535         size_aligned -= base_aligned;
2536
2537         if (plane_config->size == 0)
2538                 return false;
2539
2540         /* If the FB is too big, just don't use it since fbdev is not very
2541          * important and we should probably use that space with FBC or other
2542          * features. */
2543         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2544                 return false;
2545
2546         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2547                                                              base_aligned,
2548                                                              base_aligned,
2549                                                              size_aligned);
2550         if (!obj)
2551                 return false;
2552
2553         obj->tiling_mode = plane_config->tiling;
2554         if (obj->tiling_mode == I915_TILING_X)
2555                 obj->stride = fb->pitches[0];
2556
2557         mode_cmd.pixel_format = fb->pixel_format;
2558         mode_cmd.width = fb->width;
2559         mode_cmd.height = fb->height;
2560         mode_cmd.pitches[0] = fb->pitches[0];
2561         mode_cmd.modifier[0] = fb->modifier[0];
2562         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2563
2564         mutex_lock(&dev->struct_mutex);
2565         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2566                                    &mode_cmd, obj)) {
2567                 DRM_DEBUG_KMS("intel fb init failed\n");
2568                 goto out_unref_obj;
2569         }
2570         mutex_unlock(&dev->struct_mutex);
2571
2572         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2573         return true;
2574
2575 out_unref_obj:
2576         drm_gem_object_unreference(&obj->base);
2577         mutex_unlock(&dev->struct_mutex);
2578         return false;
2579 }
2580
2581 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2582 static void
2583 update_state_fb(struct drm_plane *plane)
2584 {
2585         if (plane->fb == plane->state->fb)
2586                 return;
2587
2588         if (plane->state->fb)
2589                 drm_framebuffer_unreference(plane->state->fb);
2590         plane->state->fb = plane->fb;
2591         if (plane->state->fb)
2592                 drm_framebuffer_reference(plane->state->fb);
2593 }
2594
2595 static void
2596 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2597                              struct intel_initial_plane_config *plane_config)
2598 {
2599         struct drm_device *dev = intel_crtc->base.dev;
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct drm_crtc *c;
2602         struct intel_crtc *i;
2603         struct drm_i915_gem_object *obj;
2604         struct drm_plane *primary = intel_crtc->base.primary;
2605         struct drm_plane_state *plane_state = primary->state;
2606         struct drm_framebuffer *fb;
2607
2608         if (!plane_config->fb)
2609                 return;
2610
2611         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2612                 fb = &plane_config->fb->base;
2613                 goto valid_fb;
2614         }
2615
2616         kfree(plane_config->fb);
2617
2618         /*
2619          * Failed to alloc the obj, check to see if we should share
2620          * an fb with another CRTC instead
2621          */
2622         for_each_crtc(dev, c) {
2623                 i = to_intel_crtc(c);
2624
2625                 if (c == &intel_crtc->base)
2626                         continue;
2627
2628                 if (!i->active)
2629                         continue;
2630
2631                 fb = c->primary->fb;
2632                 if (!fb)
2633                         continue;
2634
2635                 obj = intel_fb_obj(fb);
2636                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2637                         drm_framebuffer_reference(fb);
2638                         goto valid_fb;
2639                 }
2640         }
2641
2642         return;
2643
2644 valid_fb:
2645         plane_state->src_x = plane_state->src_y = 0;
2646         plane_state->src_w = fb->width << 16;
2647         plane_state->src_h = fb->height << 16;
2648
2649         plane_state->crtc_x = plane_state->src_y = 0;
2650         plane_state->crtc_w = fb->width;
2651         plane_state->crtc_h = fb->height;
2652
2653         obj = intel_fb_obj(fb);
2654         if (obj->tiling_mode != I915_TILING_NONE)
2655                 dev_priv->preserve_bios_swizzle = true;
2656
2657         drm_framebuffer_reference(fb);
2658         primary->fb = primary->state->fb = fb;
2659         primary->crtc = primary->state->crtc = &intel_crtc->base;
2660         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2661         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2662 }
2663
2664 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2665                                       struct drm_framebuffer *fb,
2666                                       int x, int y)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         struct drm_plane *primary = crtc->primary;
2672         bool visible = to_intel_plane_state(primary->state)->visible;
2673         struct drm_i915_gem_object *obj;
2674         int plane = intel_crtc->plane;
2675         unsigned long linear_offset;
2676         u32 dspcntr;
2677         u32 reg = DSPCNTR(plane);
2678         int pixel_size;
2679
2680         if (!visible || !fb) {
2681                 I915_WRITE(reg, 0);
2682                 if (INTEL_INFO(dev)->gen >= 4)
2683                         I915_WRITE(DSPSURF(plane), 0);
2684                 else
2685                         I915_WRITE(DSPADDR(plane), 0);
2686                 POSTING_READ(reg);
2687                 return;
2688         }
2689
2690         obj = intel_fb_obj(fb);
2691         if (WARN_ON(obj == NULL))
2692                 return;
2693
2694         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2695
2696         dspcntr = DISPPLANE_GAMMA_ENABLE;
2697
2698         dspcntr |= DISPLAY_PLANE_ENABLE;
2699
2700         if (INTEL_INFO(dev)->gen < 4) {
2701                 if (intel_crtc->pipe == PIPE_B)
2702                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2703
2704                 /* pipesrc and dspsize control the size that is scaled from,
2705                  * which should always be the user's requested size.
2706                  */
2707                 I915_WRITE(DSPSIZE(plane),
2708                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2709                            (intel_crtc->config->pipe_src_w - 1));
2710                 I915_WRITE(DSPPOS(plane), 0);
2711         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2712                 I915_WRITE(PRIMSIZE(plane),
2713                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2714                            (intel_crtc->config->pipe_src_w - 1));
2715                 I915_WRITE(PRIMPOS(plane), 0);
2716                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2717         }
2718
2719         switch (fb->pixel_format) {
2720         case DRM_FORMAT_C8:
2721                 dspcntr |= DISPPLANE_8BPP;
2722                 break;
2723         case DRM_FORMAT_XRGB1555:
2724                 dspcntr |= DISPPLANE_BGRX555;
2725                 break;
2726         case DRM_FORMAT_RGB565:
2727                 dspcntr |= DISPPLANE_BGRX565;
2728                 break;
2729         case DRM_FORMAT_XRGB8888:
2730                 dspcntr |= DISPPLANE_BGRX888;
2731                 break;
2732         case DRM_FORMAT_XBGR8888:
2733                 dspcntr |= DISPPLANE_RGBX888;
2734                 break;
2735         case DRM_FORMAT_XRGB2101010:
2736                 dspcntr |= DISPPLANE_BGRX101010;
2737                 break;
2738         case DRM_FORMAT_XBGR2101010:
2739                 dspcntr |= DISPPLANE_RGBX101010;
2740                 break;
2741         default:
2742                 BUG();
2743         }
2744
2745         if (INTEL_INFO(dev)->gen >= 4 &&
2746             obj->tiling_mode != I915_TILING_NONE)
2747                 dspcntr |= DISPPLANE_TILED;
2748
2749         if (IS_G4X(dev))
2750                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2751
2752         linear_offset = y * fb->pitches[0] + x * pixel_size;
2753
2754         if (INTEL_INFO(dev)->gen >= 4) {
2755                 intel_crtc->dspaddr_offset =
2756                         intel_gen4_compute_page_offset(dev_priv,
2757                                                        &x, &y, obj->tiling_mode,
2758                                                        pixel_size,
2759                                                        fb->pitches[0]);
2760                 linear_offset -= intel_crtc->dspaddr_offset;
2761         } else {
2762                 intel_crtc->dspaddr_offset = linear_offset;
2763         }
2764
2765         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2766                 dspcntr |= DISPPLANE_ROTATE_180;
2767
2768                 x += (intel_crtc->config->pipe_src_w - 1);
2769                 y += (intel_crtc->config->pipe_src_h - 1);
2770
2771                 /* Finding the last pixel of the last line of the display
2772                 data and adding to linear_offset*/
2773                 linear_offset +=
2774                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2775                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2776         }
2777
2778         intel_crtc->adjusted_x = x;
2779         intel_crtc->adjusted_y = y;
2780
2781         I915_WRITE(reg, dspcntr);
2782
2783         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2784         if (INTEL_INFO(dev)->gen >= 4) {
2785                 I915_WRITE(DSPSURF(plane),
2786                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2787                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2788                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2789         } else
2790                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2791         POSTING_READ(reg);
2792 }
2793
2794 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2795                                           struct drm_framebuffer *fb,
2796                                           int x, int y)
2797 {
2798         struct drm_device *dev = crtc->dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801         struct drm_plane *primary = crtc->primary;
2802         bool visible = to_intel_plane_state(primary->state)->visible;
2803         struct drm_i915_gem_object *obj;
2804         int plane = intel_crtc->plane;
2805         unsigned long linear_offset;
2806         u32 dspcntr;
2807         u32 reg = DSPCNTR(plane);
2808         int pixel_size;
2809
2810         if (!visible || !fb) {
2811                 I915_WRITE(reg, 0);
2812                 I915_WRITE(DSPSURF(plane), 0);
2813                 POSTING_READ(reg);
2814                 return;
2815         }
2816
2817         obj = intel_fb_obj(fb);
2818         if (WARN_ON(obj == NULL))
2819                 return;
2820
2821         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2822
2823         dspcntr = DISPPLANE_GAMMA_ENABLE;
2824
2825         dspcntr |= DISPLAY_PLANE_ENABLE;
2826
2827         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2828                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2829
2830         switch (fb->pixel_format) {
2831         case DRM_FORMAT_C8:
2832                 dspcntr |= DISPPLANE_8BPP;
2833                 break;
2834         case DRM_FORMAT_RGB565:
2835                 dspcntr |= DISPPLANE_BGRX565;
2836                 break;
2837         case DRM_FORMAT_XRGB8888:
2838                 dspcntr |= DISPPLANE_BGRX888;
2839                 break;
2840         case DRM_FORMAT_XBGR8888:
2841                 dspcntr |= DISPPLANE_RGBX888;
2842                 break;
2843         case DRM_FORMAT_XRGB2101010:
2844                 dspcntr |= DISPPLANE_BGRX101010;
2845                 break;
2846         case DRM_FORMAT_XBGR2101010:
2847                 dspcntr |= DISPPLANE_RGBX101010;
2848                 break;
2849         default:
2850                 BUG();
2851         }
2852
2853         if (obj->tiling_mode != I915_TILING_NONE)
2854                 dspcntr |= DISPPLANE_TILED;
2855
2856         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2857                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2858
2859         linear_offset = y * fb->pitches[0] + x * pixel_size;
2860         intel_crtc->dspaddr_offset =
2861                 intel_gen4_compute_page_offset(dev_priv,
2862                                                &x, &y, obj->tiling_mode,
2863                                                pixel_size,
2864                                                fb->pitches[0]);
2865         linear_offset -= intel_crtc->dspaddr_offset;
2866         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2867                 dspcntr |= DISPPLANE_ROTATE_180;
2868
2869                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2870                         x += (intel_crtc->config->pipe_src_w - 1);
2871                         y += (intel_crtc->config->pipe_src_h - 1);
2872
2873                         /* Finding the last pixel of the last line of the display
2874                         data and adding to linear_offset*/
2875                         linear_offset +=
2876                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2877                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2878                 }
2879         }
2880
2881         intel_crtc->adjusted_x = x;
2882         intel_crtc->adjusted_y = y;
2883
2884         I915_WRITE(reg, dspcntr);
2885
2886         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2887         I915_WRITE(DSPSURF(plane),
2888                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2889         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2890                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2891         } else {
2892                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2893                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2894         }
2895         POSTING_READ(reg);
2896 }
2897
2898 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2899                               uint32_t pixel_format)
2900 {
2901         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2902
2903         /*
2904          * The stride is either expressed as a multiple of 64 bytes
2905          * chunks for linear buffers or in number of tiles for tiled
2906          * buffers.
2907          */
2908         switch (fb_modifier) {
2909         case DRM_FORMAT_MOD_NONE:
2910                 return 64;
2911         case I915_FORMAT_MOD_X_TILED:
2912                 if (INTEL_INFO(dev)->gen == 2)
2913                         return 128;
2914                 return 512;
2915         case I915_FORMAT_MOD_Y_TILED:
2916                 /* No need to check for old gens and Y tiling since this is
2917                  * about the display engine and those will be blocked before
2918                  * we get here.
2919                  */
2920                 return 128;
2921         case I915_FORMAT_MOD_Yf_TILED:
2922                 if (bits_per_pixel == 8)
2923                         return 64;
2924                 else
2925                         return 128;
2926         default:
2927                 MISSING_CASE(fb_modifier);
2928                 return 64;
2929         }
2930 }
2931
2932 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2933                                      struct drm_i915_gem_object *obj,
2934                                      unsigned int plane)
2935 {
2936         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2937         struct i915_vma *vma;
2938         unsigned char *offset;
2939
2940         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2941                 view = &i915_ggtt_view_rotated;
2942
2943         vma = i915_gem_obj_to_ggtt_view(obj, view);
2944         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2945                 view->type))
2946                 return -1;
2947
2948         offset = (unsigned char *)vma->node.start;
2949
2950         if (plane == 1) {
2951                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2952                           PAGE_SIZE;
2953         }
2954
2955         return (unsigned long)offset;
2956 }
2957
2958 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2959 {
2960         struct drm_device *dev = intel_crtc->base.dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962
2963         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2964         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2965         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2966 }
2967
2968 /*
2969  * This function detaches (aka. unbinds) unused scalers in hardware
2970  */
2971 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2972 {
2973         struct intel_crtc_scaler_state *scaler_state;
2974         int i;
2975
2976         scaler_state = &intel_crtc->config->scaler_state;
2977
2978         /* loop through and disable scalers that aren't in use */
2979         for (i = 0; i < intel_crtc->num_scalers; i++) {
2980                 if (!scaler_state->scalers[i].in_use)
2981                         skl_detach_scaler(intel_crtc, i);
2982         }
2983 }
2984
2985 u32 skl_plane_ctl_format(uint32_t pixel_format)
2986 {
2987         switch (pixel_format) {
2988         case DRM_FORMAT_C8:
2989                 return PLANE_CTL_FORMAT_INDEXED;
2990         case DRM_FORMAT_RGB565:
2991                 return PLANE_CTL_FORMAT_RGB_565;
2992         case DRM_FORMAT_XBGR8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2994         case DRM_FORMAT_XRGB8888:
2995                 return PLANE_CTL_FORMAT_XRGB_8888;
2996         /*
2997          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2998          * to be already pre-multiplied. We need to add a knob (or a different
2999          * DRM_FORMAT) for user-space to configure that.
3000          */
3001         case DRM_FORMAT_ABGR8888:
3002                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3003                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3004         case DRM_FORMAT_ARGB8888:
3005                 return PLANE_CTL_FORMAT_XRGB_8888 |
3006                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3007         case DRM_FORMAT_XRGB2101010:
3008                 return PLANE_CTL_FORMAT_XRGB_2101010;
3009         case DRM_FORMAT_XBGR2101010:
3010                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3011         case DRM_FORMAT_YUYV:
3012                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3013         case DRM_FORMAT_YVYU:
3014                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3015         case DRM_FORMAT_UYVY:
3016                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3017         case DRM_FORMAT_VYUY:
3018                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3019         default:
3020                 MISSING_CASE(pixel_format);
3021         }
3022
3023         return 0;
3024 }
3025
3026 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3027 {
3028         switch (fb_modifier) {
3029         case DRM_FORMAT_MOD_NONE:
3030                 break;
3031         case I915_FORMAT_MOD_X_TILED:
3032                 return PLANE_CTL_TILED_X;
3033         case I915_FORMAT_MOD_Y_TILED:
3034                 return PLANE_CTL_TILED_Y;
3035         case I915_FORMAT_MOD_Yf_TILED:
3036                 return PLANE_CTL_TILED_YF;
3037         default:
3038                 MISSING_CASE(fb_modifier);
3039         }
3040
3041         return 0;
3042 }
3043
3044 u32 skl_plane_ctl_rotation(unsigned int rotation)
3045 {
3046         switch (rotation) {
3047         case BIT(DRM_ROTATE_0):
3048                 break;
3049         /*
3050          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3051          * while i915 HW rotation is clockwise, thats why this swapping.
3052          */
3053         case BIT(DRM_ROTATE_90):
3054                 return PLANE_CTL_ROTATE_270;
3055         case BIT(DRM_ROTATE_180):
3056                 return PLANE_CTL_ROTATE_180;
3057         case BIT(DRM_ROTATE_270):
3058                 return PLANE_CTL_ROTATE_90;
3059         default:
3060                 MISSING_CASE(rotation);
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3067                                          struct drm_framebuffer *fb,
3068                                          int x, int y)
3069 {
3070         struct drm_device *dev = crtc->dev;
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073         struct drm_plane *plane = crtc->primary;
3074         bool visible = to_intel_plane_state(plane->state)->visible;
3075         struct drm_i915_gem_object *obj;
3076         int pipe = intel_crtc->pipe;
3077         u32 plane_ctl, stride_div, stride;
3078         u32 tile_height, plane_offset, plane_size;
3079         unsigned int rotation;
3080         int x_offset, y_offset;
3081         unsigned long surf_addr;
3082         struct intel_crtc_state *crtc_state = intel_crtc->config;
3083         struct intel_plane_state *plane_state;
3084         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3085         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3086         int scaler_id = -1;
3087
3088         plane_state = to_intel_plane_state(plane->state);
3089
3090         if (!visible || !fb) {
3091                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3092                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3093                 POSTING_READ(PLANE_CTL(pipe, 0));
3094                 return;
3095         }
3096
3097         plane_ctl = PLANE_CTL_ENABLE |
3098                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3099                     PLANE_CTL_PIPE_CSC_ENABLE;
3100
3101         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3102         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3103         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3104
3105         rotation = plane->state->rotation;
3106         plane_ctl |= skl_plane_ctl_rotation(rotation);
3107
3108         obj = intel_fb_obj(fb);
3109         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3110                                                fb->pixel_format);
3111         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3112
3113         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3114
3115         scaler_id = plane_state->scaler_id;
3116         src_x = plane_state->src.x1 >> 16;
3117         src_y = plane_state->src.y1 >> 16;
3118         src_w = drm_rect_width(&plane_state->src) >> 16;
3119         src_h = drm_rect_height(&plane_state->src) >> 16;
3120         dst_x = plane_state->dst.x1;
3121         dst_y = plane_state->dst.y1;
3122         dst_w = drm_rect_width(&plane_state->dst);
3123         dst_h = drm_rect_height(&plane_state->dst);
3124
3125         WARN_ON(x != src_x || y != src_y);
3126
3127         if (intel_rotation_90_or_270(rotation)) {
3128                 /* stride = Surface height in tiles */
3129                 tile_height = intel_tile_height(dev, fb->pixel_format,
3130                                                 fb->modifier[0], 0);
3131                 stride = DIV_ROUND_UP(fb->height, tile_height);
3132                 x_offset = stride * tile_height - y - src_h;
3133                 y_offset = x;
3134                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3135         } else {
3136                 stride = fb->pitches[0] / stride_div;
3137                 x_offset = x;
3138                 y_offset = y;
3139                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3140         }
3141         plane_offset = y_offset << 16 | x_offset;
3142
3143         intel_crtc->adjusted_x = x_offset;
3144         intel_crtc->adjusted_y = y_offset;
3145
3146         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3147         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3148         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3149         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3150
3151         if (scaler_id >= 0) {
3152                 uint32_t ps_ctrl = 0;
3153
3154                 WARN_ON(!dst_w || !dst_h);
3155                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3156                         crtc_state->scaler_state.scalers[scaler_id].mode;
3157                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3158                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3159                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3160                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3161                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3162         } else {
3163                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3164         }
3165
3166         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3167
3168         POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174                            int x, int y, enum mode_set_atomic state)
3175 {
3176         struct drm_device *dev = crtc->dev;
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178
3179         if (dev_priv->fbc.disable_fbc)
3180                 dev_priv->fbc.disable_fbc(dev_priv);
3181
3182         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3183
3184         return 0;
3185 }
3186
3187 static void intel_complete_page_flips(struct drm_device *dev)
3188 {
3189         struct drm_crtc *crtc;
3190
3191         for_each_crtc(dev, crtc) {
3192                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193                 enum plane plane = intel_crtc->plane;
3194
3195                 intel_prepare_page_flip(dev, plane);
3196                 intel_finish_page_flip_plane(dev, plane);
3197         }
3198 }
3199
3200 static void intel_update_primary_planes(struct drm_device *dev)
3201 {
3202         struct drm_crtc *crtc;
3203
3204         for_each_crtc(dev, crtc) {
3205                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3206                 struct intel_plane_state *plane_state;
3207
3208                 drm_modeset_lock_crtc(crtc, &plane->base);
3209
3210                 plane_state = to_intel_plane_state(plane->base.state);
3211
3212                 if (plane_state->base.fb)
3213                         plane->commit_plane(&plane->base, plane_state);
3214
3215                 drm_modeset_unlock_crtc(crtc);
3216         }
3217 }
3218
3219 void intel_prepare_reset(struct drm_device *dev)
3220 {
3221         /* no reset support for gen2 */
3222         if (IS_GEN2(dev))
3223                 return;
3224
3225         /* reset doesn't touch the display */
3226         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3227                 return;
3228
3229         drm_modeset_lock_all(dev);
3230         /*
3231          * Disabling the crtcs gracefully seems nicer. Also the
3232          * g33 docs say we should at least disable all the planes.
3233          */
3234         intel_display_suspend(dev);
3235 }
3236
3237 void intel_finish_reset(struct drm_device *dev)
3238 {
3239         struct drm_i915_private *dev_priv = to_i915(dev);
3240
3241         /*
3242          * Flips in the rings will be nuked by the reset,
3243          * so complete all pending flips so that user space
3244          * will get its events and not get stuck.
3245          */
3246         intel_complete_page_flips(dev);
3247
3248         /* no reset support for gen2 */
3249         if (IS_GEN2(dev))
3250                 return;
3251
3252         /* reset doesn't touch the display */
3253         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3254                 /*
3255                  * Flips in the rings have been nuked by the reset,
3256                  * so update the base address of all primary
3257                  * planes to the the last fb to make sure we're
3258                  * showing the correct fb after a reset.
3259                  *
3260                  * FIXME: Atomic will make this obsolete since we won't schedule
3261                  * CS-based flips (which might get lost in gpu resets) any more.
3262                  */
3263                 intel_update_primary_planes(dev);
3264                 return;
3265         }
3266
3267         /*
3268          * The display has been reset as well,
3269          * so need a full re-initialization.
3270          */
3271         intel_runtime_pm_disable_interrupts(dev_priv);
3272         intel_runtime_pm_enable_interrupts(dev_priv);
3273
3274         intel_modeset_init_hw(dev);
3275
3276         spin_lock_irq(&dev_priv->irq_lock);
3277         if (dev_priv->display.hpd_irq_setup)
3278                 dev_priv->display.hpd_irq_setup(dev);
3279         spin_unlock_irq(&dev_priv->irq_lock);
3280
3281         intel_display_resume(dev);
3282
3283         intel_hpd_init(dev_priv);
3284
3285         drm_modeset_unlock_all(dev);
3286 }
3287
3288 static void
3289 intel_finish_fb(struct drm_framebuffer *old_fb)
3290 {
3291         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3292         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3293         bool was_interruptible = dev_priv->mm.interruptible;
3294         int ret;
3295
3296         /* Big Hammer, we also need to ensure that any pending
3297          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3298          * current scanout is retired before unpinning the old
3299          * framebuffer. Note that we rely on userspace rendering
3300          * into the buffer attached to the pipe they are waiting
3301          * on. If not, userspace generates a GPU hang with IPEHR
3302          * point to the MI_WAIT_FOR_EVENT.
3303          *
3304          * This should only fail upon a hung GPU, in which case we
3305          * can safely continue.
3306          */
3307         dev_priv->mm.interruptible = false;
3308         ret = i915_gem_object_wait_rendering(obj, true);
3309         dev_priv->mm.interruptible = was_interruptible;
3310
3311         WARN_ON(ret);
3312 }
3313
3314 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3315 {
3316         struct drm_device *dev = crtc->dev;
3317         struct drm_i915_private *dev_priv = dev->dev_private;
3318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3319         bool pending;
3320
3321         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3322             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3323                 return false;
3324
3325         spin_lock_irq(&dev->event_lock);
3326         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3327         spin_unlock_irq(&dev->event_lock);
3328
3329         return pending;
3330 }
3331
3332 static void intel_update_pipe_config(struct intel_crtc *crtc,
3333                                      struct intel_crtc_state *old_crtc_state)
3334 {
3335         struct drm_device *dev = crtc->base.dev;
3336         struct drm_i915_private *dev_priv = dev->dev_private;
3337         struct intel_crtc_state *pipe_config =
3338                 to_intel_crtc_state(crtc->base.state);
3339
3340         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3341         crtc->base.mode = crtc->base.state->mode;
3342
3343         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3344                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3345                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3346
3347         if (HAS_DDI(dev))
3348                 intel_set_pipe_csc(&crtc->base);
3349
3350         /*
3351          * Update pipe size and adjust fitter if needed: the reason for this is
3352          * that in compute_mode_changes we check the native mode (not the pfit
3353          * mode) to see if we can flip rather than do a full mode set. In the
3354          * fastboot case, we'll flip, but if we don't update the pipesrc and
3355          * pfit state, we'll end up with a big fb scanned out into the wrong
3356          * sized surface.
3357          */
3358
3359         I915_WRITE(PIPESRC(crtc->pipe),
3360                    ((pipe_config->pipe_src_w - 1) << 16) |
3361                    (pipe_config->pipe_src_h - 1));
3362
3363         /* on skylake this is done by detaching scalers */
3364         if (INTEL_INFO(dev)->gen >= 9) {
3365                 skl_detach_scalers(crtc);
3366
3367                 if (pipe_config->pch_pfit.enabled)
3368                         skylake_pfit_enable(crtc);
3369         } else if (HAS_PCH_SPLIT(dev)) {
3370                 if (pipe_config->pch_pfit.enabled)
3371                         ironlake_pfit_enable(crtc);
3372                 else if (old_crtc_state->pch_pfit.enabled)
3373                         ironlake_pfit_disable(crtc, true);
3374         }
3375 }
3376
3377 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3378 {
3379         struct drm_device *dev = crtc->dev;
3380         struct drm_i915_private *dev_priv = dev->dev_private;
3381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382         int pipe = intel_crtc->pipe;
3383         u32 reg, temp;
3384
3385         /* enable normal train */
3386         reg = FDI_TX_CTL(pipe);
3387         temp = I915_READ(reg);
3388         if (IS_IVYBRIDGE(dev)) {
3389                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3390                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3391         } else {
3392                 temp &= ~FDI_LINK_TRAIN_NONE;
3393                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3394         }
3395         I915_WRITE(reg, temp);
3396
3397         reg = FDI_RX_CTL(pipe);
3398         temp = I915_READ(reg);
3399         if (HAS_PCH_CPT(dev)) {
3400                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3401                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3402         } else {
3403                 temp &= ~FDI_LINK_TRAIN_NONE;
3404                 temp |= FDI_LINK_TRAIN_NONE;
3405         }
3406         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3407
3408         /* wait one idle pattern time */
3409         POSTING_READ(reg);
3410         udelay(1000);
3411
3412         /* IVB wants error correction enabled */
3413         if (IS_IVYBRIDGE(dev))
3414                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3415                            FDI_FE_ERRC_ENABLE);
3416 }
3417
3418 /* The FDI link training functions for ILK/Ibexpeak. */
3419 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3420 {
3421         struct drm_device *dev = crtc->dev;
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424         int pipe = intel_crtc->pipe;
3425         u32 reg, temp, tries;
3426
3427         /* FDI needs bits from pipe first */
3428         assert_pipe_enabled(dev_priv, pipe);
3429
3430         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3431            for train result */
3432         reg = FDI_RX_IMR(pipe);
3433         temp = I915_READ(reg);
3434         temp &= ~FDI_RX_SYMBOL_LOCK;
3435         temp &= ~FDI_RX_BIT_LOCK;
3436         I915_WRITE(reg, temp);
3437         I915_READ(reg);
3438         udelay(150);
3439
3440         /* enable CPU FDI TX and PCH FDI RX */
3441         reg = FDI_TX_CTL(pipe);
3442         temp = I915_READ(reg);
3443         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3444         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3445         temp &= ~FDI_LINK_TRAIN_NONE;
3446         temp |= FDI_LINK_TRAIN_PATTERN_1;
3447         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3448
3449         reg = FDI_RX_CTL(pipe);
3450         temp = I915_READ(reg);
3451         temp &= ~FDI_LINK_TRAIN_NONE;
3452         temp |= FDI_LINK_TRAIN_PATTERN_1;
3453         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3454
3455         POSTING_READ(reg);
3456         udelay(150);
3457
3458         /* Ironlake workaround, enable clock pointer after FDI enable*/
3459         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3460         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3461                    FDI_RX_PHASE_SYNC_POINTER_EN);
3462
3463         reg = FDI_RX_IIR(pipe);
3464         for (tries = 0; tries < 5; tries++) {
3465                 temp = I915_READ(reg);
3466                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3467
3468                 if ((temp & FDI_RX_BIT_LOCK)) {
3469                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3470                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3471                         break;
3472                 }
3473         }
3474         if (tries == 5)
3475                 DRM_ERROR("FDI train 1 fail!\n");
3476
3477         /* Train 2 */
3478         reg = FDI_TX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         temp &= ~FDI_LINK_TRAIN_NONE;
3481         temp |= FDI_LINK_TRAIN_PATTERN_2;
3482         I915_WRITE(reg, temp);
3483
3484         reg = FDI_RX_CTL(pipe);
3485         temp = I915_READ(reg);
3486         temp &= ~FDI_LINK_TRAIN_NONE;
3487         temp |= FDI_LINK_TRAIN_PATTERN_2;
3488         I915_WRITE(reg, temp);
3489
3490         POSTING_READ(reg);
3491         udelay(150);
3492
3493         reg = FDI_RX_IIR(pipe);
3494         for (tries = 0; tries < 5; tries++) {
3495                 temp = I915_READ(reg);
3496                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3497
3498                 if (temp & FDI_RX_SYMBOL_LOCK) {
3499                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3500                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3501                         break;
3502                 }
3503         }
3504         if (tries == 5)
3505                 DRM_ERROR("FDI train 2 fail!\n");
3506
3507         DRM_DEBUG_KMS("FDI train done\n");
3508
3509 }
3510
3511 static const int snb_b_fdi_train_param[] = {
3512         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3513         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3514         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3515         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3516 };
3517
3518 /* The FDI link training functions for SNB/Cougarpoint. */
3519 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3520 {
3521         struct drm_device *dev = crtc->dev;
3522         struct drm_i915_private *dev_priv = dev->dev_private;
3523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524         int pipe = intel_crtc->pipe;
3525         u32 reg, temp, i, retry;
3526
3527         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3528            for train result */
3529         reg = FDI_RX_IMR(pipe);
3530         temp = I915_READ(reg);
3531         temp &= ~FDI_RX_SYMBOL_LOCK;
3532         temp &= ~FDI_RX_BIT_LOCK;
3533         I915_WRITE(reg, temp);
3534
3535         POSTING_READ(reg);
3536         udelay(150);
3537
3538         /* enable CPU FDI TX and PCH FDI RX */
3539         reg = FDI_TX_CTL(pipe);
3540         temp = I915_READ(reg);
3541         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3542         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3543         temp &= ~FDI_LINK_TRAIN_NONE;
3544         temp |= FDI_LINK_TRAIN_PATTERN_1;
3545         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546         /* SNB-B */
3547         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3548         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3549
3550         I915_WRITE(FDI_RX_MISC(pipe),
3551                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3552
3553         reg = FDI_RX_CTL(pipe);
3554         temp = I915_READ(reg);
3555         if (HAS_PCH_CPT(dev)) {
3556                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3557                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3558         } else {
3559                 temp &= ~FDI_LINK_TRAIN_NONE;
3560                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3561         }
3562         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3563
3564         POSTING_READ(reg);
3565         udelay(150);
3566
3567         for (i = 0; i < 4; i++) {
3568                 reg = FDI_TX_CTL(pipe);
3569                 temp = I915_READ(reg);
3570                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3571                 temp |= snb_b_fdi_train_param[i];
3572                 I915_WRITE(reg, temp);
3573
3574                 POSTING_READ(reg);
3575                 udelay(500);
3576
3577                 for (retry = 0; retry < 5; retry++) {
3578                         reg = FDI_RX_IIR(pipe);
3579                         temp = I915_READ(reg);
3580                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3581                         if (temp & FDI_RX_BIT_LOCK) {
3582                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3583                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3584                                 break;
3585                         }
3586                         udelay(50);
3587                 }
3588                 if (retry < 5)
3589                         break;
3590         }
3591         if (i == 4)
3592                 DRM_ERROR("FDI train 1 fail!\n");
3593
3594         /* Train 2 */
3595         reg = FDI_TX_CTL(pipe);
3596         temp = I915_READ(reg);
3597         temp &= ~FDI_LINK_TRAIN_NONE;
3598         temp |= FDI_LINK_TRAIN_PATTERN_2;
3599         if (IS_GEN6(dev)) {
3600                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3601                 /* SNB-B */
3602                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3603         }
3604         I915_WRITE(reg, temp);
3605
3606         reg = FDI_RX_CTL(pipe);
3607         temp = I915_READ(reg);
3608         if (HAS_PCH_CPT(dev)) {
3609                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3610                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3611         } else {
3612                 temp &= ~FDI_LINK_TRAIN_NONE;
3613                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3614         }
3615         I915_WRITE(reg, temp);
3616
3617         POSTING_READ(reg);
3618         udelay(150);
3619
3620         for (i = 0; i < 4; i++) {
3621                 reg = FDI_TX_CTL(pipe);
3622                 temp = I915_READ(reg);
3623                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3624                 temp |= snb_b_fdi_train_param[i];
3625                 I915_WRITE(reg, temp);
3626
3627                 POSTING_READ(reg);
3628                 udelay(500);
3629
3630                 for (retry = 0; retry < 5; retry++) {
3631                         reg = FDI_RX_IIR(pipe);
3632                         temp = I915_READ(reg);
3633                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3634                         if (temp & FDI_RX_SYMBOL_LOCK) {
3635                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3636                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3637                                 break;
3638                         }
3639                         udelay(50);
3640                 }
3641                 if (retry < 5)
3642                         break;
3643         }
3644         if (i == 4)
3645                 DRM_ERROR("FDI train 2 fail!\n");
3646
3647         DRM_DEBUG_KMS("FDI train done.\n");
3648 }
3649
3650 /* Manual link training for Ivy Bridge A0 parts */
3651 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3652 {
3653         struct drm_device *dev = crtc->dev;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656         int pipe = intel_crtc->pipe;
3657         u32 reg, temp, i, j;
3658
3659         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3660            for train result */
3661         reg = FDI_RX_IMR(pipe);
3662         temp = I915_READ(reg);
3663         temp &= ~FDI_RX_SYMBOL_LOCK;
3664         temp &= ~FDI_RX_BIT_LOCK;
3665         I915_WRITE(reg, temp);
3666
3667         POSTING_READ(reg);
3668         udelay(150);
3669
3670         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3671                       I915_READ(FDI_RX_IIR(pipe)));
3672
3673         /* Try each vswing and preemphasis setting twice before moving on */
3674         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3675                 /* disable first in case we need to retry */
3676                 reg = FDI_TX_CTL(pipe);
3677                 temp = I915_READ(reg);
3678                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3679                 temp &= ~FDI_TX_ENABLE;
3680                 I915_WRITE(reg, temp);
3681
3682                 reg = FDI_RX_CTL(pipe);
3683                 temp = I915_READ(reg);
3684                 temp &= ~FDI_LINK_TRAIN_AUTO;
3685                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3686                 temp &= ~FDI_RX_ENABLE;
3687                 I915_WRITE(reg, temp);
3688
3689                 /* enable CPU FDI TX and PCH FDI RX */
3690                 reg = FDI_TX_CTL(pipe);
3691                 temp = I915_READ(reg);
3692                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3693                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3694                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3695                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3696                 temp |= snb_b_fdi_train_param[j/2];
3697                 temp |= FDI_COMPOSITE_SYNC;
3698                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3699
3700                 I915_WRITE(FDI_RX_MISC(pipe),
3701                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3702
3703                 reg = FDI_RX_CTL(pipe);
3704                 temp = I915_READ(reg);
3705                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3706                 temp |= FDI_COMPOSITE_SYNC;
3707                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3708
3709                 POSTING_READ(reg);
3710                 udelay(1); /* should be 0.5us */
3711
3712                 for (i = 0; i < 4; i++) {
3713                         reg = FDI_RX_IIR(pipe);
3714                         temp = I915_READ(reg);
3715                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3716
3717                         if (temp & FDI_RX_BIT_LOCK ||
3718                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3719                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3720                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3721                                               i);
3722                                 break;
3723                         }
3724                         udelay(1); /* should be 0.5us */
3725                 }
3726                 if (i == 4) {
3727                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3728                         continue;
3729                 }
3730
3731                 /* Train 2 */
3732                 reg = FDI_TX_CTL(pipe);
3733                 temp = I915_READ(reg);
3734                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3735                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3736                 I915_WRITE(reg, temp);
3737
3738                 reg = FDI_RX_CTL(pipe);
3739                 temp = I915_READ(reg);
3740                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3741                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3742                 I915_WRITE(reg, temp);
3743
3744                 POSTING_READ(reg);
3745                 udelay(2); /* should be 1.5us */
3746
3747                 for (i = 0; i < 4; i++) {
3748                         reg = FDI_RX_IIR(pipe);
3749                         temp = I915_READ(reg);
3750                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3751
3752                         if (temp & FDI_RX_SYMBOL_LOCK ||
3753                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3754                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3755                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3756                                               i);
3757                                 goto train_done;
3758                         }
3759                         udelay(2); /* should be 1.5us */
3760                 }
3761                 if (i == 4)
3762                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3763         }
3764
3765 train_done:
3766         DRM_DEBUG_KMS("FDI train done.\n");
3767 }
3768
3769 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3770 {
3771         struct drm_device *dev = intel_crtc->base.dev;
3772         struct drm_i915_private *dev_priv = dev->dev_private;
3773         int pipe = intel_crtc->pipe;
3774         u32 reg, temp;
3775
3776
3777         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3778         reg = FDI_RX_CTL(pipe);
3779         temp = I915_READ(reg);
3780         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3781         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3782         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3783         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3784
3785         POSTING_READ(reg);
3786         udelay(200);
3787
3788         /* Switch from Rawclk to PCDclk */
3789         temp = I915_READ(reg);
3790         I915_WRITE(reg, temp | FDI_PCDCLK);
3791
3792         POSTING_READ(reg);
3793         udelay(200);
3794
3795         /* Enable CPU FDI TX PLL, always on for Ironlake */
3796         reg = FDI_TX_CTL(pipe);
3797         temp = I915_READ(reg);
3798         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3799                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3800
3801                 POSTING_READ(reg);
3802                 udelay(100);
3803         }
3804 }
3805
3806 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3807 {
3808         struct drm_device *dev = intel_crtc->base.dev;
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810         int pipe = intel_crtc->pipe;
3811         u32 reg, temp;
3812
3813         /* Switch from PCDclk to Rawclk */
3814         reg = FDI_RX_CTL(pipe);
3815         temp = I915_READ(reg);
3816         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3817
3818         /* Disable CPU FDI TX PLL */
3819         reg = FDI_TX_CTL(pipe);
3820         temp = I915_READ(reg);
3821         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3822
3823         POSTING_READ(reg);
3824         udelay(100);
3825
3826         reg = FDI_RX_CTL(pipe);
3827         temp = I915_READ(reg);
3828         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3829
3830         /* Wait for the clocks to turn off. */
3831         POSTING_READ(reg);
3832         udelay(100);
3833 }
3834
3835 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3836 {
3837         struct drm_device *dev = crtc->dev;
3838         struct drm_i915_private *dev_priv = dev->dev_private;
3839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3840         int pipe = intel_crtc->pipe;
3841         u32 reg, temp;
3842
3843         /* disable CPU FDI tx and PCH FDI rx */
3844         reg = FDI_TX_CTL(pipe);
3845         temp = I915_READ(reg);
3846         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3847         POSTING_READ(reg);
3848
3849         reg = FDI_RX_CTL(pipe);
3850         temp = I915_READ(reg);
3851         temp &= ~(0x7 << 16);
3852         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3853         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3854
3855         POSTING_READ(reg);
3856         udelay(100);
3857
3858         /* Ironlake workaround, disable clock pointer after downing FDI */
3859         if (HAS_PCH_IBX(dev))
3860                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3861
3862         /* still set train pattern 1 */
3863         reg = FDI_TX_CTL(pipe);
3864         temp = I915_READ(reg);
3865         temp &= ~FDI_LINK_TRAIN_NONE;
3866         temp |= FDI_LINK_TRAIN_PATTERN_1;
3867         I915_WRITE(reg, temp);
3868
3869         reg = FDI_RX_CTL(pipe);
3870         temp = I915_READ(reg);
3871         if (HAS_PCH_CPT(dev)) {
3872                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3873                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3874         } else {
3875                 temp &= ~FDI_LINK_TRAIN_NONE;
3876                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3877         }
3878         /* BPC in FDI rx is consistent with that in PIPECONF */
3879         temp &= ~(0x07 << 16);
3880         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3881         I915_WRITE(reg, temp);
3882
3883         POSTING_READ(reg);
3884         udelay(100);
3885 }
3886
3887 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3888 {
3889         struct intel_crtc *crtc;
3890
3891         /* Note that we don't need to be called with mode_config.lock here
3892          * as our list of CRTC objects is static for the lifetime of the
3893          * device and so cannot disappear as we iterate. Similarly, we can
3894          * happily treat the predicates as racy, atomic checks as userspace
3895          * cannot claim and pin a new fb without at least acquring the
3896          * struct_mutex and so serialising with us.
3897          */
3898         for_each_intel_crtc(dev, crtc) {
3899                 if (atomic_read(&crtc->unpin_work_count) == 0)
3900                         continue;
3901
3902                 if (crtc->unpin_work)
3903                         intel_wait_for_vblank(dev, crtc->pipe);
3904
3905                 return true;
3906         }
3907
3908         return false;
3909 }
3910
3911 static void page_flip_completed(struct intel_crtc *intel_crtc)
3912 {
3913         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3914         struct intel_unpin_work *work = intel_crtc->unpin_work;
3915
3916         /* ensure that the unpin work is consistent wrt ->pending. */
3917         smp_rmb();
3918         intel_crtc->unpin_work = NULL;
3919
3920         if (work->event)
3921                 drm_send_vblank_event(intel_crtc->base.dev,
3922                                       intel_crtc->pipe,
3923                                       work->event);
3924
3925         drm_crtc_vblank_put(&intel_crtc->base);
3926
3927         wake_up_all(&dev_priv->pending_flip_queue);
3928         queue_work(dev_priv->wq, &work->work);
3929
3930         trace_i915_flip_complete(intel_crtc->plane,
3931                                  work->pending_flip_obj);
3932 }
3933
3934 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3935 {
3936         struct drm_device *dev = crtc->dev;
3937         struct drm_i915_private *dev_priv = dev->dev_private;
3938
3939         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3940         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3941                                        !intel_crtc_has_pending_flip(crtc),
3942                                        60*HZ) == 0)) {
3943                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944
3945                 spin_lock_irq(&dev->event_lock);
3946                 if (intel_crtc->unpin_work) {
3947                         WARN_ONCE(1, "Removing stuck page flip\n");
3948                         page_flip_completed(intel_crtc);
3949                 }
3950                 spin_unlock_irq(&dev->event_lock);
3951         }
3952
3953         if (crtc->primary->fb) {
3954                 mutex_lock(&dev->struct_mutex);
3955                 intel_finish_fb(crtc->primary->fb);
3956                 mutex_unlock(&dev->struct_mutex);
3957         }
3958 }
3959
3960 /* Program iCLKIP clock to the desired frequency */
3961 static void lpt_program_iclkip(struct drm_crtc *crtc)
3962 {
3963         struct drm_device *dev = crtc->dev;
3964         struct drm_i915_private *dev_priv = dev->dev_private;
3965         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3966         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3967         u32 temp;
3968
3969         mutex_lock(&dev_priv->sb_lock);
3970
3971         /* It is necessary to ungate the pixclk gate prior to programming
3972          * the divisors, and gate it back when it is done.
3973          */
3974         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3975
3976         /* Disable SSCCTL */
3977         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3978                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3979                                 SBI_SSCCTL_DISABLE,
3980                         SBI_ICLK);
3981
3982         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3983         if (clock == 20000) {
3984                 auxdiv = 1;
3985                 divsel = 0x41;
3986                 phaseinc = 0x20;
3987         } else {
3988                 /* The iCLK virtual clock root frequency is in MHz,
3989                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3990                  * divisors, it is necessary to divide one by another, so we
3991                  * convert the virtual clock precision to KHz here for higher
3992                  * precision.
3993                  */
3994                 u32 iclk_virtual_root_freq = 172800 * 1000;
3995                 u32 iclk_pi_range = 64;
3996                 u32 desired_divisor, msb_divisor_value, pi_value;
3997
3998                 desired_divisor = (iclk_virtual_root_freq / clock);
3999                 msb_divisor_value = desired_divisor / iclk_pi_range;
4000                 pi_value = desired_divisor % iclk_pi_range;
4001
4002                 auxdiv = 0;
4003                 divsel = msb_divisor_value - 2;
4004                 phaseinc = pi_value;
4005         }
4006
4007         /* This should not happen with any sane values */
4008         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4009                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4010         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4011                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4012
4013         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4014                         clock,
4015                         auxdiv,
4016                         divsel,
4017                         phasedir,
4018                         phaseinc);
4019
4020         /* Program SSCDIVINTPHASE6 */
4021         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4022         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4023         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4024         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4025         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4026         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4027         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4028         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4029
4030         /* Program SSCAUXDIV */
4031         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4032         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4033         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4034         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4035
4036         /* Enable modulator and associated divider */
4037         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4038         temp &= ~SBI_SSCCTL_DISABLE;
4039         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4040
4041         /* Wait for initialization time */
4042         udelay(24);
4043
4044         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4045
4046         mutex_unlock(&dev_priv->sb_lock);
4047 }
4048
4049 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4050                                                 enum pipe pch_transcoder)
4051 {
4052         struct drm_device *dev = crtc->base.dev;
4053         struct drm_i915_private *dev_priv = dev->dev_private;
4054         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4055
4056         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4057                    I915_READ(HTOTAL(cpu_transcoder)));
4058         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4059                    I915_READ(HBLANK(cpu_transcoder)));
4060         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4061                    I915_READ(HSYNC(cpu_transcoder)));
4062
4063         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4064                    I915_READ(VTOTAL(cpu_transcoder)));
4065         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4066                    I915_READ(VBLANK(cpu_transcoder)));
4067         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4068                    I915_READ(VSYNC(cpu_transcoder)));
4069         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4070                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4071 }
4072
4073 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4074 {
4075         struct drm_i915_private *dev_priv = dev->dev_private;
4076         uint32_t temp;
4077
4078         temp = I915_READ(SOUTH_CHICKEN1);
4079         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4080                 return;
4081
4082         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4083         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4084
4085         temp &= ~FDI_BC_BIFURCATION_SELECT;
4086         if (enable)
4087                 temp |= FDI_BC_BIFURCATION_SELECT;
4088
4089         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4090         I915_WRITE(SOUTH_CHICKEN1, temp);
4091         POSTING_READ(SOUTH_CHICKEN1);
4092 }
4093
4094 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4095 {
4096         struct drm_device *dev = intel_crtc->base.dev;
4097
4098         switch (intel_crtc->pipe) {
4099         case PIPE_A:
4100                 break;
4101         case PIPE_B:
4102                 if (intel_crtc->config->fdi_lanes > 2)
4103                         cpt_set_fdi_bc_bifurcation(dev, false);
4104                 else
4105                         cpt_set_fdi_bc_bifurcation(dev, true);
4106
4107                 break;
4108         case PIPE_C:
4109                 cpt_set_fdi_bc_bifurcation(dev, true);
4110
4111                 break;
4112         default:
4113                 BUG();
4114         }
4115 }
4116
4117 /*
4118  * Enable PCH resources required for PCH ports:
4119  *   - PCH PLLs
4120  *   - FDI training & RX/TX
4121  *   - update transcoder timings
4122  *   - DP transcoding bits
4123  *   - transcoder
4124  */
4125 static void ironlake_pch_enable(struct drm_crtc *crtc)
4126 {
4127         struct drm_device *dev = crtc->dev;
4128         struct drm_i915_private *dev_priv = dev->dev_private;
4129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4130         int pipe = intel_crtc->pipe;
4131         u32 reg, temp;
4132
4133         assert_pch_transcoder_disabled(dev_priv, pipe);
4134
4135         if (IS_IVYBRIDGE(dev))
4136                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4137
4138         /* Write the TU size bits before fdi link training, so that error
4139          * detection works. */
4140         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4141                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4142
4143         /* For PCH output, training FDI link */
4144         dev_priv->display.fdi_link_train(crtc);
4145
4146         /* We need to program the right clock selection before writing the pixel
4147          * mutliplier into the DPLL. */
4148         if (HAS_PCH_CPT(dev)) {
4149                 u32 sel;
4150
4151                 temp = I915_READ(PCH_DPLL_SEL);
4152                 temp |= TRANS_DPLL_ENABLE(pipe);
4153                 sel = TRANS_DPLLB_SEL(pipe);
4154                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4155                         temp |= sel;
4156                 else
4157                         temp &= ~sel;
4158                 I915_WRITE(PCH_DPLL_SEL, temp);
4159         }
4160
4161         /* XXX: pch pll's can be enabled any time before we enable the PCH
4162          * transcoder, and we actually should do this to not upset any PCH
4163          * transcoder that already use the clock when we share it.
4164          *
4165          * Note that enable_shared_dpll tries to do the right thing, but
4166          * get_shared_dpll unconditionally resets the pll - we need that to have
4167          * the right LVDS enable sequence. */
4168         intel_enable_shared_dpll(intel_crtc);
4169
4170         /* set transcoder timing, panel must allow it */
4171         assert_panel_unlocked(dev_priv, pipe);
4172         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4173
4174         intel_fdi_normal_train(crtc);
4175
4176         /* For PCH DP, enable TRANS_DP_CTL */
4177         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4178                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4179                 reg = TRANS_DP_CTL(pipe);
4180                 temp = I915_READ(reg);
4181                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4182                           TRANS_DP_SYNC_MASK |
4183                           TRANS_DP_BPC_MASK);
4184                 temp |= TRANS_DP_OUTPUT_ENABLE;
4185                 temp |= bpc << 9; /* same format but at 11:9 */
4186
4187                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4188                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4189                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4190                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4191
4192                 switch (intel_trans_dp_port_sel(crtc)) {
4193                 case PCH_DP_B:
4194                         temp |= TRANS_DP_PORT_SEL_B;
4195                         break;
4196                 case PCH_DP_C:
4197                         temp |= TRANS_DP_PORT_SEL_C;
4198                         break;
4199                 case PCH_DP_D:
4200                         temp |= TRANS_DP_PORT_SEL_D;
4201                         break;
4202                 default:
4203                         BUG();
4204                 }
4205
4206                 I915_WRITE(reg, temp);
4207         }
4208
4209         ironlake_enable_pch_transcoder(dev_priv, pipe);
4210 }
4211
4212 static void lpt_pch_enable(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4218
4219         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4220
4221         lpt_program_iclkip(crtc);
4222
4223         /* Set transcoder timing. */
4224         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4225
4226         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4227 }
4228
4229 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4230                                                 struct intel_crtc_state *crtc_state)
4231 {
4232         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4233         struct intel_shared_dpll *pll;
4234         struct intel_shared_dpll_config *shared_dpll;
4235         enum intel_dpll_id i;
4236
4237         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4238
4239         if (HAS_PCH_IBX(dev_priv->dev)) {
4240                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4241                 i = (enum intel_dpll_id) crtc->pipe;
4242                 pll = &dev_priv->shared_dplls[i];
4243
4244                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4245                               crtc->base.base.id, pll->name);
4246
4247                 WARN_ON(shared_dpll[i].crtc_mask);
4248
4249                 goto found;
4250         }
4251
4252         if (IS_BROXTON(dev_priv->dev)) {
4253                 /* PLL is attached to port in bxt */
4254                 struct intel_encoder *encoder;
4255                 struct intel_digital_port *intel_dig_port;
4256
4257                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4258                 if (WARN_ON(!encoder))
4259                         return NULL;
4260
4261                 intel_dig_port = enc_to_dig_port(&encoder->base);
4262                 /* 1:1 mapping between ports and PLLs */
4263                 i = (enum intel_dpll_id)intel_dig_port->port;
4264                 pll = &dev_priv->shared_dplls[i];
4265                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4266                         crtc->base.base.id, pll->name);
4267                 WARN_ON(shared_dpll[i].crtc_mask);
4268
4269                 goto found;
4270         }
4271
4272         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4273                 pll = &dev_priv->shared_dplls[i];
4274
4275                 /* Only want to check enabled timings first */
4276                 if (shared_dpll[i].crtc_mask == 0)
4277                         continue;
4278
4279                 if (memcmp(&crtc_state->dpll_hw_state,
4280                            &shared_dpll[i].hw_state,
4281                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4282                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4283                                       crtc->base.base.id, pll->name,
4284                                       shared_dpll[i].crtc_mask,
4285                                       pll->active);
4286                         goto found;
4287                 }
4288         }
4289
4290         /* Ok no matching timings, maybe there's a free one? */
4291         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4292                 pll = &dev_priv->shared_dplls[i];
4293                 if (shared_dpll[i].crtc_mask == 0) {
4294                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4295                                       crtc->base.base.id, pll->name);
4296                         goto found;
4297                 }
4298         }
4299
4300         return NULL;
4301
4302 found:
4303         if (shared_dpll[i].crtc_mask == 0)
4304                 shared_dpll[i].hw_state =
4305                         crtc_state->dpll_hw_state;
4306
4307         crtc_state->shared_dpll = i;
4308         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4309                          pipe_name(crtc->pipe));
4310
4311         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4312
4313         return pll;
4314 }
4315
4316 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4317 {
4318         struct drm_i915_private *dev_priv = to_i915(state->dev);
4319         struct intel_shared_dpll_config *shared_dpll;
4320         struct intel_shared_dpll *pll;
4321         enum intel_dpll_id i;
4322
4323         if (!to_intel_atomic_state(state)->dpll_set)
4324                 return;
4325
4326         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4327         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4328                 pll = &dev_priv->shared_dplls[i];
4329                 pll->config = shared_dpll[i];
4330         }
4331 }
4332
4333 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4334 {
4335         struct drm_i915_private *dev_priv = dev->dev_private;
4336         int dslreg = PIPEDSL(pipe);
4337         u32 temp;
4338
4339         temp = I915_READ(dslreg);
4340         udelay(500);
4341         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4342                 if (wait_for(I915_READ(dslreg) != temp, 5))
4343                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4344         }
4345 }
4346
4347 static int
4348 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4349                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4350                   int src_w, int src_h, int dst_w, int dst_h)
4351 {
4352         struct intel_crtc_scaler_state *scaler_state =
4353                 &crtc_state->scaler_state;
4354         struct intel_crtc *intel_crtc =
4355                 to_intel_crtc(crtc_state->base.crtc);
4356         int need_scaling;
4357
4358         need_scaling = intel_rotation_90_or_270(rotation) ?
4359                 (src_h != dst_w || src_w != dst_h):
4360                 (src_w != dst_w || src_h != dst_h);
4361
4362         /*
4363          * if plane is being disabled or scaler is no more required or force detach
4364          *  - free scaler binded to this plane/crtc
4365          *  - in order to do this, update crtc->scaler_usage
4366          *
4367          * Here scaler state in crtc_state is set free so that
4368          * scaler can be assigned to other user. Actual register
4369          * update to free the scaler is done in plane/panel-fit programming.
4370          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4371          */
4372         if (force_detach || !need_scaling) {
4373                 if (*scaler_id >= 0) {
4374                         scaler_state->scaler_users &= ~(1 << scaler_user);
4375                         scaler_state->scalers[*scaler_id].in_use = 0;
4376
4377                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4378                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4379                                 intel_crtc->pipe, scaler_user, *scaler_id,
4380                                 scaler_state->scaler_users);
4381                         *scaler_id = -1;
4382                 }
4383                 return 0;
4384         }
4385
4386         /* range checks */
4387         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4388                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4389
4390                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4391                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4392                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4393                         "size is out of scaler range\n",
4394                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4395                 return -EINVAL;
4396         }
4397
4398         /* mark this plane as a scaler user in crtc_state */
4399         scaler_state->scaler_users |= (1 << scaler_user);
4400         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4401                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4402                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4403                 scaler_state->scaler_users);
4404
4405         return 0;
4406 }
4407
4408 /**
4409  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4410  *
4411  * @state: crtc's scaler state
4412  *
4413  * Return
4414  *     0 - scaler_usage updated successfully
4415  *    error - requested scaling cannot be supported or other error condition
4416  */
4417 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4418 {
4419         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4420         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4421
4422         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4423                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4424
4425         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4426                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4427                 state->pipe_src_w, state->pipe_src_h,
4428                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4429 }
4430
4431 /**
4432  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4433  *
4434  * @state: crtc's scaler state
4435  * @plane_state: atomic plane state to update
4436  *
4437  * Return
4438  *     0 - scaler_usage updated successfully
4439  *    error - requested scaling cannot be supported or other error condition
4440  */
4441 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4442                                    struct intel_plane_state *plane_state)
4443 {
4444
4445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4446         struct intel_plane *intel_plane =
4447                 to_intel_plane(plane_state->base.plane);
4448         struct drm_framebuffer *fb = plane_state->base.fb;
4449         int ret;
4450
4451         bool force_detach = !fb || !plane_state->visible;
4452
4453         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4454                       intel_plane->base.base.id, intel_crtc->pipe,
4455                       drm_plane_index(&intel_plane->base));
4456
4457         ret = skl_update_scaler(crtc_state, force_detach,
4458                                 drm_plane_index(&intel_plane->base),
4459                                 &plane_state->scaler_id,
4460                                 plane_state->base.rotation,
4461                                 drm_rect_width(&plane_state->src) >> 16,
4462                                 drm_rect_height(&plane_state->src) >> 16,
4463                                 drm_rect_width(&plane_state->dst),
4464                                 drm_rect_height(&plane_state->dst));
4465
4466         if (ret || plane_state->scaler_id < 0)
4467                 return ret;
4468
4469         /* check colorkey */
4470         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4471                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4472                               intel_plane->base.base.id);
4473                 return -EINVAL;
4474         }
4475
4476         /* Check src format */
4477         switch (fb->pixel_format) {
4478         case DRM_FORMAT_RGB565:
4479         case DRM_FORMAT_XBGR8888:
4480         case DRM_FORMAT_XRGB8888:
4481         case DRM_FORMAT_ABGR8888:
4482         case DRM_FORMAT_ARGB8888:
4483         case DRM_FORMAT_XRGB2101010:
4484         case DRM_FORMAT_XBGR2101010:
4485         case DRM_FORMAT_YUYV:
4486         case DRM_FORMAT_YVYU:
4487         case DRM_FORMAT_UYVY:
4488         case DRM_FORMAT_VYUY:
4489                 break;
4490         default:
4491                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4492                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4493                 return -EINVAL;
4494         }
4495
4496         return 0;
4497 }
4498
4499 static void skylake_scaler_disable(struct intel_crtc *crtc)
4500 {
4501         int i;
4502
4503         for (i = 0; i < crtc->num_scalers; i++)
4504                 skl_detach_scaler(crtc, i);
4505 }
4506
4507 static void skylake_pfit_enable(struct intel_crtc *crtc)
4508 {
4509         struct drm_device *dev = crtc->base.dev;
4510         struct drm_i915_private *dev_priv = dev->dev_private;
4511         int pipe = crtc->pipe;
4512         struct intel_crtc_scaler_state *scaler_state =
4513                 &crtc->config->scaler_state;
4514
4515         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4516
4517         if (crtc->config->pch_pfit.enabled) {
4518                 int id;
4519
4520                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4521                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4522                         return;
4523                 }
4524
4525                 id = scaler_state->scaler_id;
4526                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4527                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4528                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4529                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4530
4531                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4532         }
4533 }
4534
4535 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4536 {
4537         struct drm_device *dev = crtc->base.dev;
4538         struct drm_i915_private *dev_priv = dev->dev_private;
4539         int pipe = crtc->pipe;
4540
4541         if (crtc->config->pch_pfit.enabled) {
4542                 /* Force use of hard-coded filter coefficients
4543                  * as some pre-programmed values are broken,
4544                  * e.g. x201.
4545                  */
4546                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4547                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4548                                                  PF_PIPE_SEL_IVB(pipe));
4549                 else
4550                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4551                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4552                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4553         }
4554 }
4555
4556 void hsw_enable_ips(struct intel_crtc *crtc)
4557 {
4558         struct drm_device *dev = crtc->base.dev;
4559         struct drm_i915_private *dev_priv = dev->dev_private;
4560
4561         if (!crtc->config->ips_enabled)
4562                 return;
4563
4564         /* We can only enable IPS after we enable a plane and wait for a vblank */
4565         intel_wait_for_vblank(dev, crtc->pipe);
4566
4567         assert_plane_enabled(dev_priv, crtc->plane);
4568         if (IS_BROADWELL(dev)) {
4569                 mutex_lock(&dev_priv->rps.hw_lock);
4570                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4571                 mutex_unlock(&dev_priv->rps.hw_lock);
4572                 /* Quoting Art Runyan: "its not safe to expect any particular
4573                  * value in IPS_CTL bit 31 after enabling IPS through the
4574                  * mailbox." Moreover, the mailbox may return a bogus state,
4575                  * so we need to just enable it and continue on.
4576                  */
4577         } else {
4578                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4579                 /* The bit only becomes 1 in the next vblank, so this wait here
4580                  * is essentially intel_wait_for_vblank. If we don't have this
4581                  * and don't wait for vblanks until the end of crtc_enable, then
4582                  * the HW state readout code will complain that the expected
4583                  * IPS_CTL value is not the one we read. */
4584                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4585                         DRM_ERROR("Timed out waiting for IPS enable\n");
4586         }
4587 }
4588
4589 void hsw_disable_ips(struct intel_crtc *crtc)
4590 {
4591         struct drm_device *dev = crtc->base.dev;
4592         struct drm_i915_private *dev_priv = dev->dev_private;
4593
4594         if (!crtc->config->ips_enabled)
4595                 return;
4596
4597         assert_plane_enabled(dev_priv, crtc->plane);
4598         if (IS_BROADWELL(dev)) {
4599                 mutex_lock(&dev_priv->rps.hw_lock);
4600                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4601                 mutex_unlock(&dev_priv->rps.hw_lock);
4602                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4603                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4604                         DRM_ERROR("Timed out waiting for IPS disable\n");
4605         } else {
4606                 I915_WRITE(IPS_CTL, 0);
4607                 POSTING_READ(IPS_CTL);
4608         }
4609
4610         /* We need to wait for a vblank before we can disable the plane. */
4611         intel_wait_for_vblank(dev, crtc->pipe);
4612 }
4613
4614 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4615 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4616 {
4617         struct drm_device *dev = crtc->dev;
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4620         enum pipe pipe = intel_crtc->pipe;
4621         int i;
4622         bool reenable_ips = false;
4623
4624         /* The clocks have to be on to load the palette. */
4625         if (!crtc->state->active)
4626                 return;
4627
4628         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4629                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4630                         assert_dsi_pll_enabled(dev_priv);
4631                 else
4632                         assert_pll_enabled(dev_priv, pipe);
4633         }
4634
4635         /* Workaround : Do not read or write the pipe palette/gamma data while
4636          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4637          */
4638         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4639             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4640              GAMMA_MODE_MODE_SPLIT)) {
4641                 hsw_disable_ips(intel_crtc);
4642                 reenable_ips = true;
4643         }
4644
4645         for (i = 0; i < 256; i++) {
4646                 u32 palreg;
4647
4648                 if (HAS_GMCH_DISPLAY(dev))
4649                         palreg = PALETTE(pipe, i);
4650                 else
4651                         palreg = LGC_PALETTE(pipe, i);
4652
4653                 I915_WRITE(palreg,
4654                            (intel_crtc->lut_r[i] << 16) |
4655                            (intel_crtc->lut_g[i] << 8) |
4656                            intel_crtc->lut_b[i]);
4657         }
4658
4659         if (reenable_ips)
4660                 hsw_enable_ips(intel_crtc);
4661 }
4662
4663 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4664 {
4665         if (intel_crtc->overlay) {
4666                 struct drm_device *dev = intel_crtc->base.dev;
4667                 struct drm_i915_private *dev_priv = dev->dev_private;
4668
4669                 mutex_lock(&dev->struct_mutex);
4670                 dev_priv->mm.interruptible = false;
4671                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4672                 dev_priv->mm.interruptible = true;
4673                 mutex_unlock(&dev->struct_mutex);
4674         }
4675
4676         /* Let userspace switch the overlay on again. In most cases userspace
4677          * has to recompute where to put it anyway.
4678          */
4679 }
4680
4681 /**
4682  * intel_post_enable_primary - Perform operations after enabling primary plane
4683  * @crtc: the CRTC whose primary plane was just enabled
4684  *
4685  * Performs potentially sleeping operations that must be done after the primary
4686  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4687  * called due to an explicit primary plane update, or due to an implicit
4688  * re-enable that is caused when a sprite plane is updated to no longer
4689  * completely hide the primary plane.
4690  */
4691 static void
4692 intel_post_enable_primary(struct drm_crtc *crtc)
4693 {
4694         struct drm_device *dev = crtc->dev;
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4697         int pipe = intel_crtc->pipe;
4698
4699         /*
4700          * BDW signals flip done immediately if the plane
4701          * is disabled, even if the plane enable is already
4702          * armed to occur at the next vblank :(
4703          */
4704         if (IS_BROADWELL(dev))
4705                 intel_wait_for_vblank(dev, pipe);
4706
4707         /*
4708          * FIXME IPS should be fine as long as one plane is
4709          * enabled, but in practice it seems to have problems
4710          * when going from primary only to sprite only and vice
4711          * versa.
4712          */
4713         hsw_enable_ips(intel_crtc);
4714
4715         /*
4716          * Gen2 reports pipe underruns whenever all planes are disabled.
4717          * So don't enable underrun reporting before at least some planes
4718          * are enabled.
4719          * FIXME: Need to fix the logic to work when we turn off all planes
4720          * but leave the pipe running.
4721          */
4722         if (IS_GEN2(dev))
4723                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4724
4725         /* Underruns don't raise interrupts, so check manually. */
4726         if (HAS_GMCH_DISPLAY(dev))
4727                 i9xx_check_fifo_underruns(dev_priv);
4728 }
4729
4730 /**
4731  * intel_pre_disable_primary - Perform operations before disabling primary plane
4732  * @crtc: the CRTC whose primary plane is to be disabled
4733  *
4734  * Performs potentially sleeping operations that must be done before the
4735  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4736  * be called due to an explicit primary plane update, or due to an implicit
4737  * disable that is caused when a sprite plane completely hides the primary
4738  * plane.
4739  */
4740 static void
4741 intel_pre_disable_primary(struct drm_crtc *crtc)
4742 {
4743         struct drm_device *dev = crtc->dev;
4744         struct drm_i915_private *dev_priv = dev->dev_private;
4745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4746         int pipe = intel_crtc->pipe;
4747
4748         /*
4749          * Gen2 reports pipe underruns whenever all planes are disabled.
4750          * So diasble underrun reporting before all the planes get disabled.
4751          * FIXME: Need to fix the logic to work when we turn off all planes
4752          * but leave the pipe running.
4753          */
4754         if (IS_GEN2(dev))
4755                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757         /*
4758          * Vblank time updates from the shadow to live plane control register
4759          * are blocked if the memory self-refresh mode is active at that
4760          * moment. So to make sure the plane gets truly disabled, disable
4761          * first the self-refresh mode. The self-refresh enable bit in turn
4762          * will be checked/applied by the HW only at the next frame start
4763          * event which is after the vblank start event, so we need to have a
4764          * wait-for-vblank between disabling the plane and the pipe.
4765          */
4766         if (HAS_GMCH_DISPLAY(dev)) {
4767                 intel_set_memory_cxsr(dev_priv, false);
4768                 dev_priv->wm.vlv.cxsr = false;
4769                 intel_wait_for_vblank(dev, pipe);
4770         }
4771
4772         /*
4773          * FIXME IPS should be fine as long as one plane is
4774          * enabled, but in practice it seems to have problems
4775          * when going from primary only to sprite only and vice
4776          * versa.
4777          */
4778         hsw_disable_ips(intel_crtc);
4779 }
4780
4781 static void intel_post_plane_update(struct intel_crtc *crtc)
4782 {
4783         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4784         struct drm_device *dev = crtc->base.dev;
4785         struct drm_i915_private *dev_priv = dev->dev_private;
4786         struct drm_plane *plane;
4787
4788         if (atomic->wait_vblank)
4789                 intel_wait_for_vblank(dev, crtc->pipe);
4790
4791         intel_frontbuffer_flip(dev, atomic->fb_bits);
4792
4793         if (atomic->disable_cxsr)
4794                 crtc->wm.cxsr_allowed = true;
4795
4796         if (crtc->atomic.update_wm_post)
4797                 intel_update_watermarks(&crtc->base);
4798
4799         if (atomic->update_fbc)
4800                 intel_fbc_update(dev_priv);
4801
4802         if (atomic->post_enable_primary)
4803                 intel_post_enable_primary(&crtc->base);
4804
4805         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4806                 intel_update_sprite_watermarks(plane, &crtc->base,
4807                                                0, 0, 0, false, false);
4808
4809         memset(atomic, 0, sizeof(*atomic));
4810 }
4811
4812 static void intel_pre_plane_update(struct intel_crtc *crtc)
4813 {
4814         struct drm_device *dev = crtc->base.dev;
4815         struct drm_i915_private *dev_priv = dev->dev_private;
4816         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4817         struct drm_plane *p;
4818
4819         /* Track fb's for any planes being disabled */
4820         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4821                 struct intel_plane *plane = to_intel_plane(p);
4822
4823                 mutex_lock(&dev->struct_mutex);
4824                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4825                                   plane->frontbuffer_bit);
4826                 mutex_unlock(&dev->struct_mutex);
4827         }
4828
4829         if (atomic->wait_for_flips)
4830                 intel_crtc_wait_for_pending_flips(&crtc->base);
4831
4832         if (atomic->disable_fbc)
4833                 intel_fbc_disable_crtc(crtc);
4834
4835         if (crtc->atomic.disable_ips)
4836                 hsw_disable_ips(crtc);
4837
4838         if (atomic->pre_disable_primary)
4839                 intel_pre_disable_primary(&crtc->base);
4840
4841         if (atomic->disable_cxsr) {
4842                 crtc->wm.cxsr_allowed = false;
4843                 intel_set_memory_cxsr(dev_priv, false);
4844         }
4845 }
4846
4847 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4848 {
4849         struct drm_device *dev = crtc->dev;
4850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4851         struct drm_plane *p;
4852         int pipe = intel_crtc->pipe;
4853
4854         intel_crtc_dpms_overlay_disable(intel_crtc);
4855
4856         drm_for_each_plane_mask(p, dev, plane_mask)
4857                 to_intel_plane(p)->disable_plane(p, crtc);
4858
4859         /*
4860          * FIXME: Once we grow proper nuclear flip support out of this we need
4861          * to compute the mask of flip planes precisely. For the time being
4862          * consider this a flip to a NULL plane.
4863          */
4864         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4865 }
4866
4867 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4868 {
4869         struct drm_device *dev = crtc->dev;
4870         struct drm_i915_private *dev_priv = dev->dev_private;
4871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4872         struct intel_encoder *encoder;
4873         int pipe = intel_crtc->pipe;
4874
4875         if (WARN_ON(intel_crtc->active))
4876                 return;
4877
4878         if (intel_crtc->config->has_pch_encoder)
4879                 intel_prepare_shared_dpll(intel_crtc);
4880
4881         if (intel_crtc->config->has_dp_encoder)
4882                 intel_dp_set_m_n(intel_crtc, M1_N1);
4883
4884         intel_set_pipe_timings(intel_crtc);
4885
4886         if (intel_crtc->config->has_pch_encoder) {
4887                 intel_cpu_transcoder_set_m_n(intel_crtc,
4888                                      &intel_crtc->config->fdi_m_n, NULL);
4889         }
4890
4891         ironlake_set_pipeconf(crtc);
4892
4893         intel_crtc->active = true;
4894
4895         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4896         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4897
4898         for_each_encoder_on_crtc(dev, crtc, encoder)
4899                 if (encoder->pre_enable)
4900                         encoder->pre_enable(encoder);
4901
4902         if (intel_crtc->config->has_pch_encoder) {
4903                 /* Note: FDI PLL enabling _must_ be done before we enable the
4904                  * cpu pipes, hence this is separate from all the other fdi/pch
4905                  * enabling. */
4906                 ironlake_fdi_pll_enable(intel_crtc);
4907         } else {
4908                 assert_fdi_tx_disabled(dev_priv, pipe);
4909                 assert_fdi_rx_disabled(dev_priv, pipe);
4910         }
4911
4912         ironlake_pfit_enable(intel_crtc);
4913
4914         /*
4915          * On ILK+ LUT must be loaded before the pipe is running but with
4916          * clocks enabled
4917          */
4918         intel_crtc_load_lut(crtc);
4919
4920         intel_update_watermarks(crtc);
4921         intel_enable_pipe(intel_crtc);
4922
4923         if (intel_crtc->config->has_pch_encoder)
4924                 ironlake_pch_enable(crtc);
4925
4926         assert_vblank_disabled(crtc);
4927         drm_crtc_vblank_on(crtc);
4928
4929         for_each_encoder_on_crtc(dev, crtc, encoder)
4930                 encoder->enable(encoder);
4931
4932         if (HAS_PCH_CPT(dev))
4933                 cpt_verify_modeset(dev, intel_crtc->pipe);
4934 }
4935
4936 /* IPS only exists on ULT machines and is tied to pipe A. */
4937 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4938 {
4939         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4940 }
4941
4942 static void haswell_crtc_enable(struct drm_crtc *crtc)
4943 {
4944         struct drm_device *dev = crtc->dev;
4945         struct drm_i915_private *dev_priv = dev->dev_private;
4946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4947         struct intel_encoder *encoder;
4948         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4949         struct intel_crtc_state *pipe_config =
4950                 to_intel_crtc_state(crtc->state);
4951         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4952
4953         if (WARN_ON(intel_crtc->active))
4954                 return;
4955
4956         if (intel_crtc_to_shared_dpll(intel_crtc))
4957                 intel_enable_shared_dpll(intel_crtc);
4958
4959         if (intel_crtc->config->has_dp_encoder)
4960                 intel_dp_set_m_n(intel_crtc, M1_N1);
4961
4962         intel_set_pipe_timings(intel_crtc);
4963
4964         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4965                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4966                            intel_crtc->config->pixel_multiplier - 1);
4967         }
4968
4969         if (intel_crtc->config->has_pch_encoder) {
4970                 intel_cpu_transcoder_set_m_n(intel_crtc,
4971                                      &intel_crtc->config->fdi_m_n, NULL);
4972         }
4973
4974         haswell_set_pipeconf(crtc);
4975
4976         intel_set_pipe_csc(crtc);
4977
4978         intel_crtc->active = true;
4979
4980         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4981         for_each_encoder_on_crtc(dev, crtc, encoder) {
4982                 if (encoder->pre_pll_enable)
4983                         encoder->pre_pll_enable(encoder);
4984                 if (encoder->pre_enable)
4985                         encoder->pre_enable(encoder);
4986         }
4987
4988         if (intel_crtc->config->has_pch_encoder) {
4989                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4990                                                       true);
4991                 dev_priv->display.fdi_link_train(crtc);
4992         }
4993
4994         if (!is_dsi)
4995                 intel_ddi_enable_pipe_clock(intel_crtc);
4996
4997         if (INTEL_INFO(dev)->gen >= 9)
4998                 skylake_pfit_enable(intel_crtc);
4999         else
5000                 ironlake_pfit_enable(intel_crtc);
5001
5002         /*
5003          * On ILK+ LUT must be loaded before the pipe is running but with
5004          * clocks enabled
5005          */
5006         intel_crtc_load_lut(crtc);
5007
5008         intel_ddi_set_pipe_settings(crtc);
5009         if (!is_dsi)
5010                 intel_ddi_enable_transcoder_func(crtc);
5011
5012         intel_update_watermarks(crtc);
5013         intel_enable_pipe(intel_crtc);
5014
5015         if (intel_crtc->config->has_pch_encoder)
5016                 lpt_pch_enable(crtc);
5017
5018         if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5019                 intel_ddi_set_vc_payload_alloc(crtc, true);
5020
5021         assert_vblank_disabled(crtc);
5022         drm_crtc_vblank_on(crtc);
5023
5024         for_each_encoder_on_crtc(dev, crtc, encoder) {
5025                 encoder->enable(encoder);
5026                 intel_opregion_notify_encoder(encoder, true);
5027         }
5028
5029         /* If we change the relative order between pipe/planes enabling, we need
5030          * to change the workaround. */
5031         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5032         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5033                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5034                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5035         }
5036 }
5037
5038 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5039 {
5040         struct drm_device *dev = crtc->base.dev;
5041         struct drm_i915_private *dev_priv = dev->dev_private;
5042         int pipe = crtc->pipe;
5043
5044         /* To avoid upsetting the power well on haswell only disable the pfit if
5045          * it's in use. The hw state code will make sure we get this right. */
5046         if (force || crtc->config->pch_pfit.enabled) {
5047                 I915_WRITE(PF_CTL(pipe), 0);
5048                 I915_WRITE(PF_WIN_POS(pipe), 0);
5049                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5050         }
5051 }
5052
5053 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5054 {
5055         struct drm_device *dev = crtc->dev;
5056         struct drm_i915_private *dev_priv = dev->dev_private;
5057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058         struct intel_encoder *encoder;
5059         int pipe = intel_crtc->pipe;
5060         u32 reg, temp;
5061
5062         for_each_encoder_on_crtc(dev, crtc, encoder)
5063                 encoder->disable(encoder);
5064
5065         drm_crtc_vblank_off(crtc);
5066         assert_vblank_disabled(crtc);
5067
5068         if (intel_crtc->config->has_pch_encoder)
5069                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5070
5071         intel_disable_pipe(intel_crtc);
5072
5073         ironlake_pfit_disable(intel_crtc, false);
5074
5075         if (intel_crtc->config->has_pch_encoder)
5076                 ironlake_fdi_disable(crtc);
5077
5078         for_each_encoder_on_crtc(dev, crtc, encoder)
5079                 if (encoder->post_disable)
5080                         encoder->post_disable(encoder);
5081
5082         if (intel_crtc->config->has_pch_encoder) {
5083                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5084
5085                 if (HAS_PCH_CPT(dev)) {
5086                         /* disable TRANS_DP_CTL */
5087                         reg = TRANS_DP_CTL(pipe);
5088                         temp = I915_READ(reg);
5089                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5090                                   TRANS_DP_PORT_SEL_MASK);
5091                         temp |= TRANS_DP_PORT_SEL_NONE;
5092                         I915_WRITE(reg, temp);
5093
5094                         /* disable DPLL_SEL */
5095                         temp = I915_READ(PCH_DPLL_SEL);
5096                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5097                         I915_WRITE(PCH_DPLL_SEL, temp);
5098                 }
5099
5100                 ironlake_fdi_pll_disable(intel_crtc);
5101         }
5102 }
5103
5104 static void haswell_crtc_disable(struct drm_crtc *crtc)
5105 {
5106         struct drm_device *dev = crtc->dev;
5107         struct drm_i915_private *dev_priv = dev->dev_private;
5108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5109         struct intel_encoder *encoder;
5110         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5111         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5112
5113         for_each_encoder_on_crtc(dev, crtc, encoder) {
5114                 intel_opregion_notify_encoder(encoder, false);
5115                 encoder->disable(encoder);
5116         }
5117
5118         drm_crtc_vblank_off(crtc);
5119         assert_vblank_disabled(crtc);
5120
5121         if (intel_crtc->config->has_pch_encoder)
5122                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5123                                                       false);
5124         intel_disable_pipe(intel_crtc);
5125
5126         if (intel_crtc->config->dp_encoder_is_mst)
5127                 intel_ddi_set_vc_payload_alloc(crtc, false);
5128
5129         if (!is_dsi)
5130                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5131
5132         if (INTEL_INFO(dev)->gen >= 9)
5133                 skylake_scaler_disable(intel_crtc);
5134         else
5135                 ironlake_pfit_disable(intel_crtc, false);
5136
5137         if (!is_dsi)
5138                 intel_ddi_disable_pipe_clock(intel_crtc);
5139
5140         if (intel_crtc->config->has_pch_encoder) {
5141                 lpt_disable_pch_transcoder(dev_priv);
5142                 intel_ddi_fdi_disable(crtc);
5143         }
5144
5145         for_each_encoder_on_crtc(dev, crtc, encoder)
5146                 if (encoder->post_disable)
5147                         encoder->post_disable(encoder);
5148 }
5149
5150 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5151 {
5152         struct drm_device *dev = crtc->base.dev;
5153         struct drm_i915_private *dev_priv = dev->dev_private;
5154         struct intel_crtc_state *pipe_config = crtc->config;
5155
5156         if (!pipe_config->gmch_pfit.control)
5157                 return;
5158
5159         /*
5160          * The panel fitter should only be adjusted whilst the pipe is disabled,
5161          * according to register description and PRM.
5162          */
5163         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5164         assert_pipe_disabled(dev_priv, crtc->pipe);
5165
5166         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5167         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5168
5169         /* Border color in case we don't scale up to the full screen. Black by
5170          * default, change to something else for debugging. */
5171         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5172 }
5173
5174 static enum intel_display_power_domain port_to_power_domain(enum port port)
5175 {
5176         switch (port) {
5177         case PORT_A:
5178                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5179         case PORT_B:
5180                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5181         case PORT_C:
5182                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5183         case PORT_D:
5184                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5185         case PORT_E:
5186                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5187         default:
5188                 WARN_ON_ONCE(1);
5189                 return POWER_DOMAIN_PORT_OTHER;
5190         }
5191 }
5192
5193 #define for_each_power_domain(domain, mask)                             \
5194         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5195                 if ((1 << (domain)) & (mask))
5196
5197 enum intel_display_power_domain
5198 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5199 {
5200         struct drm_device *dev = intel_encoder->base.dev;
5201         struct intel_digital_port *intel_dig_port;
5202
5203         switch (intel_encoder->type) {
5204         case INTEL_OUTPUT_UNKNOWN:
5205                 /* Only DDI platforms should ever use this output type */
5206                 WARN_ON_ONCE(!HAS_DDI(dev));
5207         case INTEL_OUTPUT_DISPLAYPORT:
5208         case INTEL_OUTPUT_HDMI:
5209         case INTEL_OUTPUT_EDP:
5210                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5211                 return port_to_power_domain(intel_dig_port->port);
5212         case INTEL_OUTPUT_DP_MST:
5213                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5214                 return port_to_power_domain(intel_dig_port->port);
5215         case INTEL_OUTPUT_ANALOG:
5216                 return POWER_DOMAIN_PORT_CRT;
5217         case INTEL_OUTPUT_DSI:
5218                 return POWER_DOMAIN_PORT_DSI;
5219         default:
5220                 return POWER_DOMAIN_PORT_OTHER;
5221         }
5222 }
5223
5224 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5225 {
5226         struct drm_device *dev = crtc->dev;
5227         struct intel_encoder *intel_encoder;
5228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229         enum pipe pipe = intel_crtc->pipe;
5230         unsigned long mask;
5231         enum transcoder transcoder;
5232
5233         if (!crtc->state->active)
5234                 return 0;
5235
5236         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5237
5238         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5239         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5240         if (intel_crtc->config->pch_pfit.enabled ||
5241             intel_crtc->config->pch_pfit.force_thru)
5242                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5243
5244         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5245                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5246
5247         return mask;
5248 }
5249
5250 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5251 {
5252         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254         enum intel_display_power_domain domain;
5255         unsigned long domains, new_domains, old_domains;
5256
5257         old_domains = intel_crtc->enabled_power_domains;
5258         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5259
5260         domains = new_domains & ~old_domains;
5261
5262         for_each_power_domain(domain, domains)
5263                 intel_display_power_get(dev_priv, domain);
5264
5265         return old_domains & ~new_domains;
5266 }
5267
5268 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5269                                       unsigned long domains)
5270 {
5271         enum intel_display_power_domain domain;
5272
5273         for_each_power_domain(domain, domains)
5274                 intel_display_power_put(dev_priv, domain);
5275 }
5276
5277 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5278 {
5279         struct drm_device *dev = state->dev;
5280         struct drm_i915_private *dev_priv = dev->dev_private;
5281         unsigned long put_domains[I915_MAX_PIPES] = {};
5282         struct drm_crtc_state *crtc_state;
5283         struct drm_crtc *crtc;
5284         int i;
5285
5286         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5287                 if (needs_modeset(crtc->state))
5288                         put_domains[to_intel_crtc(crtc)->pipe] =
5289                                 modeset_get_crtc_power_domains(crtc);
5290         }
5291
5292         if (dev_priv->display.modeset_commit_cdclk) {
5293                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5294
5295                 if (cdclk != dev_priv->cdclk_freq &&
5296                     !WARN_ON(!state->allow_modeset))
5297                         dev_priv->display.modeset_commit_cdclk(state);
5298         }
5299
5300         for (i = 0; i < I915_MAX_PIPES; i++)
5301                 if (put_domains[i])
5302                         modeset_put_power_domains(dev_priv, put_domains[i]);
5303 }
5304
5305 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5306 {
5307         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5308
5309         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5310             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5311                 return max_cdclk_freq;
5312         else if (IS_CHERRYVIEW(dev_priv))
5313                 return max_cdclk_freq*95/100;
5314         else if (INTEL_INFO(dev_priv)->gen < 4)
5315                 return 2*max_cdclk_freq*90/100;
5316         else
5317                 return max_cdclk_freq*90/100;
5318 }
5319
5320 static void intel_update_max_cdclk(struct drm_device *dev)
5321 {
5322         struct drm_i915_private *dev_priv = dev->dev_private;
5323
5324         if (IS_SKYLAKE(dev)) {
5325                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5326
5327                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5328                         dev_priv->max_cdclk_freq = 675000;
5329                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5330                         dev_priv->max_cdclk_freq = 540000;
5331                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5332                         dev_priv->max_cdclk_freq = 450000;
5333                 else
5334                         dev_priv->max_cdclk_freq = 337500;
5335         } else if (IS_BROADWELL(dev))  {
5336                 /*
5337                  * FIXME with extra cooling we can allow
5338                  * 540 MHz for ULX and 675 Mhz for ULT.
5339                  * How can we know if extra cooling is
5340                  * available? PCI ID, VTB, something else?
5341                  */
5342                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5343                         dev_priv->max_cdclk_freq = 450000;
5344                 else if (IS_BDW_ULX(dev))
5345                         dev_priv->max_cdclk_freq = 450000;
5346                 else if (IS_BDW_ULT(dev))
5347                         dev_priv->max_cdclk_freq = 540000;
5348                 else
5349                         dev_priv->max_cdclk_freq = 675000;
5350         } else if (IS_CHERRYVIEW(dev)) {
5351                 dev_priv->max_cdclk_freq = 320000;
5352         } else if (IS_VALLEYVIEW(dev)) {
5353                 dev_priv->max_cdclk_freq = 400000;
5354         } else {
5355                 /* otherwise assume cdclk is fixed */
5356                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5357         }
5358
5359         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5360
5361         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5362                          dev_priv->max_cdclk_freq);
5363
5364         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5365                          dev_priv->max_dotclk_freq);
5366 }
5367
5368 static void intel_update_cdclk(struct drm_device *dev)
5369 {
5370         struct drm_i915_private *dev_priv = dev->dev_private;
5371
5372         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5373         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5374                          dev_priv->cdclk_freq);
5375
5376         /*
5377          * Program the gmbus_freq based on the cdclk frequency.
5378          * BSpec erroneously claims we should aim for 4MHz, but
5379          * in fact 1MHz is the correct frequency.
5380          */
5381         if (IS_VALLEYVIEW(dev)) {
5382                 /*
5383                  * Program the gmbus_freq based on the cdclk frequency.
5384                  * BSpec erroneously claims we should aim for 4MHz, but
5385                  * in fact 1MHz is the correct frequency.
5386                  */
5387                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5388         }
5389
5390         if (dev_priv->max_cdclk_freq == 0)
5391                 intel_update_max_cdclk(dev);
5392 }
5393
5394 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5395 {
5396         struct drm_i915_private *dev_priv = dev->dev_private;
5397         uint32_t divider;
5398         uint32_t ratio;
5399         uint32_t current_freq;
5400         int ret;
5401
5402         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5403         switch (frequency) {
5404         case 144000:
5405                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5406                 ratio = BXT_DE_PLL_RATIO(60);
5407                 break;
5408         case 288000:
5409                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5410                 ratio = BXT_DE_PLL_RATIO(60);
5411                 break;
5412         case 384000:
5413                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5414                 ratio = BXT_DE_PLL_RATIO(60);
5415                 break;
5416         case 576000:
5417                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5418                 ratio = BXT_DE_PLL_RATIO(60);
5419                 break;
5420         case 624000:
5421                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5422                 ratio = BXT_DE_PLL_RATIO(65);
5423                 break;
5424         case 19200:
5425                 /*
5426                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5427                  * to suppress GCC warning.
5428                  */
5429                 ratio = 0;
5430                 divider = 0;
5431                 break;
5432         default:
5433                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5434
5435                 return;
5436         }
5437
5438         mutex_lock(&dev_priv->rps.hw_lock);
5439         /* Inform power controller of upcoming frequency change */
5440         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5441                                       0x80000000);
5442         mutex_unlock(&dev_priv->rps.hw_lock);
5443
5444         if (ret) {
5445                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5446                           ret, frequency);
5447                 return;
5448         }
5449
5450         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5451         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5452         current_freq = current_freq * 500 + 1000;
5453
5454         /*
5455          * DE PLL has to be disabled when
5456          * - setting to 19.2MHz (bypass, PLL isn't used)
5457          * - before setting to 624MHz (PLL needs toggling)
5458          * - before setting to any frequency from 624MHz (PLL needs toggling)
5459          */
5460         if (frequency == 19200 || frequency == 624000 ||
5461             current_freq == 624000) {
5462                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5463                 /* Timeout 200us */
5464                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5465                              1))
5466                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5467         }
5468
5469         if (frequency != 19200) {
5470                 uint32_t val;
5471
5472                 val = I915_READ(BXT_DE_PLL_CTL);
5473                 val &= ~BXT_DE_PLL_RATIO_MASK;
5474                 val |= ratio;
5475                 I915_WRITE(BXT_DE_PLL_CTL, val);
5476
5477                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5478                 /* Timeout 200us */
5479                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5480                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5481
5482                 val = I915_READ(CDCLK_CTL);
5483                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5484                 val |= divider;
5485                 /*
5486                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5487                  * enable otherwise.
5488                  */
5489                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5490                 if (frequency >= 500000)
5491                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5492
5493                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5494                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5495                 val |= (frequency - 1000) / 500;
5496                 I915_WRITE(CDCLK_CTL, val);
5497         }
5498
5499         mutex_lock(&dev_priv->rps.hw_lock);
5500         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5501                                       DIV_ROUND_UP(frequency, 25000));
5502         mutex_unlock(&dev_priv->rps.hw_lock);
5503
5504         if (ret) {
5505                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5506                           ret, frequency);
5507                 return;
5508         }
5509
5510         intel_update_cdclk(dev);
5511 }
5512
5513 void broxton_init_cdclk(struct drm_device *dev)
5514 {
5515         struct drm_i915_private *dev_priv = dev->dev_private;
5516         uint32_t val;
5517
5518         /*
5519          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5520          * or else the reset will hang because there is no PCH to respond.
5521          * Move the handshake programming to initialization sequence.
5522          * Previously was left up to BIOS.
5523          */
5524         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5525         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5526         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5527
5528         /* Enable PG1 for cdclk */
5529         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5530
5531         /* check if cd clock is enabled */
5532         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5533                 DRM_DEBUG_KMS("Display already initialized\n");
5534                 return;
5535         }
5536
5537         /*
5538          * FIXME:
5539          * - The initial CDCLK needs to be read from VBT.
5540          *   Need to make this change after VBT has changes for BXT.
5541          * - check if setting the max (or any) cdclk freq is really necessary
5542          *   here, it belongs to modeset time
5543          */
5544         broxton_set_cdclk(dev, 624000);
5545
5546         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5547         POSTING_READ(DBUF_CTL);
5548
5549         udelay(10);
5550
5551         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5552                 DRM_ERROR("DBuf power enable timeout!\n");
5553 }
5554
5555 void broxton_uninit_cdclk(struct drm_device *dev)
5556 {
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558
5559         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5560         POSTING_READ(DBUF_CTL);
5561
5562         udelay(10);
5563
5564         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5565                 DRM_ERROR("DBuf power disable timeout!\n");
5566
5567         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5568         broxton_set_cdclk(dev, 19200);
5569
5570         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5571 }
5572
5573 static const struct skl_cdclk_entry {
5574         unsigned int freq;
5575         unsigned int vco;
5576 } skl_cdclk_frequencies[] = {
5577         { .freq = 308570, .vco = 8640 },
5578         { .freq = 337500, .vco = 8100 },
5579         { .freq = 432000, .vco = 8640 },
5580         { .freq = 450000, .vco = 8100 },
5581         { .freq = 540000, .vco = 8100 },
5582         { .freq = 617140, .vco = 8640 },
5583         { .freq = 675000, .vco = 8100 },
5584 };
5585
5586 static unsigned int skl_cdclk_decimal(unsigned int freq)
5587 {
5588         return (freq - 1000) / 500;
5589 }
5590
5591 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5592 {
5593         unsigned int i;
5594
5595         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5596                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5597
5598                 if (e->freq == freq)
5599                         return e->vco;
5600         }
5601
5602         return 8100;
5603 }
5604
5605 static void
5606 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5607 {
5608         unsigned int min_freq;
5609         u32 val;
5610
5611         /* select the minimum CDCLK before enabling DPLL 0 */
5612         val = I915_READ(CDCLK_CTL);
5613         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5614         val |= CDCLK_FREQ_337_308;
5615
5616         if (required_vco == 8640)
5617                 min_freq = 308570;
5618         else
5619                 min_freq = 337500;
5620
5621         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5622
5623         I915_WRITE(CDCLK_CTL, val);
5624         POSTING_READ(CDCLK_CTL);
5625
5626         /*
5627          * We always enable DPLL0 with the lowest link rate possible, but still
5628          * taking into account the VCO required to operate the eDP panel at the
5629          * desired frequency. The usual DP link rates operate with a VCO of
5630          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5631          * The modeset code is responsible for the selection of the exact link
5632          * rate later on, with the constraint of choosing a frequency that
5633          * works with required_vco.
5634          */
5635         val = I915_READ(DPLL_CTRL1);
5636
5637         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5638                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5639         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5640         if (required_vco == 8640)
5641                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5642                                             SKL_DPLL0);
5643         else
5644                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5645                                             SKL_DPLL0);
5646
5647         I915_WRITE(DPLL_CTRL1, val);
5648         POSTING_READ(DPLL_CTRL1);
5649
5650         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5651
5652         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5653                 DRM_ERROR("DPLL0 not locked\n");
5654 }
5655
5656 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5657 {
5658         int ret;
5659         u32 val;
5660
5661         /* inform PCU we want to change CDCLK */
5662         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5663         mutex_lock(&dev_priv->rps.hw_lock);
5664         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5665         mutex_unlock(&dev_priv->rps.hw_lock);
5666
5667         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5668 }
5669
5670 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5671 {
5672         unsigned int i;
5673
5674         for (i = 0; i < 15; i++) {
5675                 if (skl_cdclk_pcu_ready(dev_priv))
5676                         return true;
5677                 udelay(10);
5678         }
5679
5680         return false;
5681 }
5682
5683 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5684 {
5685         struct drm_device *dev = dev_priv->dev;
5686         u32 freq_select, pcu_ack;
5687
5688         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5689
5690         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5691                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5692                 return;
5693         }
5694
5695         /* set CDCLK_CTL */
5696         switch(freq) {
5697         case 450000:
5698         case 432000:
5699                 freq_select = CDCLK_FREQ_450_432;
5700                 pcu_ack = 1;
5701                 break;
5702         case 540000:
5703                 freq_select = CDCLK_FREQ_540;
5704                 pcu_ack = 2;
5705                 break;
5706         case 308570:
5707         case 337500:
5708         default:
5709                 freq_select = CDCLK_FREQ_337_308;
5710                 pcu_ack = 0;
5711                 break;
5712         case 617140:
5713         case 675000:
5714                 freq_select = CDCLK_FREQ_675_617;
5715                 pcu_ack = 3;
5716                 break;
5717         }
5718
5719         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5720         POSTING_READ(CDCLK_CTL);
5721
5722         /* inform PCU of the change */
5723         mutex_lock(&dev_priv->rps.hw_lock);
5724         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5725         mutex_unlock(&dev_priv->rps.hw_lock);
5726
5727         intel_update_cdclk(dev);
5728 }
5729
5730 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5731 {
5732         /* disable DBUF power */
5733         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5734         POSTING_READ(DBUF_CTL);
5735
5736         udelay(10);
5737
5738         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5739                 DRM_ERROR("DBuf power disable timeout\n");
5740
5741         /*
5742          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5743          */
5744         if (dev_priv->csr.dmc_payload) {
5745                 /* disable DPLL0 */
5746                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5747                                         ~LCPLL_PLL_ENABLE);
5748                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5749                         DRM_ERROR("Couldn't disable DPLL0\n");
5750         }
5751
5752         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5753 }
5754
5755 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5756 {
5757         u32 val;
5758         unsigned int required_vco;
5759
5760         /* enable PCH reset handshake */
5761         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5762         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5763
5764         /* enable PG1 and Misc I/O */
5765         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5766
5767         /* DPLL0 not enabled (happens on early BIOS versions) */
5768         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5769                 /* enable DPLL0 */
5770                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5771                 skl_dpll0_enable(dev_priv, required_vco);
5772         }
5773
5774         /* set CDCLK to the frequency the BIOS chose */
5775         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5776
5777         /* enable DBUF power */
5778         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5779         POSTING_READ(DBUF_CTL);
5780
5781         udelay(10);
5782
5783         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5784                 DRM_ERROR("DBuf power enable timeout\n");
5785 }
5786
5787 /* Adjust CDclk dividers to allow high res or save power if possible */
5788 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5789 {
5790         struct drm_i915_private *dev_priv = dev->dev_private;
5791         u32 val, cmd;
5792
5793         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5794                                         != dev_priv->cdclk_freq);
5795
5796         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5797                 cmd = 2;
5798         else if (cdclk == 266667)
5799                 cmd = 1;
5800         else
5801                 cmd = 0;
5802
5803         mutex_lock(&dev_priv->rps.hw_lock);
5804         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5805         val &= ~DSPFREQGUAR_MASK;
5806         val |= (cmd << DSPFREQGUAR_SHIFT);
5807         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5808         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5809                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5810                      50)) {
5811                 DRM_ERROR("timed out waiting for CDclk change\n");
5812         }
5813         mutex_unlock(&dev_priv->rps.hw_lock);
5814
5815         mutex_lock(&dev_priv->sb_lock);
5816
5817         if (cdclk == 400000) {
5818                 u32 divider;
5819
5820                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5821
5822                 /* adjust cdclk divider */
5823                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5824                 val &= ~CCK_FREQUENCY_VALUES;
5825                 val |= divider;
5826                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5827
5828                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5829                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5830                              50))
5831                         DRM_ERROR("timed out waiting for CDclk change\n");
5832         }
5833
5834         /* adjust self-refresh exit latency value */
5835         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5836         val &= ~0x7f;
5837
5838         /*
5839          * For high bandwidth configs, we set a higher latency in the bunit
5840          * so that the core display fetch happens in time to avoid underruns.
5841          */
5842         if (cdclk == 400000)
5843                 val |= 4500 / 250; /* 4.5 usec */
5844         else
5845                 val |= 3000 / 250; /* 3.0 usec */
5846         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5847
5848         mutex_unlock(&dev_priv->sb_lock);
5849
5850         intel_update_cdclk(dev);
5851 }
5852
5853 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5854 {
5855         struct drm_i915_private *dev_priv = dev->dev_private;
5856         u32 val, cmd;
5857
5858         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5859                                                 != dev_priv->cdclk_freq);
5860
5861         switch (cdclk) {
5862         case 333333:
5863         case 320000:
5864         case 266667:
5865         case 200000:
5866                 break;
5867         default:
5868                 MISSING_CASE(cdclk);
5869                 return;
5870         }
5871
5872         /*
5873          * Specs are full of misinformation, but testing on actual
5874          * hardware has shown that we just need to write the desired
5875          * CCK divider into the Punit register.
5876          */
5877         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5878
5879         mutex_lock(&dev_priv->rps.hw_lock);
5880         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5881         val &= ~DSPFREQGUAR_MASK_CHV;
5882         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5883         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5884         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5885                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5886                      50)) {
5887                 DRM_ERROR("timed out waiting for CDclk change\n");
5888         }
5889         mutex_unlock(&dev_priv->rps.hw_lock);
5890
5891         intel_update_cdclk(dev);
5892 }
5893
5894 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5895                                  int max_pixclk)
5896 {
5897         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5898         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5899
5900         /*
5901          * Really only a few cases to deal with, as only 4 CDclks are supported:
5902          *   200MHz
5903          *   267MHz
5904          *   320/333MHz (depends on HPLL freq)
5905          *   400MHz (VLV only)
5906          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5907          * of the lower bin and adjust if needed.
5908          *
5909          * We seem to get an unstable or solid color picture at 200MHz.
5910          * Not sure what's wrong. For now use 200MHz only when all pipes
5911          * are off.
5912          */
5913         if (!IS_CHERRYVIEW(dev_priv) &&
5914             max_pixclk > freq_320*limit/100)
5915                 return 400000;
5916         else if (max_pixclk > 266667*limit/100)
5917                 return freq_320;
5918         else if (max_pixclk > 0)
5919                 return 266667;
5920         else
5921                 return 200000;
5922 }
5923
5924 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5925                               int max_pixclk)
5926 {
5927         /*
5928          * FIXME:
5929          * - remove the guardband, it's not needed on BXT
5930          * - set 19.2MHz bypass frequency if there are no active pipes
5931          */
5932         if (max_pixclk > 576000*9/10)
5933                 return 624000;
5934         else if (max_pixclk > 384000*9/10)
5935                 return 576000;
5936         else if (max_pixclk > 288000*9/10)
5937                 return 384000;
5938         else if (max_pixclk > 144000*9/10)
5939                 return 288000;
5940         else
5941                 return 144000;
5942 }
5943
5944 /* Compute the max pixel clock for new configuration. Uses atomic state if
5945  * that's non-NULL, look at current state otherwise. */
5946 static int intel_mode_max_pixclk(struct drm_device *dev,
5947                                  struct drm_atomic_state *state)
5948 {
5949         struct intel_crtc *intel_crtc;
5950         struct intel_crtc_state *crtc_state;
5951         int max_pixclk = 0;
5952
5953         for_each_intel_crtc(dev, intel_crtc) {
5954                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5955                 if (IS_ERR(crtc_state))
5956                         return PTR_ERR(crtc_state);
5957
5958                 if (!crtc_state->base.enable)
5959                         continue;
5960
5961                 max_pixclk = max(max_pixclk,
5962                                  crtc_state->base.adjusted_mode.crtc_clock);
5963         }
5964
5965         return max_pixclk;
5966 }
5967
5968 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5969 {
5970         struct drm_device *dev = state->dev;
5971         struct drm_i915_private *dev_priv = dev->dev_private;
5972         int max_pixclk = intel_mode_max_pixclk(dev, state);
5973
5974         if (max_pixclk < 0)
5975                 return max_pixclk;
5976
5977         to_intel_atomic_state(state)->cdclk =
5978                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5979
5980         return 0;
5981 }
5982
5983 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5984 {
5985         struct drm_device *dev = state->dev;
5986         struct drm_i915_private *dev_priv = dev->dev_private;
5987         int max_pixclk = intel_mode_max_pixclk(dev, state);
5988
5989         if (max_pixclk < 0)
5990                 return max_pixclk;
5991
5992         to_intel_atomic_state(state)->cdclk =
5993                 broxton_calc_cdclk(dev_priv, max_pixclk);
5994
5995         return 0;
5996 }
5997
5998 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5999 {
6000         unsigned int credits, default_credits;
6001
6002         if (IS_CHERRYVIEW(dev_priv))
6003                 default_credits = PFI_CREDIT(12);
6004         else
6005                 default_credits = PFI_CREDIT(8);
6006
6007         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6008                 /* CHV suggested value is 31 or 63 */
6009                 if (IS_CHERRYVIEW(dev_priv))
6010                         credits = PFI_CREDIT_63;
6011                 else
6012                         credits = PFI_CREDIT(15);
6013         } else {
6014                 credits = default_credits;
6015         }
6016
6017         /*
6018          * WA - write default credits before re-programming
6019          * FIXME: should we also set the resend bit here?
6020          */
6021         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6022                    default_credits);
6023
6024         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6025                    credits | PFI_CREDIT_RESEND);
6026
6027         /*
6028          * FIXME is this guaranteed to clear
6029          * immediately or should we poll for it?
6030          */
6031         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6032 }
6033
6034 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6035 {
6036         struct drm_device *dev = old_state->dev;
6037         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6038         struct drm_i915_private *dev_priv = dev->dev_private;
6039
6040         /*
6041          * FIXME: We can end up here with all power domains off, yet
6042          * with a CDCLK frequency other than the minimum. To account
6043          * for this take the PIPE-A power domain, which covers the HW
6044          * blocks needed for the following programming. This can be
6045          * removed once it's guaranteed that we get here either with
6046          * the minimum CDCLK set, or the required power domains
6047          * enabled.
6048          */
6049         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6050
6051         if (IS_CHERRYVIEW(dev))
6052                 cherryview_set_cdclk(dev, req_cdclk);
6053         else
6054                 valleyview_set_cdclk(dev, req_cdclk);
6055
6056         vlv_program_pfi_credits(dev_priv);
6057
6058         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6059 }
6060
6061 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6062 {
6063         struct drm_device *dev = crtc->dev;
6064         struct drm_i915_private *dev_priv = to_i915(dev);
6065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6066         struct intel_encoder *encoder;
6067         int pipe = intel_crtc->pipe;
6068         bool is_dsi;
6069
6070         if (WARN_ON(intel_crtc->active))
6071                 return;
6072
6073         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6074
6075         if (intel_crtc->config->has_dp_encoder)
6076                 intel_dp_set_m_n(intel_crtc, M1_N1);
6077
6078         intel_set_pipe_timings(intel_crtc);
6079
6080         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6081                 struct drm_i915_private *dev_priv = dev->dev_private;
6082
6083                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6084                 I915_WRITE(CHV_CANVAS(pipe), 0);
6085         }
6086
6087         i9xx_set_pipeconf(intel_crtc);
6088
6089         intel_crtc->active = true;
6090
6091         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6092
6093         for_each_encoder_on_crtc(dev, crtc, encoder)
6094                 if (encoder->pre_pll_enable)
6095                         encoder->pre_pll_enable(encoder);
6096
6097         if (!is_dsi) {
6098                 if (IS_CHERRYVIEW(dev)) {
6099                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6100                         chv_enable_pll(intel_crtc, intel_crtc->config);
6101                 } else {
6102                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6103                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6104                 }
6105         }
6106
6107         for_each_encoder_on_crtc(dev, crtc, encoder)
6108                 if (encoder->pre_enable)
6109                         encoder->pre_enable(encoder);
6110
6111         i9xx_pfit_enable(intel_crtc);
6112
6113         intel_crtc_load_lut(crtc);
6114
6115         intel_enable_pipe(intel_crtc);
6116
6117         assert_vblank_disabled(crtc);
6118         drm_crtc_vblank_on(crtc);
6119
6120         for_each_encoder_on_crtc(dev, crtc, encoder)
6121                 encoder->enable(encoder);
6122 }
6123
6124 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6125 {
6126         struct drm_device *dev = crtc->base.dev;
6127         struct drm_i915_private *dev_priv = dev->dev_private;
6128
6129         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6130         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6131 }
6132
6133 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6134 {
6135         struct drm_device *dev = crtc->dev;
6136         struct drm_i915_private *dev_priv = to_i915(dev);
6137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6138         struct intel_encoder *encoder;
6139         int pipe = intel_crtc->pipe;
6140
6141         if (WARN_ON(intel_crtc->active))
6142                 return;
6143
6144         i9xx_set_pll_dividers(intel_crtc);
6145
6146         if (intel_crtc->config->has_dp_encoder)
6147                 intel_dp_set_m_n(intel_crtc, M1_N1);
6148
6149         intel_set_pipe_timings(intel_crtc);
6150
6151         i9xx_set_pipeconf(intel_crtc);
6152
6153         intel_crtc->active = true;
6154
6155         if (!IS_GEN2(dev))
6156                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6157
6158         for_each_encoder_on_crtc(dev, crtc, encoder)
6159                 if (encoder->pre_enable)
6160                         encoder->pre_enable(encoder);
6161
6162         i9xx_enable_pll(intel_crtc);
6163
6164         i9xx_pfit_enable(intel_crtc);
6165
6166         intel_crtc_load_lut(crtc);
6167
6168         intel_update_watermarks(crtc);
6169         intel_enable_pipe(intel_crtc);
6170
6171         assert_vblank_disabled(crtc);
6172         drm_crtc_vblank_on(crtc);
6173
6174         for_each_encoder_on_crtc(dev, crtc, encoder)
6175                 encoder->enable(encoder);
6176 }
6177
6178 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6179 {
6180         struct drm_device *dev = crtc->base.dev;
6181         struct drm_i915_private *dev_priv = dev->dev_private;
6182
6183         if (!crtc->config->gmch_pfit.control)
6184                 return;
6185
6186         assert_pipe_disabled(dev_priv, crtc->pipe);
6187
6188         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6189                          I915_READ(PFIT_CONTROL));
6190         I915_WRITE(PFIT_CONTROL, 0);
6191 }
6192
6193 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6194 {
6195         struct drm_device *dev = crtc->dev;
6196         struct drm_i915_private *dev_priv = dev->dev_private;
6197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6198         struct intel_encoder *encoder;
6199         int pipe = intel_crtc->pipe;
6200
6201         /*
6202          * On gen2 planes are double buffered but the pipe isn't, so we must
6203          * wait for planes to fully turn off before disabling the pipe.
6204          * We also need to wait on all gmch platforms because of the
6205          * self-refresh mode constraint explained above.
6206          */
6207         intel_wait_for_vblank(dev, pipe);
6208
6209         for_each_encoder_on_crtc(dev, crtc, encoder)
6210                 encoder->disable(encoder);
6211
6212         drm_crtc_vblank_off(crtc);
6213         assert_vblank_disabled(crtc);
6214
6215         intel_disable_pipe(intel_crtc);
6216
6217         i9xx_pfit_disable(intel_crtc);
6218
6219         for_each_encoder_on_crtc(dev, crtc, encoder)
6220                 if (encoder->post_disable)
6221                         encoder->post_disable(encoder);
6222
6223         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6224                 if (IS_CHERRYVIEW(dev))
6225                         chv_disable_pll(dev_priv, pipe);
6226                 else if (IS_VALLEYVIEW(dev))
6227                         vlv_disable_pll(dev_priv, pipe);
6228                 else
6229                         i9xx_disable_pll(intel_crtc);
6230         }
6231
6232         for_each_encoder_on_crtc(dev, crtc, encoder)
6233                 if (encoder->post_pll_disable)
6234                         encoder->post_pll_disable(encoder);
6235
6236         if (!IS_GEN2(dev))
6237                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6238 }
6239
6240 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6241 {
6242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6243         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6244         enum intel_display_power_domain domain;
6245         unsigned long domains;
6246
6247         if (!intel_crtc->active)
6248                 return;
6249
6250         if (to_intel_plane_state(crtc->primary->state)->visible) {
6251                 intel_crtc_wait_for_pending_flips(crtc);
6252                 intel_pre_disable_primary(crtc);
6253         }
6254
6255         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6256         dev_priv->display.crtc_disable(crtc);
6257         intel_crtc->active = false;
6258         intel_update_watermarks(crtc);
6259         intel_disable_shared_dpll(intel_crtc);
6260
6261         domains = intel_crtc->enabled_power_domains;
6262         for_each_power_domain(domain, domains)
6263                 intel_display_power_put(dev_priv, domain);
6264         intel_crtc->enabled_power_domains = 0;
6265 }
6266
6267 /*
6268  * turn all crtc's off, but do not adjust state
6269  * This has to be paired with a call to intel_modeset_setup_hw_state.
6270  */
6271 int intel_display_suspend(struct drm_device *dev)
6272 {
6273         struct drm_mode_config *config = &dev->mode_config;
6274         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6275         struct drm_atomic_state *state;
6276         struct drm_crtc *crtc;
6277         unsigned crtc_mask = 0;
6278         int ret = 0;
6279
6280         if (WARN_ON(!ctx))
6281                 return 0;
6282
6283         lockdep_assert_held(&ctx->ww_ctx);
6284         state = drm_atomic_state_alloc(dev);
6285         if (WARN_ON(!state))
6286                 return -ENOMEM;
6287
6288         state->acquire_ctx = ctx;
6289         state->allow_modeset = true;
6290
6291         for_each_crtc(dev, crtc) {
6292                 struct drm_crtc_state *crtc_state =
6293                         drm_atomic_get_crtc_state(state, crtc);
6294
6295                 ret = PTR_ERR_OR_ZERO(crtc_state);
6296                 if (ret)
6297                         goto free;
6298
6299                 if (!crtc_state->active)
6300                         continue;
6301
6302                 crtc_state->active = false;
6303                 crtc_mask |= 1 << drm_crtc_index(crtc);
6304         }
6305
6306         if (crtc_mask) {
6307                 ret = drm_atomic_commit(state);
6308
6309                 if (!ret) {
6310                         for_each_crtc(dev, crtc)
6311                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6312                                         crtc->state->active = true;
6313
6314                         return ret;
6315                 }
6316         }
6317
6318 free:
6319         if (ret)
6320                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6321         drm_atomic_state_free(state);
6322         return ret;
6323 }
6324
6325 void intel_encoder_destroy(struct drm_encoder *encoder)
6326 {
6327         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6328
6329         drm_encoder_cleanup(encoder);
6330         kfree(intel_encoder);
6331 }
6332
6333 /* Cross check the actual hw state with our own modeset state tracking (and it's
6334  * internal consistency). */
6335 static void intel_connector_check_state(struct intel_connector *connector)
6336 {
6337         struct drm_crtc *crtc = connector->base.state->crtc;
6338
6339         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6340                       connector->base.base.id,
6341                       connector->base.name);
6342
6343         if (connector->get_hw_state(connector)) {
6344                 struct intel_encoder *encoder = connector->encoder;
6345                 struct drm_connector_state *conn_state = connector->base.state;
6346
6347                 I915_STATE_WARN(!crtc,
6348                          "connector enabled without attached crtc\n");
6349
6350                 if (!crtc)
6351                         return;
6352
6353                 I915_STATE_WARN(!crtc->state->active,
6354                       "connector is active, but attached crtc isn't\n");
6355
6356                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6357                         return;
6358
6359                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6360                         "atomic encoder doesn't match attached encoder\n");
6361
6362                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6363                         "attached encoder crtc differs from connector crtc\n");
6364         } else {
6365                 I915_STATE_WARN(crtc && crtc->state->active,
6366                         "attached crtc is active, but connector isn't\n");
6367                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6368                         "best encoder set without crtc!\n");
6369         }
6370 }
6371
6372 int intel_connector_init(struct intel_connector *connector)
6373 {
6374         struct drm_connector_state *connector_state;
6375
6376         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6377         if (!connector_state)
6378                 return -ENOMEM;
6379
6380         connector->base.state = connector_state;
6381         return 0;
6382 }
6383
6384 struct intel_connector *intel_connector_alloc(void)
6385 {
6386         struct intel_connector *connector;
6387
6388         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6389         if (!connector)
6390                 return NULL;
6391
6392         if (intel_connector_init(connector) < 0) {
6393                 kfree(connector);
6394                 return NULL;
6395         }
6396
6397         return connector;
6398 }
6399
6400 /* Simple connector->get_hw_state implementation for encoders that support only
6401  * one connector and no cloning and hence the encoder state determines the state
6402  * of the connector. */
6403 bool intel_connector_get_hw_state(struct intel_connector *connector)
6404 {
6405         enum pipe pipe = 0;
6406         struct intel_encoder *encoder = connector->encoder;
6407
6408         return encoder->get_hw_state(encoder, &pipe);
6409 }
6410
6411 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6412 {
6413         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6414                 return crtc_state->fdi_lanes;
6415
6416         return 0;
6417 }
6418
6419 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6420                                      struct intel_crtc_state *pipe_config)
6421 {
6422         struct drm_atomic_state *state = pipe_config->base.state;
6423         struct intel_crtc *other_crtc;
6424         struct intel_crtc_state *other_crtc_state;
6425
6426         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6427                       pipe_name(pipe), pipe_config->fdi_lanes);
6428         if (pipe_config->fdi_lanes > 4) {
6429                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6430                               pipe_name(pipe), pipe_config->fdi_lanes);
6431                 return -EINVAL;
6432         }
6433
6434         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6435                 if (pipe_config->fdi_lanes > 2) {
6436                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6437                                       pipe_config->fdi_lanes);
6438                         return -EINVAL;
6439                 } else {
6440                         return 0;
6441                 }
6442         }
6443
6444         if (INTEL_INFO(dev)->num_pipes == 2)
6445                 return 0;
6446
6447         /* Ivybridge 3 pipe is really complicated */
6448         switch (pipe) {
6449         case PIPE_A:
6450                 return 0;
6451         case PIPE_B:
6452                 if (pipe_config->fdi_lanes <= 2)
6453                         return 0;
6454
6455                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6456                 other_crtc_state =
6457                         intel_atomic_get_crtc_state(state, other_crtc);
6458                 if (IS_ERR(other_crtc_state))
6459                         return PTR_ERR(other_crtc_state);
6460
6461                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6462                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6463                                       pipe_name(pipe), pipe_config->fdi_lanes);
6464                         return -EINVAL;
6465                 }
6466                 return 0;
6467         case PIPE_C:
6468                 if (pipe_config->fdi_lanes > 2) {
6469                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6470                                       pipe_name(pipe), pipe_config->fdi_lanes);
6471                         return -EINVAL;
6472                 }
6473
6474                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6475                 other_crtc_state =
6476                         intel_atomic_get_crtc_state(state, other_crtc);
6477                 if (IS_ERR(other_crtc_state))
6478                         return PTR_ERR(other_crtc_state);
6479
6480                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6481                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6482                         return -EINVAL;
6483                 }
6484                 return 0;
6485         default:
6486                 BUG();
6487         }
6488 }
6489
6490 #define RETRY 1
6491 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6492                                        struct intel_crtc_state *pipe_config)
6493 {
6494         struct drm_device *dev = intel_crtc->base.dev;
6495         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6496         int lane, link_bw, fdi_dotclock, ret;
6497         bool needs_recompute = false;
6498
6499 retry:
6500         /* FDI is a binary signal running at ~2.7GHz, encoding
6501          * each output octet as 10 bits. The actual frequency
6502          * is stored as a divider into a 100MHz clock, and the
6503          * mode pixel clock is stored in units of 1KHz.
6504          * Hence the bw of each lane in terms of the mode signal
6505          * is:
6506          */
6507         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6508
6509         fdi_dotclock = adjusted_mode->crtc_clock;
6510
6511         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6512                                            pipe_config->pipe_bpp);
6513
6514         pipe_config->fdi_lanes = lane;
6515
6516         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6517                                link_bw, &pipe_config->fdi_m_n);
6518
6519         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6520                                        intel_crtc->pipe, pipe_config);
6521         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6522                 pipe_config->pipe_bpp -= 2*3;
6523                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6524                               pipe_config->pipe_bpp);
6525                 needs_recompute = true;
6526                 pipe_config->bw_constrained = true;
6527
6528                 goto retry;
6529         }
6530
6531         if (needs_recompute)
6532                 return RETRY;
6533
6534         return ret;
6535 }
6536
6537 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6538                                      struct intel_crtc_state *pipe_config)
6539 {
6540         if (pipe_config->pipe_bpp > 24)
6541                 return false;
6542
6543         /* HSW can handle pixel rate up to cdclk? */
6544         if (IS_HASWELL(dev_priv->dev))
6545                 return true;
6546
6547         /*
6548          * We compare against max which means we must take
6549          * the increased cdclk requirement into account when
6550          * calculating the new cdclk.
6551          *
6552          * Should measure whether using a lower cdclk w/o IPS
6553          */
6554         return ilk_pipe_pixel_rate(pipe_config) <=
6555                 dev_priv->max_cdclk_freq * 95 / 100;
6556 }
6557
6558 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6559                                    struct intel_crtc_state *pipe_config)
6560 {
6561         struct drm_device *dev = crtc->base.dev;
6562         struct drm_i915_private *dev_priv = dev->dev_private;
6563
6564         pipe_config->ips_enabled = i915.enable_ips &&
6565                 hsw_crtc_supports_ips(crtc) &&
6566                 pipe_config_supports_ips(dev_priv, pipe_config);
6567 }
6568
6569 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6570                                      struct intel_crtc_state *pipe_config)
6571 {
6572         struct drm_device *dev = crtc->base.dev;
6573         struct drm_i915_private *dev_priv = dev->dev_private;
6574         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6575
6576         /* FIXME should check pixel clock limits on all platforms */
6577         if (INTEL_INFO(dev)->gen < 4) {
6578                 int clock_limit = dev_priv->max_cdclk_freq;
6579
6580                 /*
6581                  * Enable pixel doubling when the dot clock
6582                  * is > 90% of the (display) core speed.
6583                  *
6584                  * GDG double wide on either pipe,
6585                  * otherwise pipe A only.
6586                  */
6587                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6588                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6589                         clock_limit *= 2;
6590                         pipe_config->double_wide = true;
6591                 }
6592
6593                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6594                         return -EINVAL;
6595         }
6596
6597         /*
6598          * Pipe horizontal size must be even in:
6599          * - DVO ganged mode
6600          * - LVDS dual channel mode
6601          * - Double wide pipe
6602          */
6603         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6604              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6605                 pipe_config->pipe_src_w &= ~1;
6606
6607         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6608          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6609          */
6610         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6611                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6612                 return -EINVAL;
6613
6614         if (HAS_IPS(dev))
6615                 hsw_compute_ips_config(crtc, pipe_config);
6616
6617         if (pipe_config->has_pch_encoder)
6618                 return ironlake_fdi_compute_config(crtc, pipe_config);
6619
6620         return 0;
6621 }
6622
6623 static int skylake_get_display_clock_speed(struct drm_device *dev)
6624 {
6625         struct drm_i915_private *dev_priv = to_i915(dev);
6626         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6627         uint32_t cdctl = I915_READ(CDCLK_CTL);
6628         uint32_t linkrate;
6629
6630         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6631                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6632
6633         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6634                 return 540000;
6635
6636         linkrate = (I915_READ(DPLL_CTRL1) &
6637                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6638
6639         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6640             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6641                 /* vco 8640 */
6642                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6643                 case CDCLK_FREQ_450_432:
6644                         return 432000;
6645                 case CDCLK_FREQ_337_308:
6646                         return 308570;
6647                 case CDCLK_FREQ_675_617:
6648                         return 617140;
6649                 default:
6650                         WARN(1, "Unknown cd freq selection\n");
6651                 }
6652         } else {
6653                 /* vco 8100 */
6654                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6655                 case CDCLK_FREQ_450_432:
6656                         return 450000;
6657                 case CDCLK_FREQ_337_308:
6658                         return 337500;
6659                 case CDCLK_FREQ_675_617:
6660                         return 675000;
6661                 default:
6662                         WARN(1, "Unknown cd freq selection\n");
6663                 }
6664         }
6665
6666         /* error case, do as if DPLL0 isn't enabled */
6667         return 24000;
6668 }
6669
6670 static int broxton_get_display_clock_speed(struct drm_device *dev)
6671 {
6672         struct drm_i915_private *dev_priv = to_i915(dev);
6673         uint32_t cdctl = I915_READ(CDCLK_CTL);
6674         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6675         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6676         int cdclk;
6677
6678         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6679                 return 19200;
6680
6681         cdclk = 19200 * pll_ratio / 2;
6682
6683         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6684         case BXT_CDCLK_CD2X_DIV_SEL_1:
6685                 return cdclk;  /* 576MHz or 624MHz */
6686         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6687                 return cdclk * 2 / 3; /* 384MHz */
6688         case BXT_CDCLK_CD2X_DIV_SEL_2:
6689                 return cdclk / 2; /* 288MHz */
6690         case BXT_CDCLK_CD2X_DIV_SEL_4:
6691                 return cdclk / 4; /* 144MHz */
6692         }
6693
6694         /* error case, do as if DE PLL isn't enabled */
6695         return 19200;
6696 }
6697
6698 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6699 {
6700         struct drm_i915_private *dev_priv = dev->dev_private;
6701         uint32_t lcpll = I915_READ(LCPLL_CTL);
6702         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6703
6704         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6705                 return 800000;
6706         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6707                 return 450000;
6708         else if (freq == LCPLL_CLK_FREQ_450)
6709                 return 450000;
6710         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6711                 return 540000;
6712         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6713                 return 337500;
6714         else
6715                 return 675000;
6716 }
6717
6718 static int haswell_get_display_clock_speed(struct drm_device *dev)
6719 {
6720         struct drm_i915_private *dev_priv = dev->dev_private;
6721         uint32_t lcpll = I915_READ(LCPLL_CTL);
6722         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6723
6724         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6725                 return 800000;
6726         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6727                 return 450000;
6728         else if (freq == LCPLL_CLK_FREQ_450)
6729                 return 450000;
6730         else if (IS_HSW_ULT(dev))
6731                 return 337500;
6732         else
6733                 return 540000;
6734 }
6735
6736 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6737 {
6738         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6739                                       CCK_DISPLAY_CLOCK_CONTROL);
6740 }
6741
6742 static int ilk_get_display_clock_speed(struct drm_device *dev)
6743 {
6744         return 450000;
6745 }
6746
6747 static int i945_get_display_clock_speed(struct drm_device *dev)
6748 {
6749         return 400000;
6750 }
6751
6752 static int i915_get_display_clock_speed(struct drm_device *dev)
6753 {
6754         return 333333;
6755 }
6756
6757 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6758 {
6759         return 200000;
6760 }
6761
6762 static int pnv_get_display_clock_speed(struct drm_device *dev)
6763 {
6764         u16 gcfgc = 0;
6765
6766         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6767
6768         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6769         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6770                 return 266667;
6771         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6772                 return 333333;
6773         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6774                 return 444444;
6775         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6776                 return 200000;
6777         default:
6778                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6779         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6780                 return 133333;
6781         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6782                 return 166667;
6783         }
6784 }
6785
6786 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6787 {
6788         u16 gcfgc = 0;
6789
6790         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6791
6792         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6793                 return 133333;
6794         else {
6795                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6796                 case GC_DISPLAY_CLOCK_333_MHZ:
6797                         return 333333;
6798                 default:
6799                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6800                         return 190000;
6801                 }
6802         }
6803 }
6804
6805 static int i865_get_display_clock_speed(struct drm_device *dev)
6806 {
6807         return 266667;
6808 }
6809
6810 static int i85x_get_display_clock_speed(struct drm_device *dev)
6811 {
6812         u16 hpllcc = 0;
6813
6814         /*
6815          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6816          * encoding is different :(
6817          * FIXME is this the right way to detect 852GM/852GMV?
6818          */
6819         if (dev->pdev->revision == 0x1)
6820                 return 133333;
6821
6822         pci_bus_read_config_word(dev->pdev->bus,
6823                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6824
6825         /* Assume that the hardware is in the high speed state.  This
6826          * should be the default.
6827          */
6828         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6829         case GC_CLOCK_133_200:
6830         case GC_CLOCK_133_200_2:
6831         case GC_CLOCK_100_200:
6832                 return 200000;
6833         case GC_CLOCK_166_250:
6834                 return 250000;
6835         case GC_CLOCK_100_133:
6836                 return 133333;
6837         case GC_CLOCK_133_266:
6838         case GC_CLOCK_133_266_2:
6839         case GC_CLOCK_166_266:
6840                 return 266667;
6841         }
6842
6843         /* Shouldn't happen */
6844         return 0;
6845 }
6846
6847 static int i830_get_display_clock_speed(struct drm_device *dev)
6848 {
6849         return 133333;
6850 }
6851
6852 static unsigned int intel_hpll_vco(struct drm_device *dev)
6853 {
6854         struct drm_i915_private *dev_priv = dev->dev_private;
6855         static const unsigned int blb_vco[8] = {
6856                 [0] = 3200000,
6857                 [1] = 4000000,
6858                 [2] = 5333333,
6859                 [3] = 4800000,
6860                 [4] = 6400000,
6861         };
6862         static const unsigned int pnv_vco[8] = {
6863                 [0] = 3200000,
6864                 [1] = 4000000,
6865                 [2] = 5333333,
6866                 [3] = 4800000,
6867                 [4] = 2666667,
6868         };
6869         static const unsigned int cl_vco[8] = {
6870                 [0] = 3200000,
6871                 [1] = 4000000,
6872                 [2] = 5333333,
6873                 [3] = 6400000,
6874                 [4] = 3333333,
6875                 [5] = 3566667,
6876                 [6] = 4266667,
6877         };
6878         static const unsigned int elk_vco[8] = {
6879                 [0] = 3200000,
6880                 [1] = 4000000,
6881                 [2] = 5333333,
6882                 [3] = 4800000,
6883         };
6884         static const unsigned int ctg_vco[8] = {
6885                 [0] = 3200000,
6886                 [1] = 4000000,
6887                 [2] = 5333333,
6888                 [3] = 6400000,
6889                 [4] = 2666667,
6890                 [5] = 4266667,
6891         };
6892         const unsigned int *vco_table;
6893         unsigned int vco;
6894         uint8_t tmp = 0;
6895
6896         /* FIXME other chipsets? */
6897         if (IS_GM45(dev))
6898                 vco_table = ctg_vco;
6899         else if (IS_G4X(dev))
6900                 vco_table = elk_vco;
6901         else if (IS_CRESTLINE(dev))
6902                 vco_table = cl_vco;
6903         else if (IS_PINEVIEW(dev))
6904                 vco_table = pnv_vco;
6905         else if (IS_G33(dev))
6906                 vco_table = blb_vco;
6907         else
6908                 return 0;
6909
6910         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6911
6912         vco = vco_table[tmp & 0x7];
6913         if (vco == 0)
6914                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6915         else
6916                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6917
6918         return vco;
6919 }
6920
6921 static int gm45_get_display_clock_speed(struct drm_device *dev)
6922 {
6923         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6924         uint16_t tmp = 0;
6925
6926         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6927
6928         cdclk_sel = (tmp >> 12) & 0x1;
6929
6930         switch (vco) {
6931         case 2666667:
6932         case 4000000:
6933         case 5333333:
6934                 return cdclk_sel ? 333333 : 222222;
6935         case 3200000:
6936                 return cdclk_sel ? 320000 : 228571;
6937         default:
6938                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6939                 return 222222;
6940         }
6941 }
6942
6943 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6944 {
6945         static const uint8_t div_3200[] = { 16, 10,  8 };
6946         static const uint8_t div_4000[] = { 20, 12, 10 };
6947         static const uint8_t div_5333[] = { 24, 16, 14 };
6948         const uint8_t *div_table;
6949         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6950         uint16_t tmp = 0;
6951
6952         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6953
6954         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6955
6956         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6957                 goto fail;
6958
6959         switch (vco) {
6960         case 3200000:
6961                 div_table = div_3200;
6962                 break;
6963         case 4000000:
6964                 div_table = div_4000;
6965                 break;
6966         case 5333333:
6967                 div_table = div_5333;
6968                 break;
6969         default:
6970                 goto fail;
6971         }
6972
6973         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6974
6975 fail:
6976         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6977         return 200000;
6978 }
6979
6980 static int g33_get_display_clock_speed(struct drm_device *dev)
6981 {
6982         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6983         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6984         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6985         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6986         const uint8_t *div_table;
6987         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6988         uint16_t tmp = 0;
6989
6990         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6991
6992         cdclk_sel = (tmp >> 4) & 0x7;
6993
6994         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6995                 goto fail;
6996
6997         switch (vco) {
6998         case 3200000:
6999                 div_table = div_3200;
7000                 break;
7001         case 4000000:
7002                 div_table = div_4000;
7003                 break;
7004         case 4800000:
7005                 div_table = div_4800;
7006                 break;
7007         case 5333333:
7008                 div_table = div_5333;
7009                 break;
7010         default:
7011                 goto fail;
7012         }
7013
7014         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7015
7016 fail:
7017         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7018         return 190476;
7019 }
7020
7021 static void
7022 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7023 {
7024         while (*num > DATA_LINK_M_N_MASK ||
7025                *den > DATA_LINK_M_N_MASK) {
7026                 *num >>= 1;
7027                 *den >>= 1;
7028         }
7029 }
7030
7031 static void compute_m_n(unsigned int m, unsigned int n,
7032                         uint32_t *ret_m, uint32_t *ret_n)
7033 {
7034         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7035         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7036         intel_reduce_m_n_ratio(ret_m, ret_n);
7037 }
7038
7039 void
7040 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7041                        int pixel_clock, int link_clock,
7042                        struct intel_link_m_n *m_n)
7043 {
7044         m_n->tu = 64;
7045
7046         compute_m_n(bits_per_pixel * pixel_clock,
7047                     link_clock * nlanes * 8,
7048                     &m_n->gmch_m, &m_n->gmch_n);
7049
7050         compute_m_n(pixel_clock, link_clock,
7051                     &m_n->link_m, &m_n->link_n);
7052 }
7053
7054 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7055 {
7056         if (i915.panel_use_ssc >= 0)
7057                 return i915.panel_use_ssc != 0;
7058         return dev_priv->vbt.lvds_use_ssc
7059                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7060 }
7061
7062 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7063                            int num_connectors)
7064 {
7065         struct drm_device *dev = crtc_state->base.crtc->dev;
7066         struct drm_i915_private *dev_priv = dev->dev_private;
7067         int refclk;
7068
7069         WARN_ON(!crtc_state->base.state);
7070
7071         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7072                 refclk = 100000;
7073         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7074             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7075                 refclk = dev_priv->vbt.lvds_ssc_freq;
7076                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7077         } else if (!IS_GEN2(dev)) {
7078                 refclk = 96000;
7079         } else {
7080                 refclk = 48000;
7081         }
7082
7083         return refclk;
7084 }
7085
7086 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7087 {
7088         return (1 << dpll->n) << 16 | dpll->m2;
7089 }
7090
7091 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7092 {
7093         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7094 }
7095
7096 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7097                                      struct intel_crtc_state *crtc_state,
7098                                      intel_clock_t *reduced_clock)
7099 {
7100         struct drm_device *dev = crtc->base.dev;
7101         u32 fp, fp2 = 0;
7102
7103         if (IS_PINEVIEW(dev)) {
7104                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7105                 if (reduced_clock)
7106                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7107         } else {
7108                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7109                 if (reduced_clock)
7110                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7111         }
7112
7113         crtc_state->dpll_hw_state.fp0 = fp;
7114
7115         crtc->lowfreq_avail = false;
7116         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7117             reduced_clock) {
7118                 crtc_state->dpll_hw_state.fp1 = fp2;
7119                 crtc->lowfreq_avail = true;
7120         } else {
7121                 crtc_state->dpll_hw_state.fp1 = fp;
7122         }
7123 }
7124
7125 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7126                 pipe)
7127 {
7128         u32 reg_val;
7129
7130         /*
7131          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7132          * and set it to a reasonable value instead.
7133          */
7134         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7135         reg_val &= 0xffffff00;
7136         reg_val |= 0x00000030;
7137         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7138
7139         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7140         reg_val &= 0x8cffffff;
7141         reg_val = 0x8c000000;
7142         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7143
7144         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7145         reg_val &= 0xffffff00;
7146         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7147
7148         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7149         reg_val &= 0x00ffffff;
7150         reg_val |= 0xb0000000;
7151         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7152 }
7153
7154 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7155                                          struct intel_link_m_n *m_n)
7156 {
7157         struct drm_device *dev = crtc->base.dev;
7158         struct drm_i915_private *dev_priv = dev->dev_private;
7159         int pipe = crtc->pipe;
7160
7161         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7162         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7163         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7164         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7165 }
7166
7167 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7168                                          struct intel_link_m_n *m_n,
7169                                          struct intel_link_m_n *m2_n2)
7170 {
7171         struct drm_device *dev = crtc->base.dev;
7172         struct drm_i915_private *dev_priv = dev->dev_private;
7173         int pipe = crtc->pipe;
7174         enum transcoder transcoder = crtc->config->cpu_transcoder;
7175
7176         if (INTEL_INFO(dev)->gen >= 5) {
7177                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7178                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7179                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7180                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7181                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7182                  * for gen < 8) and if DRRS is supported (to make sure the
7183                  * registers are not unnecessarily accessed).
7184                  */
7185                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7186                         crtc->config->has_drrs) {
7187                         I915_WRITE(PIPE_DATA_M2(transcoder),
7188                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7189                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7190                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7191                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7192                 }
7193         } else {
7194                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7195                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7196                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7197                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7198         }
7199 }
7200
7201 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7202 {
7203         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7204
7205         if (m_n == M1_N1) {
7206                 dp_m_n = &crtc->config->dp_m_n;
7207                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7208         } else if (m_n == M2_N2) {
7209
7210                 /*
7211                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7212                  * needs to be programmed into M1_N1.
7213                  */
7214                 dp_m_n = &crtc->config->dp_m2_n2;
7215         } else {
7216                 DRM_ERROR("Unsupported divider value\n");
7217                 return;
7218         }
7219
7220         if (crtc->config->has_pch_encoder)
7221                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7222         else
7223                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7224 }
7225
7226 static void vlv_compute_dpll(struct intel_crtc *crtc,
7227                              struct intel_crtc_state *pipe_config)
7228 {
7229         u32 dpll, dpll_md;
7230
7231         /*
7232          * Enable DPIO clock input. We should never disable the reference
7233          * clock for pipe B, since VGA hotplug / manual detection depends
7234          * on it.
7235          */
7236         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7237                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7238         /* We should never disable this, set it here for state tracking */
7239         if (crtc->pipe == PIPE_B)
7240                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7241         dpll |= DPLL_VCO_ENABLE;
7242         pipe_config->dpll_hw_state.dpll = dpll;
7243
7244         dpll_md = (pipe_config->pixel_multiplier - 1)
7245                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7246         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7247 }
7248
7249 static void vlv_prepare_pll(struct intel_crtc *crtc,
7250                             const struct intel_crtc_state *pipe_config)
7251 {
7252         struct drm_device *dev = crtc->base.dev;
7253         struct drm_i915_private *dev_priv = dev->dev_private;
7254         int pipe = crtc->pipe;
7255         u32 mdiv;
7256         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7257         u32 coreclk, reg_val;
7258
7259         mutex_lock(&dev_priv->sb_lock);
7260
7261         bestn = pipe_config->dpll.n;
7262         bestm1 = pipe_config->dpll.m1;
7263         bestm2 = pipe_config->dpll.m2;
7264         bestp1 = pipe_config->dpll.p1;
7265         bestp2 = pipe_config->dpll.p2;
7266
7267         /* See eDP HDMI DPIO driver vbios notes doc */
7268
7269         /* PLL B needs special handling */
7270         if (pipe == PIPE_B)
7271                 vlv_pllb_recal_opamp(dev_priv, pipe);
7272
7273         /* Set up Tx target for periodic Rcomp update */
7274         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7275
7276         /* Disable target IRef on PLL */
7277         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7278         reg_val &= 0x00ffffff;
7279         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7280
7281         /* Disable fast lock */
7282         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7283
7284         /* Set idtafcrecal before PLL is enabled */
7285         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7286         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7287         mdiv |= ((bestn << DPIO_N_SHIFT));
7288         mdiv |= (1 << DPIO_K_SHIFT);
7289
7290         /*
7291          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7292          * but we don't support that).
7293          * Note: don't use the DAC post divider as it seems unstable.
7294          */
7295         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7296         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7297
7298         mdiv |= DPIO_ENABLE_CALIBRATION;
7299         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7300
7301         /* Set HBR and RBR LPF coefficients */
7302         if (pipe_config->port_clock == 162000 ||
7303             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7304             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7305                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7306                                  0x009f0003);
7307         else
7308                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7309                                  0x00d0000f);
7310
7311         if (pipe_config->has_dp_encoder) {
7312                 /* Use SSC source */
7313                 if (pipe == PIPE_A)
7314                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7315                                          0x0df40000);
7316                 else
7317                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7318                                          0x0df70000);
7319         } else { /* HDMI or VGA */
7320                 /* Use bend source */
7321                 if (pipe == PIPE_A)
7322                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7323                                          0x0df70000);
7324                 else
7325                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7326                                          0x0df40000);
7327         }
7328
7329         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7330         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7331         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7332             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7333                 coreclk |= 0x01000000;
7334         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7335
7336         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7337         mutex_unlock(&dev_priv->sb_lock);
7338 }
7339
7340 static void chv_compute_dpll(struct intel_crtc *crtc,
7341                              struct intel_crtc_state *pipe_config)
7342 {
7343         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7344                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7345                 DPLL_VCO_ENABLE;
7346         if (crtc->pipe != PIPE_A)
7347                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7348
7349         pipe_config->dpll_hw_state.dpll_md =
7350                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7351 }
7352
7353 static void chv_prepare_pll(struct intel_crtc *crtc,
7354                             const struct intel_crtc_state *pipe_config)
7355 {
7356         struct drm_device *dev = crtc->base.dev;
7357         struct drm_i915_private *dev_priv = dev->dev_private;
7358         int pipe = crtc->pipe;
7359         int dpll_reg = DPLL(crtc->pipe);
7360         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7361         u32 loopfilter, tribuf_calcntr;
7362         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7363         u32 dpio_val;
7364         int vco;
7365
7366         bestn = pipe_config->dpll.n;
7367         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7368         bestm1 = pipe_config->dpll.m1;
7369         bestm2 = pipe_config->dpll.m2 >> 22;
7370         bestp1 = pipe_config->dpll.p1;
7371         bestp2 = pipe_config->dpll.p2;
7372         vco = pipe_config->dpll.vco;
7373         dpio_val = 0;
7374         loopfilter = 0;
7375
7376         /*
7377          * Enable Refclk and SSC
7378          */
7379         I915_WRITE(dpll_reg,
7380                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7381
7382         mutex_lock(&dev_priv->sb_lock);
7383
7384         /* p1 and p2 divider */
7385         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7386                         5 << DPIO_CHV_S1_DIV_SHIFT |
7387                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7388                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7389                         1 << DPIO_CHV_K_DIV_SHIFT);
7390
7391         /* Feedback post-divider - m2 */
7392         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7393
7394         /* Feedback refclk divider - n and m1 */
7395         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7396                         DPIO_CHV_M1_DIV_BY_2 |
7397                         1 << DPIO_CHV_N_DIV_SHIFT);
7398
7399         /* M2 fraction division */
7400         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7401
7402         /* M2 fraction division enable */
7403         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7404         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7405         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7406         if (bestm2_frac)
7407                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7408         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7409
7410         /* Program digital lock detect threshold */
7411         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7412         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7413                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7414         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7415         if (!bestm2_frac)
7416                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7417         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7418
7419         /* Loop filter */
7420         if (vco == 5400000) {
7421                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7422                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7423                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424                 tribuf_calcntr = 0x9;
7425         } else if (vco <= 6200000) {
7426                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7427                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7428                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7429                 tribuf_calcntr = 0x9;
7430         } else if (vco <= 6480000) {
7431                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7432                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7433                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7434                 tribuf_calcntr = 0x8;
7435         } else {
7436                 /* Not supported. Apply the same limits as in the max case */
7437                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7438                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7439                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440                 tribuf_calcntr = 0;
7441         }
7442         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7443
7444         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7445         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7446         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7447         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7448
7449         /* AFC Recal */
7450         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7451                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7452                         DPIO_AFC_RECAL);
7453
7454         mutex_unlock(&dev_priv->sb_lock);
7455 }
7456
7457 /**
7458  * vlv_force_pll_on - forcibly enable just the PLL
7459  * @dev_priv: i915 private structure
7460  * @pipe: pipe PLL to enable
7461  * @dpll: PLL configuration
7462  *
7463  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7464  * in cases where we need the PLL enabled even when @pipe is not going to
7465  * be enabled.
7466  */
7467 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7468                       const struct dpll *dpll)
7469 {
7470         struct intel_crtc *crtc =
7471                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7472         struct intel_crtc_state pipe_config = {
7473                 .base.crtc = &crtc->base,
7474                 .pixel_multiplier = 1,
7475                 .dpll = *dpll,
7476         };
7477
7478         if (IS_CHERRYVIEW(dev)) {
7479                 chv_compute_dpll(crtc, &pipe_config);
7480                 chv_prepare_pll(crtc, &pipe_config);
7481                 chv_enable_pll(crtc, &pipe_config);
7482         } else {
7483                 vlv_compute_dpll(crtc, &pipe_config);
7484                 vlv_prepare_pll(crtc, &pipe_config);
7485                 vlv_enable_pll(crtc, &pipe_config);
7486         }
7487 }
7488
7489 /**
7490  * vlv_force_pll_off - forcibly disable just the PLL
7491  * @dev_priv: i915 private structure
7492  * @pipe: pipe PLL to disable
7493  *
7494  * Disable the PLL for @pipe. To be used in cases where we need
7495  * the PLL enabled even when @pipe is not going to be enabled.
7496  */
7497 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7498 {
7499         if (IS_CHERRYVIEW(dev))
7500                 chv_disable_pll(to_i915(dev), pipe);
7501         else
7502                 vlv_disable_pll(to_i915(dev), pipe);
7503 }
7504
7505 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7506                               struct intel_crtc_state *crtc_state,
7507                               intel_clock_t *reduced_clock,
7508                               int num_connectors)
7509 {
7510         struct drm_device *dev = crtc->base.dev;
7511         struct drm_i915_private *dev_priv = dev->dev_private;
7512         u32 dpll;
7513         bool is_sdvo;
7514         struct dpll *clock = &crtc_state->dpll;
7515
7516         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7517
7518         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7519                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7520
7521         dpll = DPLL_VGA_MODE_DIS;
7522
7523         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7524                 dpll |= DPLLB_MODE_LVDS;
7525         else
7526                 dpll |= DPLLB_MODE_DAC_SERIAL;
7527
7528         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7529                 dpll |= (crtc_state->pixel_multiplier - 1)
7530                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7531         }
7532
7533         if (is_sdvo)
7534                 dpll |= DPLL_SDVO_HIGH_SPEED;
7535
7536         if (crtc_state->has_dp_encoder)
7537                 dpll |= DPLL_SDVO_HIGH_SPEED;
7538
7539         /* compute bitmask from p1 value */
7540         if (IS_PINEVIEW(dev))
7541                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7542         else {
7543                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7544                 if (IS_G4X(dev) && reduced_clock)
7545                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7546         }
7547         switch (clock->p2) {
7548         case 5:
7549                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7550                 break;
7551         case 7:
7552                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7553                 break;
7554         case 10:
7555                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7556                 break;
7557         case 14:
7558                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7559                 break;
7560         }
7561         if (INTEL_INFO(dev)->gen >= 4)
7562                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7563
7564         if (crtc_state->sdvo_tv_clock)
7565                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7566         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7567                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7568                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7569         else
7570                 dpll |= PLL_REF_INPUT_DREFCLK;
7571
7572         dpll |= DPLL_VCO_ENABLE;
7573         crtc_state->dpll_hw_state.dpll = dpll;
7574
7575         if (INTEL_INFO(dev)->gen >= 4) {
7576                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7577                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7578                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7579         }
7580 }
7581
7582 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7583                               struct intel_crtc_state *crtc_state,
7584                               intel_clock_t *reduced_clock,
7585                               int num_connectors)
7586 {
7587         struct drm_device *dev = crtc->base.dev;
7588         struct drm_i915_private *dev_priv = dev->dev_private;
7589         u32 dpll;
7590         struct dpll *clock = &crtc_state->dpll;
7591
7592         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7593
7594         dpll = DPLL_VGA_MODE_DIS;
7595
7596         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7597                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7598         } else {
7599                 if (clock->p1 == 2)
7600                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7601                 else
7602                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7603                 if (clock->p2 == 4)
7604                         dpll |= PLL_P2_DIVIDE_BY_4;
7605         }
7606
7607         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7608                 dpll |= DPLL_DVO_2X_MODE;
7609
7610         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7611                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7612                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7613         else
7614                 dpll |= PLL_REF_INPUT_DREFCLK;
7615
7616         dpll |= DPLL_VCO_ENABLE;
7617         crtc_state->dpll_hw_state.dpll = dpll;
7618 }
7619
7620 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7621 {
7622         struct drm_device *dev = intel_crtc->base.dev;
7623         struct drm_i915_private *dev_priv = dev->dev_private;
7624         enum pipe pipe = intel_crtc->pipe;
7625         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7626         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7627         uint32_t crtc_vtotal, crtc_vblank_end;
7628         int vsyncshift = 0;
7629
7630         /* We need to be careful not to changed the adjusted mode, for otherwise
7631          * the hw state checker will get angry at the mismatch. */
7632         crtc_vtotal = adjusted_mode->crtc_vtotal;
7633         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7634
7635         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7636                 /* the chip adds 2 halflines automatically */
7637                 crtc_vtotal -= 1;
7638                 crtc_vblank_end -= 1;
7639
7640                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7641                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7642                 else
7643                         vsyncshift = adjusted_mode->crtc_hsync_start -
7644                                 adjusted_mode->crtc_htotal / 2;
7645                 if (vsyncshift < 0)
7646                         vsyncshift += adjusted_mode->crtc_htotal;
7647         }
7648
7649         if (INTEL_INFO(dev)->gen > 3)
7650                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7651
7652         I915_WRITE(HTOTAL(cpu_transcoder),
7653                    (adjusted_mode->crtc_hdisplay - 1) |
7654                    ((adjusted_mode->crtc_htotal - 1) << 16));
7655         I915_WRITE(HBLANK(cpu_transcoder),
7656                    (adjusted_mode->crtc_hblank_start - 1) |
7657                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7658         I915_WRITE(HSYNC(cpu_transcoder),
7659                    (adjusted_mode->crtc_hsync_start - 1) |
7660                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7661
7662         I915_WRITE(VTOTAL(cpu_transcoder),
7663                    (adjusted_mode->crtc_vdisplay - 1) |
7664                    ((crtc_vtotal - 1) << 16));
7665         I915_WRITE(VBLANK(cpu_transcoder),
7666                    (adjusted_mode->crtc_vblank_start - 1) |
7667                    ((crtc_vblank_end - 1) << 16));
7668         I915_WRITE(VSYNC(cpu_transcoder),
7669                    (adjusted_mode->crtc_vsync_start - 1) |
7670                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7671
7672         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7673          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7674          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7675          * bits. */
7676         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7677             (pipe == PIPE_B || pipe == PIPE_C))
7678                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7679
7680         /* pipesrc controls the size that is scaled from, which should
7681          * always be the user's requested size.
7682          */
7683         I915_WRITE(PIPESRC(pipe),
7684                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7685                    (intel_crtc->config->pipe_src_h - 1));
7686 }
7687
7688 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7689                                    struct intel_crtc_state *pipe_config)
7690 {
7691         struct drm_device *dev = crtc->base.dev;
7692         struct drm_i915_private *dev_priv = dev->dev_private;
7693         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7694         uint32_t tmp;
7695
7696         tmp = I915_READ(HTOTAL(cpu_transcoder));
7697         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7698         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7699         tmp = I915_READ(HBLANK(cpu_transcoder));
7700         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7701         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7702         tmp = I915_READ(HSYNC(cpu_transcoder));
7703         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7704         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7705
7706         tmp = I915_READ(VTOTAL(cpu_transcoder));
7707         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7708         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7709         tmp = I915_READ(VBLANK(cpu_transcoder));
7710         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7711         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7712         tmp = I915_READ(VSYNC(cpu_transcoder));
7713         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7714         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7715
7716         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7717                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7718                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7719                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7720         }
7721
7722         tmp = I915_READ(PIPESRC(crtc->pipe));
7723         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7724         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7725
7726         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7727         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7728 }
7729
7730 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7731                                  struct intel_crtc_state *pipe_config)
7732 {
7733         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7734         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7735         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7736         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7737
7738         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7739         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7740         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7741         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7742
7743         mode->flags = pipe_config->base.adjusted_mode.flags;
7744         mode->type = DRM_MODE_TYPE_DRIVER;
7745
7746         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7747         mode->flags |= pipe_config->base.adjusted_mode.flags;
7748
7749         mode->hsync = drm_mode_hsync(mode);
7750         mode->vrefresh = drm_mode_vrefresh(mode);
7751         drm_mode_set_name(mode);
7752 }
7753
7754 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7755 {
7756         struct drm_device *dev = intel_crtc->base.dev;
7757         struct drm_i915_private *dev_priv = dev->dev_private;
7758         uint32_t pipeconf;
7759
7760         pipeconf = 0;
7761
7762         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7763             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7764                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7765
7766         if (intel_crtc->config->double_wide)
7767                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7768
7769         /* only g4x and later have fancy bpc/dither controls */
7770         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7771                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7772                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7773                         pipeconf |= PIPECONF_DITHER_EN |
7774                                     PIPECONF_DITHER_TYPE_SP;
7775
7776                 switch (intel_crtc->config->pipe_bpp) {
7777                 case 18:
7778                         pipeconf |= PIPECONF_6BPC;
7779                         break;
7780                 case 24:
7781                         pipeconf |= PIPECONF_8BPC;
7782                         break;
7783                 case 30:
7784                         pipeconf |= PIPECONF_10BPC;
7785                         break;
7786                 default:
7787                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7788                         BUG();
7789                 }
7790         }
7791
7792         if (HAS_PIPE_CXSR(dev)) {
7793                 if (intel_crtc->lowfreq_avail) {
7794                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7795                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7796                 } else {
7797                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7798                 }
7799         }
7800
7801         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7802                 if (INTEL_INFO(dev)->gen < 4 ||
7803                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7804                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7805                 else
7806                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7807         } else
7808                 pipeconf |= PIPECONF_PROGRESSIVE;
7809
7810         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7811                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7812
7813         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7814         POSTING_READ(PIPECONF(intel_crtc->pipe));
7815 }
7816
7817 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7818                                    struct intel_crtc_state *crtc_state)
7819 {
7820         struct drm_device *dev = crtc->base.dev;
7821         struct drm_i915_private *dev_priv = dev->dev_private;
7822         int refclk, num_connectors = 0;
7823         intel_clock_t clock;
7824         bool ok;
7825         bool is_dsi = false;
7826         struct intel_encoder *encoder;
7827         const intel_limit_t *limit;
7828         struct drm_atomic_state *state = crtc_state->base.state;
7829         struct drm_connector *connector;
7830         struct drm_connector_state *connector_state;
7831         int i;
7832
7833         memset(&crtc_state->dpll_hw_state, 0,
7834                sizeof(crtc_state->dpll_hw_state));
7835
7836         for_each_connector_in_state(state, connector, connector_state, i) {
7837                 if (connector_state->crtc != &crtc->base)
7838                         continue;
7839
7840                 encoder = to_intel_encoder(connector_state->best_encoder);
7841
7842                 switch (encoder->type) {
7843                 case INTEL_OUTPUT_DSI:
7844                         is_dsi = true;
7845                         break;
7846                 default:
7847                         break;
7848                 }
7849
7850                 num_connectors++;
7851         }
7852
7853         if (is_dsi)
7854                 return 0;
7855
7856         if (!crtc_state->clock_set) {
7857                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7858
7859                 /*
7860                  * Returns a set of divisors for the desired target clock with
7861                  * the given refclk, or FALSE.  The returned values represent
7862                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7863                  * 2) / p1 / p2.
7864                  */
7865                 limit = intel_limit(crtc_state, refclk);
7866                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7867                                                  crtc_state->port_clock,
7868                                                  refclk, NULL, &clock);
7869                 if (!ok) {
7870                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7871                         return -EINVAL;
7872                 }
7873
7874                 /* Compat-code for transition, will disappear. */
7875                 crtc_state->dpll.n = clock.n;
7876                 crtc_state->dpll.m1 = clock.m1;
7877                 crtc_state->dpll.m2 = clock.m2;
7878                 crtc_state->dpll.p1 = clock.p1;
7879                 crtc_state->dpll.p2 = clock.p2;
7880         }
7881
7882         if (IS_GEN2(dev)) {
7883                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7884                                   num_connectors);
7885         } else if (IS_CHERRYVIEW(dev)) {
7886                 chv_compute_dpll(crtc, crtc_state);
7887         } else if (IS_VALLEYVIEW(dev)) {
7888                 vlv_compute_dpll(crtc, crtc_state);
7889         } else {
7890                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7891                                   num_connectors);
7892         }
7893
7894         return 0;
7895 }
7896
7897 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7898                                  struct intel_crtc_state *pipe_config)
7899 {
7900         struct drm_device *dev = crtc->base.dev;
7901         struct drm_i915_private *dev_priv = dev->dev_private;
7902         uint32_t tmp;
7903
7904         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7905                 return;
7906
7907         tmp = I915_READ(PFIT_CONTROL);
7908         if (!(tmp & PFIT_ENABLE))
7909                 return;
7910
7911         /* Check whether the pfit is attached to our pipe. */
7912         if (INTEL_INFO(dev)->gen < 4) {
7913                 if (crtc->pipe != PIPE_B)
7914                         return;
7915         } else {
7916                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7917                         return;
7918         }
7919
7920         pipe_config->gmch_pfit.control = tmp;
7921         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7922         if (INTEL_INFO(dev)->gen < 5)
7923                 pipe_config->gmch_pfit.lvds_border_bits =
7924                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7925 }
7926
7927 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7928                                struct intel_crtc_state *pipe_config)
7929 {
7930         struct drm_device *dev = crtc->base.dev;
7931         struct drm_i915_private *dev_priv = dev->dev_private;
7932         int pipe = pipe_config->cpu_transcoder;
7933         intel_clock_t clock;
7934         u32 mdiv;
7935         int refclk = 100000;
7936
7937         /* In case of MIPI DPLL will not even be used */
7938         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7939                 return;
7940
7941         mutex_lock(&dev_priv->sb_lock);
7942         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7943         mutex_unlock(&dev_priv->sb_lock);
7944
7945         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7946         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7947         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7948         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7949         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7950
7951         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7952 }
7953
7954 static void
7955 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7956                               struct intel_initial_plane_config *plane_config)
7957 {
7958         struct drm_device *dev = crtc->base.dev;
7959         struct drm_i915_private *dev_priv = dev->dev_private;
7960         u32 val, base, offset;
7961         int pipe = crtc->pipe, plane = crtc->plane;
7962         int fourcc, pixel_format;
7963         unsigned int aligned_height;
7964         struct drm_framebuffer *fb;
7965         struct intel_framebuffer *intel_fb;
7966
7967         val = I915_READ(DSPCNTR(plane));
7968         if (!(val & DISPLAY_PLANE_ENABLE))
7969                 return;
7970
7971         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7972         if (!intel_fb) {
7973                 DRM_DEBUG_KMS("failed to alloc fb\n");
7974                 return;
7975         }
7976
7977         fb = &intel_fb->base;
7978
7979         if (INTEL_INFO(dev)->gen >= 4) {
7980                 if (val & DISPPLANE_TILED) {
7981                         plane_config->tiling = I915_TILING_X;
7982                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7983                 }
7984         }
7985
7986         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7987         fourcc = i9xx_format_to_fourcc(pixel_format);
7988         fb->pixel_format = fourcc;
7989         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7990
7991         if (INTEL_INFO(dev)->gen >= 4) {
7992                 if (plane_config->tiling)
7993                         offset = I915_READ(DSPTILEOFF(plane));
7994                 else
7995                         offset = I915_READ(DSPLINOFF(plane));
7996                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7997         } else {
7998                 base = I915_READ(DSPADDR(plane));
7999         }
8000         plane_config->base = base;
8001
8002         val = I915_READ(PIPESRC(pipe));
8003         fb->width = ((val >> 16) & 0xfff) + 1;
8004         fb->height = ((val >> 0) & 0xfff) + 1;
8005
8006         val = I915_READ(DSPSTRIDE(pipe));
8007         fb->pitches[0] = val & 0xffffffc0;
8008
8009         aligned_height = intel_fb_align_height(dev, fb->height,
8010                                                fb->pixel_format,
8011                                                fb->modifier[0]);
8012
8013         plane_config->size = fb->pitches[0] * aligned_height;
8014
8015         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8016                       pipe_name(pipe), plane, fb->width, fb->height,
8017                       fb->bits_per_pixel, base, fb->pitches[0],
8018                       plane_config->size);
8019
8020         plane_config->fb = intel_fb;
8021 }
8022
8023 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8024                                struct intel_crtc_state *pipe_config)
8025 {
8026         struct drm_device *dev = crtc->base.dev;
8027         struct drm_i915_private *dev_priv = dev->dev_private;
8028         int pipe = pipe_config->cpu_transcoder;
8029         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8030         intel_clock_t clock;
8031         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8032         int refclk = 100000;
8033
8034         mutex_lock(&dev_priv->sb_lock);
8035         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8036         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8037         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8038         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8039         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8040         mutex_unlock(&dev_priv->sb_lock);
8041
8042         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8043         clock.m2 = (pll_dw0 & 0xff) << 22;
8044         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8045                 clock.m2 |= pll_dw2 & 0x3fffff;
8046         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8047         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8048         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8049
8050         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8051 }
8052
8053 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8054                                  struct intel_crtc_state *pipe_config)
8055 {
8056         struct drm_device *dev = crtc->base.dev;
8057         struct drm_i915_private *dev_priv = dev->dev_private;
8058         uint32_t tmp;
8059
8060         if (!intel_display_power_is_enabled(dev_priv,
8061                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8062                 return false;
8063
8064         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8065         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8066
8067         tmp = I915_READ(PIPECONF(crtc->pipe));
8068         if (!(tmp & PIPECONF_ENABLE))
8069                 return false;
8070
8071         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8072                 switch (tmp & PIPECONF_BPC_MASK) {
8073                 case PIPECONF_6BPC:
8074                         pipe_config->pipe_bpp = 18;
8075                         break;
8076                 case PIPECONF_8BPC:
8077                         pipe_config->pipe_bpp = 24;
8078                         break;
8079                 case PIPECONF_10BPC:
8080                         pipe_config->pipe_bpp = 30;
8081                         break;
8082                 default:
8083                         break;
8084                 }
8085         }
8086
8087         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8088                 pipe_config->limited_color_range = true;
8089
8090         if (INTEL_INFO(dev)->gen < 4)
8091                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8092
8093         intel_get_pipe_timings(crtc, pipe_config);
8094
8095         i9xx_get_pfit_config(crtc, pipe_config);
8096
8097         if (INTEL_INFO(dev)->gen >= 4) {
8098                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8099                 pipe_config->pixel_multiplier =
8100                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8101                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8102                 pipe_config->dpll_hw_state.dpll_md = tmp;
8103         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8104                 tmp = I915_READ(DPLL(crtc->pipe));
8105                 pipe_config->pixel_multiplier =
8106                         ((tmp & SDVO_MULTIPLIER_MASK)
8107                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8108         } else {
8109                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8110                  * port and will be fixed up in the encoder->get_config
8111                  * function. */
8112                 pipe_config->pixel_multiplier = 1;
8113         }
8114         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8115         if (!IS_VALLEYVIEW(dev)) {
8116                 /*
8117                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8118                  * on 830. Filter it out here so that we don't
8119                  * report errors due to that.
8120                  */
8121                 if (IS_I830(dev))
8122                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8123
8124                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8125                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8126         } else {
8127                 /* Mask out read-only status bits. */
8128                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8129                                                      DPLL_PORTC_READY_MASK |
8130                                                      DPLL_PORTB_READY_MASK);
8131         }
8132
8133         if (IS_CHERRYVIEW(dev))
8134                 chv_crtc_clock_get(crtc, pipe_config);
8135         else if (IS_VALLEYVIEW(dev))
8136                 vlv_crtc_clock_get(crtc, pipe_config);
8137         else
8138                 i9xx_crtc_clock_get(crtc, pipe_config);
8139
8140         /*
8141          * Normally the dotclock is filled in by the encoder .get_config()
8142          * but in case the pipe is enabled w/o any ports we need a sane
8143          * default.
8144          */
8145         pipe_config->base.adjusted_mode.crtc_clock =
8146                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8147
8148         return true;
8149 }
8150
8151 static void ironlake_init_pch_refclk(struct drm_device *dev)
8152 {
8153         struct drm_i915_private *dev_priv = dev->dev_private;
8154         struct intel_encoder *encoder;
8155         u32 val, final;
8156         bool has_lvds = false;
8157         bool has_cpu_edp = false;
8158         bool has_panel = false;
8159         bool has_ck505 = false;
8160         bool can_ssc = false;
8161
8162         /* We need to take the global config into account */
8163         for_each_intel_encoder(dev, encoder) {
8164                 switch (encoder->type) {
8165                 case INTEL_OUTPUT_LVDS:
8166                         has_panel = true;
8167                         has_lvds = true;
8168                         break;
8169                 case INTEL_OUTPUT_EDP:
8170                         has_panel = true;
8171                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8172                                 has_cpu_edp = true;
8173                         break;
8174                 default:
8175                         break;
8176                 }
8177         }
8178
8179         if (HAS_PCH_IBX(dev)) {
8180                 has_ck505 = dev_priv->vbt.display_clock_mode;
8181                 can_ssc = has_ck505;
8182         } else {
8183                 has_ck505 = false;
8184                 can_ssc = true;
8185         }
8186
8187         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8188                       has_panel, has_lvds, has_ck505);
8189
8190         /* Ironlake: try to setup display ref clock before DPLL
8191          * enabling. This is only under driver's control after
8192          * PCH B stepping, previous chipset stepping should be
8193          * ignoring this setting.
8194          */
8195         val = I915_READ(PCH_DREF_CONTROL);
8196
8197         /* As we must carefully and slowly disable/enable each source in turn,
8198          * compute the final state we want first and check if we need to
8199          * make any changes at all.
8200          */
8201         final = val;
8202         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8203         if (has_ck505)
8204                 final |= DREF_NONSPREAD_CK505_ENABLE;
8205         else
8206                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8207
8208         final &= ~DREF_SSC_SOURCE_MASK;
8209         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8210         final &= ~DREF_SSC1_ENABLE;
8211
8212         if (has_panel) {
8213                 final |= DREF_SSC_SOURCE_ENABLE;
8214
8215                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8216                         final |= DREF_SSC1_ENABLE;
8217
8218                 if (has_cpu_edp) {
8219                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8220                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8221                         else
8222                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8223                 } else
8224                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8225         } else {
8226                 final |= DREF_SSC_SOURCE_DISABLE;
8227                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8228         }
8229
8230         if (final == val)
8231                 return;
8232
8233         /* Always enable nonspread source */
8234         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8235
8236         if (has_ck505)
8237                 val |= DREF_NONSPREAD_CK505_ENABLE;
8238         else
8239                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8240
8241         if (has_panel) {
8242                 val &= ~DREF_SSC_SOURCE_MASK;
8243                 val |= DREF_SSC_SOURCE_ENABLE;
8244
8245                 /* SSC must be turned on before enabling the CPU output  */
8246                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8247                         DRM_DEBUG_KMS("Using SSC on panel\n");
8248                         val |= DREF_SSC1_ENABLE;
8249                 } else
8250                         val &= ~DREF_SSC1_ENABLE;
8251
8252                 /* Get SSC going before enabling the outputs */
8253                 I915_WRITE(PCH_DREF_CONTROL, val);
8254                 POSTING_READ(PCH_DREF_CONTROL);
8255                 udelay(200);
8256
8257                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8258
8259                 /* Enable CPU source on CPU attached eDP */
8260                 if (has_cpu_edp) {
8261                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8262                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8263                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8264                         } else
8265                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8266                 } else
8267                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8268
8269                 I915_WRITE(PCH_DREF_CONTROL, val);
8270                 POSTING_READ(PCH_DREF_CONTROL);
8271                 udelay(200);
8272         } else {
8273                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8274
8275                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8276
8277                 /* Turn off CPU output */
8278                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8279
8280                 I915_WRITE(PCH_DREF_CONTROL, val);
8281                 POSTING_READ(PCH_DREF_CONTROL);
8282                 udelay(200);
8283
8284                 /* Turn off the SSC source */
8285                 val &= ~DREF_SSC_SOURCE_MASK;
8286                 val |= DREF_SSC_SOURCE_DISABLE;
8287
8288                 /* Turn off SSC1 */
8289                 val &= ~DREF_SSC1_ENABLE;
8290
8291                 I915_WRITE(PCH_DREF_CONTROL, val);
8292                 POSTING_READ(PCH_DREF_CONTROL);
8293                 udelay(200);
8294         }
8295
8296         BUG_ON(val != final);
8297 }
8298
8299 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8300 {
8301         uint32_t tmp;
8302
8303         tmp = I915_READ(SOUTH_CHICKEN2);
8304         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8305         I915_WRITE(SOUTH_CHICKEN2, tmp);
8306
8307         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8308                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8309                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8310
8311         tmp = I915_READ(SOUTH_CHICKEN2);
8312         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8313         I915_WRITE(SOUTH_CHICKEN2, tmp);
8314
8315         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8316                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8317                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8318 }
8319
8320 /* WaMPhyProgramming:hsw */
8321 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8322 {
8323         uint32_t tmp;
8324
8325         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8326         tmp &= ~(0xFF << 24);
8327         tmp |= (0x12 << 24);
8328         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8329
8330         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8331         tmp |= (1 << 11);
8332         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8333
8334         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8335         tmp |= (1 << 11);
8336         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8337
8338         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8339         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8340         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8341
8342         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8343         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8344         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8345
8346         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8347         tmp &= ~(7 << 13);
8348         tmp |= (5 << 13);
8349         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8350
8351         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8352         tmp &= ~(7 << 13);
8353         tmp |= (5 << 13);
8354         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8355
8356         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8357         tmp &= ~0xFF;
8358         tmp |= 0x1C;
8359         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8360
8361         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8362         tmp &= ~0xFF;
8363         tmp |= 0x1C;
8364         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8365
8366         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8367         tmp &= ~(0xFF << 16);
8368         tmp |= (0x1C << 16);
8369         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8370
8371         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8372         tmp &= ~(0xFF << 16);
8373         tmp |= (0x1C << 16);
8374         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8375
8376         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8377         tmp |= (1 << 27);
8378         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8379
8380         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8381         tmp |= (1 << 27);
8382         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8383
8384         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8385         tmp &= ~(0xF << 28);
8386         tmp |= (4 << 28);
8387         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8388
8389         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8390         tmp &= ~(0xF << 28);
8391         tmp |= (4 << 28);
8392         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8393 }
8394
8395 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8396  * Programming" based on the parameters passed:
8397  * - Sequence to enable CLKOUT_DP
8398  * - Sequence to enable CLKOUT_DP without spread
8399  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8400  */
8401 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8402                                  bool with_fdi)
8403 {
8404         struct drm_i915_private *dev_priv = dev->dev_private;
8405         uint32_t reg, tmp;
8406
8407         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8408                 with_spread = true;
8409         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8410                 with_fdi = false;
8411
8412         mutex_lock(&dev_priv->sb_lock);
8413
8414         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8415         tmp &= ~SBI_SSCCTL_DISABLE;
8416         tmp |= SBI_SSCCTL_PATHALT;
8417         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8418
8419         udelay(24);
8420
8421         if (with_spread) {
8422                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8423                 tmp &= ~SBI_SSCCTL_PATHALT;
8424                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8425
8426                 if (with_fdi) {
8427                         lpt_reset_fdi_mphy(dev_priv);
8428                         lpt_program_fdi_mphy(dev_priv);
8429                 }
8430         }
8431
8432         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8433         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8434         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8435         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8436
8437         mutex_unlock(&dev_priv->sb_lock);
8438 }
8439
8440 /* Sequence to disable CLKOUT_DP */
8441 static void lpt_disable_clkout_dp(struct drm_device *dev)
8442 {
8443         struct drm_i915_private *dev_priv = dev->dev_private;
8444         uint32_t reg, tmp;
8445
8446         mutex_lock(&dev_priv->sb_lock);
8447
8448         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8449         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8450         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8451         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8452
8453         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8454         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8455                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8456                         tmp |= SBI_SSCCTL_PATHALT;
8457                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8458                         udelay(32);
8459                 }
8460                 tmp |= SBI_SSCCTL_DISABLE;
8461                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8462         }
8463
8464         mutex_unlock(&dev_priv->sb_lock);
8465 }
8466
8467 static void lpt_init_pch_refclk(struct drm_device *dev)
8468 {
8469         struct intel_encoder *encoder;
8470         bool has_vga = false;
8471
8472         for_each_intel_encoder(dev, encoder) {
8473                 switch (encoder->type) {
8474                 case INTEL_OUTPUT_ANALOG:
8475                         has_vga = true;
8476                         break;
8477                 default:
8478                         break;
8479                 }
8480         }
8481
8482         if (has_vga)
8483                 lpt_enable_clkout_dp(dev, true, true);
8484         else
8485                 lpt_disable_clkout_dp(dev);
8486 }
8487
8488 /*
8489  * Initialize reference clocks when the driver loads
8490  */
8491 void intel_init_pch_refclk(struct drm_device *dev)
8492 {
8493         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8494                 ironlake_init_pch_refclk(dev);
8495         else if (HAS_PCH_LPT(dev))
8496                 lpt_init_pch_refclk(dev);
8497 }
8498
8499 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8500 {
8501         struct drm_device *dev = crtc_state->base.crtc->dev;
8502         struct drm_i915_private *dev_priv = dev->dev_private;
8503         struct drm_atomic_state *state = crtc_state->base.state;
8504         struct drm_connector *connector;
8505         struct drm_connector_state *connector_state;
8506         struct intel_encoder *encoder;
8507         int num_connectors = 0, i;
8508         bool is_lvds = false;
8509
8510         for_each_connector_in_state(state, connector, connector_state, i) {
8511                 if (connector_state->crtc != crtc_state->base.crtc)
8512                         continue;
8513
8514                 encoder = to_intel_encoder(connector_state->best_encoder);
8515
8516                 switch (encoder->type) {
8517                 case INTEL_OUTPUT_LVDS:
8518                         is_lvds = true;
8519                         break;
8520                 default:
8521                         break;
8522                 }
8523                 num_connectors++;
8524         }
8525
8526         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8527                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8528                               dev_priv->vbt.lvds_ssc_freq);
8529                 return dev_priv->vbt.lvds_ssc_freq;
8530         }
8531
8532         return 120000;
8533 }
8534
8535 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8536 {
8537         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8539         int pipe = intel_crtc->pipe;
8540         uint32_t val;
8541
8542         val = 0;
8543
8544         switch (intel_crtc->config->pipe_bpp) {
8545         case 18:
8546                 val |= PIPECONF_6BPC;
8547                 break;
8548         case 24:
8549                 val |= PIPECONF_8BPC;
8550                 break;
8551         case 30:
8552                 val |= PIPECONF_10BPC;
8553                 break;
8554         case 36:
8555                 val |= PIPECONF_12BPC;
8556                 break;
8557         default:
8558                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8559                 BUG();
8560         }
8561
8562         if (intel_crtc->config->dither)
8563                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8564
8565         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8566                 val |= PIPECONF_INTERLACED_ILK;
8567         else
8568                 val |= PIPECONF_PROGRESSIVE;
8569
8570         if (intel_crtc->config->limited_color_range)
8571                 val |= PIPECONF_COLOR_RANGE_SELECT;
8572
8573         I915_WRITE(PIPECONF(pipe), val);
8574         POSTING_READ(PIPECONF(pipe));
8575 }
8576
8577 /*
8578  * Set up the pipe CSC unit.
8579  *
8580  * Currently only full range RGB to limited range RGB conversion
8581  * is supported, but eventually this should handle various
8582  * RGB<->YCbCr scenarios as well.
8583  */
8584 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8585 {
8586         struct drm_device *dev = crtc->dev;
8587         struct drm_i915_private *dev_priv = dev->dev_private;
8588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8589         int pipe = intel_crtc->pipe;
8590         uint16_t coeff = 0x7800; /* 1.0 */
8591
8592         /*
8593          * TODO: Check what kind of values actually come out of the pipe
8594          * with these coeff/postoff values and adjust to get the best
8595          * accuracy. Perhaps we even need to take the bpc value into
8596          * consideration.
8597          */
8598
8599         if (intel_crtc->config->limited_color_range)
8600                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8601
8602         /*
8603          * GY/GU and RY/RU should be the other way around according
8604          * to BSpec, but reality doesn't agree. Just set them up in
8605          * a way that results in the correct picture.
8606          */
8607         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8608         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8609
8610         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8611         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8612
8613         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8614         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8615
8616         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8617         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8618         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8619
8620         if (INTEL_INFO(dev)->gen > 6) {
8621                 uint16_t postoff = 0;
8622
8623                 if (intel_crtc->config->limited_color_range)
8624                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8625
8626                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8627                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8628                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8629
8630                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8631         } else {
8632                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8633
8634                 if (intel_crtc->config->limited_color_range)
8635                         mode |= CSC_BLACK_SCREEN_OFFSET;
8636
8637                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8638         }
8639 }
8640
8641 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8642 {
8643         struct drm_device *dev = crtc->dev;
8644         struct drm_i915_private *dev_priv = dev->dev_private;
8645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8646         enum pipe pipe = intel_crtc->pipe;
8647         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8648         uint32_t val;
8649
8650         val = 0;
8651
8652         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8653                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8654
8655         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8656                 val |= PIPECONF_INTERLACED_ILK;
8657         else
8658                 val |= PIPECONF_PROGRESSIVE;
8659
8660         I915_WRITE(PIPECONF(cpu_transcoder), val);
8661         POSTING_READ(PIPECONF(cpu_transcoder));
8662
8663         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8664         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8665
8666         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8667                 val = 0;
8668
8669                 switch (intel_crtc->config->pipe_bpp) {
8670                 case 18:
8671                         val |= PIPEMISC_DITHER_6_BPC;
8672                         break;
8673                 case 24:
8674                         val |= PIPEMISC_DITHER_8_BPC;
8675                         break;
8676                 case 30:
8677                         val |= PIPEMISC_DITHER_10_BPC;
8678                         break;
8679                 case 36:
8680                         val |= PIPEMISC_DITHER_12_BPC;
8681                         break;
8682                 default:
8683                         /* Case prevented by pipe_config_set_bpp. */
8684                         BUG();
8685                 }
8686
8687                 if (intel_crtc->config->dither)
8688                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8689
8690                 I915_WRITE(PIPEMISC(pipe), val);
8691         }
8692 }
8693
8694 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8695                                     struct intel_crtc_state *crtc_state,
8696                                     intel_clock_t *clock,
8697                                     bool *has_reduced_clock,
8698                                     intel_clock_t *reduced_clock)
8699 {
8700         struct drm_device *dev = crtc->dev;
8701         struct drm_i915_private *dev_priv = dev->dev_private;
8702         int refclk;
8703         const intel_limit_t *limit;
8704         bool ret;
8705
8706         refclk = ironlake_get_refclk(crtc_state);
8707
8708         /*
8709          * Returns a set of divisors for the desired target clock with the given
8710          * refclk, or FALSE.  The returned values represent the clock equation:
8711          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8712          */
8713         limit = intel_limit(crtc_state, refclk);
8714         ret = dev_priv->display.find_dpll(limit, crtc_state,
8715                                           crtc_state->port_clock,
8716                                           refclk, NULL, clock);
8717         if (!ret)
8718                 return false;
8719
8720         return true;
8721 }
8722
8723 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8724 {
8725         /*
8726          * Account for spread spectrum to avoid
8727          * oversubscribing the link. Max center spread
8728          * is 2.5%; use 5% for safety's sake.
8729          */
8730         u32 bps = target_clock * bpp * 21 / 20;
8731         return DIV_ROUND_UP(bps, link_bw * 8);
8732 }
8733
8734 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8735 {
8736         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8737 }
8738
8739 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8740                                       struct intel_crtc_state *crtc_state,
8741                                       u32 *fp,
8742                                       intel_clock_t *reduced_clock, u32 *fp2)
8743 {
8744         struct drm_crtc *crtc = &intel_crtc->base;
8745         struct drm_device *dev = crtc->dev;
8746         struct drm_i915_private *dev_priv = dev->dev_private;
8747         struct drm_atomic_state *state = crtc_state->base.state;
8748         struct drm_connector *connector;
8749         struct drm_connector_state *connector_state;
8750         struct intel_encoder *encoder;
8751         uint32_t dpll;
8752         int factor, num_connectors = 0, i;
8753         bool is_lvds = false, is_sdvo = false;
8754
8755         for_each_connector_in_state(state, connector, connector_state, i) {
8756                 if (connector_state->crtc != crtc_state->base.crtc)
8757                         continue;
8758
8759                 encoder = to_intel_encoder(connector_state->best_encoder);
8760
8761                 switch (encoder->type) {
8762                 case INTEL_OUTPUT_LVDS:
8763                         is_lvds = true;
8764                         break;
8765                 case INTEL_OUTPUT_SDVO:
8766                 case INTEL_OUTPUT_HDMI:
8767                         is_sdvo = true;
8768                         break;
8769                 default:
8770                         break;
8771                 }
8772
8773                 num_connectors++;
8774         }
8775
8776         /* Enable autotuning of the PLL clock (if permissible) */
8777         factor = 21;
8778         if (is_lvds) {
8779                 if ((intel_panel_use_ssc(dev_priv) &&
8780                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8781                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8782                         factor = 25;
8783         } else if (crtc_state->sdvo_tv_clock)
8784                 factor = 20;
8785
8786         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8787                 *fp |= FP_CB_TUNE;
8788
8789         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8790                 *fp2 |= FP_CB_TUNE;
8791
8792         dpll = 0;
8793
8794         if (is_lvds)
8795                 dpll |= DPLLB_MODE_LVDS;
8796         else
8797                 dpll |= DPLLB_MODE_DAC_SERIAL;
8798
8799         dpll |= (crtc_state->pixel_multiplier - 1)
8800                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8801
8802         if (is_sdvo)
8803                 dpll |= DPLL_SDVO_HIGH_SPEED;
8804         if (crtc_state->has_dp_encoder)
8805                 dpll |= DPLL_SDVO_HIGH_SPEED;
8806
8807         /* compute bitmask from p1 value */
8808         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8809         /* also FPA1 */
8810         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8811
8812         switch (crtc_state->dpll.p2) {
8813         case 5:
8814                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8815                 break;
8816         case 7:
8817                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8818                 break;
8819         case 10:
8820                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8821                 break;
8822         case 14:
8823                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8824                 break;
8825         }
8826
8827         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8828                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8829         else
8830                 dpll |= PLL_REF_INPUT_DREFCLK;
8831
8832         return dpll | DPLL_VCO_ENABLE;
8833 }
8834
8835 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8836                                        struct intel_crtc_state *crtc_state)
8837 {
8838         struct drm_device *dev = crtc->base.dev;
8839         intel_clock_t clock, reduced_clock;
8840         u32 dpll = 0, fp = 0, fp2 = 0;
8841         bool ok, has_reduced_clock = false;
8842         bool is_lvds = false;
8843         struct intel_shared_dpll *pll;
8844
8845         memset(&crtc_state->dpll_hw_state, 0,
8846                sizeof(crtc_state->dpll_hw_state));
8847
8848         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8849
8850         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8851              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8852
8853         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8854                                      &has_reduced_clock, &reduced_clock);
8855         if (!ok && !crtc_state->clock_set) {
8856                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8857                 return -EINVAL;
8858         }
8859         /* Compat-code for transition, will disappear. */
8860         if (!crtc_state->clock_set) {
8861                 crtc_state->dpll.n = clock.n;
8862                 crtc_state->dpll.m1 = clock.m1;
8863                 crtc_state->dpll.m2 = clock.m2;
8864                 crtc_state->dpll.p1 = clock.p1;
8865                 crtc_state->dpll.p2 = clock.p2;
8866         }
8867
8868         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8869         if (crtc_state->has_pch_encoder) {
8870                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8871                 if (has_reduced_clock)
8872                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8873
8874                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8875                                              &fp, &reduced_clock,
8876                                              has_reduced_clock ? &fp2 : NULL);
8877
8878                 crtc_state->dpll_hw_state.dpll = dpll;
8879                 crtc_state->dpll_hw_state.fp0 = fp;
8880                 if (has_reduced_clock)
8881                         crtc_state->dpll_hw_state.fp1 = fp2;
8882                 else
8883                         crtc_state->dpll_hw_state.fp1 = fp;
8884
8885                 pll = intel_get_shared_dpll(crtc, crtc_state);
8886                 if (pll == NULL) {
8887                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8888                                          pipe_name(crtc->pipe));
8889                         return -EINVAL;
8890                 }
8891         }
8892
8893         if (is_lvds && has_reduced_clock)
8894                 crtc->lowfreq_avail = true;
8895         else
8896                 crtc->lowfreq_avail = false;
8897
8898         return 0;
8899 }
8900
8901 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8902                                          struct intel_link_m_n *m_n)
8903 {
8904         struct drm_device *dev = crtc->base.dev;
8905         struct drm_i915_private *dev_priv = dev->dev_private;
8906         enum pipe pipe = crtc->pipe;
8907
8908         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8909         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8910         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8911                 & ~TU_SIZE_MASK;
8912         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8913         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8914                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8915 }
8916
8917 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8918                                          enum transcoder transcoder,
8919                                          struct intel_link_m_n *m_n,
8920                                          struct intel_link_m_n *m2_n2)
8921 {
8922         struct drm_device *dev = crtc->base.dev;
8923         struct drm_i915_private *dev_priv = dev->dev_private;
8924         enum pipe pipe = crtc->pipe;
8925
8926         if (INTEL_INFO(dev)->gen >= 5) {
8927                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8928                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8929                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8930                         & ~TU_SIZE_MASK;
8931                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8932                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8933                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8934                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8935                  * gen < 8) and if DRRS is supported (to make sure the
8936                  * registers are not unnecessarily read).
8937                  */
8938                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8939                         crtc->config->has_drrs) {
8940                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8941                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8942                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8943                                         & ~TU_SIZE_MASK;
8944                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8945                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8946                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8947                 }
8948         } else {
8949                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8950                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8951                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8952                         & ~TU_SIZE_MASK;
8953                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8954                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8955                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8956         }
8957 }
8958
8959 void intel_dp_get_m_n(struct intel_crtc *crtc,
8960                       struct intel_crtc_state *pipe_config)
8961 {
8962         if (pipe_config->has_pch_encoder)
8963                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8964         else
8965                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8966                                              &pipe_config->dp_m_n,
8967                                              &pipe_config->dp_m2_n2);
8968 }
8969
8970 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8971                                         struct intel_crtc_state *pipe_config)
8972 {
8973         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8974                                      &pipe_config->fdi_m_n, NULL);
8975 }
8976
8977 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8978                                     struct intel_crtc_state *pipe_config)
8979 {
8980         struct drm_device *dev = crtc->base.dev;
8981         struct drm_i915_private *dev_priv = dev->dev_private;
8982         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8983         uint32_t ps_ctrl = 0;
8984         int id = -1;
8985         int i;
8986
8987         /* find scaler attached to this pipe */
8988         for (i = 0; i < crtc->num_scalers; i++) {
8989                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8990                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8991                         id = i;
8992                         pipe_config->pch_pfit.enabled = true;
8993                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8994                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8995                         break;
8996                 }
8997         }
8998
8999         scaler_state->scaler_id = id;
9000         if (id >= 0) {
9001                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9002         } else {
9003                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9004         }
9005 }
9006
9007 static void
9008 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9009                                  struct intel_initial_plane_config *plane_config)
9010 {
9011         struct drm_device *dev = crtc->base.dev;
9012         struct drm_i915_private *dev_priv = dev->dev_private;
9013         u32 val, base, offset, stride_mult, tiling;
9014         int pipe = crtc->pipe;
9015         int fourcc, pixel_format;
9016         unsigned int aligned_height;
9017         struct drm_framebuffer *fb;
9018         struct intel_framebuffer *intel_fb;
9019
9020         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9021         if (!intel_fb) {
9022                 DRM_DEBUG_KMS("failed to alloc fb\n");
9023                 return;
9024         }
9025
9026         fb = &intel_fb->base;
9027
9028         val = I915_READ(PLANE_CTL(pipe, 0));
9029         if (!(val & PLANE_CTL_ENABLE))
9030                 goto error;
9031
9032         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9033         fourcc = skl_format_to_fourcc(pixel_format,
9034                                       val & PLANE_CTL_ORDER_RGBX,
9035                                       val & PLANE_CTL_ALPHA_MASK);
9036         fb->pixel_format = fourcc;
9037         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9038
9039         tiling = val & PLANE_CTL_TILED_MASK;
9040         switch (tiling) {
9041         case PLANE_CTL_TILED_LINEAR:
9042                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9043                 break;
9044         case PLANE_CTL_TILED_X:
9045                 plane_config->tiling = I915_TILING_X;
9046                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9047                 break;
9048         case PLANE_CTL_TILED_Y:
9049                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9050                 break;
9051         case PLANE_CTL_TILED_YF:
9052                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9053                 break;
9054         default:
9055                 MISSING_CASE(tiling);
9056                 goto error;
9057         }
9058
9059         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9060         plane_config->base = base;
9061
9062         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9063
9064         val = I915_READ(PLANE_SIZE(pipe, 0));
9065         fb->height = ((val >> 16) & 0xfff) + 1;
9066         fb->width = ((val >> 0) & 0x1fff) + 1;
9067
9068         val = I915_READ(PLANE_STRIDE(pipe, 0));
9069         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9070                                                 fb->pixel_format);
9071         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9072
9073         aligned_height = intel_fb_align_height(dev, fb->height,
9074                                                fb->pixel_format,
9075                                                fb->modifier[0]);
9076
9077         plane_config->size = fb->pitches[0] * aligned_height;
9078
9079         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9080                       pipe_name(pipe), fb->width, fb->height,
9081                       fb->bits_per_pixel, base, fb->pitches[0],
9082                       plane_config->size);
9083
9084         plane_config->fb = intel_fb;
9085         return;
9086
9087 error:
9088         kfree(fb);
9089 }
9090
9091 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9092                                      struct intel_crtc_state *pipe_config)
9093 {
9094         struct drm_device *dev = crtc->base.dev;
9095         struct drm_i915_private *dev_priv = dev->dev_private;
9096         uint32_t tmp;
9097
9098         tmp = I915_READ(PF_CTL(crtc->pipe));
9099
9100         if (tmp & PF_ENABLE) {
9101                 pipe_config->pch_pfit.enabled = true;
9102                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9103                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9104
9105                 /* We currently do not free assignements of panel fitters on
9106                  * ivb/hsw (since we don't use the higher upscaling modes which
9107                  * differentiates them) so just WARN about this case for now. */
9108                 if (IS_GEN7(dev)) {
9109                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9110                                 PF_PIPE_SEL_IVB(crtc->pipe));
9111                 }
9112         }
9113 }
9114
9115 static void
9116 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9117                                   struct intel_initial_plane_config *plane_config)
9118 {
9119         struct drm_device *dev = crtc->base.dev;
9120         struct drm_i915_private *dev_priv = dev->dev_private;
9121         u32 val, base, offset;
9122         int pipe = crtc->pipe;
9123         int fourcc, pixel_format;
9124         unsigned int aligned_height;
9125         struct drm_framebuffer *fb;
9126         struct intel_framebuffer *intel_fb;
9127
9128         val = I915_READ(DSPCNTR(pipe));
9129         if (!(val & DISPLAY_PLANE_ENABLE))
9130                 return;
9131
9132         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9133         if (!intel_fb) {
9134                 DRM_DEBUG_KMS("failed to alloc fb\n");
9135                 return;
9136         }
9137
9138         fb = &intel_fb->base;
9139
9140         if (INTEL_INFO(dev)->gen >= 4) {
9141                 if (val & DISPPLANE_TILED) {
9142                         plane_config->tiling = I915_TILING_X;
9143                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9144                 }
9145         }
9146
9147         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9148         fourcc = i9xx_format_to_fourcc(pixel_format);
9149         fb->pixel_format = fourcc;
9150         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9151
9152         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9153         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9154                 offset = I915_READ(DSPOFFSET(pipe));
9155         } else {
9156                 if (plane_config->tiling)
9157                         offset = I915_READ(DSPTILEOFF(pipe));
9158                 else
9159                         offset = I915_READ(DSPLINOFF(pipe));
9160         }
9161         plane_config->base = base;
9162
9163         val = I915_READ(PIPESRC(pipe));
9164         fb->width = ((val >> 16) & 0xfff) + 1;
9165         fb->height = ((val >> 0) & 0xfff) + 1;
9166
9167         val = I915_READ(DSPSTRIDE(pipe));
9168         fb->pitches[0] = val & 0xffffffc0;
9169
9170         aligned_height = intel_fb_align_height(dev, fb->height,
9171                                                fb->pixel_format,
9172                                                fb->modifier[0]);
9173
9174         plane_config->size = fb->pitches[0] * aligned_height;
9175
9176         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9177                       pipe_name(pipe), fb->width, fb->height,
9178                       fb->bits_per_pixel, base, fb->pitches[0],
9179                       plane_config->size);
9180
9181         plane_config->fb = intel_fb;
9182 }
9183
9184 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9185                                      struct intel_crtc_state *pipe_config)
9186 {
9187         struct drm_device *dev = crtc->base.dev;
9188         struct drm_i915_private *dev_priv = dev->dev_private;
9189         uint32_t tmp;
9190
9191         if (!intel_display_power_is_enabled(dev_priv,
9192                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9193                 return false;
9194
9195         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9196         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9197
9198         tmp = I915_READ(PIPECONF(crtc->pipe));
9199         if (!(tmp & PIPECONF_ENABLE))
9200                 return false;
9201
9202         switch (tmp & PIPECONF_BPC_MASK) {
9203         case PIPECONF_6BPC:
9204                 pipe_config->pipe_bpp = 18;
9205                 break;
9206         case PIPECONF_8BPC:
9207                 pipe_config->pipe_bpp = 24;
9208                 break;
9209         case PIPECONF_10BPC:
9210                 pipe_config->pipe_bpp = 30;
9211                 break;
9212         case PIPECONF_12BPC:
9213                 pipe_config->pipe_bpp = 36;
9214                 break;
9215         default:
9216                 break;
9217         }
9218
9219         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9220                 pipe_config->limited_color_range = true;
9221
9222         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9223                 struct intel_shared_dpll *pll;
9224
9225                 pipe_config->has_pch_encoder = true;
9226
9227                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9228                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9229                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9230
9231                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9232
9233                 if (HAS_PCH_IBX(dev_priv->dev)) {
9234                         pipe_config->shared_dpll =
9235                                 (enum intel_dpll_id) crtc->pipe;
9236                 } else {
9237                         tmp = I915_READ(PCH_DPLL_SEL);
9238                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9239                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9240                         else
9241                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9242                 }
9243
9244                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9245
9246                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9247                                            &pipe_config->dpll_hw_state));
9248
9249                 tmp = pipe_config->dpll_hw_state.dpll;
9250                 pipe_config->pixel_multiplier =
9251                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9252                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9253
9254                 ironlake_pch_clock_get(crtc, pipe_config);
9255         } else {
9256                 pipe_config->pixel_multiplier = 1;
9257         }
9258
9259         intel_get_pipe_timings(crtc, pipe_config);
9260
9261         ironlake_get_pfit_config(crtc, pipe_config);
9262
9263         return true;
9264 }
9265
9266 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9267 {
9268         struct drm_device *dev = dev_priv->dev;
9269         struct intel_crtc *crtc;
9270
9271         for_each_intel_crtc(dev, crtc)
9272                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9273                      pipe_name(crtc->pipe));
9274
9275         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9276         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9277         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9278         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9279         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9280         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9281              "CPU PWM1 enabled\n");
9282         if (IS_HASWELL(dev))
9283                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9284                      "CPU PWM2 enabled\n");
9285         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9286              "PCH PWM1 enabled\n");
9287         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9288              "Utility pin enabled\n");
9289         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9290
9291         /*
9292          * In theory we can still leave IRQs enabled, as long as only the HPD
9293          * interrupts remain enabled. We used to check for that, but since it's
9294          * gen-specific and since we only disable LCPLL after we fully disable
9295          * the interrupts, the check below should be enough.
9296          */
9297         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9298 }
9299
9300 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9301 {
9302         struct drm_device *dev = dev_priv->dev;
9303
9304         if (IS_HASWELL(dev))
9305                 return I915_READ(D_COMP_HSW);
9306         else
9307                 return I915_READ(D_COMP_BDW);
9308 }
9309
9310 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9311 {
9312         struct drm_device *dev = dev_priv->dev;
9313
9314         if (IS_HASWELL(dev)) {
9315                 mutex_lock(&dev_priv->rps.hw_lock);
9316                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9317                                             val))
9318                         DRM_ERROR("Failed to write to D_COMP\n");
9319                 mutex_unlock(&dev_priv->rps.hw_lock);
9320         } else {
9321                 I915_WRITE(D_COMP_BDW, val);
9322                 POSTING_READ(D_COMP_BDW);
9323         }
9324 }
9325
9326 /*
9327  * This function implements pieces of two sequences from BSpec:
9328  * - Sequence for display software to disable LCPLL
9329  * - Sequence for display software to allow package C8+
9330  * The steps implemented here are just the steps that actually touch the LCPLL
9331  * register. Callers should take care of disabling all the display engine
9332  * functions, doing the mode unset, fixing interrupts, etc.
9333  */
9334 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9335                               bool switch_to_fclk, bool allow_power_down)
9336 {
9337         uint32_t val;
9338
9339         assert_can_disable_lcpll(dev_priv);
9340
9341         val = I915_READ(LCPLL_CTL);
9342
9343         if (switch_to_fclk) {
9344                 val |= LCPLL_CD_SOURCE_FCLK;
9345                 I915_WRITE(LCPLL_CTL, val);
9346
9347                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9348                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9349                         DRM_ERROR("Switching to FCLK failed\n");
9350
9351                 val = I915_READ(LCPLL_CTL);
9352         }
9353
9354         val |= LCPLL_PLL_DISABLE;
9355         I915_WRITE(LCPLL_CTL, val);
9356         POSTING_READ(LCPLL_CTL);
9357
9358         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9359                 DRM_ERROR("LCPLL still locked\n");
9360
9361         val = hsw_read_dcomp(dev_priv);
9362         val |= D_COMP_COMP_DISABLE;
9363         hsw_write_dcomp(dev_priv, val);
9364         ndelay(100);
9365
9366         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9367                      1))
9368                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9369
9370         if (allow_power_down) {
9371                 val = I915_READ(LCPLL_CTL);
9372                 val |= LCPLL_POWER_DOWN_ALLOW;
9373                 I915_WRITE(LCPLL_CTL, val);
9374                 POSTING_READ(LCPLL_CTL);
9375         }
9376 }
9377
9378 /*
9379  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9380  * source.
9381  */
9382 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9383 {
9384         uint32_t val;
9385
9386         val = I915_READ(LCPLL_CTL);
9387
9388         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9389                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9390                 return;
9391
9392         /*
9393          * Make sure we're not on PC8 state before disabling PC8, otherwise
9394          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9395          */
9396         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9397
9398         if (val & LCPLL_POWER_DOWN_ALLOW) {
9399                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9400                 I915_WRITE(LCPLL_CTL, val);
9401                 POSTING_READ(LCPLL_CTL);
9402         }
9403
9404         val = hsw_read_dcomp(dev_priv);
9405         val |= D_COMP_COMP_FORCE;
9406         val &= ~D_COMP_COMP_DISABLE;
9407         hsw_write_dcomp(dev_priv, val);
9408
9409         val = I915_READ(LCPLL_CTL);
9410         val &= ~LCPLL_PLL_DISABLE;
9411         I915_WRITE(LCPLL_CTL, val);
9412
9413         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9414                 DRM_ERROR("LCPLL not locked yet\n");
9415
9416         if (val & LCPLL_CD_SOURCE_FCLK) {
9417                 val = I915_READ(LCPLL_CTL);
9418                 val &= ~LCPLL_CD_SOURCE_FCLK;
9419                 I915_WRITE(LCPLL_CTL, val);
9420
9421                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9422                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9423                         DRM_ERROR("Switching back to LCPLL failed\n");
9424         }
9425
9426         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9427         intel_update_cdclk(dev_priv->dev);
9428 }
9429
9430 /*
9431  * Package states C8 and deeper are really deep PC states that can only be
9432  * reached when all the devices on the system allow it, so even if the graphics
9433  * device allows PC8+, it doesn't mean the system will actually get to these
9434  * states. Our driver only allows PC8+ when going into runtime PM.
9435  *
9436  * The requirements for PC8+ are that all the outputs are disabled, the power
9437  * well is disabled and most interrupts are disabled, and these are also
9438  * requirements for runtime PM. When these conditions are met, we manually do
9439  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9440  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9441  * hang the machine.
9442  *
9443  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9444  * the state of some registers, so when we come back from PC8+ we need to
9445  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9446  * need to take care of the registers kept by RC6. Notice that this happens even
9447  * if we don't put the device in PCI D3 state (which is what currently happens
9448  * because of the runtime PM support).
9449  *
9450  * For more, read "Display Sequences for Package C8" on the hardware
9451  * documentation.
9452  */
9453 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9454 {
9455         struct drm_device *dev = dev_priv->dev;
9456         uint32_t val;
9457
9458         DRM_DEBUG_KMS("Enabling package C8+\n");
9459
9460         if (HAS_PCH_LPT_LP(dev)) {
9461                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9462                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9463                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9464         }
9465
9466         lpt_disable_clkout_dp(dev);
9467         hsw_disable_lcpll(dev_priv, true, true);
9468 }
9469
9470 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9471 {
9472         struct drm_device *dev = dev_priv->dev;
9473         uint32_t val;
9474
9475         DRM_DEBUG_KMS("Disabling package C8+\n");
9476
9477         hsw_restore_lcpll(dev_priv);
9478         lpt_init_pch_refclk(dev);
9479
9480         if (HAS_PCH_LPT_LP(dev)) {
9481                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9482                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9483                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9484         }
9485
9486         intel_prepare_ddi(dev);
9487 }
9488
9489 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9490 {
9491         struct drm_device *dev = old_state->dev;
9492         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9493
9494         broxton_set_cdclk(dev, req_cdclk);
9495 }
9496
9497 /* compute the max rate for new configuration */
9498 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9499 {
9500         struct intel_crtc *intel_crtc;
9501         struct intel_crtc_state *crtc_state;
9502         int max_pixel_rate = 0;
9503
9504         for_each_intel_crtc(state->dev, intel_crtc) {
9505                 int pixel_rate;
9506
9507                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9508                 if (IS_ERR(crtc_state))
9509                         return PTR_ERR(crtc_state);
9510
9511                 if (!crtc_state->base.enable)
9512                         continue;
9513
9514                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9515
9516                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9517                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9518                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9519
9520                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9521         }
9522
9523         return max_pixel_rate;
9524 }
9525
9526 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9527 {
9528         struct drm_i915_private *dev_priv = dev->dev_private;
9529         uint32_t val, data;
9530         int ret;
9531
9532         if (WARN((I915_READ(LCPLL_CTL) &
9533                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9534                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9535                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9536                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9537                  "trying to change cdclk frequency with cdclk not enabled\n"))
9538                 return;
9539
9540         mutex_lock(&dev_priv->rps.hw_lock);
9541         ret = sandybridge_pcode_write(dev_priv,
9542                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9543         mutex_unlock(&dev_priv->rps.hw_lock);
9544         if (ret) {
9545                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9546                 return;
9547         }
9548
9549         val = I915_READ(LCPLL_CTL);
9550         val |= LCPLL_CD_SOURCE_FCLK;
9551         I915_WRITE(LCPLL_CTL, val);
9552
9553         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9554                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9555                 DRM_ERROR("Switching to FCLK failed\n");
9556
9557         val = I915_READ(LCPLL_CTL);
9558         val &= ~LCPLL_CLK_FREQ_MASK;
9559
9560         switch (cdclk) {
9561         case 450000:
9562                 val |= LCPLL_CLK_FREQ_450;
9563                 data = 0;
9564                 break;
9565         case 540000:
9566                 val |= LCPLL_CLK_FREQ_54O_BDW;
9567                 data = 1;
9568                 break;
9569         case 337500:
9570                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9571                 data = 2;
9572                 break;
9573         case 675000:
9574                 val |= LCPLL_CLK_FREQ_675_BDW;
9575                 data = 3;
9576                 break;
9577         default:
9578                 WARN(1, "invalid cdclk frequency\n");
9579                 return;
9580         }
9581
9582         I915_WRITE(LCPLL_CTL, val);
9583
9584         val = I915_READ(LCPLL_CTL);
9585         val &= ~LCPLL_CD_SOURCE_FCLK;
9586         I915_WRITE(LCPLL_CTL, val);
9587
9588         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9589                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9590                 DRM_ERROR("Switching back to LCPLL failed\n");
9591
9592         mutex_lock(&dev_priv->rps.hw_lock);
9593         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9594         mutex_unlock(&dev_priv->rps.hw_lock);
9595
9596         intel_update_cdclk(dev);
9597
9598         WARN(cdclk != dev_priv->cdclk_freq,
9599              "cdclk requested %d kHz but got %d kHz\n",
9600              cdclk, dev_priv->cdclk_freq);
9601 }
9602
9603 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9604 {
9605         struct drm_i915_private *dev_priv = to_i915(state->dev);
9606         int max_pixclk = ilk_max_pixel_rate(state);
9607         int cdclk;
9608
9609         /*
9610          * FIXME should also account for plane ratio
9611          * once 64bpp pixel formats are supported.
9612          */
9613         if (max_pixclk > 540000)
9614                 cdclk = 675000;
9615         else if (max_pixclk > 450000)
9616                 cdclk = 540000;
9617         else if (max_pixclk > 337500)
9618                 cdclk = 450000;
9619         else
9620                 cdclk = 337500;
9621
9622         /*
9623          * FIXME move the cdclk caclulation to
9624          * compute_config() so we can fail gracegully.
9625          */
9626         if (cdclk > dev_priv->max_cdclk_freq) {
9627                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9628                           cdclk, dev_priv->max_cdclk_freq);
9629                 cdclk = dev_priv->max_cdclk_freq;
9630         }
9631
9632         to_intel_atomic_state(state)->cdclk = cdclk;
9633
9634         return 0;
9635 }
9636
9637 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9638 {
9639         struct drm_device *dev = old_state->dev;
9640         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9641
9642         broadwell_set_cdclk(dev, req_cdclk);
9643 }
9644
9645 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9646                                       struct intel_crtc_state *crtc_state)
9647 {
9648         if (!intel_ddi_pll_select(crtc, crtc_state))
9649                 return -EINVAL;
9650
9651         crtc->lowfreq_avail = false;
9652
9653         return 0;
9654 }
9655
9656 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9657                                 enum port port,
9658                                 struct intel_crtc_state *pipe_config)
9659 {
9660         switch (port) {
9661         case PORT_A:
9662                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9663                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9664                 break;
9665         case PORT_B:
9666                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9667                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9668                 break;
9669         case PORT_C:
9670                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9671                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9672                 break;
9673         default:
9674                 DRM_ERROR("Incorrect port type\n");
9675         }
9676 }
9677
9678 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9679                                 enum port port,
9680                                 struct intel_crtc_state *pipe_config)
9681 {
9682         u32 temp, dpll_ctl1;
9683
9684         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9685         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9686
9687         switch (pipe_config->ddi_pll_sel) {
9688         case SKL_DPLL0:
9689                 /*
9690                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9691                  * of the shared DPLL framework and thus needs to be read out
9692                  * separately
9693                  */
9694                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9695                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9696                 break;
9697         case SKL_DPLL1:
9698                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9699                 break;
9700         case SKL_DPLL2:
9701                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9702                 break;
9703         case SKL_DPLL3:
9704                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9705                 break;
9706         }
9707 }
9708
9709 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9710                                 enum port port,
9711                                 struct intel_crtc_state *pipe_config)
9712 {
9713         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9714
9715         switch (pipe_config->ddi_pll_sel) {
9716         case PORT_CLK_SEL_WRPLL1:
9717                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9718                 break;
9719         case PORT_CLK_SEL_WRPLL2:
9720                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9721                 break;
9722         }
9723 }
9724
9725 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9726                                        struct intel_crtc_state *pipe_config)
9727 {
9728         struct drm_device *dev = crtc->base.dev;
9729         struct drm_i915_private *dev_priv = dev->dev_private;
9730         struct intel_shared_dpll *pll;
9731         enum port port;
9732         uint32_t tmp;
9733
9734         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9735
9736         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9737
9738         if (IS_SKYLAKE(dev))
9739                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9740         else if (IS_BROXTON(dev))
9741                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9742         else
9743                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9744
9745         if (pipe_config->shared_dpll >= 0) {
9746                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9747
9748                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9749                                            &pipe_config->dpll_hw_state));
9750         }
9751
9752         /*
9753          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9754          * DDI E. So just check whether this pipe is wired to DDI E and whether
9755          * the PCH transcoder is on.
9756          */
9757         if (INTEL_INFO(dev)->gen < 9 &&
9758             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9759                 pipe_config->has_pch_encoder = true;
9760
9761                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9762                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9763                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9764
9765                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9766         }
9767 }
9768
9769 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9770                                     struct intel_crtc_state *pipe_config)
9771 {
9772         struct drm_device *dev = crtc->base.dev;
9773         struct drm_i915_private *dev_priv = dev->dev_private;
9774         enum intel_display_power_domain pfit_domain;
9775         uint32_t tmp;
9776
9777         if (!intel_display_power_is_enabled(dev_priv,
9778                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9779                 return false;
9780
9781         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9782         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9783
9784         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9785         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9786                 enum pipe trans_edp_pipe;
9787                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9788                 default:
9789                         WARN(1, "unknown pipe linked to edp transcoder\n");
9790                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9791                 case TRANS_DDI_EDP_INPUT_A_ON:
9792                         trans_edp_pipe = PIPE_A;
9793                         break;
9794                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9795                         trans_edp_pipe = PIPE_B;
9796                         break;
9797                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9798                         trans_edp_pipe = PIPE_C;
9799                         break;
9800                 }
9801
9802                 if (trans_edp_pipe == crtc->pipe)
9803                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9804         }
9805
9806         if (!intel_display_power_is_enabled(dev_priv,
9807                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9808                 return false;
9809
9810         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9811         if (!(tmp & PIPECONF_ENABLE))
9812                 return false;
9813
9814         haswell_get_ddi_port_state(crtc, pipe_config);
9815
9816         intel_get_pipe_timings(crtc, pipe_config);
9817
9818         if (INTEL_INFO(dev)->gen >= 9) {
9819                 skl_init_scalers(dev, crtc, pipe_config);
9820         }
9821
9822         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9823
9824         if (INTEL_INFO(dev)->gen >= 9) {
9825                 pipe_config->scaler_state.scaler_id = -1;
9826                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9827         }
9828
9829         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9830                 if (INTEL_INFO(dev)->gen >= 9)
9831                         skylake_get_pfit_config(crtc, pipe_config);
9832                 else
9833                         ironlake_get_pfit_config(crtc, pipe_config);
9834         }
9835
9836         if (IS_HASWELL(dev))
9837                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9838                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9839
9840         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9841                 pipe_config->pixel_multiplier =
9842                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9843         } else {
9844                 pipe_config->pixel_multiplier = 1;
9845         }
9846
9847         return true;
9848 }
9849
9850 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9851 {
9852         struct drm_device *dev = crtc->dev;
9853         struct drm_i915_private *dev_priv = dev->dev_private;
9854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9855         uint32_t cntl = 0, size = 0;
9856
9857         if (base) {
9858                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9859                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9860                 unsigned int stride = roundup_pow_of_two(width) * 4;
9861
9862                 switch (stride) {
9863                 default:
9864                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9865                                   width, stride);
9866                         stride = 256;
9867                         /* fallthrough */
9868                 case 256:
9869                 case 512:
9870                 case 1024:
9871                 case 2048:
9872                         break;
9873                 }
9874
9875                 cntl |= CURSOR_ENABLE |
9876                         CURSOR_GAMMA_ENABLE |
9877                         CURSOR_FORMAT_ARGB |
9878                         CURSOR_STRIDE(stride);
9879
9880                 size = (height << 12) | width;
9881         }
9882
9883         if (intel_crtc->cursor_cntl != 0 &&
9884             (intel_crtc->cursor_base != base ||
9885              intel_crtc->cursor_size != size ||
9886              intel_crtc->cursor_cntl != cntl)) {
9887                 /* On these chipsets we can only modify the base/size/stride
9888                  * whilst the cursor is disabled.
9889                  */
9890                 I915_WRITE(CURCNTR(PIPE_A), 0);
9891                 POSTING_READ(CURCNTR(PIPE_A));
9892                 intel_crtc->cursor_cntl = 0;
9893         }
9894
9895         if (intel_crtc->cursor_base != base) {
9896                 I915_WRITE(CURBASE(PIPE_A), base);
9897                 intel_crtc->cursor_base = base;
9898         }
9899
9900         if (intel_crtc->cursor_size != size) {
9901                 I915_WRITE(CURSIZE, size);
9902                 intel_crtc->cursor_size = size;
9903         }
9904
9905         if (intel_crtc->cursor_cntl != cntl) {
9906                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9907                 POSTING_READ(CURCNTR(PIPE_A));
9908                 intel_crtc->cursor_cntl = cntl;
9909         }
9910 }
9911
9912 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9913 {
9914         struct drm_device *dev = crtc->dev;
9915         struct drm_i915_private *dev_priv = dev->dev_private;
9916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9917         int pipe = intel_crtc->pipe;
9918         uint32_t cntl;
9919
9920         cntl = 0;
9921         if (base) {
9922                 cntl = MCURSOR_GAMMA_ENABLE;
9923                 switch (intel_crtc->base.cursor->state->crtc_w) {
9924                         case 64:
9925                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9926                                 break;
9927                         case 128:
9928                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9929                                 break;
9930                         case 256:
9931                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9932                                 break;
9933                         default:
9934                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9935                                 return;
9936                 }
9937                 cntl |= pipe << 28; /* Connect to correct pipe */
9938
9939                 if (HAS_DDI(dev))
9940                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9941         }
9942
9943         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9944                 cntl |= CURSOR_ROTATE_180;
9945
9946         if (intel_crtc->cursor_cntl != cntl) {
9947                 I915_WRITE(CURCNTR(pipe), cntl);
9948                 POSTING_READ(CURCNTR(pipe));
9949                 intel_crtc->cursor_cntl = cntl;
9950         }
9951
9952         /* and commit changes on next vblank */
9953         I915_WRITE(CURBASE(pipe), base);
9954         POSTING_READ(CURBASE(pipe));
9955
9956         intel_crtc->cursor_base = base;
9957 }
9958
9959 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9960 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9961                                      bool on)
9962 {
9963         struct drm_device *dev = crtc->dev;
9964         struct drm_i915_private *dev_priv = dev->dev_private;
9965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9966         int pipe = intel_crtc->pipe;
9967         struct drm_plane_state *cursor_state = crtc->cursor->state;
9968         int x = cursor_state->crtc_x;
9969         int y = cursor_state->crtc_y;
9970         u32 base = 0, pos = 0;
9971
9972         if (on)
9973                 base = intel_crtc->cursor_addr;
9974
9975         if (x >= intel_crtc->config->pipe_src_w)
9976                 base = 0;
9977
9978         if (y >= intel_crtc->config->pipe_src_h)
9979                 base = 0;
9980
9981         if (x < 0) {
9982                 if (x + cursor_state->crtc_w <= 0)
9983                         base = 0;
9984
9985                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9986                 x = -x;
9987         }
9988         pos |= x << CURSOR_X_SHIFT;
9989
9990         if (y < 0) {
9991                 if (y + cursor_state->crtc_h <= 0)
9992                         base = 0;
9993
9994                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9995                 y = -y;
9996         }
9997         pos |= y << CURSOR_Y_SHIFT;
9998
9999         if (base == 0 && intel_crtc->cursor_base == 0)
10000                 return;
10001
10002         I915_WRITE(CURPOS(pipe), pos);
10003
10004         /* ILK+ do this automagically */
10005         if (HAS_GMCH_DISPLAY(dev) &&
10006             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10007                 base += (cursor_state->crtc_h *
10008                          cursor_state->crtc_w - 1) * 4;
10009         }
10010
10011         if (IS_845G(dev) || IS_I865G(dev))
10012                 i845_update_cursor(crtc, base);
10013         else
10014                 i9xx_update_cursor(crtc, base);
10015 }
10016
10017 static bool cursor_size_ok(struct drm_device *dev,
10018                            uint32_t width, uint32_t height)
10019 {
10020         if (width == 0 || height == 0)
10021                 return false;
10022
10023         /*
10024          * 845g/865g are special in that they are only limited by
10025          * the width of their cursors, the height is arbitrary up to
10026          * the precision of the register. Everything else requires
10027          * square cursors, limited to a few power-of-two sizes.
10028          */
10029         if (IS_845G(dev) || IS_I865G(dev)) {
10030                 if ((width & 63) != 0)
10031                         return false;
10032
10033                 if (width > (IS_845G(dev) ? 64 : 512))
10034                         return false;
10035
10036                 if (height > 1023)
10037                         return false;
10038         } else {
10039                 switch (width | height) {
10040                 case 256:
10041                 case 128:
10042                         if (IS_GEN2(dev))
10043                                 return false;
10044                 case 64:
10045                         break;
10046                 default:
10047                         return false;
10048                 }
10049         }
10050
10051         return true;
10052 }
10053
10054 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10055                                  u16 *blue, uint32_t start, uint32_t size)
10056 {
10057         int end = (start + size > 256) ? 256 : start + size, i;
10058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10059
10060         for (i = start; i < end; i++) {
10061                 intel_crtc->lut_r[i] = red[i] >> 8;
10062                 intel_crtc->lut_g[i] = green[i] >> 8;
10063                 intel_crtc->lut_b[i] = blue[i] >> 8;
10064         }
10065
10066         intel_crtc_load_lut(crtc);
10067 }
10068
10069 /* VESA 640x480x72Hz mode to set on the pipe */
10070 static struct drm_display_mode load_detect_mode = {
10071         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10072                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10073 };
10074
10075 struct drm_framebuffer *
10076 __intel_framebuffer_create(struct drm_device *dev,
10077                            struct drm_mode_fb_cmd2 *mode_cmd,
10078                            struct drm_i915_gem_object *obj)
10079 {
10080         struct intel_framebuffer *intel_fb;
10081         int ret;
10082
10083         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10084         if (!intel_fb) {
10085                 drm_gem_object_unreference(&obj->base);
10086                 return ERR_PTR(-ENOMEM);
10087         }
10088
10089         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10090         if (ret)
10091                 goto err;
10092
10093         return &intel_fb->base;
10094 err:
10095         drm_gem_object_unreference(&obj->base);
10096         kfree(intel_fb);
10097
10098         return ERR_PTR(ret);
10099 }
10100
10101 static struct drm_framebuffer *
10102 intel_framebuffer_create(struct drm_device *dev,
10103                          struct drm_mode_fb_cmd2 *mode_cmd,
10104                          struct drm_i915_gem_object *obj)
10105 {
10106         struct drm_framebuffer *fb;
10107         int ret;
10108
10109         ret = i915_mutex_lock_interruptible(dev);
10110         if (ret)
10111                 return ERR_PTR(ret);
10112         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10113         mutex_unlock(&dev->struct_mutex);
10114
10115         return fb;
10116 }
10117
10118 static u32
10119 intel_framebuffer_pitch_for_width(int width, int bpp)
10120 {
10121         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10122         return ALIGN(pitch, 64);
10123 }
10124
10125 static u32
10126 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10127 {
10128         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10129         return PAGE_ALIGN(pitch * mode->vdisplay);
10130 }
10131
10132 static struct drm_framebuffer *
10133 intel_framebuffer_create_for_mode(struct drm_device *dev,
10134                                   struct drm_display_mode *mode,
10135                                   int depth, int bpp)
10136 {
10137         struct drm_i915_gem_object *obj;
10138         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10139
10140         obj = i915_gem_alloc_object(dev,
10141                                     intel_framebuffer_size_for_mode(mode, bpp));
10142         if (obj == NULL)
10143                 return ERR_PTR(-ENOMEM);
10144
10145         mode_cmd.width = mode->hdisplay;
10146         mode_cmd.height = mode->vdisplay;
10147         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10148                                                                 bpp);
10149         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10150
10151         return intel_framebuffer_create(dev, &mode_cmd, obj);
10152 }
10153
10154 static struct drm_framebuffer *
10155 mode_fits_in_fbdev(struct drm_device *dev,
10156                    struct drm_display_mode *mode)
10157 {
10158 #ifdef CONFIG_DRM_FBDEV_EMULATION
10159         struct drm_i915_private *dev_priv = dev->dev_private;
10160         struct drm_i915_gem_object *obj;
10161         struct drm_framebuffer *fb;
10162
10163         if (!dev_priv->fbdev)
10164                 return NULL;
10165
10166         if (!dev_priv->fbdev->fb)
10167                 return NULL;
10168
10169         obj = dev_priv->fbdev->fb->obj;
10170         BUG_ON(!obj);
10171
10172         fb = &dev_priv->fbdev->fb->base;
10173         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10174                                                                fb->bits_per_pixel))
10175                 return NULL;
10176
10177         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10178                 return NULL;
10179
10180         return fb;
10181 #else
10182         return NULL;
10183 #endif
10184 }
10185
10186 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10187                                            struct drm_crtc *crtc,
10188                                            struct drm_display_mode *mode,
10189                                            struct drm_framebuffer *fb,
10190                                            int x, int y)
10191 {
10192         struct drm_plane_state *plane_state;
10193         int hdisplay, vdisplay;
10194         int ret;
10195
10196         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10197         if (IS_ERR(plane_state))
10198                 return PTR_ERR(plane_state);
10199
10200         if (mode)
10201                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10202         else
10203                 hdisplay = vdisplay = 0;
10204
10205         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10206         if (ret)
10207                 return ret;
10208         drm_atomic_set_fb_for_plane(plane_state, fb);
10209         plane_state->crtc_x = 0;
10210         plane_state->crtc_y = 0;
10211         plane_state->crtc_w = hdisplay;
10212         plane_state->crtc_h = vdisplay;
10213         plane_state->src_x = x << 16;
10214         plane_state->src_y = y << 16;
10215         plane_state->src_w = hdisplay << 16;
10216         plane_state->src_h = vdisplay << 16;
10217
10218         return 0;
10219 }
10220
10221 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10222                                 struct drm_display_mode *mode,
10223                                 struct intel_load_detect_pipe *old,
10224                                 struct drm_modeset_acquire_ctx *ctx)
10225 {
10226         struct intel_crtc *intel_crtc;
10227         struct intel_encoder *intel_encoder =
10228                 intel_attached_encoder(connector);
10229         struct drm_crtc *possible_crtc;
10230         struct drm_encoder *encoder = &intel_encoder->base;
10231         struct drm_crtc *crtc = NULL;
10232         struct drm_device *dev = encoder->dev;
10233         struct drm_framebuffer *fb;
10234         struct drm_mode_config *config = &dev->mode_config;
10235         struct drm_atomic_state *state = NULL;
10236         struct drm_connector_state *connector_state;
10237         struct intel_crtc_state *crtc_state;
10238         int ret, i = -1;
10239
10240         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10241                       connector->base.id, connector->name,
10242                       encoder->base.id, encoder->name);
10243
10244 retry:
10245         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10246         if (ret)
10247                 goto fail;
10248
10249         /*
10250          * Algorithm gets a little messy:
10251          *
10252          *   - if the connector already has an assigned crtc, use it (but make
10253          *     sure it's on first)
10254          *
10255          *   - try to find the first unused crtc that can drive this connector,
10256          *     and use that if we find one
10257          */
10258
10259         /* See if we already have a CRTC for this connector */
10260         if (encoder->crtc) {
10261                 crtc = encoder->crtc;
10262
10263                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10264                 if (ret)
10265                         goto fail;
10266                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10267                 if (ret)
10268                         goto fail;
10269
10270                 old->dpms_mode = connector->dpms;
10271                 old->load_detect_temp = false;
10272
10273                 /* Make sure the crtc and connector are running */
10274                 if (connector->dpms != DRM_MODE_DPMS_ON)
10275                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10276
10277                 return true;
10278         }
10279
10280         /* Find an unused one (if possible) */
10281         for_each_crtc(dev, possible_crtc) {
10282                 i++;
10283                 if (!(encoder->possible_crtcs & (1 << i)))
10284                         continue;
10285                 if (possible_crtc->state->enable)
10286                         continue;
10287
10288                 crtc = possible_crtc;
10289                 break;
10290         }
10291
10292         /*
10293          * If we didn't find an unused CRTC, don't use any.
10294          */
10295         if (!crtc) {
10296                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10297                 goto fail;
10298         }
10299
10300         ret = drm_modeset_lock(&crtc->mutex, ctx);
10301         if (ret)
10302                 goto fail;
10303         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10304         if (ret)
10305                 goto fail;
10306
10307         intel_crtc = to_intel_crtc(crtc);
10308         old->dpms_mode = connector->dpms;
10309         old->load_detect_temp = true;
10310         old->release_fb = NULL;
10311
10312         state = drm_atomic_state_alloc(dev);
10313         if (!state)
10314                 return false;
10315
10316         state->acquire_ctx = ctx;
10317
10318         connector_state = drm_atomic_get_connector_state(state, connector);
10319         if (IS_ERR(connector_state)) {
10320                 ret = PTR_ERR(connector_state);
10321                 goto fail;
10322         }
10323
10324         connector_state->crtc = crtc;
10325         connector_state->best_encoder = &intel_encoder->base;
10326
10327         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10328         if (IS_ERR(crtc_state)) {
10329                 ret = PTR_ERR(crtc_state);
10330                 goto fail;
10331         }
10332
10333         crtc_state->base.active = crtc_state->base.enable = true;
10334
10335         if (!mode)
10336                 mode = &load_detect_mode;
10337
10338         /* We need a framebuffer large enough to accommodate all accesses
10339          * that the plane may generate whilst we perform load detection.
10340          * We can not rely on the fbcon either being present (we get called
10341          * during its initialisation to detect all boot displays, or it may
10342          * not even exist) or that it is large enough to satisfy the
10343          * requested mode.
10344          */
10345         fb = mode_fits_in_fbdev(dev, mode);
10346         if (fb == NULL) {
10347                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10348                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10349                 old->release_fb = fb;
10350         } else
10351                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10352         if (IS_ERR(fb)) {
10353                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10354                 goto fail;
10355         }
10356
10357         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10358         if (ret)
10359                 goto fail;
10360
10361         drm_mode_copy(&crtc_state->base.mode, mode);
10362
10363         if (drm_atomic_commit(state)) {
10364                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10365                 if (old->release_fb)
10366                         old->release_fb->funcs->destroy(old->release_fb);
10367                 goto fail;
10368         }
10369         crtc->primary->crtc = crtc;
10370
10371         /* let the connector get through one full cycle before testing */
10372         intel_wait_for_vblank(dev, intel_crtc->pipe);
10373         return true;
10374
10375 fail:
10376         drm_atomic_state_free(state);
10377         state = NULL;
10378
10379         if (ret == -EDEADLK) {
10380                 drm_modeset_backoff(ctx);
10381                 goto retry;
10382         }
10383
10384         return false;
10385 }
10386
10387 void intel_release_load_detect_pipe(struct drm_connector *connector,
10388                                     struct intel_load_detect_pipe *old,
10389                                     struct drm_modeset_acquire_ctx *ctx)
10390 {
10391         struct drm_device *dev = connector->dev;
10392         struct intel_encoder *intel_encoder =
10393                 intel_attached_encoder(connector);
10394         struct drm_encoder *encoder = &intel_encoder->base;
10395         struct drm_crtc *crtc = encoder->crtc;
10396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10397         struct drm_atomic_state *state;
10398         struct drm_connector_state *connector_state;
10399         struct intel_crtc_state *crtc_state;
10400         int ret;
10401
10402         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10403                       connector->base.id, connector->name,
10404                       encoder->base.id, encoder->name);
10405
10406         if (old->load_detect_temp) {
10407                 state = drm_atomic_state_alloc(dev);
10408                 if (!state)
10409                         goto fail;
10410
10411                 state->acquire_ctx = ctx;
10412
10413                 connector_state = drm_atomic_get_connector_state(state, connector);
10414                 if (IS_ERR(connector_state))
10415                         goto fail;
10416
10417                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10418                 if (IS_ERR(crtc_state))
10419                         goto fail;
10420
10421                 connector_state->best_encoder = NULL;
10422                 connector_state->crtc = NULL;
10423
10424                 crtc_state->base.enable = crtc_state->base.active = false;
10425
10426                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10427                                                       0, 0);
10428                 if (ret)
10429                         goto fail;
10430
10431                 ret = drm_atomic_commit(state);
10432                 if (ret)
10433                         goto fail;
10434
10435                 if (old->release_fb) {
10436                         drm_framebuffer_unregister_private(old->release_fb);
10437                         drm_framebuffer_unreference(old->release_fb);
10438                 }
10439
10440                 return;
10441         }
10442
10443         /* Switch crtc and encoder back off if necessary */
10444         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10445                 connector->funcs->dpms(connector, old->dpms_mode);
10446
10447         return;
10448 fail:
10449         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10450         drm_atomic_state_free(state);
10451 }
10452
10453 static int i9xx_pll_refclk(struct drm_device *dev,
10454                            const struct intel_crtc_state *pipe_config)
10455 {
10456         struct drm_i915_private *dev_priv = dev->dev_private;
10457         u32 dpll = pipe_config->dpll_hw_state.dpll;
10458
10459         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10460                 return dev_priv->vbt.lvds_ssc_freq;
10461         else if (HAS_PCH_SPLIT(dev))
10462                 return 120000;
10463         else if (!IS_GEN2(dev))
10464                 return 96000;
10465         else
10466                 return 48000;
10467 }
10468
10469 /* Returns the clock of the currently programmed mode of the given pipe. */
10470 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10471                                 struct intel_crtc_state *pipe_config)
10472 {
10473         struct drm_device *dev = crtc->base.dev;
10474         struct drm_i915_private *dev_priv = dev->dev_private;
10475         int pipe = pipe_config->cpu_transcoder;
10476         u32 dpll = pipe_config->dpll_hw_state.dpll;
10477         u32 fp;
10478         intel_clock_t clock;
10479         int port_clock;
10480         int refclk = i9xx_pll_refclk(dev, pipe_config);
10481
10482         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10483                 fp = pipe_config->dpll_hw_state.fp0;
10484         else
10485                 fp = pipe_config->dpll_hw_state.fp1;
10486
10487         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10488         if (IS_PINEVIEW(dev)) {
10489                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10490                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10491         } else {
10492                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10493                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10494         }
10495
10496         if (!IS_GEN2(dev)) {
10497                 if (IS_PINEVIEW(dev))
10498                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10499                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10500                 else
10501                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10502                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10503
10504                 switch (dpll & DPLL_MODE_MASK) {
10505                 case DPLLB_MODE_DAC_SERIAL:
10506                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10507                                 5 : 10;
10508                         break;
10509                 case DPLLB_MODE_LVDS:
10510                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10511                                 7 : 14;
10512                         break;
10513                 default:
10514                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10515                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10516                         return;
10517                 }
10518
10519                 if (IS_PINEVIEW(dev))
10520                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10521                 else
10522                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10523         } else {
10524                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10525                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10526
10527                 if (is_lvds) {
10528                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10529                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10530
10531                         if (lvds & LVDS_CLKB_POWER_UP)
10532                                 clock.p2 = 7;
10533                         else
10534                                 clock.p2 = 14;
10535                 } else {
10536                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10537                                 clock.p1 = 2;
10538                         else {
10539                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10540                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10541                         }
10542                         if (dpll & PLL_P2_DIVIDE_BY_4)
10543                                 clock.p2 = 4;
10544                         else
10545                                 clock.p2 = 2;
10546                 }
10547
10548                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10549         }
10550
10551         /*
10552          * This value includes pixel_multiplier. We will use
10553          * port_clock to compute adjusted_mode.crtc_clock in the
10554          * encoder's get_config() function.
10555          */
10556         pipe_config->port_clock = port_clock;
10557 }
10558
10559 int intel_dotclock_calculate(int link_freq,
10560                              const struct intel_link_m_n *m_n)
10561 {
10562         /*
10563          * The calculation for the data clock is:
10564          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10565          * But we want to avoid losing precison if possible, so:
10566          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10567          *
10568          * and the link clock is simpler:
10569          * link_clock = (m * link_clock) / n
10570          */
10571
10572         if (!m_n->link_n)
10573                 return 0;
10574
10575         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10576 }
10577
10578 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10579                                    struct intel_crtc_state *pipe_config)
10580 {
10581         struct drm_device *dev = crtc->base.dev;
10582
10583         /* read out port_clock from the DPLL */
10584         i9xx_crtc_clock_get(crtc, pipe_config);
10585
10586         /*
10587          * This value does not include pixel_multiplier.
10588          * We will check that port_clock and adjusted_mode.crtc_clock
10589          * agree once we know their relationship in the encoder's
10590          * get_config() function.
10591          */
10592         pipe_config->base.adjusted_mode.crtc_clock =
10593                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10594                                          &pipe_config->fdi_m_n);
10595 }
10596
10597 /** Returns the currently programmed mode of the given pipe. */
10598 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10599                                              struct drm_crtc *crtc)
10600 {
10601         struct drm_i915_private *dev_priv = dev->dev_private;
10602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10603         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10604         struct drm_display_mode *mode;
10605         struct intel_crtc_state pipe_config;
10606         int htot = I915_READ(HTOTAL(cpu_transcoder));
10607         int hsync = I915_READ(HSYNC(cpu_transcoder));
10608         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10609         int vsync = I915_READ(VSYNC(cpu_transcoder));
10610         enum pipe pipe = intel_crtc->pipe;
10611
10612         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10613         if (!mode)
10614                 return NULL;
10615
10616         /*
10617          * Construct a pipe_config sufficient for getting the clock info
10618          * back out of crtc_clock_get.
10619          *
10620          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10621          * to use a real value here instead.
10622          */
10623         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10624         pipe_config.pixel_multiplier = 1;
10625         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10626         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10627         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10628         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10629
10630         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10631         mode->hdisplay = (htot & 0xffff) + 1;
10632         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10633         mode->hsync_start = (hsync & 0xffff) + 1;
10634         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10635         mode->vdisplay = (vtot & 0xffff) + 1;
10636         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10637         mode->vsync_start = (vsync & 0xffff) + 1;
10638         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10639
10640         drm_mode_set_name(mode);
10641
10642         return mode;
10643 }
10644
10645 void intel_mark_busy(struct drm_device *dev)
10646 {
10647         struct drm_i915_private *dev_priv = dev->dev_private;
10648
10649         if (dev_priv->mm.busy)
10650                 return;
10651
10652         intel_runtime_pm_get(dev_priv);
10653         i915_update_gfx_val(dev_priv);
10654         if (INTEL_INFO(dev)->gen >= 6)
10655                 gen6_rps_busy(dev_priv);
10656         dev_priv->mm.busy = true;
10657 }
10658
10659 void intel_mark_idle(struct drm_device *dev)
10660 {
10661         struct drm_i915_private *dev_priv = dev->dev_private;
10662
10663         if (!dev_priv->mm.busy)
10664                 return;
10665
10666         dev_priv->mm.busy = false;
10667
10668         if (INTEL_INFO(dev)->gen >= 6)
10669                 gen6_rps_idle(dev->dev_private);
10670
10671         intel_runtime_pm_put(dev_priv);
10672 }
10673
10674 static void intel_crtc_destroy(struct drm_crtc *crtc)
10675 {
10676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10677         struct drm_device *dev = crtc->dev;
10678         struct intel_unpin_work *work;
10679
10680         spin_lock_irq(&dev->event_lock);
10681         work = intel_crtc->unpin_work;
10682         intel_crtc->unpin_work = NULL;
10683         spin_unlock_irq(&dev->event_lock);
10684
10685         if (work) {
10686                 cancel_work_sync(&work->work);
10687                 kfree(work);
10688         }
10689
10690         drm_crtc_cleanup(crtc);
10691
10692         kfree(intel_crtc);
10693 }
10694
10695 static void intel_unpin_work_fn(struct work_struct *__work)
10696 {
10697         struct intel_unpin_work *work =
10698                 container_of(__work, struct intel_unpin_work, work);
10699         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10700         struct drm_device *dev = crtc->base.dev;
10701         struct drm_plane *primary = crtc->base.primary;
10702
10703         mutex_lock(&dev->struct_mutex);
10704         intel_unpin_fb_obj(work->old_fb, primary->state);
10705         drm_gem_object_unreference(&work->pending_flip_obj->base);
10706
10707         if (work->flip_queued_req)
10708                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10709         mutex_unlock(&dev->struct_mutex);
10710
10711         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10712         drm_framebuffer_unreference(work->old_fb);
10713
10714         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10715         atomic_dec(&crtc->unpin_work_count);
10716
10717         kfree(work);
10718 }
10719
10720 static void do_intel_finish_page_flip(struct drm_device *dev,
10721                                       struct drm_crtc *crtc)
10722 {
10723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10724         struct intel_unpin_work *work;
10725         unsigned long flags;
10726
10727         /* Ignore early vblank irqs */
10728         if (intel_crtc == NULL)
10729                 return;
10730
10731         /*
10732          * This is called both by irq handlers and the reset code (to complete
10733          * lost pageflips) so needs the full irqsave spinlocks.
10734          */
10735         spin_lock_irqsave(&dev->event_lock, flags);
10736         work = intel_crtc->unpin_work;
10737
10738         /* Ensure we don't miss a work->pending update ... */
10739         smp_rmb();
10740
10741         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10742                 spin_unlock_irqrestore(&dev->event_lock, flags);
10743                 return;
10744         }
10745
10746         page_flip_completed(intel_crtc);
10747
10748         spin_unlock_irqrestore(&dev->event_lock, flags);
10749 }
10750
10751 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10752 {
10753         struct drm_i915_private *dev_priv = dev->dev_private;
10754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10755
10756         do_intel_finish_page_flip(dev, crtc);
10757 }
10758
10759 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10760 {
10761         struct drm_i915_private *dev_priv = dev->dev_private;
10762         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10763
10764         do_intel_finish_page_flip(dev, crtc);
10765 }
10766
10767 /* Is 'a' after or equal to 'b'? */
10768 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10769 {
10770         return !((a - b) & 0x80000000);
10771 }
10772
10773 static bool page_flip_finished(struct intel_crtc *crtc)
10774 {
10775         struct drm_device *dev = crtc->base.dev;
10776         struct drm_i915_private *dev_priv = dev->dev_private;
10777
10778         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10779             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10780                 return true;
10781
10782         /*
10783          * The relevant registers doen't exist on pre-ctg.
10784          * As the flip done interrupt doesn't trigger for mmio
10785          * flips on gmch platforms, a flip count check isn't
10786          * really needed there. But since ctg has the registers,
10787          * include it in the check anyway.
10788          */
10789         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10790                 return true;
10791
10792         /*
10793          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10794          * used the same base address. In that case the mmio flip might
10795          * have completed, but the CS hasn't even executed the flip yet.
10796          *
10797          * A flip count check isn't enough as the CS might have updated
10798          * the base address just after start of vblank, but before we
10799          * managed to process the interrupt. This means we'd complete the
10800          * CS flip too soon.
10801          *
10802          * Combining both checks should get us a good enough result. It may
10803          * still happen that the CS flip has been executed, but has not
10804          * yet actually completed. But in case the base address is the same
10805          * anyway, we don't really care.
10806          */
10807         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10808                 crtc->unpin_work->gtt_offset &&
10809                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10810                                     crtc->unpin_work->flip_count);
10811 }
10812
10813 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10814 {
10815         struct drm_i915_private *dev_priv = dev->dev_private;
10816         struct intel_crtc *intel_crtc =
10817                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10818         unsigned long flags;
10819
10820
10821         /*
10822          * This is called both by irq handlers and the reset code (to complete
10823          * lost pageflips) so needs the full irqsave spinlocks.
10824          *
10825          * NB: An MMIO update of the plane base pointer will also
10826          * generate a page-flip completion irq, i.e. every modeset
10827          * is also accompanied by a spurious intel_prepare_page_flip().
10828          */
10829         spin_lock_irqsave(&dev->event_lock, flags);
10830         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10831                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10832         spin_unlock_irqrestore(&dev->event_lock, flags);
10833 }
10834
10835 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10836 {
10837         /* Ensure that the work item is consistent when activating it ... */
10838         smp_wmb();
10839         atomic_set(&work->pending, INTEL_FLIP_PENDING);
10840         /* and that it is marked active as soon as the irq could fire. */
10841         smp_wmb();
10842 }
10843
10844 static int intel_gen2_queue_flip(struct drm_device *dev,
10845                                  struct drm_crtc *crtc,
10846                                  struct drm_framebuffer *fb,
10847                                  struct drm_i915_gem_object *obj,
10848                                  struct drm_i915_gem_request *req,
10849                                  uint32_t flags)
10850 {
10851         struct intel_engine_cs *ring = req->ring;
10852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10853         u32 flip_mask;
10854         int ret;
10855
10856         ret = intel_ring_begin(req, 6);
10857         if (ret)
10858                 return ret;
10859
10860         /* Can't queue multiple flips, so wait for the previous
10861          * one to finish before executing the next.
10862          */
10863         if (intel_crtc->plane)
10864                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10865         else
10866                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10867         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10868         intel_ring_emit(ring, MI_NOOP);
10869         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10870                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10871         intel_ring_emit(ring, fb->pitches[0]);
10872         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10873         intel_ring_emit(ring, 0); /* aux display base address, unused */
10874
10875         intel_mark_page_flip_active(intel_crtc->unpin_work);
10876         return 0;
10877 }
10878
10879 static int intel_gen3_queue_flip(struct drm_device *dev,
10880                                  struct drm_crtc *crtc,
10881                                  struct drm_framebuffer *fb,
10882                                  struct drm_i915_gem_object *obj,
10883                                  struct drm_i915_gem_request *req,
10884                                  uint32_t flags)
10885 {
10886         struct intel_engine_cs *ring = req->ring;
10887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10888         u32 flip_mask;
10889         int ret;
10890
10891         ret = intel_ring_begin(req, 6);
10892         if (ret)
10893                 return ret;
10894
10895         if (intel_crtc->plane)
10896                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10897         else
10898                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10899         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10900         intel_ring_emit(ring, MI_NOOP);
10901         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10902                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10903         intel_ring_emit(ring, fb->pitches[0]);
10904         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10905         intel_ring_emit(ring, MI_NOOP);
10906
10907         intel_mark_page_flip_active(intel_crtc->unpin_work);
10908         return 0;
10909 }
10910
10911 static int intel_gen4_queue_flip(struct drm_device *dev,
10912                                  struct drm_crtc *crtc,
10913                                  struct drm_framebuffer *fb,
10914                                  struct drm_i915_gem_object *obj,
10915                                  struct drm_i915_gem_request *req,
10916                                  uint32_t flags)
10917 {
10918         struct intel_engine_cs *ring = req->ring;
10919         struct drm_i915_private *dev_priv = dev->dev_private;
10920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10921         uint32_t pf, pipesrc;
10922         int ret;
10923
10924         ret = intel_ring_begin(req, 4);
10925         if (ret)
10926                 return ret;
10927
10928         /* i965+ uses the linear or tiled offsets from the
10929          * Display Registers (which do not change across a page-flip)
10930          * so we need only reprogram the base address.
10931          */
10932         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10933                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10934         intel_ring_emit(ring, fb->pitches[0]);
10935         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10936                         obj->tiling_mode);
10937
10938         /* XXX Enabling the panel-fitter across page-flip is so far
10939          * untested on non-native modes, so ignore it for now.
10940          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10941          */
10942         pf = 0;
10943         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10944         intel_ring_emit(ring, pf | pipesrc);
10945
10946         intel_mark_page_flip_active(intel_crtc->unpin_work);
10947         return 0;
10948 }
10949
10950 static int intel_gen6_queue_flip(struct drm_device *dev,
10951                                  struct drm_crtc *crtc,
10952                                  struct drm_framebuffer *fb,
10953                                  struct drm_i915_gem_object *obj,
10954                                  struct drm_i915_gem_request *req,
10955                                  uint32_t flags)
10956 {
10957         struct intel_engine_cs *ring = req->ring;
10958         struct drm_i915_private *dev_priv = dev->dev_private;
10959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10960         uint32_t pf, pipesrc;
10961         int ret;
10962
10963         ret = intel_ring_begin(req, 4);
10964         if (ret)
10965                 return ret;
10966
10967         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10968                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10969         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10970         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10971
10972         /* Contrary to the suggestions in the documentation,
10973          * "Enable Panel Fitter" does not seem to be required when page
10974          * flipping with a non-native mode, and worse causes a normal
10975          * modeset to fail.
10976          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10977          */
10978         pf = 0;
10979         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10980         intel_ring_emit(ring, pf | pipesrc);
10981
10982         intel_mark_page_flip_active(intel_crtc->unpin_work);
10983         return 0;
10984 }
10985
10986 static int intel_gen7_queue_flip(struct drm_device *dev,
10987                                  struct drm_crtc *crtc,
10988                                  struct drm_framebuffer *fb,
10989                                  struct drm_i915_gem_object *obj,
10990                                  struct drm_i915_gem_request *req,
10991                                  uint32_t flags)
10992 {
10993         struct intel_engine_cs *ring = req->ring;
10994         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10995         uint32_t plane_bit = 0;
10996         int len, ret;
10997
10998         switch (intel_crtc->plane) {
10999         case PLANE_A:
11000                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11001                 break;
11002         case PLANE_B:
11003                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11004                 break;
11005         case PLANE_C:
11006                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11007                 break;
11008         default:
11009                 WARN_ONCE(1, "unknown plane in flip command\n");
11010                 return -ENODEV;
11011         }
11012
11013         len = 4;
11014         if (ring->id == RCS) {
11015                 len += 6;
11016                 /*
11017                  * On Gen 8, SRM is now taking an extra dword to accommodate
11018                  * 48bits addresses, and we need a NOOP for the batch size to
11019                  * stay even.
11020                  */
11021                 if (IS_GEN8(dev))
11022                         len += 2;
11023         }
11024
11025         /*
11026          * BSpec MI_DISPLAY_FLIP for IVB:
11027          * "The full packet must be contained within the same cache line."
11028          *
11029          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11030          * cacheline, if we ever start emitting more commands before
11031          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11032          * then do the cacheline alignment, and finally emit the
11033          * MI_DISPLAY_FLIP.
11034          */
11035         ret = intel_ring_cacheline_align(req);
11036         if (ret)
11037                 return ret;
11038
11039         ret = intel_ring_begin(req, len);
11040         if (ret)
11041                 return ret;
11042
11043         /* Unmask the flip-done completion message. Note that the bspec says that
11044          * we should do this for both the BCS and RCS, and that we must not unmask
11045          * more than one flip event at any time (or ensure that one flip message
11046          * can be sent by waiting for flip-done prior to queueing new flips).
11047          * Experimentation says that BCS works despite DERRMR masking all
11048          * flip-done completion events and that unmasking all planes at once
11049          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11050          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11051          */
11052         if (ring->id == RCS) {
11053                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11054                 intel_ring_emit(ring, DERRMR);
11055                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11056                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11057                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11058                 if (IS_GEN8(dev))
11059                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11060                                               MI_SRM_LRM_GLOBAL_GTT);
11061                 else
11062                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11063                                               MI_SRM_LRM_GLOBAL_GTT);
11064                 intel_ring_emit(ring, DERRMR);
11065                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11066                 if (IS_GEN8(dev)) {
11067                         intel_ring_emit(ring, 0);
11068                         intel_ring_emit(ring, MI_NOOP);
11069                 }
11070         }
11071
11072         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11073         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11074         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11075         intel_ring_emit(ring, (MI_NOOP));
11076
11077         intel_mark_page_flip_active(intel_crtc->unpin_work);
11078         return 0;
11079 }
11080
11081 static bool use_mmio_flip(struct intel_engine_cs *ring,
11082                           struct drm_i915_gem_object *obj)
11083 {
11084         /*
11085          * This is not being used for older platforms, because
11086          * non-availability of flip done interrupt forces us to use
11087          * CS flips. Older platforms derive flip done using some clever
11088          * tricks involving the flip_pending status bits and vblank irqs.
11089          * So using MMIO flips there would disrupt this mechanism.
11090          */
11091
11092         if (ring == NULL)
11093                 return true;
11094
11095         if (INTEL_INFO(ring->dev)->gen < 5)
11096                 return false;
11097
11098         if (i915.use_mmio_flip < 0)
11099                 return false;
11100         else if (i915.use_mmio_flip > 0)
11101                 return true;
11102         else if (i915.enable_execlists)
11103                 return true;
11104         else
11105                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11106 }
11107
11108 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11109                              struct intel_unpin_work *work)
11110 {
11111         struct drm_device *dev = intel_crtc->base.dev;
11112         struct drm_i915_private *dev_priv = dev->dev_private;
11113         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11114         const enum pipe pipe = intel_crtc->pipe;
11115         u32 ctl, stride;
11116
11117         ctl = I915_READ(PLANE_CTL(pipe, 0));
11118         ctl &= ~PLANE_CTL_TILED_MASK;
11119         switch (fb->modifier[0]) {
11120         case DRM_FORMAT_MOD_NONE:
11121                 break;
11122         case I915_FORMAT_MOD_X_TILED:
11123                 ctl |= PLANE_CTL_TILED_X;
11124                 break;
11125         case I915_FORMAT_MOD_Y_TILED:
11126                 ctl |= PLANE_CTL_TILED_Y;
11127                 break;
11128         case I915_FORMAT_MOD_Yf_TILED:
11129                 ctl |= PLANE_CTL_TILED_YF;
11130                 break;
11131         default:
11132                 MISSING_CASE(fb->modifier[0]);
11133         }
11134
11135         /*
11136          * The stride is either expressed as a multiple of 64 bytes chunks for
11137          * linear buffers or in number of tiles for tiled buffers.
11138          */
11139         stride = fb->pitches[0] /
11140                  intel_fb_stride_alignment(dev, fb->modifier[0],
11141                                            fb->pixel_format);
11142
11143         /*
11144          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11145          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11146          */
11147         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11148         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11149
11150         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11151         POSTING_READ(PLANE_SURF(pipe, 0));
11152 }
11153
11154 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11155                              struct intel_unpin_work *work)
11156 {
11157         struct drm_device *dev = intel_crtc->base.dev;
11158         struct drm_i915_private *dev_priv = dev->dev_private;
11159         struct intel_framebuffer *intel_fb =
11160                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11161         struct drm_i915_gem_object *obj = intel_fb->obj;
11162         u32 dspcntr;
11163         u32 reg;
11164
11165         reg = DSPCNTR(intel_crtc->plane);
11166         dspcntr = I915_READ(reg);
11167
11168         if (obj->tiling_mode != I915_TILING_NONE)
11169                 dspcntr |= DISPPLANE_TILED;
11170         else
11171                 dspcntr &= ~DISPPLANE_TILED;
11172
11173         I915_WRITE(reg, dspcntr);
11174
11175         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11176         POSTING_READ(DSPSURF(intel_crtc->plane));
11177 }
11178
11179 /*
11180  * XXX: This is the temporary way to update the plane registers until we get
11181  * around to using the usual plane update functions for MMIO flips
11182  */
11183 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11184 {
11185         struct intel_crtc *crtc = mmio_flip->crtc;
11186         struct intel_unpin_work *work;
11187
11188         spin_lock_irq(&crtc->base.dev->event_lock);
11189         work = crtc->unpin_work;
11190         spin_unlock_irq(&crtc->base.dev->event_lock);
11191         if (work == NULL)
11192                 return;
11193
11194         intel_mark_page_flip_active(work);
11195
11196         intel_pipe_update_start(crtc);
11197
11198         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11199                 skl_do_mmio_flip(crtc, work);
11200         else
11201                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11202                 ilk_do_mmio_flip(crtc, work);
11203
11204         intel_pipe_update_end(crtc);
11205 }
11206
11207 static void intel_mmio_flip_work_func(struct work_struct *work)
11208 {
11209         struct intel_mmio_flip *mmio_flip =
11210                 container_of(work, struct intel_mmio_flip, work);
11211
11212         if (mmio_flip->req) {
11213                 WARN_ON(__i915_wait_request(mmio_flip->req,
11214                                             mmio_flip->crtc->reset_counter,
11215                                             false, NULL,
11216                                             &mmio_flip->i915->rps.mmioflips));
11217                 i915_gem_request_unreference__unlocked(mmio_flip->req);
11218         }
11219
11220         intel_do_mmio_flip(mmio_flip);
11221         kfree(mmio_flip);
11222 }
11223
11224 static int intel_queue_mmio_flip(struct drm_device *dev,
11225                                  struct drm_crtc *crtc,
11226                                  struct drm_framebuffer *fb,
11227                                  struct drm_i915_gem_object *obj,
11228                                  struct intel_engine_cs *ring,
11229                                  uint32_t flags)
11230 {
11231         struct intel_mmio_flip *mmio_flip;
11232
11233         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11234         if (mmio_flip == NULL)
11235                 return -ENOMEM;
11236
11237         mmio_flip->i915 = to_i915(dev);
11238         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11239         mmio_flip->crtc = to_intel_crtc(crtc);
11240
11241         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11242         schedule_work(&mmio_flip->work);
11243
11244         return 0;
11245 }
11246
11247 static int intel_default_queue_flip(struct drm_device *dev,
11248                                     struct drm_crtc *crtc,
11249                                     struct drm_framebuffer *fb,
11250                                     struct drm_i915_gem_object *obj,
11251                                     struct drm_i915_gem_request *req,
11252                                     uint32_t flags)
11253 {
11254         return -ENODEV;
11255 }
11256
11257 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11258                                          struct drm_crtc *crtc)
11259 {
11260         struct drm_i915_private *dev_priv = dev->dev_private;
11261         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11262         struct intel_unpin_work *work = intel_crtc->unpin_work;
11263         u32 addr;
11264
11265         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11266                 return true;
11267
11268         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11269                 return false;
11270
11271         if (!work->enable_stall_check)
11272                 return false;
11273
11274         if (work->flip_ready_vblank == 0) {
11275                 if (work->flip_queued_req &&
11276                     !i915_gem_request_completed(work->flip_queued_req, true))
11277                         return false;
11278
11279                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11280         }
11281
11282         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11283                 return false;
11284
11285         /* Potential stall - if we see that the flip has happened,
11286          * assume a missed interrupt. */
11287         if (INTEL_INFO(dev)->gen >= 4)
11288                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11289         else
11290                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11291
11292         /* There is a potential issue here with a false positive after a flip
11293          * to the same address. We could address this by checking for a
11294          * non-incrementing frame counter.
11295          */
11296         return addr == work->gtt_offset;
11297 }
11298
11299 void intel_check_page_flip(struct drm_device *dev, int pipe)
11300 {
11301         struct drm_i915_private *dev_priv = dev->dev_private;
11302         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11304         struct intel_unpin_work *work;
11305
11306         WARN_ON(!in_interrupt());
11307
11308         if (crtc == NULL)
11309                 return;
11310
11311         spin_lock(&dev->event_lock);
11312         work = intel_crtc->unpin_work;
11313         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11314                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11315                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11316                 page_flip_completed(intel_crtc);
11317                 work = NULL;
11318         }
11319         if (work != NULL &&
11320             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11321                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11322         spin_unlock(&dev->event_lock);
11323 }
11324
11325 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11326                                 struct drm_framebuffer *fb,
11327                                 struct drm_pending_vblank_event *event,
11328                                 uint32_t page_flip_flags)
11329 {
11330         struct drm_device *dev = crtc->dev;
11331         struct drm_i915_private *dev_priv = dev->dev_private;
11332         struct drm_framebuffer *old_fb = crtc->primary->fb;
11333         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11335         struct drm_plane *primary = crtc->primary;
11336         enum pipe pipe = intel_crtc->pipe;
11337         struct intel_unpin_work *work;
11338         struct intel_engine_cs *ring;
11339         bool mmio_flip;
11340         struct drm_i915_gem_request *request = NULL;
11341         int ret;
11342
11343         /*
11344          * drm_mode_page_flip_ioctl() should already catch this, but double
11345          * check to be safe.  In the future we may enable pageflipping from
11346          * a disabled primary plane.
11347          */
11348         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11349                 return -EBUSY;
11350
11351         /* Can't change pixel format via MI display flips. */
11352         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11353                 return -EINVAL;
11354
11355         /*
11356          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11357          * Note that pitch changes could also affect these register.
11358          */
11359         if (INTEL_INFO(dev)->gen > 3 &&
11360             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11361              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11362                 return -EINVAL;
11363
11364         if (i915_terminally_wedged(&dev_priv->gpu_error))
11365                 goto out_hang;
11366
11367         work = kzalloc(sizeof(*work), GFP_KERNEL);
11368         if (work == NULL)
11369                 return -ENOMEM;
11370
11371         work->event = event;
11372         work->crtc = crtc;
11373         work->old_fb = old_fb;
11374         INIT_WORK(&work->work, intel_unpin_work_fn);
11375
11376         ret = drm_crtc_vblank_get(crtc);
11377         if (ret)
11378                 goto free_work;
11379
11380         /* We borrow the event spin lock for protecting unpin_work */
11381         spin_lock_irq(&dev->event_lock);
11382         if (intel_crtc->unpin_work) {
11383                 /* Before declaring the flip queue wedged, check if
11384                  * the hardware completed the operation behind our backs.
11385                  */
11386                 if (__intel_pageflip_stall_check(dev, crtc)) {
11387                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11388                         page_flip_completed(intel_crtc);
11389                 } else {
11390                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11391                         spin_unlock_irq(&dev->event_lock);
11392
11393                         drm_crtc_vblank_put(crtc);
11394                         kfree(work);
11395                         return -EBUSY;
11396                 }
11397         }
11398         intel_crtc->unpin_work = work;
11399         spin_unlock_irq(&dev->event_lock);
11400
11401         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11402                 flush_workqueue(dev_priv->wq);
11403
11404         /* Reference the objects for the scheduled work. */
11405         drm_framebuffer_reference(work->old_fb);
11406         drm_gem_object_reference(&obj->base);
11407
11408         crtc->primary->fb = fb;
11409         update_state_fb(crtc->primary);
11410
11411         work->pending_flip_obj = obj;
11412
11413         ret = i915_mutex_lock_interruptible(dev);
11414         if (ret)
11415                 goto cleanup;
11416
11417         atomic_inc(&intel_crtc->unpin_work_count);
11418         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11419
11420         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11421                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11422
11423         if (IS_VALLEYVIEW(dev)) {
11424                 ring = &dev_priv->ring[BCS];
11425                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11426                         /* vlv: DISPLAY_FLIP fails to change tiling */
11427                         ring = NULL;
11428         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11429                 ring = &dev_priv->ring[BCS];
11430         } else if (INTEL_INFO(dev)->gen >= 7) {
11431                 ring = i915_gem_request_get_ring(obj->last_write_req);
11432                 if (ring == NULL || ring->id != RCS)
11433                         ring = &dev_priv->ring[BCS];
11434         } else {
11435                 ring = &dev_priv->ring[RCS];
11436         }
11437
11438         mmio_flip = use_mmio_flip(ring, obj);
11439
11440         /* When using CS flips, we want to emit semaphores between rings.
11441          * However, when using mmio flips we will create a task to do the
11442          * synchronisation, so all we want here is to pin the framebuffer
11443          * into the display plane and skip any waits.
11444          */
11445         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11446                                          crtc->primary->state,
11447                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11448         if (ret)
11449                 goto cleanup_pending;
11450
11451         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11452                                                   obj, 0);
11453         work->gtt_offset += intel_crtc->dspaddr_offset;
11454
11455         if (mmio_flip) {
11456                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11457                                             page_flip_flags);
11458                 if (ret)
11459                         goto cleanup_unpin;
11460
11461                 i915_gem_request_assign(&work->flip_queued_req,
11462                                         obj->last_write_req);
11463         } else {
11464                 if (!request) {
11465                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11466                         if (ret)
11467                                 goto cleanup_unpin;
11468                 }
11469
11470                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11471                                                    page_flip_flags);
11472                 if (ret)
11473                         goto cleanup_unpin;
11474
11475                 i915_gem_request_assign(&work->flip_queued_req, request);
11476         }
11477
11478         if (request)
11479                 i915_add_request_no_flush(request);
11480
11481         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11482         work->enable_stall_check = true;
11483
11484         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11485                           to_intel_plane(primary)->frontbuffer_bit);
11486         mutex_unlock(&dev->struct_mutex);
11487
11488         intel_fbc_disable_crtc(intel_crtc);
11489         intel_frontbuffer_flip_prepare(dev,
11490                                        to_intel_plane(primary)->frontbuffer_bit);
11491
11492         trace_i915_flip_request(intel_crtc->plane, obj);
11493
11494         return 0;
11495
11496 cleanup_unpin:
11497         intel_unpin_fb_obj(fb, crtc->primary->state);
11498 cleanup_pending:
11499         if (request)
11500                 i915_gem_request_cancel(request);
11501         atomic_dec(&intel_crtc->unpin_work_count);
11502         mutex_unlock(&dev->struct_mutex);
11503 cleanup:
11504         crtc->primary->fb = old_fb;
11505         update_state_fb(crtc->primary);
11506
11507         drm_gem_object_unreference_unlocked(&obj->base);
11508         drm_framebuffer_unreference(work->old_fb);
11509
11510         spin_lock_irq(&dev->event_lock);
11511         intel_crtc->unpin_work = NULL;
11512         spin_unlock_irq(&dev->event_lock);
11513
11514         drm_crtc_vblank_put(crtc);
11515 free_work:
11516         kfree(work);
11517
11518         if (ret == -EIO) {
11519                 struct drm_atomic_state *state;
11520                 struct drm_plane_state *plane_state;
11521
11522 out_hang:
11523                 state = drm_atomic_state_alloc(dev);
11524                 if (!state)
11525                         return -ENOMEM;
11526                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11527
11528 retry:
11529                 plane_state = drm_atomic_get_plane_state(state, primary);
11530                 ret = PTR_ERR_OR_ZERO(plane_state);
11531                 if (!ret) {
11532                         drm_atomic_set_fb_for_plane(plane_state, fb);
11533
11534                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11535                         if (!ret)
11536                                 ret = drm_atomic_commit(state);
11537                 }
11538
11539                 if (ret == -EDEADLK) {
11540                         drm_modeset_backoff(state->acquire_ctx);
11541                         drm_atomic_state_clear(state);
11542                         goto retry;
11543                 }
11544
11545                 if (ret)
11546                         drm_atomic_state_free(state);
11547
11548                 if (ret == 0 && event) {
11549                         spin_lock_irq(&dev->event_lock);
11550                         drm_send_vblank_event(dev, pipe, event);
11551                         spin_unlock_irq(&dev->event_lock);
11552                 }
11553         }
11554         return ret;
11555 }
11556
11557
11558 /**
11559  * intel_wm_need_update - Check whether watermarks need updating
11560  * @plane: drm plane
11561  * @state: new plane state
11562  *
11563  * Check current plane state versus the new one to determine whether
11564  * watermarks need to be recalculated.
11565  *
11566  * Returns true or false.
11567  */
11568 static bool intel_wm_need_update(struct drm_plane *plane,
11569                                  struct drm_plane_state *state)
11570 {
11571         /* Update watermarks on tiling changes. */
11572         if (!plane->state->fb || !state->fb ||
11573             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11574             plane->state->rotation != state->rotation)
11575                 return true;
11576
11577         if (plane->state->crtc_w != state->crtc_w)
11578                 return true;
11579
11580         return false;
11581 }
11582
11583 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11584                                     struct drm_plane_state *plane_state)
11585 {
11586         struct drm_crtc *crtc = crtc_state->crtc;
11587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11588         struct drm_plane *plane = plane_state->plane;
11589         struct drm_device *dev = crtc->dev;
11590         struct drm_i915_private *dev_priv = dev->dev_private;
11591         struct intel_plane_state *old_plane_state =
11592                 to_intel_plane_state(plane->state);
11593         int idx = intel_crtc->base.base.id, ret;
11594         int i = drm_plane_index(plane);
11595         bool mode_changed = needs_modeset(crtc_state);
11596         bool was_crtc_enabled = crtc->state->active;
11597         bool is_crtc_enabled = crtc_state->active;
11598
11599         bool turn_off, turn_on, visible, was_visible;
11600         struct drm_framebuffer *fb = plane_state->fb;
11601
11602         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11603             plane->type != DRM_PLANE_TYPE_CURSOR) {
11604                 ret = skl_update_scaler_plane(
11605                         to_intel_crtc_state(crtc_state),
11606                         to_intel_plane_state(plane_state));
11607                 if (ret)
11608                         return ret;
11609         }
11610
11611         /*
11612          * Disabling a plane is always okay; we just need to update
11613          * fb tracking in a special way since cleanup_fb() won't
11614          * get called by the plane helpers.
11615          */
11616         if (old_plane_state->base.fb && !fb)
11617                 intel_crtc->atomic.disabled_planes |= 1 << i;
11618
11619         was_visible = old_plane_state->visible;
11620         visible = to_intel_plane_state(plane_state)->visible;
11621
11622         if (!was_crtc_enabled && WARN_ON(was_visible))
11623                 was_visible = false;
11624
11625         if (!is_crtc_enabled && WARN_ON(visible))
11626                 visible = false;
11627
11628         if (!was_visible && !visible)
11629                 return 0;
11630
11631         turn_off = was_visible && (!visible || mode_changed);
11632         turn_on = visible && (!was_visible || mode_changed);
11633
11634         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11635                          plane->base.id, fb ? fb->base.id : -1);
11636
11637         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11638                          plane->base.id, was_visible, visible,
11639                          turn_off, turn_on, mode_changed);
11640
11641         if (turn_on) {
11642                 intel_crtc->atomic.update_wm_pre = true;
11643                 /* must disable cxsr around plane enable/disable */
11644                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11645                         intel_crtc->atomic.disable_cxsr = true;
11646                         /* to potentially re-enable cxsr */
11647                         intel_crtc->atomic.wait_vblank = true;
11648                         intel_crtc->atomic.update_wm_post = true;
11649                 }
11650         } else if (turn_off) {
11651                 intel_crtc->atomic.update_wm_post = true;
11652                 /* must disable cxsr around plane enable/disable */
11653                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11654                         if (is_crtc_enabled)
11655                                 intel_crtc->atomic.wait_vblank = true;
11656                         intel_crtc->atomic.disable_cxsr = true;
11657                 }
11658         } else if (intel_wm_need_update(plane, plane_state)) {
11659                 intel_crtc->atomic.update_wm_pre = true;
11660         }
11661
11662         if (visible || was_visible)
11663                 intel_crtc->atomic.fb_bits |=
11664                         to_intel_plane(plane)->frontbuffer_bit;
11665
11666         switch (plane->type) {
11667         case DRM_PLANE_TYPE_PRIMARY:
11668                 intel_crtc->atomic.wait_for_flips = true;
11669                 intel_crtc->atomic.pre_disable_primary = turn_off;
11670                 intel_crtc->atomic.post_enable_primary = turn_on;
11671
11672                 if (turn_off) {
11673                         /*
11674                          * FIXME: Actually if we will still have any other
11675                          * plane enabled on the pipe we could let IPS enabled
11676                          * still, but for now lets consider that when we make
11677                          * primary invisible by setting DSPCNTR to 0 on
11678                          * update_primary_plane function IPS needs to be
11679                          * disable.
11680                          */
11681                         intel_crtc->atomic.disable_ips = true;
11682
11683                         intel_crtc->atomic.disable_fbc = true;
11684                 }
11685
11686                 /*
11687                  * FBC does not work on some platforms for rotated
11688                  * planes, so disable it when rotation is not 0 and
11689                  * update it when rotation is set back to 0.
11690                  *
11691                  * FIXME: This is redundant with the fbc update done in
11692                  * the primary plane enable function except that that
11693                  * one is done too late. We eventually need to unify
11694                  * this.
11695                  */
11696
11697                 if (visible &&
11698                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11699                     dev_priv->fbc.crtc == intel_crtc &&
11700                     plane_state->rotation != BIT(DRM_ROTATE_0))
11701                         intel_crtc->atomic.disable_fbc = true;
11702
11703                 /*
11704                  * BDW signals flip done immediately if the plane
11705                  * is disabled, even if the plane enable is already
11706                  * armed to occur at the next vblank :(
11707                  */
11708                 if (turn_on && IS_BROADWELL(dev))
11709                         intel_crtc->atomic.wait_vblank = true;
11710
11711                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11712                 break;
11713         case DRM_PLANE_TYPE_CURSOR:
11714                 break;
11715         case DRM_PLANE_TYPE_OVERLAY:
11716                 if (turn_off && !mode_changed) {
11717                         intel_crtc->atomic.wait_vblank = true;
11718                         intel_crtc->atomic.update_sprite_watermarks |=
11719                                 1 << i;
11720                 }
11721         }
11722         return 0;
11723 }
11724
11725 static bool encoders_cloneable(const struct intel_encoder *a,
11726                                const struct intel_encoder *b)
11727 {
11728         /* masks could be asymmetric, so check both ways */
11729         return a == b || (a->cloneable & (1 << b->type) &&
11730                           b->cloneable & (1 << a->type));
11731 }
11732
11733 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11734                                          struct intel_crtc *crtc,
11735                                          struct intel_encoder *encoder)
11736 {
11737         struct intel_encoder *source_encoder;
11738         struct drm_connector *connector;
11739         struct drm_connector_state *connector_state;
11740         int i;
11741
11742         for_each_connector_in_state(state, connector, connector_state, i) {
11743                 if (connector_state->crtc != &crtc->base)
11744                         continue;
11745
11746                 source_encoder =
11747                         to_intel_encoder(connector_state->best_encoder);
11748                 if (!encoders_cloneable(encoder, source_encoder))
11749                         return false;
11750         }
11751
11752         return true;
11753 }
11754
11755 static bool check_encoder_cloning(struct drm_atomic_state *state,
11756                                   struct intel_crtc *crtc)
11757 {
11758         struct intel_encoder *encoder;
11759         struct drm_connector *connector;
11760         struct drm_connector_state *connector_state;
11761         int i;
11762
11763         for_each_connector_in_state(state, connector, connector_state, i) {
11764                 if (connector_state->crtc != &crtc->base)
11765                         continue;
11766
11767                 encoder = to_intel_encoder(connector_state->best_encoder);
11768                 if (!check_single_encoder_cloning(state, crtc, encoder))
11769                         return false;
11770         }
11771
11772         return true;
11773 }
11774
11775 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11776                                    struct drm_crtc_state *crtc_state)
11777 {
11778         struct drm_device *dev = crtc->dev;
11779         struct drm_i915_private *dev_priv = dev->dev_private;
11780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11781         struct intel_crtc_state *pipe_config =
11782                 to_intel_crtc_state(crtc_state);
11783         struct drm_atomic_state *state = crtc_state->state;
11784         int ret;
11785         bool mode_changed = needs_modeset(crtc_state);
11786
11787         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11788                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11789                 return -EINVAL;
11790         }
11791
11792         if (mode_changed && !crtc_state->active)
11793                 intel_crtc->atomic.update_wm_post = true;
11794
11795         if (mode_changed && crtc_state->enable &&
11796             dev_priv->display.crtc_compute_clock &&
11797             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11798                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11799                                                            pipe_config);
11800                 if (ret)
11801                         return ret;
11802         }
11803
11804         ret = 0;
11805         if (INTEL_INFO(dev)->gen >= 9) {
11806                 if (mode_changed)
11807                         ret = skl_update_scaler_crtc(pipe_config);
11808
11809                 if (!ret)
11810                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11811                                                          pipe_config);
11812         }
11813
11814         return ret;
11815 }
11816
11817 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11818         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11819         .load_lut = intel_crtc_load_lut,
11820         .atomic_begin = intel_begin_crtc_commit,
11821         .atomic_flush = intel_finish_crtc_commit,
11822         .atomic_check = intel_crtc_atomic_check,
11823 };
11824
11825 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11826 {
11827         struct intel_connector *connector;
11828
11829         for_each_intel_connector(dev, connector) {
11830                 if (connector->base.encoder) {
11831                         connector->base.state->best_encoder =
11832                                 connector->base.encoder;
11833                         connector->base.state->crtc =
11834                                 connector->base.encoder->crtc;
11835                 } else {
11836                         connector->base.state->best_encoder = NULL;
11837                         connector->base.state->crtc = NULL;
11838                 }
11839         }
11840 }
11841
11842 static void
11843 connected_sink_compute_bpp(struct intel_connector *connector,
11844                            struct intel_crtc_state *pipe_config)
11845 {
11846         int bpp = pipe_config->pipe_bpp;
11847
11848         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11849                 connector->base.base.id,
11850                 connector->base.name);
11851
11852         /* Don't use an invalid EDID bpc value */
11853         if (connector->base.display_info.bpc &&
11854             connector->base.display_info.bpc * 3 < bpp) {
11855                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11856                               bpp, connector->base.display_info.bpc*3);
11857                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11858         }
11859
11860         /* Clamp bpp to 8 on screens without EDID 1.4 */
11861         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11862                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11863                               bpp);
11864                 pipe_config->pipe_bpp = 24;
11865         }
11866 }
11867
11868 static int
11869 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11870                           struct intel_crtc_state *pipe_config)
11871 {
11872         struct drm_device *dev = crtc->base.dev;
11873         struct drm_atomic_state *state;
11874         struct drm_connector *connector;
11875         struct drm_connector_state *connector_state;
11876         int bpp, i;
11877
11878         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11879                 bpp = 10*3;
11880         else if (INTEL_INFO(dev)->gen >= 5)
11881                 bpp = 12*3;
11882         else
11883                 bpp = 8*3;
11884
11885
11886         pipe_config->pipe_bpp = bpp;
11887
11888         state = pipe_config->base.state;
11889
11890         /* Clamp display bpp to EDID value */
11891         for_each_connector_in_state(state, connector, connector_state, i) {
11892                 if (connector_state->crtc != &crtc->base)
11893                         continue;
11894
11895                 connected_sink_compute_bpp(to_intel_connector(connector),
11896                                            pipe_config);
11897         }
11898
11899         return bpp;
11900 }
11901
11902 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11903 {
11904         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11905                         "type: 0x%x flags: 0x%x\n",
11906                 mode->crtc_clock,
11907                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11908                 mode->crtc_hsync_end, mode->crtc_htotal,
11909                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11910                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11911 }
11912
11913 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11914                                    struct intel_crtc_state *pipe_config,
11915                                    const char *context)
11916 {
11917         struct drm_device *dev = crtc->base.dev;
11918         struct drm_plane *plane;
11919         struct intel_plane *intel_plane;
11920         struct intel_plane_state *state;
11921         struct drm_framebuffer *fb;
11922
11923         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11924                       context, pipe_config, pipe_name(crtc->pipe));
11925
11926         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11927         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11928                       pipe_config->pipe_bpp, pipe_config->dither);
11929         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11930                       pipe_config->has_pch_encoder,
11931                       pipe_config->fdi_lanes,
11932                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11933                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11934                       pipe_config->fdi_m_n.tu);
11935         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11936                       pipe_config->has_dp_encoder,
11937                       pipe_config->lane_count,
11938                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11939                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11940                       pipe_config->dp_m_n.tu);
11941
11942         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11943                       pipe_config->has_dp_encoder,
11944                       pipe_config->lane_count,
11945                       pipe_config->dp_m2_n2.gmch_m,
11946                       pipe_config->dp_m2_n2.gmch_n,
11947                       pipe_config->dp_m2_n2.link_m,
11948                       pipe_config->dp_m2_n2.link_n,
11949                       pipe_config->dp_m2_n2.tu);
11950
11951         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11952                       pipe_config->has_audio,
11953                       pipe_config->has_infoframe);
11954
11955         DRM_DEBUG_KMS("requested mode:\n");
11956         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11957         DRM_DEBUG_KMS("adjusted mode:\n");
11958         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11959         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11960         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11961         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11962                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11963         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11964                       crtc->num_scalers,
11965                       pipe_config->scaler_state.scaler_users,
11966                       pipe_config->scaler_state.scaler_id);
11967         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11968                       pipe_config->gmch_pfit.control,
11969                       pipe_config->gmch_pfit.pgm_ratios,
11970                       pipe_config->gmch_pfit.lvds_border_bits);
11971         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11972                       pipe_config->pch_pfit.pos,
11973                       pipe_config->pch_pfit.size,
11974                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11975         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11976         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11977
11978         if (IS_BROXTON(dev)) {
11979                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11980                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11981                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11982                               pipe_config->ddi_pll_sel,
11983                               pipe_config->dpll_hw_state.ebb0,
11984                               pipe_config->dpll_hw_state.ebb4,
11985                               pipe_config->dpll_hw_state.pll0,
11986                               pipe_config->dpll_hw_state.pll1,
11987                               pipe_config->dpll_hw_state.pll2,
11988                               pipe_config->dpll_hw_state.pll3,
11989                               pipe_config->dpll_hw_state.pll6,
11990                               pipe_config->dpll_hw_state.pll8,
11991                               pipe_config->dpll_hw_state.pll9,
11992                               pipe_config->dpll_hw_state.pll10,
11993                               pipe_config->dpll_hw_state.pcsdw12);
11994         } else if (IS_SKYLAKE(dev)) {
11995                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11996                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11997                               pipe_config->ddi_pll_sel,
11998                               pipe_config->dpll_hw_state.ctrl1,
11999                               pipe_config->dpll_hw_state.cfgcr1,
12000                               pipe_config->dpll_hw_state.cfgcr2);
12001         } else if (HAS_DDI(dev)) {
12002                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12003                               pipe_config->ddi_pll_sel,
12004                               pipe_config->dpll_hw_state.wrpll);
12005         } else {
12006                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12007                               "fp0: 0x%x, fp1: 0x%x\n",
12008                               pipe_config->dpll_hw_state.dpll,
12009                               pipe_config->dpll_hw_state.dpll_md,
12010                               pipe_config->dpll_hw_state.fp0,
12011                               pipe_config->dpll_hw_state.fp1);
12012         }
12013
12014         DRM_DEBUG_KMS("planes on this crtc\n");
12015         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12016                 intel_plane = to_intel_plane(plane);
12017                 if (intel_plane->pipe != crtc->pipe)
12018                         continue;
12019
12020                 state = to_intel_plane_state(plane->state);
12021                 fb = state->base.fb;
12022                 if (!fb) {
12023                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12024                                 "disabled, scaler_id = %d\n",
12025                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12026                                 plane->base.id, intel_plane->pipe,
12027                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12028                                 drm_plane_index(plane), state->scaler_id);
12029                         continue;
12030                 }
12031
12032                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12033                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12034                         plane->base.id, intel_plane->pipe,
12035                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12036                         drm_plane_index(plane));
12037                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12038                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12039                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12040                         state->scaler_id,
12041                         state->src.x1 >> 16, state->src.y1 >> 16,
12042                         drm_rect_width(&state->src) >> 16,
12043                         drm_rect_height(&state->src) >> 16,
12044                         state->dst.x1, state->dst.y1,
12045                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12046         }
12047 }
12048
12049 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12050 {
12051         struct drm_device *dev = state->dev;
12052         struct intel_encoder *encoder;
12053         struct drm_connector *connector;
12054         struct drm_connector_state *connector_state;
12055         unsigned int used_ports = 0;
12056         int i;
12057
12058         /*
12059          * Walk the connector list instead of the encoder
12060          * list to detect the problem on ddi platforms
12061          * where there's just one encoder per digital port.
12062          */
12063         for_each_connector_in_state(state, connector, connector_state, i) {
12064                 if (!connector_state->best_encoder)
12065                         continue;
12066
12067                 encoder = to_intel_encoder(connector_state->best_encoder);
12068
12069                 WARN_ON(!connector_state->crtc);
12070
12071                 switch (encoder->type) {
12072                         unsigned int port_mask;
12073                 case INTEL_OUTPUT_UNKNOWN:
12074                         if (WARN_ON(!HAS_DDI(dev)))
12075                                 break;
12076                 case INTEL_OUTPUT_DISPLAYPORT:
12077                 case INTEL_OUTPUT_HDMI:
12078                 case INTEL_OUTPUT_EDP:
12079                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12080
12081                         /* the same port mustn't appear more than once */
12082                         if (used_ports & port_mask)
12083                                 return false;
12084
12085                         used_ports |= port_mask;
12086                 default:
12087                         break;
12088                 }
12089         }
12090
12091         return true;
12092 }
12093
12094 static void
12095 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12096 {
12097         struct drm_crtc_state tmp_state;
12098         struct intel_crtc_scaler_state scaler_state;
12099         struct intel_dpll_hw_state dpll_hw_state;
12100         enum intel_dpll_id shared_dpll;
12101         uint32_t ddi_pll_sel;
12102         bool force_thru;
12103
12104         /* FIXME: before the switch to atomic started, a new pipe_config was
12105          * kzalloc'd. Code that depends on any field being zero should be
12106          * fixed, so that the crtc_state can be safely duplicated. For now,
12107          * only fields that are know to not cause problems are preserved. */
12108
12109         tmp_state = crtc_state->base;
12110         scaler_state = crtc_state->scaler_state;
12111         shared_dpll = crtc_state->shared_dpll;
12112         dpll_hw_state = crtc_state->dpll_hw_state;
12113         ddi_pll_sel = crtc_state->ddi_pll_sel;
12114         force_thru = crtc_state->pch_pfit.force_thru;
12115
12116         memset(crtc_state, 0, sizeof *crtc_state);
12117
12118         crtc_state->base = tmp_state;
12119         crtc_state->scaler_state = scaler_state;
12120         crtc_state->shared_dpll = shared_dpll;
12121         crtc_state->dpll_hw_state = dpll_hw_state;
12122         crtc_state->ddi_pll_sel = ddi_pll_sel;
12123         crtc_state->pch_pfit.force_thru = force_thru;
12124 }
12125
12126 static int
12127 intel_modeset_pipe_config(struct drm_crtc *crtc,
12128                           struct intel_crtc_state *pipe_config)
12129 {
12130         struct drm_atomic_state *state = pipe_config->base.state;
12131         struct intel_encoder *encoder;
12132         struct drm_connector *connector;
12133         struct drm_connector_state *connector_state;
12134         int base_bpp, ret = -EINVAL;
12135         int i;
12136         bool retry = true;
12137
12138         clear_intel_crtc_state(pipe_config);
12139
12140         pipe_config->cpu_transcoder =
12141                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12142
12143         /*
12144          * Sanitize sync polarity flags based on requested ones. If neither
12145          * positive or negative polarity is requested, treat this as meaning
12146          * negative polarity.
12147          */
12148         if (!(pipe_config->base.adjusted_mode.flags &
12149               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12150                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12151
12152         if (!(pipe_config->base.adjusted_mode.flags &
12153               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12154                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12155
12156         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12157                                              pipe_config);
12158         if (base_bpp < 0)
12159                 goto fail;
12160
12161         /*
12162          * Determine the real pipe dimensions. Note that stereo modes can
12163          * increase the actual pipe size due to the frame doubling and
12164          * insertion of additional space for blanks between the frame. This
12165          * is stored in the crtc timings. We use the requested mode to do this
12166          * computation to clearly distinguish it from the adjusted mode, which
12167          * can be changed by the connectors in the below retry loop.
12168          */
12169         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12170                                &pipe_config->pipe_src_w,
12171                                &pipe_config->pipe_src_h);
12172
12173 encoder_retry:
12174         /* Ensure the port clock defaults are reset when retrying. */
12175         pipe_config->port_clock = 0;
12176         pipe_config->pixel_multiplier = 1;
12177
12178         /* Fill in default crtc timings, allow encoders to overwrite them. */
12179         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12180                               CRTC_STEREO_DOUBLE);
12181
12182         /* Pass our mode to the connectors and the CRTC to give them a chance to
12183          * adjust it according to limitations or connector properties, and also
12184          * a chance to reject the mode entirely.
12185          */
12186         for_each_connector_in_state(state, connector, connector_state, i) {
12187                 if (connector_state->crtc != crtc)
12188                         continue;
12189
12190                 encoder = to_intel_encoder(connector_state->best_encoder);
12191
12192                 if (!(encoder->compute_config(encoder, pipe_config))) {
12193                         DRM_DEBUG_KMS("Encoder config failure\n");
12194                         goto fail;
12195                 }
12196         }
12197
12198         /* Set default port clock if not overwritten by the encoder. Needs to be
12199          * done afterwards in case the encoder adjusts the mode. */
12200         if (!pipe_config->port_clock)
12201                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12202                         * pipe_config->pixel_multiplier;
12203
12204         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12205         if (ret < 0) {
12206                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12207                 goto fail;
12208         }
12209
12210         if (ret == RETRY) {
12211                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12212                         ret = -EINVAL;
12213                         goto fail;
12214                 }
12215
12216                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12217                 retry = false;
12218                 goto encoder_retry;
12219         }
12220
12221         /* Dithering seems to not pass-through bits correctly when it should, so
12222          * only enable it on 6bpc panels. */
12223         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12224         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12225                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12226
12227 fail:
12228         return ret;
12229 }
12230
12231 static void
12232 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12233 {
12234         struct drm_crtc *crtc;
12235         struct drm_crtc_state *crtc_state;
12236         int i;
12237
12238         /* Double check state. */
12239         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12240                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12241
12242                 /* Update hwmode for vblank functions */
12243                 if (crtc->state->active)
12244                         crtc->hwmode = crtc->state->adjusted_mode;
12245                 else
12246                         crtc->hwmode.crtc_clock = 0;
12247         }
12248 }
12249
12250 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12251 {
12252         int diff;
12253
12254         if (clock1 == clock2)
12255                 return true;
12256
12257         if (!clock1 || !clock2)
12258                 return false;
12259
12260         diff = abs(clock1 - clock2);
12261
12262         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12263                 return true;
12264
12265         return false;
12266 }
12267
12268 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12269         list_for_each_entry((intel_crtc), \
12270                             &(dev)->mode_config.crtc_list, \
12271                             base.head) \
12272                 if (mask & (1 <<(intel_crtc)->pipe))
12273
12274 static bool
12275 intel_compare_m_n(unsigned int m, unsigned int n,
12276                   unsigned int m2, unsigned int n2,
12277                   bool exact)
12278 {
12279         if (m == m2 && n == n2)
12280                 return true;
12281
12282         if (exact || !m || !n || !m2 || !n2)
12283                 return false;
12284
12285         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12286
12287         if (m > m2) {
12288                 while (m > m2) {
12289                         m2 <<= 1;
12290                         n2 <<= 1;
12291                 }
12292         } else if (m < m2) {
12293                 while (m < m2) {
12294                         m <<= 1;
12295                         n <<= 1;
12296                 }
12297         }
12298
12299         return m == m2 && n == n2;
12300 }
12301
12302 static bool
12303 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12304                        struct intel_link_m_n *m2_n2,
12305                        bool adjust)
12306 {
12307         if (m_n->tu == m2_n2->tu &&
12308             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12309                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12310             intel_compare_m_n(m_n->link_m, m_n->link_n,
12311                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12312                 if (adjust)
12313                         *m2_n2 = *m_n;
12314
12315                 return true;
12316         }
12317
12318         return false;
12319 }
12320
12321 static bool
12322 intel_pipe_config_compare(struct drm_device *dev,
12323                           struct intel_crtc_state *current_config,
12324                           struct intel_crtc_state *pipe_config,
12325                           bool adjust)
12326 {
12327         bool ret = true;
12328
12329 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12330         do { \
12331                 if (!adjust) \
12332                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12333                 else \
12334                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12335         } while (0)
12336
12337 #define PIPE_CONF_CHECK_X(name) \
12338         if (current_config->name != pipe_config->name) { \
12339                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12340                           "(expected 0x%08x, found 0x%08x)\n", \
12341                           current_config->name, \
12342                           pipe_config->name); \
12343                 ret = false; \
12344         }
12345
12346 #define PIPE_CONF_CHECK_I(name) \
12347         if (current_config->name != pipe_config->name) { \
12348                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12349                           "(expected %i, found %i)\n", \
12350                           current_config->name, \
12351                           pipe_config->name); \
12352                 ret = false; \
12353         }
12354
12355 #define PIPE_CONF_CHECK_M_N(name) \
12356         if (!intel_compare_link_m_n(&current_config->name, \
12357                                     &pipe_config->name,\
12358                                     adjust)) { \
12359                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12360                           "(expected tu %i gmch %i/%i link %i/%i, " \
12361                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12362                           current_config->name.tu, \
12363                           current_config->name.gmch_m, \
12364                           current_config->name.gmch_n, \
12365                           current_config->name.link_m, \
12366                           current_config->name.link_n, \
12367                           pipe_config->name.tu, \
12368                           pipe_config->name.gmch_m, \
12369                           pipe_config->name.gmch_n, \
12370                           pipe_config->name.link_m, \
12371                           pipe_config->name.link_n); \
12372                 ret = false; \
12373         }
12374
12375 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12376         if (!intel_compare_link_m_n(&current_config->name, \
12377                                     &pipe_config->name, adjust) && \
12378             !intel_compare_link_m_n(&current_config->alt_name, \
12379                                     &pipe_config->name, adjust)) { \
12380                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12381                           "(expected tu %i gmch %i/%i link %i/%i, " \
12382                           "or tu %i gmch %i/%i link %i/%i, " \
12383                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12384                           current_config->name.tu, \
12385                           current_config->name.gmch_m, \
12386                           current_config->name.gmch_n, \
12387                           current_config->name.link_m, \
12388                           current_config->name.link_n, \
12389                           current_config->alt_name.tu, \
12390                           current_config->alt_name.gmch_m, \
12391                           current_config->alt_name.gmch_n, \
12392                           current_config->alt_name.link_m, \
12393                           current_config->alt_name.link_n, \
12394                           pipe_config->name.tu, \
12395                           pipe_config->name.gmch_m, \
12396                           pipe_config->name.gmch_n, \
12397                           pipe_config->name.link_m, \
12398                           pipe_config->name.link_n); \
12399                 ret = false; \
12400         }
12401
12402 /* This is required for BDW+ where there is only one set of registers for
12403  * switching between high and low RR.
12404  * This macro can be used whenever a comparison has to be made between one
12405  * hw state and multiple sw state variables.
12406  */
12407 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12408         if ((current_config->name != pipe_config->name) && \
12409                 (current_config->alt_name != pipe_config->name)) { \
12410                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12411                                   "(expected %i or %i, found %i)\n", \
12412                                   current_config->name, \
12413                                   current_config->alt_name, \
12414                                   pipe_config->name); \
12415                         ret = false; \
12416         }
12417
12418 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12419         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12420                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12421                           "(expected %i, found %i)\n", \
12422                           current_config->name & (mask), \
12423                           pipe_config->name & (mask)); \
12424                 ret = false; \
12425         }
12426
12427 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12428         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12429                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12430                           "(expected %i, found %i)\n", \
12431                           current_config->name, \
12432                           pipe_config->name); \
12433                 ret = false; \
12434         }
12435
12436 #define PIPE_CONF_QUIRK(quirk)  \
12437         ((current_config->quirks | pipe_config->quirks) & (quirk))
12438
12439         PIPE_CONF_CHECK_I(cpu_transcoder);
12440
12441         PIPE_CONF_CHECK_I(has_pch_encoder);
12442         PIPE_CONF_CHECK_I(fdi_lanes);
12443         PIPE_CONF_CHECK_M_N(fdi_m_n);
12444
12445         PIPE_CONF_CHECK_I(has_dp_encoder);
12446         PIPE_CONF_CHECK_I(lane_count);
12447
12448         if (INTEL_INFO(dev)->gen < 8) {
12449                 PIPE_CONF_CHECK_M_N(dp_m_n);
12450
12451                 PIPE_CONF_CHECK_I(has_drrs);
12452                 if (current_config->has_drrs)
12453                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12454         } else
12455                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12456
12457         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12458         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12459         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12460         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12461         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12462         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12463
12464         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12465         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12466         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12467         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12468         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12469         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12470
12471         PIPE_CONF_CHECK_I(pixel_multiplier);
12472         PIPE_CONF_CHECK_I(has_hdmi_sink);
12473         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12474             IS_VALLEYVIEW(dev))
12475                 PIPE_CONF_CHECK_I(limited_color_range);
12476         PIPE_CONF_CHECK_I(has_infoframe);
12477
12478         PIPE_CONF_CHECK_I(has_audio);
12479
12480         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12481                               DRM_MODE_FLAG_INTERLACE);
12482
12483         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12484                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12485                                       DRM_MODE_FLAG_PHSYNC);
12486                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12487                                       DRM_MODE_FLAG_NHSYNC);
12488                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12489                                       DRM_MODE_FLAG_PVSYNC);
12490                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12491                                       DRM_MODE_FLAG_NVSYNC);
12492         }
12493
12494         PIPE_CONF_CHECK_X(gmch_pfit.control);
12495         /* pfit ratios are autocomputed by the hw on gen4+ */
12496         if (INTEL_INFO(dev)->gen < 4)
12497                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12498         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12499
12500         if (!adjust) {
12501                 PIPE_CONF_CHECK_I(pipe_src_w);
12502                 PIPE_CONF_CHECK_I(pipe_src_h);
12503
12504                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12505                 if (current_config->pch_pfit.enabled) {
12506                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12507                         PIPE_CONF_CHECK_X(pch_pfit.size);
12508                 }
12509
12510                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12511         }
12512
12513         /* BDW+ don't expose a synchronous way to read the state */
12514         if (IS_HASWELL(dev))
12515                 PIPE_CONF_CHECK_I(ips_enabled);
12516
12517         PIPE_CONF_CHECK_I(double_wide);
12518
12519         PIPE_CONF_CHECK_X(ddi_pll_sel);
12520
12521         PIPE_CONF_CHECK_I(shared_dpll);
12522         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12523         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12524         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12525         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12526         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12527         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12528         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12529         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12530
12531         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12532                 PIPE_CONF_CHECK_I(pipe_bpp);
12533
12534         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12535         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12536
12537 #undef PIPE_CONF_CHECK_X
12538 #undef PIPE_CONF_CHECK_I
12539 #undef PIPE_CONF_CHECK_I_ALT
12540 #undef PIPE_CONF_CHECK_FLAGS
12541 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12542 #undef PIPE_CONF_QUIRK
12543 #undef INTEL_ERR_OR_DBG_KMS
12544
12545         return ret;
12546 }
12547
12548 static void check_wm_state(struct drm_device *dev)
12549 {
12550         struct drm_i915_private *dev_priv = dev->dev_private;
12551         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12552         struct intel_crtc *intel_crtc;
12553         int plane;
12554
12555         if (INTEL_INFO(dev)->gen < 9)
12556                 return;
12557
12558         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12559         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12560
12561         for_each_intel_crtc(dev, intel_crtc) {
12562                 struct skl_ddb_entry *hw_entry, *sw_entry;
12563                 const enum pipe pipe = intel_crtc->pipe;
12564
12565                 if (!intel_crtc->active)
12566                         continue;
12567
12568                 /* planes */
12569                 for_each_plane(dev_priv, pipe, plane) {
12570                         hw_entry = &hw_ddb.plane[pipe][plane];
12571                         sw_entry = &sw_ddb->plane[pipe][plane];
12572
12573                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12574                                 continue;
12575
12576                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12577                                   "(expected (%u,%u), found (%u,%u))\n",
12578                                   pipe_name(pipe), plane + 1,
12579                                   sw_entry->start, sw_entry->end,
12580                                   hw_entry->start, hw_entry->end);
12581                 }
12582
12583                 /* cursor */
12584                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12585                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12586
12587                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12588                         continue;
12589
12590                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12591                           "(expected (%u,%u), found (%u,%u))\n",
12592                           pipe_name(pipe),
12593                           sw_entry->start, sw_entry->end,
12594                           hw_entry->start, hw_entry->end);
12595         }
12596 }
12597
12598 static void
12599 check_connector_state(struct drm_device *dev,
12600                       struct drm_atomic_state *old_state)
12601 {
12602         struct drm_connector_state *old_conn_state;
12603         struct drm_connector *connector;
12604         int i;
12605
12606         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12607                 struct drm_encoder *encoder = connector->encoder;
12608                 struct drm_connector_state *state = connector->state;
12609
12610                 /* This also checks the encoder/connector hw state with the
12611                  * ->get_hw_state callbacks. */
12612                 intel_connector_check_state(to_intel_connector(connector));
12613
12614                 I915_STATE_WARN(state->best_encoder != encoder,
12615                      "connector's atomic encoder doesn't match legacy encoder\n");
12616         }
12617 }
12618
12619 static void
12620 check_encoder_state(struct drm_device *dev)
12621 {
12622         struct intel_encoder *encoder;
12623         struct intel_connector *connector;
12624
12625         for_each_intel_encoder(dev, encoder) {
12626                 bool enabled = false;
12627                 enum pipe pipe;
12628
12629                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12630                               encoder->base.base.id,
12631                               encoder->base.name);
12632
12633                 for_each_intel_connector(dev, connector) {
12634                         if (connector->base.state->best_encoder != &encoder->base)
12635                                 continue;
12636                         enabled = true;
12637
12638                         I915_STATE_WARN(connector->base.state->crtc !=
12639                                         encoder->base.crtc,
12640                              "connector's crtc doesn't match encoder crtc\n");
12641                 }
12642
12643                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12644                      "encoder's enabled state mismatch "
12645                      "(expected %i, found %i)\n",
12646                      !!encoder->base.crtc, enabled);
12647
12648                 if (!encoder->base.crtc) {
12649                         bool active;
12650
12651                         active = encoder->get_hw_state(encoder, &pipe);
12652                         I915_STATE_WARN(active,
12653                              "encoder detached but still enabled on pipe %c.\n",
12654                              pipe_name(pipe));
12655                 }
12656         }
12657 }
12658
12659 static void
12660 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12661 {
12662         struct drm_i915_private *dev_priv = dev->dev_private;
12663         struct intel_encoder *encoder;
12664         struct drm_crtc_state *old_crtc_state;
12665         struct drm_crtc *crtc;
12666         int i;
12667
12668         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12669                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12670                 struct intel_crtc_state *pipe_config, *sw_config;
12671                 bool active;
12672
12673                 if (!needs_modeset(crtc->state) &&
12674                     !to_intel_crtc_state(crtc->state)->update_pipe)
12675                         continue;
12676
12677                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12678                 pipe_config = to_intel_crtc_state(old_crtc_state);
12679                 memset(pipe_config, 0, sizeof(*pipe_config));
12680                 pipe_config->base.crtc = crtc;
12681                 pipe_config->base.state = old_state;
12682
12683                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12684                               crtc->base.id);
12685
12686                 active = dev_priv->display.get_pipe_config(intel_crtc,
12687                                                            pipe_config);
12688
12689                 /* hw state is inconsistent with the pipe quirk */
12690                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12691                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12692                         active = crtc->state->active;
12693
12694                 I915_STATE_WARN(crtc->state->active != active,
12695                      "crtc active state doesn't match with hw state "
12696                      "(expected %i, found %i)\n", crtc->state->active, active);
12697
12698                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12699                      "transitional active state does not match atomic hw state "
12700                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12701
12702                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12703                         enum pipe pipe;
12704
12705                         active = encoder->get_hw_state(encoder, &pipe);
12706                         I915_STATE_WARN(active != crtc->state->active,
12707                                 "[ENCODER:%i] active %i with crtc active %i\n",
12708                                 encoder->base.base.id, active, crtc->state->active);
12709
12710                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12711                                         "Encoder connected to wrong pipe %c\n",
12712                                         pipe_name(pipe));
12713
12714                         if (active)
12715                                 encoder->get_config(encoder, pipe_config);
12716                 }
12717
12718                 if (!crtc->state->active)
12719                         continue;
12720
12721                 sw_config = to_intel_crtc_state(crtc->state);
12722                 if (!intel_pipe_config_compare(dev, sw_config,
12723                                                pipe_config, false)) {
12724                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12725                         intel_dump_pipe_config(intel_crtc, pipe_config,
12726                                                "[hw state]");
12727                         intel_dump_pipe_config(intel_crtc, sw_config,
12728                                                "[sw state]");
12729                 }
12730         }
12731 }
12732
12733 static void
12734 check_shared_dpll_state(struct drm_device *dev)
12735 {
12736         struct drm_i915_private *dev_priv = dev->dev_private;
12737         struct intel_crtc *crtc;
12738         struct intel_dpll_hw_state dpll_hw_state;
12739         int i;
12740
12741         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12742                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12743                 int enabled_crtcs = 0, active_crtcs = 0;
12744                 bool active;
12745
12746                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12747
12748                 DRM_DEBUG_KMS("%s\n", pll->name);
12749
12750                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12751
12752                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12753                      "more active pll users than references: %i vs %i\n",
12754                      pll->active, hweight32(pll->config.crtc_mask));
12755                 I915_STATE_WARN(pll->active && !pll->on,
12756                      "pll in active use but not on in sw tracking\n");
12757                 I915_STATE_WARN(pll->on && !pll->active,
12758                      "pll in on but not on in use in sw tracking\n");
12759                 I915_STATE_WARN(pll->on != active,
12760                      "pll on state mismatch (expected %i, found %i)\n",
12761                      pll->on, active);
12762
12763                 for_each_intel_crtc(dev, crtc) {
12764                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12765                                 enabled_crtcs++;
12766                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12767                                 active_crtcs++;
12768                 }
12769                 I915_STATE_WARN(pll->active != active_crtcs,
12770                      "pll active crtcs mismatch (expected %i, found %i)\n",
12771                      pll->active, active_crtcs);
12772                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12773                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12774                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12775
12776                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12777                                        sizeof(dpll_hw_state)),
12778                      "pll hw state mismatch\n");
12779         }
12780 }
12781
12782 static void
12783 intel_modeset_check_state(struct drm_device *dev,
12784                           struct drm_atomic_state *old_state)
12785 {
12786         check_wm_state(dev);
12787         check_connector_state(dev, old_state);
12788         check_encoder_state(dev);
12789         check_crtc_state(dev, old_state);
12790         check_shared_dpll_state(dev);
12791 }
12792
12793 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12794                                      int dotclock)
12795 {
12796         /*
12797          * FDI already provided one idea for the dotclock.
12798          * Yell if the encoder disagrees.
12799          */
12800         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12801              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12802              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12803 }
12804
12805 static void update_scanline_offset(struct intel_crtc *crtc)
12806 {
12807         struct drm_device *dev = crtc->base.dev;
12808
12809         /*
12810          * The scanline counter increments at the leading edge of hsync.
12811          *
12812          * On most platforms it starts counting from vtotal-1 on the
12813          * first active line. That means the scanline counter value is
12814          * always one less than what we would expect. Ie. just after
12815          * start of vblank, which also occurs at start of hsync (on the
12816          * last active line), the scanline counter will read vblank_start-1.
12817          *
12818          * On gen2 the scanline counter starts counting from 1 instead
12819          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12820          * to keep the value positive), instead of adding one.
12821          *
12822          * On HSW+ the behaviour of the scanline counter depends on the output
12823          * type. For DP ports it behaves like most other platforms, but on HDMI
12824          * there's an extra 1 line difference. So we need to add two instead of
12825          * one to the value.
12826          */
12827         if (IS_GEN2(dev)) {
12828                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12829                 int vtotal;
12830
12831                 vtotal = adjusted_mode->crtc_vtotal;
12832                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12833                         vtotal /= 2;
12834
12835                 crtc->scanline_offset = vtotal - 1;
12836         } else if (HAS_DDI(dev) &&
12837                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12838                 crtc->scanline_offset = 2;
12839         } else
12840                 crtc->scanline_offset = 1;
12841 }
12842
12843 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12844 {
12845         struct drm_device *dev = state->dev;
12846         struct drm_i915_private *dev_priv = to_i915(dev);
12847         struct intel_shared_dpll_config *shared_dpll = NULL;
12848         struct intel_crtc *intel_crtc;
12849         struct intel_crtc_state *intel_crtc_state;
12850         struct drm_crtc *crtc;
12851         struct drm_crtc_state *crtc_state;
12852         int i;
12853
12854         if (!dev_priv->display.crtc_compute_clock)
12855                 return;
12856
12857         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12858                 int dpll;
12859
12860                 intel_crtc = to_intel_crtc(crtc);
12861                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12862                 dpll = intel_crtc_state->shared_dpll;
12863
12864                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12865                         continue;
12866
12867                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12868
12869                 if (!shared_dpll)
12870                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12871
12872                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12873         }
12874 }
12875
12876 /*
12877  * This implements the workaround described in the "notes" section of the mode
12878  * set sequence documentation. When going from no pipes or single pipe to
12879  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12880  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12881  */
12882 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12883 {
12884         struct drm_crtc_state *crtc_state;
12885         struct intel_crtc *intel_crtc;
12886         struct drm_crtc *crtc;
12887         struct intel_crtc_state *first_crtc_state = NULL;
12888         struct intel_crtc_state *other_crtc_state = NULL;
12889         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12890         int i;
12891
12892         /* look at all crtc's that are going to be enabled in during modeset */
12893         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12894                 intel_crtc = to_intel_crtc(crtc);
12895
12896                 if (!crtc_state->active || !needs_modeset(crtc_state))
12897                         continue;
12898
12899                 if (first_crtc_state) {
12900                         other_crtc_state = to_intel_crtc_state(crtc_state);
12901                         break;
12902                 } else {
12903                         first_crtc_state = to_intel_crtc_state(crtc_state);
12904                         first_pipe = intel_crtc->pipe;
12905                 }
12906         }
12907
12908         /* No workaround needed? */
12909         if (!first_crtc_state)
12910                 return 0;
12911
12912         /* w/a possibly needed, check how many crtc's are already enabled. */
12913         for_each_intel_crtc(state->dev, intel_crtc) {
12914                 struct intel_crtc_state *pipe_config;
12915
12916                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12917                 if (IS_ERR(pipe_config))
12918                         return PTR_ERR(pipe_config);
12919
12920                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12921
12922                 if (!pipe_config->base.active ||
12923                     needs_modeset(&pipe_config->base))
12924                         continue;
12925
12926                 /* 2 or more enabled crtcs means no need for w/a */
12927                 if (enabled_pipe != INVALID_PIPE)
12928                         return 0;
12929
12930                 enabled_pipe = intel_crtc->pipe;
12931         }
12932
12933         if (enabled_pipe != INVALID_PIPE)
12934                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12935         else if (other_crtc_state)
12936                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12937
12938         return 0;
12939 }
12940
12941 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12942 {
12943         struct drm_crtc *crtc;
12944         struct drm_crtc_state *crtc_state;
12945         int ret = 0;
12946
12947         /* add all active pipes to the state */
12948         for_each_crtc(state->dev, crtc) {
12949                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12950                 if (IS_ERR(crtc_state))
12951                         return PTR_ERR(crtc_state);
12952
12953                 if (!crtc_state->active || needs_modeset(crtc_state))
12954                         continue;
12955
12956                 crtc_state->mode_changed = true;
12957
12958                 ret = drm_atomic_add_affected_connectors(state, crtc);
12959                 if (ret)
12960                         break;
12961
12962                 ret = drm_atomic_add_affected_planes(state, crtc);
12963                 if (ret)
12964                         break;
12965         }
12966
12967         return ret;
12968 }
12969
12970 static int intel_modeset_checks(struct drm_atomic_state *state)
12971 {
12972         struct drm_device *dev = state->dev;
12973         struct drm_i915_private *dev_priv = dev->dev_private;
12974         int ret;
12975
12976         if (!check_digital_port_conflicts(state)) {
12977                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12978                 return -EINVAL;
12979         }
12980
12981         /*
12982          * See if the config requires any additional preparation, e.g.
12983          * to adjust global state with pipes off.  We need to do this
12984          * here so we can get the modeset_pipe updated config for the new
12985          * mode set on this crtc.  For other crtcs we need to use the
12986          * adjusted_mode bits in the crtc directly.
12987          */
12988         if (dev_priv->display.modeset_calc_cdclk) {
12989                 unsigned int cdclk;
12990
12991                 ret = dev_priv->display.modeset_calc_cdclk(state);
12992
12993                 cdclk = to_intel_atomic_state(state)->cdclk;
12994                 if (!ret && cdclk != dev_priv->cdclk_freq)
12995                         ret = intel_modeset_all_pipes(state);
12996
12997                 if (ret < 0)
12998                         return ret;
12999         } else
13000                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13001
13002         intel_modeset_clear_plls(state);
13003
13004         if (IS_HASWELL(dev))
13005                 return haswell_mode_set_planes_workaround(state);
13006
13007         return 0;
13008 }
13009
13010 /**
13011  * intel_atomic_check - validate state object
13012  * @dev: drm device
13013  * @state: state to validate
13014  */
13015 static int intel_atomic_check(struct drm_device *dev,
13016                               struct drm_atomic_state *state)
13017 {
13018         struct drm_crtc *crtc;
13019         struct drm_crtc_state *crtc_state;
13020         int ret, i;
13021         bool any_ms = false;
13022
13023         ret = drm_atomic_helper_check_modeset(dev, state);
13024         if (ret)
13025                 return ret;
13026
13027         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13028                 struct intel_crtc_state *pipe_config =
13029                         to_intel_crtc_state(crtc_state);
13030
13031                 /* Catch I915_MODE_FLAG_INHERITED */
13032                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13033                         crtc_state->mode_changed = true;
13034
13035                 if (!crtc_state->enable) {
13036                         if (needs_modeset(crtc_state))
13037                                 any_ms = true;
13038                         continue;
13039                 }
13040
13041                 if (!needs_modeset(crtc_state))
13042                         continue;
13043
13044                 /* FIXME: For only active_changed we shouldn't need to do any
13045                  * state recomputation at all. */
13046
13047                 ret = drm_atomic_add_affected_connectors(state, crtc);
13048                 if (ret)
13049                         return ret;
13050
13051                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13052                 if (ret)
13053                         return ret;
13054
13055                 if (intel_pipe_config_compare(state->dev,
13056                                         to_intel_crtc_state(crtc->state),
13057                                         pipe_config, true)) {
13058                         crtc_state->mode_changed = false;
13059                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13060                 }
13061
13062                 if (needs_modeset(crtc_state)) {
13063                         any_ms = true;
13064
13065                         ret = drm_atomic_add_affected_planes(state, crtc);
13066                         if (ret)
13067                                 return ret;
13068                 }
13069
13070                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13071                                        needs_modeset(crtc_state) ?
13072                                        "[modeset]" : "[fastset]");
13073         }
13074
13075         if (any_ms) {
13076                 ret = intel_modeset_checks(state);
13077
13078                 if (ret)
13079                         return ret;
13080         } else
13081                 to_intel_atomic_state(state)->cdclk =
13082                         to_i915(state->dev)->cdclk_freq;
13083
13084         return drm_atomic_helper_check_planes(state->dev, state);
13085 }
13086
13087 /**
13088  * intel_atomic_commit - commit validated state object
13089  * @dev: DRM device
13090  * @state: the top-level driver state object
13091  * @async: asynchronous commit
13092  *
13093  * This function commits a top-level state object that has been validated
13094  * with drm_atomic_helper_check().
13095  *
13096  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13097  * we can only handle plane-related operations and do not yet support
13098  * asynchronous commit.
13099  *
13100  * RETURNS
13101  * Zero for success or -errno.
13102  */
13103 static int intel_atomic_commit(struct drm_device *dev,
13104                                struct drm_atomic_state *state,
13105                                bool async)
13106 {
13107         struct drm_i915_private *dev_priv = dev->dev_private;
13108         struct drm_crtc *crtc;
13109         struct drm_crtc_state *crtc_state;
13110         int ret = 0;
13111         int i;
13112         bool any_ms = false;
13113
13114         if (async) {
13115                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13116                 return -EINVAL;
13117         }
13118
13119         ret = drm_atomic_helper_prepare_planes(dev, state);
13120         if (ret)
13121                 return ret;
13122
13123         drm_atomic_helper_swap_state(dev, state);
13124
13125         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13126                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13127
13128                 if (!needs_modeset(crtc->state))
13129                         continue;
13130
13131                 any_ms = true;
13132                 intel_pre_plane_update(intel_crtc);
13133
13134                 if (crtc_state->active) {
13135                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13136                         dev_priv->display.crtc_disable(crtc);
13137                         intel_crtc->active = false;
13138                         intel_disable_shared_dpll(intel_crtc);
13139                 }
13140         }
13141
13142         /* Only after disabling all output pipelines that will be changed can we
13143          * update the the output configuration. */
13144         intel_modeset_update_crtc_state(state);
13145
13146         if (any_ms) {
13147                 intel_shared_dpll_commit(state);
13148
13149                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13150                 modeset_update_crtc_power_domains(state);
13151         }
13152
13153         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13154         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13155                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13156                 bool modeset = needs_modeset(crtc->state);
13157                 bool update_pipe = !modeset &&
13158                         to_intel_crtc_state(crtc->state)->update_pipe;
13159                 unsigned long put_domains = 0;
13160
13161                 if (modeset && crtc->state->active) {
13162                         update_scanline_offset(to_intel_crtc(crtc));
13163                         dev_priv->display.crtc_enable(crtc);
13164                 }
13165
13166                 if (update_pipe) {
13167                         put_domains = modeset_get_crtc_power_domains(crtc);
13168
13169                         /* make sure intel_modeset_check_state runs */
13170                         any_ms = true;
13171                 }
13172
13173                 if (!modeset)
13174                         intel_pre_plane_update(intel_crtc);
13175
13176                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13177
13178                 if (put_domains)
13179                         modeset_put_power_domains(dev_priv, put_domains);
13180
13181                 intel_post_plane_update(intel_crtc);
13182         }
13183
13184         /* FIXME: add subpixel order */
13185
13186         drm_atomic_helper_wait_for_vblanks(dev, state);
13187         drm_atomic_helper_cleanup_planes(dev, state);
13188
13189         if (any_ms)
13190                 intel_modeset_check_state(dev, state);
13191
13192         drm_atomic_state_free(state);
13193
13194         return 0;
13195 }
13196
13197 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13198 {
13199         struct drm_device *dev = crtc->dev;
13200         struct drm_atomic_state *state;
13201         struct drm_crtc_state *crtc_state;
13202         int ret;
13203
13204         state = drm_atomic_state_alloc(dev);
13205         if (!state) {
13206                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13207                               crtc->base.id);
13208                 return;
13209         }
13210
13211         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13212
13213 retry:
13214         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13215         ret = PTR_ERR_OR_ZERO(crtc_state);
13216         if (!ret) {
13217                 if (!crtc_state->active)
13218                         goto out;
13219
13220                 crtc_state->mode_changed = true;
13221                 ret = drm_atomic_commit(state);
13222         }
13223
13224         if (ret == -EDEADLK) {
13225                 drm_atomic_state_clear(state);
13226                 drm_modeset_backoff(state->acquire_ctx);
13227                 goto retry;
13228         }
13229
13230         if (ret)
13231 out:
13232                 drm_atomic_state_free(state);
13233 }
13234
13235 #undef for_each_intel_crtc_masked
13236
13237 static const struct drm_crtc_funcs intel_crtc_funcs = {
13238         .gamma_set = intel_crtc_gamma_set,
13239         .set_config = drm_atomic_helper_set_config,
13240         .destroy = intel_crtc_destroy,
13241         .page_flip = intel_crtc_page_flip,
13242         .atomic_duplicate_state = intel_crtc_duplicate_state,
13243         .atomic_destroy_state = intel_crtc_destroy_state,
13244 };
13245
13246 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13247                                       struct intel_shared_dpll *pll,
13248                                       struct intel_dpll_hw_state *hw_state)
13249 {
13250         uint32_t val;
13251
13252         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13253                 return false;
13254
13255         val = I915_READ(PCH_DPLL(pll->id));
13256         hw_state->dpll = val;
13257         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13258         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13259
13260         return val & DPLL_VCO_ENABLE;
13261 }
13262
13263 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13264                                   struct intel_shared_dpll *pll)
13265 {
13266         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13267         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13268 }
13269
13270 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13271                                 struct intel_shared_dpll *pll)
13272 {
13273         /* PCH refclock must be enabled first */
13274         ibx_assert_pch_refclk_enabled(dev_priv);
13275
13276         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13277
13278         /* Wait for the clocks to stabilize. */
13279         POSTING_READ(PCH_DPLL(pll->id));
13280         udelay(150);
13281
13282         /* The pixel multiplier can only be updated once the
13283          * DPLL is enabled and the clocks are stable.
13284          *
13285          * So write it again.
13286          */
13287         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13288         POSTING_READ(PCH_DPLL(pll->id));
13289         udelay(200);
13290 }
13291
13292 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13293                                  struct intel_shared_dpll *pll)
13294 {
13295         struct drm_device *dev = dev_priv->dev;
13296         struct intel_crtc *crtc;
13297
13298         /* Make sure no transcoder isn't still depending on us. */
13299         for_each_intel_crtc(dev, crtc) {
13300                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13301                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13302         }
13303
13304         I915_WRITE(PCH_DPLL(pll->id), 0);
13305         POSTING_READ(PCH_DPLL(pll->id));
13306         udelay(200);
13307 }
13308
13309 static char *ibx_pch_dpll_names[] = {
13310         "PCH DPLL A",
13311         "PCH DPLL B",
13312 };
13313
13314 static void ibx_pch_dpll_init(struct drm_device *dev)
13315 {
13316         struct drm_i915_private *dev_priv = dev->dev_private;
13317         int i;
13318
13319         dev_priv->num_shared_dpll = 2;
13320
13321         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13322                 dev_priv->shared_dplls[i].id = i;
13323                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13324                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13325                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13326                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13327                 dev_priv->shared_dplls[i].get_hw_state =
13328                         ibx_pch_dpll_get_hw_state;
13329         }
13330 }
13331
13332 static void intel_shared_dpll_init(struct drm_device *dev)
13333 {
13334         struct drm_i915_private *dev_priv = dev->dev_private;
13335
13336         if (HAS_DDI(dev))
13337                 intel_ddi_pll_init(dev);
13338         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13339                 ibx_pch_dpll_init(dev);
13340         else
13341                 dev_priv->num_shared_dpll = 0;
13342
13343         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13344 }
13345
13346 /**
13347  * intel_prepare_plane_fb - Prepare fb for usage on plane
13348  * @plane: drm plane to prepare for
13349  * @fb: framebuffer to prepare for presentation
13350  *
13351  * Prepares a framebuffer for usage on a display plane.  Generally this
13352  * involves pinning the underlying object and updating the frontbuffer tracking
13353  * bits.  Some older platforms need special physical address handling for
13354  * cursor planes.
13355  *
13356  * Returns 0 on success, negative error code on failure.
13357  */
13358 int
13359 intel_prepare_plane_fb(struct drm_plane *plane,
13360                        const struct drm_plane_state *new_state)
13361 {
13362         struct drm_device *dev = plane->dev;
13363         struct drm_framebuffer *fb = new_state->fb;
13364         struct intel_plane *intel_plane = to_intel_plane(plane);
13365         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13366         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13367         int ret = 0;
13368
13369         if (!obj)
13370                 return 0;
13371
13372         mutex_lock(&dev->struct_mutex);
13373
13374         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13375             INTEL_INFO(dev)->cursor_needs_physical) {
13376                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13377                 ret = i915_gem_object_attach_phys(obj, align);
13378                 if (ret)
13379                         DRM_DEBUG_KMS("failed to attach phys object\n");
13380         } else {
13381                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13382         }
13383
13384         if (ret == 0)
13385                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13386
13387         mutex_unlock(&dev->struct_mutex);
13388
13389         return ret;
13390 }
13391
13392 /**
13393  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13394  * @plane: drm plane to clean up for
13395  * @fb: old framebuffer that was on plane
13396  *
13397  * Cleans up a framebuffer that has just been removed from a plane.
13398  */
13399 void
13400 intel_cleanup_plane_fb(struct drm_plane *plane,
13401                        const struct drm_plane_state *old_state)
13402 {
13403         struct drm_device *dev = plane->dev;
13404         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13405
13406         if (!obj)
13407                 return;
13408
13409         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13410             !INTEL_INFO(dev)->cursor_needs_physical) {
13411                 mutex_lock(&dev->struct_mutex);
13412                 intel_unpin_fb_obj(old_state->fb, old_state);
13413                 mutex_unlock(&dev->struct_mutex);
13414         }
13415 }
13416
13417 int
13418 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13419 {
13420         int max_scale;
13421         struct drm_device *dev;
13422         struct drm_i915_private *dev_priv;
13423         int crtc_clock, cdclk;
13424
13425         if (!intel_crtc || !crtc_state)
13426                 return DRM_PLANE_HELPER_NO_SCALING;
13427
13428         dev = intel_crtc->base.dev;
13429         dev_priv = dev->dev_private;
13430         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13431         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13432
13433         if (!crtc_clock || !cdclk)
13434                 return DRM_PLANE_HELPER_NO_SCALING;
13435
13436         /*
13437          * skl max scale is lower of:
13438          *    close to 3 but not 3, -1 is for that purpose
13439          *            or
13440          *    cdclk/crtc_clock
13441          */
13442         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13443
13444         return max_scale;
13445 }
13446
13447 static int
13448 intel_check_primary_plane(struct drm_plane *plane,
13449                           struct intel_crtc_state *crtc_state,
13450                           struct intel_plane_state *state)
13451 {
13452         struct drm_crtc *crtc = state->base.crtc;
13453         struct drm_framebuffer *fb = state->base.fb;
13454         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13455         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13456         bool can_position = false;
13457
13458         /* use scaler when colorkey is not required */
13459         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13460             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13461                 min_scale = 1;
13462                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13463                 can_position = true;
13464         }
13465
13466         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13467                                              &state->dst, &state->clip,
13468                                              min_scale, max_scale,
13469                                              can_position, true,
13470                                              &state->visible);
13471 }
13472
13473 static void
13474 intel_commit_primary_plane(struct drm_plane *plane,
13475                            struct intel_plane_state *state)
13476 {
13477         struct drm_crtc *crtc = state->base.crtc;
13478         struct drm_framebuffer *fb = state->base.fb;
13479         struct drm_device *dev = plane->dev;
13480         struct drm_i915_private *dev_priv = dev->dev_private;
13481         struct intel_crtc *intel_crtc;
13482         struct drm_rect *src = &state->src;
13483
13484         crtc = crtc ? crtc : plane->crtc;
13485         intel_crtc = to_intel_crtc(crtc);
13486
13487         plane->fb = fb;
13488         crtc->x = src->x1 >> 16;
13489         crtc->y = src->y1 >> 16;
13490
13491         if (!crtc->state->active)
13492                 return;
13493
13494         dev_priv->display.update_primary_plane(crtc, fb,
13495                                                state->src.x1 >> 16,
13496                                                state->src.y1 >> 16);
13497 }
13498
13499 static void
13500 intel_disable_primary_plane(struct drm_plane *plane,
13501                             struct drm_crtc *crtc)
13502 {
13503         struct drm_device *dev = plane->dev;
13504         struct drm_i915_private *dev_priv = dev->dev_private;
13505
13506         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13507 }
13508
13509 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13510                                     struct drm_crtc_state *old_crtc_state)
13511 {
13512         struct drm_device *dev = crtc->dev;
13513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13514         struct intel_crtc_state *old_intel_state =
13515                 to_intel_crtc_state(old_crtc_state);
13516         bool modeset = needs_modeset(crtc->state);
13517
13518         if (intel_crtc->atomic.update_wm_pre)
13519                 intel_update_watermarks(crtc);
13520
13521         /* Perform vblank evasion around commit operation */
13522         if (crtc->state->active)
13523                 intel_pipe_update_start(intel_crtc);
13524
13525         if (modeset)
13526                 return;
13527
13528         if (to_intel_crtc_state(crtc->state)->update_pipe)
13529                 intel_update_pipe_config(intel_crtc, old_intel_state);
13530         else if (INTEL_INFO(dev)->gen >= 9)
13531                 skl_detach_scalers(intel_crtc);
13532 }
13533
13534 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13535                                      struct drm_crtc_state *old_crtc_state)
13536 {
13537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13538
13539         if (crtc->state->active)
13540                 intel_pipe_update_end(intel_crtc);
13541 }
13542
13543 /**
13544  * intel_plane_destroy - destroy a plane
13545  * @plane: plane to destroy
13546  *
13547  * Common destruction function for all types of planes (primary, cursor,
13548  * sprite).
13549  */
13550 void intel_plane_destroy(struct drm_plane *plane)
13551 {
13552         struct intel_plane *intel_plane = to_intel_plane(plane);
13553         drm_plane_cleanup(plane);
13554         kfree(intel_plane);
13555 }
13556
13557 const struct drm_plane_funcs intel_plane_funcs = {
13558         .update_plane = drm_atomic_helper_update_plane,
13559         .disable_plane = drm_atomic_helper_disable_plane,
13560         .destroy = intel_plane_destroy,
13561         .set_property = drm_atomic_helper_plane_set_property,
13562         .atomic_get_property = intel_plane_atomic_get_property,
13563         .atomic_set_property = intel_plane_atomic_set_property,
13564         .atomic_duplicate_state = intel_plane_duplicate_state,
13565         .atomic_destroy_state = intel_plane_destroy_state,
13566
13567 };
13568
13569 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13570                                                     int pipe)
13571 {
13572         struct intel_plane *primary;
13573         struct intel_plane_state *state;
13574         const uint32_t *intel_primary_formats;
13575         unsigned int num_formats;
13576
13577         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13578         if (primary == NULL)
13579                 return NULL;
13580
13581         state = intel_create_plane_state(&primary->base);
13582         if (!state) {
13583                 kfree(primary);
13584                 return NULL;
13585         }
13586         primary->base.state = &state->base;
13587
13588         primary->can_scale = false;
13589         primary->max_downscale = 1;
13590         if (INTEL_INFO(dev)->gen >= 9) {
13591                 primary->can_scale = true;
13592                 state->scaler_id = -1;
13593         }
13594         primary->pipe = pipe;
13595         primary->plane = pipe;
13596         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13597         primary->check_plane = intel_check_primary_plane;
13598         primary->commit_plane = intel_commit_primary_plane;
13599         primary->disable_plane = intel_disable_primary_plane;
13600         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13601                 primary->plane = !pipe;
13602
13603         if (INTEL_INFO(dev)->gen >= 9) {
13604                 intel_primary_formats = skl_primary_formats;
13605                 num_formats = ARRAY_SIZE(skl_primary_formats);
13606         } else if (INTEL_INFO(dev)->gen >= 4) {
13607                 intel_primary_formats = i965_primary_formats;
13608                 num_formats = ARRAY_SIZE(i965_primary_formats);
13609         } else {
13610                 intel_primary_formats = i8xx_primary_formats;
13611                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13612         }
13613
13614         drm_universal_plane_init(dev, &primary->base, 0,
13615                                  &intel_plane_funcs,
13616                                  intel_primary_formats, num_formats,
13617                                  DRM_PLANE_TYPE_PRIMARY);
13618
13619         if (INTEL_INFO(dev)->gen >= 4)
13620                 intel_create_rotation_property(dev, primary);
13621
13622         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13623
13624         return &primary->base;
13625 }
13626
13627 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13628 {
13629         if (!dev->mode_config.rotation_property) {
13630                 unsigned long flags = BIT(DRM_ROTATE_0) |
13631                         BIT(DRM_ROTATE_180);
13632
13633                 if (INTEL_INFO(dev)->gen >= 9)
13634                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13635
13636                 dev->mode_config.rotation_property =
13637                         drm_mode_create_rotation_property(dev, flags);
13638         }
13639         if (dev->mode_config.rotation_property)
13640                 drm_object_attach_property(&plane->base.base,
13641                                 dev->mode_config.rotation_property,
13642                                 plane->base.state->rotation);
13643 }
13644
13645 static int
13646 intel_check_cursor_plane(struct drm_plane *plane,
13647                          struct intel_crtc_state *crtc_state,
13648                          struct intel_plane_state *state)
13649 {
13650         struct drm_crtc *crtc = crtc_state->base.crtc;
13651         struct drm_framebuffer *fb = state->base.fb;
13652         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13653         unsigned stride;
13654         int ret;
13655
13656         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13657                                             &state->dst, &state->clip,
13658                                             DRM_PLANE_HELPER_NO_SCALING,
13659                                             DRM_PLANE_HELPER_NO_SCALING,
13660                                             true, true, &state->visible);
13661         if (ret)
13662                 return ret;
13663
13664         /* if we want to turn off the cursor ignore width and height */
13665         if (!obj)
13666                 return 0;
13667
13668         /* Check for which cursor types we support */
13669         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13670                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13671                           state->base.crtc_w, state->base.crtc_h);
13672                 return -EINVAL;
13673         }
13674
13675         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13676         if (obj->base.size < stride * state->base.crtc_h) {
13677                 DRM_DEBUG_KMS("buffer is too small\n");
13678                 return -ENOMEM;
13679         }
13680
13681         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13682                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13683                 return -EINVAL;
13684         }
13685
13686         return 0;
13687 }
13688
13689 static void
13690 intel_disable_cursor_plane(struct drm_plane *plane,
13691                            struct drm_crtc *crtc)
13692 {
13693         intel_crtc_update_cursor(crtc, false);
13694 }
13695
13696 static void
13697 intel_commit_cursor_plane(struct drm_plane *plane,
13698                           struct intel_plane_state *state)
13699 {
13700         struct drm_crtc *crtc = state->base.crtc;
13701         struct drm_device *dev = plane->dev;
13702         struct intel_crtc *intel_crtc;
13703         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13704         uint32_t addr;
13705
13706         crtc = crtc ? crtc : plane->crtc;
13707         intel_crtc = to_intel_crtc(crtc);
13708
13709         if (intel_crtc->cursor_bo == obj)
13710                 goto update;
13711
13712         if (!obj)
13713                 addr = 0;
13714         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13715                 addr = i915_gem_obj_ggtt_offset(obj);
13716         else
13717                 addr = obj->phys_handle->busaddr;
13718
13719         intel_crtc->cursor_addr = addr;
13720         intel_crtc->cursor_bo = obj;
13721
13722 update:
13723         if (crtc->state->active)
13724                 intel_crtc_update_cursor(crtc, state->visible);
13725 }
13726
13727 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13728                                                    int pipe)
13729 {
13730         struct intel_plane *cursor;
13731         struct intel_plane_state *state;
13732
13733         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13734         if (cursor == NULL)
13735                 return NULL;
13736
13737         state = intel_create_plane_state(&cursor->base);
13738         if (!state) {
13739                 kfree(cursor);
13740                 return NULL;
13741         }
13742         cursor->base.state = &state->base;
13743
13744         cursor->can_scale = false;
13745         cursor->max_downscale = 1;
13746         cursor->pipe = pipe;
13747         cursor->plane = pipe;
13748         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13749         cursor->check_plane = intel_check_cursor_plane;
13750         cursor->commit_plane = intel_commit_cursor_plane;
13751         cursor->disable_plane = intel_disable_cursor_plane;
13752
13753         drm_universal_plane_init(dev, &cursor->base, 0,
13754                                  &intel_plane_funcs,
13755                                  intel_cursor_formats,
13756                                  ARRAY_SIZE(intel_cursor_formats),
13757                                  DRM_PLANE_TYPE_CURSOR);
13758
13759         if (INTEL_INFO(dev)->gen >= 4) {
13760                 if (!dev->mode_config.rotation_property)
13761                         dev->mode_config.rotation_property =
13762                                 drm_mode_create_rotation_property(dev,
13763                                                         BIT(DRM_ROTATE_0) |
13764                                                         BIT(DRM_ROTATE_180));
13765                 if (dev->mode_config.rotation_property)
13766                         drm_object_attach_property(&cursor->base.base,
13767                                 dev->mode_config.rotation_property,
13768                                 state->base.rotation);
13769         }
13770
13771         if (INTEL_INFO(dev)->gen >=9)
13772                 state->scaler_id = -1;
13773
13774         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13775
13776         return &cursor->base;
13777 }
13778
13779 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13780         struct intel_crtc_state *crtc_state)
13781 {
13782         int i;
13783         struct intel_scaler *intel_scaler;
13784         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13785
13786         for (i = 0; i < intel_crtc->num_scalers; i++) {
13787                 intel_scaler = &scaler_state->scalers[i];
13788                 intel_scaler->in_use = 0;
13789                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13790         }
13791
13792         scaler_state->scaler_id = -1;
13793 }
13794
13795 static void intel_crtc_init(struct drm_device *dev, int pipe)
13796 {
13797         struct drm_i915_private *dev_priv = dev->dev_private;
13798         struct intel_crtc *intel_crtc;
13799         struct intel_crtc_state *crtc_state = NULL;
13800         struct drm_plane *primary = NULL;
13801         struct drm_plane *cursor = NULL;
13802         int i, ret;
13803
13804         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13805         if (intel_crtc == NULL)
13806                 return;
13807
13808         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13809         if (!crtc_state)
13810                 goto fail;
13811         intel_crtc->config = crtc_state;
13812         intel_crtc->base.state = &crtc_state->base;
13813         crtc_state->base.crtc = &intel_crtc->base;
13814
13815         /* initialize shared scalers */
13816         if (INTEL_INFO(dev)->gen >= 9) {
13817                 if (pipe == PIPE_C)
13818                         intel_crtc->num_scalers = 1;
13819                 else
13820                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13821
13822                 skl_init_scalers(dev, intel_crtc, crtc_state);
13823         }
13824
13825         primary = intel_primary_plane_create(dev, pipe);
13826         if (!primary)
13827                 goto fail;
13828
13829         cursor = intel_cursor_plane_create(dev, pipe);
13830         if (!cursor)
13831                 goto fail;
13832
13833         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13834                                         cursor, &intel_crtc_funcs);
13835         if (ret)
13836                 goto fail;
13837
13838         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13839         for (i = 0; i < 256; i++) {
13840                 intel_crtc->lut_r[i] = i;
13841                 intel_crtc->lut_g[i] = i;
13842                 intel_crtc->lut_b[i] = i;
13843         }
13844
13845         /*
13846          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13847          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13848          */
13849         intel_crtc->pipe = pipe;
13850         intel_crtc->plane = pipe;
13851         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13852                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13853                 intel_crtc->plane = !pipe;
13854         }
13855
13856         intel_crtc->cursor_base = ~0;
13857         intel_crtc->cursor_cntl = ~0;
13858         intel_crtc->cursor_size = ~0;
13859
13860         intel_crtc->wm.cxsr_allowed = true;
13861
13862         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13863                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13864         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13865         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13866
13867         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13868
13869         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13870         return;
13871
13872 fail:
13873         if (primary)
13874                 drm_plane_cleanup(primary);
13875         if (cursor)
13876                 drm_plane_cleanup(cursor);
13877         kfree(crtc_state);
13878         kfree(intel_crtc);
13879 }
13880
13881 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13882 {
13883         struct drm_encoder *encoder = connector->base.encoder;
13884         struct drm_device *dev = connector->base.dev;
13885
13886         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13887
13888         if (!encoder || WARN_ON(!encoder->crtc))
13889                 return INVALID_PIPE;
13890
13891         return to_intel_crtc(encoder->crtc)->pipe;
13892 }
13893
13894 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13895                                 struct drm_file *file)
13896 {
13897         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13898         struct drm_crtc *drmmode_crtc;
13899         struct intel_crtc *crtc;
13900
13901         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13902
13903         if (!drmmode_crtc) {
13904                 DRM_ERROR("no such CRTC id\n");
13905                 return -ENOENT;
13906         }
13907
13908         crtc = to_intel_crtc(drmmode_crtc);
13909         pipe_from_crtc_id->pipe = crtc->pipe;
13910
13911         return 0;
13912 }
13913
13914 static int intel_encoder_clones(struct intel_encoder *encoder)
13915 {
13916         struct drm_device *dev = encoder->base.dev;
13917         struct intel_encoder *source_encoder;
13918         int index_mask = 0;
13919         int entry = 0;
13920
13921         for_each_intel_encoder(dev, source_encoder) {
13922                 if (encoders_cloneable(encoder, source_encoder))
13923                         index_mask |= (1 << entry);
13924
13925                 entry++;
13926         }
13927
13928         return index_mask;
13929 }
13930
13931 static bool has_edp_a(struct drm_device *dev)
13932 {
13933         struct drm_i915_private *dev_priv = dev->dev_private;
13934
13935         if (!IS_MOBILE(dev))
13936                 return false;
13937
13938         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13939                 return false;
13940
13941         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13942                 return false;
13943
13944         return true;
13945 }
13946
13947 static bool intel_crt_present(struct drm_device *dev)
13948 {
13949         struct drm_i915_private *dev_priv = dev->dev_private;
13950
13951         if (INTEL_INFO(dev)->gen >= 9)
13952                 return false;
13953
13954         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13955                 return false;
13956
13957         if (IS_CHERRYVIEW(dev))
13958                 return false;
13959
13960         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13961                 return false;
13962
13963         return true;
13964 }
13965
13966 static void intel_setup_outputs(struct drm_device *dev)
13967 {
13968         struct drm_i915_private *dev_priv = dev->dev_private;
13969         struct intel_encoder *encoder;
13970         bool dpd_is_edp = false;
13971
13972         intel_lvds_init(dev);
13973
13974         if (intel_crt_present(dev))
13975                 intel_crt_init(dev);
13976
13977         if (IS_BROXTON(dev)) {
13978                 /*
13979                  * FIXME: Broxton doesn't support port detection via the
13980                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13981                  * detect the ports.
13982                  */
13983                 intel_ddi_init(dev, PORT_A);
13984                 intel_ddi_init(dev, PORT_B);
13985                 intel_ddi_init(dev, PORT_C);
13986         } else if (HAS_DDI(dev)) {
13987                 int found;
13988
13989                 /*
13990                  * Haswell uses DDI functions to detect digital outputs.
13991                  * On SKL pre-D0 the strap isn't connected, so we assume
13992                  * it's there.
13993                  */
13994                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13995                 /* WaIgnoreDDIAStrap: skl */
13996                 if (found || IS_SKYLAKE(dev))
13997                         intel_ddi_init(dev, PORT_A);
13998
13999                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14000                  * register */
14001                 found = I915_READ(SFUSE_STRAP);
14002
14003                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14004                         intel_ddi_init(dev, PORT_B);
14005                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14006                         intel_ddi_init(dev, PORT_C);
14007                 if (found & SFUSE_STRAP_DDID_DETECTED)
14008                         intel_ddi_init(dev, PORT_D);
14009                 /*
14010                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14011                  */
14012                 if (IS_SKYLAKE(dev) &&
14013                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14014                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14015                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14016                         intel_ddi_init(dev, PORT_E);
14017
14018         } else if (HAS_PCH_SPLIT(dev)) {
14019                 int found;
14020                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14021
14022                 if (has_edp_a(dev))
14023                         intel_dp_init(dev, DP_A, PORT_A);
14024
14025                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14026                         /* PCH SDVOB multiplex with HDMIB */
14027                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14028                         if (!found)
14029                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14030                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14031                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14032                 }
14033
14034                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14035                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14036
14037                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14038                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14039
14040                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14041                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14042
14043                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14044                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14045         } else if (IS_VALLEYVIEW(dev)) {
14046                 /*
14047                  * The DP_DETECTED bit is the latched state of the DDC
14048                  * SDA pin at boot. However since eDP doesn't require DDC
14049                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14050                  * eDP ports may have been muxed to an alternate function.
14051                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14052                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14053                  * detect eDP ports.
14054                  */
14055                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14056                     !intel_dp_is_edp(dev, PORT_B))
14057                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14058                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14059                     intel_dp_is_edp(dev, PORT_B))
14060                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14061
14062                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14063                     !intel_dp_is_edp(dev, PORT_C))
14064                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14065                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14066                     intel_dp_is_edp(dev, PORT_C))
14067                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14068
14069                 if (IS_CHERRYVIEW(dev)) {
14070                         /* eDP not supported on port D, so don't check VBT */
14071                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14072                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14073                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14074                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14075                 }
14076
14077                 intel_dsi_init(dev);
14078         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14079                 bool found = false;
14080
14081                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14082                         DRM_DEBUG_KMS("probing SDVOB\n");
14083                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14084                         if (!found && IS_G4X(dev)) {
14085                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14086                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14087                         }
14088
14089                         if (!found && IS_G4X(dev))
14090                                 intel_dp_init(dev, DP_B, PORT_B);
14091                 }
14092
14093                 /* Before G4X SDVOC doesn't have its own detect register */
14094
14095                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14096                         DRM_DEBUG_KMS("probing SDVOC\n");
14097                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14098                 }
14099
14100                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14101
14102                         if (IS_G4X(dev)) {
14103                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14104                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14105                         }
14106                         if (IS_G4X(dev))
14107                                 intel_dp_init(dev, DP_C, PORT_C);
14108                 }
14109
14110                 if (IS_G4X(dev) &&
14111                     (I915_READ(DP_D) & DP_DETECTED))
14112                         intel_dp_init(dev, DP_D, PORT_D);
14113         } else if (IS_GEN2(dev))
14114                 intel_dvo_init(dev);
14115
14116         if (SUPPORTS_TV(dev))
14117                 intel_tv_init(dev);
14118
14119         intel_psr_init(dev);
14120
14121         for_each_intel_encoder(dev, encoder) {
14122                 encoder->base.possible_crtcs = encoder->crtc_mask;
14123                 encoder->base.possible_clones =
14124                         intel_encoder_clones(encoder);
14125         }
14126
14127         intel_init_pch_refclk(dev);
14128
14129         drm_helper_move_panel_connectors_to_head(dev);
14130 }
14131
14132 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14133 {
14134         struct drm_device *dev = fb->dev;
14135         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14136
14137         drm_framebuffer_cleanup(fb);
14138         mutex_lock(&dev->struct_mutex);
14139         WARN_ON(!intel_fb->obj->framebuffer_references--);
14140         drm_gem_object_unreference(&intel_fb->obj->base);
14141         mutex_unlock(&dev->struct_mutex);
14142         kfree(intel_fb);
14143 }
14144
14145 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14146                                                 struct drm_file *file,
14147                                                 unsigned int *handle)
14148 {
14149         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14150         struct drm_i915_gem_object *obj = intel_fb->obj;
14151
14152         if (obj->userptr.mm) {
14153                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14154                 return -EINVAL;
14155         }
14156
14157         return drm_gem_handle_create(file, &obj->base, handle);
14158 }
14159
14160 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14161                                         struct drm_file *file,
14162                                         unsigned flags, unsigned color,
14163                                         struct drm_clip_rect *clips,
14164                                         unsigned num_clips)
14165 {
14166         struct drm_device *dev = fb->dev;
14167         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14168         struct drm_i915_gem_object *obj = intel_fb->obj;
14169
14170         mutex_lock(&dev->struct_mutex);
14171         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14172         mutex_unlock(&dev->struct_mutex);
14173
14174         return 0;
14175 }
14176
14177 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14178         .destroy = intel_user_framebuffer_destroy,
14179         .create_handle = intel_user_framebuffer_create_handle,
14180         .dirty = intel_user_framebuffer_dirty,
14181 };
14182
14183 static
14184 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14185                          uint32_t pixel_format)
14186 {
14187         u32 gen = INTEL_INFO(dev)->gen;
14188
14189         if (gen >= 9) {
14190                 /* "The stride in bytes must not exceed the of the size of 8K
14191                  *  pixels and 32K bytes."
14192                  */
14193                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14194         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14195                 return 32*1024;
14196         } else if (gen >= 4) {
14197                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14198                         return 16*1024;
14199                 else
14200                         return 32*1024;
14201         } else if (gen >= 3) {
14202                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14203                         return 8*1024;
14204                 else
14205                         return 16*1024;
14206         } else {
14207                 /* XXX DSPC is limited to 4k tiled */
14208                 return 8*1024;
14209         }
14210 }
14211
14212 static int intel_framebuffer_init(struct drm_device *dev,
14213                                   struct intel_framebuffer *intel_fb,
14214                                   struct drm_mode_fb_cmd2 *mode_cmd,
14215                                   struct drm_i915_gem_object *obj)
14216 {
14217         unsigned int aligned_height;
14218         int ret;
14219         u32 pitch_limit, stride_alignment;
14220
14221         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14222
14223         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14224                 /* Enforce that fb modifier and tiling mode match, but only for
14225                  * X-tiled. This is needed for FBC. */
14226                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14227                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14228                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14229                         return -EINVAL;
14230                 }
14231         } else {
14232                 if (obj->tiling_mode == I915_TILING_X)
14233                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14234                 else if (obj->tiling_mode == I915_TILING_Y) {
14235                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14236                         return -EINVAL;
14237                 }
14238         }
14239
14240         /* Passed in modifier sanity checking. */
14241         switch (mode_cmd->modifier[0]) {
14242         case I915_FORMAT_MOD_Y_TILED:
14243         case I915_FORMAT_MOD_Yf_TILED:
14244                 if (INTEL_INFO(dev)->gen < 9) {
14245                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14246                                   mode_cmd->modifier[0]);
14247                         return -EINVAL;
14248                 }
14249         case DRM_FORMAT_MOD_NONE:
14250         case I915_FORMAT_MOD_X_TILED:
14251                 break;
14252         default:
14253                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14254                           mode_cmd->modifier[0]);
14255                 return -EINVAL;
14256         }
14257
14258         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14259                                                      mode_cmd->pixel_format);
14260         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14261                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14262                           mode_cmd->pitches[0], stride_alignment);
14263                 return -EINVAL;
14264         }
14265
14266         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14267                                            mode_cmd->pixel_format);
14268         if (mode_cmd->pitches[0] > pitch_limit) {
14269                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14270                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14271                           "tiled" : "linear",
14272                           mode_cmd->pitches[0], pitch_limit);
14273                 return -EINVAL;
14274         }
14275
14276         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14277             mode_cmd->pitches[0] != obj->stride) {
14278                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14279                           mode_cmd->pitches[0], obj->stride);
14280                 return -EINVAL;
14281         }
14282
14283         /* Reject formats not supported by any plane early. */
14284         switch (mode_cmd->pixel_format) {
14285         case DRM_FORMAT_C8:
14286         case DRM_FORMAT_RGB565:
14287         case DRM_FORMAT_XRGB8888:
14288         case DRM_FORMAT_ARGB8888:
14289                 break;
14290         case DRM_FORMAT_XRGB1555:
14291                 if (INTEL_INFO(dev)->gen > 3) {
14292                         DRM_DEBUG("unsupported pixel format: %s\n",
14293                                   drm_get_format_name(mode_cmd->pixel_format));
14294                         return -EINVAL;
14295                 }
14296                 break;
14297         case DRM_FORMAT_ABGR8888:
14298                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14299                         DRM_DEBUG("unsupported pixel format: %s\n",
14300                                   drm_get_format_name(mode_cmd->pixel_format));
14301                         return -EINVAL;
14302                 }
14303                 break;
14304         case DRM_FORMAT_XBGR8888:
14305         case DRM_FORMAT_XRGB2101010:
14306         case DRM_FORMAT_XBGR2101010:
14307                 if (INTEL_INFO(dev)->gen < 4) {
14308                         DRM_DEBUG("unsupported pixel format: %s\n",
14309                                   drm_get_format_name(mode_cmd->pixel_format));
14310                         return -EINVAL;
14311                 }
14312                 break;
14313         case DRM_FORMAT_ABGR2101010:
14314                 if (!IS_VALLEYVIEW(dev)) {
14315                         DRM_DEBUG("unsupported pixel format: %s\n",
14316                                   drm_get_format_name(mode_cmd->pixel_format));
14317                         return -EINVAL;
14318                 }
14319                 break;
14320         case DRM_FORMAT_YUYV:
14321         case DRM_FORMAT_UYVY:
14322         case DRM_FORMAT_YVYU:
14323         case DRM_FORMAT_VYUY:
14324                 if (INTEL_INFO(dev)->gen < 5) {
14325                         DRM_DEBUG("unsupported pixel format: %s\n",
14326                                   drm_get_format_name(mode_cmd->pixel_format));
14327                         return -EINVAL;
14328                 }
14329                 break;
14330         default:
14331                 DRM_DEBUG("unsupported pixel format: %s\n",
14332                           drm_get_format_name(mode_cmd->pixel_format));
14333                 return -EINVAL;
14334         }
14335
14336         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14337         if (mode_cmd->offsets[0] != 0)
14338                 return -EINVAL;
14339
14340         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14341                                                mode_cmd->pixel_format,
14342                                                mode_cmd->modifier[0]);
14343         /* FIXME drm helper for size checks (especially planar formats)? */
14344         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14345                 return -EINVAL;
14346
14347         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14348         intel_fb->obj = obj;
14349         intel_fb->obj->framebuffer_references++;
14350
14351         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14352         if (ret) {
14353                 DRM_ERROR("framebuffer init failed %d\n", ret);
14354                 return ret;
14355         }
14356
14357         return 0;
14358 }
14359
14360 static struct drm_framebuffer *
14361 intel_user_framebuffer_create(struct drm_device *dev,
14362                               struct drm_file *filp,
14363                               struct drm_mode_fb_cmd2 *mode_cmd)
14364 {
14365         struct drm_i915_gem_object *obj;
14366
14367         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14368                                                 mode_cmd->handles[0]));
14369         if (&obj->base == NULL)
14370                 return ERR_PTR(-ENOENT);
14371
14372         return intel_framebuffer_create(dev, mode_cmd, obj);
14373 }
14374
14375 #ifndef CONFIG_DRM_FBDEV_EMULATION
14376 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14377 {
14378 }
14379 #endif
14380
14381 static const struct drm_mode_config_funcs intel_mode_funcs = {
14382         .fb_create = intel_user_framebuffer_create,
14383         .output_poll_changed = intel_fbdev_output_poll_changed,
14384         .atomic_check = intel_atomic_check,
14385         .atomic_commit = intel_atomic_commit,
14386         .atomic_state_alloc = intel_atomic_state_alloc,
14387         .atomic_state_clear = intel_atomic_state_clear,
14388 };
14389
14390 /* Set up chip specific display functions */
14391 static void intel_init_display(struct drm_device *dev)
14392 {
14393         struct drm_i915_private *dev_priv = dev->dev_private;
14394
14395         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14396                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14397         else if (IS_CHERRYVIEW(dev))
14398                 dev_priv->display.find_dpll = chv_find_best_dpll;
14399         else if (IS_VALLEYVIEW(dev))
14400                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14401         else if (IS_PINEVIEW(dev))
14402                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14403         else
14404                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14405
14406         if (INTEL_INFO(dev)->gen >= 9) {
14407                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14408                 dev_priv->display.get_initial_plane_config =
14409                         skylake_get_initial_plane_config;
14410                 dev_priv->display.crtc_compute_clock =
14411                         haswell_crtc_compute_clock;
14412                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14413                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14414                 dev_priv->display.update_primary_plane =
14415                         skylake_update_primary_plane;
14416         } else if (HAS_DDI(dev)) {
14417                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14418                 dev_priv->display.get_initial_plane_config =
14419                         ironlake_get_initial_plane_config;
14420                 dev_priv->display.crtc_compute_clock =
14421                         haswell_crtc_compute_clock;
14422                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14423                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14424                 dev_priv->display.update_primary_plane =
14425                         ironlake_update_primary_plane;
14426         } else if (HAS_PCH_SPLIT(dev)) {
14427                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14428                 dev_priv->display.get_initial_plane_config =
14429                         ironlake_get_initial_plane_config;
14430                 dev_priv->display.crtc_compute_clock =
14431                         ironlake_crtc_compute_clock;
14432                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14433                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14434                 dev_priv->display.update_primary_plane =
14435                         ironlake_update_primary_plane;
14436         } else if (IS_VALLEYVIEW(dev)) {
14437                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14438                 dev_priv->display.get_initial_plane_config =
14439                         i9xx_get_initial_plane_config;
14440                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14441                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14442                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14443                 dev_priv->display.update_primary_plane =
14444                         i9xx_update_primary_plane;
14445         } else {
14446                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14447                 dev_priv->display.get_initial_plane_config =
14448                         i9xx_get_initial_plane_config;
14449                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14450                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14451                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14452                 dev_priv->display.update_primary_plane =
14453                         i9xx_update_primary_plane;
14454         }
14455
14456         /* Returns the core display clock speed */
14457         if (IS_SKYLAKE(dev))
14458                 dev_priv->display.get_display_clock_speed =
14459                         skylake_get_display_clock_speed;
14460         else if (IS_BROXTON(dev))
14461                 dev_priv->display.get_display_clock_speed =
14462                         broxton_get_display_clock_speed;
14463         else if (IS_BROADWELL(dev))
14464                 dev_priv->display.get_display_clock_speed =
14465                         broadwell_get_display_clock_speed;
14466         else if (IS_HASWELL(dev))
14467                 dev_priv->display.get_display_clock_speed =
14468                         haswell_get_display_clock_speed;
14469         else if (IS_VALLEYVIEW(dev))
14470                 dev_priv->display.get_display_clock_speed =
14471                         valleyview_get_display_clock_speed;
14472         else if (IS_GEN5(dev))
14473                 dev_priv->display.get_display_clock_speed =
14474                         ilk_get_display_clock_speed;
14475         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14476                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14477                 dev_priv->display.get_display_clock_speed =
14478                         i945_get_display_clock_speed;
14479         else if (IS_GM45(dev))
14480                 dev_priv->display.get_display_clock_speed =
14481                         gm45_get_display_clock_speed;
14482         else if (IS_CRESTLINE(dev))
14483                 dev_priv->display.get_display_clock_speed =
14484                         i965gm_get_display_clock_speed;
14485         else if (IS_PINEVIEW(dev))
14486                 dev_priv->display.get_display_clock_speed =
14487                         pnv_get_display_clock_speed;
14488         else if (IS_G33(dev) || IS_G4X(dev))
14489                 dev_priv->display.get_display_clock_speed =
14490                         g33_get_display_clock_speed;
14491         else if (IS_I915G(dev))
14492                 dev_priv->display.get_display_clock_speed =
14493                         i915_get_display_clock_speed;
14494         else if (IS_I945GM(dev) || IS_845G(dev))
14495                 dev_priv->display.get_display_clock_speed =
14496                         i9xx_misc_get_display_clock_speed;
14497         else if (IS_PINEVIEW(dev))
14498                 dev_priv->display.get_display_clock_speed =
14499                         pnv_get_display_clock_speed;
14500         else if (IS_I915GM(dev))
14501                 dev_priv->display.get_display_clock_speed =
14502                         i915gm_get_display_clock_speed;
14503         else if (IS_I865G(dev))
14504                 dev_priv->display.get_display_clock_speed =
14505                         i865_get_display_clock_speed;
14506         else if (IS_I85X(dev))
14507                 dev_priv->display.get_display_clock_speed =
14508                         i85x_get_display_clock_speed;
14509         else { /* 830 */
14510                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14511                 dev_priv->display.get_display_clock_speed =
14512                         i830_get_display_clock_speed;
14513         }
14514
14515         if (IS_GEN5(dev)) {
14516                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14517         } else if (IS_GEN6(dev)) {
14518                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14519         } else if (IS_IVYBRIDGE(dev)) {
14520                 /* FIXME: detect B0+ stepping and use auto training */
14521                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14522         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14523                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14524                 if (IS_BROADWELL(dev)) {
14525                         dev_priv->display.modeset_commit_cdclk =
14526                                 broadwell_modeset_commit_cdclk;
14527                         dev_priv->display.modeset_calc_cdclk =
14528                                 broadwell_modeset_calc_cdclk;
14529                 }
14530         } else if (IS_VALLEYVIEW(dev)) {
14531                 dev_priv->display.modeset_commit_cdclk =
14532                         valleyview_modeset_commit_cdclk;
14533                 dev_priv->display.modeset_calc_cdclk =
14534                         valleyview_modeset_calc_cdclk;
14535         } else if (IS_BROXTON(dev)) {
14536                 dev_priv->display.modeset_commit_cdclk =
14537                         broxton_modeset_commit_cdclk;
14538                 dev_priv->display.modeset_calc_cdclk =
14539                         broxton_modeset_calc_cdclk;
14540         }
14541
14542         switch (INTEL_INFO(dev)->gen) {
14543         case 2:
14544                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14545                 break;
14546
14547         case 3:
14548                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14549                 break;
14550
14551         case 4:
14552         case 5:
14553                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14554                 break;
14555
14556         case 6:
14557                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14558                 break;
14559         case 7:
14560         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14561                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14562                 break;
14563         case 9:
14564                 /* Drop through - unsupported since execlist only. */
14565         default:
14566                 /* Default just returns -ENODEV to indicate unsupported */
14567                 dev_priv->display.queue_flip = intel_default_queue_flip;
14568         }
14569
14570         mutex_init(&dev_priv->pps_mutex);
14571 }
14572
14573 /*
14574  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14575  * resume, or other times.  This quirk makes sure that's the case for
14576  * affected systems.
14577  */
14578 static void quirk_pipea_force(struct drm_device *dev)
14579 {
14580         struct drm_i915_private *dev_priv = dev->dev_private;
14581
14582         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14583         DRM_INFO("applying pipe a force quirk\n");
14584 }
14585
14586 static void quirk_pipeb_force(struct drm_device *dev)
14587 {
14588         struct drm_i915_private *dev_priv = dev->dev_private;
14589
14590         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14591         DRM_INFO("applying pipe b force quirk\n");
14592 }
14593
14594 /*
14595  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14596  */
14597 static void quirk_ssc_force_disable(struct drm_device *dev)
14598 {
14599         struct drm_i915_private *dev_priv = dev->dev_private;
14600         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14601         DRM_INFO("applying lvds SSC disable quirk\n");
14602 }
14603
14604 /*
14605  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14606  * brightness value
14607  */
14608 static void quirk_invert_brightness(struct drm_device *dev)
14609 {
14610         struct drm_i915_private *dev_priv = dev->dev_private;
14611         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14612         DRM_INFO("applying inverted panel brightness quirk\n");
14613 }
14614
14615 /* Some VBT's incorrectly indicate no backlight is present */
14616 static void quirk_backlight_present(struct drm_device *dev)
14617 {
14618         struct drm_i915_private *dev_priv = dev->dev_private;
14619         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14620         DRM_INFO("applying backlight present quirk\n");
14621 }
14622
14623 struct intel_quirk {
14624         int device;
14625         int subsystem_vendor;
14626         int subsystem_device;
14627         void (*hook)(struct drm_device *dev);
14628 };
14629
14630 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14631 struct intel_dmi_quirk {
14632         void (*hook)(struct drm_device *dev);
14633         const struct dmi_system_id (*dmi_id_list)[];
14634 };
14635
14636 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14637 {
14638         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14639         return 1;
14640 }
14641
14642 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14643         {
14644                 .dmi_id_list = &(const struct dmi_system_id[]) {
14645                         {
14646                                 .callback = intel_dmi_reverse_brightness,
14647                                 .ident = "NCR Corporation",
14648                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14649                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14650                                 },
14651                         },
14652                         { }  /* terminating entry */
14653                 },
14654                 .hook = quirk_invert_brightness,
14655         },
14656 };
14657
14658 static struct intel_quirk intel_quirks[] = {
14659         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14660         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14661
14662         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14663         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14664
14665         /* 830 needs to leave pipe A & dpll A up */
14666         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14667
14668         /* 830 needs to leave pipe B & dpll B up */
14669         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14670
14671         /* Lenovo U160 cannot use SSC on LVDS */
14672         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14673
14674         /* Sony Vaio Y cannot use SSC on LVDS */
14675         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14676
14677         /* Acer Aspire 5734Z must invert backlight brightness */
14678         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14679
14680         /* Acer/eMachines G725 */
14681         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14682
14683         /* Acer/eMachines e725 */
14684         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14685
14686         /* Acer/Packard Bell NCL20 */
14687         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14688
14689         /* Acer Aspire 4736Z */
14690         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14691
14692         /* Acer Aspire 5336 */
14693         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14694
14695         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14696         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14697
14698         /* Acer C720 Chromebook (Core i3 4005U) */
14699         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14700
14701         /* Apple Macbook 2,1 (Core 2 T7400) */
14702         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14703
14704         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14705         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14706
14707         /* HP Chromebook 14 (Celeron 2955U) */
14708         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14709
14710         /* Dell Chromebook 11 */
14711         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14712
14713         /* Dell Chromebook 11 (2015 version) */
14714         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14715 };
14716
14717 static void intel_init_quirks(struct drm_device *dev)
14718 {
14719         struct pci_dev *d = dev->pdev;
14720         int i;
14721
14722         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14723                 struct intel_quirk *q = &intel_quirks[i];
14724
14725                 if (d->device == q->device &&
14726                     (d->subsystem_vendor == q->subsystem_vendor ||
14727                      q->subsystem_vendor == PCI_ANY_ID) &&
14728                     (d->subsystem_device == q->subsystem_device ||
14729                      q->subsystem_device == PCI_ANY_ID))
14730                         q->hook(dev);
14731         }
14732         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14733                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14734                         intel_dmi_quirks[i].hook(dev);
14735         }
14736 }
14737
14738 /* Disable the VGA plane that we never use */
14739 static void i915_disable_vga(struct drm_device *dev)
14740 {
14741         struct drm_i915_private *dev_priv = dev->dev_private;
14742         u8 sr1;
14743         u32 vga_reg = i915_vgacntrl_reg(dev);
14744
14745         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14746         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14747         outb(SR01, VGA_SR_INDEX);
14748         sr1 = inb(VGA_SR_DATA);
14749         outb(sr1 | 1<<5, VGA_SR_DATA);
14750         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14751         udelay(300);
14752
14753         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14754         POSTING_READ(vga_reg);
14755 }
14756
14757 void intel_modeset_init_hw(struct drm_device *dev)
14758 {
14759         intel_update_cdclk(dev);
14760         intel_prepare_ddi(dev);
14761         intel_init_clock_gating(dev);
14762         intel_enable_gt_powersave(dev);
14763 }
14764
14765 void intel_modeset_init(struct drm_device *dev)
14766 {
14767         struct drm_i915_private *dev_priv = dev->dev_private;
14768         int sprite, ret;
14769         enum pipe pipe;
14770         struct intel_crtc *crtc;
14771
14772         drm_mode_config_init(dev);
14773
14774         dev->mode_config.min_width = 0;
14775         dev->mode_config.min_height = 0;
14776
14777         dev->mode_config.preferred_depth = 24;
14778         dev->mode_config.prefer_shadow = 1;
14779
14780         dev->mode_config.allow_fb_modifiers = true;
14781
14782         dev->mode_config.funcs = &intel_mode_funcs;
14783
14784         intel_init_quirks(dev);
14785
14786         intel_init_pm(dev);
14787
14788         if (INTEL_INFO(dev)->num_pipes == 0)
14789                 return;
14790
14791         /*
14792          * There may be no VBT; and if the BIOS enabled SSC we can
14793          * just keep using it to avoid unnecessary flicker.  Whereas if the
14794          * BIOS isn't using it, don't assume it will work even if the VBT
14795          * indicates as much.
14796          */
14797         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14798                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14799                                             DREF_SSC1_ENABLE);
14800
14801                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14802                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14803                                      bios_lvds_use_ssc ? "en" : "dis",
14804                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14805                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14806                 }
14807         }
14808
14809         intel_init_display(dev);
14810         intel_init_audio(dev);
14811
14812         if (IS_GEN2(dev)) {
14813                 dev->mode_config.max_width = 2048;
14814                 dev->mode_config.max_height = 2048;
14815         } else if (IS_GEN3(dev)) {
14816                 dev->mode_config.max_width = 4096;
14817                 dev->mode_config.max_height = 4096;
14818         } else {
14819                 dev->mode_config.max_width = 8192;
14820                 dev->mode_config.max_height = 8192;
14821         }
14822
14823         if (IS_845G(dev) || IS_I865G(dev)) {
14824                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14825                 dev->mode_config.cursor_height = 1023;
14826         } else if (IS_GEN2(dev)) {
14827                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14828                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14829         } else {
14830                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14831                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14832         }
14833
14834         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14835
14836         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14837                       INTEL_INFO(dev)->num_pipes,
14838                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14839
14840         for_each_pipe(dev_priv, pipe) {
14841                 intel_crtc_init(dev, pipe);
14842                 for_each_sprite(dev_priv, pipe, sprite) {
14843                         ret = intel_plane_init(dev, pipe, sprite);
14844                         if (ret)
14845                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14846                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14847                 }
14848         }
14849
14850         intel_update_czclk(dev_priv);
14851         intel_update_cdclk(dev);
14852
14853         intel_shared_dpll_init(dev);
14854
14855         /* Just disable it once at startup */
14856         i915_disable_vga(dev);
14857         intel_setup_outputs(dev);
14858
14859         /* Just in case the BIOS is doing something questionable. */
14860         intel_fbc_disable(dev_priv);
14861
14862         drm_modeset_lock_all(dev);
14863         intel_modeset_setup_hw_state(dev);
14864         drm_modeset_unlock_all(dev);
14865
14866         for_each_intel_crtc(dev, crtc) {
14867                 struct intel_initial_plane_config plane_config = {};
14868
14869                 if (!crtc->active)
14870                         continue;
14871
14872                 /*
14873                  * Note that reserving the BIOS fb up front prevents us
14874                  * from stuffing other stolen allocations like the ring
14875                  * on top.  This prevents some ugliness at boot time, and
14876                  * can even allow for smooth boot transitions if the BIOS
14877                  * fb is large enough for the active pipe configuration.
14878                  */
14879                 dev_priv->display.get_initial_plane_config(crtc,
14880                                                            &plane_config);
14881
14882                 /*
14883                  * If the fb is shared between multiple heads, we'll
14884                  * just get the first one.
14885                  */
14886                 intel_find_initial_plane_obj(crtc, &plane_config);
14887         }
14888 }
14889
14890 static void intel_enable_pipe_a(struct drm_device *dev)
14891 {
14892         struct intel_connector *connector;
14893         struct drm_connector *crt = NULL;
14894         struct intel_load_detect_pipe load_detect_temp;
14895         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14896
14897         /* We can't just switch on the pipe A, we need to set things up with a
14898          * proper mode and output configuration. As a gross hack, enable pipe A
14899          * by enabling the load detect pipe once. */
14900         for_each_intel_connector(dev, connector) {
14901                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14902                         crt = &connector->base;
14903                         break;
14904                 }
14905         }
14906
14907         if (!crt)
14908                 return;
14909
14910         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14911                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14912 }
14913
14914 static bool
14915 intel_check_plane_mapping(struct intel_crtc *crtc)
14916 {
14917         struct drm_device *dev = crtc->base.dev;
14918         struct drm_i915_private *dev_priv = dev->dev_private;
14919         u32 val;
14920
14921         if (INTEL_INFO(dev)->num_pipes == 1)
14922                 return true;
14923
14924         val = I915_READ(DSPCNTR(!crtc->plane));
14925
14926         if ((val & DISPLAY_PLANE_ENABLE) &&
14927             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14928                 return false;
14929
14930         return true;
14931 }
14932
14933 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14934 {
14935         struct drm_device *dev = crtc->base.dev;
14936         struct intel_encoder *encoder;
14937
14938         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14939                 return true;
14940
14941         return false;
14942 }
14943
14944 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14945 {
14946         struct drm_device *dev = crtc->base.dev;
14947         struct drm_i915_private *dev_priv = dev->dev_private;
14948         u32 reg;
14949
14950         /* Clear any frame start delays used for debugging left by the BIOS */
14951         reg = PIPECONF(crtc->config->cpu_transcoder);
14952         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14953
14954         /* restore vblank interrupts to correct state */
14955         drm_crtc_vblank_reset(&crtc->base);
14956         if (crtc->active) {
14957                 struct intel_plane *plane;
14958
14959                 drm_crtc_vblank_on(&crtc->base);
14960
14961                 /* Disable everything but the primary plane */
14962                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14963                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14964                                 continue;
14965
14966                         plane->disable_plane(&plane->base, &crtc->base);
14967                 }
14968         }
14969
14970         /* We need to sanitize the plane -> pipe mapping first because this will
14971          * disable the crtc (and hence change the state) if it is wrong. Note
14972          * that gen4+ has a fixed plane -> pipe mapping.  */
14973         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14974                 bool plane;
14975
14976                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14977                               crtc->base.base.id);
14978
14979                 /* Pipe has the wrong plane attached and the plane is active.
14980                  * Temporarily change the plane mapping and disable everything
14981                  * ...  */
14982                 plane = crtc->plane;
14983                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14984                 crtc->plane = !plane;
14985                 intel_crtc_disable_noatomic(&crtc->base);
14986                 crtc->plane = plane;
14987         }
14988
14989         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14990             crtc->pipe == PIPE_A && !crtc->active) {
14991                 /* BIOS forgot to enable pipe A, this mostly happens after
14992                  * resume. Force-enable the pipe to fix this, the update_dpms
14993                  * call below we restore the pipe to the right state, but leave
14994                  * the required bits on. */
14995                 intel_enable_pipe_a(dev);
14996         }
14997
14998         /* Adjust the state of the output pipe according to whether we
14999          * have active connectors/encoders. */
15000         if (!intel_crtc_has_encoders(crtc))
15001                 intel_crtc_disable_noatomic(&crtc->base);
15002
15003         if (crtc->active != crtc->base.state->active) {
15004                 struct intel_encoder *encoder;
15005
15006                 /* This can happen either due to bugs in the get_hw_state
15007                  * functions or because of calls to intel_crtc_disable_noatomic,
15008                  * or because the pipe is force-enabled due to the
15009                  * pipe A quirk. */
15010                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15011                               crtc->base.base.id,
15012                               crtc->base.state->enable ? "enabled" : "disabled",
15013                               crtc->active ? "enabled" : "disabled");
15014
15015                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15016                 crtc->base.state->active = crtc->active;
15017                 crtc->base.enabled = crtc->active;
15018
15019                 /* Because we only establish the connector -> encoder ->
15020                  * crtc links if something is active, this means the
15021                  * crtc is now deactivated. Break the links. connector
15022                  * -> encoder links are only establish when things are
15023                  *  actually up, hence no need to break them. */
15024                 WARN_ON(crtc->active);
15025
15026                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15027                         encoder->base.crtc = NULL;
15028         }
15029
15030         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15031                 /*
15032                  * We start out with underrun reporting disabled to avoid races.
15033                  * For correct bookkeeping mark this on active crtcs.
15034                  *
15035                  * Also on gmch platforms we dont have any hardware bits to
15036                  * disable the underrun reporting. Which means we need to start
15037                  * out with underrun reporting disabled also on inactive pipes,
15038                  * since otherwise we'll complain about the garbage we read when
15039                  * e.g. coming up after runtime pm.
15040                  *
15041                  * No protection against concurrent access is required - at
15042                  * worst a fifo underrun happens which also sets this to false.
15043                  */
15044                 crtc->cpu_fifo_underrun_disabled = true;
15045                 crtc->pch_fifo_underrun_disabled = true;
15046         }
15047 }
15048
15049 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15050 {
15051         struct intel_connector *connector;
15052         struct drm_device *dev = encoder->base.dev;
15053         bool active = false;
15054
15055         /* We need to check both for a crtc link (meaning that the
15056          * encoder is active and trying to read from a pipe) and the
15057          * pipe itself being active. */
15058         bool has_active_crtc = encoder->base.crtc &&
15059                 to_intel_crtc(encoder->base.crtc)->active;
15060
15061         for_each_intel_connector(dev, connector) {
15062                 if (connector->base.encoder != &encoder->base)
15063                         continue;
15064
15065                 active = true;
15066                 break;
15067         }
15068
15069         if (active && !has_active_crtc) {
15070                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15071                               encoder->base.base.id,
15072                               encoder->base.name);
15073
15074                 /* Connector is active, but has no active pipe. This is
15075                  * fallout from our resume register restoring. Disable
15076                  * the encoder manually again. */
15077                 if (encoder->base.crtc) {
15078                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15079                                       encoder->base.base.id,
15080                                       encoder->base.name);
15081                         encoder->disable(encoder);
15082                         if (encoder->post_disable)
15083                                 encoder->post_disable(encoder);
15084                 }
15085                 encoder->base.crtc = NULL;
15086
15087                 /* Inconsistent output/port/pipe state happens presumably due to
15088                  * a bug in one of the get_hw_state functions. Or someplace else
15089                  * in our code, like the register restore mess on resume. Clamp
15090                  * things to off as a safer default. */
15091                 for_each_intel_connector(dev, connector) {
15092                         if (connector->encoder != encoder)
15093                                 continue;
15094                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15095                         connector->base.encoder = NULL;
15096                 }
15097         }
15098         /* Enabled encoders without active connectors will be fixed in
15099          * the crtc fixup. */
15100 }
15101
15102 void i915_redisable_vga_power_on(struct drm_device *dev)
15103 {
15104         struct drm_i915_private *dev_priv = dev->dev_private;
15105         u32 vga_reg = i915_vgacntrl_reg(dev);
15106
15107         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15108                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15109                 i915_disable_vga(dev);
15110         }
15111 }
15112
15113 void i915_redisable_vga(struct drm_device *dev)
15114 {
15115         struct drm_i915_private *dev_priv = dev->dev_private;
15116
15117         /* This function can be called both from intel_modeset_setup_hw_state or
15118          * at a very early point in our resume sequence, where the power well
15119          * structures are not yet restored. Since this function is at a very
15120          * paranoid "someone might have enabled VGA while we were not looking"
15121          * level, just check if the power well is enabled instead of trying to
15122          * follow the "don't touch the power well if we don't need it" policy
15123          * the rest of the driver uses. */
15124         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15125                 return;
15126
15127         i915_redisable_vga_power_on(dev);
15128 }
15129
15130 static bool primary_get_hw_state(struct intel_plane *plane)
15131 {
15132         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15133
15134         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15135 }
15136
15137 /* FIXME read out full plane state for all planes */
15138 static void readout_plane_state(struct intel_crtc *crtc)
15139 {
15140         struct drm_plane *primary = crtc->base.primary;
15141         struct intel_plane_state *plane_state =
15142                 to_intel_plane_state(primary->state);
15143
15144         plane_state->visible =
15145                 primary_get_hw_state(to_intel_plane(primary));
15146
15147         if (plane_state->visible)
15148                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15149 }
15150
15151 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15152 {
15153         struct drm_i915_private *dev_priv = dev->dev_private;
15154         enum pipe pipe;
15155         struct intel_crtc *crtc;
15156         struct intel_encoder *encoder;
15157         struct intel_connector *connector;
15158         int i;
15159
15160         for_each_intel_crtc(dev, crtc) {
15161                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15162                 memset(crtc->config, 0, sizeof(*crtc->config));
15163                 crtc->config->base.crtc = &crtc->base;
15164
15165                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15166                                                                  crtc->config);
15167
15168                 crtc->base.state->active = crtc->active;
15169                 crtc->base.enabled = crtc->active;
15170
15171                 readout_plane_state(crtc);
15172
15173                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15174                               crtc->base.base.id,
15175                               crtc->active ? "enabled" : "disabled");
15176         }
15177
15178         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15179                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15180
15181                 pll->on = pll->get_hw_state(dev_priv, pll,
15182                                             &pll->config.hw_state);
15183                 pll->active = 0;
15184                 pll->config.crtc_mask = 0;
15185                 for_each_intel_crtc(dev, crtc) {
15186                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15187                                 pll->active++;
15188                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15189                         }
15190                 }
15191
15192                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15193                               pll->name, pll->config.crtc_mask, pll->on);
15194
15195                 if (pll->config.crtc_mask)
15196                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15197         }
15198
15199         for_each_intel_encoder(dev, encoder) {
15200                 pipe = 0;
15201
15202                 if (encoder->get_hw_state(encoder, &pipe)) {
15203                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15204                         encoder->base.crtc = &crtc->base;
15205                         encoder->get_config(encoder, crtc->config);
15206                 } else {
15207                         encoder->base.crtc = NULL;
15208                 }
15209
15210                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15211                               encoder->base.base.id,
15212                               encoder->base.name,
15213                               encoder->base.crtc ? "enabled" : "disabled",
15214                               pipe_name(pipe));
15215         }
15216
15217         for_each_intel_connector(dev, connector) {
15218                 if (connector->get_hw_state(connector)) {
15219                         connector->base.dpms = DRM_MODE_DPMS_ON;
15220                         connector->base.encoder = &connector->encoder->base;
15221                 } else {
15222                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15223                         connector->base.encoder = NULL;
15224                 }
15225                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15226                               connector->base.base.id,
15227                               connector->base.name,
15228                               connector->base.encoder ? "enabled" : "disabled");
15229         }
15230
15231         for_each_intel_crtc(dev, crtc) {
15232                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15233
15234                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15235                 if (crtc->base.state->active) {
15236                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15237                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15238                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15239
15240                         /*
15241                          * The initial mode needs to be set in order to keep
15242                          * the atomic core happy. It wants a valid mode if the
15243                          * crtc's enabled, so we do the above call.
15244                          *
15245                          * At this point some state updated by the connectors
15246                          * in their ->detect() callback has not run yet, so
15247                          * no recalculation can be done yet.
15248                          *
15249                          * Even if we could do a recalculation and modeset
15250                          * right now it would cause a double modeset if
15251                          * fbdev or userspace chooses a different initial mode.
15252                          *
15253                          * If that happens, someone indicated they wanted a
15254                          * mode change, which means it's safe to do a full
15255                          * recalculation.
15256                          */
15257                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15258
15259                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15260                         update_scanline_offset(crtc);
15261                 }
15262         }
15263 }
15264
15265 /* Scan out the current hw modeset state,
15266  * and sanitizes it to the current state
15267  */
15268 static void
15269 intel_modeset_setup_hw_state(struct drm_device *dev)
15270 {
15271         struct drm_i915_private *dev_priv = dev->dev_private;
15272         enum pipe pipe;
15273         struct intel_crtc *crtc;
15274         struct intel_encoder *encoder;
15275         int i;
15276
15277         intel_modeset_readout_hw_state(dev);
15278
15279         /* HW state is read out, now we need to sanitize this mess. */
15280         for_each_intel_encoder(dev, encoder) {
15281                 intel_sanitize_encoder(encoder);
15282         }
15283
15284         for_each_pipe(dev_priv, pipe) {
15285                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15286                 intel_sanitize_crtc(crtc);
15287                 intel_dump_pipe_config(crtc, crtc->config,
15288                                        "[setup_hw_state]");
15289         }
15290
15291         intel_modeset_update_connector_atomic_state(dev);
15292
15293         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15294                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15295
15296                 if (!pll->on || pll->active)
15297                         continue;
15298
15299                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15300
15301                 pll->disable(dev_priv, pll);
15302                 pll->on = false;
15303         }
15304
15305         if (IS_VALLEYVIEW(dev))
15306                 vlv_wm_get_hw_state(dev);
15307         else if (IS_GEN9(dev))
15308                 skl_wm_get_hw_state(dev);
15309         else if (HAS_PCH_SPLIT(dev))
15310                 ilk_wm_get_hw_state(dev);
15311
15312         for_each_intel_crtc(dev, crtc) {
15313                 unsigned long put_domains;
15314
15315                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15316                 if (WARN_ON(put_domains))
15317                         modeset_put_power_domains(dev_priv, put_domains);
15318         }
15319         intel_display_set_init_power(dev_priv, false);
15320 }
15321
15322 void intel_display_resume(struct drm_device *dev)
15323 {
15324         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15325         struct intel_connector *conn;
15326         struct intel_plane *plane;
15327         struct drm_crtc *crtc;
15328         int ret;
15329
15330         if (!state)
15331                 return;
15332
15333         state->acquire_ctx = dev->mode_config.acquire_ctx;
15334
15335         /* preserve complete old state, including dpll */
15336         intel_atomic_get_shared_dpll_state(state);
15337
15338         for_each_crtc(dev, crtc) {
15339                 struct drm_crtc_state *crtc_state =
15340                         drm_atomic_get_crtc_state(state, crtc);
15341
15342                 ret = PTR_ERR_OR_ZERO(crtc_state);
15343                 if (ret)
15344                         goto err;
15345
15346                 /* force a restore */
15347                 crtc_state->mode_changed = true;
15348         }
15349
15350         for_each_intel_plane(dev, plane) {
15351                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15352                 if (ret)
15353                         goto err;
15354         }
15355
15356         for_each_intel_connector(dev, conn) {
15357                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15358                 if (ret)
15359                         goto err;
15360         }
15361
15362         intel_modeset_setup_hw_state(dev);
15363
15364         i915_redisable_vga(dev);
15365         ret = drm_atomic_commit(state);
15366         if (!ret)
15367                 return;
15368
15369 err:
15370         DRM_ERROR("Restoring old state failed with %i\n", ret);
15371         drm_atomic_state_free(state);
15372 }
15373
15374 void intel_modeset_gem_init(struct drm_device *dev)
15375 {
15376         struct drm_crtc *c;
15377         struct drm_i915_gem_object *obj;
15378         int ret;
15379
15380         mutex_lock(&dev->struct_mutex);
15381         intel_init_gt_powersave(dev);
15382         mutex_unlock(&dev->struct_mutex);
15383
15384         intel_modeset_init_hw(dev);
15385
15386         intel_setup_overlay(dev);
15387
15388         /*
15389          * Make sure any fbs we allocated at startup are properly
15390          * pinned & fenced.  When we do the allocation it's too early
15391          * for this.
15392          */
15393         for_each_crtc(dev, c) {
15394                 obj = intel_fb_obj(c->primary->fb);
15395                 if (obj == NULL)
15396                         continue;
15397
15398                 mutex_lock(&dev->struct_mutex);
15399                 ret = intel_pin_and_fence_fb_obj(c->primary,
15400                                                  c->primary->fb,
15401                                                  c->primary->state,
15402                                                  NULL, NULL);
15403                 mutex_unlock(&dev->struct_mutex);
15404                 if (ret) {
15405                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15406                                   to_intel_crtc(c)->pipe);
15407                         drm_framebuffer_unreference(c->primary->fb);
15408                         c->primary->fb = NULL;
15409                         c->primary->crtc = c->primary->state->crtc = NULL;
15410                         update_state_fb(c->primary);
15411                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15412                 }
15413         }
15414
15415         intel_backlight_register(dev);
15416 }
15417
15418 void intel_connector_unregister(struct intel_connector *intel_connector)
15419 {
15420         struct drm_connector *connector = &intel_connector->base;
15421
15422         intel_panel_destroy_backlight(connector);
15423         drm_connector_unregister(connector);
15424 }
15425
15426 void intel_modeset_cleanup(struct drm_device *dev)
15427 {
15428         struct drm_i915_private *dev_priv = dev->dev_private;
15429         struct drm_connector *connector;
15430
15431         intel_disable_gt_powersave(dev);
15432
15433         intel_backlight_unregister(dev);
15434
15435         /*
15436          * Interrupts and polling as the first thing to avoid creating havoc.
15437          * Too much stuff here (turning of connectors, ...) would
15438          * experience fancy races otherwise.
15439          */
15440         intel_irq_uninstall(dev_priv);
15441
15442         /*
15443          * Due to the hpd irq storm handling the hotplug work can re-arm the
15444          * poll handlers. Hence disable polling after hpd handling is shut down.
15445          */
15446         drm_kms_helper_poll_fini(dev);
15447
15448         intel_unregister_dsm_handler();
15449
15450         intel_fbc_disable(dev_priv);
15451
15452         /* flush any delayed tasks or pending work */
15453         flush_scheduled_work();
15454
15455         /* destroy the backlight and sysfs files before encoders/connectors */
15456         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15457                 struct intel_connector *intel_connector;
15458
15459                 intel_connector = to_intel_connector(connector);
15460                 intel_connector->unregister(intel_connector);
15461         }
15462
15463         drm_mode_config_cleanup(dev);
15464
15465         intel_cleanup_overlay(dev);
15466
15467         mutex_lock(&dev->struct_mutex);
15468         intel_cleanup_gt_powersave(dev);
15469         mutex_unlock(&dev->struct_mutex);
15470 }
15471
15472 /*
15473  * Return which encoder is currently attached for connector.
15474  */
15475 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15476 {
15477         return &intel_attached_encoder(connector)->base;
15478 }
15479
15480 void intel_connector_attach_encoder(struct intel_connector *connector,
15481                                     struct intel_encoder *encoder)
15482 {
15483         connector->encoder = encoder;
15484         drm_mode_connector_attach_encoder(&connector->base,
15485                                           &encoder->base);
15486 }
15487
15488 /*
15489  * set vga decode state - true == enable VGA decode
15490  */
15491 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15492 {
15493         struct drm_i915_private *dev_priv = dev->dev_private;
15494         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15495         u16 gmch_ctrl;
15496
15497         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15498                 DRM_ERROR("failed to read control word\n");
15499                 return -EIO;
15500         }
15501
15502         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15503                 return 0;
15504
15505         if (state)
15506                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15507         else
15508                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15509
15510         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15511                 DRM_ERROR("failed to write control word\n");
15512                 return -EIO;
15513         }
15514
15515         return 0;
15516 }
15517
15518 struct intel_display_error_state {
15519
15520         u32 power_well_driver;
15521
15522         int num_transcoders;
15523
15524         struct intel_cursor_error_state {
15525                 u32 control;
15526                 u32 position;
15527                 u32 base;
15528                 u32 size;
15529         } cursor[I915_MAX_PIPES];
15530
15531         struct intel_pipe_error_state {
15532                 bool power_domain_on;
15533                 u32 source;
15534                 u32 stat;
15535         } pipe[I915_MAX_PIPES];
15536
15537         struct intel_plane_error_state {
15538                 u32 control;
15539                 u32 stride;
15540                 u32 size;
15541                 u32 pos;
15542                 u32 addr;
15543                 u32 surface;
15544                 u32 tile_offset;
15545         } plane[I915_MAX_PIPES];
15546
15547         struct intel_transcoder_error_state {
15548                 bool power_domain_on;
15549                 enum transcoder cpu_transcoder;
15550
15551                 u32 conf;
15552
15553                 u32 htotal;
15554                 u32 hblank;
15555                 u32 hsync;
15556                 u32 vtotal;
15557                 u32 vblank;
15558                 u32 vsync;
15559         } transcoder[4];
15560 };
15561
15562 struct intel_display_error_state *
15563 intel_display_capture_error_state(struct drm_device *dev)
15564 {
15565         struct drm_i915_private *dev_priv = dev->dev_private;
15566         struct intel_display_error_state *error;
15567         int transcoders[] = {
15568                 TRANSCODER_A,
15569                 TRANSCODER_B,
15570                 TRANSCODER_C,
15571                 TRANSCODER_EDP,
15572         };
15573         int i;
15574
15575         if (INTEL_INFO(dev)->num_pipes == 0)
15576                 return NULL;
15577
15578         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15579         if (error == NULL)
15580                 return NULL;
15581
15582         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15583                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15584
15585         for_each_pipe(dev_priv, i) {
15586                 error->pipe[i].power_domain_on =
15587                         __intel_display_power_is_enabled(dev_priv,
15588                                                          POWER_DOMAIN_PIPE(i));
15589                 if (!error->pipe[i].power_domain_on)
15590                         continue;
15591
15592                 error->cursor[i].control = I915_READ(CURCNTR(i));
15593                 error->cursor[i].position = I915_READ(CURPOS(i));
15594                 error->cursor[i].base = I915_READ(CURBASE(i));
15595
15596                 error->plane[i].control = I915_READ(DSPCNTR(i));
15597                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15598                 if (INTEL_INFO(dev)->gen <= 3) {
15599                         error->plane[i].size = I915_READ(DSPSIZE(i));
15600                         error->plane[i].pos = I915_READ(DSPPOS(i));
15601                 }
15602                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15603                         error->plane[i].addr = I915_READ(DSPADDR(i));
15604                 if (INTEL_INFO(dev)->gen >= 4) {
15605                         error->plane[i].surface = I915_READ(DSPSURF(i));
15606                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15607                 }
15608
15609                 error->pipe[i].source = I915_READ(PIPESRC(i));
15610
15611                 if (HAS_GMCH_DISPLAY(dev))
15612                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15613         }
15614
15615         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15616         if (HAS_DDI(dev_priv->dev))
15617                 error->num_transcoders++; /* Account for eDP. */
15618
15619         for (i = 0; i < error->num_transcoders; i++) {
15620                 enum transcoder cpu_transcoder = transcoders[i];
15621
15622                 error->transcoder[i].power_domain_on =
15623                         __intel_display_power_is_enabled(dev_priv,
15624                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15625                 if (!error->transcoder[i].power_domain_on)
15626                         continue;
15627
15628                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15629
15630                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15631                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15632                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15633                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15634                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15635                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15636                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15637         }
15638
15639         return error;
15640 }
15641
15642 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15643
15644 void
15645 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15646                                 struct drm_device *dev,
15647                                 struct intel_display_error_state *error)
15648 {
15649         struct drm_i915_private *dev_priv = dev->dev_private;
15650         int i;
15651
15652         if (!error)
15653                 return;
15654
15655         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15656         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15657                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15658                            error->power_well_driver);
15659         for_each_pipe(dev_priv, i) {
15660                 err_printf(m, "Pipe [%d]:\n", i);
15661                 err_printf(m, "  Power: %s\n",
15662                            error->pipe[i].power_domain_on ? "on" : "off");
15663                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15664                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15665
15666                 err_printf(m, "Plane [%d]:\n", i);
15667                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15668                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15669                 if (INTEL_INFO(dev)->gen <= 3) {
15670                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15671                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15672                 }
15673                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15674                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15675                 if (INTEL_INFO(dev)->gen >= 4) {
15676                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15677                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15678                 }
15679
15680                 err_printf(m, "Cursor [%d]:\n", i);
15681                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15682                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15683                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15684         }
15685
15686         for (i = 0; i < error->num_transcoders; i++) {
15687                 err_printf(m, "CPU transcoder: %c\n",
15688                            transcoder_name(error->transcoder[i].cpu_transcoder));
15689                 err_printf(m, "  Power: %s\n",
15690                            error->transcoder[i].power_domain_on ? "on" : "off");
15691                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15692                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15693                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15694                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15695                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15696                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15697                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15698         }
15699 }
15700
15701 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15702 {
15703         struct intel_crtc *crtc;
15704
15705         for_each_intel_crtc(dev, crtc) {
15706                 struct intel_unpin_work *work;
15707
15708                 spin_lock_irq(&dev->event_lock);
15709
15710                 work = crtc->unpin_work;
15711
15712                 if (work && work->event &&
15713                     work->event->base.file_priv == file) {
15714                         kfree(work->event);
15715                         work->event = NULL;
15716                 }
15717
15718                 spin_unlock_irq(&dev->event_lock);
15719         }
15720 }