Merge remote-tracking branch 'drm-intel/for-linux-next'
[karo-tx-linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50         DRM_FORMAT_C8,
51         DRM_FORMAT_RGB565,
52         DRM_FORMAT_XRGB1555,
53         DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58         DRM_FORMAT_C8,
59         DRM_FORMAT_RGB565,
60         DRM_FORMAT_XRGB8888,
61         DRM_FORMAT_XBGR8888,
62         DRM_FORMAT_XRGB2101010,
63         DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67         DRM_FORMAT_C8,
68         DRM_FORMAT_RGB565,
69         DRM_FORMAT_XRGB8888,
70         DRM_FORMAT_XBGR8888,
71         DRM_FORMAT_ARGB8888,
72         DRM_FORMAT_ABGR8888,
73         DRM_FORMAT_XRGB2101010,
74         DRM_FORMAT_XBGR2101010,
75         DRM_FORMAT_YUYV,
76         DRM_FORMAT_YVYU,
77         DRM_FORMAT_UYVY,
78         DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83         DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89                                 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91                                    struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94                                   struct intel_framebuffer *ifb,
95                                   struct drm_mode_fb_cmd2 *mode_cmd,
96                                   struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100                                          struct intel_link_m_n *m_n,
101                                          struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106                             const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108                             const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112         struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114                            int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121         int     min, max;
122 } intel_range_t;
123
124 typedef struct {
125         int     dot_limit;
126         int     p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
132         intel_p2_t          p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140         /* Obtain SKU information */
141         mutex_lock(&dev_priv->sb_lock);
142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143                 CCK_FUSE_HPLL_FREQ_MASK;
144         mutex_unlock(&dev_priv->sb_lock);
145
146         return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150                                   const char *name, u32 reg)
151 {
152         u32 val;
153         int divider;
154
155         if (dev_priv->hpll_freq == 0)
156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158         mutex_lock(&dev_priv->sb_lock);
159         val = vlv_cck_read(dev_priv, reg);
160         mutex_unlock(&dev_priv->sb_lock);
161
162         divider = val & CCK_FREQUENCY_VALUES;
163
164         WARN((val & CCK_FREQUENCY_STATUS) !=
165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
166              "%s change in progress\n", name);
167
168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174         struct drm_i915_private *dev_priv = dev->dev_private;
175
176         WARN_ON(!HAS_PCH_SPLIT(dev));
177
178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184         struct drm_i915_private *dev_priv = dev->dev_private;
185         uint32_t clkcfg;
186
187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188         if (IS_VALLEYVIEW(dev))
189                 return 200;
190
191         clkcfg = I915_READ(CLKCFG);
192         switch (clkcfg & CLKCFG_FSB_MASK) {
193         case CLKCFG_FSB_400:
194                 return 100;
195         case CLKCFG_FSB_533:
196                 return 133;
197         case CLKCFG_FSB_667:
198                 return 166;
199         case CLKCFG_FSB_800:
200                 return 200;
201         case CLKCFG_FSB_1067:
202                 return 266;
203         case CLKCFG_FSB_1333:
204                 return 333;
205         /* these two are just a guess; one of them might be right */
206         case CLKCFG_FSB_1600:
207         case CLKCFG_FSB_1600_ALT:
208                 return 400;
209         default:
210                 return 133;
211         }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216         if (!IS_VALLEYVIEW(dev_priv))
217                 return;
218
219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220                                                       CCK_CZ_CLOCK_CONTROL);
221
222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228         if (IS_GEN5(dev)) {
229                 struct drm_i915_private *dev_priv = dev->dev_private;
230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231         } else
232                 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236         .dot = { .min = 25000, .max = 350000 },
237         .vco = { .min = 908000, .max = 1512000 },
238         .n = { .min = 2, .max = 16 },
239         .m = { .min = 96, .max = 140 },
240         .m1 = { .min = 18, .max = 26 },
241         .m2 = { .min = 6, .max = 16 },
242         .p = { .min = 4, .max = 128 },
243         .p1 = { .min = 2, .max = 33 },
244         .p2 = { .dot_limit = 165000,
245                 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249         .dot = { .min = 25000, .max = 350000 },
250         .vco = { .min = 908000, .max = 1512000 },
251         .n = { .min = 2, .max = 16 },
252         .m = { .min = 96, .max = 140 },
253         .m1 = { .min = 18, .max = 26 },
254         .m2 = { .min = 6, .max = 16 },
255         .p = { .min = 4, .max = 128 },
256         .p1 = { .min = 2, .max = 33 },
257         .p2 = { .dot_limit = 165000,
258                 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262         .dot = { .min = 25000, .max = 350000 },
263         .vco = { .min = 908000, .max = 1512000 },
264         .n = { .min = 2, .max = 16 },
265         .m = { .min = 96, .max = 140 },
266         .m1 = { .min = 18, .max = 26 },
267         .m2 = { .min = 6, .max = 16 },
268         .p = { .min = 4, .max = 128 },
269         .p1 = { .min = 1, .max = 6 },
270         .p2 = { .dot_limit = 165000,
271                 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275         .dot = { .min = 20000, .max = 400000 },
276         .vco = { .min = 1400000, .max = 2800000 },
277         .n = { .min = 1, .max = 6 },
278         .m = { .min = 70, .max = 120 },
279         .m1 = { .min = 8, .max = 18 },
280         .m2 = { .min = 3, .max = 7 },
281         .p = { .min = 5, .max = 80 },
282         .p1 = { .min = 1, .max = 8 },
283         .p2 = { .dot_limit = 200000,
284                 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288         .dot = { .min = 20000, .max = 400000 },
289         .vco = { .min = 1400000, .max = 2800000 },
290         .n = { .min = 1, .max = 6 },
291         .m = { .min = 70, .max = 120 },
292         .m1 = { .min = 8, .max = 18 },
293         .m2 = { .min = 3, .max = 7 },
294         .p = { .min = 7, .max = 98 },
295         .p1 = { .min = 1, .max = 8 },
296         .p2 = { .dot_limit = 112000,
297                 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302         .dot = { .min = 25000, .max = 270000 },
303         .vco = { .min = 1750000, .max = 3500000},
304         .n = { .min = 1, .max = 4 },
305         .m = { .min = 104, .max = 138 },
306         .m1 = { .min = 17, .max = 23 },
307         .m2 = { .min = 5, .max = 11 },
308         .p = { .min = 10, .max = 30 },
309         .p1 = { .min = 1, .max = 3},
310         .p2 = { .dot_limit = 270000,
311                 .p2_slow = 10,
312                 .p2_fast = 10
313         },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317         .dot = { .min = 22000, .max = 400000 },
318         .vco = { .min = 1750000, .max = 3500000},
319         .n = { .min = 1, .max = 4 },
320         .m = { .min = 104, .max = 138 },
321         .m1 = { .min = 16, .max = 23 },
322         .m2 = { .min = 5, .max = 11 },
323         .p = { .min = 5, .max = 80 },
324         .p1 = { .min = 1, .max = 8},
325         .p2 = { .dot_limit = 165000,
326                 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330         .dot = { .min = 20000, .max = 115000 },
331         .vco = { .min = 1750000, .max = 3500000 },
332         .n = { .min = 1, .max = 3 },
333         .m = { .min = 104, .max = 138 },
334         .m1 = { .min = 17, .max = 23 },
335         .m2 = { .min = 5, .max = 11 },
336         .p = { .min = 28, .max = 112 },
337         .p1 = { .min = 2, .max = 8 },
338         .p2 = { .dot_limit = 0,
339                 .p2_slow = 14, .p2_fast = 14
340         },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344         .dot = { .min = 80000, .max = 224000 },
345         .vco = { .min = 1750000, .max = 3500000 },
346         .n = { .min = 1, .max = 3 },
347         .m = { .min = 104, .max = 138 },
348         .m1 = { .min = 17, .max = 23 },
349         .m2 = { .min = 5, .max = 11 },
350         .p = { .min = 14, .max = 42 },
351         .p1 = { .min = 2, .max = 6 },
352         .p2 = { .dot_limit = 0,
353                 .p2_slow = 7, .p2_fast = 7
354         },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358         .dot = { .min = 20000, .max = 400000},
359         .vco = { .min = 1700000, .max = 3500000 },
360         /* Pineview's Ncounter is a ring counter */
361         .n = { .min = 3, .max = 6 },
362         .m = { .min = 2, .max = 256 },
363         /* Pineview only has one combined m divider, which we treat as m2. */
364         .m1 = { .min = 0, .max = 0 },
365         .m2 = { .min = 0, .max = 254 },
366         .p = { .min = 5, .max = 80 },
367         .p1 = { .min = 1, .max = 8 },
368         .p2 = { .dot_limit = 200000,
369                 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373         .dot = { .min = 20000, .max = 400000 },
374         .vco = { .min = 1700000, .max = 3500000 },
375         .n = { .min = 3, .max = 6 },
376         .m = { .min = 2, .max = 256 },
377         .m1 = { .min = 0, .max = 0 },
378         .m2 = { .min = 0, .max = 254 },
379         .p = { .min = 7, .max = 112 },
380         .p1 = { .min = 1, .max = 8 },
381         .p2 = { .dot_limit = 112000,
382                 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386  *
387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
388  * the range value for them is (actual_value - 2).
389  */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391         .dot = { .min = 25000, .max = 350000 },
392         .vco = { .min = 1760000, .max = 3510000 },
393         .n = { .min = 1, .max = 5 },
394         .m = { .min = 79, .max = 127 },
395         .m1 = { .min = 12, .max = 22 },
396         .m2 = { .min = 5, .max = 9 },
397         .p = { .min = 5, .max = 80 },
398         .p1 = { .min = 1, .max = 8 },
399         .p2 = { .dot_limit = 225000,
400                 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404         .dot = { .min = 25000, .max = 350000 },
405         .vco = { .min = 1760000, .max = 3510000 },
406         .n = { .min = 1, .max = 3 },
407         .m = { .min = 79, .max = 118 },
408         .m1 = { .min = 12, .max = 22 },
409         .m2 = { .min = 5, .max = 9 },
410         .p = { .min = 28, .max = 112 },
411         .p1 = { .min = 2, .max = 8 },
412         .p2 = { .dot_limit = 225000,
413                 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417         .dot = { .min = 25000, .max = 350000 },
418         .vco = { .min = 1760000, .max = 3510000 },
419         .n = { .min = 1, .max = 3 },
420         .m = { .min = 79, .max = 127 },
421         .m1 = { .min = 12, .max = 22 },
422         .m2 = { .min = 5, .max = 9 },
423         .p = { .min = 14, .max = 56 },
424         .p1 = { .min = 2, .max = 8 },
425         .p2 = { .dot_limit = 225000,
426                 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431         .dot = { .min = 25000, .max = 350000 },
432         .vco = { .min = 1760000, .max = 3510000 },
433         .n = { .min = 1, .max = 2 },
434         .m = { .min = 79, .max = 126 },
435         .m1 = { .min = 12, .max = 22 },
436         .m2 = { .min = 5, .max = 9 },
437         .p = { .min = 28, .max = 112 },
438         .p1 = { .min = 2, .max = 8 },
439         .p2 = { .dot_limit = 225000,
440                 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444         .dot = { .min = 25000, .max = 350000 },
445         .vco = { .min = 1760000, .max = 3510000 },
446         .n = { .min = 1, .max = 3 },
447         .m = { .min = 79, .max = 126 },
448         .m1 = { .min = 12, .max = 22 },
449         .m2 = { .min = 5, .max = 9 },
450         .p = { .min = 14, .max = 42 },
451         .p1 = { .min = 2, .max = 6 },
452         .p2 = { .dot_limit = 225000,
453                 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457          /*
458           * These are the data rate limits (measured in fast clocks)
459           * since those are the strictest limits we have. The fast
460           * clock and actual rate limits are more relaxed, so checking
461           * them would make no difference.
462           */
463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464         .vco = { .min = 4000000, .max = 6000000 },
465         .n = { .min = 1, .max = 7 },
466         .m1 = { .min = 2, .max = 3 },
467         .m2 = { .min = 11, .max = 156 },
468         .p1 = { .min = 2, .max = 3 },
469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473         /*
474          * These are the data rate limits (measured in fast clocks)
475          * since those are the strictest limits we have.  The fast
476          * clock and actual rate limits are more relaxed, so checking
477          * them would make no difference.
478          */
479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
480         .vco = { .min = 4800000, .max = 6480000 },
481         .n = { .min = 1, .max = 1 },
482         .m1 = { .min = 2, .max = 2 },
483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
484         .p1 = { .min = 2, .max = 4 },
485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489         /* FIXME: find real dot limits */
490         .dot = { .min = 0, .max = INT_MAX },
491         .vco = { .min = 4800000, .max = 6700000 },
492         .n = { .min = 1, .max = 1 },
493         .m1 = { .min = 2, .max = 2 },
494         /* FIXME: find real m2 limits */
495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
496         .p1 = { .min = 2, .max = 4 },
497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503         return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507  * Returns whether any output on the specified pipe is of the specified type
508  */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511         struct drm_device *dev = crtc->base.dev;
512         struct intel_encoder *encoder;
513
514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515                 if (encoder->type == type)
516                         return true;
517
518         return false;
519 }
520
521 /**
522  * Returns whether any output on the specified pipe will have the specified
523  * type after a staged modeset is complete, i.e., the same as
524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525  * encoder->crtc.
526  */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528                                       int type)
529 {
530         struct drm_atomic_state *state = crtc_state->base.state;
531         struct drm_connector *connector;
532         struct drm_connector_state *connector_state;
533         struct intel_encoder *encoder;
534         int i, num_connectors = 0;
535
536         for_each_connector_in_state(state, connector, connector_state, i) {
537                 if (connector_state->crtc != crtc_state->base.crtc)
538                         continue;
539
540                 num_connectors++;
541
542                 encoder = to_intel_encoder(connector_state->best_encoder);
543                 if (encoder->type == type)
544                         return true;
545         }
546
547         WARN_ON(num_connectors == 0);
548
549         return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555         struct drm_device *dev = crtc_state->base.crtc->dev;
556         const intel_limit_t *limit;
557
558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559                 if (intel_is_dual_link_lvds(dev)) {
560                         if (refclk == 100000)
561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
562                         else
563                                 limit = &intel_limits_ironlake_dual_lvds;
564                 } else {
565                         if (refclk == 100000)
566                                 limit = &intel_limits_ironlake_single_lvds_100m;
567                         else
568                                 limit = &intel_limits_ironlake_single_lvds;
569                 }
570         } else
571                 limit = &intel_limits_ironlake_dac;
572
573         return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579         struct drm_device *dev = crtc_state->base.crtc->dev;
580         const intel_limit_t *limit;
581
582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583                 if (intel_is_dual_link_lvds(dev))
584                         limit = &intel_limits_g4x_dual_channel_lvds;
585                 else
586                         limit = &intel_limits_g4x_single_channel_lvds;
587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589                 limit = &intel_limits_g4x_hdmi;
590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591                 limit = &intel_limits_g4x_sdvo;
592         } else /* The option is for other outputs */
593                 limit = &intel_limits_i9xx_sdvo;
594
595         return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601         struct drm_device *dev = crtc_state->base.crtc->dev;
602         const intel_limit_t *limit;
603
604         if (IS_BROXTON(dev))
605                 limit = &intel_limits_bxt;
606         else if (HAS_PCH_SPLIT(dev))
607                 limit = intel_ironlake_limit(crtc_state, refclk);
608         else if (IS_G4X(dev)) {
609                 limit = intel_g4x_limit(crtc_state);
610         } else if (IS_PINEVIEW(dev)) {
611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612                         limit = &intel_limits_pineview_lvds;
613                 else
614                         limit = &intel_limits_pineview_sdvo;
615         } else if (IS_CHERRYVIEW(dev)) {
616                 limit = &intel_limits_chv;
617         } else if (IS_VALLEYVIEW(dev)) {
618                 limit = &intel_limits_vlv;
619         } else if (!IS_GEN2(dev)) {
620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621                         limit = &intel_limits_i9xx_lvds;
622                 else
623                         limit = &intel_limits_i9xx_sdvo;
624         } else {
625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626                         limit = &intel_limits_i8xx_lvds;
627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628                         limit = &intel_limits_i8xx_dvo;
629                 else
630                         limit = &intel_limits_i8xx_dac;
631         }
632         return limit;
633 }
634
635 /*
636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639  * The helpers' return value is the rate of the clock that is fed to the
640  * display engine's pipe which can be the above fast dot clock rate or a
641  * divided-down version of it.
642  */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646         clock->m = clock->m2 + 2;
647         clock->p = clock->p1 * clock->p2;
648         if (WARN_ON(clock->n == 0 || clock->p == 0))
649                 return 0;
650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653         return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663         clock->m = i9xx_dpll_compute_m(clock);
664         clock->p = clock->p1 * clock->p2;
665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666                 return 0;
667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670         return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675         clock->m = clock->m1 * clock->m2;
676         clock->p = clock->p1 * clock->p2;
677         if (WARN_ON(clock->n == 0 || clock->p == 0))
678                 return 0;
679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682         return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687         clock->m = clock->m1 * clock->m2;
688         clock->p = clock->p1 * clock->p2;
689         if (WARN_ON(clock->n == 0 || clock->p == 0))
690                 return 0;
691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692                         clock->n << 22);
693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695         return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700  * Returns whether the given set of divisors are valid for a given refclk with
701  * the given connectors.
702  */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705                                const intel_limit_t *limit,
706                                const intel_clock_t *clock)
707 {
708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
709                 INTELPllInvalid("n out of range\n");
710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
711                 INTELPllInvalid("p1 out of range\n");
712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
713                 INTELPllInvalid("m2 out of range\n");
714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
715                 INTELPllInvalid("m1 out of range\n");
716
717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718                 if (clock->m1 <= clock->m2)
719                         INTELPllInvalid("m1 <= m2\n");
720
721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
723                         INTELPllInvalid("p out of range\n");
724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
725                         INTELPllInvalid("m out of range\n");
726         }
727
728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729                 INTELPllInvalid("vco out of range\n");
730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731          * connector, etc., rather than just a single range.
732          */
733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734                 INTELPllInvalid("dot out of range\n");
735
736         return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741                    const struct intel_crtc_state *crtc_state,
742                    int target)
743 {
744         struct drm_device *dev = crtc_state->base.crtc->dev;
745
746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747                 /*
748                  * For LVDS just rely on its current settings for dual-channel.
749                  * We haven't figured out how to reliably set up different
750                  * single/dual channel state, if we even can.
751                  */
752                 if (intel_is_dual_link_lvds(dev))
753                         return limit->p2.p2_fast;
754                 else
755                         return limit->p2.p2_slow;
756         } else {
757                 if (target < limit->p2.dot_limit)
758                         return limit->p2.p2_slow;
759                 else
760                         return limit->p2.p2_fast;
761         }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766                     struct intel_crtc_state *crtc_state,
767                     int target, int refclk, intel_clock_t *match_clock,
768                     intel_clock_t *best_clock)
769 {
770         struct drm_device *dev = crtc_state->base.crtc->dev;
771         intel_clock_t clock;
772         int err = target;
773
774         memset(best_clock, 0, sizeof(*best_clock));
775
776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779              clock.m1++) {
780                 for (clock.m2 = limit->m2.min;
781                      clock.m2 <= limit->m2.max; clock.m2++) {
782                         if (clock.m2 >= clock.m1)
783                                 break;
784                         for (clock.n = limit->n.min;
785                              clock.n <= limit->n.max; clock.n++) {
786                                 for (clock.p1 = limit->p1.min;
787                                         clock.p1 <= limit->p1.max; clock.p1++) {
788                                         int this_err;
789
790                                         i9xx_calc_dpll_params(refclk, &clock);
791                                         if (!intel_PLL_is_valid(dev, limit,
792                                                                 &clock))
793                                                 continue;
794                                         if (match_clock &&
795                                             clock.p != match_clock->p)
796                                                 continue;
797
798                                         this_err = abs(clock.dot - target);
799                                         if (this_err < err) {
800                                                 *best_clock = clock;
801                                                 err = this_err;
802                                         }
803                                 }
804                         }
805                 }
806         }
807
808         return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813                    struct intel_crtc_state *crtc_state,
814                    int target, int refclk, intel_clock_t *match_clock,
815                    intel_clock_t *best_clock)
816 {
817         struct drm_device *dev = crtc_state->base.crtc->dev;
818         intel_clock_t clock;
819         int err = target;
820
821         memset(best_clock, 0, sizeof(*best_clock));
822
823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826              clock.m1++) {
827                 for (clock.m2 = limit->m2.min;
828                      clock.m2 <= limit->m2.max; clock.m2++) {
829                         for (clock.n = limit->n.min;
830                              clock.n <= limit->n.max; clock.n++) {
831                                 for (clock.p1 = limit->p1.min;
832                                         clock.p1 <= limit->p1.max; clock.p1++) {
833                                         int this_err;
834
835                                         pnv_calc_dpll_params(refclk, &clock);
836                                         if (!intel_PLL_is_valid(dev, limit,
837                                                                 &clock))
838                                                 continue;
839                                         if (match_clock &&
840                                             clock.p != match_clock->p)
841                                                 continue;
842
843                                         this_err = abs(clock.dot - target);
844                                         if (this_err < err) {
845                                                 *best_clock = clock;
846                                                 err = this_err;
847                                         }
848                                 }
849                         }
850                 }
851         }
852
853         return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858                    struct intel_crtc_state *crtc_state,
859                    int target, int refclk, intel_clock_t *match_clock,
860                    intel_clock_t *best_clock)
861 {
862         struct drm_device *dev = crtc_state->base.crtc->dev;
863         intel_clock_t clock;
864         int max_n;
865         bool found = false;
866         /* approximately equals target * 0.00585 */
867         int err_most = (target >> 8) + (target >> 9);
868
869         memset(best_clock, 0, sizeof(*best_clock));
870
871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873         max_n = limit->n.max;
874         /* based on hardware requirement, prefer smaller n to precision */
875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876                 /* based on hardware requirement, prefere larger m1,m2 */
877                 for (clock.m1 = limit->m1.max;
878                      clock.m1 >= limit->m1.min; clock.m1--) {
879                         for (clock.m2 = limit->m2.max;
880                              clock.m2 >= limit->m2.min; clock.m2--) {
881                                 for (clock.p1 = limit->p1.max;
882                                      clock.p1 >= limit->p1.min; clock.p1--) {
883                                         int this_err;
884
885                                         i9xx_calc_dpll_params(refclk, &clock);
886                                         if (!intel_PLL_is_valid(dev, limit,
887                                                                 &clock))
888                                                 continue;
889
890                                         this_err = abs(clock.dot - target);
891                                         if (this_err < err_most) {
892                                                 *best_clock = clock;
893                                                 err_most = this_err;
894                                                 max_n = clock.n;
895                                                 found = true;
896                                         }
897                                 }
898                         }
899                 }
900         }
901         return found;
902 }
903
904 /*
905  * Check if the calculated PLL configuration is more optimal compared to the
906  * best configuration and error found so far. Return the calculated error.
907  */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909                                const intel_clock_t *calculated_clock,
910                                const intel_clock_t *best_clock,
911                                unsigned int best_error_ppm,
912                                unsigned int *error_ppm)
913 {
914         /*
915          * For CHV ignore the error and consider only the P value.
916          * Prefer a bigger P value based on HW requirements.
917          */
918         if (IS_CHERRYVIEW(dev)) {
919                 *error_ppm = 0;
920
921                 return calculated_clock->p > best_clock->p;
922         }
923
924         if (WARN_ON_ONCE(!target_freq))
925                 return false;
926
927         *error_ppm = div_u64(1000000ULL *
928                                 abs(target_freq - calculated_clock->dot),
929                              target_freq);
930         /*
931          * Prefer a better P value over a better (smaller) error if the error
932          * is small. Ensure this preference for future configurations too by
933          * setting the error to 0.
934          */
935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936                 *error_ppm = 0;
937
938                 return true;
939         }
940
941         return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946                    struct intel_crtc_state *crtc_state,
947                    int target, int refclk, intel_clock_t *match_clock,
948                    intel_clock_t *best_clock)
949 {
950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951         struct drm_device *dev = crtc->base.dev;
952         intel_clock_t clock;
953         unsigned int bestppm = 1000000;
954         /* min update 19.2 MHz */
955         int max_n = min(limit->n.max, refclk / 19200);
956         bool found = false;
957
958         target *= 5; /* fast clock */
959
960         memset(best_clock, 0, sizeof(*best_clock));
961
962         /* based on hardware requirement, prefer smaller n to precision */
963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967                                 clock.p = clock.p1 * clock.p2;
968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970                                         unsigned int ppm;
971
972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973                                                                      refclk * clock.m1);
974
975                                         vlv_calc_dpll_params(refclk, &clock);
976
977                                         if (!intel_PLL_is_valid(dev, limit,
978                                                                 &clock))
979                                                 continue;
980
981                                         if (!vlv_PLL_is_optimal(dev, target,
982                                                                 &clock,
983                                                                 best_clock,
984                                                                 bestppm, &ppm))
985                                                 continue;
986
987                                         *best_clock = clock;
988                                         bestppm = ppm;
989                                         found = true;
990                                 }
991                         }
992                 }
993         }
994
995         return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 int reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         u32 val;
1161         bool cur_state;
1162
1163         val = I915_READ(DPLL(pipe));
1164         cur_state = !!(val & DPLL_VCO_ENABLE);
1165         I915_STATE_WARN(cur_state != state,
1166              "PLL state assertion failure (expected %s, current %s)\n",
1167              state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173         u32 val;
1174         bool cur_state;
1175
1176         mutex_lock(&dev_priv->sb_lock);
1177         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178         mutex_unlock(&dev_priv->sb_lock);
1179
1180         cur_state = val & DSI_PLL_VCO_EN;
1181         I915_STATE_WARN(cur_state != state,
1182              "DSI PLL state assertion failure (expected %s, current %s)\n",
1183              state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193         if (crtc->config->shared_dpll < 0)
1194                 return NULL;
1195
1196         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201                         struct intel_shared_dpll *pll,
1202                         bool state)
1203 {
1204         bool cur_state;
1205         struct intel_dpll_hw_state hw_state;
1206
1207         if (WARN (!pll,
1208                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1209                 return;
1210
1211         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212         I915_STATE_WARN(cur_state != state,
1213              "%s assertion failure (expected %s, current %s)\n",
1214              pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218                           enum pipe pipe, bool state)
1219 {
1220         bool cur_state;
1221         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222                                                                       pipe);
1223
1224         if (HAS_DDI(dev_priv->dev)) {
1225                 /* DDI does not have a specific FDI_TX register */
1226                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228         } else {
1229                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230                 cur_state = !!(val & FDI_TX_ENABLE);
1231         }
1232         I915_STATE_WARN(cur_state != state,
1233              "FDI TX state assertion failure (expected %s, current %s)\n",
1234              state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240                           enum pipe pipe, bool state)
1241 {
1242         u32 val;
1243         bool cur_state;
1244
1245         val = I915_READ(FDI_RX_CTL(pipe));
1246         cur_state = !!(val & FDI_RX_ENABLE);
1247         I915_STATE_WARN(cur_state != state,
1248              "FDI RX state assertion failure (expected %s, current %s)\n",
1249              state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255                                       enum pipe pipe)
1256 {
1257         u32 val;
1258
1259         /* ILK FDI PLL is always enabled */
1260         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261                 return;
1262
1263         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264         if (HAS_DDI(dev_priv->dev))
1265                 return;
1266
1267         val = I915_READ(FDI_TX_CTL(pipe));
1268         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272                        enum pipe pipe, bool state)
1273 {
1274         u32 val;
1275         bool cur_state;
1276
1277         val = I915_READ(FDI_RX_CTL(pipe));
1278         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279         I915_STATE_WARN(cur_state != state,
1280              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281              state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285                            enum pipe pipe)
1286 {
1287         struct drm_device *dev = dev_priv->dev;
1288         int pp_reg;
1289         u32 val;
1290         enum pipe panel_pipe = PIPE_A;
1291         bool locked = true;
1292
1293         if (WARN_ON(HAS_DDI(dev)))
1294                 return;
1295
1296         if (HAS_PCH_SPLIT(dev)) {
1297                 u32 port_sel;
1298
1299                 pp_reg = PCH_PP_CONTROL;
1300                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304                         panel_pipe = PIPE_B;
1305                 /* XXX: else fix for eDP */
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 /* presumably write lock depends on pipe, not port select */
1308                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309                 panel_pipe = pipe;
1310         } else {
1311                 pp_reg = PP_CONTROL;
1312                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313                         panel_pipe = PIPE_B;
1314         }
1315
1316         val = I915_READ(pp_reg);
1317         if (!(val & PANEL_POWER_ON) ||
1318             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319                 locked = false;
1320
1321         I915_STATE_WARN(panel_pipe == pipe && locked,
1322              "panel assertion failure, pipe %c regs locked\n",
1323              pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327                           enum pipe pipe, bool state)
1328 {
1329         struct drm_device *dev = dev_priv->dev;
1330         bool cur_state;
1331
1332         if (IS_845G(dev) || IS_I865G(dev))
1333                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334         else
1335                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345                  enum pipe pipe, bool state)
1346 {
1347         bool cur_state;
1348         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349                                                                       pipe);
1350
1351         /* if we need the pipe quirk it must be always on */
1352         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354                 state = true;
1355
1356         if (!intel_display_power_is_enabled(dev_priv,
1357                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358                 cur_state = false;
1359         } else {
1360                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361                 cur_state = !!(val & PIPECONF_ENABLE);
1362         }
1363
1364         I915_STATE_WARN(cur_state != state,
1365              "pipe %c assertion failure (expected %s, current %s)\n",
1366              pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370                          enum plane plane, bool state)
1371 {
1372         u32 val;
1373         bool cur_state;
1374
1375         val = I915_READ(DSPCNTR(plane));
1376         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377         I915_STATE_WARN(cur_state != state,
1378              "plane %c assertion failure (expected %s, current %s)\n",
1379              plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe)
1387 {
1388         struct drm_device *dev = dev_priv->dev;
1389         int i;
1390
1391         /* Primary planes are fixed to pipes on gen4+ */
1392         if (INTEL_INFO(dev)->gen >= 4) {
1393                 u32 val = I915_READ(DSPCNTR(pipe));
1394                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395                      "plane %c assertion failure, should be disabled but not\n",
1396                      plane_name(pipe));
1397                 return;
1398         }
1399
1400         /* Need to check both planes against the pipe */
1401         for_each_pipe(dev_priv, i) {
1402                 u32 val = I915_READ(DSPCNTR(i));
1403                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404                         DISPPLANE_SEL_PIPE_SHIFT;
1405                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407                      plane_name(i), pipe_name(pipe));
1408         }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412                                     enum pipe pipe)
1413 {
1414         struct drm_device *dev = dev_priv->dev;
1415         int sprite;
1416
1417         if (INTEL_INFO(dev)->gen >= 9) {
1418                 for_each_sprite(dev_priv, pipe, sprite) {
1419                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422                              sprite, pipe_name(pipe));
1423                 }
1424         } else if (IS_VALLEYVIEW(dev)) {
1425                 for_each_sprite(dev_priv, pipe, sprite) {
1426                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1427                         I915_STATE_WARN(val & SP_ENABLE,
1428                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429                              sprite_name(pipe, sprite), pipe_name(pipe));
1430                 }
1431         } else if (INTEL_INFO(dev)->gen >= 7) {
1432                 u32 val = I915_READ(SPRCTL(pipe));
1433                 I915_STATE_WARN(val & SPRITE_ENABLE,
1434                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435                      plane_name(pipe), pipe_name(pipe));
1436         } else if (INTEL_INFO(dev)->gen >= 5) {
1437                 u32 val = I915_READ(DVSCNTR(pipe));
1438                 I915_STATE_WARN(val & DVS_ENABLE,
1439                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440                      plane_name(pipe), pipe_name(pipe));
1441         }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447                 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452         u32 val;
1453         bool enabled;
1454
1455         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457         val = I915_READ(PCH_DREF_CONTROL);
1458         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459                             DREF_SUPERSPREAD_SOURCE_MASK));
1460         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464                                            enum pipe pipe)
1465 {
1466         u32 val;
1467         bool enabled;
1468
1469         val = I915_READ(PCH_TRANSCONF(pipe));
1470         enabled = !!(val & TRANS_ENABLE);
1471         I915_STATE_WARN(enabled,
1472              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473              pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477                             enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479         if ((val & DP_PORT_EN) == 0)
1480                 return false;
1481
1482         if (HAS_PCH_CPT(dev_priv->dev)) {
1483                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486                         return false;
1487         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489                         return false;
1490         } else {
1491                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492                         return false;
1493         }
1494         return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498                               enum pipe pipe, u32 val)
1499 {
1500         if ((val & SDVO_ENABLE) == 0)
1501                 return false;
1502
1503         if (HAS_PCH_CPT(dev_priv->dev)) {
1504                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505                         return false;
1506         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508                         return false;
1509         } else {
1510                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511                         return false;
1512         }
1513         return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517                               enum pipe pipe, u32 val)
1518 {
1519         if ((val & LVDS_PORT_EN) == 0)
1520                 return false;
1521
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533                               enum pipe pipe, u32 val)
1534 {
1535         if ((val & ADPA_DAC_ENABLE) == 0)
1536                 return false;
1537         if (HAS_PCH_CPT(dev_priv->dev)) {
1538                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539                         return false;
1540         } else {
1541                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542                         return false;
1543         }
1544         return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548                                    enum pipe pipe, int reg, u32 port_sel)
1549 {
1550         u32 val = I915_READ(reg);
1551         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553              reg, pipe_name(pipe));
1554
1555         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556              && (val & DP_PIPEB_SELECT),
1557              "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561                                      enum pipe pipe, int reg)
1562 {
1563         u32 val = I915_READ(reg);
1564         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566              reg, pipe_name(pipe));
1567
1568         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569              && (val & SDVO_PIPE_B_SELECT),
1570              "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574                                       enum pipe pipe)
1575 {
1576         u32 val;
1577
1578         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582         val = I915_READ(PCH_ADPA);
1583         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584              "PCH VGA enabled on transcoder %c, should be disabled\n",
1585              pipe_name(pipe));
1586
1587         val = I915_READ(PCH_LVDS);
1588         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590              pipe_name(pipe));
1591
1592         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598                            const struct intel_crtc_state *pipe_config)
1599 {
1600         struct drm_device *dev = crtc->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int reg = DPLL(crtc->pipe);
1603         u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605         assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607         /* No really, not for ILK+ */
1608         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610         /* PLL is protected by panel, make sure we can write it */
1611         if (IS_MOBILE(dev_priv->dev))
1612                 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614         I915_WRITE(reg, dpll);
1615         POSTING_READ(reg);
1616         udelay(150);
1617
1618         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622         POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624         /* We do this three times for luck */
1625         I915_WRITE(reg, dpll);
1626         POSTING_READ(reg);
1627         udelay(150); /* wait for warmup */
1628         I915_WRITE(reg, dpll);
1629         POSTING_READ(reg);
1630         udelay(150); /* wait for warmup */
1631         I915_WRITE(reg, dpll);
1632         POSTING_READ(reg);
1633         udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637                            const struct intel_crtc_state *pipe_config)
1638 {
1639         struct drm_device *dev = crtc->base.dev;
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         int pipe = crtc->pipe;
1642         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643         u32 tmp;
1644
1645         assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649         mutex_lock(&dev_priv->sb_lock);
1650
1651         /* Enable back the 10bit clock to display controller */
1652         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653         tmp |= DPIO_DCLKP_EN;
1654         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656         mutex_unlock(&dev_priv->sb_lock);
1657
1658         /*
1659          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660          */
1661         udelay(1);
1662
1663         /* Enable PLL */
1664         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666         /* Check PLL is locked */
1667         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670         /* not sure when this should be written */
1671         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672         POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677         struct intel_crtc *crtc;
1678         int count = 0;
1679
1680         for_each_intel_crtc(dev, crtc)
1681                 count += crtc->base.state->active &&
1682                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684         return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689         struct drm_device *dev = crtc->base.dev;
1690         struct drm_i915_private *dev_priv = dev->dev_private;
1691         int reg = DPLL(crtc->pipe);
1692         u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694         assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696         /* No really, not for ILK+ */
1697         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699         /* PLL is protected by panel, make sure we can write it */
1700         if (IS_MOBILE(dev) && !IS_I830(dev))
1701                 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703         /* Enable DVO 2x clock on both PLLs if necessary */
1704         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705                 /*
1706                  * It appears to be important that we don't enable this
1707                  * for the current pipe before otherwise configuring the
1708                  * PLL. No idea how this should be handled if multiple
1709                  * DVO outputs are enabled simultaneosly.
1710                  */
1711                 dpll |= DPLL_DVO_2X_MODE;
1712                 I915_WRITE(DPLL(!crtc->pipe),
1713                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714         }
1715
1716         /*
1717          * Apparently we need to have VGA mode enabled prior to changing
1718          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719          * dividers, even though the register value does change.
1720          */
1721         I915_WRITE(reg, 0);
1722
1723         I915_WRITE(reg, dpll);
1724
1725         /* Wait for the clocks to stabilize. */
1726         POSTING_READ(reg);
1727         udelay(150);
1728
1729         if (INTEL_INFO(dev)->gen >= 4) {
1730                 I915_WRITE(DPLL_MD(crtc->pipe),
1731                            crtc->config->dpll_hw_state.dpll_md);
1732         } else {
1733                 /* The pixel multiplier can only be updated once the
1734                  * DPLL is enabled and the clocks are stable.
1735                  *
1736                  * So write it again.
1737                  */
1738                 I915_WRITE(reg, dpll);
1739         }
1740
1741         /* We do this three times for luck */
1742         I915_WRITE(reg, dpll);
1743         POSTING_READ(reg);
1744         udelay(150); /* wait for warmup */
1745         I915_WRITE(reg, dpll);
1746         POSTING_READ(reg);
1747         udelay(150); /* wait for warmup */
1748         I915_WRITE(reg, dpll);
1749         POSTING_READ(reg);
1750         udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754  * i9xx_disable_pll - disable a PLL
1755  * @dev_priv: i915 private structure
1756  * @pipe: pipe PLL to disable
1757  *
1758  * Disable the PLL for @pipe, making sure the pipe is off first.
1759  *
1760  * Note!  This is for pre-ILK only.
1761  */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->base.dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         enum pipe pipe = crtc->pipe;
1767
1768         /* Disable DVO 2x clock on both PLLs if necessary */
1769         if (IS_I830(dev) &&
1770             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771             !intel_num_dvo_pipes(dev)) {
1772                 I915_WRITE(DPLL(PIPE_B),
1773                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774                 I915_WRITE(DPLL(PIPE_A),
1775                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776         }
1777
1778         /* Don't disable pipe or pipe PLLs if needed */
1779         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781                 return;
1782
1783         /* Make sure the pipe isn't still relying on us */
1784         assert_pipe_disabled(dev_priv, pipe);
1785
1786         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787         POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792         u32 val;
1793
1794         /* Make sure the pipe isn't still relying on us */
1795         assert_pipe_disabled(dev_priv, pipe);
1796
1797         /*
1798          * Leave integrated clock source and reference clock enabled for pipe B.
1799          * The latter is needed for VGA hotplug / manual detection.
1800          */
1801         val = DPLL_VGA_MODE_DIS;
1802         if (pipe == PIPE_B)
1803                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804         I915_WRITE(DPLL(pipe), val);
1805         POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812         u32 val;
1813
1814         /* Make sure the pipe isn't still relying on us */
1815         assert_pipe_disabled(dev_priv, pipe);
1816
1817         /* Set PLL en = 0 */
1818         val = DPLL_SSC_REF_CLK_CHV |
1819                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820         if (pipe != PIPE_A)
1821                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822         I915_WRITE(DPLL(pipe), val);
1823         POSTING_READ(DPLL(pipe));
1824
1825         mutex_lock(&dev_priv->sb_lock);
1826
1827         /* Disable 10bit clock to display controller */
1828         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829         val &= ~DPIO_DCLKP_EN;
1830         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832         mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836                          struct intel_digital_port *dport,
1837                          unsigned int expected_mask)
1838 {
1839         u32 port_mask;
1840         int dpll_reg;
1841
1842         switch (dport->port) {
1843         case PORT_B:
1844                 port_mask = DPLL_PORTB_READY_MASK;
1845                 dpll_reg = DPLL(0);
1846                 break;
1847         case PORT_C:
1848                 port_mask = DPLL_PORTC_READY_MASK;
1849                 dpll_reg = DPLL(0);
1850                 expected_mask <<= 4;
1851                 break;
1852         case PORT_D:
1853                 port_mask = DPLL_PORTD_READY_MASK;
1854                 dpll_reg = DPIO_PHY_STATUS;
1855                 break;
1856         default:
1857                 BUG();
1858         }
1859
1860         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867         struct drm_device *dev = crtc->base.dev;
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871         if (WARN_ON(pll == NULL))
1872                 return;
1873
1874         WARN_ON(!pll->config.crtc_mask);
1875         if (pll->active == 0) {
1876                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877                 WARN_ON(pll->on);
1878                 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880                 pll->mode_set(dev_priv, pll);
1881         }
1882 }
1883
1884 /**
1885  * intel_enable_shared_dpll - enable PCH PLL
1886  * @dev_priv: i915 private structure
1887  * @pipe: pipe PLL to enable
1888  *
1889  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890  * drives the transcoder clock.
1891  */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894         struct drm_device *dev = crtc->base.dev;
1895         struct drm_i915_private *dev_priv = dev->dev_private;
1896         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898         if (WARN_ON(pll == NULL))
1899                 return;
1900
1901         if (WARN_ON(pll->config.crtc_mask == 0))
1902                 return;
1903
1904         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905                       pll->name, pll->active, pll->on,
1906                       crtc->base.base.id);
1907
1908         if (pll->active++) {
1909                 WARN_ON(!pll->on);
1910                 assert_shared_dpll_enabled(dev_priv, pll);
1911                 return;
1912         }
1913         WARN_ON(pll->on);
1914
1915         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918         pll->enable(dev_priv, pll);
1919         pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924         struct drm_device *dev = crtc->base.dev;
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928         /* PCH only available on ILK+ */
1929         if (INTEL_INFO(dev)->gen < 5)
1930                 return;
1931
1932         if (pll == NULL)
1933                 return;
1934
1935         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936                 return;
1937
1938         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939                       pll->name, pll->active, pll->on,
1940                       crtc->base.base.id);
1941
1942         if (WARN_ON(pll->active == 0)) {
1943                 assert_shared_dpll_disabled(dev_priv, pll);
1944                 return;
1945         }
1946
1947         assert_shared_dpll_enabled(dev_priv, pll);
1948         WARN_ON(!pll->on);
1949         if (--pll->active)
1950                 return;
1951
1952         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953         pll->disable(dev_priv, pll);
1954         pll->on = false;
1955
1956         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960                                            enum pipe pipe)
1961 {
1962         struct drm_device *dev = dev_priv->dev;
1963         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965         uint32_t reg, val, pipeconf_val;
1966
1967         /* PCH only available on ILK+ */
1968         BUG_ON(!HAS_PCH_SPLIT(dev));
1969
1970         /* Make sure PCH DPLL is enabled */
1971         assert_shared_dpll_enabled(dev_priv,
1972                                    intel_crtc_to_shared_dpll(intel_crtc));
1973
1974         /* FDI must be feeding us bits for PCH ports */
1975         assert_fdi_tx_enabled(dev_priv, pipe);
1976         assert_fdi_rx_enabled(dev_priv, pipe);
1977
1978         if (HAS_PCH_CPT(dev)) {
1979                 /* Workaround: Set the timing override bit before enabling the
1980                  * pch transcoder. */
1981                 reg = TRANS_CHICKEN2(pipe);
1982                 val = I915_READ(reg);
1983                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984                 I915_WRITE(reg, val);
1985         }
1986
1987         reg = PCH_TRANSCONF(pipe);
1988         val = I915_READ(reg);
1989         pipeconf_val = I915_READ(PIPECONF(pipe));
1990
1991         if (HAS_PCH_IBX(dev_priv->dev)) {
1992                 /*
1993                  * Make the BPC in transcoder be consistent with
1994                  * that in pipeconf reg. For HDMI we must use 8bpc
1995                  * here for both 8bpc and 12bpc.
1996                  */
1997                 val &= ~PIPECONF_BPC_MASK;
1998                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999                         val |= PIPECONF_8BPC;
2000                 else
2001                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2002         }
2003
2004         val &= ~TRANS_INTERLACE_MASK;
2005         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006                 if (HAS_PCH_IBX(dev_priv->dev) &&
2007                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008                         val |= TRANS_LEGACY_INTERLACED_ILK;
2009                 else
2010                         val |= TRANS_INTERLACED;
2011         else
2012                 val |= TRANS_PROGRESSIVE;
2013
2014         I915_WRITE(reg, val | TRANS_ENABLE);
2015         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2017 }
2018
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020                                       enum transcoder cpu_transcoder)
2021 {
2022         u32 val, pipeconf_val;
2023
2024         /* PCH only available on ILK+ */
2025         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2026
2027         /* FDI must be feeding us bits for PCH ports */
2028         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
2031         /* Workaround: set timing override bit. */
2032         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2035
2036         val = TRANS_ENABLE;
2037         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2038
2039         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040             PIPECONF_INTERLACED_ILK)
2041                 val |= TRANS_INTERLACED;
2042         else
2043                 val |= TRANS_PROGRESSIVE;
2044
2045         I915_WRITE(LPT_TRANSCONF, val);
2046         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047                 DRM_ERROR("Failed to enable PCH transcoder\n");
2048 }
2049
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051                                             enum pipe pipe)
2052 {
2053         struct drm_device *dev = dev_priv->dev;
2054         uint32_t reg, val;
2055
2056         /* FDI relies on the transcoder */
2057         assert_fdi_tx_disabled(dev_priv, pipe);
2058         assert_fdi_rx_disabled(dev_priv, pipe);
2059
2060         /* Ports must be off as well */
2061         assert_pch_ports_disabled(dev_priv, pipe);
2062
2063         reg = PCH_TRANSCONF(pipe);
2064         val = I915_READ(reg);
2065         val &= ~TRANS_ENABLE;
2066         I915_WRITE(reg, val);
2067         /* wait for PCH transcoder off, transcoder state */
2068         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2069                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2070
2071         if (!HAS_PCH_IBX(dev)) {
2072                 /* Workaround: Clear the timing override chicken bit again. */
2073                 reg = TRANS_CHICKEN2(pipe);
2074                 val = I915_READ(reg);
2075                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2076                 I915_WRITE(reg, val);
2077         }
2078 }
2079
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2081 {
2082         u32 val;
2083
2084         val = I915_READ(LPT_TRANSCONF);
2085         val &= ~TRANS_ENABLE;
2086         I915_WRITE(LPT_TRANSCONF, val);
2087         /* wait for PCH transcoder off, transcoder state */
2088         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089                 DRM_ERROR("Failed to disable PCH transcoder\n");
2090
2091         /* Workaround: clear timing override bit. */
2092         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2093         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2095 }
2096
2097 /**
2098  * intel_enable_pipe - enable a pipe, asserting requirements
2099  * @crtc: crtc responsible for the pipe
2100  *
2101  * Enable @crtc's pipe, making sure that various hardware specific requirements
2102  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2103  */
2104 static void intel_enable_pipe(struct intel_crtc *crtc)
2105 {
2106         struct drm_device *dev = crtc->base.dev;
2107         struct drm_i915_private *dev_priv = dev->dev_private;
2108         enum pipe pipe = crtc->pipe;
2109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2110                                                                       pipe);
2111         enum pipe pch_transcoder;
2112         int reg;
2113         u32 val;
2114
2115         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
2117         assert_planes_disabled(dev_priv, pipe);
2118         assert_cursor_disabled(dev_priv, pipe);
2119         assert_sprites_disabled(dev_priv, pipe);
2120
2121         if (HAS_PCH_LPT(dev_priv->dev))
2122                 pch_transcoder = TRANSCODER_A;
2123         else
2124                 pch_transcoder = pipe;
2125
2126         /*
2127          * A pipe without a PLL won't actually be able to drive bits from
2128          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2129          * need the check.
2130          */
2131         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2133                         assert_dsi_pll_enabled(dev_priv);
2134                 else
2135                         assert_pll_enabled(dev_priv, pipe);
2136         else {
2137                 if (crtc->config->has_pch_encoder) {
2138                         /* if driving the PCH, we need FDI enabled */
2139                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140                         assert_fdi_tx_pll_enabled(dev_priv,
2141                                                   (enum pipe) cpu_transcoder);
2142                 }
2143                 /* FIXME: assert CPU port conditions for SNB+ */
2144         }
2145
2146         reg = PIPECONF(cpu_transcoder);
2147         val = I915_READ(reg);
2148         if (val & PIPECONF_ENABLE) {
2149                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2151                 return;
2152         }
2153
2154         I915_WRITE(reg, val | PIPECONF_ENABLE);
2155         POSTING_READ(reg);
2156 }
2157
2158 /**
2159  * intel_disable_pipe - disable a pipe, asserting requirements
2160  * @crtc: crtc whose pipes is to be disabled
2161  *
2162  * Disable the pipe of @crtc, making sure that various hardware
2163  * specific requirements are met, if applicable, e.g. plane
2164  * disabled, panel fitter off, etc.
2165  *
2166  * Will wait until the pipe has shut down before returning.
2167  */
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2169 {
2170         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172         enum pipe pipe = crtc->pipe;
2173         int reg;
2174         u32 val;
2175
2176         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
2178         /*
2179          * Make sure planes won't keep trying to pump pixels to us,
2180          * or we might hang the display.
2181          */
2182         assert_planes_disabled(dev_priv, pipe);
2183         assert_cursor_disabled(dev_priv, pipe);
2184         assert_sprites_disabled(dev_priv, pipe);
2185
2186         reg = PIPECONF(cpu_transcoder);
2187         val = I915_READ(reg);
2188         if ((val & PIPECONF_ENABLE) == 0)
2189                 return;
2190
2191         /*
2192          * Double wide has implications for planes
2193          * so best keep it disabled when not needed.
2194          */
2195         if (crtc->config->double_wide)
2196                 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198         /* Don't disable pipe or pipe PLLs if needed */
2199         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201                 val &= ~PIPECONF_ENABLE;
2202
2203         I915_WRITE(reg, val);
2204         if ((val & PIPECONF_ENABLE) == 0)
2205                 intel_wait_for_pipe_off(crtc);
2206 }
2207
2208 static bool need_vtd_wa(struct drm_device *dev)
2209 {
2210 #ifdef CONFIG_INTEL_IOMMU
2211         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212                 return true;
2213 #endif
2214         return false;
2215 }
2216
2217 unsigned int
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219                   uint64_t fb_format_modifier, unsigned int plane)
2220 {
2221         unsigned int tile_height;
2222         uint32_t pixel_bytes;
2223
2224         switch (fb_format_modifier) {
2225         case DRM_FORMAT_MOD_NONE:
2226                 tile_height = 1;
2227                 break;
2228         case I915_FORMAT_MOD_X_TILED:
2229                 tile_height = IS_GEN2(dev) ? 16 : 8;
2230                 break;
2231         case I915_FORMAT_MOD_Y_TILED:
2232                 tile_height = 32;
2233                 break;
2234         case I915_FORMAT_MOD_Yf_TILED:
2235                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236                 switch (pixel_bytes) {
2237                 default:
2238                 case 1:
2239                         tile_height = 64;
2240                         break;
2241                 case 2:
2242                 case 4:
2243                         tile_height = 32;
2244                         break;
2245                 case 8:
2246                         tile_height = 16;
2247                         break;
2248                 case 16:
2249                         WARN_ONCE(1,
2250                                   "128-bit pixels are not supported for display!");
2251                         tile_height = 16;
2252                         break;
2253                 }
2254                 break;
2255         default:
2256                 MISSING_CASE(fb_format_modifier);
2257                 tile_height = 1;
2258                 break;
2259         }
2260
2261         return tile_height;
2262 }
2263
2264 unsigned int
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266                       uint32_t pixel_format, uint64_t fb_format_modifier)
2267 {
2268         return ALIGN(height, intel_tile_height(dev, pixel_format,
2269                                                fb_format_modifier, 0));
2270 }
2271
2272 static int
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274                         const struct drm_plane_state *plane_state)
2275 {
2276         struct intel_rotation_info *info = &view->rotation_info;
2277         unsigned int tile_height, tile_pitch;
2278
2279         *view = i915_ggtt_view_normal;
2280
2281         if (!plane_state)
2282                 return 0;
2283
2284         if (!intel_rotation_90_or_270(plane_state->rotation))
2285                 return 0;
2286
2287         *view = i915_ggtt_view_rotated;
2288
2289         info->height = fb->height;
2290         info->pixel_format = fb->pixel_format;
2291         info->pitch = fb->pitches[0];
2292         info->uv_offset = fb->offsets[1];
2293         info->fb_modifier = fb->modifier[0];
2294
2295         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296                                         fb->modifier[0], 0);
2297         tile_pitch = PAGE_SIZE / tile_height;
2298         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
2302         if (info->pixel_format == DRM_FORMAT_NV12) {
2303                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304                                                 fb->modifier[0], 1);
2305                 tile_pitch = PAGE_SIZE / tile_height;
2306                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308                                                      tile_height);
2309                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310                                 PAGE_SIZE;
2311         }
2312
2313         return 0;
2314 }
2315
2316 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2317 {
2318         if (INTEL_INFO(dev_priv)->gen >= 9)
2319                 return 256 * 1024;
2320         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2321                  IS_VALLEYVIEW(dev_priv))
2322                 return 128 * 1024;
2323         else if (INTEL_INFO(dev_priv)->gen >= 4)
2324                 return 4 * 1024;
2325         else
2326                 return 0;
2327 }
2328
2329 int
2330 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331                            struct drm_framebuffer *fb,
2332                            const struct drm_plane_state *plane_state,
2333                            struct intel_engine_cs *pipelined,
2334                            struct drm_i915_gem_request **pipelined_request)
2335 {
2336         struct drm_device *dev = fb->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2339         struct i915_ggtt_view view;
2340         u32 alignment;
2341         int ret;
2342
2343         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2344
2345         switch (fb->modifier[0]) {
2346         case DRM_FORMAT_MOD_NONE:
2347                 alignment = intel_linear_alignment(dev_priv);
2348                 break;
2349         case I915_FORMAT_MOD_X_TILED:
2350                 if (INTEL_INFO(dev)->gen >= 9)
2351                         alignment = 256 * 1024;
2352                 else {
2353                         /* pin() will align the object as required by fence */
2354                         alignment = 0;
2355                 }
2356                 break;
2357         case I915_FORMAT_MOD_Y_TILED:
2358         case I915_FORMAT_MOD_Yf_TILED:
2359                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360                           "Y tiling bo slipped through, driver bug!\n"))
2361                         return -EINVAL;
2362                 alignment = 1 * 1024 * 1024;
2363                 break;
2364         default:
2365                 MISSING_CASE(fb->modifier[0]);
2366                 return -EINVAL;
2367         }
2368
2369         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370         if (ret)
2371                 return ret;
2372
2373         /* Note that the w/a also requires 64 PTE of padding following the
2374          * bo. We currently fill all unused PTE with the shadow page and so
2375          * we should always have valid PTE following the scanout preventing
2376          * the VT-d warning.
2377          */
2378         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379                 alignment = 256 * 1024;
2380
2381         /*
2382          * Global gtt pte registers are special registers which actually forward
2383          * writes to a chunk of system memory. Which means that there is no risk
2384          * that the register values disappear as soon as we call
2385          * intel_runtime_pm_put(), so it is correct to wrap only the
2386          * pin/unpin/fence and not more.
2387          */
2388         intel_runtime_pm_get(dev_priv);
2389
2390         dev_priv->mm.interruptible = false;
2391         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392                                                    pipelined_request, &view);
2393         if (ret)
2394                 goto err_interruptible;
2395
2396         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397          * fence, whereas 965+ only requires a fence if using
2398          * framebuffer compression.  For simplicity, we always install
2399          * a fence as the cost is not that onerous.
2400          */
2401         ret = i915_gem_object_get_fence(obj);
2402         if (ret == -EDEADLK) {
2403                 /*
2404                  * -EDEADLK means there are no free fences
2405                  * no pending flips.
2406                  *
2407                  * This is propagated to atomic, but it uses
2408                  * -EDEADLK to force a locking recovery, so
2409                  * change the returned error to -EBUSY.
2410                  */
2411                 ret = -EBUSY;
2412                 goto err_unpin;
2413         } else if (ret)
2414                 goto err_unpin;
2415
2416         i915_gem_object_pin_fence(obj);
2417
2418         dev_priv->mm.interruptible = true;
2419         intel_runtime_pm_put(dev_priv);
2420         return 0;
2421
2422 err_unpin:
2423         i915_gem_object_unpin_from_display_plane(obj, &view);
2424 err_interruptible:
2425         dev_priv->mm.interruptible = true;
2426         intel_runtime_pm_put(dev_priv);
2427         return ret;
2428 }
2429
2430 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2431                                const struct drm_plane_state *plane_state)
2432 {
2433         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2434         struct i915_ggtt_view view;
2435         int ret;
2436
2437         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2438
2439         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2440         WARN_ONCE(ret, "Couldn't get view from plane state!");
2441
2442         i915_gem_object_unpin_fence(obj);
2443         i915_gem_object_unpin_from_display_plane(obj, &view);
2444 }
2445
2446 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2447  * is assumed to be a power-of-two. */
2448 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2449                                              int *x, int *y,
2450                                              unsigned int tiling_mode,
2451                                              unsigned int cpp,
2452                                              unsigned int pitch)
2453 {
2454         if (tiling_mode != I915_TILING_NONE) {
2455                 unsigned int tile_rows, tiles;
2456
2457                 tile_rows = *y / 8;
2458                 *y %= 8;
2459
2460                 tiles = *x / (512/cpp);
2461                 *x %= 512/cpp;
2462
2463                 return tile_rows * pitch * 8 + tiles * 4096;
2464         } else {
2465                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2466                 unsigned int offset;
2467
2468                 offset = *y * pitch + *x * cpp;
2469                 *y = (offset & alignment) / pitch;
2470                 *x = ((offset & alignment) - *y * pitch) / cpp;
2471                 return offset & ~alignment;
2472         }
2473 }
2474
2475 static int i9xx_format_to_fourcc(int format)
2476 {
2477         switch (format) {
2478         case DISPPLANE_8BPP:
2479                 return DRM_FORMAT_C8;
2480         case DISPPLANE_BGRX555:
2481                 return DRM_FORMAT_XRGB1555;
2482         case DISPPLANE_BGRX565:
2483                 return DRM_FORMAT_RGB565;
2484         default:
2485         case DISPPLANE_BGRX888:
2486                 return DRM_FORMAT_XRGB8888;
2487         case DISPPLANE_RGBX888:
2488                 return DRM_FORMAT_XBGR8888;
2489         case DISPPLANE_BGRX101010:
2490                 return DRM_FORMAT_XRGB2101010;
2491         case DISPPLANE_RGBX101010:
2492                 return DRM_FORMAT_XBGR2101010;
2493         }
2494 }
2495
2496 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2497 {
2498         switch (format) {
2499         case PLANE_CTL_FORMAT_RGB_565:
2500                 return DRM_FORMAT_RGB565;
2501         default:
2502         case PLANE_CTL_FORMAT_XRGB_8888:
2503                 if (rgb_order) {
2504                         if (alpha)
2505                                 return DRM_FORMAT_ABGR8888;
2506                         else
2507                                 return DRM_FORMAT_XBGR8888;
2508                 } else {
2509                         if (alpha)
2510                                 return DRM_FORMAT_ARGB8888;
2511                         else
2512                                 return DRM_FORMAT_XRGB8888;
2513                 }
2514         case PLANE_CTL_FORMAT_XRGB_2101010:
2515                 if (rgb_order)
2516                         return DRM_FORMAT_XBGR2101010;
2517                 else
2518                         return DRM_FORMAT_XRGB2101010;
2519         }
2520 }
2521
2522 static bool
2523 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2524                               struct intel_initial_plane_config *plane_config)
2525 {
2526         struct drm_device *dev = crtc->base.dev;
2527         struct drm_i915_private *dev_priv = to_i915(dev);
2528         struct drm_i915_gem_object *obj = NULL;
2529         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2530         struct drm_framebuffer *fb = &plane_config->fb->base;
2531         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533                                     PAGE_SIZE);
2534
2535         size_aligned -= base_aligned;
2536
2537         if (plane_config->size == 0)
2538                 return false;
2539
2540         /* If the FB is too big, just don't use it since fbdev is not very
2541          * important and we should probably use that space with FBC or other
2542          * features. */
2543         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2544                 return false;
2545
2546         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2547                                                              base_aligned,
2548                                                              base_aligned,
2549                                                              size_aligned);
2550         if (!obj)
2551                 return false;
2552
2553         obj->tiling_mode = plane_config->tiling;
2554         if (obj->tiling_mode == I915_TILING_X)
2555                 obj->stride = fb->pitches[0];
2556
2557         mode_cmd.pixel_format = fb->pixel_format;
2558         mode_cmd.width = fb->width;
2559         mode_cmd.height = fb->height;
2560         mode_cmd.pitches[0] = fb->pitches[0];
2561         mode_cmd.modifier[0] = fb->modifier[0];
2562         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2563
2564         mutex_lock(&dev->struct_mutex);
2565         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2566                                    &mode_cmd, obj)) {
2567                 DRM_DEBUG_KMS("intel fb init failed\n");
2568                 goto out_unref_obj;
2569         }
2570         mutex_unlock(&dev->struct_mutex);
2571
2572         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2573         return true;
2574
2575 out_unref_obj:
2576         drm_gem_object_unreference(&obj->base);
2577         mutex_unlock(&dev->struct_mutex);
2578         return false;
2579 }
2580
2581 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2582 static void
2583 update_state_fb(struct drm_plane *plane)
2584 {
2585         if (plane->fb == plane->state->fb)
2586                 return;
2587
2588         if (plane->state->fb)
2589                 drm_framebuffer_unreference(plane->state->fb);
2590         plane->state->fb = plane->fb;
2591         if (plane->state->fb)
2592                 drm_framebuffer_reference(plane->state->fb);
2593 }
2594
2595 static void
2596 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2597                              struct intel_initial_plane_config *plane_config)
2598 {
2599         struct drm_device *dev = intel_crtc->base.dev;
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct drm_crtc *c;
2602         struct intel_crtc *i;
2603         struct drm_i915_gem_object *obj;
2604         struct drm_plane *primary = intel_crtc->base.primary;
2605         struct drm_plane_state *plane_state = primary->state;
2606         struct drm_framebuffer *fb;
2607
2608         if (!plane_config->fb)
2609                 return;
2610
2611         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2612                 fb = &plane_config->fb->base;
2613                 goto valid_fb;
2614         }
2615
2616         kfree(plane_config->fb);
2617
2618         /*
2619          * Failed to alloc the obj, check to see if we should share
2620          * an fb with another CRTC instead
2621          */
2622         for_each_crtc(dev, c) {
2623                 i = to_intel_crtc(c);
2624
2625                 if (c == &intel_crtc->base)
2626                         continue;
2627
2628                 if (!i->active)
2629                         continue;
2630
2631                 fb = c->primary->fb;
2632                 if (!fb)
2633                         continue;
2634
2635                 obj = intel_fb_obj(fb);
2636                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2637                         drm_framebuffer_reference(fb);
2638                         goto valid_fb;
2639                 }
2640         }
2641
2642         return;
2643
2644 valid_fb:
2645         plane_state->src_x = plane_state->src_y = 0;
2646         plane_state->src_w = fb->width << 16;
2647         plane_state->src_h = fb->height << 16;
2648
2649         plane_state->crtc_x = plane_state->src_y = 0;
2650         plane_state->crtc_w = fb->width;
2651         plane_state->crtc_h = fb->height;
2652
2653         obj = intel_fb_obj(fb);
2654         if (obj->tiling_mode != I915_TILING_NONE)
2655                 dev_priv->preserve_bios_swizzle = true;
2656
2657         drm_framebuffer_reference(fb);
2658         primary->fb = primary->state->fb = fb;
2659         primary->crtc = primary->state->crtc = &intel_crtc->base;
2660         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2661         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2662 }
2663
2664 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2665                                       struct drm_framebuffer *fb,
2666                                       int x, int y)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         struct drm_plane *primary = crtc->primary;
2672         bool visible = to_intel_plane_state(primary->state)->visible;
2673         struct drm_i915_gem_object *obj;
2674         int plane = intel_crtc->plane;
2675         unsigned long linear_offset;
2676         u32 dspcntr;
2677         u32 reg = DSPCNTR(plane);
2678         int pixel_size;
2679
2680         if (!visible || !fb) {
2681                 I915_WRITE(reg, 0);
2682                 if (INTEL_INFO(dev)->gen >= 4)
2683                         I915_WRITE(DSPSURF(plane), 0);
2684                 else
2685                         I915_WRITE(DSPADDR(plane), 0);
2686                 POSTING_READ(reg);
2687                 return;
2688         }
2689
2690         obj = intel_fb_obj(fb);
2691         if (WARN_ON(obj == NULL))
2692                 return;
2693
2694         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2695
2696         dspcntr = DISPPLANE_GAMMA_ENABLE;
2697
2698         dspcntr |= DISPLAY_PLANE_ENABLE;
2699
2700         if (INTEL_INFO(dev)->gen < 4) {
2701                 if (intel_crtc->pipe == PIPE_B)
2702                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2703
2704                 /* pipesrc and dspsize control the size that is scaled from,
2705                  * which should always be the user's requested size.
2706                  */
2707                 I915_WRITE(DSPSIZE(plane),
2708                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2709                            (intel_crtc->config->pipe_src_w - 1));
2710                 I915_WRITE(DSPPOS(plane), 0);
2711         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2712                 I915_WRITE(PRIMSIZE(plane),
2713                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2714                            (intel_crtc->config->pipe_src_w - 1));
2715                 I915_WRITE(PRIMPOS(plane), 0);
2716                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2717         }
2718
2719         switch (fb->pixel_format) {
2720         case DRM_FORMAT_C8:
2721                 dspcntr |= DISPPLANE_8BPP;
2722                 break;
2723         case DRM_FORMAT_XRGB1555:
2724                 dspcntr |= DISPPLANE_BGRX555;
2725                 break;
2726         case DRM_FORMAT_RGB565:
2727                 dspcntr |= DISPPLANE_BGRX565;
2728                 break;
2729         case DRM_FORMAT_XRGB8888:
2730                 dspcntr |= DISPPLANE_BGRX888;
2731                 break;
2732         case DRM_FORMAT_XBGR8888:
2733                 dspcntr |= DISPPLANE_RGBX888;
2734                 break;
2735         case DRM_FORMAT_XRGB2101010:
2736                 dspcntr |= DISPPLANE_BGRX101010;
2737                 break;
2738         case DRM_FORMAT_XBGR2101010:
2739                 dspcntr |= DISPPLANE_RGBX101010;
2740                 break;
2741         default:
2742                 BUG();
2743         }
2744
2745         if (INTEL_INFO(dev)->gen >= 4 &&
2746             obj->tiling_mode != I915_TILING_NONE)
2747                 dspcntr |= DISPPLANE_TILED;
2748
2749         if (IS_G4X(dev))
2750                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2751
2752         linear_offset = y * fb->pitches[0] + x * pixel_size;
2753
2754         if (INTEL_INFO(dev)->gen >= 4) {
2755                 intel_crtc->dspaddr_offset =
2756                         intel_gen4_compute_page_offset(dev_priv,
2757                                                        &x, &y, obj->tiling_mode,
2758                                                        pixel_size,
2759                                                        fb->pitches[0]);
2760                 linear_offset -= intel_crtc->dspaddr_offset;
2761         } else {
2762                 intel_crtc->dspaddr_offset = linear_offset;
2763         }
2764
2765         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2766                 dspcntr |= DISPPLANE_ROTATE_180;
2767
2768                 x += (intel_crtc->config->pipe_src_w - 1);
2769                 y += (intel_crtc->config->pipe_src_h - 1);
2770
2771                 /* Finding the last pixel of the last line of the display
2772                 data and adding to linear_offset*/
2773                 linear_offset +=
2774                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2775                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2776         }
2777
2778         intel_crtc->adjusted_x = x;
2779         intel_crtc->adjusted_y = y;
2780
2781         I915_WRITE(reg, dspcntr);
2782
2783         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2784         if (INTEL_INFO(dev)->gen >= 4) {
2785                 I915_WRITE(DSPSURF(plane),
2786                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2787                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2788                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2789         } else
2790                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2791         POSTING_READ(reg);
2792 }
2793
2794 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2795                                           struct drm_framebuffer *fb,
2796                                           int x, int y)
2797 {
2798         struct drm_device *dev = crtc->dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801         struct drm_plane *primary = crtc->primary;
2802         bool visible = to_intel_plane_state(primary->state)->visible;
2803         struct drm_i915_gem_object *obj;
2804         int plane = intel_crtc->plane;
2805         unsigned long linear_offset;
2806         u32 dspcntr;
2807         u32 reg = DSPCNTR(plane);
2808         int pixel_size;
2809
2810         if (!visible || !fb) {
2811                 I915_WRITE(reg, 0);
2812                 I915_WRITE(DSPSURF(plane), 0);
2813                 POSTING_READ(reg);
2814                 return;
2815         }
2816
2817         obj = intel_fb_obj(fb);
2818         if (WARN_ON(obj == NULL))
2819                 return;
2820
2821         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2822
2823         dspcntr = DISPPLANE_GAMMA_ENABLE;
2824
2825         dspcntr |= DISPLAY_PLANE_ENABLE;
2826
2827         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2828                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2829
2830         switch (fb->pixel_format) {
2831         case DRM_FORMAT_C8:
2832                 dspcntr |= DISPPLANE_8BPP;
2833                 break;
2834         case DRM_FORMAT_RGB565:
2835                 dspcntr |= DISPPLANE_BGRX565;
2836                 break;
2837         case DRM_FORMAT_XRGB8888:
2838                 dspcntr |= DISPPLANE_BGRX888;
2839                 break;
2840         case DRM_FORMAT_XBGR8888:
2841                 dspcntr |= DISPPLANE_RGBX888;
2842                 break;
2843         case DRM_FORMAT_XRGB2101010:
2844                 dspcntr |= DISPPLANE_BGRX101010;
2845                 break;
2846         case DRM_FORMAT_XBGR2101010:
2847                 dspcntr |= DISPPLANE_RGBX101010;
2848                 break;
2849         default:
2850                 BUG();
2851         }
2852
2853         if (obj->tiling_mode != I915_TILING_NONE)
2854                 dspcntr |= DISPPLANE_TILED;
2855
2856         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2857                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2858
2859         linear_offset = y * fb->pitches[0] + x * pixel_size;
2860         intel_crtc->dspaddr_offset =
2861                 intel_gen4_compute_page_offset(dev_priv,
2862                                                &x, &y, obj->tiling_mode,
2863                                                pixel_size,
2864                                                fb->pitches[0]);
2865         linear_offset -= intel_crtc->dspaddr_offset;
2866         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2867                 dspcntr |= DISPPLANE_ROTATE_180;
2868
2869                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2870                         x += (intel_crtc->config->pipe_src_w - 1);
2871                         y += (intel_crtc->config->pipe_src_h - 1);
2872
2873                         /* Finding the last pixel of the last line of the display
2874                         data and adding to linear_offset*/
2875                         linear_offset +=
2876                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2877                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2878                 }
2879         }
2880
2881         intel_crtc->adjusted_x = x;
2882         intel_crtc->adjusted_y = y;
2883
2884         I915_WRITE(reg, dspcntr);
2885
2886         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2887         I915_WRITE(DSPSURF(plane),
2888                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2889         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2890                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2891         } else {
2892                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2893                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2894         }
2895         POSTING_READ(reg);
2896 }
2897
2898 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2899                               uint32_t pixel_format)
2900 {
2901         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2902
2903         /*
2904          * The stride is either expressed as a multiple of 64 bytes
2905          * chunks for linear buffers or in number of tiles for tiled
2906          * buffers.
2907          */
2908         switch (fb_modifier) {
2909         case DRM_FORMAT_MOD_NONE:
2910                 return 64;
2911         case I915_FORMAT_MOD_X_TILED:
2912                 if (INTEL_INFO(dev)->gen == 2)
2913                         return 128;
2914                 return 512;
2915         case I915_FORMAT_MOD_Y_TILED:
2916                 /* No need to check for old gens and Y tiling since this is
2917                  * about the display engine and those will be blocked before
2918                  * we get here.
2919                  */
2920                 return 128;
2921         case I915_FORMAT_MOD_Yf_TILED:
2922                 if (bits_per_pixel == 8)
2923                         return 64;
2924                 else
2925                         return 128;
2926         default:
2927                 MISSING_CASE(fb_modifier);
2928                 return 64;
2929         }
2930 }
2931
2932 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2933                                      struct drm_i915_gem_object *obj,
2934                                      unsigned int plane)
2935 {
2936         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2937         struct i915_vma *vma;
2938         unsigned char *offset;
2939
2940         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2941                 view = &i915_ggtt_view_rotated;
2942
2943         vma = i915_gem_obj_to_ggtt_view(obj, view);
2944         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2945                 view->type))
2946                 return -1;
2947
2948         offset = (unsigned char *)vma->node.start;
2949
2950         if (plane == 1) {
2951                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2952                           PAGE_SIZE;
2953         }
2954
2955         return (unsigned long)offset;
2956 }
2957
2958 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2959 {
2960         struct drm_device *dev = intel_crtc->base.dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962
2963         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2964         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2965         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2966 }
2967
2968 /*
2969  * This function detaches (aka. unbinds) unused scalers in hardware
2970  */
2971 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2972 {
2973         struct intel_crtc_scaler_state *scaler_state;
2974         int i;
2975
2976         scaler_state = &intel_crtc->config->scaler_state;
2977
2978         /* loop through and disable scalers that aren't in use */
2979         for (i = 0; i < intel_crtc->num_scalers; i++) {
2980                 if (!scaler_state->scalers[i].in_use)
2981                         skl_detach_scaler(intel_crtc, i);
2982         }
2983 }
2984
2985 u32 skl_plane_ctl_format(uint32_t pixel_format)
2986 {
2987         switch (pixel_format) {
2988         case DRM_FORMAT_C8:
2989                 return PLANE_CTL_FORMAT_INDEXED;
2990         case DRM_FORMAT_RGB565:
2991                 return PLANE_CTL_FORMAT_RGB_565;
2992         case DRM_FORMAT_XBGR8888:
2993                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2994         case DRM_FORMAT_XRGB8888:
2995                 return PLANE_CTL_FORMAT_XRGB_8888;
2996         /*
2997          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2998          * to be already pre-multiplied. We need to add a knob (or a different
2999          * DRM_FORMAT) for user-space to configure that.
3000          */
3001         case DRM_FORMAT_ABGR8888:
3002                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3003                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3004         case DRM_FORMAT_ARGB8888:
3005                 return PLANE_CTL_FORMAT_XRGB_8888 |
3006                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3007         case DRM_FORMAT_XRGB2101010:
3008                 return PLANE_CTL_FORMAT_XRGB_2101010;
3009         case DRM_FORMAT_XBGR2101010:
3010                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3011         case DRM_FORMAT_YUYV:
3012                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3013         case DRM_FORMAT_YVYU:
3014                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3015         case DRM_FORMAT_UYVY:
3016                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3017         case DRM_FORMAT_VYUY:
3018                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3019         default:
3020                 MISSING_CASE(pixel_format);
3021         }
3022
3023         return 0;
3024 }
3025
3026 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3027 {
3028         switch (fb_modifier) {
3029         case DRM_FORMAT_MOD_NONE:
3030                 break;
3031         case I915_FORMAT_MOD_X_TILED:
3032                 return PLANE_CTL_TILED_X;
3033         case I915_FORMAT_MOD_Y_TILED:
3034                 return PLANE_CTL_TILED_Y;
3035         case I915_FORMAT_MOD_Yf_TILED:
3036                 return PLANE_CTL_TILED_YF;
3037         default:
3038                 MISSING_CASE(fb_modifier);
3039         }
3040
3041         return 0;
3042 }
3043
3044 u32 skl_plane_ctl_rotation(unsigned int rotation)
3045 {
3046         switch (rotation) {
3047         case BIT(DRM_ROTATE_0):
3048                 break;
3049         /*
3050          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3051          * while i915 HW rotation is clockwise, thats why this swapping.
3052          */
3053         case BIT(DRM_ROTATE_90):
3054                 return PLANE_CTL_ROTATE_270;
3055         case BIT(DRM_ROTATE_180):
3056                 return PLANE_CTL_ROTATE_180;
3057         case BIT(DRM_ROTATE_270):
3058                 return PLANE_CTL_ROTATE_90;
3059         default:
3060                 MISSING_CASE(rotation);
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3067                                          struct drm_framebuffer *fb,
3068                                          int x, int y)
3069 {
3070         struct drm_device *dev = crtc->dev;
3071         struct drm_i915_private *dev_priv = dev->dev_private;
3072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073         struct drm_plane *plane = crtc->primary;
3074         bool visible = to_intel_plane_state(plane->state)->visible;
3075         struct drm_i915_gem_object *obj;
3076         int pipe = intel_crtc->pipe;
3077         u32 plane_ctl, stride_div, stride;
3078         u32 tile_height, plane_offset, plane_size;
3079         unsigned int rotation;
3080         int x_offset, y_offset;
3081         unsigned long surf_addr;
3082         struct intel_crtc_state *crtc_state = intel_crtc->config;
3083         struct intel_plane_state *plane_state;
3084         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3085         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3086         int scaler_id = -1;
3087
3088         plane_state = to_intel_plane_state(plane->state);
3089
3090         if (!visible || !fb) {
3091                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3092                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3093                 POSTING_READ(PLANE_CTL(pipe, 0));
3094                 return;
3095         }
3096
3097         plane_ctl = PLANE_CTL_ENABLE |
3098                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3099                     PLANE_CTL_PIPE_CSC_ENABLE;
3100
3101         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3102         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3103         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3104
3105         rotation = plane->state->rotation;
3106         plane_ctl |= skl_plane_ctl_rotation(rotation);
3107
3108         obj = intel_fb_obj(fb);
3109         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3110                                                fb->pixel_format);
3111         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3112
3113         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3114
3115         scaler_id = plane_state->scaler_id;
3116         src_x = plane_state->src.x1 >> 16;
3117         src_y = plane_state->src.y1 >> 16;
3118         src_w = drm_rect_width(&plane_state->src) >> 16;
3119         src_h = drm_rect_height(&plane_state->src) >> 16;
3120         dst_x = plane_state->dst.x1;
3121         dst_y = plane_state->dst.y1;
3122         dst_w = drm_rect_width(&plane_state->dst);
3123         dst_h = drm_rect_height(&plane_state->dst);
3124
3125         WARN_ON(x != src_x || y != src_y);
3126
3127         if (intel_rotation_90_or_270(rotation)) {
3128                 /* stride = Surface height in tiles */
3129                 tile_height = intel_tile_height(dev, fb->pixel_format,
3130                                                 fb->modifier[0], 0);
3131                 stride = DIV_ROUND_UP(fb->height, tile_height);
3132                 x_offset = stride * tile_height - y - src_h;
3133                 y_offset = x;
3134                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3135         } else {
3136                 stride = fb->pitches[0] / stride_div;
3137                 x_offset = x;
3138                 y_offset = y;
3139                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3140         }
3141         plane_offset = y_offset << 16 | x_offset;
3142
3143         intel_crtc->adjusted_x = x_offset;
3144         intel_crtc->adjusted_y = y_offset;
3145
3146         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3147         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3148         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3149         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3150
3151         if (scaler_id >= 0) {
3152                 uint32_t ps_ctrl = 0;
3153
3154                 WARN_ON(!dst_w || !dst_h);
3155                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3156                         crtc_state->scaler_state.scalers[scaler_id].mode;
3157                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3158                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3159                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3160                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3161                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3162         } else {
3163                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3164         }
3165
3166         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3167
3168         POSTING_READ(PLANE_SURF(pipe, 0));
3169 }
3170
3171 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3172 static int
3173 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3174                            int x, int y, enum mode_set_atomic state)
3175 {
3176         struct drm_device *dev = crtc->dev;
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178
3179         if (dev_priv->fbc.disable_fbc)
3180                 dev_priv->fbc.disable_fbc(dev_priv);
3181
3182         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3183
3184         return 0;
3185 }
3186
3187 static void intel_complete_page_flips(struct drm_device *dev)
3188 {
3189         struct drm_crtc *crtc;
3190
3191         for_each_crtc(dev, crtc) {
3192                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193                 enum plane plane = intel_crtc->plane;
3194
3195                 intel_prepare_page_flip(dev, plane);