drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 333         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 334 }
 335
 336 /**
 337  * Returns whether any output on the specified pipe is of the specified type
 338  */
 339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 340 {
 341         struct drm_device *dev = crtc->dev;
 342         struct intel_encoder *encoder;
 343
 344         for_each_encoder_on_crtc(dev, crtc, encoder)
 345                 if (encoder->type == type)
 346                         return true;
 347
 348         return false;
 349 }
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 limit = &intel_limits_vlv;
 412         } else if (!IS_GEN2(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 414                         limit = &intel_limits_i9xx_lvds;
 415                 else
 416                         limit = &intel_limits_i9xx_sdvo;
 417         } else {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i8xx_lvds;
 420                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 421                         limit = &intel_limits_i8xx_dvo;
 422                 else
 423                         limit = &intel_limits_i8xx_dac;
 424         }
 425         return limit;
 426 }
 427
 428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 429 static void pineview_clock(int refclk, intel_clock_t *clock)
 430 {
 431         clock->m = clock->m2 + 2;
 432         clock->p = clock->p1 * clock->p2;
 433         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 434         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 435 }
 436
 437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 438 {
 439         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 440 }
 441
 442 static void i9xx_clock(int refclk, intel_clock_t *clock)
 443 {
 444         clock->m = i9xx_dpll_compute_m(clock);
 445         clock->p = clock->p1 * clock->p2;
 446         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 447         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 448 }
 449
 450 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 451 /**
 452  * Returns whether the given set of divisors are valid for a given refclk with
 453  * the given connectors.
 454  */
 455
 456 static bool intel_PLL_is_valid(struct drm_device *dev,
 457                                const intel_limit_t *limit,
 458                                const intel_clock_t *clock)
 459 {
 460         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 461                 INTELPllInvalid("n out of range\n");
 462         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 463                 INTELPllInvalid("p1 out of range\n");
 464         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 465                 INTELPllInvalid("m2 out of range\n");
 466         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 467                 INTELPllInvalid("m1 out of range\n");
 468
 469         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 470                 if (clock->m1 <= clock->m2)
 471                         INTELPllInvalid("m1 <= m2\n");
 472
 473         if (!IS_VALLEYVIEW(dev)) {
 474                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 475                         INTELPllInvalid("p out of range\n");
 476                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 477                         INTELPllInvalid("m out of range\n");
 478         }
 479
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         intel_clock_t clock;
 675         unsigned int bestppm = 1000000;
 676         /* min update 19.2 MHz */
 677         int max_n = min(limit->n.max, refclk / 19200);
 678         bool found = false;
 679
 680         target *= 5; /* fast clock */
 681
 682         memset(best_clock, 0, sizeof(*best_clock));
 683
 684         /* based on hardware requirement, prefer smaller n to precision */
 685         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 686                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 687                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 688                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 689                                 clock.p = clock.p1 * clock.p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                                         unsigned int ppm, diff;
 693
 694                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 695                                                                      refclk * clock.m1);
 696
 697                                         vlv_clock(refclk, &clock);
 698
 699                                         if (!intel_PLL_is_valid(dev, limit,
 700                                                                 &clock))
 701                                                 continue;
 702
 703                                         diff = abs(clock.dot - target);
 704                                         ppm = div_u64(1000000ULL * diff, target);
 705
 706                                         if (ppm < 100 && clock.p > best_clock->p) {
 707                                                 bestppm = 0;
 708                                                 *best_clock = clock;
 709                                                 found = true;
 710                                         }
 711
 712                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 713                                                 bestppm = ppm;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return found;
 723 }
 724
 725 bool intel_crtc_active(struct drm_crtc *crtc)
 726 {
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728
 729         /* Be paranoid as we can arrive here with only partial
 730          * state retrieved from the hardware during setup.
 731          *
 732          * We can ditch the adjusted_mode.crtc_clock check as soon
 733          * as Haswell has gained clock readout/fastboot support.
 734          *
 735          * We can ditch the crtc->fb check as soon as we can
 736          * properly reconstruct framebuffers.
 737          */
 738         return intel_crtc->active && crtc->fb &&
 739                 intel_crtc->config.adjusted_mode.crtc_clock;
 740 }
 741
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe)
 744 {
 745         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 747
 748         return intel_crtc->config.cpu_transcoder;
 749 }
 750
 751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 frame, frame_reg = PIPEFRAME(pipe);
 755
 756         frame = I915_READ(frame_reg);
 757
 758         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 759                 DRM_DEBUG_KMS("vblank wait timed out\n");
 760 }
 761
 762 /**
 763  * intel_wait_for_vblank - wait for vblank on a given pipe
 764  * @dev: drm device
 765  * @pipe: pipe to wait for
 766  *
 767  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 768  * mode setting code.
 769  */
 770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int pipestat_reg = PIPESTAT(pipe);
 774
 775         if (INTEL_INFO(dev)->gen >= 5) {
 776                 ironlake_wait_for_vblank(dev, pipe);
 777                 return;
 778         }
 779
 780         /* Clear existing vblank status. Note this will clear any other
 781          * sticky status fields as well.
 782          *
 783          * This races with i915_driver_irq_handler() with the result
 784          * that either function could miss a vblank event.  Here it is not
 785          * fatal, as we will either wait upon the next vblank interrupt or
 786          * timeout.  Generally speaking intel_wait_for_vblank() is only
 787          * called during modeset at which time the GPU should be idle and
 788          * should *not* be performing page flips and thus not waiting on
 789          * vblanks...
 790          * Currently, the result of us stealing a vblank from the irq
 791          * handler is that a single frame will be skipped during swapbuffers.
 792          */
 793         I915_WRITE(pipestat_reg,
 794                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 795
 796         /* Wait for vblank interrupt bit to set */
 797         if (wait_for(I915_READ(pipestat_reg) &
 798                      PIPE_VBLANK_INTERRUPT_STATUS,
 799                      50))
 800                 DRM_DEBUG_KMS("vblank wait timed out\n");
 801 }
 802
 803 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         u32 reg = PIPEDSL(pipe);
 807         u32 line1, line2;
 808         u32 line_mask;
 809
 810         if (IS_GEN2(dev))
 811                 line_mask = DSL_LINEMASK_GEN2;
 812         else
 813                 line_mask = DSL_LINEMASK_GEN3;
 814
 815         line1 = I915_READ(reg) & line_mask;
 816         mdelay(5);
 817         line2 = I915_READ(reg) & line_mask;
 818
 819         return line1 == line2;
 820 }
 821
 822 /*
 823  * intel_wait_for_pipe_off - wait for pipe to turn off
 824  * @dev: drm device
 825  * @pipe: pipe to wait for
 826  *
 827  * After disabling a pipe, we can't wait for vblank in the usual way,
 828  * spinning on the vblank interrupt status bit, since we won't actually
 829  * see an interrupt when the pipe is disabled.
 830  *
 831  * On Gen4 and above:
 832  *   wait for the pipe register state bit to turn off
 833  *
 834  * Otherwise:
 835  *   wait for the display line value to settle (it usually
 836  *   ends up stopping at the start of the next frame).
 837  *
 838  */
 839 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 840 {
 841         struct drm_i915_private *dev_priv = dev->dev_private;
 842         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 843                                                                       pipe);
 844
 845         if (INTEL_INFO(dev)->gen >= 4) {
 846                 int reg = PIPECONF(cpu_transcoder);
 847
 848                 /* Wait for the Pipe State to go off */
 849                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 850                              100))
 851                         WARN(1, "pipe_off wait timed out\n");
 852         } else {
 853                 /* Wait for the display line to settle */
 854                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 855                         WARN(1, "pipe_off wait timed out\n");
 856         }
 857 }
 858
 859 /*
 860  * ibx_digital_port_connected - is the specified port connected?
 861  * @dev_priv: i915 private structure
 862  * @port: the port to test
 863  *
 864  * Returns true if @port is connected, false otherwise.
 865  */
 866 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 867                                 struct intel_digital_port *port)
 868 {
 869         u32 bit;
 870
 871         if (HAS_PCH_IBX(dev_priv->dev)) {
 872                 switch(port->port) {
 873                 case PORT_B:
 874                         bit = SDE_PORTB_HOTPLUG;
 875                         break;
 876                 case PORT_C:
 877                         bit = SDE_PORTC_HOTPLUG;
 878                         break;
 879                 case PORT_D:
 880                         bit = SDE_PORTD_HOTPLUG;
 881                         break;
 882                 default:
 883                         return true;
 884                 }
 885         } else {
 886                 switch(port->port) {
 887                 case PORT_B:
 888                         bit = SDE_PORTB_HOTPLUG_CPT;
 889                         break;
 890                 case PORT_C:
 891                         bit = SDE_PORTC_HOTPLUG_CPT;
 892                         break;
 893                 case PORT_D:
 894                         bit = SDE_PORTD_HOTPLUG_CPT;
 895                         break;
 896                 default:
 897                         return true;
 898                 }
 899         }
 900
 901         return I915_READ(SDEISR) & bit;
 902 }
 903
 904 static const char *state_string(bool enabled)
 905 {
 906         return enabled ? "on" : "off";
 907 }
 908
 909 /* Only for pre-ILK configs */
 910 void assert_pll(struct drm_i915_private *dev_priv,
 911                 enum pipe pipe, bool state)
 912 {
 913         int reg;
 914         u32 val;
 915         bool cur_state;
 916
 917         reg = DPLL(pipe);
 918         val = I915_READ(reg);
 919         cur_state = !!(val & DPLL_VCO_ENABLE);
 920         WARN(cur_state != state,
 921              "PLL state assertion failure (expected %s, current %s)\n",
 922              state_string(state), state_string(cur_state));
 923 }
 924
 925 /* XXX: the dsi pll is shared between MIPI DSI ports */
 926 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 927 {
 928         u32 val;
 929         bool cur_state;
 930
 931         mutex_lock(&dev_priv->dpio_lock);
 932         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 933         mutex_unlock(&dev_priv->dpio_lock);
 934
 935         cur_state = val & DSI_PLL_VCO_EN;
 936         WARN(cur_state != state,
 937              "DSI PLL state assertion failure (expected %s, current %s)\n",
 938              state_string(state), state_string(cur_state));
 939 }
 940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 942
 943 struct intel_shared_dpll *
 944 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 945 {
 946         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 947
 948         if (crtc->config.shared_dpll < 0)
 949                 return NULL;
 950
 951         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 952 }
 953
 954 /* For ILK+ */
 955 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 956                         struct intel_shared_dpll *pll,
 957                         bool state)
 958 {
 959         bool cur_state;
 960         struct intel_dpll_hw_state hw_state;
 961
 962         if (HAS_PCH_LPT(dev_priv->dev)) {
 963                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 964                 return;
 965         }
 966
 967         if (WARN (!pll,
 968                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 969                 return;
 970
 971         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 972         WARN(cur_state != state,
 973              "%s assertion failure (expected %s, current %s)\n",
 974              pll->name, state_string(state), state_string(cur_state));
 975 }
 976
 977 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 978                           enum pipe pipe, bool state)
 979 {
 980         int reg;
 981         u32 val;
 982         bool cur_state;
 983         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 984                                                                       pipe);
 985
 986         if (HAS_DDI(dev_priv->dev)) {
 987                 /* DDI does not have a specific FDI_TX register */
 988                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 989                 val = I915_READ(reg);
 990                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 991         } else {
 992                 reg = FDI_TX_CTL(pipe);
 993                 val = I915_READ(reg);
 994                 cur_state = !!(val & FDI_TX_ENABLE);
 995         }
 996         WARN(cur_state != state,
 997              "FDI TX state assertion failure (expected %s, current %s)\n",
 998              state_string(state), state_string(cur_state));
 999 }
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004                           enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = FDI_RX_CTL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & FDI_RX_ENABLE);
1013         WARN(cur_state != state,
1014              "FDI RX state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         /* ILK FDI PLL is always enabled */
1027         if (dev_priv->info->gen == 5)
1028                 return;
1029
1030         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031         if (HAS_DDI(dev_priv->dev))
1032                 return;
1033
1034         reg = FDI_TX_CTL(pipe);
1035         val = I915_READ(reg);
1036         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037 }
1038
1039 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = FDI_RX_CTL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049         WARN(cur_state != state,
1050              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053
1054 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055                                   enum pipe pipe)
1056 {
1057         int pp_reg, lvds_reg;
1058         u32 val;
1059         enum pipe panel_pipe = PIPE_A;
1060         bool locked = true;
1061
1062         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063                 pp_reg = PCH_PP_CONTROL;
1064                 lvds_reg = PCH_LVDS;
1065         } else {
1066                 pp_reg = PP_CONTROL;
1067                 lvds_reg = LVDS;
1068         }
1069
1070         val = I915_READ(pp_reg);
1071         if (!(val & PANEL_POWER_ON) ||
1072             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073                 locked = false;
1074
1075         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076                 panel_pipe = PIPE_B;
1077
1078         WARN(panel_pipe == pipe && locked,
1079              "panel assertion failure, pipe %c regs locked\n",
1080              pipe_name(pipe));
1081 }
1082
1083 static void assert_cursor(struct drm_i915_private *dev_priv,
1084                           enum pipe pipe, bool state)
1085 {
1086         struct drm_device *dev = dev_priv->dev;
1087         bool cur_state;
1088
1089         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091         else if (IS_845G(dev) || IS_I865G(dev))
1092                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093         else
1094                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096         WARN(cur_state != state,
1097              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098              pipe_name(pipe), state_string(state), state_string(cur_state));
1099 }
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104                  enum pipe pipe, bool state)
1105 {
1106         int reg;
1107         u32 val;
1108         bool cur_state;
1109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110                                                                       pipe);
1111
1112         /* if we need the pipe A quirk it must be always on */
1113         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114                 state = true;
1115
1116         if (!intel_display_power_enabled(dev_priv->dev,
1117                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1118                 cur_state = false;
1119         } else {
1120                 reg = PIPECONF(cpu_transcoder);
1121                 val = I915_READ(reg);
1122                 cur_state = !!(val & PIPECONF_ENABLE);
1123         }
1124
1125         WARN(cur_state != state,
1126              "pipe %c assertion failure (expected %s, current %s)\n",
1127              pipe_name(pipe), state_string(state), state_string(cur_state));
1128 }
1129
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131                          enum plane plane, bool state)
1132 {
1133         int reg;
1134         u32 val;
1135         bool cur_state;
1136
1137         reg = DSPCNTR(plane);
1138         val = I915_READ(reg);
1139         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140         WARN(cur_state != state,
1141              "plane %c assertion failure (expected %s, current %s)\n",
1142              plane_name(plane), state_string(state), state_string(cur_state));
1143 }
1144
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149                                    enum pipe pipe)
1150 {
1151         struct drm_device *dev = dev_priv->dev;
1152         int reg, i;
1153         u32 val;
1154         int cur_pipe;
1155
1156         /* Primary planes are fixed to pipes on gen4+ */
1157         if (INTEL_INFO(dev)->gen >= 4) {
1158                 reg = DSPCNTR(pipe);
1159                 val = I915_READ(reg);
1160                 WARN((val & DISPLAY_PLANE_ENABLE),
1161                      "plane %c assertion failure, should be disabled but not\n",
1162                      plane_name(pipe));
1163                 return;
1164         }
1165
1166         /* Need to check both planes against the pipe */
1167         for_each_pipe(i) {
1168                 reg = DSPCNTR(i);
1169                 val = I915_READ(reg);
1170                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171                         DISPPLANE_SEL_PIPE_SHIFT;
1172                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1173                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174                      plane_name(i), pipe_name(pipe));
1175         }
1176 }
1177
1178 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179                                     enum pipe pipe)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         int reg, i;
1183         u32 val;
1184
1185         if (IS_VALLEYVIEW(dev)) {
1186                 for (i = 0; i < dev_priv->num_plane; i++) {
1187                         reg = SPCNTR(pipe, i);
1188                         val = I915_READ(reg);
1189                         WARN((val & SP_ENABLE),
1190                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191                              sprite_name(pipe, i), pipe_name(pipe));
1192                 }
1193         } else if (INTEL_INFO(dev)->gen >= 7) {
1194                 reg = SPRCTL(pipe);
1195                 val = I915_READ(reg);
1196                 WARN((val & SPRITE_ENABLE),
1197                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198                      plane_name(pipe), pipe_name(pipe));
1199         } else if (INTEL_INFO(dev)->gen >= 5) {
1200                 reg = DVSCNTR(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & DVS_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         }
1206 }
1207
1208 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209 {
1210         u32 val;
1211         bool enabled;
1212
1213         if (HAS_PCH_LPT(dev_priv->dev)) {
1214                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215                 return;
1216         }
1217
1218         val = I915_READ(PCH_DREF_CONTROL);
1219         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220                             DREF_SUPERSPREAD_SOURCE_MASK));
1221         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222 }
1223
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225                                            enum pipe pipe)
1226 {
1227         int reg;
1228         u32 val;
1229         bool enabled;
1230
1231         reg = PCH_TRANSCONF(pipe);
1232         val = I915_READ(reg);
1233         enabled = !!(val & TRANS_ENABLE);
1234         WARN(enabled,
1235              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236              pipe_name(pipe));
1237 }
1238
1239 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240                             enum pipe pipe, u32 port_sel, u32 val)
1241 {
1242         if ((val & DP_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249                         return false;
1250         } else {
1251                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252                         return false;
1253         }
1254         return true;
1255 }
1256
1257 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258                               enum pipe pipe, u32 val)
1259 {
1260         if ((val & SDVO_ENABLE) == 0)
1261                 return false;
1262
1263         if (HAS_PCH_CPT(dev_priv->dev)) {
1264                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1265                         return false;
1266         } else {
1267                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1268                         return false;
1269         }
1270         return true;
1271 }
1272
1273 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274                               enum pipe pipe, u32 val)
1275 {
1276         if ((val & LVDS_PORT_EN) == 0)
1277                 return false;
1278
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290                               enum pipe pipe, u32 val)
1291 {
1292         if ((val & ADPA_DAC_ENABLE) == 0)
1293                 return false;
1294         if (HAS_PCH_CPT(dev_priv->dev)) {
1295                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296                         return false;
1297         } else {
1298                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299                         return false;
1300         }
1301         return true;
1302 }
1303
1304 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1305                                    enum pipe pipe, int reg, u32 port_sel)
1306 {
1307         u32 val = I915_READ(reg);
1308         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1309              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310              reg, pipe_name(pipe));
1311
1312         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313              && (val & DP_PIPEB_SELECT),
1314              "IBX PCH dp port still using transcoder B\n");
1315 }
1316
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318                                      enum pipe pipe, int reg)
1319 {
1320         u32 val = I915_READ(reg);
1321         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1322              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323              reg, pipe_name(pipe));
1324
1325         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1326              && (val & SDVO_PIPE_B_SELECT),
1327              "IBX PCH hdmi port still using transcoder B\n");
1328 }
1329
1330 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331                                       enum pipe pipe)
1332 {
1333         int reg;
1334         u32 val;
1335
1336         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1339
1340         reg = PCH_ADPA;
1341         val = I915_READ(reg);
1342         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1343              "PCH VGA enabled on transcoder %c, should be disabled\n",
1344              pipe_name(pipe));
1345
1346         reg = PCH_LVDS;
1347         val = I915_READ(reg);
1348         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1349              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1355 }
1356
1357 static void intel_init_dpio(struct drm_device *dev)
1358 {
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361         if (!IS_VALLEYVIEW(dev))
1362                 return;
1363
1364         /*
1365          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1367          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368          *   b. The other bits such as sfr settings / modesel may all be set
1369          *      to 0.
1370          *
1371          * This should only be done on init and resume from S3 with both
1372          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373          */
1374         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375 }
1376
1377 static void vlv_enable_pll(struct intel_crtc *crtc)
1378 {
1379         struct drm_device *dev = crtc->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         int reg = DPLL(crtc->pipe);
1382         u32 dpll = crtc->config.dpll_hw_state.dpll;
1383
1384         assert_pipe_disabled(dev_priv, crtc->pipe);
1385
1386         /* No really, not for ILK+ */
1387         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389         /* PLL is protected by panel, make sure we can write it */
1390         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1391                 assert_panel_unlocked(dev_priv, crtc->pipe);
1392
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150);
1396
1397         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401         POSTING_READ(DPLL_MD(crtc->pipe));
1402
1403         /* We do this three times for luck */
1404         I915_WRITE(reg, dpll);
1405         POSTING_READ(reg);
1406         udelay(150); /* wait for warmup */
1407         I915_WRITE(reg, dpll);
1408         POSTING_READ(reg);
1409         udelay(150); /* wait for warmup */
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150); /* wait for warmup */
1413 }
1414
1415 static void i9xx_enable_pll(struct intel_crtc *crtc)
1416 {
1417         struct drm_device *dev = crtc->base.dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         int reg = DPLL(crtc->pipe);
1420         u32 dpll = crtc->config.dpll_hw_state.dpll;
1421
1422         assert_pipe_disabled(dev_priv, crtc->pipe);
1423
1424         /* No really, not for ILK+ */
1425         BUG_ON(dev_priv->info->gen >= 5);
1426
1427         /* PLL is protected by panel, make sure we can write it */
1428         if (IS_MOBILE(dev) && !IS_I830(dev))
1429                 assert_panel_unlocked(dev_priv, crtc->pipe);
1430
1431         I915_WRITE(reg, dpll);
1432
1433         /* Wait for the clocks to stabilize. */
1434         POSTING_READ(reg);
1435         udelay(150);
1436
1437         if (INTEL_INFO(dev)->gen >= 4) {
1438                 I915_WRITE(DPLL_MD(crtc->pipe),
1439                            crtc->config.dpll_hw_state.dpll_md);
1440         } else {
1441                 /* The pixel multiplier can only be updated once the
1442                  * DPLL is enabled and the clocks are stable.
1443                  *
1444                  * So write it again.
1445                  */
1446                 I915_WRITE(reg, dpll);
1447         }
1448
1449         /* We do this three times for luck */
1450         I915_WRITE(reg, dpll);
1451         POSTING_READ(reg);
1452         udelay(150); /* wait for warmup */
1453         I915_WRITE(reg, dpll);
1454         POSTING_READ(reg);
1455         udelay(150); /* wait for warmup */
1456         I915_WRITE(reg, dpll);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462  * i9xx_disable_pll - disable a PLL
1463  * @dev_priv: i915 private structure
1464  * @pipe: pipe PLL to disable
1465  *
1466  * Disable the PLL for @pipe, making sure the pipe is off first.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  */
1470 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472         /* Don't disable pipe A or pipe A PLLs if needed */
1473         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474                 return;
1475
1476         /* Make sure the pipe isn't still relying on us */
1477         assert_pipe_disabled(dev_priv, pipe);
1478
1479         I915_WRITE(DPLL(pipe), 0);
1480         POSTING_READ(DPLL(pipe));
1481 }
1482
1483 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484 {
1485         u32 val = 0;
1486
1487         /* Make sure the pipe isn't still relying on us */
1488         assert_pipe_disabled(dev_priv, pipe);
1489
1490         /* Leave integrated clock source enabled */
1491         if (pipe == PIPE_B)
1492                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493         I915_WRITE(DPLL(pipe), val);
1494         POSTING_READ(DPLL(pipe));
1495 }
1496
1497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498 {
1499         u32 port_mask;
1500
1501         if (!port)
1502                 port_mask = DPLL_PORTB_READY_MASK;
1503         else
1504                 port_mask = DPLL_PORTC_READY_MASK;
1505
1506         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508                      'B' + port, I915_READ(DPLL(0)));
1509 }
1510
1511 /**
1512  * ironlake_enable_shared_dpll - enable PCH PLL
1513  * @dev_priv: i915 private structure
1514  * @pipe: pipe PLL to enable
1515  *
1516  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517  * drives the transcoder clock.
1518  */
1519 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1520 {
1521         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1523
1524         /* PCH PLLs only available on ILK, SNB and IVB */
1525         BUG_ON(dev_priv->info->gen < 5);
1526         if (WARN_ON(pll == NULL))
1527                 return;
1528
1529         if (WARN_ON(pll->refcount == 0))
1530                 return;
1531
1532         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533                       pll->name, pll->active, pll->on,
1534                       crtc->base.base.id);
1535
1536         if (pll->active++) {
1537                 WARN_ON(!pll->on);
1538                 assert_shared_dpll_enabled(dev_priv, pll);
1539                 return;
1540         }
1541         WARN_ON(pll->on);
1542
1543         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1544         pll->enable(dev_priv, pll);
1545         pll->on = true;
1546 }
1547
1548 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1549 {
1550         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1552
1553         /* PCH only available on ILK+ */
1554         BUG_ON(dev_priv->info->gen < 5);
1555         if (WARN_ON(pll == NULL))
1556                return;
1557
1558         if (WARN_ON(pll->refcount == 0))
1559                 return;
1560
1561         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562                       pll->name, pll->active, pll->on,
1563                       crtc->base.base.id);
1564
1565         if (WARN_ON(pll->active == 0)) {
1566                 assert_shared_dpll_disabled(dev_priv, pll);
1567                 return;
1568         }
1569
1570         assert_shared_dpll_enabled(dev_priv, pll);
1571         WARN_ON(!pll->on);
1572         if (--pll->active)
1573                 return;
1574
1575         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1576         pll->disable(dev_priv, pll);
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586         uint32_t reg, val, pipeconf_val;
1587
1588         /* PCH only available on ILK+ */
1589         BUG_ON(dev_priv->info->gen < 5);
1590
1591         /* Make sure PCH DPLL is enabled */
1592         assert_shared_dpll_enabled(dev_priv,
1593                                    intel_crtc_to_shared_dpll(intel_crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port, bool dsi)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_cursor_disabled(dev_priv, pipe);
1739         assert_sprites_disabled(dev_priv, pipe);
1740
1741         if (HAS_PCH_LPT(dev_priv->dev))
1742                 pch_transcoder = TRANSCODER_A;
1743         else
1744                 pch_transcoder = pipe;
1745
1746         /*
1747          * A pipe without a PLL won't actually be able to drive bits from
1748          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1749          * need the check.
1750          */
1751         if (!HAS_PCH_SPLIT(dev_priv->dev))
1752                 if (dsi)
1753                         assert_dsi_pll_enabled(dev_priv);
1754                 else
1755                         assert_pll_enabled(dev_priv, pipe);
1756         else {
1757                 if (pch_port) {
1758                         /* if driving the PCH, we need FDI enabled */
1759                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1760                         assert_fdi_tx_pll_enabled(dev_priv,
1761                                                   (enum pipe) cpu_transcoder);
1762                 }
1763                 /* FIXME: assert CPU port conditions for SNB+ */
1764         }
1765
1766         reg = PIPECONF(cpu_transcoder);
1767         val = I915_READ(reg);
1768         if (val & PIPECONF_ENABLE)
1769                 return;
1770
1771         I915_WRITE(reg, val | PIPECONF_ENABLE);
1772         intel_wait_for_vblank(dev_priv->dev, pipe);
1773 }
1774
1775 /**
1776  * intel_disable_pipe - disable a pipe, asserting requirements
1777  * @dev_priv: i915 private structure
1778  * @pipe: pipe to disable
1779  *
1780  * Disable @pipe, making sure that various hardware specific requirements
1781  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782  *
1783  * @pipe should be %PIPE_A or %PIPE_B.
1784  *
1785  * Will wait until the pipe has shut down before returning.
1786  */
1787 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788                                enum pipe pipe)
1789 {
1790         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791                                                                       pipe);
1792         int reg;
1793         u32 val;
1794
1795         /*
1796          * Make sure planes won't keep trying to pump pixels to us,
1797          * or we might hang the display.
1798          */
1799         assert_planes_disabled(dev_priv, pipe);
1800         assert_cursor_disabled(dev_priv, pipe);
1801         assert_sprites_disabled(dev_priv, pipe);
1802
1803         /* Don't disable pipe A or pipe A PLLs if needed */
1804         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805                 return;
1806
1807         reg = PIPECONF(cpu_transcoder);
1808         val = I915_READ(reg);
1809         if ((val & PIPECONF_ENABLE) == 0)
1810                 return;
1811
1812         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1813         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814 }
1815
1816 /*
1817  * Plane regs are double buffered, going from enabled->disabled needs a
1818  * trigger in order to latch.  The display address reg provides this.
1819  */
1820 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane)
1822 {
1823         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825         I915_WRITE(reg, I915_READ(reg));
1826         POSTING_READ(reg);
1827 }
1828
1829 /**
1830  * intel_enable_primary_plane - enable the primary plane on a given pipe
1831  * @dev_priv: i915 private structure
1832  * @plane: plane to enable
1833  * @pipe: pipe being fed
1834  *
1835  * Enable @plane on @pipe, making sure that @pipe is running first.
1836  */
1837 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838                                        enum plane plane, enum pipe pipe)
1839 {
1840         struct intel_crtc *intel_crtc =
1841                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1842         int reg;
1843         u32 val;
1844
1845         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846         assert_pipe_enabled(dev_priv, pipe);
1847
1848         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1849
1850         intel_crtc->primary_enabled = true;
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_primary_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_primary_plane - disable the primary plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871                                         enum plane plane, enum pipe pipe)
1872 {
1873         struct intel_crtc *intel_crtc =
1874                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1875         int reg;
1876         u32 val;
1877
1878         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1879
1880         intel_crtc->primary_enabled = false;
1881
1882         reg = DSPCNTR(plane);
1883         val = I915_READ(reg);
1884         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885                 return;
1886
1887         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1888         intel_flush_primary_plane(dev_priv, plane);
1889         intel_wait_for_vblank(dev_priv->dev, pipe);
1890 }
1891
1892 static bool need_vtd_wa(struct drm_device *dev)
1893 {
1894 #ifdef CONFIG_INTEL_IOMMU
1895         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896                 return true;
1897 #endif
1898         return false;
1899 }
1900
1901 int
1902 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1903                            struct drm_i915_gem_object *obj,
1904                            struct intel_ring_buffer *pipelined)
1905 {
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         u32 alignment;
1908         int ret;
1909
1910         switch (obj->tiling_mode) {
1911         case I915_TILING_NONE:
1912                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913                         alignment = 128 * 1024;
1914                 else if (INTEL_INFO(dev)->gen >= 4)
1915                         alignment = 4 * 1024;
1916                 else
1917                         alignment = 64 * 1024;
1918                 break;
1919         case I915_TILING_X:
1920                 /* pin() will align the object as required by fence */
1921                 alignment = 0;
1922                 break;
1923         case I915_TILING_Y:
1924                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1925                 return -EINVAL;
1926         default:
1927                 BUG();
1928         }
1929
1930         /* Note that the w/a also requires 64 PTE of padding following the
1931          * bo. We currently fill all unused PTE with the shadow page and so
1932          * we should always have valid PTE following the scanout preventing
1933          * the VT-d warning.
1934          */
1935         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936                 alignment = 256 * 1024;
1937
1938         dev_priv->mm.interruptible = false;
1939         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1940         if (ret)
1941                 goto err_interruptible;
1942
1943         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944          * fence, whereas 965+ only requires a fence if using
1945          * framebuffer compression.  For simplicity, we always install
1946          * a fence as the cost is not that onerous.
1947          */
1948         ret = i915_gem_object_get_fence(obj);
1949         if (ret)
1950                 goto err_unpin;
1951
1952         i915_gem_object_pin_fence(obj);
1953
1954         dev_priv->mm.interruptible = true;
1955         return 0;
1956
1957 err_unpin:
1958         i915_gem_object_unpin_from_display_plane(obj);
1959 err_interruptible:
1960         dev_priv->mm.interruptible = true;
1961         return ret;
1962 }
1963
1964 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965 {
1966         i915_gem_object_unpin_fence(obj);
1967         i915_gem_object_unpin_from_display_plane(obj);
1968 }
1969
1970 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971  * is assumed to be a power-of-two. */
1972 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973                                              unsigned int tiling_mode,
1974                                              unsigned int cpp,
1975                                              unsigned int pitch)
1976 {
1977         if (tiling_mode != I915_TILING_NONE) {
1978                 unsigned int tile_rows, tiles;
1979
1980                 tile_rows = *y / 8;
1981                 *y %= 8;
1982
1983                 tiles = *x / (512/cpp);
1984                 *x %= 512/cpp;
1985
1986                 return tile_rows * pitch * 8 + tiles * 4096;
1987         } else {
1988                 unsigned int offset;
1989
1990                 offset = *y * pitch + *x * cpp;
1991                 *y = 0;
1992                 *x = (offset & 4095) / cpp;
1993                 return offset & -4096;
1994         }
1995 }
1996
1997 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998                              int x, int y)
1999 {
2000         struct drm_device *dev = crtc->dev;
2001         struct drm_i915_private *dev_priv = dev->dev_private;
2002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003         struct intel_framebuffer *intel_fb;
2004         struct drm_i915_gem_object *obj;
2005         int plane = intel_crtc->plane;
2006         unsigned long linear_offset;
2007         u32 dspcntr;
2008         u32 reg;
2009
2010         switch (plane) {
2011         case 0:
2012         case 1:
2013                 break;
2014         default:
2015                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2016                 return -EINVAL;
2017         }
2018
2019         intel_fb = to_intel_framebuffer(fb);
2020         obj = intel_fb->obj;
2021
2022         reg = DSPCNTR(plane);
2023         dspcntr = I915_READ(reg);
2024         /* Mask out pixel format bits in case we change it */
2025         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2026         switch (fb->pixel_format) {
2027         case DRM_FORMAT_C8:
2028                 dspcntr |= DISPPLANE_8BPP;
2029                 break;
2030         case DRM_FORMAT_XRGB1555:
2031         case DRM_FORMAT_ARGB1555:
2032                 dspcntr |= DISPPLANE_BGRX555;
2033                 break;
2034         case DRM_FORMAT_RGB565:
2035                 dspcntr |= DISPPLANE_BGRX565;
2036                 break;
2037         case DRM_FORMAT_XRGB8888:
2038         case DRM_FORMAT_ARGB8888:
2039                 dspcntr |= DISPPLANE_BGRX888;
2040                 break;
2041         case DRM_FORMAT_XBGR8888:
2042         case DRM_FORMAT_ABGR8888:
2043                 dspcntr |= DISPPLANE_RGBX888;
2044                 break;
2045         case DRM_FORMAT_XRGB2101010:
2046         case DRM_FORMAT_ARGB2101010:
2047                 dspcntr |= DISPPLANE_BGRX101010;
2048                 break;
2049         case DRM_FORMAT_XBGR2101010:
2050         case DRM_FORMAT_ABGR2101010:
2051                 dspcntr |= DISPPLANE_RGBX101010;
2052                 break;
2053         default:
2054                 BUG();
2055         }
2056
2057         if (INTEL_INFO(dev)->gen >= 4) {
2058                 if (obj->tiling_mode != I915_TILING_NONE)
2059                         dspcntr |= DISPPLANE_TILED;
2060                 else
2061                         dspcntr &= ~DISPPLANE_TILED;
2062         }
2063
2064         if (IS_G4X(dev))
2065                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
2067         I915_WRITE(reg, dspcntr);
2068
2069         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2070
2071         if (INTEL_INFO(dev)->gen >= 4) {
2072                 intel_crtc->dspaddr_offset =
2073                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074                                                        fb->bits_per_pixel / 8,
2075                                                        fb->pitches[0]);
2076                 linear_offset -= intel_crtc->dspaddr_offset;
2077         } else {
2078                 intel_crtc->dspaddr_offset = linear_offset;
2079         }
2080
2081         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083                       fb->pitches[0]);
2084         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2085         if (INTEL_INFO(dev)->gen >= 4) {
2086                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2087                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2088                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2090         } else
2091                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2092         POSTING_READ(reg);
2093
2094         return 0;
2095 }
2096
2097 static int ironlake_update_plane(struct drm_crtc *crtc,
2098                                  struct drm_framebuffer *fb, int x, int y)
2099 {
2100         struct drm_device *dev = crtc->dev;
2101         struct drm_i915_private *dev_priv = dev->dev_private;
2102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103         struct intel_framebuffer *intel_fb;
2104         struct drm_i915_gem_object *obj;
2105         int plane = intel_crtc->plane;
2106         unsigned long linear_offset;
2107         u32 dspcntr;
2108         u32 reg;
2109
2110         switch (plane) {
2111         case 0:
2112         case 1:
2113         case 2:
2114                 break;
2115         default:
2116                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2117                 return -EINVAL;
2118         }
2119
2120         intel_fb = to_intel_framebuffer(fb);
2121         obj = intel_fb->obj;
2122
2123         reg = DSPCNTR(plane);
2124         dspcntr = I915_READ(reg);
2125         /* Mask out pixel format bits in case we change it */
2126         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2127         switch (fb->pixel_format) {
2128         case DRM_FORMAT_C8:
2129                 dspcntr |= DISPPLANE_8BPP;
2130                 break;
2131         case DRM_FORMAT_RGB565:
2132                 dspcntr |= DISPPLANE_BGRX565;
2133                 break;
2134         case DRM_FORMAT_XRGB8888:
2135         case DRM_FORMAT_ARGB8888:
2136                 dspcntr |= DISPPLANE_BGRX888;
2137                 break;
2138         case DRM_FORMAT_XBGR8888:
2139         case DRM_FORMAT_ABGR8888:
2140                 dspcntr |= DISPPLANE_RGBX888;
2141                 break;
2142         case DRM_FORMAT_XRGB2101010:
2143         case DRM_FORMAT_ARGB2101010:
2144                 dspcntr |= DISPPLANE_BGRX101010;
2145                 break;
2146         case DRM_FORMAT_XBGR2101010:
2147         case DRM_FORMAT_ABGR2101010:
2148                 dspcntr |= DISPPLANE_RGBX101010;
2149                 break;
2150         default:
2151                 BUG();
2152         }
2153
2154         if (obj->tiling_mode != I915_TILING_NONE)
2155                 dspcntr |= DISPPLANE_TILED;
2156         else
2157                 dspcntr &= ~DISPPLANE_TILED;
2158
2159         if (IS_HASWELL(dev))
2160                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161         else
2162                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2163
2164         I915_WRITE(reg, dspcntr);
2165
2166         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2167         intel_crtc->dspaddr_offset =
2168                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169                                                fb->bits_per_pixel / 8,
2170                                                fb->pitches[0]);
2171         linear_offset -= intel_crtc->dspaddr_offset;
2172
2173         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175                       fb->pitches[0]);
2176         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2177         I915_MODIFY_DISPBASE(DSPSURF(plane),
2178                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2179         if (IS_HASWELL(dev)) {
2180                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181         } else {
2182                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184         }
2185         POSTING_READ(reg);
2186
2187         return 0;
2188 }
2189
2190 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2191 static int
2192 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193                            int x, int y, enum mode_set_atomic state)
2194 {
2195         struct drm_device *dev = crtc->dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197
2198         if (dev_priv->display.disable_fbc)
2199                 dev_priv->display.disable_fbc(dev);
2200         intel_increase_pllclock(crtc);
2201
2202         return dev_priv->display.update_plane(crtc, fb, x, y);
2203 }
2204
2205 void intel_display_handle_reset(struct drm_device *dev)
2206 {
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_crtc *crtc;
2209
2210         /*
2211          * Flips in the rings have been nuked by the reset,
2212          * so complete all pending flips so that user space
2213          * will get its events and not get stuck.
2214          *
2215          * Also update the base address of all primary
2216          * planes to the the last fb to make sure we're
2217          * showing the correct fb after a reset.
2218          *
2219          * Need to make two loops over the crtcs so that we
2220          * don't try to grab a crtc mutex before the
2221          * pending_flip_queue really got woken up.
2222          */
2223
2224         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226                 enum plane plane = intel_crtc->plane;
2227
2228                 intel_prepare_page_flip(dev, plane);
2229                 intel_finish_page_flip_plane(dev, plane);
2230         }
2231
2232         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235                 mutex_lock(&crtc->mutex);
2236                 if (intel_crtc->active)
2237                         dev_priv->display.update_plane(crtc, crtc->fb,
2238                                                        crtc->x, crtc->y);
2239                 mutex_unlock(&crtc->mutex);
2240         }
2241 }
2242
2243 static int
2244 intel_finish_fb(struct drm_framebuffer *old_fb)
2245 {
2246         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248         bool was_interruptible = dev_priv->mm.interruptible;
2249         int ret;
2250
2251         /* Big Hammer, we also need to ensure that any pending
2252          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253          * current scanout is retired before unpinning the old
2254          * framebuffer.
2255          *
2256          * This should only fail upon a hung GPU, in which case we
2257          * can safely continue.
2258          */
2259         dev_priv->mm.interruptible = false;
2260         ret = i915_gem_object_finish_gpu(obj);
2261         dev_priv->mm.interruptible = was_interruptible;
2262
2263         return ret;
2264 }
2265
2266 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267 {
2268         struct drm_device *dev = crtc->dev;
2269         struct drm_i915_master_private *master_priv;
2270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272         if (!dev->primary->master)
2273                 return;
2274
2275         master_priv = dev->primary->master->driver_priv;
2276         if (!master_priv->sarea_priv)
2277                 return;
2278
2279         switch (intel_crtc->pipe) {
2280         case 0:
2281                 master_priv->sarea_priv->pipeA_x = x;
2282                 master_priv->sarea_priv->pipeA_y = y;
2283                 break;
2284         case 1:
2285                 master_priv->sarea_priv->pipeB_x = x;
2286                 master_priv->sarea_priv->pipeB_y = y;
2287                 break;
2288         default:
2289                 break;
2290         }
2291 }
2292
2293 static int
2294 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2295                     struct drm_framebuffer *fb)
2296 {
2297         struct drm_device *dev = crtc->dev;
2298         struct drm_i915_private *dev_priv = dev->dev_private;
2299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300         struct drm_framebuffer *old_fb;
2301         int ret;
2302
2303         /* no fb bound */
2304         if (!fb) {
2305                 DRM_ERROR("No FB bound\n");
2306                 return 0;
2307         }
2308
2309         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2310                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311                           plane_name(intel_crtc->plane),
2312                           INTEL_INFO(dev)->num_pipes);
2313                 return -EINVAL;
2314         }
2315
2316         mutex_lock(&dev->struct_mutex);
2317         ret = intel_pin_and_fence_fb_obj(dev,
2318                                          to_intel_framebuffer(fb)->obj,
2319                                          NULL);
2320         if (ret != 0) {
2321                 mutex_unlock(&dev->struct_mutex);
2322                 DRM_ERROR("pin & fence failed\n");
2323                 return ret;
2324         }
2325
2326         /*
2327          * Update pipe size and adjust fitter if needed: the reason for this is
2328          * that in compute_mode_changes we check the native mode (not the pfit
2329          * mode) to see if we can flip rather than do a full mode set. In the
2330          * fastboot case, we'll flip, but if we don't update the pipesrc and
2331          * pfit state, we'll end up with a big fb scanned out into the wrong
2332          * sized surface.
2333          *
2334          * To fix this properly, we need to hoist the checks up into
2335          * compute_mode_changes (or above), check the actual pfit state and
2336          * whether the platform allows pfit disable with pipe active, and only
2337          * then update the pipesrc and pfit state, even on the flip path.
2338          */
2339         if (i915_fastboot) {
2340                 const struct drm_display_mode *adjusted_mode =
2341                         &intel_crtc->config.adjusted_mode;
2342
2343                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2344                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345                            (adjusted_mode->crtc_vdisplay - 1));
2346                 if (!intel_crtc->config.pch_pfit.enabled &&
2347                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352                 }
2353         }
2354
2355         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2356         if (ret) {
2357                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2358                 mutex_unlock(&dev->struct_mutex);
2359                 DRM_ERROR("failed to update base address\n");
2360                 return ret;
2361         }
2362
2363         old_fb = crtc->fb;
2364         crtc->fb = fb;
2365         crtc->x = x;
2366         crtc->y = y;
2367
2368         if (old_fb) {
2369                 if (intel_crtc->active && old_fb != fb)
2370                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2371                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2372         }
2373
2374         intel_update_fbc(dev);
2375         intel_edp_psr_update(dev);
2376         mutex_unlock(&dev->struct_mutex);
2377
2378         intel_crtc_update_sarea_pos(crtc, x, y);
2379
2380         return 0;
2381 }
2382
2383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384 {
2385         struct drm_device *dev = crtc->dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388         int pipe = intel_crtc->pipe;
2389         u32 reg, temp;
2390
2391         /* enable normal train */
2392         reg = FDI_TX_CTL(pipe);
2393         temp = I915_READ(reg);
2394         if (IS_IVYBRIDGE(dev)) {
2395                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2397         } else {
2398                 temp &= ~FDI_LINK_TRAIN_NONE;
2399                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         }
2401         I915_WRITE(reg, temp);
2402
2403         reg = FDI_RX_CTL(pipe);
2404         temp = I915_READ(reg);
2405         if (HAS_PCH_CPT(dev)) {
2406                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408         } else {
2409                 temp &= ~FDI_LINK_TRAIN_NONE;
2410                 temp |= FDI_LINK_TRAIN_NONE;
2411         }
2412         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414         /* wait one idle pattern time */
2415         POSTING_READ(reg);
2416         udelay(1000);
2417
2418         /* IVB wants error correction enabled */
2419         if (IS_IVYBRIDGE(dev))
2420                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421                            FDI_FE_ERRC_ENABLE);
2422 }
2423
2424 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2425 {
2426         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2427 }
2428
2429 static void ivb_modeset_global_resources(struct drm_device *dev)
2430 {
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         struct intel_crtc *pipe_B_crtc =
2433                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2434         struct intel_crtc *pipe_C_crtc =
2435                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2436         uint32_t temp;
2437
2438         /*
2439          * When everything is off disable fdi C so that we could enable fdi B
2440          * with all lanes. Note that we don't care about enabled pipes without
2441          * an enabled pch encoder.
2442          */
2443         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2444             !pipe_has_enabled_pch(pipe_C_crtc)) {
2445                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2446                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2447
2448                 temp = I915_READ(SOUTH_CHICKEN1);
2449                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2450                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2451                 I915_WRITE(SOUTH_CHICKEN1, temp);
2452         }
2453 }
2454
2455 /* The FDI link training functions for ILK/Ibexpeak. */
2456 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2457 {
2458         struct drm_device *dev = crtc->dev;
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461         int pipe = intel_crtc->pipe;
2462         int plane = intel_crtc->plane;
2463         u32 reg, temp, tries;
2464
2465         /* FDI needs bits from pipe & plane first */
2466         assert_pipe_enabled(dev_priv, pipe);
2467         assert_plane_enabled(dev_priv, plane);
2468
2469         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2470            for train result */
2471         reg = FDI_RX_IMR(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_RX_SYMBOL_LOCK;
2474         temp &= ~FDI_RX_BIT_LOCK;
2475         I915_WRITE(reg, temp);
2476         I915_READ(reg);
2477         udelay(150);
2478
2479         /* enable CPU FDI TX and PCH FDI RX */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_1;
2486         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2487
2488         reg = FDI_RX_CTL(pipe);
2489         temp = I915_READ(reg);
2490         temp &= ~FDI_LINK_TRAIN_NONE;
2491         temp |= FDI_LINK_TRAIN_PATTERN_1;
2492         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2493
2494         POSTING_READ(reg);
2495         udelay(150);
2496
2497         /* Ironlake workaround, enable clock pointer after FDI enable*/
2498         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2499         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2500                    FDI_RX_PHASE_SYNC_POINTER_EN);
2501
2502         reg = FDI_RX_IIR(pipe);
2503         for (tries = 0; tries < 5; tries++) {
2504                 temp = I915_READ(reg);
2505                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2506
2507                 if ((temp & FDI_RX_BIT_LOCK)) {
2508                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2509                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2510                         break;
2511                 }
2512         }
2513         if (tries == 5)
2514                 DRM_ERROR("FDI train 1 fail!\n");
2515
2516         /* Train 2 */
2517         reg = FDI_TX_CTL(pipe);
2518         temp = I915_READ(reg);
2519         temp &= ~FDI_LINK_TRAIN_NONE;
2520         temp |= FDI_LINK_TRAIN_PATTERN_2;
2521         I915_WRITE(reg, temp);
2522
2523         reg = FDI_RX_CTL(pipe);
2524         temp = I915_READ(reg);
2525         temp &= ~FDI_LINK_TRAIN_NONE;
2526         temp |= FDI_LINK_TRAIN_PATTERN_2;
2527         I915_WRITE(reg, temp);
2528
2529         POSTING_READ(reg);
2530         udelay(150);
2531
2532         reg = FDI_RX_IIR(pipe);
2533         for (tries = 0; tries < 5; tries++) {
2534                 temp = I915_READ(reg);
2535                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536
2537                 if (temp & FDI_RX_SYMBOL_LOCK) {
2538                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2540                         break;
2541                 }
2542         }
2543         if (tries == 5)
2544                 DRM_ERROR("FDI train 2 fail!\n");
2545
2546         DRM_DEBUG_KMS("FDI train done\n");
2547
2548 }
2549
2550 static const int snb_b_fdi_train_param[] = {
2551         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2552         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2553         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2554         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2555 };
2556
2557 /* The FDI link training functions for SNB/Cougarpoint. */
2558 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2559 {
2560         struct drm_device *dev = crtc->dev;
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2563         int pipe = intel_crtc->pipe;
2564         u32 reg, temp, i, retry;
2565
2566         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2567            for train result */
2568         reg = FDI_RX_IMR(pipe);
2569         temp = I915_READ(reg);
2570         temp &= ~FDI_RX_SYMBOL_LOCK;
2571         temp &= ~FDI_RX_BIT_LOCK;
2572         I915_WRITE(reg, temp);
2573
2574         POSTING_READ(reg);
2575         udelay(150);
2576
2577         /* enable CPU FDI TX and PCH FDI RX */
2578         reg = FDI_TX_CTL(pipe);
2579         temp = I915_READ(reg);
2580         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2581         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2582         temp &= ~FDI_LINK_TRAIN_NONE;
2583         temp |= FDI_LINK_TRAIN_PATTERN_1;
2584         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585         /* SNB-B */
2586         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2587         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2588
2589         I915_WRITE(FDI_RX_MISC(pipe),
2590                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2591
2592         reg = FDI_RX_CTL(pipe);
2593         temp = I915_READ(reg);
2594         if (HAS_PCH_CPT(dev)) {
2595                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2597         } else {
2598                 temp &= ~FDI_LINK_TRAIN_NONE;
2599                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600         }
2601         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603         POSTING_READ(reg);
2604         udelay(150);
2605
2606         for (i = 0; i < 4; i++) {
2607                 reg = FDI_TX_CTL(pipe);
2608                 temp = I915_READ(reg);
2609                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610                 temp |= snb_b_fdi_train_param[i];
2611                 I915_WRITE(reg, temp);
2612
2613                 POSTING_READ(reg);
2614                 udelay(500);
2615
2616                 for (retry = 0; retry < 5; retry++) {
2617                         reg = FDI_RX_IIR(pipe);
2618                         temp = I915_READ(reg);
2619                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620                         if (temp & FDI_RX_BIT_LOCK) {
2621                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2622                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2623                                 break;
2624                         }
2625                         udelay(50);
2626                 }
2627                 if (retry < 5)
2628                         break;
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 1 fail!\n");
2632
2633         /* Train 2 */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_NONE;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2;
2638         if (IS_GEN6(dev)) {
2639                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640                 /* SNB-B */
2641                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642         }
2643         I915_WRITE(reg, temp);
2644
2645         reg = FDI_RX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         if (HAS_PCH_CPT(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2650         } else {
2651                 temp &= ~FDI_LINK_TRAIN_NONE;
2652                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2653         }
2654         I915_WRITE(reg, temp);
2655
2656         POSTING_READ(reg);
2657         udelay(150);
2658
2659         for (i = 0; i < 4; i++) {
2660                 reg = FDI_TX_CTL(pipe);
2661                 temp = I915_READ(reg);
2662                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663                 temp |= snb_b_fdi_train_param[i];
2664                 I915_WRITE(reg, temp);
2665
2666                 POSTING_READ(reg);
2667                 udelay(500);
2668
2669                 for (retry = 0; retry < 5; retry++) {
2670                         reg = FDI_RX_IIR(pipe);
2671                         temp = I915_READ(reg);
2672                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673                         if (temp & FDI_RX_SYMBOL_LOCK) {
2674                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2675                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2676                                 break;
2677                         }
2678                         udelay(50);
2679                 }
2680                 if (retry < 5)
2681                         break;
2682         }
2683         if (i == 4)
2684                 DRM_ERROR("FDI train 2 fail!\n");
2685
2686         DRM_DEBUG_KMS("FDI train done.\n");
2687 }
2688
2689 /* Manual link training for Ivy Bridge A0 parts */
2690 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2691 {
2692         struct drm_device *dev = crtc->dev;
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695         int pipe = intel_crtc->pipe;
2696         u32 reg, temp, i, j;
2697
2698         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2699            for train result */
2700         reg = FDI_RX_IMR(pipe);
2701         temp = I915_READ(reg);
2702         temp &= ~FDI_RX_SYMBOL_LOCK;
2703         temp &= ~FDI_RX_BIT_LOCK;
2704         I915_WRITE(reg, temp);
2705
2706         POSTING_READ(reg);
2707         udelay(150);
2708
2709         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2710                       I915_READ(FDI_RX_IIR(pipe)));
2711
2712         /* Try each vswing and preemphasis setting twice before moving on */
2713         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2714                 /* disable first in case we need to retry */
2715                 reg = FDI_TX_CTL(pipe);
2716                 temp = I915_READ(reg);
2717                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2718                 temp &= ~FDI_TX_ENABLE;
2719                 I915_WRITE(reg, temp);
2720
2721                 reg = FDI_RX_CTL(pipe);
2722                 temp = I915_READ(reg);
2723                 temp &= ~FDI_LINK_TRAIN_AUTO;
2724                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2725                 temp &= ~FDI_RX_ENABLE;
2726                 I915_WRITE(reg, temp);
2727
2728                 /* enable CPU FDI TX and PCH FDI RX */
2729                 reg = FDI_TX_CTL(pipe);
2730                 temp = I915_READ(reg);
2731                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2732                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2733                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2734                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2735                 temp |= snb_b_fdi_train_param[j/2];
2736                 temp |= FDI_COMPOSITE_SYNC;
2737                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2738
2739                 I915_WRITE(FDI_RX_MISC(pipe),
2740                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2741
2742                 reg = FDI_RX_CTL(pipe);
2743                 temp = I915_READ(reg);
2744                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2745                 temp |= FDI_COMPOSITE_SYNC;
2746                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2747
2748                 POSTING_READ(reg);
2749                 udelay(1); /* should be 0.5us */
2750
2751                 for (i = 0; i < 4; i++) {
2752                         reg = FDI_RX_IIR(pipe);
2753                         temp = I915_READ(reg);
2754                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2755
2756                         if (temp & FDI_RX_BIT_LOCK ||
2757                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2758                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2759                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2760                                               i);
2761                                 break;
2762                         }
2763                         udelay(1); /* should be 0.5us */
2764                 }
2765                 if (i == 4) {
2766                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2767                         continue;
2768                 }
2769
2770                 /* Train 2 */
2771                 reg = FDI_TX_CTL(pipe);
2772                 temp = I915_READ(reg);
2773                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2774                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2775                 I915_WRITE(reg, temp);
2776
2777                 reg = FDI_RX_CTL(pipe);
2778                 temp = I915_READ(reg);
2779                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2780                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2781                 I915_WRITE(reg, temp);
2782
2783                 POSTING_READ(reg);
2784                 udelay(2); /* should be 1.5us */
2785
2786                 for (i = 0; i < 4; i++) {
2787                         reg = FDI_RX_IIR(pipe);
2788                         temp = I915_READ(reg);
2789                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2790
2791                         if (temp & FDI_RX_SYMBOL_LOCK ||
2792                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2793                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2794                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2795                                               i);
2796                                 goto train_done;
2797                         }
2798                         udelay(2); /* should be 1.5us */
2799                 }
2800                 if (i == 4)
2801                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2802         }
2803
2804 train_done:
2805         DRM_DEBUG_KMS("FDI train done.\n");
2806 }
2807
2808 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2809 {
2810         struct drm_device *dev = intel_crtc->base.dev;
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         int pipe = intel_crtc->pipe;
2813         u32 reg, temp;
2814
2815
2816         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2817         reg = FDI_RX_CTL(pipe);
2818         temp = I915_READ(reg);
2819         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2820         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2821         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2822         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2823
2824         POSTING_READ(reg);
2825         udelay(200);
2826
2827         /* Switch from Rawclk to PCDclk */
2828         temp = I915_READ(reg);
2829         I915_WRITE(reg, temp | FDI_PCDCLK);
2830
2831         POSTING_READ(reg);
2832         udelay(200);
2833
2834         /* Enable CPU FDI TX PLL, always on for Ironlake */
2835         reg = FDI_TX_CTL(pipe);
2836         temp = I915_READ(reg);
2837         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2839
2840                 POSTING_READ(reg);
2841                 udelay(100);
2842         }
2843 }
2844
2845 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2846 {
2847         struct drm_device *dev = intel_crtc->base.dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         int pipe = intel_crtc->pipe;
2850         u32 reg, temp;
2851
2852         /* Switch from PCDclk to Rawclk */
2853         reg = FDI_RX_CTL(pipe);
2854         temp = I915_READ(reg);
2855         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2856
2857         /* Disable CPU FDI TX PLL */
2858         reg = FDI_TX_CTL(pipe);
2859         temp = I915_READ(reg);
2860         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2861
2862         POSTING_READ(reg);
2863         udelay(100);
2864
2865         reg = FDI_RX_CTL(pipe);
2866         temp = I915_READ(reg);
2867         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2868
2869         /* Wait for the clocks to turn off. */
2870         POSTING_READ(reg);
2871         udelay(100);
2872 }
2873
2874 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2875 {
2876         struct drm_device *dev = crtc->dev;
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879         int pipe = intel_crtc->pipe;
2880         u32 reg, temp;
2881
2882         /* disable CPU FDI tx and PCH FDI rx */
2883         reg = FDI_TX_CTL(pipe);
2884         temp = I915_READ(reg);
2885         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2886         POSTING_READ(reg);
2887
2888         reg = FDI_RX_CTL(pipe);
2889         temp = I915_READ(reg);
2890         temp &= ~(0x7 << 16);
2891         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2892         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2893
2894         POSTING_READ(reg);
2895         udelay(100);
2896
2897         /* Ironlake workaround, disable clock pointer after downing FDI */
2898         if (HAS_PCH_IBX(dev)) {
2899                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2900         }
2901
2902         /* still set train pattern 1 */
2903         reg = FDI_TX_CTL(pipe);
2904         temp = I915_READ(reg);
2905         temp &= ~FDI_LINK_TRAIN_NONE;
2906         temp |= FDI_LINK_TRAIN_PATTERN_1;
2907         I915_WRITE(reg, temp);
2908
2909         reg = FDI_RX_CTL(pipe);
2910         temp = I915_READ(reg);
2911         if (HAS_PCH_CPT(dev)) {
2912                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914         } else {
2915                 temp &= ~FDI_LINK_TRAIN_NONE;
2916                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2917         }
2918         /* BPC in FDI rx is consistent with that in PIPECONF */
2919         temp &= ~(0x07 << 16);
2920         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2921         I915_WRITE(reg, temp);
2922
2923         POSTING_READ(reg);
2924         udelay(100);
2925 }
2926
2927 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2928 {
2929         struct drm_device *dev = crtc->dev;
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932         unsigned long flags;
2933         bool pending;
2934
2935         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2936             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2937                 return false;
2938
2939         spin_lock_irqsave(&dev->event_lock, flags);
2940         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2941         spin_unlock_irqrestore(&dev->event_lock, flags);
2942
2943         return pending;
2944 }
2945
2946 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2947 {
2948         struct drm_device *dev = crtc->dev;
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951         if (crtc->fb == NULL)
2952                 return;
2953
2954         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2955
2956         wait_event(dev_priv->pending_flip_queue,
2957                    !intel_crtc_has_pending_flip(crtc));
2958
2959         mutex_lock(&dev->struct_mutex);
2960         intel_finish_fb(crtc->fb);
2961         mutex_unlock(&dev->struct_mutex);
2962 }
2963
2964 /* Program iCLKIP clock to the desired frequency */
2965 static void lpt_program_iclkip(struct drm_crtc *crtc)
2966 {
2967         struct drm_device *dev = crtc->dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2970         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2971         u32 temp;
2972
2973         mutex_lock(&dev_priv->dpio_lock);
2974
2975         /* It is necessary to ungate the pixclk gate prior to programming
2976          * the divisors, and gate it back when it is done.
2977          */
2978         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2979
2980         /* Disable SSCCTL */
2981         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2982                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2983                                 SBI_SSCCTL_DISABLE,
2984                         SBI_ICLK);
2985
2986         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2987         if (clock == 20000) {
2988                 auxdiv = 1;
2989                 divsel = 0x41;
2990                 phaseinc = 0x20;
2991         } else {
2992                 /* The iCLK virtual clock root frequency is in MHz,
2993                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2994                  * divisors, it is necessary to divide one by another, so we
2995                  * convert the virtual clock precision to KHz here for higher
2996                  * precision.
2997                  */
2998                 u32 iclk_virtual_root_freq = 172800 * 1000;
2999                 u32 iclk_pi_range = 64;
3000                 u32 desired_divisor, msb_divisor_value, pi_value;
3001
3002                 desired_divisor = (iclk_virtual_root_freq / clock);
3003                 msb_divisor_value = desired_divisor / iclk_pi_range;
3004                 pi_value = desired_divisor % iclk_pi_range;
3005
3006                 auxdiv = 0;
3007                 divsel = msb_divisor_value - 2;
3008                 phaseinc = pi_value;
3009         }
3010
3011         /* This should not happen with any sane values */
3012         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3013                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3014         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3015                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3016
3017         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3018                         clock,
3019                         auxdiv,
3020                         divsel,
3021                         phasedir,
3022                         phaseinc);
3023
3024         /* Program SSCDIVINTPHASE6 */
3025         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3026         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3027         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3028         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3029         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3030         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3031         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3032         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3033
3034         /* Program SSCAUXDIV */
3035         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3036         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3037         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3038         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3039
3040         /* Enable modulator and associated divider */
3041         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3042         temp &= ~SBI_SSCCTL_DISABLE;
3043         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3044
3045         /* Wait for initialization time */
3046         udelay(24);
3047
3048         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3049
3050         mutex_unlock(&dev_priv->dpio_lock);
3051 }
3052
3053 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3054                                                 enum pipe pch_transcoder)
3055 {
3056         struct drm_device *dev = crtc->base.dev;
3057         struct drm_i915_private *dev_priv = dev->dev_private;
3058         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3059
3060         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3061                    I915_READ(HTOTAL(cpu_transcoder)));
3062         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3063                    I915_READ(HBLANK(cpu_transcoder)));
3064         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3065                    I915_READ(HSYNC(cpu_transcoder)));
3066
3067         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3068                    I915_READ(VTOTAL(cpu_transcoder)));
3069         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3070                    I915_READ(VBLANK(cpu_transcoder)));
3071         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3072                    I915_READ(VSYNC(cpu_transcoder)));
3073         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3074                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3075 }
3076
3077 /*
3078  * Enable PCH resources required for PCH ports:
3079  *   - PCH PLLs
3080  *   - FDI training & RX/TX
3081  *   - update transcoder timings
3082  *   - DP transcoding bits
3083  *   - transcoder
3084  */
3085 static void ironlake_pch_enable(struct drm_crtc *crtc)
3086 {
3087         struct drm_device *dev = crtc->dev;
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3090         int pipe = intel_crtc->pipe;
3091         u32 reg, temp;
3092
3093         assert_pch_transcoder_disabled(dev_priv, pipe);
3094
3095         /* Write the TU size bits before fdi link training, so that error
3096          * detection works. */
3097         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3098                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3099
3100         /* For PCH output, training FDI link */
3101         dev_priv->display.fdi_link_train(crtc);
3102
3103         /* We need to program the right clock selection before writing the pixel
3104          * mutliplier into the DPLL. */
3105         if (HAS_PCH_CPT(dev)) {
3106                 u32 sel;
3107
3108                 temp = I915_READ(PCH_DPLL_SEL);
3109                 temp |= TRANS_DPLL_ENABLE(pipe);
3110                 sel = TRANS_DPLLB_SEL(pipe);
3111                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3112                         temp |= sel;
3113                 else
3114                         temp &= ~sel;
3115                 I915_WRITE(PCH_DPLL_SEL, temp);
3116         }
3117
3118         /* XXX: pch pll's can be enabled any time before we enable the PCH
3119          * transcoder, and we actually should do this to not upset any PCH
3120          * transcoder that already use the clock when we share it.
3121          *
3122          * Note that enable_shared_dpll tries to do the right thing, but
3123          * get_shared_dpll unconditionally resets the pll - we need that to have
3124          * the right LVDS enable sequence. */
3125         ironlake_enable_shared_dpll(intel_crtc);
3126
3127         /* set transcoder timing, panel must allow it */
3128         assert_panel_unlocked(dev_priv, pipe);
3129         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3130
3131         intel_fdi_normal_train(crtc);
3132
3133         /* For PCH DP, enable TRANS_DP_CTL */
3134         if (HAS_PCH_CPT(dev) &&
3135             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3136              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3137                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3138                 reg = TRANS_DP_CTL(pipe);
3139                 temp = I915_READ(reg);
3140                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3141                           TRANS_DP_SYNC_MASK |
3142                           TRANS_DP_BPC_MASK);
3143                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3144                          TRANS_DP_ENH_FRAMING);
3145                 temp |= bpc << 9; /* same format but at 11:9 */
3146
3147                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3148                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3149                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3150                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3151
3152                 switch (intel_trans_dp_port_sel(crtc)) {
3153                 case PCH_DP_B:
3154                         temp |= TRANS_DP_PORT_SEL_B;
3155                         break;
3156                 case PCH_DP_C:
3157                         temp |= TRANS_DP_PORT_SEL_C;
3158                         break;
3159                 case PCH_DP_D:
3160                         temp |= TRANS_DP_PORT_SEL_D;
3161                         break;
3162                 default:
3163                         BUG();
3164                 }
3165
3166                 I915_WRITE(reg, temp);
3167         }
3168
3169         ironlake_enable_pch_transcoder(dev_priv, pipe);
3170 }
3171
3172 static void lpt_pch_enable(struct drm_crtc *crtc)
3173 {
3174         struct drm_device *dev = crtc->dev;
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3178
3179         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3180
3181         lpt_program_iclkip(crtc);
3182
3183         /* Set transcoder timing. */
3184         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3185
3186         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3187 }
3188
3189 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3190 {
3191         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3192
3193         if (pll == NULL)
3194                 return;
3195
3196         if (pll->refcount == 0) {
3197                 WARN(1, "bad %s refcount\n", pll->name);
3198                 return;
3199         }
3200
3201         if (--pll->refcount == 0) {
3202                 WARN_ON(pll->on);
3203                 WARN_ON(pll->active);
3204         }
3205
3206         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3207 }
3208
3209 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3210 {
3211         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3212         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3213         enum intel_dpll_id i;
3214
3215         if (pll) {
3216                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3217                               crtc->base.base.id, pll->name);
3218                 intel_put_shared_dpll(crtc);
3219         }
3220
3221         if (HAS_PCH_IBX(dev_priv->dev)) {
3222                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3223                 i = (enum intel_dpll_id) crtc->pipe;
3224                 pll = &dev_priv->shared_dplls[i];
3225
3226                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3227                               crtc->base.base.id, pll->name);
3228
3229                 goto found;
3230         }
3231
3232         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3233                 pll = &dev_priv->shared_dplls[i];
3234
3235                 /* Only want to check enabled timings first */
3236                 if (pll->refcount == 0)
3237                         continue;
3238
3239                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3240                            sizeof(pll->hw_state)) == 0) {
3241                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3242                                       crtc->base.base.id,
3243                                       pll->name, pll->refcount, pll->active);
3244
3245                         goto found;
3246                 }
3247         }
3248
3249         /* Ok no matching timings, maybe there's a free one? */
3250         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3251                 pll = &dev_priv->shared_dplls[i];
3252                 if (pll->refcount == 0) {
3253                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3254                                       crtc->base.base.id, pll->name);
3255                         goto found;
3256                 }
3257         }
3258
3259         return NULL;
3260
3261 found:
3262         crtc->config.shared_dpll = i;
3263         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3264                          pipe_name(crtc->pipe));
3265
3266         if (pll->active == 0) {
3267                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3268                        sizeof(pll->hw_state));
3269
3270                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3271                 WARN_ON(pll->on);
3272                 assert_shared_dpll_disabled(dev_priv, pll);
3273
3274                 pll->mode_set(dev_priv, pll);
3275         }
3276         pll->refcount++;
3277
3278         return pll;
3279 }
3280
3281 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3282 {
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         int dslreg = PIPEDSL(pipe);
3285         u32 temp;
3286
3287         temp = I915_READ(dslreg);
3288         udelay(500);
3289         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3290                 if (wait_for(I915_READ(dslreg) != temp, 5))
3291                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3292         }
3293 }
3294
3295 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3296 {
3297         struct drm_device *dev = crtc->base.dev;
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299         int pipe = crtc->pipe;
3300
3301         if (crtc->config.pch_pfit.enabled) {
3302                 /* Force use of hard-coded filter coefficients
3303                  * as some pre-programmed values are broken,
3304                  * e.g. x201.
3305                  */
3306                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3307                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3308                                                  PF_PIPE_SEL_IVB(pipe));
3309                 else
3310                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3311                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3312                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3313         }
3314 }
3315
3316 static void intel_enable_planes(struct drm_crtc *crtc)
3317 {
3318         struct drm_device *dev = crtc->dev;
3319         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3320         struct intel_plane *intel_plane;
3321
3322         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3323                 if (intel_plane->pipe == pipe)
3324                         intel_plane_restore(&intel_plane->base);
3325 }
3326
3327 static void intel_disable_planes(struct drm_crtc *crtc)
3328 {
3329         struct drm_device *dev = crtc->dev;
3330         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3331         struct intel_plane *intel_plane;
3332
3333         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3334                 if (intel_plane->pipe == pipe)
3335                         intel_plane_disable(&intel_plane->base);
3336 }
3337
3338 void hsw_enable_ips(struct intel_crtc *crtc)
3339 {
3340         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3341
3342         if (!crtc->config.ips_enabled)
3343                 return;
3344
3345         /* We can only enable IPS after we enable a plane and wait for a vblank.
3346          * We guarantee that the plane is enabled by calling intel_enable_ips
3347          * only after intel_enable_plane. And intel_enable_plane already waits
3348          * for a vblank, so all we need to do here is to enable the IPS bit. */
3349         assert_plane_enabled(dev_priv, crtc->plane);
3350         I915_WRITE(IPS_CTL, IPS_ENABLE);
3351
3352         /* The bit only becomes 1 in the next vblank, so this wait here is
3353          * essentially intel_wait_for_vblank. If we don't have this and don't
3354          * wait for vblanks until the end of crtc_enable, then the HW state
3355          * readout code will complain that the expected IPS_CTL value is not the
3356          * one we read. */
3357         if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3358                 DRM_ERROR("Timed out waiting for IPS enable\n");
3359 }
3360
3361 void hsw_disable_ips(struct intel_crtc *crtc)
3362 {
3363         struct drm_device *dev = crtc->base.dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366         if (!crtc->config.ips_enabled)
3367                 return;
3368
3369         assert_plane_enabled(dev_priv, crtc->plane);
3370         I915_WRITE(IPS_CTL, 0);
3371         POSTING_READ(IPS_CTL);
3372
3373         /* We need to wait for a vblank before we can disable the plane. */
3374         intel_wait_for_vblank(dev, crtc->pipe);
3375 }
3376
3377 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3378 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383         enum pipe pipe = intel_crtc->pipe;
3384         int palreg = PALETTE(pipe);
3385         int i;
3386         bool reenable_ips = false;
3387
3388         /* The clocks have to be on to load the palette. */
3389         if (!crtc->enabled || !intel_crtc->active)
3390                 return;
3391
3392         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3393                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3394                         assert_dsi_pll_enabled(dev_priv);
3395                 else
3396                         assert_pll_enabled(dev_priv, pipe);
3397         }
3398
3399         /* use legacy palette for Ironlake */
3400         if (HAS_PCH_SPLIT(dev))
3401                 palreg = LGC_PALETTE(pipe);
3402
3403         /* Workaround : Do not read or write the pipe palette/gamma data while
3404          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3405          */
3406         if (intel_crtc->config.ips_enabled &&
3407             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3408              GAMMA_MODE_MODE_SPLIT)) {
3409                 hsw_disable_ips(intel_crtc);
3410                 reenable_ips = true;
3411         }
3412
3413         for (i = 0; i < 256; i++) {
3414                 I915_WRITE(palreg + 4 * i,
3415                            (intel_crtc->lut_r[i] << 16) |
3416                            (intel_crtc->lut_g[i] << 8) |
3417                            intel_crtc->lut_b[i]);
3418         }
3419
3420         if (reenable_ips)
3421                 hsw_enable_ips(intel_crtc);
3422 }
3423
3424 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3425 {
3426         struct drm_device *dev = crtc->dev;
3427         struct drm_i915_private *dev_priv = dev->dev_private;
3428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429         struct intel_encoder *encoder;
3430         int pipe = intel_crtc->pipe;
3431         int plane = intel_crtc->plane;
3432
3433         WARN_ON(!crtc->enabled);
3434
3435         if (intel_crtc->active)
3436                 return;
3437
3438         intel_crtc->active = true;
3439
3440         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3441         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3442
3443         for_each_encoder_on_crtc(dev, crtc, encoder)
3444                 if (encoder->pre_enable)
3445                         encoder->pre_enable(encoder);
3446
3447         if (intel_crtc->config.has_pch_encoder) {
3448                 /* Note: FDI PLL enabling _must_ be done before we enable the
3449                  * cpu pipes, hence this is separate from all the other fdi/pch
3450                  * enabling. */
3451                 ironlake_fdi_pll_enable(intel_crtc);
3452         } else {
3453                 assert_fdi_tx_disabled(dev_priv, pipe);
3454                 assert_fdi_rx_disabled(dev_priv, pipe);
3455         }
3456
3457         ironlake_pfit_enable(intel_crtc);
3458
3459         /*
3460          * On ILK+ LUT must be loaded before the pipe is running but with
3461          * clocks enabled
3462          */
3463         intel_crtc_load_lut(crtc);
3464
3465         intel_update_watermarks(crtc);
3466         intel_enable_pipe(dev_priv, pipe,
3467                           intel_crtc->config.has_pch_encoder, false);
3468         intel_enable_primary_plane(dev_priv, plane, pipe);
3469         intel_enable_planes(crtc);
3470         intel_crtc_update_cursor(crtc, true);
3471
3472         if (intel_crtc->config.has_pch_encoder)
3473                 ironlake_pch_enable(crtc);
3474
3475         mutex_lock(&dev->struct_mutex);
3476         intel_update_fbc(dev);
3477         mutex_unlock(&dev->struct_mutex);
3478
3479         for_each_encoder_on_crtc(dev, crtc, encoder)
3480                 encoder->enable(encoder);
3481
3482         if (HAS_PCH_CPT(dev))
3483                 cpt_verify_modeset(dev, intel_crtc->pipe);
3484
3485         /*
3486          * There seems to be a race in PCH platform hw (at least on some
3487          * outputs) where an enabled pipe still completes any pageflip right
3488          * away (as if the pipe is off) instead of waiting for vblank. As soon
3489          * as the first vblank happend, everything works as expected. Hence just
3490          * wait for one vblank before returning to avoid strange things
3491          * happening.
3492          */
3493         intel_wait_for_vblank(dev, intel_crtc->pipe);
3494 }
3495
3496 /* IPS only exists on ULT machines and is tied to pipe A. */
3497 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3498 {
3499         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3500 }
3501
3502 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         int pipe = intel_crtc->pipe;
3508         int plane = intel_crtc->plane;
3509
3510         intel_enable_primary_plane(dev_priv, plane, pipe);
3511         intel_enable_planes(crtc);
3512         intel_crtc_update_cursor(crtc, true);
3513
3514         hsw_enable_ips(intel_crtc);
3515
3516         mutex_lock(&dev->struct_mutex);
3517         intel_update_fbc(dev);
3518         mutex_unlock(&dev->struct_mutex);
3519 }
3520
3521 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3522 {
3523         struct drm_device *dev = crtc->dev;
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526         int pipe = intel_crtc->pipe;
3527         int plane = intel_crtc->plane;
3528
3529         intel_crtc_wait_for_pending_flips(crtc);
3530         drm_vblank_off(dev, pipe);
3531
3532         /* FBC must be disabled before disabling the plane on HSW. */
3533         if (dev_priv->fbc.plane == plane)
3534                 intel_disable_fbc(dev);
3535
3536         hsw_disable_ips(intel_crtc);
3537
3538         intel_crtc_update_cursor(crtc, false);
3539         intel_disable_planes(crtc);
3540         intel_disable_primary_plane(dev_priv, plane, pipe);
3541 }
3542
3543 /*
3544  * This implements the workaround described in the "notes" section of the mode
3545  * set sequence documentation. When going from no pipes or single pipe to
3546  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3547  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3548  */
3549 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3550 {
3551         struct drm_device *dev = crtc->base.dev;
3552         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3553
3554         /* We want to get the other_active_crtc only if there's only 1 other
3555          * active crtc. */
3556         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3557                 if (!crtc_it->active || crtc_it == crtc)
3558                         continue;
3559
3560                 if (other_active_crtc)
3561                         return;
3562
3563                 other_active_crtc = crtc_it;
3564         }
3565         if (!other_active_crtc)
3566                 return;
3567
3568         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3569         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3570 }
3571
3572 static void haswell_crtc_enable(struct drm_crtc *crtc)
3573 {
3574         struct drm_device *dev = crtc->dev;
3575         struct drm_i915_private *dev_priv = dev->dev_private;
3576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3577         struct intel_encoder *encoder;
3578         int pipe = intel_crtc->pipe;
3579
3580         WARN_ON(!crtc->enabled);
3581
3582         if (intel_crtc->active)
3583                 return;
3584
3585         intel_crtc->active = true;
3586
3587         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3588         if (intel_crtc->config.has_pch_encoder)
3589                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3590
3591         if (intel_crtc->config.has_pch_encoder)
3592                 dev_priv->display.fdi_link_train(crtc);
3593
3594         for_each_encoder_on_crtc(dev, crtc, encoder)
3595                 if (encoder->pre_enable)
3596                         encoder->pre_enable(encoder);
3597
3598         intel_ddi_enable_pipe_clock(intel_crtc);
3599
3600         ironlake_pfit_enable(intel_crtc);
3601
3602         /*
3603          * On ILK+ LUT must be loaded before the pipe is running but with
3604          * clocks enabled
3605          */
3606         intel_crtc_load_lut(crtc);
3607
3608         intel_ddi_set_pipe_settings(crtc);
3609         intel_ddi_enable_transcoder_func(crtc);
3610
3611         intel_update_watermarks(crtc);
3612         intel_enable_pipe(dev_priv, pipe,
3613                           intel_crtc->config.has_pch_encoder, false);
3614
3615         if (intel_crtc->config.has_pch_encoder)
3616                 lpt_pch_enable(crtc);
3617
3618         for_each_encoder_on_crtc(dev, crtc, encoder) {
3619                 encoder->enable(encoder);
3620                 intel_opregion_notify_encoder(encoder, true);
3621         }
3622
3623         /* If we change the relative order between pipe/planes enabling, we need
3624          * to change the workaround. */
3625         haswell_mode_set_planes_workaround(intel_crtc);
3626         haswell_crtc_enable_planes(crtc);
3627
3628         /*
3629          * There seems to be a race in PCH platform hw (at least on some
3630          * outputs) where an enabled pipe still completes any pageflip right
3631          * away (as if the pipe is off) instead of waiting for vblank. As soon
3632          * as the first vblank happend, everything works as expected. Hence just
3633          * wait for one vblank before returning to avoid strange things
3634          * happening.
3635          */
3636         intel_wait_for_vblank(dev, intel_crtc->pipe);
3637 }
3638
3639 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->base.dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         int pipe = crtc->pipe;
3644
3645         /* To avoid upsetting the power well on haswell only disable the pfit if
3646          * it's in use. The hw state code will make sure we get this right. */
3647         if (crtc->config.pch_pfit.enabled) {
3648                 I915_WRITE(PF_CTL(pipe), 0);
3649                 I915_WRITE(PF_WIN_POS(pipe), 0);
3650                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3651         }
3652 }
3653
3654 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3655 {
3656         struct drm_device *dev = crtc->dev;
3657         struct drm_i915_private *dev_priv = dev->dev_private;
3658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3659         struct intel_encoder *encoder;
3660         int pipe = intel_crtc->pipe;
3661         int plane = intel_crtc->plane;
3662         u32 reg, temp;
3663
3664
3665         if (!intel_crtc->active)
3666                 return;
3667
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 encoder->disable(encoder);
3670
3671         intel_crtc_wait_for_pending_flips(crtc);
3672         drm_vblank_off(dev, pipe);
3673
3674         if (dev_priv->fbc.plane == plane)
3675                 intel_disable_fbc(dev);
3676
3677         intel_crtc_update_cursor(crtc, false);
3678         intel_disable_planes(crtc);
3679         intel_disable_primary_plane(dev_priv, plane, pipe);
3680
3681         if (intel_crtc->config.has_pch_encoder)
3682                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3683
3684         intel_disable_pipe(dev_priv, pipe);
3685
3686         ironlake_pfit_disable(intel_crtc);
3687
3688         for_each_encoder_on_crtc(dev, crtc, encoder)
3689                 if (encoder->post_disable)
3690                         encoder->post_disable(encoder);
3691
3692         if (intel_crtc->config.has_pch_encoder) {
3693                 ironlake_fdi_disable(crtc);
3694
3695                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3696                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3697
3698                 if (HAS_PCH_CPT(dev)) {
3699                         /* disable TRANS_DP_CTL */
3700                         reg = TRANS_DP_CTL(pipe);
3701                         temp = I915_READ(reg);
3702                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3703                                   TRANS_DP_PORT_SEL_MASK);
3704                         temp |= TRANS_DP_PORT_SEL_NONE;
3705                         I915_WRITE(reg, temp);
3706
3707                         /* disable DPLL_SEL */
3708                         temp = I915_READ(PCH_DPLL_SEL);
3709                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3710                         I915_WRITE(PCH_DPLL_SEL, temp);
3711                 }
3712
3713                 /* disable PCH DPLL */
3714                 intel_disable_shared_dpll(intel_crtc);
3715
3716                 ironlake_fdi_pll_disable(intel_crtc);
3717         }
3718
3719         intel_crtc->active = false;
3720         intel_update_watermarks(crtc);
3721
3722         mutex_lock(&dev->struct_mutex);
3723         intel_update_fbc(dev);
3724         mutex_unlock(&dev->struct_mutex);
3725 }
3726
3727 static void haswell_crtc_disable(struct drm_crtc *crtc)
3728 {
3729         struct drm_device *dev = crtc->dev;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3732         struct intel_encoder *encoder;
3733         int pipe = intel_crtc->pipe;
3734         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3735
3736         if (!intel_crtc->active)
3737                 return;
3738
3739         haswell_crtc_disable_planes(crtc);
3740
3741         for_each_encoder_on_crtc(dev, crtc, encoder) {
3742                 intel_opregion_notify_encoder(encoder, false);
3743                 encoder->disable(encoder);
3744         }
3745
3746         if (intel_crtc->config.has_pch_encoder)
3747                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3748         intel_disable_pipe(dev_priv, pipe);
3749
3750         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3751
3752         ironlake_pfit_disable(intel_crtc);
3753
3754         intel_ddi_disable_pipe_clock(intel_crtc);
3755
3756         for_each_encoder_on_crtc(dev, crtc, encoder)
3757                 if (encoder->post_disable)
3758                         encoder->post_disable(encoder);
3759
3760         if (intel_crtc->config.has_pch_encoder) {
3761                 lpt_disable_pch_transcoder(dev_priv);
3762                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3763                 intel_ddi_fdi_disable(crtc);
3764         }
3765
3766         intel_crtc->active = false;
3767         intel_update_watermarks(crtc);
3768
3769         mutex_lock(&dev->struct_mutex);
3770         intel_update_fbc(dev);
3771         mutex_unlock(&dev->struct_mutex);
3772 }
3773
3774 static void ironlake_crtc_off(struct drm_crtc *crtc)
3775 {
3776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777         intel_put_shared_dpll(intel_crtc);
3778 }
3779
3780 static void haswell_crtc_off(struct drm_crtc *crtc)
3781 {
3782         intel_ddi_put_crtc_pll(crtc);
3783 }
3784
3785 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3786 {
3787         if (!enable && intel_crtc->overlay) {
3788                 struct drm_device *dev = intel_crtc->base.dev;
3789                 struct drm_i915_private *dev_priv = dev->dev_private;
3790
3791                 mutex_lock(&dev->struct_mutex);
3792                 dev_priv->mm.interruptible = false;
3793                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3794                 dev_priv->mm.interruptible = true;
3795                 mutex_unlock(&dev->struct_mutex);
3796         }
3797
3798         /* Let userspace switch the overlay on again. In most cases userspace
3799          * has to recompute where to put it anyway.
3800          */
3801 }
3802
3803 /**
3804  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3805  * cursor plane briefly if not already running after enabling the display
3806  * plane.
3807  * This workaround avoids occasional blank screens when self refresh is
3808  * enabled.
3809  */
3810 static void
3811 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3812 {
3813         u32 cntl = I915_READ(CURCNTR(pipe));
3814
3815         if ((cntl & CURSOR_MODE) == 0) {
3816                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3817
3818                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3819                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3820                 intel_wait_for_vblank(dev_priv->dev, pipe);
3821                 I915_WRITE(CURCNTR(pipe), cntl);
3822                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3823                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3824         }
3825 }
3826
3827 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3828 {
3829         struct drm_device *dev = crtc->base.dev;
3830         struct drm_i915_private *dev_priv = dev->dev_private;
3831         struct intel_crtc_config *pipe_config = &crtc->config;
3832
3833         if (!crtc->config.gmch_pfit.control)
3834                 return;
3835
3836         /*
3837          * The panel fitter should only be adjusted whilst the pipe is disabled,
3838          * according to register description and PRM.
3839          */
3840         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3841         assert_pipe_disabled(dev_priv, crtc->pipe);
3842
3843         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3844         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3845
3846         /* Border color in case we don't scale up to the full screen. Black by
3847          * default, change to something else for debugging. */
3848         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3849 }
3850
3851 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3852 {
3853         struct drm_device *dev = crtc->dev;
3854         struct drm_i915_private *dev_priv = dev->dev_private;
3855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856         struct intel_encoder *encoder;
3857         int pipe = intel_crtc->pipe;
3858         int plane = intel_crtc->plane;
3859         bool is_dsi;
3860
3861         WARN_ON(!crtc->enabled);
3862
3863         if (intel_crtc->active)
3864                 return;
3865
3866         intel_crtc->active = true;
3867
3868         for_each_encoder_on_crtc(dev, crtc, encoder)
3869                 if (encoder->pre_pll_enable)
3870                         encoder->pre_pll_enable(encoder);
3871
3872         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3873
3874         if (!is_dsi)
3875                 vlv_enable_pll(intel_crtc);
3876
3877         for_each_encoder_on_crtc(dev, crtc, encoder)
3878                 if (encoder->pre_enable)
3879                         encoder->pre_enable(encoder);
3880
3881         i9xx_pfit_enable(intel_crtc);
3882
3883         intel_crtc_load_lut(crtc);
3884
3885         intel_update_watermarks(crtc);
3886         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3887         intel_enable_primary_plane(dev_priv, plane, pipe);
3888         intel_enable_planes(crtc);
3889         intel_crtc_update_cursor(crtc, true);
3890
3891         intel_update_fbc(dev);
3892
3893         for_each_encoder_on_crtc(dev, crtc, encoder)
3894                 encoder->enable(encoder);
3895 }
3896
3897 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3898 {
3899         struct drm_device *dev = crtc->dev;
3900         struct drm_i915_private *dev_priv = dev->dev_private;
3901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902         struct intel_encoder *encoder;
3903         int pipe = intel_crtc->pipe;
3904         int plane = intel_crtc->plane;
3905
3906         WARN_ON(!crtc->enabled);
3907
3908         if (intel_crtc->active)
3909                 return;
3910
3911         intel_crtc->active = true;
3912
3913         for_each_encoder_on_crtc(dev, crtc, encoder)
3914                 if (encoder->pre_enable)
3915                         encoder->pre_enable(encoder);
3916
3917         i9xx_enable_pll(intel_crtc);
3918
3919         i9xx_pfit_enable(intel_crtc);
3920
3921         intel_crtc_load_lut(crtc);
3922
3923         intel_update_watermarks(crtc);
3924         intel_enable_pipe(dev_priv, pipe, false, false);
3925         intel_enable_primary_plane(dev_priv, plane, pipe);
3926         intel_enable_planes(crtc);
3927         /* The fixup needs to happen before cursor is enabled */
3928         if (IS_G4X(dev))
3929                 g4x_fixup_plane(dev_priv, pipe);
3930         intel_crtc_update_cursor(crtc, true);
3931
3932         /* Give the overlay scaler a chance to enable if it's on this pipe */
3933         intel_crtc_dpms_overlay(intel_crtc, true);
3934
3935         intel_update_fbc(dev);
3936
3937         for_each_encoder_on_crtc(dev, crtc, encoder)
3938                 encoder->enable(encoder);
3939 }
3940
3941 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3942 {
3943         struct drm_device *dev = crtc->base.dev;
3944         struct drm_i915_private *dev_priv = dev->dev_private;
3945
3946         if (!crtc->config.gmch_pfit.control)
3947                 return;
3948
3949         assert_pipe_disabled(dev_priv, crtc->pipe);
3950
3951         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3952                          I915_READ(PFIT_CONTROL));
3953         I915_WRITE(PFIT_CONTROL, 0);
3954 }
3955
3956 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961         struct intel_encoder *encoder;
3962         int pipe = intel_crtc->pipe;
3963         int plane = intel_crtc->plane;
3964
3965         if (!intel_crtc->active)
3966                 return;
3967
3968         for_each_encoder_on_crtc(dev, crtc, encoder)
3969                 encoder->disable(encoder);
3970
3971         /* Give the overlay scaler a chance to disable if it's on this pipe */
3972         intel_crtc_wait_for_pending_flips(crtc);
3973         drm_vblank_off(dev, pipe);
3974
3975         if (dev_priv->fbc.plane == plane)
3976                 intel_disable_fbc(dev);
3977
3978         intel_crtc_dpms_overlay(intel_crtc, false);
3979         intel_crtc_update_cursor(crtc, false);
3980         intel_disable_planes(crtc);
3981         intel_disable_primary_plane(dev_priv, plane, pipe);
3982
3983         intel_disable_pipe(dev_priv, pipe);
3984
3985         i9xx_pfit_disable(intel_crtc);
3986
3987         for_each_encoder_on_crtc(dev, crtc, encoder)
3988                 if (encoder->post_disable)
3989                         encoder->post_disable(encoder);
3990
3991         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3992                 vlv_disable_pll(dev_priv, pipe);
3993         else if (!IS_VALLEYVIEW(dev))
3994                 i9xx_disable_pll(dev_priv, pipe);
3995
3996         intel_crtc->active = false;
3997         intel_update_watermarks(crtc);
3998
3999         intel_update_fbc(dev);
4000 }
4001
4002 static void i9xx_crtc_off(struct drm_crtc *crtc)
4003 {
4004 }
4005
4006 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4007                                     bool enabled)
4008 {
4009         struct drm_device *dev = crtc->dev;
4010         struct drm_i915_master_private *master_priv;
4011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4012         int pipe = intel_crtc->pipe;
4013
4014         if (!dev->primary->master)
4015                 return;
4016
4017         master_priv = dev->primary->master->driver_priv;
4018         if (!master_priv->sarea_priv)
4019                 return;
4020
4021         switch (pipe) {
4022         case 0:
4023                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4024                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4025                 break;
4026         case 1:
4027                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4028                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4029                 break;
4030         default:
4031                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4032                 break;
4033         }
4034 }
4035
4036 /**
4037  * Sets the power management mode of the pipe and plane.
4038  */
4039 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4040 {
4041         struct drm_device *dev = crtc->dev;
4042         struct drm_i915_private *dev_priv = dev->dev_private;
4043         struct intel_encoder *intel_encoder;
4044         bool enable = false;
4045
4046         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4047                 enable |= intel_encoder->connectors_active;
4048
4049         if (enable)
4050                 dev_priv->display.crtc_enable(crtc);
4051         else
4052                 dev_priv->display.crtc_disable(crtc);
4053
4054         intel_crtc_update_sarea(crtc, enable);
4055 }
4056
4057 static void intel_crtc_disable(struct drm_crtc *crtc)
4058 {
4059         struct drm_device *dev = crtc->dev;
4060         struct drm_connector *connector;
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063
4064         /* crtc should still be enabled when we disable it. */
4065         WARN_ON(!crtc->enabled);
4066
4067         dev_priv->display.crtc_disable(crtc);
4068         intel_crtc->eld_vld = false;
4069         intel_crtc_update_sarea(crtc, false);
4070         dev_priv->display.off(crtc);
4071
4072         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4073         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4074         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4075
4076         if (crtc->fb) {
4077                 mutex_lock(&dev->struct_mutex);
4078                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4079                 mutex_unlock(&dev->struct_mutex);
4080                 crtc->fb = NULL;
4081         }
4082
4083         /* Update computed state. */
4084         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4085                 if (!connector->encoder || !connector->encoder->crtc)
4086                         continue;
4087
4088                 if (connector->encoder->crtc != crtc)
4089                         continue;
4090
4091                 connector->dpms = DRM_MODE_DPMS_OFF;
4092                 to_intel_encoder(connector->encoder)->connectors_active = false;
4093         }
4094 }
4095
4096 void intel_encoder_destroy(struct drm_encoder *encoder)
4097 {
4098         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4099
4100         drm_encoder_cleanup(encoder);
4101         kfree(intel_encoder);
4102 }
4103
4104 /* Simple dpms helper for encoders with just one connector, no cloning and only
4105  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4106  * state of the entire output pipe. */
4107 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4108 {
4109         if (mode == DRM_MODE_DPMS_ON) {
4110                 encoder->connectors_active = true;
4111
4112                 intel_crtc_update_dpms(encoder->base.crtc);
4113         } else {
4114                 encoder->connectors_active = false;
4115
4116                 intel_crtc_update_dpms(encoder->base.crtc);
4117         }
4118 }
4119
4120 /* Cross check the actual hw state with our own modeset state tracking (and it's
4121  * internal consistency). */
4122 static void intel_connector_check_state(struct intel_connector *connector)
4123 {
4124         if (connector->get_hw_state(connector)) {
4125                 struct intel_encoder *encoder = connector->encoder;
4126                 struct drm_crtc *crtc;
4127                 bool encoder_enabled;
4128                 enum pipe pipe;
4129
4130                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4131                               connector->base.base.id,
4132                               drm_get_connector_name(&connector->base));
4133
4134                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4135                      "wrong connector dpms state\n");
4136                 WARN(connector->base.encoder != &encoder->base,
4137                      "active connector not linked to encoder\n");
4138                 WARN(!encoder->connectors_active,
4139                      "encoder->connectors_active not set\n");
4140
4141                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4142                 WARN(!encoder_enabled, "encoder not enabled\n");
4143                 if (WARN_ON(!encoder->base.crtc))
4144                         return;
4145
4146                 crtc = encoder->base.crtc;
4147
4148                 WARN(!crtc->enabled, "crtc not enabled\n");
4149                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4150                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4151                      "encoder active on the wrong pipe\n");
4152         }
4153 }
4154
4155 /* Even simpler default implementation, if there's really no special case to
4156  * consider. */
4157 void intel_connector_dpms(struct drm_connector *connector, int mode)
4158 {
4159         /* All the simple cases only support two dpms states. */
4160         if (mode != DRM_MODE_DPMS_ON)
4161                 mode = DRM_MODE_DPMS_OFF;
4162
4163         if (mode == connector->dpms)
4164                 return;
4165
4166         connector->dpms = mode;
4167
4168         /* Only need to change hw state when actually enabled */
4169         if (connector->encoder)
4170                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4171
4172         intel_modeset_check_state(connector->dev);
4173 }
4174
4175 /* Simple connector->get_hw_state implementation for encoders that support only
4176  * one connector and no cloning and hence the encoder state determines the state
4177  * of the connector. */
4178 bool intel_connector_get_hw_state(struct intel_connector *connector)
4179 {
4180         enum pipe pipe = 0;
4181         struct intel_encoder *encoder = connector->encoder;
4182
4183         return encoder->get_hw_state(encoder, &pipe);
4184 }
4185
4186 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4187                                      struct intel_crtc_config *pipe_config)
4188 {
4189         struct drm_i915_private *dev_priv = dev->dev_private;
4190         struct intel_crtc *pipe_B_crtc =
4191                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4192
4193         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4194                       pipe_name(pipe), pipe_config->fdi_lanes);
4195         if (pipe_config->fdi_lanes > 4) {
4196                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4197                               pipe_name(pipe), pipe_config->fdi_lanes);
4198                 return false;
4199         }
4200
4201         if (IS_HASWELL(dev)) {
4202                 if (pipe_config->fdi_lanes > 2) {
4203                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4204                                       pipe_config->fdi_lanes);
4205                         return false;
4206                 } else {
4207                         return true;
4208                 }
4209         }
4210
4211         if (INTEL_INFO(dev)->num_pipes == 2)
4212                 return true;
4213
4214         /* Ivybridge 3 pipe is really complicated */
4215         switch (pipe) {
4216         case PIPE_A:
4217                 return true;
4218         case PIPE_B:
4219                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4220                     pipe_config->fdi_lanes > 2) {
4221                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4222                                       pipe_name(pipe), pipe_config->fdi_lanes);
4223                         return false;
4224                 }
4225                 return true;
4226         case PIPE_C:
4227                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4228                     pipe_B_crtc->config.fdi_lanes <= 2) {
4229                         if (pipe_config->fdi_lanes > 2) {
4230                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4231                                               pipe_name(pipe), pipe_config->fdi_lanes);
4232                                 return false;
4233                         }
4234                 } else {
4235                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4236                         return false;
4237                 }
4238                 return true;
4239         default:
4240                 BUG();
4241         }
4242 }
4243
4244 #define RETRY 1
4245 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4246                                        struct intel_crtc_config *pipe_config)
4247 {
4248         struct drm_device *dev = intel_crtc->base.dev;
4249         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4250         int lane, link_bw, fdi_dotclock;
4251         bool setup_ok, needs_recompute = false;
4252
4253 retry:
4254         /* FDI is a binary signal running at ~2.7GHz, encoding
4255          * each output octet as 10 bits. The actual frequency
4256          * is stored as a divider into a 100MHz clock, and the
4257          * mode pixel clock is stored in units of 1KHz.
4258          * Hence the bw of each lane in terms of the mode signal
4259          * is:
4260          */
4261         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4262
4263         fdi_dotclock = adjusted_mode->crtc_clock;
4264
4265         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4266                                            pipe_config->pipe_bpp);
4267
4268         pipe_config->fdi_lanes = lane;
4269
4270         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4271                                link_bw, &pipe_config->fdi_m_n);
4272
4273         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4274                                             intel_crtc->pipe, pipe_config);
4275         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4276                 pipe_config->pipe_bpp -= 2*3;
4277                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4278                               pipe_config->pipe_bpp);
4279                 needs_recompute = true;
4280                 pipe_config->bw_constrained = true;
4281
4282                 goto retry;
4283         }
4284
4285         if (needs_recompute)
4286                 return RETRY;
4287
4288         return setup_ok ? 0 : -EINVAL;
4289 }
4290
4291 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4292                                    struct intel_crtc_config *pipe_config)
4293 {
4294         pipe_config->ips_enabled = i915_enable_ips &&
4295                                    hsw_crtc_supports_ips(crtc) &&
4296                                    pipe_config->pipe_bpp <= 24;
4297 }
4298
4299 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4300                                      struct intel_crtc_config *pipe_config)
4301 {
4302         struct drm_device *dev = crtc->base.dev;
4303         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4304
4305         /* FIXME should check pixel clock limits on all platforms */
4306         if (INTEL_INFO(dev)->gen < 4) {
4307                 struct drm_i915_private *dev_priv = dev->dev_private;
4308                 int clock_limit =
4309                         dev_priv->display.get_display_clock_speed(dev);
4310
4311                 /*
4312                  * Enable pixel doubling when the dot clock
4313                  * is > 90% of the (display) core speed.
4314                  *
4315                  * GDG double wide on either pipe,
4316                  * otherwise pipe A only.
4317                  */
4318                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4319                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4320                         clock_limit *= 2;
4321                         pipe_config->double_wide = true;
4322                 }
4323
4324                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4325                         return -EINVAL;
4326         }
4327
4328         /*
4329          * Pipe horizontal size must be even in:
4330          * - DVO ganged mode
4331          * - LVDS dual channel mode
4332          * - Double wide pipe
4333          */
4334         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4335              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4336                 pipe_config->pipe_src_w &= ~1;
4337
4338         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4339          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4340          */
4341         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4342                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4343                 return -EINVAL;
4344
4345         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4346                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4347         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4348                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4349                  * for lvds. */
4350                 pipe_config->pipe_bpp = 8*3;
4351         }
4352
4353         if (HAS_IPS(dev))
4354                 hsw_compute_ips_config(crtc, pipe_config);
4355
4356         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4357          * clock survives for now. */
4358         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4359                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4360
4361         if (pipe_config->has_pch_encoder)
4362                 return ironlake_fdi_compute_config(crtc, pipe_config);
4363
4364         return 0;
4365 }
4366
4367 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4368 {
4369         return 400000; /* FIXME */
4370 }
4371
4372 static int i945_get_display_clock_speed(struct drm_device *dev)
4373 {
4374         return 400000;
4375 }
4376
4377 static int i915_get_display_clock_speed(struct drm_device *dev)
4378 {
4379         return 333000;
4380 }
4381
4382 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4383 {
4384         return 200000;
4385 }
4386
4387 static int pnv_get_display_clock_speed(struct drm_device *dev)
4388 {
4389         u16 gcfgc = 0;
4390
4391         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4392
4393         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4394         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4395                 return 267000;
4396         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4397                 return 333000;
4398         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4399                 return 444000;
4400         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4401                 return 200000;
4402         default:
4403                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4404         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4405                 return 133000;
4406         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4407                 return 167000;
4408         }
4409 }
4410
4411 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4412 {
4413         u16 gcfgc = 0;
4414
4415         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4416
4417         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4418                 return 133000;
4419         else {
4420                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4421                 case GC_DISPLAY_CLOCK_333_MHZ:
4422                         return 333000;
4423                 default:
4424                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4425                         return 190000;
4426                 }
4427         }
4428 }
4429
4430 static int i865_get_display_clock_speed(struct drm_device *dev)
4431 {
4432         return 266000;
4433 }
4434
4435 static int i855_get_display_clock_speed(struct drm_device *dev)
4436 {
4437         u16 hpllcc = 0;
4438         /* Assume that the hardware is in the high speed state.  This
4439          * should be the default.
4440          */
4441         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4442         case GC_CLOCK_133_200:
4443         case GC_CLOCK_100_200:
4444                 return 200000;
4445         case GC_CLOCK_166_250:
4446                 return 250000;
4447         case GC_CLOCK_100_133:
4448                 return 133000;
4449         }
4450
4451         /* Shouldn't happen */
4452         return 0;
4453 }
4454
4455 static int i830_get_display_clock_speed(struct drm_device *dev)
4456 {
4457         return 133000;
4458 }
4459
4460 static void
4461 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4462 {
4463         while (*num > DATA_LINK_M_N_MASK ||
4464                *den > DATA_LINK_M_N_MASK) {
4465                 *num >>= 1;
4466                 *den >>= 1;
4467         }
4468 }
4469
4470 static void compute_m_n(unsigned int m, unsigned int n,
4471                         uint32_t *ret_m, uint32_t *ret_n)
4472 {
4473         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4474         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4475         intel_reduce_m_n_ratio(ret_m, ret_n);
4476 }
4477
4478 void
4479 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4480                        int pixel_clock, int link_clock,
4481                        struct intel_link_m_n *m_n)
4482 {
4483         m_n->tu = 64;
4484
4485         compute_m_n(bits_per_pixel * pixel_clock,
4486                     link_clock * nlanes * 8,
4487                     &m_n->gmch_m, &m_n->gmch_n);
4488
4489         compute_m_n(pixel_clock, link_clock,
4490                     &m_n->link_m, &m_n->link_n);
4491 }
4492
4493 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4494 {
4495         if (i915_panel_use_ssc >= 0)
4496                 return i915_panel_use_ssc != 0;
4497         return dev_priv->vbt.lvds_use_ssc
4498                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4499 }
4500
4501 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4502 {
4503         struct drm_device *dev = crtc->dev;
4504         struct drm_i915_private *dev_priv = dev->dev_private;
4505         int refclk;
4506
4507         if (IS_VALLEYVIEW(dev)) {
4508                 refclk = 100000;
4509         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4510             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4511                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4512                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4513                               refclk / 1000);
4514         } else if (!IS_GEN2(dev)) {
4515                 refclk = 96000;
4516         } else {
4517                 refclk = 48000;
4518         }
4519
4520         return refclk;
4521 }
4522
4523 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4524 {
4525         return (1 << dpll->n) << 16 | dpll->m2;
4526 }
4527
4528 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4529 {
4530         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4531 }
4532
4533 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4534                                      intel_clock_t *reduced_clock)
4535 {
4536         struct drm_device *dev = crtc->base.dev;
4537         struct drm_i915_private *dev_priv = dev->dev_private;
4538         int pipe = crtc->pipe;
4539         u32 fp, fp2 = 0;
4540
4541         if (IS_PINEVIEW(dev)) {
4542                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4543                 if (reduced_clock)
4544                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4545         } else {
4546                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4547                 if (reduced_clock)
4548                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4549         }
4550
4551         I915_WRITE(FP0(pipe), fp);
4552         crtc->config.dpll_hw_state.fp0 = fp;
4553
4554         crtc->lowfreq_avail = false;
4555         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4556             reduced_clock && i915_powersave) {
4557                 I915_WRITE(FP1(pipe), fp2);
4558                 crtc->config.dpll_hw_state.fp1 = fp2;
4559                 crtc->lowfreq_avail = true;
4560         } else {
4561                 I915_WRITE(FP1(pipe), fp);
4562                 crtc->config.dpll_hw_state.fp1 = fp;
4563         }
4564 }
4565
4566 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4567                 pipe)
4568 {
4569         u32 reg_val;
4570
4571         /*
4572          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4573          * and set it to a reasonable value instead.
4574          */
4575         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4576         reg_val &= 0xffffff00;
4577         reg_val |= 0x00000030;
4578         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4579
4580         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4581         reg_val &= 0x8cffffff;
4582         reg_val = 0x8c000000;
4583         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4584
4585         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4586         reg_val &= 0xffffff00;
4587         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4588
4589         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4590         reg_val &= 0x00ffffff;
4591         reg_val |= 0xb0000000;
4592         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4593 }
4594
4595 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4596                                          struct intel_link_m_n *m_n)
4597 {
4598         struct drm_device *dev = crtc->base.dev;
4599         struct drm_i915_private *dev_priv = dev->dev_private;
4600         int pipe = crtc->pipe;
4601
4602         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4603         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4604         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4605         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4606 }
4607
4608 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4609                                          struct intel_link_m_n *m_n)
4610 {
4611         struct drm_device *dev = crtc->base.dev;
4612         struct drm_i915_private *dev_priv = dev->dev_private;
4613         int pipe = crtc->pipe;
4614         enum transcoder transcoder = crtc->config.cpu_transcoder;
4615
4616         if (INTEL_INFO(dev)->gen >= 5) {
4617                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4618                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4619                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4620                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4621         } else {
4622                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4623                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4624                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4625                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4626         }
4627 }
4628
4629 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4630 {
4631         if (crtc->config.has_pch_encoder)
4632                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4633         else
4634                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4635 }
4636
4637 static void vlv_update_pll(struct intel_crtc *crtc)
4638 {
4639         struct drm_device *dev = crtc->base.dev;
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         int pipe = crtc->pipe;
4642         u32 dpll, mdiv;
4643         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4644         u32 coreclk, reg_val, dpll_md;
4645
4646         mutex_lock(&dev_priv->dpio_lock);
4647
4648         bestn = crtc->config.dpll.n;
4649         bestm1 = crtc->config.dpll.m1;
4650         bestm2 = crtc->config.dpll.m2;
4651         bestp1 = crtc->config.dpll.p1;
4652         bestp2 = crtc->config.dpll.p2;
4653
4654         /* See eDP HDMI DPIO driver vbios notes doc */
4655
4656         /* PLL B needs special handling */
4657         if (pipe)
4658                 vlv_pllb_recal_opamp(dev_priv, pipe);
4659
4660         /* Set up Tx target for periodic Rcomp update */
4661         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4662
4663         /* Disable target IRef on PLL */
4664         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4665         reg_val &= 0x00ffffff;
4666         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4667
4668         /* Disable fast lock */
4669         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4670
4671         /* Set idtafcrecal before PLL is enabled */
4672         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4673         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4674         mdiv |= ((bestn << DPIO_N_SHIFT));
4675         mdiv |= (1 << DPIO_K_SHIFT);
4676
4677         /*
4678          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4679          * but we don't support that).
4680          * Note: don't use the DAC post divider as it seems unstable.
4681          */
4682         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4683         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4684
4685         mdiv |= DPIO_ENABLE_CALIBRATION;
4686         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4687
4688         /* Set HBR and RBR LPF coefficients */
4689         if (crtc->config.port_clock == 162000 ||
4690             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4691             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4692                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4693                                  0x009f0003);
4694         else
4695                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4696                                  0x00d0000f);
4697
4698         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4699             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4700                 /* Use SSC source */
4701                 if (!pipe)
4702                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4703                                          0x0df40000);
4704                 else
4705                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4706                                          0x0df70000);
4707         } else { /* HDMI or VGA */
4708                 /* Use bend source */
4709                 if (!pipe)
4710                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4711                                          0x0df70000);
4712                 else
4713                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4714                                          0x0df40000);
4715         }
4716
4717         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4718         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4719         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4720             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4721                 coreclk |= 0x01000000;
4722         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4723
4724         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4725
4726         /* Enable DPIO clock input */
4727         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4728                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4729         /* We should never disable this, set it here for state tracking */
4730         if (pipe == PIPE_B)
4731                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4732         dpll |= DPLL_VCO_ENABLE;
4733         crtc->config.dpll_hw_state.dpll = dpll;
4734
4735         dpll_md = (crtc->config.pixel_multiplier - 1)
4736                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4737         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4738
4739         if (crtc->config.has_dp_encoder)
4740                 intel_dp_set_m_n(crtc);
4741
4742         mutex_unlock(&dev_priv->dpio_lock);
4743 }
4744
4745 static void i9xx_update_pll(struct intel_crtc *crtc,
4746                             intel_clock_t *reduced_clock,
4747                             int num_connectors)
4748 {
4749         struct drm_device *dev = crtc->base.dev;
4750         struct drm_i915_private *dev_priv = dev->dev_private;
4751         u32 dpll;
4752         bool is_sdvo;
4753         struct dpll *clock = &crtc->config.dpll;
4754
4755         i9xx_update_pll_dividers(crtc, reduced_clock);
4756
4757         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4758                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4759
4760         dpll = DPLL_VGA_MODE_DIS;
4761
4762         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4763                 dpll |= DPLLB_MODE_LVDS;
4764         else
4765                 dpll |= DPLLB_MODE_DAC_SERIAL;
4766
4767         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4768                 dpll |= (crtc->config.pixel_multiplier - 1)
4769                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4770         }
4771
4772         if (is_sdvo)
4773                 dpll |= DPLL_SDVO_HIGH_SPEED;
4774
4775         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4776                 dpll |= DPLL_SDVO_HIGH_SPEED;
4777
4778         /* compute bitmask from p1 value */
4779         if (IS_PINEVIEW(dev))
4780                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4781         else {
4782                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4783                 if (IS_G4X(dev) && reduced_clock)
4784                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4785         }
4786         switch (clock->p2) {
4787         case 5:
4788                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4789                 break;
4790         case 7:
4791                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4792                 break;
4793         case 10:
4794                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4795                 break;
4796         case 14:
4797                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4798                 break;
4799         }
4800         if (INTEL_INFO(dev)->gen >= 4)
4801                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4802
4803         if (crtc->config.sdvo_tv_clock)
4804                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4805         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4806                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4807                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4808         else
4809                 dpll |= PLL_REF_INPUT_DREFCLK;
4810
4811         dpll |= DPLL_VCO_ENABLE;
4812         crtc->config.dpll_hw_state.dpll = dpll;
4813
4814         if (INTEL_INFO(dev)->gen >= 4) {
4815                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4816                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4817                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4818         }
4819
4820         if (crtc->config.has_dp_encoder)
4821                 intel_dp_set_m_n(crtc);
4822 }
4823
4824 static void i8xx_update_pll(struct intel_crtc *crtc,
4825                             intel_clock_t *reduced_clock,
4826                             int num_connectors)
4827 {
4828         struct drm_device *dev = crtc->base.dev;
4829         struct drm_i915_private *dev_priv = dev->dev_private;
4830         u32 dpll;
4831         struct dpll *clock = &crtc->config.dpll;
4832
4833         i9xx_update_pll_dividers(crtc, reduced_clock);
4834
4835         dpll = DPLL_VGA_MODE_DIS;
4836
4837         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4838                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4839         } else {
4840                 if (clock->p1 == 2)
4841                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4842                 else
4843                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4844                 if (clock->p2 == 4)
4845                         dpll |= PLL_P2_DIVIDE_BY_4;
4846         }
4847
4848         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4849                 dpll |= DPLL_DVO_2X_MODE;
4850
4851         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4852                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4853                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4854         else
4855                 dpll |= PLL_REF_INPUT_DREFCLK;
4856
4857         dpll |= DPLL_VCO_ENABLE;
4858         crtc->config.dpll_hw_state.dpll = dpll;
4859 }
4860
4861 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4862 {
4863         struct drm_device *dev = intel_crtc->base.dev;
4864         struct drm_i915_private *dev_priv = dev->dev_private;
4865         enum pipe pipe = intel_crtc->pipe;
4866         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4867         struct drm_display_mode *adjusted_mode =
4868                 &intel_crtc->config.adjusted_mode;
4869         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4870
4871         /* We need to be careful not to changed the adjusted mode, for otherwise
4872          * the hw state checker will get angry at the mismatch. */
4873         crtc_vtotal = adjusted_mode->crtc_vtotal;
4874         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4875
4876         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4877                 /* the chip adds 2 halflines automatically */
4878                 crtc_vtotal -= 1;
4879                 crtc_vblank_end -= 1;
4880                 vsyncshift = adjusted_mode->crtc_hsync_start
4881                              - adjusted_mode->crtc_htotal / 2;
4882         } else {
4883                 vsyncshift = 0;
4884         }
4885
4886         if (INTEL_INFO(dev)->gen > 3)
4887                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4888
4889         I915_WRITE(HTOTAL(cpu_transcoder),
4890                    (adjusted_mode->crtc_hdisplay - 1) |
4891                    ((adjusted_mode->crtc_htotal - 1) << 16));
4892         I915_WRITE(HBLANK(cpu_transcoder),
4893                    (adjusted_mode->crtc_hblank_start - 1) |
4894                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4895         I915_WRITE(HSYNC(cpu_transcoder),
4896                    (adjusted_mode->crtc_hsync_start - 1) |
4897                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4898
4899         I915_WRITE(VTOTAL(cpu_transcoder),
4900                    (adjusted_mode->crtc_vdisplay - 1) |
4901                    ((crtc_vtotal - 1) << 16));
4902         I915_WRITE(VBLANK(cpu_transcoder),
4903                    (adjusted_mode->crtc_vblank_start - 1) |
4904                    ((crtc_vblank_end - 1) << 16));
4905         I915_WRITE(VSYNC(cpu_transcoder),
4906                    (adjusted_mode->crtc_vsync_start - 1) |
4907                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4908
4909         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4910          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4911          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4912          * bits. */
4913         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4914             (pipe == PIPE_B || pipe == PIPE_C))
4915                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4916
4917         /* pipesrc controls the size that is scaled from, which should
4918          * always be the user's requested size.
4919          */
4920         I915_WRITE(PIPESRC(pipe),
4921                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4922                    (intel_crtc->config.pipe_src_h - 1));
4923 }
4924
4925 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4926                                    struct intel_crtc_config *pipe_config)
4927 {
4928         struct drm_device *dev = crtc->base.dev;
4929         struct drm_i915_private *dev_priv = dev->dev_private;
4930         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4931         uint32_t tmp;
4932
4933         tmp = I915_READ(HTOTAL(cpu_transcoder));
4934         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4935         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4936         tmp = I915_READ(HBLANK(cpu_transcoder));
4937         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4938         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4939         tmp = I915_READ(HSYNC(cpu_transcoder));
4940         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4941         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4942
4943         tmp = I915_READ(VTOTAL(cpu_transcoder));
4944         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4945         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4946         tmp = I915_READ(VBLANK(cpu_transcoder));
4947         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4948         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4949         tmp = I915_READ(VSYNC(cpu_transcoder));
4950         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4951         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4952
4953         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4954                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4955                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4956                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4957         }
4958
4959         tmp = I915_READ(PIPESRC(crtc->pipe));
4960         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4961         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4962
4963         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4964         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4965 }
4966
4967 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4968                                              struct intel_crtc_config *pipe_config)
4969 {
4970         struct drm_crtc *crtc = &intel_crtc->base;
4971
4972         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4973         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4974         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4975         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4976
4977         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4978         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4979         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4980         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4981
4982         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4983
4984         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4985         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4986 }
4987
4988 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4989 {
4990         struct drm_device *dev = intel_crtc->base.dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         uint32_t pipeconf;
4993
4994         pipeconf = 0;
4995
4996         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4997             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4998                 pipeconf |= PIPECONF_ENABLE;
4999
5000         if (intel_crtc->config.double_wide)
5001                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5002
5003         /* only g4x and later have fancy bpc/dither controls */
5004         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5005                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5006                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5007                         pipeconf |= PIPECONF_DITHER_EN |
5008                                     PIPECONF_DITHER_TYPE_SP;
5009
5010                 switch (intel_crtc->config.pipe_bpp) {
5011                 case 18:
5012                         pipeconf |= PIPECONF_6BPC;
5013                         break;
5014                 case 24:
5015                         pipeconf |= PIPECONF_8BPC;
5016                         break;
5017                 case 30:
5018                         pipeconf |= PIPECONF_10BPC;
5019                         break;
5020                 default:
5021                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5022                         BUG();
5023                 }
5024         }
5025
5026         if (HAS_PIPE_CXSR(dev)) {
5027                 if (intel_crtc->lowfreq_avail) {
5028                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5029                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5030                 } else {
5031                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5032                 }
5033         }
5034
5035         if (!IS_GEN2(dev) &&
5036             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5037                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5038         else
5039                 pipeconf |= PIPECONF_PROGRESSIVE;
5040
5041         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5042                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5043
5044         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5045         POSTING_READ(PIPECONF(intel_crtc->pipe));
5046 }
5047
5048 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5049                               int x, int y,
5050                               struct drm_framebuffer *fb)
5051 {
5052         struct drm_device *dev = crtc->dev;
5053         struct drm_i915_private *dev_priv = dev->dev_private;
5054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5055         int pipe = intel_crtc->pipe;
5056         int plane = intel_crtc->plane;
5057         int refclk, num_connectors = 0;
5058         intel_clock_t clock, reduced_clock;
5059         u32 dspcntr;
5060         bool ok, has_reduced_clock = false;
5061         bool is_lvds = false, is_dsi = false;
5062         struct intel_encoder *encoder;
5063         const intel_limit_t *limit;
5064         int ret;
5065
5066         for_each_encoder_on_crtc(dev, crtc, encoder) {
5067                 switch (encoder->type) {
5068                 case INTEL_OUTPUT_LVDS:
5069                         is_lvds = true;
5070                         break;
5071                 case INTEL_OUTPUT_DSI:
5072                         is_dsi = true;
5073                         break;
5074                 }
5075
5076                 num_connectors++;
5077         }
5078
5079         if (is_dsi)
5080                 goto skip_dpll;
5081
5082         if (!intel_crtc->config.clock_set) {
5083                 refclk = i9xx_get_refclk(crtc, num_connectors);
5084
5085                 /*
5086                  * Returns a set of divisors for the desired target clock with
5087                  * the given refclk, or FALSE.  The returned values represent
5088                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5089                  * 2) / p1 / p2.
5090                  */
5091                 limit = intel_limit(crtc, refclk);
5092                 ok = dev_priv->display.find_dpll(limit, crtc,
5093                                                  intel_crtc->config.port_clock,
5094                                                  refclk, NULL, &clock);
5095                 if (!ok) {
5096                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5097                         return -EINVAL;
5098                 }
5099
5100                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5101                         /*
5102                          * Ensure we match the reduced clock's P to the target
5103                          * clock.  If the clocks don't match, we can't switch
5104                          * the display clock by using the FP0/FP1. In such case
5105                          * we will disable the LVDS downclock feature.
5106                          */
5107                         has_reduced_clock =
5108                                 dev_priv->display.find_dpll(limit, crtc,
5109                                                             dev_priv->lvds_downclock,
5110                                                             refclk, &clock,
5111                                                             &reduced_clock);
5112                 }
5113                 /* Compat-code for transition, will disappear. */
5114                 intel_crtc->config.dpll.n = clock.n;
5115                 intel_crtc->config.dpll.m1 = clock.m1;
5116                 intel_crtc->config.dpll.m2 = clock.m2;
5117                 intel_crtc->config.dpll.p1 = clock.p1;
5118                 intel_crtc->config.dpll.p2 = clock.p2;
5119         }
5120
5121         if (IS_GEN2(dev)) {
5122                 i8xx_update_pll(intel_crtc,
5123                                 has_reduced_clock ? &reduced_clock : NULL,
5124                                 num_connectors);
5125         } else if (IS_VALLEYVIEW(dev)) {
5126                 vlv_update_pll(intel_crtc);
5127         } else {
5128                 i9xx_update_pll(intel_crtc,
5129                                 has_reduced_clock ? &reduced_clock : NULL,
5130                                 num_connectors);
5131         }
5132
5133 skip_dpll:
5134         /* Set up the display plane register */
5135         dspcntr = DISPPLANE_GAMMA_ENABLE;
5136
5137         if (!IS_VALLEYVIEW(dev)) {
5138                 if (pipe == 0)
5139                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5140                 else
5141                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5142         }
5143
5144         intel_set_pipe_timings(intel_crtc);
5145
5146         /* pipesrc and dspsize control the size that is scaled from,
5147          * which should always be the user's requested size.
5148          */
5149         I915_WRITE(DSPSIZE(plane),
5150                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5151                    (intel_crtc->config.pipe_src_w - 1));
5152         I915_WRITE(DSPPOS(plane), 0);
5153
5154         i9xx_set_pipeconf(intel_crtc);
5155
5156         I915_WRITE(DSPCNTR(plane), dspcntr);
5157         POSTING_READ(DSPCNTR(plane));
5158
5159         ret = intel_pipe_set_base(crtc, x, y, fb);
5160
5161         return ret;
5162 }
5163
5164 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5165                                  struct intel_crtc_config *pipe_config)
5166 {
5167         struct drm_device *dev = crtc->base.dev;
5168         struct drm_i915_private *dev_priv = dev->dev_private;
5169         uint32_t tmp;
5170
5171         tmp = I915_READ(PFIT_CONTROL);
5172         if (!(tmp & PFIT_ENABLE))
5173                 return;
5174
5175         /* Check whether the pfit is attached to our pipe. */
5176         if (INTEL_INFO(dev)->gen < 4) {
5177                 if (crtc->pipe != PIPE_B)
5178                         return;
5179         } else {
5180                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5181                         return;
5182         }
5183
5184         pipe_config->gmch_pfit.control = tmp;
5185         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5186         if (INTEL_INFO(dev)->gen < 5)
5187                 pipe_config->gmch_pfit.lvds_border_bits =
5188                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5189 }
5190
5191 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5192                                struct intel_crtc_config *pipe_config)
5193 {
5194         struct drm_device *dev = crtc->base.dev;
5195         struct drm_i915_private *dev_priv = dev->dev_private;
5196         int pipe = pipe_config->cpu_transcoder;
5197         intel_clock_t clock;
5198         u32 mdiv;
5199         int refclk = 100000;
5200
5201         mutex_lock(&dev_priv->dpio_lock);
5202         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5203         mutex_unlock(&dev_priv->dpio_lock);
5204
5205         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5206         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5207         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5208         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5209         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5210
5211         vlv_clock(refclk, &clock);
5212
5213         /* clock.dot is the fast clock */
5214         pipe_config->port_clock = clock.dot / 5;
5215 }
5216
5217 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5218                                  struct intel_crtc_config *pipe_config)
5219 {
5220         struct drm_device *dev = crtc->base.dev;
5221         struct drm_i915_private *dev_priv = dev->dev_private;
5222         uint32_t tmp;
5223
5224         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5225         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5226
5227         tmp = I915_READ(PIPECONF(crtc->pipe));
5228         if (!(tmp & PIPECONF_ENABLE))
5229                 return false;
5230
5231         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5232                 switch (tmp & PIPECONF_BPC_MASK) {
5233                 case PIPECONF_6BPC:
5234                         pipe_config->pipe_bpp = 18;
5235                         break;
5236                 case PIPECONF_8BPC:
5237                         pipe_config->pipe_bpp = 24;
5238                         break;
5239                 case PIPECONF_10BPC:
5240                         pipe_config->pipe_bpp = 30;
5241                         break;
5242                 default:
5243                         break;
5244                 }
5245         }
5246
5247         if (INTEL_INFO(dev)->gen < 4)
5248                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5249
5250         intel_get_pipe_timings(crtc, pipe_config);
5251
5252         i9xx_get_pfit_config(crtc, pipe_config);
5253
5254         if (INTEL_INFO(dev)->gen >= 4) {
5255                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5256                 pipe_config->pixel_multiplier =
5257                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5258                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5259                 pipe_config->dpll_hw_state.dpll_md = tmp;
5260         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5261                 tmp = I915_READ(DPLL(crtc->pipe));
5262                 pipe_config->pixel_multiplier =
5263                         ((tmp & SDVO_MULTIPLIER_MASK)
5264                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5265         } else {
5266                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5267                  * port and will be fixed up in the encoder->get_config
5268                  * function. */
5269                 pipe_config->pixel_multiplier = 1;
5270         }
5271         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5272         if (!IS_VALLEYVIEW(dev)) {
5273                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5274                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5275         } else {
5276                 /* Mask out read-only status bits. */
5277                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5278                                                      DPLL_PORTC_READY_MASK |
5279                                                      DPLL_PORTB_READY_MASK);
5280         }
5281
5282         if (IS_VALLEYVIEW(dev))
5283                 vlv_crtc_clock_get(crtc, pipe_config);
5284         else
5285                 i9xx_crtc_clock_get(crtc, pipe_config);
5286
5287         return true;
5288 }
5289
5290 static void ironlake_init_pch_refclk(struct drm_device *dev)
5291 {
5292         struct drm_i915_private *dev_priv = dev->dev_private;
5293         struct drm_mode_config *mode_config = &dev->mode_config;
5294         struct intel_encoder *encoder;
5295         u32 val, final;
5296         bool has_lvds = false;
5297         bool has_cpu_edp = false;
5298         bool has_panel = false;
5299         bool has_ck505 = false;
5300         bool can_ssc = false;
5301
5302         /* We need to take the global config into account */
5303         list_for_each_entry(encoder, &mode_config->encoder_list,
5304                             base.head) {
5305                 switch (encoder->type) {
5306                 case INTEL_OUTPUT_LVDS:
5307                         has_panel = true;
5308                         has_lvds = true;
5309                         break;
5310                 case INTEL_OUTPUT_EDP:
5311                         has_panel = true;
5312                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5313                                 has_cpu_edp = true;
5314                         break;
5315                 }
5316         }
5317
5318         if (HAS_PCH_IBX(dev)) {
5319                 has_ck505 = dev_priv->vbt.display_clock_mode;
5320                 can_ssc = has_ck505;
5321         } else {
5322                 has_ck505 = false;
5323                 can_ssc = true;
5324         }
5325
5326         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5327                       has_panel, has_lvds, has_ck505);
5328
5329         /* Ironlake: try to setup display ref clock before DPLL
5330          * enabling. This is only under driver's control after
5331          * PCH B stepping, previous chipset stepping should be
5332          * ignoring this setting.
5333          */
5334         val = I915_READ(PCH_DREF_CONTROL);
5335
5336         /* As we must carefully and slowly disable/enable each source in turn,
5337          * compute the final state we want first and check if we need to
5338          * make any changes at all.
5339          */
5340         final = val;
5341         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5342         if (has_ck505)
5343                 final |= DREF_NONSPREAD_CK505_ENABLE;
5344         else
5345                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5346
5347         final &= ~DREF_SSC_SOURCE_MASK;
5348         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5349         final &= ~DREF_SSC1_ENABLE;
5350
5351         if (has_panel) {
5352                 final |= DREF_SSC_SOURCE_ENABLE;
5353
5354                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5355                         final |= DREF_SSC1_ENABLE;
5356
5357                 if (has_cpu_edp) {
5358                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5359                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5360                         else
5361                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5362                 } else
5363                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5364         } else {
5365                 final |= DREF_SSC_SOURCE_DISABLE;
5366                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5367         }
5368
5369         if (final == val)
5370                 return;
5371
5372         /* Always enable nonspread source */
5373         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5374
5375         if (has_ck505)
5376                 val |= DREF_NONSPREAD_CK505_ENABLE;
5377         else
5378                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5379
5380         if (has_panel) {
5381                 val &= ~DREF_SSC_SOURCE_MASK;
5382                 val |= DREF_SSC_SOURCE_ENABLE;
5383
5384                 /* SSC must be turned on before enabling the CPU output  */
5385                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5386                         DRM_DEBUG_KMS("Using SSC on panel\n");
5387                         val |= DREF_SSC1_ENABLE;
5388                 } else
5389                         val &= ~DREF_SSC1_ENABLE;
5390
5391                 /* Get SSC going before enabling the outputs */
5392                 I915_WRITE(PCH_DREF_CONTROL, val);
5393                 POSTING_READ(PCH_DREF_CONTROL);
5394                 udelay(200);
5395
5396                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5397
5398                 /* Enable CPU source on CPU attached eDP */
5399                 if (has_cpu_edp) {
5400                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5401                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5402                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5403                         }
5404                         else
5405                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5406                 } else
5407                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5408
5409                 I915_WRITE(PCH_DREF_CONTROL, val);
5410                 POSTING_READ(PCH_DREF_CONTROL);
5411                 udelay(200);
5412         } else {
5413                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5414
5415                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5416
5417                 /* Turn off CPU output */
5418                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5419
5420                 I915_WRITE(PCH_DREF_CONTROL, val);
5421                 POSTING_READ(PCH_DREF_CONTROL);
5422                 udelay(200);
5423
5424                 /* Turn off the SSC source */
5425                 val &= ~DREF_SSC_SOURCE_MASK;
5426                 val |= DREF_SSC_SOURCE_DISABLE;
5427
5428                 /* Turn off SSC1 */
5429                 val &= ~DREF_SSC1_ENABLE;
5430
5431                 I915_WRITE(PCH_DREF_CONTROL, val);
5432                 POSTING_READ(PCH_DREF_CONTROL);
5433                 udelay(200);
5434         }
5435
5436         BUG_ON(val != final);
5437 }
5438
5439 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5440 {
5441         uint32_t tmp;
5442
5443         tmp = I915_READ(SOUTH_CHICKEN2);
5444         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5445         I915_WRITE(SOUTH_CHICKEN2, tmp);
5446
5447         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5448                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5449                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5450
5451         tmp = I915_READ(SOUTH_CHICKEN2);
5452         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5453         I915_WRITE(SOUTH_CHICKEN2, tmp);
5454
5455         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5456                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5457                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5458 }
5459
5460 /* WaMPhyProgramming:hsw */
5461 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5462 {
5463         uint32_t tmp;
5464
5465         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5466         tmp &= ~(0xFF << 24);
5467         tmp |= (0x12 << 24);
5468         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5469
5470         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5471         tmp |= (1 << 11);
5472         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5473
5474         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5475         tmp |= (1 << 11);
5476         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5477
5478         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5479         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5480         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5481
5482         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5483         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5484         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5485
5486         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5487         tmp &= ~(7 << 13);
5488         tmp |= (5 << 13);
5489         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5490
5491         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5492         tmp &= ~(7 << 13);
5493         tmp |= (5 << 13);
5494         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5495
5496         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5497         tmp &= ~0xFF;
5498         tmp |= 0x1C;
5499         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5500
5501         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5502         tmp &= ~0xFF;
5503         tmp |= 0x1C;
5504         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5505
5506         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5507         tmp &= ~(0xFF << 16);
5508         tmp |= (0x1C << 16);
5509         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5510
5511         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5512         tmp &= ~(0xFF << 16);
5513         tmp |= (0x1C << 16);
5514         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5515
5516         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5517         tmp |= (1 << 27);
5518         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5519
5520         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5521         tmp |= (1 << 27);
5522         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5523
5524         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5525         tmp &= ~(0xF << 28);
5526         tmp |= (4 << 28);
5527         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5528
5529         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5530         tmp &= ~(0xF << 28);
5531         tmp |= (4 << 28);
5532         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5533 }
5534
5535 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5536  * Programming" based on the parameters passed:
5537  * - Sequence to enable CLKOUT_DP
5538  * - Sequence to enable CLKOUT_DP without spread
5539  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5540  */
5541 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5542                                  bool with_fdi)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         uint32_t reg, tmp;
5546
5547         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5548                 with_spread = true;
5549         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5550                  with_fdi, "LP PCH doesn't have FDI\n"))
5551                 with_fdi = false;
5552
5553         mutex_lock(&dev_priv->dpio_lock);
5554
5555         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5556         tmp &= ~SBI_SSCCTL_DISABLE;
5557         tmp |= SBI_SSCCTL_PATHALT;
5558         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5559
5560         udelay(24);
5561
5562         if (with_spread) {
5563                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5564                 tmp &= ~SBI_SSCCTL_PATHALT;
5565                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5566
5567                 if (with_fdi) {
5568                         lpt_reset_fdi_mphy(dev_priv);
5569                         lpt_program_fdi_mphy(dev_priv);
5570                 }
5571         }
5572
5573         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5574                SBI_GEN0 : SBI_DBUFF0;
5575         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5576         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5577         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5578
5579         mutex_unlock(&dev_priv->dpio_lock);
5580 }
5581
5582 /* Sequence to disable CLKOUT_DP */
5583 static void lpt_disable_clkout_dp(struct drm_device *dev)
5584 {
5585         struct drm_i915_private *dev_priv = dev->dev_private;
5586         uint32_t reg, tmp;
5587
5588         mutex_lock(&dev_priv->dpio_lock);
5589
5590         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5591                SBI_GEN0 : SBI_DBUFF0;
5592         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5593         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5594         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5595
5596         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5597         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5598                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5599                         tmp |= SBI_SSCCTL_PATHALT;
5600                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5601                         udelay(32);
5602                 }
5603                 tmp |= SBI_SSCCTL_DISABLE;
5604                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5605         }
5606
5607         mutex_unlock(&dev_priv->dpio_lock);
5608 }
5609
5610 static void lpt_init_pch_refclk(struct drm_device *dev)
5611 {
5612         struct drm_mode_config *mode_config = &dev->mode_config;
5613         struct intel_encoder *encoder;
5614         bool has_vga = false;
5615
5616         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5617                 switch (encoder->type) {
5618                 case INTEL_OUTPUT_ANALOG:
5619                         has_vga = true;
5620                         break;
5621                 }
5622         }
5623
5624         if (has_vga)
5625                 lpt_enable_clkout_dp(dev, true, true);
5626         else
5627                 lpt_disable_clkout_dp(dev);
5628 }
5629
5630 /*
5631  * Initialize reference clocks when the driver loads
5632  */
5633 void intel_init_pch_refclk(struct drm_device *dev)
5634 {
5635         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5636                 ironlake_init_pch_refclk(dev);
5637         else if (HAS_PCH_LPT(dev))
5638                 lpt_init_pch_refclk(dev);
5639 }
5640
5641 static int ironlake_get_refclk(struct drm_crtc *crtc)
5642 {
5643         struct drm_device *dev = crtc->dev;
5644         struct drm_i915_private *dev_priv = dev->dev_private;
5645         struct intel_encoder *encoder;
5646         int num_connectors = 0;
5647         bool is_lvds = false;
5648
5649         for_each_encoder_on_crtc(dev, crtc, encoder) {
5650                 switch (encoder->type) {
5651                 case INTEL_OUTPUT_LVDS:
5652                         is_lvds = true;
5653                         break;
5654                 }
5655                 num_connectors++;
5656         }
5657
5658         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5659                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5660                               dev_priv->vbt.lvds_ssc_freq);
5661                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5662         }
5663
5664         return 120000;
5665 }
5666
5667 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5668 {
5669         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5671         int pipe = intel_crtc->pipe;
5672         uint32_t val;
5673
5674         val = 0;
5675
5676         switch (intel_crtc->config.pipe_bpp) {
5677         case 18:
5678                 val |= PIPECONF_6BPC;
5679                 break;
5680         case 24:
5681                 val |= PIPECONF_8BPC;
5682                 break;
5683         case 30:
5684                 val |= PIPECONF_10BPC;
5685                 break;
5686         case 36:
5687                 val |= PIPECONF_12BPC;
5688                 break;
5689         default:
5690                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5691                 BUG();
5692         }
5693
5694         if (intel_crtc->config.dither)
5695                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5696
5697         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5698                 val |= PIPECONF_INTERLACED_ILK;
5699         else
5700                 val |= PIPECONF_PROGRESSIVE;
5701
5702         if (intel_crtc->config.limited_color_range)
5703                 val |= PIPECONF_COLOR_RANGE_SELECT;
5704
5705         I915_WRITE(PIPECONF(pipe), val);
5706         POSTING_READ(PIPECONF(pipe));
5707 }
5708
5709 /*
5710  * Set up the pipe CSC unit.
5711  *
5712  * Currently only full range RGB to limited range RGB conversion
5713  * is supported, but eventually this should handle various
5714  * RGB<->YCbCr scenarios as well.
5715  */
5716 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5717 {
5718         struct drm_device *dev = crtc->dev;
5719         struct drm_i915_private *dev_priv = dev->dev_private;
5720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5721         int pipe = intel_crtc->pipe;
5722         uint16_t coeff = 0x7800; /* 1.0 */
5723
5724         /*
5725          * TODO: Check what kind of values actually come out of the pipe
5726          * with these coeff/postoff values and adjust to get the best
5727          * accuracy. Perhaps we even need to take the bpc value into
5728          * consideration.
5729          */
5730
5731         if (intel_crtc->config.limited_color_range)
5732                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5733
5734         /*
5735          * GY/GU and RY/RU should be the other way around according
5736          * to BSpec, but reality doesn't agree. Just set them up in
5737          * a way that results in the correct picture.
5738          */
5739         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5740         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5741
5742         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5743         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5744
5745         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5746         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5747
5748         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5749         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5750         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5751
5752         if (INTEL_INFO(dev)->gen > 6) {
5753                 uint16_t postoff = 0;
5754
5755                 if (intel_crtc->config.limited_color_range)
5756                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5757
5758                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5759                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5760                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5761
5762                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5763         } else {
5764                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5765
5766                 if (intel_crtc->config.limited_color_range)
5767                         mode |= CSC_BLACK_SCREEN_OFFSET;
5768
5769                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5770         }
5771 }
5772
5773 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5774 {
5775         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5777         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5778         uint32_t val;
5779
5780         val = 0;
5781
5782         if (intel_crtc->config.dither)
5783                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5784
5785         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5786                 val |= PIPECONF_INTERLACED_ILK;
5787         else
5788                 val |= PIPECONF_PROGRESSIVE;
5789
5790         I915_WRITE(PIPECONF(cpu_transcoder), val);
5791         POSTING_READ(PIPECONF(cpu_transcoder));
5792
5793         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5794         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5795 }
5796
5797 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5798                                     intel_clock_t *clock,
5799                                     bool *has_reduced_clock,
5800                                     intel_clock_t *reduced_clock)
5801 {
5802         struct drm_device *dev = crtc->dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         struct intel_encoder *intel_encoder;
5805         int refclk;
5806         const intel_limit_t *limit;
5807         bool ret, is_lvds = false;
5808
5809         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5810                 switch (intel_encoder->type) {
5811                 case INTEL_OUTPUT_LVDS:
5812                         is_lvds = true;
5813                         break;
5814                 }
5815         }
5816
5817         refclk = ironlake_get_refclk(crtc);
5818
5819         /*
5820          * Returns a set of divisors for the desired target clock with the given
5821          * refclk, or FALSE.  The returned values represent the clock equation:
5822          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5823          */
5824         limit = intel_limit(crtc, refclk);
5825         ret = dev_priv->display.find_dpll(limit, crtc,
5826                                           to_intel_crtc(crtc)->config.port_clock,
5827                                           refclk, NULL, clock);
5828         if (!ret)
5829                 return false;
5830
5831         if (is_lvds && dev_priv->lvds_downclock_avail) {
5832                 /*
5833                  * Ensure we match the reduced clock's P to the target clock.
5834                  * If the clocks don't match, we can't switch the display clock
5835                  * by using the FP0/FP1. In such case we will disable the LVDS
5836                  * downclock feature.
5837                 */
5838                 *has_reduced_clock =
5839                         dev_priv->display.find_dpll(limit, crtc,
5840                                                     dev_priv->lvds_downclock,
5841                                                     refclk, clock,
5842                                                     reduced_clock);
5843         }
5844
5845         return true;
5846 }
5847
5848 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5849 {
5850         struct drm_i915_private *dev_priv = dev->dev_private;
5851         uint32_t temp;
5852
5853         temp = I915_READ(SOUTH_CHICKEN1);
5854         if (temp & FDI_BC_BIFURCATION_SELECT)
5855                 return;
5856
5857         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5858         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5859
5860         temp |= FDI_BC_BIFURCATION_SELECT;
5861         DRM_DEBUG_KMS("enabling fdi C rx\n");
5862         I915_WRITE(SOUTH_CHICKEN1, temp);
5863         POSTING_READ(SOUTH_CHICKEN1);
5864 }
5865
5866 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5867 {
5868         struct drm_device *dev = intel_crtc->base.dev;
5869         struct drm_i915_private *dev_priv = dev->dev_private;
5870
5871         switch (intel_crtc->pipe) {
5872         case PIPE_A:
5873                 break;
5874         case PIPE_B:
5875                 if (intel_crtc->config.fdi_lanes > 2)
5876                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5877                 else
5878                         cpt_enable_fdi_bc_bifurcation(dev);
5879
5880                 break;
5881         case PIPE_C:
5882                 cpt_enable_fdi_bc_bifurcation(dev);
5883
5884                 break;
5885         default:
5886                 BUG();
5887         }
5888 }
5889
5890 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5891 {
5892         /*
5893          * Account for spread spectrum to avoid
5894          * oversubscribing the link. Max center spread
5895          * is 2.5%; use 5% for safety's sake.
5896          */
5897         u32 bps = target_clock * bpp * 21 / 20;
5898         return bps / (link_bw * 8) + 1;
5899 }
5900
5901 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5902 {
5903         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5904 }
5905
5906 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5907                                       u32 *fp,
5908                                       intel_clock_t *reduced_clock, u32 *fp2)
5909 {
5910         struct drm_crtc *crtc = &intel_crtc->base;
5911         struct drm_device *dev = crtc->dev;
5912         struct drm_i915_private *dev_priv = dev->dev_private;
5913         struct intel_encoder *intel_encoder;
5914         uint32_t dpll;
5915         int factor, num_connectors = 0;
5916         bool is_lvds = false, is_sdvo = false;
5917
5918         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5919                 switch (intel_encoder->type) {
5920                 case INTEL_OUTPUT_LVDS:
5921                         is_lvds = true;
5922                         break;
5923                 case INTEL_OUTPUT_SDVO:
5924                 case INTEL_OUTPUT_HDMI:
5925                         is_sdvo = true;
5926                         break;
5927                 }
5928
5929                 num_connectors++;
5930         }
5931
5932         /* Enable autotuning of the PLL clock (if permissible) */
5933         factor = 21;
5934         if (is_lvds) {
5935                 if ((intel_panel_use_ssc(dev_priv) &&
5936                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5937                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5938                         factor = 25;
5939         } else if (intel_crtc->config.sdvo_tv_clock)
5940                 factor = 20;
5941
5942         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5943                 *fp |= FP_CB_TUNE;
5944
5945         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5946                 *fp2 |= FP_CB_TUNE;
5947
5948         dpll = 0;
5949
5950         if (is_lvds)
5951                 dpll |= DPLLB_MODE_LVDS;
5952         else
5953                 dpll |= DPLLB_MODE_DAC_SERIAL;
5954
5955         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5956                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5957
5958         if (is_sdvo)
5959                 dpll |= DPLL_SDVO_HIGH_SPEED;
5960         if (intel_crtc->config.has_dp_encoder)
5961                 dpll |= DPLL_SDVO_HIGH_SPEED;
5962
5963         /* compute bitmask from p1 value */
5964         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5965         /* also FPA1 */
5966         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5967
5968         switch (intel_crtc->config.dpll.p2) {
5969         case 5:
5970                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5971                 break;
5972         case 7:
5973                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5974                 break;
5975         case 10:
5976                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5977                 break;
5978         case 14:
5979                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5980                 break;
5981         }
5982
5983         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5984                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5985         else
5986                 dpll |= PLL_REF_INPUT_DREFCLK;
5987
5988         return dpll | DPLL_VCO_ENABLE;
5989 }
5990
5991 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5992                                   int x, int y,
5993                                   struct drm_framebuffer *fb)
5994 {
5995         struct drm_device *dev = crtc->dev;
5996         struct drm_i915_private *dev_priv = dev->dev_private;
5997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998         int pipe = intel_crtc->pipe;
5999         int plane = intel_crtc->plane;
6000         int num_connectors = 0;
6001         intel_clock_t clock, reduced_clock;
6002         u32 dpll = 0, fp = 0, fp2 = 0;
6003         bool ok, has_reduced_clock = false;
6004         bool is_lvds = false;
6005         struct intel_encoder *encoder;
6006         struct intel_shared_dpll *pll;
6007         int ret;
6008
6009         for_each_encoder_on_crtc(dev, crtc, encoder) {
6010                 switch (encoder->type) {
6011                 case INTEL_OUTPUT_LVDS:
6012                         is_lvds = true;
6013                         break;
6014                 }
6015
6016                 num_connectors++;
6017         }
6018
6019         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6020              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6021
6022         ok = ironlake_compute_clocks(crtc, &clock,
6023                                      &has_reduced_clock, &reduced_clock);
6024         if (!ok && !intel_crtc->config.clock_set) {
6025                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6026                 return -EINVAL;
6027         }
6028         /* Compat-code for transition, will disappear. */
6029         if (!intel_crtc->config.clock_set) {
6030                 intel_crtc->config.dpll.n = clock.n;
6031                 intel_crtc->config.dpll.m1 = clock.m1;
6032                 intel_crtc->config.dpll.m2 = clock.m2;
6033                 intel_crtc->config.dpll.p1 = clock.p1;
6034                 intel_crtc->config.dpll.p2 = clock.p2;
6035         }
6036
6037         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6038         if (intel_crtc->config.has_pch_encoder) {
6039                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6040                 if (has_reduced_clock)
6041                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6042
6043                 dpll = ironlake_compute_dpll(intel_crtc,
6044                                              &fp, &reduced_clock,
6045                                              has_reduced_clock ? &fp2 : NULL);
6046
6047                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6048                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6049                 if (has_reduced_clock)
6050                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6051                 else
6052                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6053
6054                 pll = intel_get_shared_dpll(intel_crtc);
6055                 if (pll == NULL) {
6056                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6057                                          pipe_name(pipe));
6058                         return -EINVAL;
6059                 }
6060         } else
6061                 intel_put_shared_dpll(intel_crtc);
6062
6063         if (intel_crtc->config.has_dp_encoder)
6064                 intel_dp_set_m_n(intel_crtc);
6065
6066         if (is_lvds && has_reduced_clock && i915_powersave)
6067                 intel_crtc->lowfreq_avail = true;
6068         else
6069                 intel_crtc->lowfreq_avail = false;
6070
6071         intel_set_pipe_timings(intel_crtc);
6072
6073         if (intel_crtc->config.has_pch_encoder) {
6074                 intel_cpu_transcoder_set_m_n(intel_crtc,
6075                                              &intel_crtc->config.fdi_m_n);
6076         }
6077
6078         if (IS_IVYBRIDGE(dev))
6079                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6080
6081         ironlake_set_pipeconf(crtc);
6082
6083         /* Set up the display plane register */
6084         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6085         POSTING_READ(DSPCNTR(plane));
6086
6087         ret = intel_pipe_set_base(crtc, x, y, fb);
6088
6089         return ret;
6090 }
6091
6092 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6093                                          struct intel_link_m_n *m_n)
6094 {
6095         struct drm_device *dev = crtc->base.dev;
6096         struct drm_i915_private *dev_priv = dev->dev_private;
6097         enum pipe pipe = crtc->pipe;
6098
6099         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6100         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6101         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6102                 & ~TU_SIZE_MASK;
6103         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6104         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6105                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6106 }
6107
6108 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6109                                          enum transcoder transcoder,
6110                                          struct intel_link_m_n *m_n)
6111 {
6112         struct drm_device *dev = crtc->base.dev;
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114         enum pipe pipe = crtc->pipe;
6115
6116         if (INTEL_INFO(dev)->gen >= 5) {
6117                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6118                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6119                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6120                         & ~TU_SIZE_MASK;
6121                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6122                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6123                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6124         } else {
6125                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6126                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6127                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6128                         & ~TU_SIZE_MASK;
6129                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6130                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6131                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6132         }
6133 }
6134
6135 void intel_dp_get_m_n(struct intel_crtc *crtc,
6136                       struct intel_crtc_config *pipe_config)
6137 {
6138         if (crtc->config.has_pch_encoder)
6139                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6140         else
6141                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6142                                              &pipe_config->dp_m_n);
6143 }
6144
6145 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6146                                         struct intel_crtc_config *pipe_config)
6147 {
6148         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6149                                      &pipe_config->fdi_m_n);
6150 }
6151
6152 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6153                                      struct intel_crtc_config *pipe_config)
6154 {
6155         struct drm_device *dev = crtc->base.dev;
6156         struct drm_i915_private *dev_priv = dev->dev_private;
6157         uint32_t tmp;
6158
6159         tmp = I915_READ(PF_CTL(crtc->pipe));
6160
6161         if (tmp & PF_ENABLE) {
6162                 pipe_config->pch_pfit.enabled = true;
6163                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6164                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6165
6166                 /* We currently do not free assignements of panel fitters on
6167                  * ivb/hsw (since we don't use the higher upscaling modes which
6168                  * differentiates them) so just WARN about this case for now. */
6169                 if (IS_GEN7(dev)) {
6170                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6171                                 PF_PIPE_SEL_IVB(crtc->pipe));
6172                 }
6173         }
6174 }
6175
6176 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6177                                      struct intel_crtc_config *pipe_config)
6178 {
6179         struct drm_device *dev = crtc->base.dev;
6180         struct drm_i915_private *dev_priv = dev->dev_private;
6181         uint32_t tmp;
6182
6183         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6184         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6185
6186         tmp = I915_READ(PIPECONF(crtc->pipe));
6187         if (!(tmp & PIPECONF_ENABLE))
6188                 return false;
6189
6190         switch (tmp & PIPECONF_BPC_MASK) {
6191         case PIPECONF_6BPC:
6192                 pipe_config->pipe_bpp = 18;
6193                 break;
6194         case PIPECONF_8BPC:
6195                 pipe_config->pipe_bpp = 24;
6196                 break;
6197         case PIPECONF_10BPC:
6198                 pipe_config->pipe_bpp = 30;
6199                 break;
6200         case PIPECONF_12BPC:
6201                 pipe_config->pipe_bpp = 36;
6202                 break;
6203         default:
6204                 break;
6205         }
6206
6207         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6208                 struct intel_shared_dpll *pll;
6209
6210                 pipe_config->has_pch_encoder = true;
6211
6212                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6213                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6214                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6215
6216                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6217
6218                 if (HAS_PCH_IBX(dev_priv->dev)) {
6219                         pipe_config->shared_dpll =
6220                                 (enum intel_dpll_id) crtc->pipe;
6221                 } else {
6222                         tmp = I915_READ(PCH_DPLL_SEL);
6223                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6224                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6225                         else
6226                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6227                 }
6228
6229                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6230
6231                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6232                                            &pipe_config->dpll_hw_state));
6233
6234                 tmp = pipe_config->dpll_hw_state.dpll;
6235                 pipe_config->pixel_multiplier =
6236                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6237                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6238
6239                 ironlake_pch_clock_get(crtc, pipe_config);
6240         } else {
6241                 pipe_config->pixel_multiplier = 1;
6242         }
6243
6244         intel_get_pipe_timings(crtc, pipe_config);
6245
6246         ironlake_get_pfit_config(crtc, pipe_config);
6247
6248         return true;
6249 }
6250
6251 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6252 {
6253         struct drm_device *dev = dev_priv->dev;
6254         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6255         struct intel_crtc *crtc;
6256         unsigned long irqflags;
6257         uint32_t val;
6258
6259         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6260                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6261                      pipe_name(crtc->pipe));
6262
6263         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6264         WARN(plls->spll_refcount, "SPLL enabled\n");
6265         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6266         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6267         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6268         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6269              "CPU PWM1 enabled\n");
6270         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6271              "CPU PWM2 enabled\n");
6272         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6273              "PCH PWM1 enabled\n");
6274         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6275              "Utility pin enabled\n");
6276         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6277
6278         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6279         val = I915_READ(DEIMR);
6280         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6281              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6282         val = I915_READ(SDEIMR);
6283         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6284              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6285         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6286 }
6287
6288 /*
6289  * This function implements pieces of two sequences from BSpec:
6290  * - Sequence for display software to disable LCPLL
6291  * - Sequence for display software to allow package C8+
6292  * The steps implemented here are just the steps that actually touch the LCPLL
6293  * register. Callers should take care of disabling all the display engine
6294  * functions, doing the mode unset, fixing interrupts, etc.
6295  */
6296 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6297                               bool switch_to_fclk, bool allow_power_down)
6298 {
6299         uint32_t val;
6300
6301         assert_can_disable_lcpll(dev_priv);
6302
6303         val = I915_READ(LCPLL_CTL);
6304
6305         if (switch_to_fclk) {
6306                 val |= LCPLL_CD_SOURCE_FCLK;
6307                 I915_WRITE(LCPLL_CTL, val);
6308
6309                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6310                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6311                         DRM_ERROR("Switching to FCLK failed\n");
6312
6313                 val = I915_READ(LCPLL_CTL);
6314         }
6315
6316         val |= LCPLL_PLL_DISABLE;
6317         I915_WRITE(LCPLL_CTL, val);
6318         POSTING_READ(LCPLL_CTL);
6319
6320         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6321                 DRM_ERROR("LCPLL still locked\n");
6322
6323         val = I915_READ(D_COMP);
6324         val |= D_COMP_COMP_DISABLE;
6325         mutex_lock(&dev_priv->rps.hw_lock);
6326         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6327                 DRM_ERROR("Failed to disable D_COMP\n");
6328         mutex_unlock(&dev_priv->rps.hw_lock);
6329         POSTING_READ(D_COMP);
6330         ndelay(100);
6331
6332         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6333                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6334
6335         if (allow_power_down) {
6336                 val = I915_READ(LCPLL_CTL);
6337                 val |= LCPLL_POWER_DOWN_ALLOW;
6338                 I915_WRITE(LCPLL_CTL, val);
6339                 POSTING_READ(LCPLL_CTL);
6340         }
6341 }
6342
6343 /*
6344  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6345  * source.
6346  */
6347 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6348 {
6349         uint32_t val;
6350
6351         val = I915_READ(LCPLL_CTL);
6352
6353         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6354                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6355                 return;
6356
6357         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6358          * we'll hang the machine! */
6359         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6360
6361         if (val & LCPLL_POWER_DOWN_ALLOW) {
6362                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6363                 I915_WRITE(LCPLL_CTL, val);
6364                 POSTING_READ(LCPLL_CTL);
6365         }
6366
6367         val = I915_READ(D_COMP);
6368         val |= D_COMP_COMP_FORCE;
6369         val &= ~D_COMP_COMP_DISABLE;
6370         mutex_lock(&dev_priv->rps.hw_lock);
6371         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6372                 DRM_ERROR("Failed to enable D_COMP\n");
6373         mutex_unlock(&dev_priv->rps.hw_lock);
6374         POSTING_READ(D_COMP);
6375
6376         val = I915_READ(LCPLL_CTL);
6377         val &= ~LCPLL_PLL_DISABLE;
6378         I915_WRITE(LCPLL_CTL, val);
6379
6380         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6381                 DRM_ERROR("LCPLL not locked yet\n");
6382
6383         if (val & LCPLL_CD_SOURCE_FCLK) {
6384                 val = I915_READ(LCPLL_CTL);
6385                 val &= ~LCPLL_CD_SOURCE_FCLK;
6386                 I915_WRITE(LCPLL_CTL, val);
6387
6388                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6389                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6390                         DRM_ERROR("Switching back to LCPLL failed\n");
6391         }
6392
6393         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6394 }
6395
6396 void hsw_enable_pc8_work(struct work_struct *__work)
6397 {
6398         struct drm_i915_private *dev_priv =
6399                 container_of(to_delayed_work(__work), struct drm_i915_private,
6400                              pc8.enable_work);
6401         struct drm_device *dev = dev_priv->dev;
6402         uint32_t val;
6403
6404         if (dev_priv->pc8.enabled)
6405                 return;
6406
6407         DRM_DEBUG_KMS("Enabling package C8+\n");
6408
6409         dev_priv->pc8.enabled = true;
6410
6411         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6412                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6413                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6414                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6415         }
6416
6417         lpt_disable_clkout_dp(dev);
6418         hsw_pc8_disable_interrupts(dev);
6419         hsw_disable_lcpll(dev_priv, true, true);
6420 }
6421
6422 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6423 {
6424         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6425         WARN(dev_priv->pc8.disable_count < 1,
6426              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6427
6428         dev_priv->pc8.disable_count--;
6429         if (dev_priv->pc8.disable_count != 0)
6430                 return;
6431
6432         schedule_delayed_work(&dev_priv->pc8.enable_work,
6433                               msecs_to_jiffies(i915_pc8_timeout));
6434 }
6435
6436 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6437 {
6438         struct drm_device *dev = dev_priv->dev;
6439         uint32_t val;
6440
6441         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6442         WARN(dev_priv->pc8.disable_count < 0,
6443              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6444
6445         dev_priv->pc8.disable_count++;
6446         if (dev_priv->pc8.disable_count != 1)
6447                 return;
6448
6449         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6450         if (!dev_priv->pc8.enabled)
6451                 return;
6452
6453         DRM_DEBUG_KMS("Disabling package C8+\n");
6454
6455         hsw_restore_lcpll(dev_priv);
6456         hsw_pc8_restore_interrupts(dev);
6457         lpt_init_pch_refclk(dev);
6458
6459         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6460                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6461                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6462                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6463         }
6464
6465         intel_prepare_ddi(dev);
6466         i915_gem_init_swizzling(dev);
6467         mutex_lock(&dev_priv->rps.hw_lock);
6468         gen6_update_ring_freq(dev);
6469         mutex_unlock(&dev_priv->rps.hw_lock);
6470         dev_priv->pc8.enabled = false;
6471 }
6472
6473 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6474 {
6475         mutex_lock(&dev_priv->pc8.lock);
6476         __hsw_enable_package_c8(dev_priv);
6477         mutex_unlock(&dev_priv->pc8.lock);
6478 }
6479
6480 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6481 {
6482         mutex_lock(&dev_priv->pc8.lock);
6483         __hsw_disable_package_c8(dev_priv);
6484         mutex_unlock(&dev_priv->pc8.lock);
6485 }
6486
6487 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6488 {
6489         struct drm_device *dev = dev_priv->dev;
6490         struct intel_crtc *crtc;
6491         uint32_t val;
6492
6493         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6494                 if (crtc->base.enabled)
6495                         return false;
6496
6497         /* This case is still possible since we have the i915.disable_power_well
6498          * parameter and also the KVMr or something else might be requesting the
6499          * power well. */
6500         val = I915_READ(HSW_PWR_WELL_DRIVER);
6501         if (val != 0) {
6502                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6503                 return false;
6504         }
6505
6506         return true;
6507 }
6508
6509 /* Since we're called from modeset_global_resources there's no way to
6510  * symmetrically increase and decrease the refcount, so we use
6511  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6512  * or not.
6513  */
6514 static void hsw_update_package_c8(struct drm_device *dev)
6515 {
6516         struct drm_i915_private *dev_priv = dev->dev_private;
6517         bool allow;
6518
6519         if (!i915_enable_pc8)
6520                 return;
6521
6522         mutex_lock(&dev_priv->pc8.lock);
6523
6524         allow = hsw_can_enable_package_c8(dev_priv);
6525
6526         if (allow == dev_priv->pc8.requirements_met)
6527                 goto done;
6528
6529         dev_priv->pc8.requirements_met = allow;
6530
6531         if (allow)
6532                 __hsw_enable_package_c8(dev_priv);
6533         else
6534                 __hsw_disable_package_c8(dev_priv);
6535
6536 done:
6537         mutex_unlock(&dev_priv->pc8.lock);
6538 }
6539
6540 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6541 {
6542         if (!dev_priv->pc8.gpu_idle) {
6543                 dev_priv->pc8.gpu_idle = true;
6544                 hsw_enable_package_c8(dev_priv);
6545         }
6546 }
6547
6548 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6549 {
6550         if (dev_priv->pc8.gpu_idle) {
6551                 dev_priv->pc8.gpu_idle = false;
6552                 hsw_disable_package_c8(dev_priv);
6553         }
6554 }
6555
6556 #define for_each_power_domain(domain, mask)                             \
6557         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6558                 if ((1 << (domain)) & (mask))
6559
6560 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6561                                             enum pipe pipe, bool pfit_enabled)
6562 {
6563         unsigned long mask;
6564         enum transcoder transcoder;
6565
6566         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6567
6568         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6569         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6570         if (pfit_enabled)
6571                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6572
6573         return mask;
6574 }
6575
6576 static void modeset_update_power_wells(struct drm_device *dev)
6577 {
6578         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6579         struct intel_crtc *crtc;
6580
6581         /*
6582          * First get all needed power domains, then put all unneeded, to avoid
6583          * any unnecessary toggling of the power wells.
6584          */
6585         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6586                 enum intel_display_power_domain domain;
6587
6588                 if (!crtc->base.enabled)
6589                         continue;
6590
6591                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6592                                                 crtc->pipe,
6593                                                 crtc->config.pch_pfit.enabled);
6594
6595                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6596                         intel_display_power_get(dev, domain);
6597         }
6598
6599         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6600                 enum intel_display_power_domain domain;
6601
6602                 for_each_power_domain(domain, crtc->enabled_power_domains)
6603                         intel_display_power_put(dev, domain);
6604
6605                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6606         }
6607 }
6608
6609 static void haswell_modeset_global_resources(struct drm_device *dev)
6610 {
6611         modeset_update_power_wells(dev);
6612         hsw_update_package_c8(dev);
6613 }
6614
6615 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6616                                  int x, int y,
6617                                  struct drm_framebuffer *fb)
6618 {
6619         struct drm_device *dev = crtc->dev;
6620         struct drm_i915_private *dev_priv = dev->dev_private;
6621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6622         int plane = intel_crtc->plane;
6623         int ret;
6624
6625         if (!intel_ddi_pll_mode_set(crtc))
6626                 return -EINVAL;
6627
6628         if (intel_crtc->config.has_dp_encoder)
6629                 intel_dp_set_m_n(intel_crtc);
6630
6631         intel_crtc->lowfreq_avail = false;
6632
6633         intel_set_pipe_timings(intel_crtc);
6634
6635         if (intel_crtc->config.has_pch_encoder) {
6636                 intel_cpu_transcoder_set_m_n(intel_crtc,
6637                                              &intel_crtc->config.fdi_m_n);
6638         }
6639
6640         haswell_set_pipeconf(crtc);
6641
6642         intel_set_pipe_csc(crtc);
6643
6644         /* Set up the display plane register */
6645         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6646         POSTING_READ(DSPCNTR(plane));
6647
6648         ret = intel_pipe_set_base(crtc, x, y, fb);
6649
6650         return ret;
6651 }
6652
6653 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6654                                     struct intel_crtc_config *pipe_config)
6655 {
6656         struct drm_device *dev = crtc->base.dev;
6657         struct drm_i915_private *dev_priv = dev->dev_private;
6658         enum intel_display_power_domain pfit_domain;
6659         uint32_t tmp;
6660
6661         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6662         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6663
6664         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6665         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6666                 enum pipe trans_edp_pipe;
6667                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6668                 default:
6669                         WARN(1, "unknown pipe linked to edp transcoder\n");
6670                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6671                 case TRANS_DDI_EDP_INPUT_A_ON:
6672                         trans_edp_pipe = PIPE_A;
6673                         break;
6674                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6675                         trans_edp_pipe = PIPE_B;
6676                         break;
6677                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6678                         trans_edp_pipe = PIPE_C;
6679                         break;
6680                 }
6681
6682                 if (trans_edp_pipe == crtc->pipe)
6683                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6684         }
6685
6686         if (!intel_display_power_enabled(dev,
6687                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6688                 return false;
6689
6690         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6691         if (!(tmp & PIPECONF_ENABLE))
6692                 return false;
6693
6694         /*
6695          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6696          * DDI E. So just check whether this pipe is wired to DDI E and whether
6697          * the PCH transcoder is on.
6698          */
6699         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6700         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6701             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6702                 pipe_config->has_pch_encoder = true;
6703
6704                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6705                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6706                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6707
6708                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6709         }
6710
6711         intel_get_pipe_timings(crtc, pipe_config);
6712
6713         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6714         if (intel_display_power_enabled(dev, pfit_domain))
6715                 ironlake_get_pfit_config(crtc, pipe_config);
6716
6717         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6718                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6719
6720         pipe_config->pixel_multiplier = 1;
6721
6722         return true;
6723 }
6724
6725 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6726                                int x, int y,
6727                                struct drm_framebuffer *fb)
6728 {
6729         struct drm_device *dev = crtc->dev;
6730         struct drm_i915_private *dev_priv = dev->dev_private;
6731         struct intel_encoder *encoder;
6732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6733         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6734         int pipe = intel_crtc->pipe;
6735         int ret;
6736
6737         drm_vblank_pre_modeset(dev, pipe);
6738
6739         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6740
6741         drm_vblank_post_modeset(dev, pipe);
6742
6743         if (ret != 0)
6744                 return ret;
6745
6746         for_each_encoder_on_crtc(dev, crtc, encoder) {
6747                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6748                         encoder->base.base.id,
6749                         drm_get_encoder_name(&encoder->base),
6750                         mode->base.id, mode->name);
6751                 encoder->mode_set(encoder);
6752         }
6753
6754         return 0;
6755 }
6756
6757 static struct {
6758         int clock;
6759         u32 config;
6760 } hdmi_audio_clock[] = {
6761         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6762         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6763         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6764         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6765         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6766         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6767         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6768         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6769         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6770         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6771 };
6772
6773 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6774 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6775 {
6776         int i;
6777
6778         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6779                 if (mode->clock == hdmi_audio_clock[i].clock)
6780                         break;
6781         }
6782
6783         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6784                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6785                 i = 1;
6786         }
6787
6788         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6789                       hdmi_audio_clock[i].clock,
6790                       hdmi_audio_clock[i].config);
6791
6792         return hdmi_audio_clock[i].config;
6793 }
6794
6795 static bool intel_eld_uptodate(struct drm_connector *connector,
6796                                int reg_eldv, uint32_t bits_eldv,
6797                                int reg_elda, uint32_t bits_elda,
6798                                int reg_edid)
6799 {
6800         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6801         uint8_t *eld = connector->eld;
6802         uint32_t i;
6803
6804         i = I915_READ(reg_eldv);
6805         i &= bits_eldv;
6806
6807         if (!eld[0])
6808                 return !i;
6809
6810         if (!i)
6811                 return false;
6812
6813         i = I915_READ(reg_elda);
6814         i &= ~bits_elda;
6815         I915_WRITE(reg_elda, i);
6816
6817         for (i = 0; i < eld[2]; i++)
6818                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6819                         return false;
6820
6821         return true;
6822 }
6823
6824 static void g4x_write_eld(struct drm_connector *connector,
6825                           struct drm_crtc *crtc,
6826                           struct drm_display_mode *mode)
6827 {
6828         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6829         uint8_t *eld = connector->eld;
6830         uint32_t eldv;
6831         uint32_t len;
6832         uint32_t i;
6833
6834         i = I915_READ(G4X_AUD_VID_DID);
6835
6836         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6837                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6838         else
6839                 eldv = G4X_ELDV_DEVCTG;
6840
6841         if (intel_eld_uptodate(connector,
6842                                G4X_AUD_CNTL_ST, eldv,
6843                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6844                                G4X_HDMIW_HDMIEDID))
6845                 return;
6846
6847         i = I915_READ(G4X_AUD_CNTL_ST);
6848         i &= ~(eldv | G4X_ELD_ADDR);
6849         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6850         I915_WRITE(G4X_AUD_CNTL_ST, i);
6851
6852         if (!eld[0])
6853                 return;
6854
6855         len = min_t(uint8_t, eld[2], len);
6856         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6857         for (i = 0; i < len; i++)
6858                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6859
6860         i = I915_READ(G4X_AUD_CNTL_ST);
6861         i |= eldv;
6862         I915_WRITE(G4X_AUD_CNTL_ST, i);
6863 }
6864
6865 static void haswell_write_eld(struct drm_connector *connector,
6866                               struct drm_crtc *crtc,
6867                               struct drm_display_mode *mode)
6868 {
6869         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6870         uint8_t *eld = connector->eld;
6871         struct drm_device *dev = crtc->dev;
6872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6873         uint32_t eldv;
6874         uint32_t i;
6875         int len;
6876         int pipe = to_intel_crtc(crtc)->pipe;
6877         int tmp;
6878
6879         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6880         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6881         int aud_config = HSW_AUD_CFG(pipe);
6882         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6883
6884
6885         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6886
6887         /* Audio output enable */
6888         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6889         tmp = I915_READ(aud_cntrl_st2);
6890         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6891         I915_WRITE(aud_cntrl_st2, tmp);
6892
6893         /* Wait for 1 vertical blank */
6894         intel_wait_for_vblank(dev, pipe);
6895
6896         /* Set ELD valid state */
6897         tmp = I915_READ(aud_cntrl_st2);
6898         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6899         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6900         I915_WRITE(aud_cntrl_st2, tmp);
6901         tmp = I915_READ(aud_cntrl_st2);
6902         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6903
6904         /* Enable HDMI mode */
6905         tmp = I915_READ(aud_config);
6906         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6907         /* clear N_programing_enable and N_value_index */
6908         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6909         I915_WRITE(aud_config, tmp);
6910
6911         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6912
6913         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6914         intel_crtc->eld_vld = true;
6915
6916         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6917                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6918                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6919                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6920         } else {
6921                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
6922         }
6923
6924         if (intel_eld_uptodate(connector,
6925                                aud_cntrl_st2, eldv,
6926                                aud_cntl_st, IBX_ELD_ADDRESS,
6927                                hdmiw_hdmiedid))
6928                 return;
6929
6930         i = I915_READ(aud_cntrl_st2);
6931         i &= ~eldv;
6932         I915_WRITE(aud_cntrl_st2, i);
6933
6934         if (!eld[0])
6935                 return;
6936
6937         i = I915_READ(aud_cntl_st);
6938         i &= ~IBX_ELD_ADDRESS;
6939         I915_WRITE(aud_cntl_st, i);
6940         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6941         DRM_DEBUG_DRIVER("port num:%d\n", i);
6942
6943         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6944         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6945         for (i = 0; i < len; i++)
6946                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6947
6948         i = I915_READ(aud_cntrl_st2);
6949         i |= eldv;
6950         I915_WRITE(aud_cntrl_st2, i);
6951
6952 }
6953
6954 static void ironlake_write_eld(struct drm_connector *connector,
6955                                struct drm_crtc *crtc,
6956                                struct drm_display_mode *mode)
6957 {
6958         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6959         uint8_t *eld = connector->eld;
6960         uint32_t eldv;
6961         uint32_t i;
6962         int len;
6963         int hdmiw_hdmiedid;
6964         int aud_config;
6965         int aud_cntl_st;
6966         int aud_cntrl_st2;
6967         int pipe = to_intel_crtc(crtc)->pipe;
6968
6969         if (HAS_PCH_IBX(connector->dev)) {
6970                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6971                 aud_config = IBX_AUD_CFG(pipe);
6972                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6973                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6974         } else {
6975                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6976                 aud_config = CPT_AUD_CFG(pipe);
6977                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6978                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6979         }
6980
6981         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6982
6983         i = I915_READ(aud_cntl_st);
6984         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6985         if (!i) {
6986                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6987                 /* operate blindly on all ports */
6988                 eldv = IBX_ELD_VALIDB;
6989                 eldv |= IBX_ELD_VALIDB << 4;
6990                 eldv |= IBX_ELD_VALIDB << 8;
6991         } else {
6992                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6993                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6994         }
6995
6996         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6997                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6998                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6999                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7000         } else {
7001                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7002         }
7003
7004         if (intel_eld_uptodate(connector,
7005                                aud_cntrl_st2, eldv,
7006                                aud_cntl_st, IBX_ELD_ADDRESS,
7007                                hdmiw_hdmiedid))
7008                 return;
7009
7010         i = I915_READ(aud_cntrl_st2);
7011         i &= ~eldv;
7012         I915_WRITE(aud_cntrl_st2, i);
7013
7014         if (!eld[0])
7015                 return;
7016
7017         i = I915_READ(aud_cntl_st);
7018         i &= ~IBX_ELD_ADDRESS;
7019         I915_WRITE(aud_cntl_st, i);
7020
7021         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7022         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7023         for (i = 0; i < len; i++)
7024                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7025
7026         i = I915_READ(aud_cntrl_st2);
7027         i |= eldv;
7028         I915_WRITE(aud_cntrl_st2, i);
7029 }
7030
7031 void intel_write_eld(struct drm_encoder *encoder,
7032                      struct drm_display_mode *mode)
7033 {
7034         struct drm_crtc *crtc = encoder->crtc;
7035         struct drm_connector *connector;
7036         struct drm_device *dev = encoder->dev;
7037         struct drm_i915_private *dev_priv = dev->dev_private;
7038
7039         connector = drm_select_eld(encoder, mode);
7040         if (!connector)
7041                 return;
7042
7043         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7044                          connector->base.id,
7045                          drm_get_connector_name(connector),
7046                          connector->encoder->base.id,
7047                          drm_get_encoder_name(connector->encoder));
7048
7049         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7050
7051         if (dev_priv->display.write_eld)
7052                 dev_priv->display.write_eld(connector, crtc, mode);
7053 }
7054
7055 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7056 {
7057         struct drm_device *dev = crtc->dev;
7058         struct drm_i915_private *dev_priv = dev->dev_private;
7059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7060         bool visible = base != 0;
7061         u32 cntl;
7062
7063         if (intel_crtc->cursor_visible == visible)
7064                 return;
7065
7066         cntl = I915_READ(_CURACNTR);
7067         if (visible) {
7068                 /* On these chipsets we can only modify the base whilst
7069                  * the cursor is disabled.
7070                  */
7071                 I915_WRITE(_CURABASE, base);
7072
7073                 cntl &= ~(CURSOR_FORMAT_MASK);
7074                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7075                 cntl |= CURSOR_ENABLE |
7076                         CURSOR_GAMMA_ENABLE |
7077                         CURSOR_FORMAT_ARGB;
7078         } else
7079                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7080         I915_WRITE(_CURACNTR, cntl);
7081
7082         intel_crtc->cursor_visible = visible;
7083 }
7084
7085 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7086 {
7087         struct drm_device *dev = crtc->dev;
7088         struct drm_i915_private *dev_priv = dev->dev_private;
7089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090         int pipe = intel_crtc->pipe;
7091         bool visible = base != 0;
7092
7093         if (intel_crtc->cursor_visible != visible) {
7094                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7095                 if (base) {
7096                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7097                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7098                         cntl |= pipe << 28; /* Connect to correct pipe */
7099                 } else {
7100                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7101                         cntl |= CURSOR_MODE_DISABLE;
7102                 }
7103                 I915_WRITE(CURCNTR(pipe), cntl);
7104
7105                 intel_crtc->cursor_visible = visible;
7106         }
7107         /* and commit changes on next vblank */
7108         I915_WRITE(CURBASE(pipe), base);
7109 }
7110
7111 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7112 {
7113         struct drm_device *dev = crtc->dev;
7114         struct drm_i915_private *dev_priv = dev->dev_private;
7115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7116         int pipe = intel_crtc->pipe;
7117         bool visible = base != 0;
7118
7119         if (intel_crtc->cursor_visible != visible) {
7120                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7121                 if (base) {
7122                         cntl &= ~CURSOR_MODE;
7123                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7124                 } else {
7125                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7126                         cntl |= CURSOR_MODE_DISABLE;
7127                 }
7128                 if (IS_HASWELL(dev)) {
7129                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7130                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7131                 }
7132                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7133
7134                 intel_crtc->cursor_visible = visible;
7135         }
7136         /* and commit changes on next vblank */
7137         I915_WRITE(CURBASE_IVB(pipe), base);
7138 }
7139
7140 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7141 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7142                                      bool on)
7143 {
7144         struct drm_device *dev = crtc->dev;
7145         struct drm_i915_private *dev_priv = dev->dev_private;
7146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7147         int pipe = intel_crtc->pipe;
7148         int x = intel_crtc->cursor_x;
7149         int y = intel_crtc->cursor_y;
7150         u32 base = 0, pos = 0;
7151         bool visible;
7152
7153         if (on)
7154                 base = intel_crtc->cursor_addr;
7155
7156         if (x >= intel_crtc->config.pipe_src_w)
7157                 base = 0;
7158
7159         if (y >= intel_crtc->config.pipe_src_h)
7160                 base = 0;
7161
7162         if (x < 0) {
7163                 if (x + intel_crtc->cursor_width <= 0)
7164                         base = 0;
7165
7166                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7167                 x = -x;
7168         }
7169         pos |= x << CURSOR_X_SHIFT;
7170
7171         if (y < 0) {
7172                 if (y + intel_crtc->cursor_height <= 0)
7173                         base = 0;
7174
7175                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7176                 y = -y;
7177         }
7178         pos |= y << CURSOR_Y_SHIFT;
7179
7180         visible = base != 0;
7181         if (!visible && !intel_crtc->cursor_visible)
7182                 return;
7183
7184         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7185                 I915_WRITE(CURPOS_IVB(pipe), pos);
7186                 ivb_update_cursor(crtc, base);
7187         } else {
7188                 I915_WRITE(CURPOS(pipe), pos);
7189                 if (IS_845G(dev) || IS_I865G(dev))
7190                         i845_update_cursor(crtc, base);
7191                 else
7192                         i9xx_update_cursor(crtc, base);
7193         }
7194 }
7195
7196 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7197                                  struct drm_file *file,
7198                                  uint32_t handle,
7199                                  uint32_t width, uint32_t height)
7200 {
7201         struct drm_device *dev = crtc->dev;
7202         struct drm_i915_private *dev_priv = dev->dev_private;
7203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7204         struct drm_i915_gem_object *obj;
7205         uint32_t addr;
7206         int ret;
7207
7208         /* if we want to turn off the cursor ignore width and height */
7209         if (!handle) {
7210                 DRM_DEBUG_KMS("cursor off\n");
7211                 addr = 0;
7212                 obj = NULL;
7213                 mutex_lock(&dev->struct_mutex);
7214                 goto finish;
7215         }
7216
7217         /* Currently we only support 64x64 cursors */
7218         if (width != 64 || height != 64) {
7219                 DRM_ERROR("we currently only support 64x64 cursors\n");
7220                 return -EINVAL;
7221         }
7222
7223         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7224         if (&obj->base == NULL)
7225                 return -ENOENT;
7226
7227         if (obj->base.size < width * height * 4) {
7228                 DRM_ERROR("buffer is to small\n");
7229                 ret = -ENOMEM;
7230                 goto fail;
7231         }
7232
7233         /* we only need to pin inside GTT if cursor is non-phy */
7234         mutex_lock(&dev->struct_mutex);
7235         if (!dev_priv->info->cursor_needs_physical) {
7236                 unsigned alignment;
7237
7238                 if (obj->tiling_mode) {
7239                         DRM_ERROR("cursor cannot be tiled\n");
7240                         ret = -EINVAL;
7241                         goto fail_locked;
7242                 }
7243
7244                 /* Note that the w/a also requires 2 PTE of padding following
7245                  * the bo. We currently fill all unused PTE with the shadow
7246                  * page and so we should always have valid PTE following the
7247                  * cursor preventing the VT-d warning.
7248                  */
7249                 alignment = 0;
7250                 if (need_vtd_wa(dev))
7251                         alignment = 64*1024;
7252
7253                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7254                 if (ret) {
7255                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7256                         goto fail_locked;
7257                 }
7258
7259                 ret = i915_gem_object_put_fence(obj);
7260                 if (ret) {
7261                         DRM_ERROR("failed to release fence for cursor");
7262                         goto fail_unpin;
7263                 }
7264
7265                 addr = i915_gem_obj_ggtt_offset(obj);
7266         } else {
7267                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7268                 ret = i915_gem_attach_phys_object(dev, obj,
7269                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7270                                                   align);
7271                 if (ret) {
7272                         DRM_ERROR("failed to attach phys object\n");
7273                         goto fail_locked;
7274                 }
7275                 addr = obj->phys_obj->handle->busaddr;
7276         }
7277
7278         if (IS_GEN2(dev))
7279                 I915_WRITE(CURSIZE, (height << 12) | width);
7280
7281  finish:
7282         if (intel_crtc->cursor_bo) {
7283                 if (dev_priv->info->cursor_needs_physical) {
7284                         if (intel_crtc->cursor_bo != obj)
7285                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7286                 } else
7287                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7288                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7289         }
7290
7291         mutex_unlock(&dev->struct_mutex);
7292
7293         intel_crtc->cursor_addr = addr;
7294         intel_crtc->cursor_bo = obj;
7295         intel_crtc->cursor_width = width;
7296         intel_crtc->cursor_height = height;
7297
7298         if (intel_crtc->active)
7299                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7300
7301         return 0;
7302 fail_unpin:
7303         i915_gem_object_unpin_from_display_plane(obj);
7304 fail_locked:
7305         mutex_unlock(&dev->struct_mutex);
7306 fail:
7307         drm_gem_object_unreference_unlocked(&obj->base);
7308         return ret;
7309 }
7310
7311 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7312 {
7313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314
7315         intel_crtc->cursor_x = x;
7316         intel_crtc->cursor_y = y;
7317
7318         if (intel_crtc->active)
7319                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7320
7321         return 0;
7322 }
7323
7324 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7325                                  u16 *blue, uint32_t start, uint32_t size)
7326 {
7327         int end = (start + size > 256) ? 256 : start + size, i;
7328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7329
7330         for (i = start; i < end; i++) {
7331                 intel_crtc->lut_r[i] = red[i] >> 8;
7332                 intel_crtc->lut_g[i] = green[i] >> 8;
7333                 intel_crtc->lut_b[i] = blue[i] >> 8;
7334         }
7335
7336         intel_crtc_load_lut(crtc);
7337 }
7338
7339 /* VESA 640x480x72Hz mode to set on the pipe */
7340 static struct drm_display_mode load_detect_mode = {
7341         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7342                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7343 };
7344
7345 static struct drm_framebuffer *
7346 intel_framebuffer_create(struct drm_device *dev,
7347                          struct drm_mode_fb_cmd2 *mode_cmd,
7348                          struct drm_i915_gem_object *obj)
7349 {
7350         struct intel_framebuffer *intel_fb;
7351         int ret;
7352
7353         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7354         if (!intel_fb) {
7355                 drm_gem_object_unreference_unlocked(&obj->base);
7356                 return ERR_PTR(-ENOMEM);
7357         }
7358
7359         ret = i915_mutex_lock_interruptible(dev);
7360         if (ret)
7361                 goto err;
7362
7363         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7364         mutex_unlock(&dev->struct_mutex);
7365         if (ret)
7366                 goto err;
7367
7368         return &intel_fb->base;
7369 err:
7370         drm_gem_object_unreference_unlocked(&obj->base);
7371         kfree(intel_fb);
7372
7373         return ERR_PTR(ret);
7374 }
7375
7376 static u32
7377 intel_framebuffer_pitch_for_width(int width, int bpp)
7378 {
7379         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7380         return ALIGN(pitch, 64);
7381 }
7382
7383 static u32
7384 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7385 {
7386         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7387         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7388 }
7389
7390 static struct drm_framebuffer *
7391 intel_framebuffer_create_for_mode(struct drm_device *dev,
7392                                   struct drm_display_mode *mode,
7393                                   int depth, int bpp)
7394 {
7395         struct drm_i915_gem_object *obj;
7396         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7397
7398         obj = i915_gem_alloc_object(dev,
7399                                     intel_framebuffer_size_for_mode(mode, bpp));
7400         if (obj == NULL)
7401                 return ERR_PTR(-ENOMEM);
7402
7403         mode_cmd.width = mode->hdisplay;
7404         mode_cmd.height = mode->vdisplay;
7405         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7406                                                                 bpp);
7407         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7408
7409         return intel_framebuffer_create(dev, &mode_cmd, obj);
7410 }
7411
7412 static struct drm_framebuffer *
7413 mode_fits_in_fbdev(struct drm_device *dev,
7414                    struct drm_display_mode *mode)
7415 {
7416 #ifdef CONFIG_DRM_I915_FBDEV
7417         struct drm_i915_private *dev_priv = dev->dev_private;
7418         struct drm_i915_gem_object *obj;
7419         struct drm_framebuffer *fb;
7420
7421         if (dev_priv->fbdev == NULL)
7422                 return NULL;
7423
7424         obj = dev_priv->fbdev->ifb.obj;
7425         if (obj == NULL)
7426                 return NULL;
7427
7428         fb = &dev_priv->fbdev->ifb.base;
7429         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7430                                                                fb->bits_per_pixel))
7431                 return NULL;
7432
7433         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7434                 return NULL;
7435
7436         return fb;
7437 #else
7438         return NULL;
7439 #endif
7440 }
7441
7442 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7443                                 struct drm_display_mode *mode,
7444                                 struct intel_load_detect_pipe *old)
7445 {
7446         struct intel_crtc *intel_crtc;
7447         struct intel_encoder *intel_encoder =
7448                 intel_attached_encoder(connector);
7449         struct drm_crtc *possible_crtc;
7450         struct drm_encoder *encoder = &intel_encoder->base;
7451         struct drm_crtc *crtc = NULL;
7452         struct drm_device *dev = encoder->dev;
7453         struct drm_framebuffer *fb;
7454         int i = -1;
7455
7456         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7457                       connector->base.id, drm_get_connector_name(connector),
7458                       encoder->base.id, drm_get_encoder_name(encoder));
7459
7460         /*
7461          * Algorithm gets a little messy:
7462          *
7463          *   - if the connector already has an assigned crtc, use it (but make
7464          *     sure it's on first)
7465          *
7466          *   - try to find the first unused crtc that can drive this connector,
7467          *     and use that if we find one
7468          */
7469
7470         /* See if we already have a CRTC for this connector */
7471         if (encoder->crtc) {
7472                 crtc = encoder->crtc;
7473
7474                 mutex_lock(&crtc->mutex);
7475
7476                 old->dpms_mode = connector->dpms;
7477                 old->load_detect_temp = false;
7478
7479                 /* Make sure the crtc and connector are running */
7480                 if (connector->dpms != DRM_MODE_DPMS_ON)
7481                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7482
7483                 return true;
7484         }
7485
7486         /* Find an unused one (if possible) */
7487         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7488                 i++;
7489                 if (!(encoder->possible_crtcs & (1 << i)))
7490                         continue;
7491                 if (!possible_crtc->enabled) {
7492                         crtc = possible_crtc;
7493                         break;
7494                 }
7495         }
7496
7497         /*
7498          * If we didn't find an unused CRTC, don't use any.
7499          */
7500         if (!crtc) {
7501                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7502                 return false;
7503         }
7504
7505         mutex_lock(&crtc->mutex);
7506         intel_encoder->new_crtc = to_intel_crtc(crtc);
7507         to_intel_connector(connector)->new_encoder = intel_encoder;
7508
7509         intel_crtc = to_intel_crtc(crtc);
7510         old->dpms_mode = connector->dpms;
7511         old->load_detect_temp = true;
7512         old->release_fb = NULL;
7513
7514         if (!mode)
7515                 mode = &load_detect_mode;
7516
7517         /* We need a framebuffer large enough to accommodate all accesses
7518          * that the plane may generate whilst we perform load detection.
7519          * We can not rely on the fbcon either being present (we get called
7520          * during its initialisation to detect all boot displays, or it may
7521          * not even exist) or that it is large enough to satisfy the
7522          * requested mode.
7523          */
7524         fb = mode_fits_in_fbdev(dev, mode);
7525         if (fb == NULL) {
7526                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7527                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7528                 old->release_fb = fb;
7529         } else
7530                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7531         if (IS_ERR(fb)) {
7532                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7533                 mutex_unlock(&crtc->mutex);
7534                 return false;
7535         }
7536
7537         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7538                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7539                 if (old->release_fb)
7540                         old->release_fb->funcs->destroy(old->release_fb);
7541                 mutex_unlock(&crtc->mutex);
7542                 return false;
7543         }
7544
7545         /* let the connector get through one full cycle before testing */
7546         intel_wait_for_vblank(dev, intel_crtc->pipe);
7547         return true;
7548 }
7549
7550 void intel_release_load_detect_pipe(struct drm_connector *connector,
7551                                     struct intel_load_detect_pipe *old)
7552 {
7553         struct intel_encoder *intel_encoder =
7554                 intel_attached_encoder(connector);
7555         struct drm_encoder *encoder = &intel_encoder->base;
7556         struct drm_crtc *crtc = encoder->crtc;
7557
7558         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7559                       connector->base.id, drm_get_connector_name(connector),
7560                       encoder->base.id, drm_get_encoder_name(encoder));
7561
7562         if (old->load_detect_temp) {
7563                 to_intel_connector(connector)->new_encoder = NULL;
7564                 intel_encoder->new_crtc = NULL;
7565                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7566
7567                 if (old->release_fb) {
7568                         drm_framebuffer_unregister_private(old->release_fb);
7569                         drm_framebuffer_unreference(old->release_fb);
7570                 }
7571
7572                 mutex_unlock(&crtc->mutex);
7573                 return;
7574         }
7575
7576         /* Switch crtc and encoder back off if necessary */
7577         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7578                 connector->funcs->dpms(connector, old->dpms_mode);
7579
7580         mutex_unlock(&crtc->mutex);
7581 }
7582
7583 static int i9xx_pll_refclk(struct drm_device *dev,
7584                            const struct intel_crtc_config *pipe_config)
7585 {
7586         struct drm_i915_private *dev_priv = dev->dev_private;
7587         u32 dpll = pipe_config->dpll_hw_state.dpll;
7588
7589         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7590                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7591         else if (HAS_PCH_SPLIT(dev))
7592                 return 120000;
7593         else if (!IS_GEN2(dev))
7594                 return 96000;
7595         else
7596                 return 48000;
7597 }
7598
7599 /* Returns the clock of the currently programmed mode of the given pipe. */
7600 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7601                                 struct intel_crtc_config *pipe_config)
7602 {
7603         struct drm_device *dev = crtc->base.dev;
7604         struct drm_i915_private *dev_priv = dev->dev_private;
7605         int pipe = pipe_config->cpu_transcoder;
7606         u32 dpll = pipe_config->dpll_hw_state.dpll;
7607         u32 fp;
7608         intel_clock_t clock;
7609         int refclk = i9xx_pll_refclk(dev, pipe_config);
7610
7611         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7612                 fp = pipe_config->dpll_hw_state.fp0;
7613         else
7614                 fp = pipe_config->dpll_hw_state.fp1;
7615
7616         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7617         if (IS_PINEVIEW(dev)) {
7618                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7619                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7620         } else {
7621                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7622                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7623         }
7624
7625         if (!IS_GEN2(dev)) {
7626                 if (IS_PINEVIEW(dev))
7627                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7628                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7629                 else
7630                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7631                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7632
7633                 switch (dpll & DPLL_MODE_MASK) {
7634                 case DPLLB_MODE_DAC_SERIAL:
7635                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7636                                 5 : 10;
7637                         break;
7638                 case DPLLB_MODE_LVDS:
7639                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7640                                 7 : 14;
7641                         break;
7642                 default:
7643                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7644                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7645                         return;
7646                 }
7647
7648                 if (IS_PINEVIEW(dev))
7649                         pineview_clock(refclk, &clock);
7650                 else
7651                         i9xx_clock(refclk, &clock);
7652         } else {
7653                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7654
7655                 if (is_lvds) {
7656                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7657                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7658                         clock.p2 = 14;
7659                 } else {
7660                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7661                                 clock.p1 = 2;
7662                         else {
7663                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7664                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7665                         }
7666                         if (dpll & PLL_P2_DIVIDE_BY_4)
7667                                 clock.p2 = 4;
7668                         else
7669                                 clock.p2 = 2;
7670                 }
7671
7672                 i9xx_clock(refclk, &clock);
7673         }
7674
7675         /*
7676          * This value includes pixel_multiplier. We will use
7677          * port_clock to compute adjusted_mode.crtc_clock in the
7678          * encoder's get_config() function.
7679          */
7680         pipe_config->port_clock = clock.dot;
7681 }
7682
7683 int intel_dotclock_calculate(int link_freq,
7684                              const struct intel_link_m_n *m_n)
7685 {
7686         /*
7687          * The calculation for the data clock is:
7688          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7689          * But we want to avoid losing precison if possible, so:
7690          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7691          *
7692          * and the link clock is simpler:
7693          * link_clock = (m * link_clock) / n
7694          */
7695
7696         if (!m_n->link_n)
7697                 return 0;
7698
7699         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7700 }
7701
7702 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7703                                    struct intel_crtc_config *pipe_config)
7704 {
7705         struct drm_device *dev = crtc->base.dev;
7706
7707         /* read out port_clock from the DPLL */
7708         i9xx_crtc_clock_get(crtc, pipe_config);
7709
7710         /*
7711          * This value does not include pixel_multiplier.
7712          * We will check that port_clock and adjusted_mode.crtc_clock
7713          * agree once we know their relationship in the encoder's
7714          * get_config() function.
7715          */
7716         pipe_config->adjusted_mode.crtc_clock =
7717                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7718                                          &pipe_config->fdi_m_n);
7719 }
7720
7721 /** Returns the currently programmed mode of the given pipe. */
7722 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7723                                              struct drm_crtc *crtc)
7724 {
7725         struct drm_i915_private *dev_priv = dev->dev_private;
7726         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7727         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7728         struct drm_display_mode *mode;
7729         struct intel_crtc_config pipe_config;
7730         int htot = I915_READ(HTOTAL(cpu_transcoder));
7731         int hsync = I915_READ(HSYNC(cpu_transcoder));
7732         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7733         int vsync = I915_READ(VSYNC(cpu_transcoder));
7734         enum pipe pipe = intel_crtc->pipe;
7735
7736         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7737         if (!mode)
7738                 return NULL;
7739
7740         /*
7741          * Construct a pipe_config sufficient for getting the clock info
7742          * back out of crtc_clock_get.
7743          *
7744          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7745          * to use a real value here instead.
7746          */
7747         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7748         pipe_config.pixel_multiplier = 1;
7749         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7750         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7751         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7752         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7753
7754         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7755         mode->hdisplay = (htot & 0xffff) + 1;
7756         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7757         mode->hsync_start = (hsync & 0xffff) + 1;
7758         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7759         mode->vdisplay = (vtot & 0xffff) + 1;
7760         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7761         mode->vsync_start = (vsync & 0xffff) + 1;
7762         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7763
7764         drm_mode_set_name(mode);
7765
7766         return mode;
7767 }
7768
7769 static void intel_increase_pllclock(struct drm_crtc *crtc)
7770 {
7771         struct drm_device *dev = crtc->dev;
7772         drm_i915_private_t *dev_priv = dev->dev_private;
7773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7774         int pipe = intel_crtc->pipe;
7775         int dpll_reg = DPLL(pipe);
7776         int dpll;
7777
7778         if (HAS_PCH_SPLIT(dev))
7779                 return;
7780
7781         if (!dev_priv->lvds_downclock_avail)
7782                 return;
7783
7784         dpll = I915_READ(dpll_reg);
7785         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7786                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7787
7788                 assert_panel_unlocked(dev_priv, pipe);
7789
7790                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7791                 I915_WRITE(dpll_reg, dpll);
7792                 intel_wait_for_vblank(dev, pipe);
7793
7794                 dpll = I915_READ(dpll_reg);
7795                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7796                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7797         }
7798 }
7799
7800 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7801 {
7802         struct drm_device *dev = crtc->dev;
7803         drm_i915_private_t *dev_priv = dev->dev_private;
7804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7805
7806         if (HAS_PCH_SPLIT(dev))
7807                 return;
7808
7809         if (!dev_priv->lvds_downclock_avail)
7810                 return;
7811
7812         /*
7813          * Since this is called by a timer, we should never get here in
7814          * the manual case.
7815          */
7816         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7817                 int pipe = intel_crtc->pipe;
7818                 int dpll_reg = DPLL(pipe);
7819                 int dpll;
7820
7821                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7822
7823                 assert_panel_unlocked(dev_priv, pipe);
7824
7825                 dpll = I915_READ(dpll_reg);
7826                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7827                 I915_WRITE(dpll_reg, dpll);
7828                 intel_wait_for_vblank(dev, pipe);
7829                 dpll = I915_READ(dpll_reg);
7830                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7831                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7832         }
7833
7834 }
7835
7836 void intel_mark_busy(struct drm_device *dev)
7837 {
7838         struct drm_i915_private *dev_priv = dev->dev_private;
7839
7840         hsw_package_c8_gpu_busy(dev_priv);
7841         i915_update_gfx_val(dev_priv);
7842 }
7843
7844 void intel_mark_idle(struct drm_device *dev)
7845 {
7846         struct drm_i915_private *dev_priv = dev->dev_private;
7847         struct drm_crtc *crtc;
7848
7849         hsw_package_c8_gpu_idle(dev_priv);
7850
7851         if (!i915_powersave)
7852                 return;
7853
7854         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7855                 if (!crtc->fb)
7856                         continue;
7857
7858                 intel_decrease_pllclock(crtc);
7859         }
7860
7861         if (dev_priv->info->gen >= 6)
7862                 gen6_rps_idle(dev->dev_private);
7863 }
7864
7865 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7866                         struct intel_ring_buffer *ring)
7867 {
7868         struct drm_device *dev = obj->base.dev;
7869         struct drm_crtc *crtc;
7870
7871         if (!i915_powersave)
7872                 return;
7873
7874         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7875                 if (!crtc->fb)
7876                         continue;
7877
7878                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7879                         continue;
7880
7881                 intel_increase_pllclock(crtc);
7882                 if (ring && intel_fbc_enabled(dev))
7883                         ring->fbc_dirty = true;
7884         }
7885 }
7886
7887 static void intel_crtc_destroy(struct drm_crtc *crtc)
7888 {
7889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7890         struct drm_device *dev = crtc->dev;
7891         struct intel_unpin_work *work;
7892         unsigned long flags;
7893
7894         spin_lock_irqsave(&dev->event_lock, flags);
7895         work = intel_crtc->unpin_work;
7896         intel_crtc->unpin_work = NULL;
7897         spin_unlock_irqrestore(&dev->event_lock, flags);
7898
7899         if (work) {
7900                 cancel_work_sync(&work->work);
7901                 kfree(work);
7902         }
7903
7904         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7905
7906         drm_crtc_cleanup(crtc);
7907
7908         kfree(intel_crtc);
7909 }
7910
7911 static void intel_unpin_work_fn(struct work_struct *__work)
7912 {
7913         struct intel_unpin_work *work =
7914                 container_of(__work, struct intel_unpin_work, work);
7915         struct drm_device *dev = work->crtc->dev;
7916
7917         mutex_lock(&dev->struct_mutex);
7918         intel_unpin_fb_obj(work->old_fb_obj);
7919         drm_gem_object_unreference(&work->pending_flip_obj->base);
7920         drm_gem_object_unreference(&work->old_fb_obj->base);
7921
7922         intel_update_fbc(dev);
7923         mutex_unlock(&dev->struct_mutex);
7924
7925         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7926         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7927
7928         kfree(work);
7929 }
7930
7931 static void do_intel_finish_page_flip(struct drm_device *dev,
7932                                       struct drm_crtc *crtc)
7933 {
7934         drm_i915_private_t *dev_priv = dev->dev_private;
7935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7936         struct intel_unpin_work *work;
7937         unsigned long flags;
7938
7939         /* Ignore early vblank irqs */
7940         if (intel_crtc == NULL)
7941                 return;
7942
7943         spin_lock_irqsave(&dev->event_lock, flags);
7944         work = intel_crtc->unpin_work;
7945
7946         /* Ensure we don't miss a work->pending update ... */
7947         smp_rmb();
7948
7949         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7950                 spin_unlock_irqrestore(&dev->event_lock, flags);
7951                 return;
7952         }
7953
7954         /* and that the unpin work is consistent wrt ->pending. */
7955         smp_rmb();
7956
7957         intel_crtc->unpin_work = NULL;
7958
7959         if (work->event)
7960                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7961
7962         drm_vblank_put(dev, intel_crtc->pipe);
7963
7964         spin_unlock_irqrestore(&dev->event_lock, flags);
7965
7966         wake_up_all(&dev_priv->pending_flip_queue);
7967
7968         queue_work(dev_priv->wq, &work->work);
7969
7970         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7971 }
7972
7973 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7974 {
7975         drm_i915_private_t *dev_priv = dev->dev_private;
7976         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7977
7978         do_intel_finish_page_flip(dev, crtc);
7979 }
7980
7981 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7982 {
7983         drm_i915_private_t *dev_priv = dev->dev_private;
7984         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7985
7986         do_intel_finish_page_flip(dev, crtc);
7987 }
7988
7989 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7990 {
7991         drm_i915_private_t *dev_priv = dev->dev_private;
7992         struct intel_crtc *intel_crtc =
7993                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7994         unsigned long flags;
7995
7996         /* NB: An MMIO update of the plane base pointer will also
7997          * generate a page-flip completion irq, i.e. every modeset
7998          * is also accompanied by a spurious intel_prepare_page_flip().
7999          */
8000         spin_lock_irqsave(&dev->event_lock, flags);
8001         if (intel_crtc->unpin_work)
8002                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8003         spin_unlock_irqrestore(&dev->event_lock, flags);
8004 }
8005
8006 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8007 {
8008         /* Ensure that the work item is consistent when activating it ... */
8009         smp_wmb();
8010         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8011         /* and that it is marked active as soon as the irq could fire. */
8012         smp_wmb();
8013 }
8014
8015 static int intel_gen2_queue_flip(struct drm_device *dev,
8016                                  struct drm_crtc *crtc,
8017                                  struct drm_framebuffer *fb,
8018                                  struct drm_i915_gem_object *obj,
8019                                  uint32_t flags)
8020 {
8021         struct drm_i915_private *dev_priv = dev->dev_private;
8022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8023         u32 flip_mask;
8024         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8025         int ret;
8026
8027         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8028         if (ret)
8029                 goto err;
8030
8031         ret = intel_ring_begin(ring, 6);
8032         if (ret)
8033                 goto err_unpin;
8034
8035         /* Can't queue multiple flips, so wait for the previous
8036          * one to finish before executing the next.
8037          */
8038         if (intel_crtc->plane)
8039                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8040         else
8041                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8042         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8043         intel_ring_emit(ring, MI_NOOP);
8044         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8045                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8046         intel_ring_emit(ring, fb->pitches[0]);
8047         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8048         intel_ring_emit(ring, 0); /* aux display base address, unused */
8049
8050         intel_mark_page_flip_active(intel_crtc);
8051         __intel_ring_advance(ring);
8052         return 0;
8053
8054 err_unpin:
8055         intel_unpin_fb_obj(obj);
8056 err:
8057         return ret;
8058 }
8059
8060 static int intel_gen3_queue_flip(struct drm_device *dev,
8061                                  struct drm_crtc *crtc,
8062                                  struct drm_framebuffer *fb,
8063                                  struct drm_i915_gem_object *obj,
8064                                  uint32_t flags)
8065 {
8066         struct drm_i915_private *dev_priv = dev->dev_private;
8067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8068         u32 flip_mask;
8069         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8070         int ret;
8071
8072         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8073         if (ret)
8074                 goto err;
8075
8076         ret = intel_ring_begin(ring, 6);
8077         if (ret)
8078                 goto err_unpin;
8079
8080         if (intel_crtc->plane)
8081                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8082         else
8083                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8084         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8085         intel_ring_emit(ring, MI_NOOP);
8086         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8087                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8088         intel_ring_emit(ring, fb->pitches[0]);
8089         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8090         intel_ring_emit(ring, MI_NOOP);
8091
8092         intel_mark_page_flip_active(intel_crtc);
8093         __intel_ring_advance(ring);
8094         return 0;
8095
8096 err_unpin:
8097         intel_unpin_fb_obj(obj);
8098 err:
8099         return ret;
8100 }
8101
8102 static int intel_gen4_queue_flip(struct drm_device *dev,
8103                                  struct drm_crtc *crtc,
8104                                  struct drm_framebuffer *fb,
8105                                  struct drm_i915_gem_object *obj,
8106                                  uint32_t flags)
8107 {
8108         struct drm_i915_private *dev_priv = dev->dev_private;
8109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8110         uint32_t pf, pipesrc;
8111         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8112         int ret;
8113
8114         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8115         if (ret)
8116                 goto err;
8117
8118         ret = intel_ring_begin(ring, 4);
8119         if (ret)
8120                 goto err_unpin;
8121
8122         /* i965+ uses the linear or tiled offsets from the
8123          * Display Registers (which do not change across a page-flip)
8124          * so we need only reprogram the base address.
8125          */
8126         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8127                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8128         intel_ring_emit(ring, fb->pitches[0]);
8129         intel_ring_emit(ring,
8130                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8131                         obj->tiling_mode);
8132
8133         /* XXX Enabling the panel-fitter across page-flip is so far
8134          * untested on non-native modes, so ignore it for now.
8135          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8136          */
8137         pf = 0;
8138         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8139         intel_ring_emit(ring, pf | pipesrc);
8140
8141         intel_mark_page_flip_active(intel_crtc);
8142         __intel_ring_advance(ring);
8143         return 0;
8144
8145 err_unpin:
8146         intel_unpin_fb_obj(obj);
8147 err:
8148         return ret;
8149 }
8150
8151 static int intel_gen6_queue_flip(struct drm_device *dev,
8152                                  struct drm_crtc *crtc,
8153                                  struct drm_framebuffer *fb,
8154                                  struct drm_i915_gem_object *obj,
8155                                  uint32_t flags)
8156 {
8157         struct drm_i915_private *dev_priv = dev->dev_private;
8158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8159         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8160         uint32_t pf, pipesrc;
8161         int ret;
8162
8163         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8164         if (ret)
8165                 goto err;
8166
8167         ret = intel_ring_begin(ring, 4);
8168         if (ret)
8169                 goto err_unpin;
8170
8171         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8172                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8173         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8174         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8175
8176         /* Contrary to the suggestions in the documentation,
8177          * "Enable Panel Fitter" does not seem to be required when page
8178          * flipping with a non-native mode, and worse causes a normal
8179          * modeset to fail.
8180          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8181          */
8182         pf = 0;
8183         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8184         intel_ring_emit(ring, pf | pipesrc);
8185
8186         intel_mark_page_flip_active(intel_crtc);
8187         __intel_ring_advance(ring);
8188         return 0;
8189
8190 err_unpin:
8191         intel_unpin_fb_obj(obj);
8192 err:
8193         return ret;
8194 }
8195
8196 static int intel_gen7_queue_flip(struct drm_device *dev,
8197                                  struct drm_crtc *crtc,
8198                                  struct drm_framebuffer *fb,
8199                                  struct drm_i915_gem_object *obj,
8200                                  uint32_t flags)
8201 {
8202         struct drm_i915_private *dev_priv = dev->dev_private;
8203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8204         struct intel_ring_buffer *ring;
8205         uint32_t plane_bit = 0;
8206         int len, ret;
8207
8208         ring = obj->ring;
8209         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8210                 ring = &dev_priv->ring[BCS];
8211
8212         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8213         if (ret)
8214                 goto err;
8215
8216         switch(intel_crtc->plane) {
8217         case PLANE_A:
8218                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8219                 break;
8220         case PLANE_B:
8221                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8222                 break;
8223         case PLANE_C:
8224                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8225                 break;
8226         default:
8227                 WARN_ONCE(1, "unknown plane in flip command\n");
8228                 ret = -ENODEV;
8229                 goto err_unpin;
8230         }
8231
8232         len = 4;
8233         if (ring->id == RCS)
8234                 len += 6;
8235
8236         ret = intel_ring_begin(ring, len);
8237         if (ret)
8238                 goto err_unpin;
8239
8240         /* Unmask the flip-done completion message. Note that the bspec says that
8241          * we should do this for both the BCS and RCS, and that we must not unmask
8242          * more than one flip event at any time (or ensure that one flip message
8243          * can be sent by waiting for flip-done prior to queueing new flips).
8244          * Experimentation says that BCS works despite DERRMR masking all
8245          * flip-done completion events and that unmasking all planes at once
8246          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8247          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8248          */
8249         if (ring->id == RCS) {
8250                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8251                 intel_ring_emit(ring, DERRMR);
8252                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8253                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8254                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8255                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8256                 intel_ring_emit(ring, DERRMR);
8257                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8258         }
8259
8260         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8261         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8262         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8263         intel_ring_emit(ring, (MI_NOOP));
8264
8265         intel_mark_page_flip_active(intel_crtc);
8266         __intel_ring_advance(ring);
8267         return 0;
8268
8269 err_unpin:
8270         intel_unpin_fb_obj(obj);
8271 err:
8272         return ret;
8273 }
8274
8275 static int intel_default_queue_flip(struct drm_device *dev,
8276                                     struct drm_crtc *crtc,
8277                                     struct drm_framebuffer *fb,
8278                                     struct drm_i915_gem_object *obj,
8279                                     uint32_t flags)
8280 {
8281         return -ENODEV;
8282 }
8283
8284 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8285                                 struct drm_framebuffer *fb,
8286                                 struct drm_pending_vblank_event *event,
8287                                 uint32_t page_flip_flags)
8288 {
8289         struct drm_device *dev = crtc->dev;
8290         struct drm_i915_private *dev_priv = dev->dev_private;
8291         struct drm_framebuffer *old_fb = crtc->fb;
8292         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8294         struct intel_unpin_work *work;
8295         unsigned long flags;
8296         int ret;
8297
8298         /* Can't change pixel format via MI display flips. */
8299         if (fb->pixel_format != crtc->fb->pixel_format)
8300                 return -EINVAL;
8301
8302         /*
8303          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8304          * Note that pitch changes could also affect these register.
8305          */
8306         if (INTEL_INFO(dev)->gen > 3 &&
8307             (fb->offsets[0] != crtc->fb->offsets[0] ||
8308              fb->pitches[0] != crtc->fb->pitches[0]))
8309                 return -EINVAL;
8310
8311         work = kzalloc(sizeof(*work), GFP_KERNEL);
8312         if (work == NULL)
8313                 return -ENOMEM;
8314
8315         work->event = event;
8316         work->crtc = crtc;
8317         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8318         INIT_WORK(&work->work, intel_unpin_work_fn);
8319
8320         ret = drm_vblank_get(dev, intel_crtc->pipe);
8321         if (ret)
8322                 goto free_work;
8323
8324         /* We borrow the event spin lock for protecting unpin_work */
8325         spin_lock_irqsave(&dev->event_lock, flags);
8326         if (intel_crtc->unpin_work) {
8327                 spin_unlock_irqrestore(&dev->event_lock, flags);
8328                 kfree(work);
8329                 drm_vblank_put(dev, intel_crtc->pipe);
8330
8331                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8332                 return -EBUSY;
8333         }
8334         intel_crtc->unpin_work = work;
8335         spin_unlock_irqrestore(&dev->event_lock, flags);
8336
8337         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8338                 flush_workqueue(dev_priv->wq);
8339
8340         ret = i915_mutex_lock_interruptible(dev);
8341         if (ret)
8342                 goto cleanup;
8343
8344         /* Reference the objects for the scheduled work. */
8345         drm_gem_object_reference(&work->old_fb_obj->base);
8346         drm_gem_object_reference(&obj->base);
8347
8348         crtc->fb = fb;
8349
8350         work->pending_flip_obj = obj;
8351
8352         work->enable_stall_check = true;
8353
8354         atomic_inc(&intel_crtc->unpin_work_count);
8355         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8356
8357         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8358         if (ret)
8359                 goto cleanup_pending;
8360
8361         intel_disable_fbc(dev);
8362         intel_mark_fb_busy(obj, NULL);
8363         mutex_unlock(&dev->struct_mutex);
8364
8365         trace_i915_flip_request(intel_crtc->plane, obj);
8366
8367         return 0;
8368
8369 cleanup_pending:
8370         atomic_dec(&intel_crtc->unpin_work_count);
8371         crtc->fb = old_fb;
8372         drm_gem_object_unreference(&work->old_fb_obj->base);
8373         drm_gem_object_unreference(&obj->base);
8374         mutex_unlock(&dev->struct_mutex);
8375
8376 cleanup:
8377         spin_lock_irqsave(&dev->event_lock, flags);
8378         intel_crtc->unpin_work = NULL;
8379         spin_unlock_irqrestore(&dev->event_lock, flags);
8380
8381         drm_vblank_put(dev, intel_crtc->pipe);
8382 free_work:
8383         kfree(work);
8384
8385         return ret;
8386 }
8387
8388 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8389         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8390         .load_lut = intel_crtc_load_lut,
8391 };
8392
8393 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8394                                   struct drm_crtc *crtc)
8395 {
8396         struct drm_device *dev;
8397         struct drm_crtc *tmp;
8398         int crtc_mask = 1;
8399
8400         WARN(!crtc, "checking null crtc?\n");
8401
8402         dev = crtc->dev;
8403
8404         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8405                 if (tmp == crtc)
8406                         break;
8407                 crtc_mask <<= 1;
8408         }
8409
8410         if (encoder->possible_crtcs & crtc_mask)
8411                 return true;
8412         return false;
8413 }
8414
8415 /**
8416  * intel_modeset_update_staged_output_state
8417  *
8418  * Updates the staged output configuration state, e.g. after we've read out the
8419  * current hw state.
8420  */
8421 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8422 {
8423         struct intel_encoder *encoder;
8424         struct intel_connector *connector;
8425
8426         list_for_each_entry(connector, &dev->mode_config.connector_list,
8427                             base.head) {
8428                 connector->new_encoder =
8429                         to_intel_encoder(connector->base.encoder);
8430         }
8431
8432         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8433                             base.head) {
8434                 encoder->new_crtc =
8435                         to_intel_crtc(encoder->base.crtc);
8436         }
8437 }
8438
8439 /**
8440  * intel_modeset_commit_output_state
8441  *
8442  * This function copies the stage display pipe configuration to the real one.
8443  */
8444 static void intel_modeset_commit_output_state(struct drm_device *dev)
8445 {
8446         struct intel_encoder *encoder;
8447         struct intel_connector *connector;
8448
8449         list_for_each_entry(connector, &dev->mode_config.connector_list,
8450                             base.head) {
8451                 connector->base.encoder = &connector->new_encoder->base;
8452         }
8453
8454         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8455                             base.head) {
8456                 encoder->base.crtc = &encoder->new_crtc->base;
8457         }
8458 }
8459
8460 static void
8461 connected_sink_compute_bpp(struct intel_connector * connector,
8462                            struct intel_crtc_config *pipe_config)
8463 {
8464         int bpp = pipe_config->pipe_bpp;
8465
8466         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8467                 connector->base.base.id,
8468                 drm_get_connector_name(&connector->base));
8469
8470         /* Don't use an invalid EDID bpc value */
8471         if (connector->base.display_info.bpc &&
8472             connector->base.display_info.bpc * 3 < bpp) {
8473                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8474                               bpp, connector->base.display_info.bpc*3);
8475                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8476         }
8477
8478         /* Clamp bpp to 8 on screens without EDID 1.4 */
8479         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8480                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8481                               bpp);
8482                 pipe_config->pipe_bpp = 24;
8483         }
8484 }
8485
8486 static int
8487 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8488                           struct drm_framebuffer *fb,
8489                           struct intel_crtc_config *pipe_config)
8490 {
8491         struct drm_device *dev = crtc->base.dev;
8492         struct intel_connector *connector;
8493         int bpp;
8494
8495         switch (fb->pixel_format) {
8496         case DRM_FORMAT_C8:
8497                 bpp = 8*3; /* since we go through a colormap */
8498                 break;
8499         case DRM_FORMAT_XRGB1555:
8500         case DRM_FORMAT_ARGB1555:
8501                 /* checked in intel_framebuffer_init already */
8502                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8503                         return -EINVAL;
8504         case DRM_FORMAT_RGB565:
8505                 bpp = 6*3; /* min is 18bpp */
8506                 break;
8507         case DRM_FORMAT_XBGR8888:
8508         case DRM_FORMAT_ABGR8888:
8509                 /* checked in intel_framebuffer_init already */
8510                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8511                         return -EINVAL;
8512         case DRM_FORMAT_XRGB8888:
8513         case DRM_FORMAT_ARGB8888:
8514                 bpp = 8*3;
8515                 break;
8516         case DRM_FORMAT_XRGB2101010:
8517         case DRM_FORMAT_ARGB2101010:
8518         case DRM_FORMAT_XBGR2101010:
8519         case DRM_FORMAT_ABGR2101010:
8520                 /* checked in intel_framebuffer_init already */
8521                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8522                         return -EINVAL;
8523                 bpp = 10*3;
8524                 break;
8525         /* TODO: gen4+ supports 16 bpc floating point, too. */
8526         default:
8527                 DRM_DEBUG_KMS("unsupported depth\n");
8528                 return -EINVAL;
8529         }
8530
8531         pipe_config->pipe_bpp = bpp;
8532
8533         /* Clamp display bpp to EDID value */
8534         list_for_each_entry(connector, &dev->mode_config.connector_list,
8535                             base.head) {
8536                 if (!connector->new_encoder ||
8537                     connector->new_encoder->new_crtc != crtc)
8538                         continue;
8539
8540                 connected_sink_compute_bpp(connector, pipe_config);
8541         }
8542
8543         return bpp;
8544 }
8545
8546 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8547 {
8548         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8549                         "type: 0x%x flags: 0x%x\n",
8550                 mode->crtc_clock,
8551                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8552                 mode->crtc_hsync_end, mode->crtc_htotal,
8553                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8554                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8555 }
8556
8557 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8558                                    struct intel_crtc_config *pipe_config,
8559                                    const char *context)
8560 {
8561         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8562                       context, pipe_name(crtc->pipe));
8563
8564         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8565         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8566                       pipe_config->pipe_bpp, pipe_config->dither);
8567         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8568                       pipe_config->has_pch_encoder,
8569                       pipe_config->fdi_lanes,
8570                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8571                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8572                       pipe_config->fdi_m_n.tu);
8573         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8574                       pipe_config->has_dp_encoder,
8575                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8576                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8577                       pipe_config->dp_m_n.tu);
8578         DRM_DEBUG_KMS("requested mode:\n");
8579         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8580         DRM_DEBUG_KMS("adjusted mode:\n");
8581         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8582         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8583         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8584         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8585                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8586         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8587                       pipe_config->gmch_pfit.control,
8588                       pipe_config->gmch_pfit.pgm_ratios,
8589                       pipe_config->gmch_pfit.lvds_border_bits);
8590         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8591                       pipe_config->pch_pfit.pos,
8592                       pipe_config->pch_pfit.size,
8593                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8594         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8595         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8596 }
8597
8598 static bool check_encoder_cloning(struct drm_crtc *crtc)
8599 {
8600         int num_encoders = 0;
8601         bool uncloneable_encoders = false;
8602         struct intel_encoder *encoder;
8603
8604         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8605                             base.head) {
8606                 if (&encoder->new_crtc->base != crtc)
8607                         continue;
8608
8609                 num_encoders++;
8610                 if (!encoder->cloneable)
8611                         uncloneable_encoders = true;
8612         }
8613
8614         return !(num_encoders > 1 && uncloneable_encoders);
8615 }
8616
8617 static struct intel_crtc_config *
8618 intel_modeset_pipe_config(struct drm_crtc *crtc,
8619                           struct drm_framebuffer *fb,
8620                           struct drm_display_mode *mode)
8621 {
8622         struct drm_device *dev = crtc->dev;
8623         struct intel_encoder *encoder;
8624         struct intel_crtc_config *pipe_config;
8625         int plane_bpp, ret = -EINVAL;
8626         bool retry = true;
8627
8628         if (!check_encoder_cloning(crtc)) {
8629                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8630                 return ERR_PTR(-EINVAL);
8631         }
8632
8633         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8634         if (!pipe_config)
8635                 return ERR_PTR(-ENOMEM);
8636
8637         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8638         drm_mode_copy(&pipe_config->requested_mode, mode);
8639
8640         pipe_config->cpu_transcoder =
8641                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8642         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8643
8644         /*
8645          * Sanitize sync polarity flags based on requested ones. If neither
8646          * positive or negative polarity is requested, treat this as meaning
8647          * negative polarity.
8648          */
8649         if (!(pipe_config->adjusted_mode.flags &
8650               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8651                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8652
8653         if (!(pipe_config->adjusted_mode.flags &
8654               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8655                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8656
8657         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8658          * plane pixel format and any sink constraints into account. Returns the
8659          * source plane bpp so that dithering can be selected on mismatches
8660          * after encoders and crtc also have had their say. */
8661         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8662                                               fb, pipe_config);
8663         if (plane_bpp < 0)
8664                 goto fail;
8665
8666         /*
8667          * Determine the real pipe dimensions. Note that stereo modes can
8668          * increase the actual pipe size due to the frame doubling and
8669          * insertion of additional space for blanks between the frame. This
8670          * is stored in the crtc timings. We use the requested mode to do this
8671          * computation to clearly distinguish it from the adjusted mode, which
8672          * can be changed by the connectors in the below retry loop.
8673          */
8674         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8675         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8676         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8677
8678 encoder_retry:
8679         /* Ensure the port clock defaults are reset when retrying. */
8680         pipe_config->port_clock = 0;
8681         pipe_config->pixel_multiplier = 1;
8682
8683         /* Fill in default crtc timings, allow encoders to overwrite them. */
8684         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8685
8686         /* Pass our mode to the connectors and the CRTC to give them a chance to
8687          * adjust it according to limitations or connector properties, and also
8688          * a chance to reject the mode entirely.
8689          */
8690         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8691                             base.head) {
8692
8693                 if (&encoder->new_crtc->base != crtc)
8694                         continue;
8695
8696                 if (!(encoder->compute_config(encoder, pipe_config))) {
8697                         DRM_DEBUG_KMS("Encoder config failure\n");
8698                         goto fail;
8699                 }
8700         }
8701
8702         /* Set default port clock if not overwritten by the encoder. Needs to be
8703          * done afterwards in case the encoder adjusts the mode. */
8704         if (!pipe_config->port_clock)
8705                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8706                         * pipe_config->pixel_multiplier;
8707
8708         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8709         if (ret < 0) {
8710                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8711                 goto fail;
8712         }
8713
8714         if (ret == RETRY) {
8715                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8716                         ret = -EINVAL;
8717                         goto fail;
8718                 }
8719
8720                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8721                 retry = false;
8722                 goto encoder_retry;
8723         }
8724
8725         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8726         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8727                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8728
8729         return pipe_config;
8730 fail:
8731         kfree(pipe_config);
8732         return ERR_PTR(ret);
8733 }
8734
8735 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8736  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8737 static void
8738 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8739                              unsigned *prepare_pipes, unsigned *disable_pipes)
8740 {
8741         struct intel_crtc *intel_crtc;
8742         struct drm_device *dev = crtc->dev;
8743         struct intel_encoder *encoder;
8744         struct intel_connector *connector;
8745         struct drm_crtc *tmp_crtc;
8746
8747         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8748
8749         /* Check which crtcs have changed outputs connected to them, these need
8750          * to be part of the prepare_pipes mask. We don't (yet) support global
8751          * modeset across multiple crtcs, so modeset_pipes will only have one
8752          * bit set at most. */
8753         list_for_each_entry(connector, &dev->mode_config.connector_list,
8754                             base.head) {
8755                 if (connector->base.encoder == &connector->new_encoder->base)
8756                         continue;
8757
8758                 if (connector->base.encoder) {
8759                         tmp_crtc = connector->base.encoder->crtc;
8760
8761                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8762                 }
8763
8764                 if (connector->new_encoder)
8765                         *prepare_pipes |=
8766                                 1 << connector->new_encoder->new_crtc->pipe;
8767         }
8768
8769         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8770                             base.head) {
8771                 if (encoder->base.crtc == &encoder->new_crtc->base)
8772                         continue;
8773
8774                 if (encoder->base.crtc) {
8775                         tmp_crtc = encoder->base.crtc;
8776
8777                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8778                 }
8779
8780                 if (encoder->new_crtc)
8781                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8782         }
8783
8784         /* Check for any pipes that will be fully disabled ... */
8785         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8786                             base.head) {
8787                 bool used = false;
8788
8789                 /* Don't try to disable disabled crtcs. */
8790                 if (!intel_crtc->base.enabled)
8791                         continue;
8792
8793                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8794                                     base.head) {
8795                         if (encoder->new_crtc == intel_crtc)
8796                                 used = true;
8797                 }
8798
8799                 if (!used)
8800                         *disable_pipes |= 1 << intel_crtc->pipe;
8801         }
8802
8803
8804         /* set_mode is also used to update properties on life display pipes. */
8805         intel_crtc = to_intel_crtc(crtc);
8806         if (crtc->enabled)
8807                 *prepare_pipes |= 1 << intel_crtc->pipe;
8808
8809         /*
8810          * For simplicity do a full modeset on any pipe where the output routing
8811          * changed. We could be more clever, but that would require us to be
8812          * more careful with calling the relevant encoder->mode_set functions.
8813          */
8814         if (*prepare_pipes)
8815                 *modeset_pipes = *prepare_pipes;
8816
8817         /* ... and mask these out. */
8818         *modeset_pipes &= ~(*disable_pipes);
8819         *prepare_pipes &= ~(*disable_pipes);
8820
8821         /*
8822          * HACK: We don't (yet) fully support global modesets. intel_set_config
8823          * obies this rule, but the modeset restore mode of
8824          * intel_modeset_setup_hw_state does not.
8825          */
8826         *modeset_pipes &= 1 << intel_crtc->pipe;
8827         *prepare_pipes &= 1 << intel_crtc->pipe;
8828
8829         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8830                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8831 }
8832
8833 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8834 {
8835         struct drm_encoder *encoder;
8836         struct drm_device *dev = crtc->dev;
8837
8838         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8839                 if (encoder->crtc == crtc)
8840                         return true;
8841
8842         return false;
8843 }
8844
8845 static void
8846 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8847 {
8848         struct intel_encoder *intel_encoder;
8849         struct intel_crtc *intel_crtc;
8850         struct drm_connector *connector;
8851
8852         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8853                             base.head) {
8854                 if (!intel_encoder->base.crtc)
8855                         continue;
8856
8857                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8858
8859                 if (prepare_pipes & (1 << intel_crtc->pipe))
8860                         intel_encoder->connectors_active = false;
8861         }
8862
8863         intel_modeset_commit_output_state(dev);
8864
8865         /* Update computed state. */
8866         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8867                             base.head) {
8868                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8869         }
8870
8871         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8872                 if (!connector->encoder || !connector->encoder->crtc)
8873                         continue;
8874
8875                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8876
8877                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8878                         struct drm_property *dpms_property =
8879                                 dev->mode_config.dpms_property;
8880
8881                         connector->dpms = DRM_MODE_DPMS_ON;
8882                         drm_object_property_set_value(&connector->base,
8883                                                          dpms_property,
8884                                                          DRM_MODE_DPMS_ON);
8885
8886                         intel_encoder = to_intel_encoder(connector->encoder);
8887                         intel_encoder->connectors_active = true;
8888                 }
8889         }
8890
8891 }
8892
8893 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8894 {
8895         int diff;
8896
8897         if (clock1 == clock2)
8898                 return true;
8899
8900         if (!clock1 || !clock2)
8901                 return false;
8902
8903         diff = abs(clock1 - clock2);
8904
8905         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8906                 return true;
8907
8908         return false;
8909 }
8910
8911 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8912         list_for_each_entry((intel_crtc), \
8913                             &(dev)->mode_config.crtc_list, \
8914                             base.head) \
8915                 if (mask & (1 <<(intel_crtc)->pipe))
8916
8917 static bool
8918 intel_pipe_config_compare(struct drm_device *dev,
8919                           struct intel_crtc_config *current_config,
8920                           struct intel_crtc_config *pipe_config)
8921 {
8922 #define PIPE_CONF_CHECK_X(name) \
8923         if (current_config->name != pipe_config->name) { \
8924                 DRM_ERROR("mismatch in " #name " " \
8925                           "(expected 0x%08x, found 0x%08x)\n", \
8926                           current_config->name, \
8927                           pipe_config->name); \
8928                 return false; \
8929         }
8930
8931 #define PIPE_CONF_CHECK_I(name) \
8932         if (current_config->name != pipe_config->name) { \
8933                 DRM_ERROR("mismatch in " #name " " \
8934                           "(expected %i, found %i)\n", \
8935                           current_config->name, \
8936                           pipe_config->name); \
8937                 return false; \
8938         }
8939
8940 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8941         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8942                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8943                           "(expected %i, found %i)\n", \
8944                           current_config->name & (mask), \
8945                           pipe_config->name & (mask)); \
8946                 return false; \
8947         }
8948
8949 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8950         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8951                 DRM_ERROR("mismatch in " #name " " \
8952                           "(expected %i, found %i)\n", \
8953                           current_config->name, \
8954                           pipe_config->name); \
8955                 return false; \
8956         }
8957
8958 #define PIPE_CONF_QUIRK(quirk)  \
8959         ((current_config->quirks | pipe_config->quirks) & (quirk))
8960
8961         PIPE_CONF_CHECK_I(cpu_transcoder);
8962
8963         PIPE_CONF_CHECK_I(has_pch_encoder);
8964         PIPE_CONF_CHECK_I(fdi_lanes);
8965         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8966         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8967         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8968         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8969         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8970
8971         PIPE_CONF_CHECK_I(has_dp_encoder);
8972         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8973         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8974         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8975         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8976         PIPE_CONF_CHECK_I(dp_m_n.tu);
8977
8978         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8979         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8980         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8981         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8982         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8983         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8984
8985         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8986         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8987         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8988         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8989         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8990         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8991
8992         PIPE_CONF_CHECK_I(pixel_multiplier);
8993
8994         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8995                               DRM_MODE_FLAG_INTERLACE);
8996
8997         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8998                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8999                                       DRM_MODE_FLAG_PHSYNC);
9000                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9001                                       DRM_MODE_FLAG_NHSYNC);
9002                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9003                                       DRM_MODE_FLAG_PVSYNC);
9004                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9005                                       DRM_MODE_FLAG_NVSYNC);
9006         }
9007
9008         PIPE_CONF_CHECK_I(pipe_src_w);
9009         PIPE_CONF_CHECK_I(pipe_src_h);
9010
9011         PIPE_CONF_CHECK_I(gmch_pfit.control);
9012         /* pfit ratios are autocomputed by the hw on gen4+ */
9013         if (INTEL_INFO(dev)->gen < 4)
9014                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9015         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9016         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9017         if (current_config->pch_pfit.enabled) {
9018                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9019                 PIPE_CONF_CHECK_I(pch_pfit.size);
9020         }
9021
9022         PIPE_CONF_CHECK_I(ips_enabled);
9023
9024         PIPE_CONF_CHECK_I(double_wide);
9025
9026         PIPE_CONF_CHECK_I(shared_dpll);
9027         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9028         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9029         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9030         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9031
9032         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9033                 PIPE_CONF_CHECK_I(pipe_bpp);
9034
9035         if (!IS_HASWELL(dev)) {
9036                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9037                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9038         }
9039
9040 #undef PIPE_CONF_CHECK_X
9041 #undef PIPE_CONF_CHECK_I
9042 #undef PIPE_CONF_CHECK_FLAGS
9043 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9044 #undef PIPE_CONF_QUIRK
9045
9046         return true;
9047 }
9048
9049 static void
9050 check_connector_state(struct drm_device *dev)
9051 {
9052         struct intel_connector *connector;
9053
9054         list_for_each_entry(connector, &dev->mode_config.connector_list,
9055                             base.head) {
9056                 /* This also checks the encoder/connector hw state with the
9057                  * ->get_hw_state callbacks. */
9058                 intel_connector_check_state(connector);
9059
9060                 WARN(&connector->new_encoder->base != connector->base.encoder,
9061                      "connector's staged encoder doesn't match current encoder\n");
9062         }
9063 }
9064
9065 static void
9066 check_encoder_state(struct drm_device *dev)
9067 {
9068         struct intel_encoder *encoder;
9069         struct intel_connector *connector;
9070
9071         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9072                             base.head) {
9073                 bool enabled = false;
9074                 bool active = false;
9075                 enum pipe pipe, tracked_pipe;
9076
9077                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9078                               encoder->base.base.id,
9079                               drm_get_encoder_name(&encoder->base));
9080
9081                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9082                      "encoder's stage crtc doesn't match current crtc\n");
9083                 WARN(encoder->connectors_active && !encoder->base.crtc,
9084                      "encoder's active_connectors set, but no crtc\n");
9085
9086                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9087                                     base.head) {
9088                         if (connector->base.encoder != &encoder->base)
9089                                 continue;
9090                         enabled = true;
9091                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9092                                 active = true;
9093                 }
9094                 WARN(!!encoder->base.crtc != enabled,
9095                      "encoder's enabled state mismatch "
9096                      "(expected %i, found %i)\n",
9097                      !!encoder->base.crtc, enabled);
9098                 WARN(active && !encoder->base.crtc,
9099                      "active encoder with no crtc\n");
9100
9101                 WARN(encoder->connectors_active != active,
9102                      "encoder's computed active state doesn't match tracked active state "
9103                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9104
9105                 active = encoder->get_hw_state(encoder, &pipe);
9106                 WARN(active != encoder->connectors_active,
9107                      "encoder's hw state doesn't match sw tracking "
9108                      "(expected %i, found %i)\n",
9109                      encoder->connectors_active, active);
9110
9111                 if (!encoder->base.crtc)
9112                         continue;
9113
9114                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9115                 WARN(active && pipe != tracked_pipe,
9116                      "active encoder's pipe doesn't match"
9117                      "(expected %i, found %i)\n",
9118                      tracked_pipe, pipe);
9119
9120         }
9121 }
9122
9123 static void
9124 check_crtc_state(struct drm_device *dev)
9125 {
9126         drm_i915_private_t *dev_priv = dev->dev_private;
9127         struct intel_crtc *crtc;
9128         struct intel_encoder *encoder;
9129         struct intel_crtc_config pipe_config;
9130
9131         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9132                             base.head) {
9133                 bool enabled = false;
9134                 bool active = false;
9135
9136                 memset(&pipe_config, 0, sizeof(pipe_config));
9137
9138                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9139                               crtc->base.base.id);
9140
9141                 WARN(crtc->active && !crtc->base.enabled,
9142                      "active crtc, but not enabled in sw tracking\n");
9143
9144                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9145                                     base.head) {
9146                         if (encoder->base.crtc != &crtc->base)
9147                                 continue;
9148                         enabled = true;
9149                         if (encoder->connectors_active)
9150                                 active = true;
9151                 }
9152
9153                 WARN(active != crtc->active,
9154                      "crtc's computed active state doesn't match tracked active state "
9155                      "(expected %i, found %i)\n", active, crtc->active);
9156                 WARN(enabled != crtc->base.enabled,
9157                      "crtc's computed enabled state doesn't match tracked enabled state "
9158                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9159
9160                 active = dev_priv->display.get_pipe_config(crtc,
9161                                                            &pipe_config);
9162
9163                 /* hw state is inconsistent with the pipe A quirk */
9164                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9165                         active = crtc->active;
9166
9167                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9168                                     base.head) {
9169                         enum pipe pipe;
9170                         if (encoder->base.crtc != &crtc->base)
9171                                 continue;
9172                         if (encoder->get_config &&
9173                             encoder->get_hw_state(encoder, &pipe))
9174                                 encoder->get_config(encoder, &pipe_config);
9175                 }
9176
9177                 WARN(crtc->active != active,
9178                      "crtc active state doesn't match with hw state "
9179                      "(expected %i, found %i)\n", crtc->active, active);
9180
9181                 if (active &&
9182                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9183                         WARN(1, "pipe state doesn't match!\n");
9184                         intel_dump_pipe_config(crtc, &pipe_config,
9185                                                "[hw state]");
9186                         intel_dump_pipe_config(crtc, &crtc->config,
9187                                                "[sw state]");
9188                 }
9189         }
9190 }
9191
9192 static void
9193 check_shared_dpll_state(struct drm_device *dev)
9194 {
9195         drm_i915_private_t *dev_priv = dev->dev_private;
9196         struct intel_crtc *crtc;
9197         struct intel_dpll_hw_state dpll_hw_state;
9198         int i;
9199
9200         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9201                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9202                 int enabled_crtcs = 0, active_crtcs = 0;
9203                 bool active;
9204
9205                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9206
9207                 DRM_DEBUG_KMS("%s\n", pll->name);
9208
9209                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9210
9211                 WARN(pll->active > pll->refcount,
9212                      "more active pll users than references: %i vs %i\n",
9213                      pll->active, pll->refcount);
9214                 WARN(pll->active && !pll->on,
9215                      "pll in active use but not on in sw tracking\n");
9216                 WARN(pll->on && !pll->active,
9217                      "pll in on but not on in use in sw tracking\n");
9218                 WARN(pll->on != active,
9219                      "pll on state mismatch (expected %i, found %i)\n",
9220                      pll->on, active);
9221
9222                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9223                                     base.head) {
9224                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9225                                 enabled_crtcs++;
9226                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9227                                 active_crtcs++;
9228                 }
9229                 WARN(pll->active != active_crtcs,
9230                      "pll active crtcs mismatch (expected %i, found %i)\n",
9231                      pll->active, active_crtcs);
9232                 WARN(pll->refcount != enabled_crtcs,
9233                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9234                      pll->refcount, enabled_crtcs);
9235
9236                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9237                                        sizeof(dpll_hw_state)),
9238                      "pll hw state mismatch\n");
9239         }
9240 }
9241
9242 void
9243 intel_modeset_check_state(struct drm_device *dev)
9244 {
9245         check_connector_state(dev);
9246         check_encoder_state(dev);
9247         check_crtc_state(dev);
9248         check_shared_dpll_state(dev);
9249 }
9250
9251 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9252                                      int dotclock)
9253 {
9254         /*
9255          * FDI already provided one idea for the dotclock.
9256          * Yell if the encoder disagrees.
9257          */
9258         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9259              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9260              pipe_config->adjusted_mode.crtc_clock, dotclock);
9261 }
9262
9263 static int __intel_set_mode(struct drm_crtc *crtc,
9264                             struct drm_display_mode *mode,
9265                             int x, int y, struct drm_framebuffer *fb)
9266 {
9267         struct drm_device *dev = crtc->dev;
9268         drm_i915_private_t *dev_priv = dev->dev_private;
9269         struct drm_display_mode *saved_mode, *saved_hwmode;
9270         struct intel_crtc_config *pipe_config = NULL;
9271         struct intel_crtc *intel_crtc;
9272         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9273         int ret = 0;
9274
9275         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9276         if (!saved_mode)
9277                 return -ENOMEM;
9278         saved_hwmode = saved_mode + 1;
9279
9280         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9281                                      &prepare_pipes, &disable_pipes);
9282
9283         *saved_hwmode = crtc->hwmode;
9284         *saved_mode = crtc->mode;
9285
9286         /* Hack: Because we don't (yet) support global modeset on multiple
9287          * crtcs, we don't keep track of the new mode for more than one crtc.
9288          * Hence simply check whether any bit is set in modeset_pipes in all the
9289          * pieces of code that are not yet converted to deal with mutliple crtcs
9290          * changing their mode at the same time. */
9291         if (modeset_pipes) {
9292                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9293                 if (IS_ERR(pipe_config)) {
9294                         ret = PTR_ERR(pipe_config);
9295                         pipe_config = NULL;
9296
9297                         goto out;
9298                 }
9299                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9300                                        "[modeset]");
9301         }
9302
9303         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9304                 intel_crtc_disable(&intel_crtc->base);
9305
9306         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9307                 if (intel_crtc->base.enabled)
9308                         dev_priv->display.crtc_disable(&intel_crtc->base);
9309         }
9310
9311         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9312          * to set it here already despite that we pass it down the callchain.
9313          */
9314         if (modeset_pipes) {
9315                 crtc->mode = *mode;
9316                 /* mode_set/enable/disable functions rely on a correct pipe
9317                  * config. */
9318                 to_intel_crtc(crtc)->config = *pipe_config;
9319         }
9320
9321         /* Only after disabling all output pipelines that will be changed can we
9322          * update the the output configuration. */
9323         intel_modeset_update_state(dev, prepare_pipes);
9324
9325         if (dev_priv->display.modeset_global_resources)
9326                 dev_priv->display.modeset_global_resources(dev);
9327
9328         /* Set up the DPLL and any encoders state that needs to adjust or depend
9329          * on the DPLL.
9330          */
9331         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9332                 ret = intel_crtc_mode_set(&intel_crtc->base,
9333                                           x, y, fb);
9334                 if (ret)
9335                         goto done;
9336         }
9337
9338         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9339         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9340                 dev_priv->display.crtc_enable(&intel_crtc->base);
9341
9342         if (modeset_pipes) {
9343                 /* Store real post-adjustment hardware mode. */
9344                 crtc->hwmode = pipe_config->adjusted_mode;
9345
9346                 /* Calculate and store various constants which
9347                  * are later needed by vblank and swap-completion
9348                  * timestamping. They are derived from true hwmode.
9349                  */
9350                 drm_calc_timestamping_constants(crtc);
9351         }
9352
9353         /* FIXME: add subpixel order */
9354 done:
9355         if (ret && crtc->enabled) {
9356                 crtc->hwmode = *saved_hwmode;
9357                 crtc->mode = *saved_mode;
9358         }
9359
9360 out:
9361         kfree(pipe_config);
9362         kfree(saved_mode);
9363         return ret;
9364 }
9365
9366 static int intel_set_mode(struct drm_crtc *crtc,
9367                           struct drm_display_mode *mode,
9368                           int x, int y, struct drm_framebuffer *fb)
9369 {
9370         int ret;
9371
9372         ret = __intel_set_mode(crtc, mode, x, y, fb);
9373
9374         if (ret == 0)
9375                 intel_modeset_check_state(crtc->dev);
9376
9377         return ret;
9378 }
9379
9380 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9381 {
9382         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9383 }
9384
9385 #undef for_each_intel_crtc_masked
9386
9387 static void intel_set_config_free(struct intel_set_config *config)
9388 {
9389         if (!config)
9390                 return;
9391
9392         kfree(config->save_connector_encoders);
9393         kfree(config->save_encoder_crtcs);
9394         kfree(config);
9395 }
9396
9397 static int intel_set_config_save_state(struct drm_device *dev,
9398                                        struct intel_set_config *config)
9399 {
9400         struct drm_encoder *encoder;
9401         struct drm_connector *connector;
9402         int count;
9403
9404         config->save_encoder_crtcs =
9405                 kcalloc(dev->mode_config.num_encoder,
9406                         sizeof(struct drm_crtc *), GFP_KERNEL);
9407         if (!config->save_encoder_crtcs)
9408                 return -ENOMEM;
9409
9410         config->save_connector_encoders =
9411                 kcalloc(dev->mode_config.num_connector,
9412                         sizeof(struct drm_encoder *), GFP_KERNEL);
9413         if (!config->save_connector_encoders)
9414                 return -ENOMEM;
9415
9416         /* Copy data. Note that driver private data is not affected.
9417          * Should anything bad happen only the expected state is
9418          * restored, not the drivers personal bookkeeping.
9419          */
9420         count = 0;
9421         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9422                 config->save_encoder_crtcs[count++] = encoder->crtc;
9423         }
9424
9425         count = 0;
9426         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9427                 config->save_connector_encoders[count++] = connector->encoder;
9428         }
9429
9430         return 0;
9431 }
9432
9433 static void intel_set_config_restore_state(struct drm_device *dev,
9434                                            struct intel_set_config *config)
9435 {
9436         struct intel_encoder *encoder;
9437         struct intel_connector *connector;
9438         int count;
9439
9440         count = 0;
9441         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9442                 encoder->new_crtc =
9443                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9444         }
9445
9446         count = 0;
9447         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9448                 connector->new_encoder =
9449                         to_intel_encoder(config->save_connector_encoders[count++]);
9450         }
9451 }
9452
9453 static bool
9454 is_crtc_connector_off(struct drm_mode_set *set)
9455 {
9456         int i;
9457
9458         if (set->num_connectors == 0)
9459                 return false;
9460
9461         if (WARN_ON(set->connectors == NULL))
9462                 return false;
9463
9464         for (i = 0; i < set->num_connectors; i++)
9465                 if (set->connectors[i]->encoder &&
9466                     set->connectors[i]->encoder->crtc == set->crtc &&
9467                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9468                         return true;
9469
9470         return false;
9471 }
9472
9473 static void
9474 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9475                                       struct intel_set_config *config)
9476 {
9477
9478         /* We should be able to check here if the fb has the same properties
9479          * and then just flip_or_move it */
9480         if (is_crtc_connector_off(set)) {
9481                 config->mode_changed = true;
9482         } else if (set->crtc->fb != set->fb) {
9483                 /* If we have no fb then treat it as a full mode set */
9484                 if (set->crtc->fb == NULL) {
9485                         struct intel_crtc *intel_crtc =
9486                                 to_intel_crtc(set->crtc);
9487
9488                         if (intel_crtc->active && i915_fastboot) {
9489                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9490                                 config->fb_changed = true;
9491                         } else {
9492                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9493                                 config->mode_changed = true;
9494                         }
9495                 } else if (set->fb == NULL) {
9496                         config->mode_changed = true;
9497                 } else if (set->fb->pixel_format !=
9498                            set->crtc->fb->pixel_format) {
9499                         config->mode_changed = true;
9500                 } else {
9501                         config->fb_changed = true;
9502                 }
9503         }
9504
9505         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9506                 config->fb_changed = true;
9507
9508         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9509                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9510                 drm_mode_debug_printmodeline(&set->crtc->mode);
9511                 drm_mode_debug_printmodeline(set->mode);
9512                 config->mode_changed = true;
9513         }
9514
9515         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9516                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9517 }
9518
9519 static int
9520 intel_modeset_stage_output_state(struct drm_device *dev,
9521                                  struct drm_mode_set *set,
9522                                  struct intel_set_config *config)
9523 {
9524         struct drm_crtc *new_crtc;
9525         struct intel_connector *connector;
9526         struct intel_encoder *encoder;
9527         int ro;
9528
9529         /* The upper layers ensure that we either disable a crtc or have a list
9530          * of connectors. For paranoia, double-check this. */
9531         WARN_ON(!set->fb && (set->num_connectors != 0));
9532         WARN_ON(set->fb && (set->num_connectors == 0));
9533
9534         list_for_each_entry(connector, &dev->mode_config.connector_list,
9535                             base.head) {
9536                 /* Otherwise traverse passed in connector list and get encoders
9537                  * for them. */
9538                 for (ro = 0; ro < set->num_connectors; ro++) {
9539                         if (set->connectors[ro] == &connector->base) {
9540                                 connector->new_encoder = connector->encoder;
9541                                 break;
9542                         }
9543                 }
9544
9545                 /* If we disable the crtc, disable all its connectors. Also, if
9546                  * the connector is on the changing crtc but not on the new
9547                  * connector list, disable it. */
9548                 if ((!set->fb || ro == set->num_connectors) &&
9549                     connector->base.encoder &&
9550                     connector->base.encoder->crtc == set->crtc) {
9551                         connector->new_encoder = NULL;
9552
9553                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9554                                 connector->base.base.id,
9555                                 drm_get_connector_name(&connector->base));
9556                 }
9557
9558
9559                 if (&connector->new_encoder->base != connector->base.encoder) {
9560                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9561                         config->mode_changed = true;
9562                 }
9563         }
9564         /* connector->new_encoder is now updated for all connectors. */
9565
9566         /* Update crtc of enabled connectors. */
9567         list_for_each_entry(connector, &dev->mode_config.connector_list,
9568                             base.head) {
9569                 if (!connector->new_encoder)
9570                         continue;
9571
9572                 new_crtc = connector->new_encoder->base.crtc;
9573
9574                 for (ro = 0; ro < set->num_connectors; ro++) {
9575                         if (set->connectors[ro] == &connector->base)
9576                                 new_crtc = set->crtc;
9577                 }
9578
9579                 /* Make sure the new CRTC will work with the encoder */
9580                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9581                                            new_crtc)) {
9582                         return -EINVAL;
9583                 }
9584                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9585
9586                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9587                         connector->base.base.id,
9588                         drm_get_connector_name(&connector->base),
9589                         new_crtc->base.id);
9590         }
9591
9592         /* Check for any encoders that needs to be disabled. */
9593         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9594                             base.head) {
9595                 list_for_each_entry(connector,
9596                                     &dev->mode_config.connector_list,
9597                                     base.head) {
9598                         if (connector->new_encoder == encoder) {
9599                                 WARN_ON(!connector->new_encoder->new_crtc);
9600
9601                                 goto next_encoder;
9602                         }
9603                 }
9604                 encoder->new_crtc = NULL;
9605 next_encoder:
9606                 /* Only now check for crtc changes so we don't miss encoders
9607                  * that will be disabled. */
9608                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9609                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9610                         config->mode_changed = true;
9611                 }
9612         }
9613         /* Now we've also updated encoder->new_crtc for all encoders. */
9614
9615         return 0;
9616 }
9617
9618 static int intel_crtc_set_config(struct drm_mode_set *set)
9619 {
9620         struct drm_device *dev;
9621         struct drm_mode_set save_set;
9622         struct intel_set_config *config;
9623         int ret;
9624
9625         BUG_ON(!set);
9626         BUG_ON(!set->crtc);
9627         BUG_ON(!set->crtc->helper_private);
9628
9629         /* Enforce sane interface api - has been abused by the fb helper. */
9630         BUG_ON(!set->mode && set->fb);
9631         BUG_ON(set->fb && set->num_connectors == 0);
9632
9633         if (set->fb) {
9634                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9635                                 set->crtc->base.id, set->fb->base.id,
9636                                 (int)set->num_connectors, set->x, set->y);
9637         } else {
9638                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9639         }
9640
9641         dev = set->crtc->dev;
9642
9643         ret = -ENOMEM;
9644         config = kzalloc(sizeof(*config), GFP_KERNEL);
9645         if (!config)
9646                 goto out_config;
9647
9648         ret = intel_set_config_save_state(dev, config);
9649         if (ret)
9650                 goto out_config;
9651
9652         save_set.crtc = set->crtc;
9653         save_set.mode = &set->crtc->mode;
9654         save_set.x = set->crtc->x;
9655         save_set.y = set->crtc->y;
9656         save_set.fb = set->crtc->fb;
9657
9658         /* Compute whether we need a full modeset, only an fb base update or no
9659          * change at all. In the future we might also check whether only the
9660          * mode changed, e.g. for LVDS where we only change the panel fitter in
9661          * such cases. */
9662         intel_set_config_compute_mode_changes(set, config);
9663
9664         ret = intel_modeset_stage_output_state(dev, set, config);
9665         if (ret)
9666                 goto fail;
9667
9668         if (config->mode_changed) {
9669                 ret = intel_set_mode(set->crtc, set->mode,
9670                                      set->x, set->y, set->fb);
9671         } else if (config->fb_changed) {
9672                 intel_crtc_wait_for_pending_flips(set->crtc);
9673
9674                 ret = intel_pipe_set_base(set->crtc,
9675                                           set->x, set->y, set->fb);
9676         }
9677
9678         if (ret) {
9679                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9680                               set->crtc->base.id, ret);
9681 fail:
9682                 intel_set_config_restore_state(dev, config);
9683
9684                 /* Try to restore the config */
9685                 if (config->mode_changed &&
9686                     intel_set_mode(save_set.crtc, save_set.mode,
9687                                    save_set.x, save_set.y, save_set.fb))
9688                         DRM_ERROR("failed to restore config after modeset failure\n");
9689         }
9690
9691 out_config:
9692         intel_set_config_free(config);
9693         return ret;
9694 }
9695
9696 static const struct drm_crtc_funcs intel_crtc_funcs = {
9697         .cursor_set = intel_crtc_cursor_set,
9698         .cursor_move = intel_crtc_cursor_move,
9699         .gamma_set = intel_crtc_gamma_set,
9700         .set_config = intel_crtc_set_config,
9701         .destroy = intel_crtc_destroy,
9702         .page_flip = intel_crtc_page_flip,
9703 };
9704
9705 static void intel_cpu_pll_init(struct drm_device *dev)
9706 {
9707         if (HAS_DDI(dev))
9708                 intel_ddi_pll_init(dev);
9709 }
9710
9711 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9712                                       struct intel_shared_dpll *pll,
9713                                       struct intel_dpll_hw_state *hw_state)
9714 {
9715         uint32_t val;
9716
9717         val = I915_READ(PCH_DPLL(pll->id));
9718         hw_state->dpll = val;
9719         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9720         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9721
9722         return val & DPLL_VCO_ENABLE;
9723 }
9724
9725 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9726                                   struct intel_shared_dpll *pll)
9727 {
9728         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9729         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9730 }
9731
9732 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9733                                 struct intel_shared_dpll *pll)
9734 {
9735         /* PCH refclock must be enabled first */
9736         assert_pch_refclk_enabled(dev_priv);
9737
9738         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9739
9740         /* Wait for the clocks to stabilize. */
9741         POSTING_READ(PCH_DPLL(pll->id));
9742         udelay(150);
9743
9744         /* The pixel multiplier can only be updated once the
9745          * DPLL is enabled and the clocks are stable.
9746          *
9747          * So write it again.
9748          */
9749         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9750         POSTING_READ(PCH_DPLL(pll->id));
9751         udelay(200);
9752 }
9753
9754 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9755                                  struct intel_shared_dpll *pll)
9756 {
9757         struct drm_device *dev = dev_priv->dev;
9758         struct intel_crtc *crtc;
9759
9760         /* Make sure no transcoder isn't still depending on us. */
9761         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9762                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9763                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9764         }
9765
9766         I915_WRITE(PCH_DPLL(pll->id), 0);
9767         POSTING_READ(PCH_DPLL(pll->id));
9768         udelay(200);
9769 }
9770
9771 static char *ibx_pch_dpll_names[] = {
9772         "PCH DPLL A",
9773         "PCH DPLL B",
9774 };
9775
9776 static void ibx_pch_dpll_init(struct drm_device *dev)
9777 {
9778         struct drm_i915_private *dev_priv = dev->dev_private;
9779         int i;
9780
9781         dev_priv->num_shared_dpll = 2;
9782
9783         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9784                 dev_priv->shared_dplls[i].id = i;
9785                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9786                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9787                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9788                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9789                 dev_priv->shared_dplls[i].get_hw_state =
9790                         ibx_pch_dpll_get_hw_state;
9791         }
9792 }
9793
9794 static void intel_shared_dpll_init(struct drm_device *dev)
9795 {
9796         struct drm_i915_private *dev_priv = dev->dev_private;
9797
9798         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9799                 ibx_pch_dpll_init(dev);
9800         else
9801                 dev_priv->num_shared_dpll = 0;
9802
9803         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9804         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9805                       dev_priv->num_shared_dpll);
9806 }
9807
9808 static void intel_crtc_init(struct drm_device *dev, int pipe)
9809 {
9810         drm_i915_private_t *dev_priv = dev->dev_private;
9811         struct intel_crtc *intel_crtc;
9812         int i;
9813
9814         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9815         if (intel_crtc == NULL)
9816                 return;
9817
9818         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9819
9820         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9821         for (i = 0; i < 256; i++) {
9822                 intel_crtc->lut_r[i] = i;
9823                 intel_crtc->lut_g[i] = i;
9824                 intel_crtc->lut_b[i] = i;
9825         }
9826
9827         /* Swap pipes & planes for FBC on pre-965 */
9828         intel_crtc->pipe = pipe;
9829         intel_crtc->plane = pipe;
9830         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9831                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9832                 intel_crtc->plane = !pipe;
9833         }
9834
9835         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9836                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9837         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9838         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9839
9840         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9841 }
9842
9843 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9844                                 struct drm_file *file)
9845 {
9846         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9847         struct drm_mode_object *drmmode_obj;
9848         struct intel_crtc *crtc;
9849
9850         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9851                 return -ENODEV;
9852
9853         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9854                         DRM_MODE_OBJECT_CRTC);
9855
9856         if (!drmmode_obj) {
9857                 DRM_ERROR("no such CRTC id\n");
9858                 return -EINVAL;
9859         }
9860
9861         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9862         pipe_from_crtc_id->pipe = crtc->pipe;
9863
9864         return 0;
9865 }
9866
9867 static int intel_encoder_clones(struct intel_encoder *encoder)
9868 {
9869         struct drm_device *dev = encoder->base.dev;
9870         struct intel_encoder *source_encoder;
9871         int index_mask = 0;
9872         int entry = 0;
9873
9874         list_for_each_entry(source_encoder,
9875                             &dev->mode_config.encoder_list, base.head) {
9876
9877                 if (encoder == source_encoder)
9878                         index_mask |= (1 << entry);
9879
9880                 /* Intel hw has only one MUX where enocoders could be cloned. */
9881                 if (encoder->cloneable && source_encoder->cloneable)
9882                         index_mask |= (1 << entry);
9883
9884                 entry++;
9885         }
9886
9887         return index_mask;
9888 }
9889
9890 static bool has_edp_a(struct drm_device *dev)
9891 {
9892         struct drm_i915_private *dev_priv = dev->dev_private;
9893
9894         if (!IS_MOBILE(dev))
9895                 return false;
9896
9897         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9898                 return false;
9899
9900         if (IS_GEN5(dev) &&
9901             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9902                 return false;
9903
9904         return true;
9905 }
9906
9907 static void intel_setup_outputs(struct drm_device *dev)
9908 {
9909         struct drm_i915_private *dev_priv = dev->dev_private;
9910         struct intel_encoder *encoder;
9911         bool dpd_is_edp = false;
9912
9913         intel_lvds_init(dev);
9914
9915         if (!IS_ULT(dev))
9916                 intel_crt_init(dev);
9917
9918         if (HAS_DDI(dev)) {
9919                 int found;
9920
9921                 /* Haswell uses DDI functions to detect digital outputs */
9922                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9923                 /* DDI A only supports eDP */
9924                 if (found)
9925                         intel_ddi_init(dev, PORT_A);
9926
9927                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9928                  * register */
9929                 found = I915_READ(SFUSE_STRAP);
9930
9931                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9932                         intel_ddi_init(dev, PORT_B);
9933                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9934                         intel_ddi_init(dev, PORT_C);
9935                 if (found & SFUSE_STRAP_DDID_DETECTED)
9936                         intel_ddi_init(dev, PORT_D);
9937         } else if (HAS_PCH_SPLIT(dev)) {
9938                 int found;
9939                 dpd_is_edp = intel_dpd_is_edp(dev);
9940
9941                 if (has_edp_a(dev))
9942                         intel_dp_init(dev, DP_A, PORT_A);
9943
9944                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9945                         /* PCH SDVOB multiplex with HDMIB */
9946                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9947                         if (!found)
9948                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9949                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9950                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9951                 }
9952
9953                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9954                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9955
9956                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9957                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9958
9959                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9960                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9961
9962                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9963                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9964         } else if (IS_VALLEYVIEW(dev)) {
9965                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9966                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9967                                         PORT_B);
9968                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9969                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9970                 }
9971
9972                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9973                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9974                                         PORT_C);
9975                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9976                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9977                                               PORT_C);
9978                 }
9979
9980                 intel_dsi_init(dev);
9981         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9982                 bool found = false;
9983
9984                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9985                         DRM_DEBUG_KMS("probing SDVOB\n");
9986                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9987                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9988                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9989                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9990                         }
9991
9992                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9993                                 intel_dp_init(dev, DP_B, PORT_B);
9994                 }
9995
9996                 /* Before G4X SDVOC doesn't have its own detect register */
9997
9998                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9999                         DRM_DEBUG_KMS("probing SDVOC\n");
10000                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10001                 }
10002
10003                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10004
10005                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10006                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10007                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10008                         }
10009                         if (SUPPORTS_INTEGRATED_DP(dev))
10010                                 intel_dp_init(dev, DP_C, PORT_C);
10011                 }
10012
10013                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10014                     (I915_READ(DP_D) & DP_DETECTED))
10015                         intel_dp_init(dev, DP_D, PORT_D);
10016         } else if (IS_GEN2(dev))
10017                 intel_dvo_init(dev);
10018
10019         if (SUPPORTS_TV(dev))
10020                 intel_tv_init(dev);
10021
10022         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10023                 encoder->base.possible_crtcs = encoder->crtc_mask;
10024                 encoder->base.possible_clones =
10025                         intel_encoder_clones(encoder);
10026         }
10027
10028         intel_init_pch_refclk(dev);
10029
10030         drm_helper_move_panel_connectors_to_head(dev);
10031 }
10032
10033 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10034 {
10035         drm_framebuffer_cleanup(&fb->base);
10036         WARN_ON(!fb->obj->framebuffer_references--);
10037         drm_gem_object_unreference_unlocked(&fb->obj->base);
10038 }
10039
10040 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10041 {
10042         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10043
10044         intel_framebuffer_fini(intel_fb);
10045         kfree(intel_fb);
10046 }
10047
10048 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10049                                                 struct drm_file *file,
10050                                                 unsigned int *handle)
10051 {
10052         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10053         struct drm_i915_gem_object *obj = intel_fb->obj;
10054
10055         return drm_gem_handle_create(file, &obj->base, handle);
10056 }
10057
10058 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10059         .destroy = intel_user_framebuffer_destroy,
10060         .create_handle = intel_user_framebuffer_create_handle,
10061 };
10062
10063 int intel_framebuffer_init(struct drm_device *dev,
10064                            struct intel_framebuffer *intel_fb,
10065                            struct drm_mode_fb_cmd2 *mode_cmd,
10066                            struct drm_i915_gem_object *obj)
10067 {
10068         int aligned_height, tile_height;
10069         int pitch_limit;
10070         int ret;
10071
10072         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10073
10074         if (obj->tiling_mode == I915_TILING_Y) {
10075                 DRM_DEBUG("hardware does not support tiling Y\n");
10076                 return -EINVAL;
10077         }
10078
10079         if (mode_cmd->pitches[0] & 63) {
10080                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10081                           mode_cmd->pitches[0]);
10082                 return -EINVAL;
10083         }
10084
10085         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10086                 pitch_limit = 32*1024;
10087         } else if (INTEL_INFO(dev)->gen >= 4) {
10088                 if (obj->tiling_mode)
10089                         pitch_limit = 16*1024;
10090                 else
10091                         pitch_limit = 32*1024;
10092         } else if (INTEL_INFO(dev)->gen >= 3) {
10093                 if (obj->tiling_mode)
10094                         pitch_limit = 8*1024;
10095                 else
10096                         pitch_limit = 16*1024;
10097         } else
10098                 /* XXX DSPC is limited to 4k tiled */
10099                 pitch_limit = 8*1024;
10100
10101         if (mode_cmd->pitches[0] > pitch_limit) {
10102                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10103                           obj->tiling_mode ? "tiled" : "linear",
10104                           mode_cmd->pitches[0], pitch_limit);
10105                 return -EINVAL;
10106         }
10107
10108         if (obj->tiling_mode != I915_TILING_NONE &&
10109             mode_cmd->pitches[0] != obj->stride) {
10110                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10111                           mode_cmd->pitches[0], obj->stride);
10112                 return -EINVAL;
10113         }
10114
10115         /* Reject formats not supported by any plane early. */
10116         switch (mode_cmd->pixel_format) {
10117         case DRM_FORMAT_C8:
10118         case DRM_FORMAT_RGB565:
10119         case DRM_FORMAT_XRGB8888:
10120         case DRM_FORMAT_ARGB8888:
10121                 break;
10122         case DRM_FORMAT_XRGB1555:
10123         case DRM_FORMAT_ARGB1555:
10124                 if (INTEL_INFO(dev)->gen > 3) {
10125                         DRM_DEBUG("unsupported pixel format: %s\n",
10126                                   drm_get_format_name(mode_cmd->pixel_format));
10127                         return -EINVAL;
10128                 }
10129                 break;
10130         case DRM_FORMAT_XBGR8888:
10131         case DRM_FORMAT_ABGR8888:
10132         case DRM_FORMAT_XRGB2101010:
10133         case DRM_FORMAT_ARGB2101010:
10134         case DRM_FORMAT_XBGR2101010:
10135         case DRM_FORMAT_ABGR2101010:
10136                 if (INTEL_INFO(dev)->gen < 4) {
10137                         DRM_DEBUG("unsupported pixel format: %s\n",
10138                                   drm_get_format_name(mode_cmd->pixel_format));
10139                         return -EINVAL;
10140                 }
10141                 break;
10142         case DRM_FORMAT_YUYV:
10143         case DRM_FORMAT_UYVY:
10144         case DRM_FORMAT_YVYU:
10145         case DRM_FORMAT_VYUY:
10146                 if (INTEL_INFO(dev)->gen < 5) {
10147                         DRM_DEBUG("unsupported pixel format: %s\n",
10148                                   drm_get_format_name(mode_cmd->pixel_format));
10149                         return -EINVAL;
10150                 }
10151                 break;
10152         default:
10153                 DRM_DEBUG("unsupported pixel format: %s\n",
10154                           drm_get_format_name(mode_cmd->pixel_format));
10155                 return -EINVAL;
10156         }
10157
10158         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10159         if (mode_cmd->offsets[0] != 0)
10160                 return -EINVAL;
10161
10162         tile_height = IS_GEN2(dev) ? 16 : 8;
10163         aligned_height = ALIGN(mode_cmd->height,
10164                                obj->tiling_mode ? tile_height : 1);
10165         /* FIXME drm helper for size checks (especially planar formats)? */
10166         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10167                 return -EINVAL;
10168
10169         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10170         intel_fb->obj = obj;
10171         intel_fb->obj->framebuffer_references++;
10172
10173         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10174         if (ret) {
10175                 DRM_ERROR("framebuffer init failed %d\n", ret);
10176                 return ret;
10177         }
10178
10179         return 0;
10180 }
10181
10182 static struct drm_framebuffer *
10183 intel_user_framebuffer_create(struct drm_device *dev,
10184                               struct drm_file *filp,
10185                               struct drm_mode_fb_cmd2 *mode_cmd)
10186 {
10187         struct drm_i915_gem_object *obj;
10188
10189         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10190                                                 mode_cmd->handles[0]));
10191         if (&obj->base == NULL)
10192                 return ERR_PTR(-ENOENT);
10193
10194         return intel_framebuffer_create(dev, mode_cmd, obj);
10195 }
10196
10197 #ifndef CONFIG_DRM_I915_FBDEV
10198 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10199 {
10200 }
10201 #endif
10202
10203 static const struct drm_mode_config_funcs intel_mode_funcs = {
10204         .fb_create = intel_user_framebuffer_create,
10205         .output_poll_changed = intel_fbdev_output_poll_changed,
10206 };
10207
10208 /* Set up chip specific display functions */
10209 static void intel_init_display(struct drm_device *dev)
10210 {
10211         struct drm_i915_private *dev_priv = dev->dev_private;
10212
10213         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10214                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10215         else if (IS_VALLEYVIEW(dev))
10216                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10217         else if (IS_PINEVIEW(dev))
10218                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10219         else
10220                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10221
10222         if (HAS_DDI(dev)) {
10223                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10224                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10225                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10226                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10227                 dev_priv->display.off = haswell_crtc_off;
10228                 dev_priv->display.update_plane = ironlake_update_plane;
10229         } else if (HAS_PCH_SPLIT(dev)) {
10230                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10231                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10232                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10233                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10234                 dev_priv->display.off = ironlake_crtc_off;
10235                 dev_priv->display.update_plane = ironlake_update_plane;
10236         } else if (IS_VALLEYVIEW(dev)) {
10237                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10238                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10239                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10240                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10241                 dev_priv->display.off = i9xx_crtc_off;
10242                 dev_priv->display.update_plane = i9xx_update_plane;
10243         } else {
10244                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10245                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10246                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10247                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10248                 dev_priv->display.off = i9xx_crtc_off;
10249                 dev_priv->display.update_plane = i9xx_update_plane;
10250         }
10251
10252         /* Returns the core display clock speed */
10253         if (IS_VALLEYVIEW(dev))
10254                 dev_priv->display.get_display_clock_speed =
10255                         valleyview_get_display_clock_speed;
10256         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10257                 dev_priv->display.get_display_clock_speed =
10258                         i945_get_display_clock_speed;
10259         else if (IS_I915G(dev))
10260                 dev_priv->display.get_display_clock_speed =
10261                         i915_get_display_clock_speed;
10262         else if (IS_I945GM(dev) || IS_845G(dev))
10263                 dev_priv->display.get_display_clock_speed =
10264                         i9xx_misc_get_display_clock_speed;
10265         else if (IS_PINEVIEW(dev))
10266                 dev_priv->display.get_display_clock_speed =
10267                         pnv_get_display_clock_speed;
10268         else if (IS_I915GM(dev))
10269                 dev_priv->display.get_display_clock_speed =
10270                         i915gm_get_display_clock_speed;
10271         else if (IS_I865G(dev))
10272                 dev_priv->display.get_display_clock_speed =
10273                         i865_get_display_clock_speed;
10274         else if (IS_I85X(dev))
10275                 dev_priv->display.get_display_clock_speed =
10276                         i855_get_display_clock_speed;
10277         else /* 852, 830 */
10278                 dev_priv->display.get_display_clock_speed =
10279                         i830_get_display_clock_speed;
10280
10281         if (HAS_PCH_SPLIT(dev)) {
10282                 if (IS_GEN5(dev)) {
10283                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10284                         dev_priv->display.write_eld = ironlake_write_eld;
10285                 } else if (IS_GEN6(dev)) {
10286                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10287                         dev_priv->display.write_eld = ironlake_write_eld;
10288                 } else if (IS_IVYBRIDGE(dev)) {
10289                         /* FIXME: detect B0+ stepping and use auto training */
10290                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10291                         dev_priv->display.write_eld = ironlake_write_eld;
10292                         dev_priv->display.modeset_global_resources =
10293                                 ivb_modeset_global_resources;
10294                 } else if (IS_HASWELL(dev)) {
10295                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10296                         dev_priv->display.write_eld = haswell_write_eld;
10297                         dev_priv->display.modeset_global_resources =
10298                                 haswell_modeset_global_resources;
10299                 }
10300         } else if (IS_G4X(dev)) {
10301                 dev_priv->display.write_eld = g4x_write_eld;
10302         }
10303
10304         /* Default just returns -ENODEV to indicate unsupported */
10305         dev_priv->display.queue_flip = intel_default_queue_flip;
10306
10307         switch (INTEL_INFO(dev)->gen) {
10308         case 2:
10309                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10310                 break;
10311
10312         case 3:
10313                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10314                 break;
10315
10316         case 4:
10317         case 5:
10318                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10319                 break;
10320
10321         case 6:
10322                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10323                 break;
10324         case 7:
10325                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10326                 break;
10327         }
10328 }
10329
10330 /*
10331  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10332  * resume, or other times.  This quirk makes sure that's the case for
10333  * affected systems.
10334  */
10335 static void quirk_pipea_force(struct drm_device *dev)
10336 {
10337         struct drm_i915_private *dev_priv = dev->dev_private;
10338
10339         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10340         DRM_INFO("applying pipe a force quirk\n");
10341 }
10342
10343 /*
10344  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10345  */
10346 static void quirk_ssc_force_disable(struct drm_device *dev)
10347 {
10348         struct drm_i915_private *dev_priv = dev->dev_private;
10349         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10350         DRM_INFO("applying lvds SSC disable quirk\n");
10351 }
10352
10353 /*
10354  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10355  * brightness value
10356  */
10357 static void quirk_invert_brightness(struct drm_device *dev)
10358 {
10359         struct drm_i915_private *dev_priv = dev->dev_private;
10360         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10361         DRM_INFO("applying inverted panel brightness quirk\n");
10362 }
10363
10364 /*
10365  * Some machines (Dell XPS13) suffer broken backlight controls if
10366  * BLM_PCH_PWM_ENABLE is set.
10367  */
10368 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10369 {
10370         struct drm_i915_private *dev_priv = dev->dev_private;
10371         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10372         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10373 }
10374
10375 struct intel_quirk {
10376         int device;
10377         int subsystem_vendor;
10378         int subsystem_device;
10379         void (*hook)(struct drm_device *dev);
10380 };
10381
10382 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10383 struct intel_dmi_quirk {
10384         void (*hook)(struct drm_device *dev);
10385         const struct dmi_system_id (*dmi_id_list)[];
10386 };
10387
10388 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10389 {
10390         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10391         return 1;
10392 }
10393
10394 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10395         {
10396                 .dmi_id_list = &(const struct dmi_system_id[]) {
10397                         {
10398                                 .callback = intel_dmi_reverse_brightness,
10399                                 .ident = "NCR Corporation",
10400                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10401                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10402                                 },
10403                         },
10404                         { }  /* terminating entry */
10405                 },
10406                 .hook = quirk_invert_brightness,
10407         },
10408 };
10409
10410 static struct intel_quirk intel_quirks[] = {
10411         /* HP Mini needs pipe A force quirk (LP: #322104) */
10412         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10413
10414         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10415         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10416
10417         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10418         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10419
10420         /* 830 needs to leave pipe A & dpll A up */
10421         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10422
10423         /* Lenovo U160 cannot use SSC on LVDS */
10424         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10425
10426         /* Sony Vaio Y cannot use SSC on LVDS */
10427         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10428
10429         /*
10430          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10431          * seem to use inverted backlight PWM.
10432          */
10433         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10434
10435         /* Dell XPS13 HD Sandy Bridge */
10436         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10437         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10438         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10439 };
10440
10441 static void intel_init_quirks(struct drm_device *dev)
10442 {
10443         struct pci_dev *d = dev->pdev;
10444         int i;
10445
10446         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10447                 struct intel_quirk *q = &intel_quirks[i];
10448
10449                 if (d->device == q->device &&
10450                     (d->subsystem_vendor == q->subsystem_vendor ||
10451                      q->subsystem_vendor == PCI_ANY_ID) &&
10452                     (d->subsystem_device == q->subsystem_device ||
10453                      q->subsystem_device == PCI_ANY_ID))
10454                         q->hook(dev);
10455         }
10456         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10457                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10458                         intel_dmi_quirks[i].hook(dev);
10459         }
10460 }
10461
10462 /* Disable the VGA plane that we never use */
10463 static void i915_disable_vga(struct drm_device *dev)
10464 {
10465         struct drm_i915_private *dev_priv = dev->dev_private;
10466         u8 sr1;
10467         u32 vga_reg = i915_vgacntrl_reg(dev);
10468
10469         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10470         outb(SR01, VGA_SR_INDEX);
10471         sr1 = inb(VGA_SR_DATA);
10472         outb(sr1 | 1<<5, VGA_SR_DATA);
10473         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10474         udelay(300);
10475
10476         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10477         POSTING_READ(vga_reg);
10478 }
10479
10480 void intel_modeset_init_hw(struct drm_device *dev)
10481 {
10482         struct drm_i915_private *dev_priv = dev->dev_private;
10483
10484         intel_prepare_ddi(dev);
10485
10486         intel_init_clock_gating(dev);
10487
10488         /* Enable the CRI clock source so we can get at the display */
10489         if (IS_VALLEYVIEW(dev))
10490                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10491                            DPLL_INTEGRATED_CRI_CLK_VLV);
10492
10493         intel_init_dpio(dev);
10494
10495         mutex_lock(&dev->struct_mutex);
10496         intel_enable_gt_powersave(dev);
10497         mutex_unlock(&dev->struct_mutex);
10498 }
10499
10500 void intel_modeset_suspend_hw(struct drm_device *dev)
10501 {
10502         intel_suspend_hw(dev);
10503 }
10504
10505 void intel_modeset_init(struct drm_device *dev)
10506 {
10507         struct drm_i915_private *dev_priv = dev->dev_private;
10508         int i, j, ret;
10509
10510         drm_mode_config_init(dev);
10511
10512         dev->mode_config.min_width = 0;
10513         dev->mode_config.min_height = 0;
10514
10515         dev->mode_config.preferred_depth = 24;
10516         dev->mode_config.prefer_shadow = 1;
10517
10518         dev->mode_config.funcs = &intel_mode_funcs;
10519
10520         intel_init_quirks(dev);
10521
10522         intel_init_pm(dev);
10523
10524         if (INTEL_INFO(dev)->num_pipes == 0)
10525                 return;
10526
10527         intel_init_display(dev);
10528
10529         if (IS_GEN2(dev)) {
10530                 dev->mode_config.max_width = 2048;
10531                 dev->mode_config.max_height = 2048;
10532         } else if (IS_GEN3(dev)) {
10533                 dev->mode_config.max_width = 4096;
10534                 dev->mode_config.max_height = 4096;
10535         } else {
10536                 dev->mode_config.max_width = 8192;
10537                 dev->mode_config.max_height = 8192;
10538         }
10539         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10540
10541         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10542                       INTEL_INFO(dev)->num_pipes,
10543                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10544
10545         for_each_pipe(i) {
10546                 intel_crtc_init(dev, i);
10547                 for (j = 0; j < dev_priv->num_plane; j++) {
10548                         ret = intel_plane_init(dev, i, j);
10549                         if (ret)
10550                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10551                                               pipe_name(i), sprite_name(i, j), ret);
10552                 }
10553         }
10554
10555         intel_cpu_pll_init(dev);
10556         intel_shared_dpll_init(dev);
10557
10558         /* Just disable it once at startup */
10559         i915_disable_vga(dev);
10560         intel_setup_outputs(dev);
10561
10562         /* Just in case the BIOS is doing something questionable. */
10563         intel_disable_fbc(dev);
10564 }
10565
10566 static void
10567 intel_connector_break_all_links(struct intel_connector *connector)
10568 {
10569         connector->base.dpms = DRM_MODE_DPMS_OFF;
10570         connector->base.encoder = NULL;
10571         connector->encoder->connectors_active = false;
10572         connector->encoder->base.crtc = NULL;
10573 }
10574
10575 static void intel_enable_pipe_a(struct drm_device *dev)
10576 {
10577         struct intel_connector *connector;
10578         struct drm_connector *crt = NULL;
10579         struct intel_load_detect_pipe load_detect_temp;
10580
10581         /* We can't just switch on the pipe A, we need to set things up with a
10582          * proper mode and output configuration. As a gross hack, enable pipe A
10583          * by enabling the load detect pipe once. */
10584         list_for_each_entry(connector,
10585                             &dev->mode_config.connector_list,
10586                             base.head) {
10587                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10588                         crt = &connector->base;
10589                         break;
10590                 }
10591         }
10592
10593         if (!crt)
10594                 return;
10595
10596         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10597                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10598
10599
10600 }
10601
10602 static bool
10603 intel_check_plane_mapping(struct intel_crtc *crtc)
10604 {
10605         struct drm_device *dev = crtc->base.dev;
10606         struct drm_i915_private *dev_priv = dev->dev_private;
10607         u32 reg, val;
10608
10609         if (INTEL_INFO(dev)->num_pipes == 1)
10610                 return true;
10611
10612         reg = DSPCNTR(!crtc->plane);
10613         val = I915_READ(reg);
10614
10615         if ((val & DISPLAY_PLANE_ENABLE) &&
10616             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10617                 return false;
10618
10619         return true;
10620 }
10621
10622 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10623 {
10624         struct drm_device *dev = crtc->base.dev;
10625         struct drm_i915_private *dev_priv = dev->dev_private;
10626         u32 reg;
10627
10628         /* Clear any frame start delays used for debugging left by the BIOS */
10629         reg = PIPECONF(crtc->config.cpu_transcoder);
10630         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10631
10632         /* We need to sanitize the plane -> pipe mapping first because this will
10633          * disable the crtc (and hence change the state) if it is wrong. Note
10634          * that gen4+ has a fixed plane -> pipe mapping.  */
10635         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10636                 struct intel_connector *connector;
10637                 bool plane;
10638
10639                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10640                               crtc->base.base.id);
10641
10642                 /* Pipe has the wrong plane attached and the plane is active.
10643                  * Temporarily change the plane mapping and disable everything
10644                  * ...  */
10645                 plane = crtc->plane;
10646                 crtc->plane = !plane;
10647                 dev_priv->display.crtc_disable(&crtc->base);
10648                 crtc->plane = plane;
10649
10650                 /* ... and break all links. */
10651                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10652                                     base.head) {
10653                         if (connector->encoder->base.crtc != &crtc->base)
10654                                 continue;
10655
10656                         intel_connector_break_all_links(connector);
10657                 }
10658
10659                 WARN_ON(crtc->active);
10660                 crtc->base.enabled = false;
10661         }
10662
10663         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10664             crtc->pipe == PIPE_A && !crtc->active) {
10665                 /* BIOS forgot to enable pipe A, this mostly happens after
10666                  * resume. Force-enable the pipe to fix this, the update_dpms
10667                  * call below we restore the pipe to the right state, but leave
10668                  * the required bits on. */
10669                 intel_enable_pipe_a(dev);
10670         }
10671
10672         /* Adjust the state of the output pipe according to whether we
10673          * have active connectors/encoders. */
10674         intel_crtc_update_dpms(&crtc->base);
10675
10676         if (crtc->active != crtc->base.enabled) {
10677                 struct intel_encoder *encoder;
10678
10679                 /* This can happen either due to bugs in the get_hw_state
10680                  * functions or because the pipe is force-enabled due to the
10681                  * pipe A quirk. */
10682                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10683                               crtc->base.base.id,
10684                               crtc->base.enabled ? "enabled" : "disabled",
10685                               crtc->active ? "enabled" : "disabled");
10686
10687                 crtc->base.enabled = crtc->active;
10688
10689                 /* Because we only establish the connector -> encoder ->
10690                  * crtc links if something is active, this means the
10691                  * crtc is now deactivated. Break the links. connector
10692                  * -> encoder links are only establish when things are
10693                  *  actually up, hence no need to break them. */
10694                 WARN_ON(crtc->active);
10695
10696                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10697                         WARN_ON(encoder->connectors_active);
10698                         encoder->base.crtc = NULL;
10699                 }
10700         }
10701 }
10702
10703 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10704 {
10705         struct intel_connector *connector;
10706         struct drm_device *dev = encoder->base.dev;
10707
10708         /* We need to check both for a crtc link (meaning that the
10709          * encoder is active and trying to read from a pipe) and the
10710          * pipe itself being active. */
10711         bool has_active_crtc = encoder->base.crtc &&
10712                 to_intel_crtc(encoder->base.crtc)->active;
10713
10714         if (encoder->connectors_active && !has_active_crtc) {
10715                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10716                               encoder->base.base.id,
10717                               drm_get_encoder_name(&encoder->base));
10718
10719                 /* Connector is active, but has no active pipe. This is
10720                  * fallout from our resume register restoring. Disable
10721                  * the encoder manually again. */
10722                 if (encoder->base.crtc) {
10723                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10724                                       encoder->base.base.id,
10725                                       drm_get_encoder_name(&encoder->base));
10726                         encoder->disable(encoder);
10727                 }
10728
10729                 /* Inconsistent output/port/pipe state happens presumably due to
10730                  * a bug in one of the get_hw_state functions. Or someplace else
10731                  * in our code, like the register restore mess on resume. Clamp
10732                  * things to off as a safer default. */
10733                 list_for_each_entry(connector,
10734                                     &dev->mode_config.connector_list,
10735                                     base.head) {
10736                         if (connector->encoder != encoder)
10737                                 continue;
10738
10739                         intel_connector_break_all_links(connector);
10740                 }
10741         }
10742         /* Enabled encoders without active connectors will be fixed in
10743          * the crtc fixup. */
10744 }
10745
10746 void i915_redisable_vga(struct drm_device *dev)
10747 {
10748         struct drm_i915_private *dev_priv = dev->dev_private;
10749         u32 vga_reg = i915_vgacntrl_reg(dev);
10750
10751         /* This function can be called both from intel_modeset_setup_hw_state or
10752          * at a very early point in our resume sequence, where the power well
10753          * structures are not yet restored. Since this function is at a very
10754          * paranoid "someone might have enabled VGA while we were not looking"
10755          * level, just check if the power well is enabled instead of trying to
10756          * follow the "don't touch the power well if we don't need it" policy
10757          * the rest of the driver uses. */
10758         if (HAS_POWER_WELL(dev) &&
10759             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10760                 return;
10761
10762         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10763                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10764                 i915_disable_vga(dev);
10765         }
10766 }
10767
10768 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10769 {
10770         struct drm_i915_private *dev_priv = dev->dev_private;
10771         enum pipe pipe;
10772         struct intel_crtc *crtc;
10773         struct intel_encoder *encoder;
10774         struct intel_connector *connector;
10775         int i;
10776
10777         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10778                             base.head) {
10779                 memset(&crtc->config, 0, sizeof(crtc->config));
10780
10781                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10782                                                                  &crtc->config);
10783
10784                 crtc->base.enabled = crtc->active;
10785                 crtc->primary_enabled = crtc->active;
10786
10787                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10788                               crtc->base.base.id,
10789                               crtc->active ? "enabled" : "disabled");
10790         }
10791
10792         /* FIXME: Smash this into the new shared dpll infrastructure. */
10793         if (HAS_DDI(dev))
10794                 intel_ddi_setup_hw_pll_state(dev);
10795
10796         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10797                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10798
10799                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10800                 pll->active = 0;
10801                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10802                                     base.head) {
10803                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10804                                 pll->active++;
10805                 }
10806                 pll->refcount = pll->active;
10807
10808                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10809                               pll->name, pll->refcount, pll->on);
10810         }
10811
10812         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10813                             base.head) {
10814                 pipe = 0;
10815
10816                 if (encoder->get_hw_state(encoder, &pipe)) {
10817                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10818                         encoder->base.crtc = &crtc->base;
10819                         if (encoder->get_config)
10820                                 encoder->get_config(encoder, &crtc->config);
10821                 } else {
10822                         encoder->base.crtc = NULL;
10823                 }
10824
10825                 encoder->connectors_active = false;
10826                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
10827                               encoder->base.base.id,
10828                               drm_get_encoder_name(&encoder->base),
10829                               encoder->base.crtc ? "enabled" : "disabled",
10830                               pipe_name(pipe));
10831         }
10832
10833         list_for_each_entry(connector, &dev->mode_config.connector_list,
10834                             base.head) {
10835                 if (connector->get_hw_state(connector)) {
10836                         connector->base.dpms = DRM_MODE_DPMS_ON;
10837                         connector->encoder->connectors_active = true;
10838                         connector->base.encoder = &connector->encoder->base;
10839                 } else {
10840                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10841                         connector->base.encoder = NULL;
10842                 }
10843                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10844                               connector->base.base.id,
10845                               drm_get_connector_name(&connector->base),
10846                               connector->base.encoder ? "enabled" : "disabled");
10847         }
10848 }
10849
10850 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10851  * and i915 state tracking structures. */
10852 void intel_modeset_setup_hw_state(struct drm_device *dev,
10853                                   bool force_restore)
10854 {
10855         struct drm_i915_private *dev_priv = dev->dev_private;
10856         enum pipe pipe;
10857         struct intel_crtc *crtc;
10858         struct intel_encoder *encoder;
10859         int i;
10860
10861         intel_modeset_readout_hw_state(dev);
10862
10863         /*
10864          * Now that we have the config, copy it to each CRTC struct
10865          * Note that this could go away if we move to using crtc_config
10866          * checking everywhere.
10867          */
10868         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10869                             base.head) {
10870                 if (crtc->active && i915_fastboot) {
10871                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10872
10873                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10874                                       crtc->base.base.id);
10875                         drm_mode_debug_printmodeline(&crtc->base.mode);
10876                 }
10877         }
10878
10879         /* HW state is read out, now we need to sanitize this mess. */
10880         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10881                             base.head) {
10882                 intel_sanitize_encoder(encoder);
10883         }
10884
10885         for_each_pipe(pipe) {
10886                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10887                 intel_sanitize_crtc(crtc);
10888                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10889         }
10890
10891         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10892                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10893
10894                 if (!pll->on || pll->active)
10895                         continue;
10896
10897                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10898
10899                 pll->disable(dev_priv, pll);
10900                 pll->on = false;
10901         }
10902
10903         if (IS_HASWELL(dev))
10904                 ilk_wm_get_hw_state(dev);
10905
10906         if (force_restore) {
10907                 i915_redisable_vga(dev);
10908
10909                 /*
10910                  * We need to use raw interfaces for restoring state to avoid
10911                  * checking (bogus) intermediate states.
10912                  */
10913                 for_each_pipe(pipe) {
10914                         struct drm_crtc *crtc =
10915                                 dev_priv->pipe_to_crtc_mapping[pipe];
10916
10917                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10918                                          crtc->fb);
10919                 }
10920         } else {
10921                 intel_modeset_update_staged_output_state(dev);
10922         }
10923
10924         intel_modeset_check_state(dev);
10925
10926         drm_mode_config_reset(dev);
10927 }
10928
10929 void intel_modeset_gem_init(struct drm_device *dev)
10930 {
10931         intel_modeset_init_hw(dev);
10932
10933         intel_setup_overlay(dev);
10934
10935         intel_modeset_setup_hw_state(dev, false);
10936 }
10937
10938 void intel_modeset_cleanup(struct drm_device *dev)
10939 {
10940         struct drm_i915_private *dev_priv = dev->dev_private;
10941         struct drm_crtc *crtc;
10942         struct drm_connector *connector;
10943
10944         /*
10945          * Interrupts and polling as the first thing to avoid creating havoc.
10946          * Too much stuff here (turning of rps, connectors, ...) would
10947          * experience fancy races otherwise.
10948          */
10949         drm_irq_uninstall(dev);
10950         cancel_work_sync(&dev_priv->hotplug_work);
10951         /*
10952          * Due to the hpd irq storm handling the hotplug work can re-arm the
10953          * poll handlers. Hence disable polling after hpd handling is shut down.
10954          */
10955         drm_kms_helper_poll_fini(dev);
10956
10957         mutex_lock(&dev->struct_mutex);
10958
10959         intel_unregister_dsm_handler();
10960
10961         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10962                 /* Skip inactive CRTCs */
10963                 if (!crtc->fb)
10964                         continue;
10965
10966                 intel_increase_pllclock(crtc);
10967         }
10968
10969         intel_disable_fbc(dev);
10970
10971         intel_disable_gt_powersave(dev);
10972
10973         ironlake_teardown_rc6(dev);
10974
10975         mutex_unlock(&dev->struct_mutex);
10976
10977         /* flush any delayed tasks or pending work */
10978         flush_scheduled_work();
10979
10980         /* destroy backlight, if any, before the connectors */
10981         intel_panel_destroy_backlight(dev);
10982
10983         /* destroy the sysfs files before encoders/connectors */
10984         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10985                 drm_sysfs_connector_remove(connector);
10986
10987         drm_mode_config_cleanup(dev);
10988
10989         intel_cleanup_overlay(dev);
10990 }
10991
10992 /*
10993  * Return which encoder is currently attached for connector.
10994  */
10995 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10996 {
10997         return &intel_attached_encoder(connector)->base;
10998 }
10999
11000 void intel_connector_attach_encoder(struct intel_connector *connector,
11001                                     struct intel_encoder *encoder)
11002 {
11003         connector->encoder = encoder;
11004         drm_mode_connector_attach_encoder(&connector->base,
11005                                           &encoder->base);
11006 }
11007
11008 /*
11009  * set vga decode state - true == enable VGA decode
11010  */
11011 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11012 {
11013         struct drm_i915_private *dev_priv = dev->dev_private;
11014         u16 gmch_ctrl;
11015
11016         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11017         if (state)
11018                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11019         else
11020                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11021         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11022         return 0;
11023 }
11024
11025 struct intel_display_error_state {
11026
11027         u32 power_well_driver;
11028
11029         int num_transcoders;
11030
11031         struct intel_cursor_error_state {
11032                 u32 control;
11033                 u32 position;
11034                 u32 base;
11035                 u32 size;
11036         } cursor[I915_MAX_PIPES];
11037
11038         struct intel_pipe_error_state {
11039                 u32 source;
11040         } pipe[I915_MAX_PIPES];
11041
11042         struct intel_plane_error_state {
11043                 u32 control;
11044                 u32 stride;
11045                 u32 size;
11046                 u32 pos;
11047                 u32 addr;
11048                 u32 surface;
11049                 u32 tile_offset;
11050         } plane[I915_MAX_PIPES];
11051
11052         struct intel_transcoder_error_state {
11053                 enum transcoder cpu_transcoder;
11054
11055                 u32 conf;
11056
11057                 u32 htotal;
11058                 u32 hblank;
11059                 u32 hsync;
11060                 u32 vtotal;
11061                 u32 vblank;
11062                 u32 vsync;
11063         } transcoder[4];
11064 };
11065
11066 struct intel_display_error_state *
11067 intel_display_capture_error_state(struct drm_device *dev)
11068 {
11069         drm_i915_private_t *dev_priv = dev->dev_private;
11070         struct intel_display_error_state *error;
11071         int transcoders[] = {
11072                 TRANSCODER_A,
11073                 TRANSCODER_B,
11074                 TRANSCODER_C,
11075                 TRANSCODER_EDP,
11076         };
11077         int i;
11078
11079         if (INTEL_INFO(dev)->num_pipes == 0)
11080                 return NULL;
11081
11082         error = kmalloc(sizeof(*error), GFP_ATOMIC);
11083         if (error == NULL)
11084                 return NULL;
11085
11086         if (HAS_POWER_WELL(dev))
11087                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11088
11089         for_each_pipe(i) {
11090                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11091                         error->cursor[i].control = I915_READ(CURCNTR(i));
11092                         error->cursor[i].position = I915_READ(CURPOS(i));
11093                         error->cursor[i].base = I915_READ(CURBASE(i));
11094                 } else {
11095                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11096                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11097                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11098                 }
11099
11100                 error->plane[i].control = I915_READ(DSPCNTR(i));
11101                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11102                 if (INTEL_INFO(dev)->gen <= 3) {
11103                         error->plane[i].size = I915_READ(DSPSIZE(i));
11104                         error->plane[i].pos = I915_READ(DSPPOS(i));
11105                 }
11106                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11107                         error->plane[i].addr = I915_READ(DSPADDR(i));
11108                 if (INTEL_INFO(dev)->gen >= 4) {
11109                         error->plane[i].surface = I915_READ(DSPSURF(i));
11110                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11111                 }
11112
11113                 error->pipe[i].source = I915_READ(PIPESRC(i));
11114         }
11115
11116         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11117         if (HAS_DDI(dev_priv->dev))
11118                 error->num_transcoders++; /* Account for eDP. */
11119
11120         for (i = 0; i < error->num_transcoders; i++) {
11121                 enum transcoder cpu_transcoder = transcoders[i];
11122
11123                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11124
11125                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11126                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11127                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11128                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11129                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11130                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11131                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11132         }
11133
11134         /* In the code above we read the registers without checking if the power
11135          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11136          * prevent the next I915_WRITE from detecting it and printing an error
11137          * message. */
11138         intel_uncore_clear_errors(dev);
11139
11140         return error;
11141 }
11142
11143 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11144
11145 void
11146 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11147                                 struct drm_device *dev,
11148                                 struct intel_display_error_state *error)
11149 {
11150         int i;
11151
11152         if (!error)
11153                 return;
11154
11155         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11156         if (HAS_POWER_WELL(dev))
11157                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11158                            error->power_well_driver);
11159         for_each_pipe(i) {
11160                 err_printf(m, "Pipe [%d]:\n", i);
11161                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11162
11163                 err_printf(m, "Plane [%d]:\n", i);
11164                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11165                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11166                 if (INTEL_INFO(dev)->gen <= 3) {
11167                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11168                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11169                 }
11170                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11171                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11172                 if (INTEL_INFO(dev)->gen >= 4) {
11173                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11174                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11175                 }
11176
11177                 err_printf(m, "Cursor [%d]:\n", i);
11178                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11179                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11180                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11181         }
11182
11183         for (i = 0; i < error->num_transcoders; i++) {
11184                 err_printf(m, "CPU transcoder: %c\n",
11185                            transcoder_name(error->transcoder[i].cpu_transcoder));
11186                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11187                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11188                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11189                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11190                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11191                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11192                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11193         }
11194 }