drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         case HDMI_INFOFRAME_TYPE_VENDOR:
  78                 return VIDEO_DIP_SELECT_VENDOR;
  79         default:
  80                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81                 return 0;
  82         }
  83 }
  84
  85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86 {
  87         switch (type) {
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_ENABLE_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_ENABLE_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_ENABLE_VENDOR;
  94         default:
  95                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 101 {
 102         switch (type) {
 103         case HDMI_INFOFRAME_TYPE_AVI:
 104                 return VIDEO_DIP_ENABLE_AVI_HSW;
 105         case HDMI_INFOFRAME_TYPE_SPD:
 106                 return VIDEO_DIP_ENABLE_SPD_HSW;
 107         case HDMI_INFOFRAME_TYPE_VENDOR:
 108                 return VIDEO_DIP_ENABLE_VS_HSW;
 109         default:
 110                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 111                 return 0;
 112         }
 113 }
 114
 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 116                                   enum transcoder cpu_transcoder,
 117                                   struct drm_i915_private *dev_priv)
 118 {
 119         switch (type) {
 120         case HDMI_INFOFRAME_TYPE_AVI:
 121                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 122         case HDMI_INFOFRAME_TYPE_SPD:
 123                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 124         case HDMI_INFOFRAME_TYPE_VENDOR:
 125                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 126         default:
 127                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 128                 return 0;
 129         }
 130 }
 131
 132 static void g4x_write_infoframe(struct drm_encoder *encoder,
 133                                 enum hdmi_infoframe_type type,
 134                                 const void *frame, ssize_t len)
 135 {
 136         const uint32_t *data = frame;
 137         struct drm_device *dev = encoder->dev;
 138         struct drm_i915_private *dev_priv = dev->dev_private;
 139         u32 val = I915_READ(VIDEO_DIP_CTL);
 140         int i;
 141
 142         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 143
 144         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 145         val |= g4x_infoframe_index(type);
 146
 147         val &= ~g4x_infoframe_enable(type);
 148
 149         I915_WRITE(VIDEO_DIP_CTL, val);
 150
 151         mmiowb();
 152         for (i = 0; i < len; i += 4) {
 153                 I915_WRITE(VIDEO_DIP_DATA, *data);
 154                 data++;
 155         }
 156         /* Write every possible data byte to force correct ECC calculation. */
 157         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 158                 I915_WRITE(VIDEO_DIP_DATA, 0);
 159         mmiowb();
 160
 161         val |= g4x_infoframe_enable(type);
 162         val &= ~VIDEO_DIP_FREQ_MASK;
 163         val |= VIDEO_DIP_FREQ_VSYNC;
 164
 165         I915_WRITE(VIDEO_DIP_CTL, val);
 166         POSTING_READ(VIDEO_DIP_CTL);
 167 }
 168
 169 static void ibx_write_infoframe(struct drm_encoder *encoder,
 170                                 enum hdmi_infoframe_type type,
 171                                 const void *frame, ssize_t len)
 172 {
 173         const uint32_t *data = frame;
 174         struct drm_device *dev = encoder->dev;
 175         struct drm_i915_private *dev_priv = dev->dev_private;
 176         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 177         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 178         u32 val = I915_READ(reg);
 179
 180         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 181
 182         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 183         val |= g4x_infoframe_index(type);
 184
 185         val &= ~g4x_infoframe_enable(type);
 186
 187         I915_WRITE(reg, val);
 188
 189         mmiowb();
 190         for (i = 0; i < len; i += 4) {
 191                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 192                 data++;
 193         }
 194         /* Write every possible data byte to force correct ECC calculation. */
 195         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 196                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 197         mmiowb();
 198
 199         val |= g4x_infoframe_enable(type);
 200         val &= ~VIDEO_DIP_FREQ_MASK;
 201         val |= VIDEO_DIP_FREQ_VSYNC;
 202
 203         I915_WRITE(reg, val);
 204         POSTING_READ(reg);
 205 }
 206
 207 static void cpt_write_infoframe(struct drm_encoder *encoder,
 208                                 enum hdmi_infoframe_type type,
 209                                 const void *frame, ssize_t len)
 210 {
 211         const uint32_t *data = frame;
 212         struct drm_device *dev = encoder->dev;
 213         struct drm_i915_private *dev_priv = dev->dev_private;
 214         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 215         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 216         u32 val = I915_READ(reg);
 217
 218         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 219
 220         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 221         val |= g4x_infoframe_index(type);
 222
 223         /* The DIP control register spec says that we need to update the AVI
 224          * infoframe without clearing its enable bit */
 225         if (type != HDMI_INFOFRAME_TYPE_AVI)
 226                 val &= ~g4x_infoframe_enable(type);
 227
 228         I915_WRITE(reg, val);
 229
 230         mmiowb();
 231         for (i = 0; i < len; i += 4) {
 232                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 233                 data++;
 234         }
 235         /* Write every possible data byte to force correct ECC calculation. */
 236         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 237                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 238         mmiowb();
 239
 240         val |= g4x_infoframe_enable(type);
 241         val &= ~VIDEO_DIP_FREQ_MASK;
 242         val |= VIDEO_DIP_FREQ_VSYNC;
 243
 244         I915_WRITE(reg, val);
 245         POSTING_READ(reg);
 246 }
 247
 248 static void vlv_write_infoframe(struct drm_encoder *encoder,
 249                                 enum hdmi_infoframe_type type,
 250                                 const void *frame, ssize_t len)
 251 {
 252         const uint32_t *data = frame;
 253         struct drm_device *dev = encoder->dev;
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 256         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 257         u32 val = I915_READ(reg);
 258
 259         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 260
 261         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 262         val |= g4x_infoframe_index(type);
 263
 264         val &= ~g4x_infoframe_enable(type);
 265
 266         I915_WRITE(reg, val);
 267
 268         mmiowb();
 269         for (i = 0; i < len; i += 4) {
 270                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 271                 data++;
 272         }
 273         /* Write every possible data byte to force correct ECC calculation. */
 274         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 275                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 276         mmiowb();
 277
 278         val |= g4x_infoframe_enable(type);
 279         val &= ~VIDEO_DIP_FREQ_MASK;
 280         val |= VIDEO_DIP_FREQ_VSYNC;
 281
 282         I915_WRITE(reg, val);
 283         POSTING_READ(reg);
 284 }
 285
 286 static void hsw_write_infoframe(struct drm_encoder *encoder,
 287                                 enum hdmi_infoframe_type type,
 288                                 const void *frame, ssize_t len)
 289 {
 290         const uint32_t *data = frame;
 291         struct drm_device *dev = encoder->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 294         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 295         u32 data_reg;
 296         int i;
 297         u32 val = I915_READ(ctl_reg);
 298
 299         data_reg = hsw_infoframe_data_reg(type,
 300                                           intel_crtc->config.cpu_transcoder,
 301                                           dev_priv);
 302         if (data_reg == 0)
 303                 return;
 304
 305         val &= ~hsw_infoframe_enable(type);
 306         I915_WRITE(ctl_reg, val);
 307
 308         mmiowb();
 309         for (i = 0; i < len; i += 4) {
 310                 I915_WRITE(data_reg + i, *data);
 311                 data++;
 312         }
 313         /* Write every possible data byte to force correct ECC calculation. */
 314         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 315                 I915_WRITE(data_reg + i, 0);
 316         mmiowb();
 317
 318         val |= hsw_infoframe_enable(type);
 319         I915_WRITE(ctl_reg, val);
 320         POSTING_READ(ctl_reg);
 321 }
 322
 323 /*
 324  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 325  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 326  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 327  * used for both technologies.
 328  *
 329  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 330  * DW1:       DB3       | DB2 | DB1 | DB0
 331  * DW2:       DB7       | DB6 | DB5 | DB4
 332  * DW3: ...
 333  *
 334  * (HB is Header Byte, DB is Data Byte)
 335  *
 336  * The hdmi pack() functions don't know about that hardware specific hole so we
 337  * trick them by giving an offset into the buffer and moving back the header
 338  * bytes by one.
 339  */
 340 static void intel_write_infoframe(struct drm_encoder *encoder,
 341                                   union hdmi_infoframe *frame)
 342 {
 343         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 344         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 345         ssize_t len;
 346
 347         /* see comment above for the reason for this offset */
 348         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 349         if (len < 0)
 350                 return;
 351
 352         /* Insert the 'hole' (see big comment above) at position 3 */
 353         buffer[0] = buffer[1];
 354         buffer[1] = buffer[2];
 355         buffer[2] = buffer[3];
 356         buffer[3] = 0;
 357         len++;
 358
 359         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 360 }
 361
 362 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 363                                          struct drm_display_mode *adjusted_mode)
 364 {
 365         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 366         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 367         union hdmi_infoframe frame;
 368         int ret;
 369
 370         /* Set user selected PAR to incoming mode's member */
 371         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 372
 373         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 374                                                        adjusted_mode);
 375         if (ret < 0) {
 376                 DRM_ERROR("couldn't fill AVI infoframe\n");
 377                 return;
 378         }
 379
 380         if (intel_hdmi->rgb_quant_range_selectable) {
 381                 if (intel_crtc->config.limited_color_range)
 382                         frame.avi.quantization_range =
 383                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 384                 else
 385                         frame.avi.quantization_range =
 386                                 HDMI_QUANTIZATION_RANGE_FULL;
 387         }
 388
 389         intel_write_infoframe(encoder, &frame);
 390 }
 391
 392 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 393 {
 394         union hdmi_infoframe frame;
 395         int ret;
 396
 397         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 398         if (ret < 0) {
 399                 DRM_ERROR("couldn't fill SPD infoframe\n");
 400                 return;
 401         }
 402
 403         frame.spd.sdi = HDMI_SPD_SDI_PC;
 404
 405         intel_write_infoframe(encoder, &frame);
 406 }
 407
 408 static void
 409 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 410                               struct drm_display_mode *adjusted_mode)
 411 {
 412         union hdmi_infoframe frame;
 413         int ret;
 414
 415         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 416                                                           adjusted_mode);
 417         if (ret < 0)
 418                 return;
 419
 420         intel_write_infoframe(encoder, &frame);
 421 }
 422
 423 static void g4x_set_infoframes(struct drm_encoder *encoder,
 424                                bool enable,
 425                                struct drm_display_mode *adjusted_mode)
 426 {
 427         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 428         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 429         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 430         u32 reg = VIDEO_DIP_CTL;
 431         u32 val = I915_READ(reg);
 432         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 433
 434         assert_hdmi_port_disabled(intel_hdmi);
 435
 436         /* If the registers were not initialized yet, they might be zeroes,
 437          * which means we're selecting the AVI DIP and we're setting its
 438          * frequency to once. This seems to really confuse the HW and make
 439          * things stop working (the register spec says the AVI always needs to
 440          * be sent every VSync). So here we avoid writing to the register more
 441          * than we need and also explicitly select the AVI DIP and explicitly
 442          * set its frequency to every VSync. Avoiding to write it twice seems to
 443          * be enough to solve the problem, but being defensive shouldn't hurt us
 444          * either. */
 445         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 446
 447         if (!enable) {
 448                 if (!(val & VIDEO_DIP_ENABLE))
 449                         return;
 450                 val &= ~VIDEO_DIP_ENABLE;
 451                 I915_WRITE(reg, val);
 452                 POSTING_READ(reg);
 453                 return;
 454         }
 455
 456         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 457                 if (val & VIDEO_DIP_ENABLE) {
 458                         val &= ~VIDEO_DIP_ENABLE;
 459                         I915_WRITE(reg, val);
 460                         POSTING_READ(reg);
 461                 }
 462                 val &= ~VIDEO_DIP_PORT_MASK;
 463                 val |= port;
 464         }
 465
 466         val |= VIDEO_DIP_ENABLE;
 467         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 468
 469         I915_WRITE(reg, val);
 470         POSTING_READ(reg);
 471
 472         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 473         intel_hdmi_set_spd_infoframe(encoder);
 474         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 475 }
 476
 477 static void ibx_set_infoframes(struct drm_encoder *encoder,
 478                                bool enable,
 479                                struct drm_display_mode *adjusted_mode)
 480 {
 481         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 482         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 483         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 484         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 485         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 486         u32 val = I915_READ(reg);
 487         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 488
 489         assert_hdmi_port_disabled(intel_hdmi);
 490
 491         /* See the big comment in g4x_set_infoframes() */
 492         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 493
 494         if (!enable) {
 495                 if (!(val & VIDEO_DIP_ENABLE))
 496                         return;
 497                 val &= ~VIDEO_DIP_ENABLE;
 498                 I915_WRITE(reg, val);
 499                 POSTING_READ(reg);
 500                 return;
 501         }
 502
 503         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 504                 if (val & VIDEO_DIP_ENABLE) {
 505                         val &= ~VIDEO_DIP_ENABLE;
 506                         I915_WRITE(reg, val);
 507                         POSTING_READ(reg);
 508                 }
 509                 val &= ~VIDEO_DIP_PORT_MASK;
 510                 val |= port;
 511         }
 512
 513         val |= VIDEO_DIP_ENABLE;
 514         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 515                  VIDEO_DIP_ENABLE_GCP);
 516
 517         I915_WRITE(reg, val);
 518         POSTING_READ(reg);
 519
 520         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 521         intel_hdmi_set_spd_infoframe(encoder);
 522         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 523 }
 524
 525 static void cpt_set_infoframes(struct drm_encoder *encoder,
 526                                bool enable,
 527                                struct drm_display_mode *adjusted_mode)
 528 {
 529         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 530         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 531         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 532         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 533         u32 val = I915_READ(reg);
 534
 535         assert_hdmi_port_disabled(intel_hdmi);
 536
 537         /* See the big comment in g4x_set_infoframes() */
 538         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 539
 540         if (!enable) {
 541                 if (!(val & VIDEO_DIP_ENABLE))
 542                         return;
 543                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 544                 I915_WRITE(reg, val);
 545                 POSTING_READ(reg);
 546                 return;
 547         }
 548
 549         /* Set both together, unset both together: see the spec. */
 550         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 551         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 552                  VIDEO_DIP_ENABLE_GCP);
 553
 554         I915_WRITE(reg, val);
 555         POSTING_READ(reg);
 556
 557         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 558         intel_hdmi_set_spd_infoframe(encoder);
 559         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 560 }
 561
 562 static void vlv_set_infoframes(struct drm_encoder *encoder,
 563                                bool enable,
 564                                struct drm_display_mode *adjusted_mode)
 565 {
 566         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 567         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 568         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 569         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 570         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 571         u32 val = I915_READ(reg);
 572         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 573
 574         assert_hdmi_port_disabled(intel_hdmi);
 575
 576         /* See the big comment in g4x_set_infoframes() */
 577         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 578
 579         if (!enable) {
 580                 if (!(val & VIDEO_DIP_ENABLE))
 581                         return;
 582                 val &= ~VIDEO_DIP_ENABLE;
 583                 I915_WRITE(reg, val);
 584                 POSTING_READ(reg);
 585                 return;
 586         }
 587
 588         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 589                 if (val & VIDEO_DIP_ENABLE) {
 590                         val &= ~VIDEO_DIP_ENABLE;
 591                         I915_WRITE(reg, val);
 592                         POSTING_READ(reg);
 593                 }
 594                 val &= ~VIDEO_DIP_PORT_MASK;
 595                 val |= port;
 596         }
 597
 598         val |= VIDEO_DIP_ENABLE;
 599         val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
 600                  VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
 601
 602         I915_WRITE(reg, val);
 603         POSTING_READ(reg);
 604
 605         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 606         intel_hdmi_set_spd_infoframe(encoder);
 607         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 608 }
 609
 610 static void hsw_set_infoframes(struct drm_encoder *encoder,
 611                                bool enable,
 612                                struct drm_display_mode *adjusted_mode)
 613 {
 614         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 615         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 616         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 617         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 618         u32 val = I915_READ(reg);
 619
 620         assert_hdmi_port_disabled(intel_hdmi);
 621
 622         if (!enable) {
 623                 I915_WRITE(reg, 0);
 624                 POSTING_READ(reg);
 625                 return;
 626         }
 627
 628         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 629                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 630
 631         I915_WRITE(reg, val);
 632         POSTING_READ(reg);
 633
 634         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 635         intel_hdmi_set_spd_infoframe(encoder);
 636         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 637 }
 638
 639 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 640 {
 641         struct drm_device *dev = encoder->base.dev;
 642         struct drm_i915_private *dev_priv = dev->dev_private;
 643         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 644         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 645         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 646         u32 hdmi_val;
 647
 648         hdmi_val = SDVO_ENCODING_HDMI;
 649         if (!HAS_PCH_SPLIT(dev))
 650                 hdmi_val |= intel_hdmi->color_range;
 651         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 652                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 653         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 654                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 655
 656         if (crtc->config.pipe_bpp > 24)
 657                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 658         else
 659                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 660
 661         if (crtc->config.has_hdmi_sink)
 662                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 663
 664         if (crtc->config.has_audio) {
 665                 WARN_ON(!crtc->config.has_hdmi_sink);
 666                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 667                                  pipe_name(crtc->pipe));
 668                 hdmi_val |= SDVO_AUDIO_ENABLE;
 669                 intel_write_eld(&encoder->base, adjusted_mode);
 670         }
 671
 672         if (HAS_PCH_CPT(dev))
 673                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 674         else if (IS_CHERRYVIEW(dev))
 675                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 676         else
 677                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 678
 679         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 680         POSTING_READ(intel_hdmi->hdmi_reg);
 681 }
 682
 683 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 684                                     enum pipe *pipe)
 685 {
 686         struct drm_device *dev = encoder->base.dev;
 687         struct drm_i915_private *dev_priv = dev->dev_private;
 688         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 689         enum intel_display_power_domain power_domain;
 690         u32 tmp;
 691
 692         power_domain = intel_display_port_power_domain(encoder);
 693         if (!intel_display_power_enabled(dev_priv, power_domain))
 694                 return false;
 695
 696         tmp = I915_READ(intel_hdmi->hdmi_reg);
 697
 698         if (!(tmp & SDVO_ENABLE))
 699                 return false;
 700
 701         if (HAS_PCH_CPT(dev))
 702                 *pipe = PORT_TO_PIPE_CPT(tmp);
 703         else if (IS_CHERRYVIEW(dev))
 704                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 705         else
 706                 *pipe = PORT_TO_PIPE(tmp);
 707
 708         return true;
 709 }
 710
 711 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 712                                   struct intel_crtc_config *pipe_config)
 713 {
 714         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 715         struct drm_device *dev = encoder->base.dev;
 716         struct drm_i915_private *dev_priv = dev->dev_private;
 717         u32 tmp, flags = 0;
 718         int dotclock;
 719
 720         tmp = I915_READ(intel_hdmi->hdmi_reg);
 721
 722         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 723                 flags |= DRM_MODE_FLAG_PHSYNC;
 724         else
 725                 flags |= DRM_MODE_FLAG_NHSYNC;
 726
 727         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 728                 flags |= DRM_MODE_FLAG_PVSYNC;
 729         else
 730                 flags |= DRM_MODE_FLAG_NVSYNC;
 731
 732         if (tmp & HDMI_MODE_SELECT_HDMI)
 733                 pipe_config->has_hdmi_sink = true;
 734
 735         if (tmp & SDVO_AUDIO_ENABLE)
 736                 pipe_config->has_audio = true;
 737
 738         if (!HAS_PCH_SPLIT(dev) &&
 739             tmp & HDMI_COLOR_RANGE_16_235)
 740                 pipe_config->limited_color_range = true;
 741
 742         pipe_config->adjusted_mode.flags |= flags;
 743
 744         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 745                 dotclock = pipe_config->port_clock * 2 / 3;
 746         else
 747                 dotclock = pipe_config->port_clock;
 748
 749         if (HAS_PCH_SPLIT(dev_priv->dev))
 750                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 751
 752         pipe_config->adjusted_mode.crtc_clock = dotclock;
 753 }
 754
 755 static void intel_enable_hdmi(struct intel_encoder *encoder)
 756 {
 757         struct drm_device *dev = encoder->base.dev;
 758         struct drm_i915_private *dev_priv = dev->dev_private;
 759         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 760         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 761         u32 temp;
 762         u32 enable_bits = SDVO_ENABLE;
 763
 764         if (intel_crtc->config.has_audio)
 765                 enable_bits |= SDVO_AUDIO_ENABLE;
 766
 767         temp = I915_READ(intel_hdmi->hdmi_reg);
 768
 769         /* HW workaround for IBX, we need to move the port to transcoder A
 770          * before disabling it, so restore the transcoder select bit here. */
 771         if (HAS_PCH_IBX(dev))
 772                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 773
 774         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 775          * we do this anyway which shows more stable in testing.
 776          */
 777         if (HAS_PCH_SPLIT(dev)) {
 778                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 779                 POSTING_READ(intel_hdmi->hdmi_reg);
 780         }
 781
 782         temp |= enable_bits;
 783
 784         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 785         POSTING_READ(intel_hdmi->hdmi_reg);
 786
 787         /* HW workaround, need to write this twice for issue that may result
 788          * in first write getting masked.
 789          */
 790         if (HAS_PCH_SPLIT(dev)) {
 791                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 792                 POSTING_READ(intel_hdmi->hdmi_reg);
 793         }
 794 }
 795
 796 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 797 {
 798 }
 799
 800 static void intel_disable_hdmi(struct intel_encoder *encoder)
 801 {
 802         struct drm_device *dev = encoder->base.dev;
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 805         u32 temp;
 806         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 807
 808         temp = I915_READ(intel_hdmi->hdmi_reg);
 809
 810         /* HW workaround for IBX, we need to move the port to transcoder A
 811          * before disabling it. */
 812         if (HAS_PCH_IBX(dev)) {
 813                 struct drm_crtc *crtc = encoder->base.crtc;
 814                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 815
 816                 if (temp & SDVO_PIPE_B_SELECT) {
 817                         temp &= ~SDVO_PIPE_B_SELECT;
 818                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 819                         POSTING_READ(intel_hdmi->hdmi_reg);
 820
 821                         /* Again we need to write this twice. */
 822                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 823                         POSTING_READ(intel_hdmi->hdmi_reg);
 824
 825                         /* Transcoder selection bits only update
 826                          * effectively on vblank. */
 827                         if (crtc)
 828                                 intel_wait_for_vblank(dev, pipe);
 829                         else
 830                                 msleep(50);
 831                 }
 832         }
 833
 834         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 835          * we do this anyway which shows more stable in testing.
 836          */
 837         if (HAS_PCH_SPLIT(dev)) {
 838                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 839                 POSTING_READ(intel_hdmi->hdmi_reg);
 840         }
 841
 842         temp &= ~enable_bits;
 843
 844         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 845         POSTING_READ(intel_hdmi->hdmi_reg);
 846
 847         /* HW workaround, need to write this twice for issue that may result
 848          * in first write getting masked.
 849          */
 850         if (HAS_PCH_SPLIT(dev)) {
 851                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 852                 POSTING_READ(intel_hdmi->hdmi_reg);
 853         }
 854 }
 855
 856 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 857 {
 858         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 859
 860         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
 861                 return 165000;
 862         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 863                 return 300000;
 864         else
 865                 return 225000;
 866 }
 867
 868 static enum drm_mode_status
 869 intel_hdmi_mode_valid(struct drm_connector *connector,
 870                       struct drm_display_mode *mode)
 871 {
 872         if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
 873                                                true))
 874                 return MODE_CLOCK_HIGH;
 875         if (mode->clock < 20000)
 876                 return MODE_CLOCK_LOW;
 877
 878         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 879                 return MODE_NO_DBLESCAN;
 880
 881         return MODE_OK;
 882 }
 883
 884 static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
 885 {
 886         struct drm_device *dev = crtc->base.dev;
 887         struct intel_encoder *encoder;
 888         int count = 0, count_hdmi = 0;
 889
 890         if (HAS_GMCH_DISPLAY(dev))
 891                 return false;
 892
 893         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 894                 if (encoder->new_crtc != crtc)
 895                         continue;
 896
 897                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
 898                 count++;
 899         }
 900
 901         /*
 902          * HDMI 12bpc affects the clocks, so it's only possible
 903          * when not cloning with other encoder types.
 904          */
 905         return count_hdmi > 0 && count_hdmi == count;
 906 }
 907
 908 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 909                                struct intel_crtc_config *pipe_config)
 910 {
 911         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 912         struct drm_device *dev = encoder->base.dev;
 913         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 914         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 915         int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
 916         int desired_bpp;
 917
 918         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
 919
 920         if (intel_hdmi->color_range_auto) {
 921                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 922                 if (pipe_config->has_hdmi_sink &&
 923                     drm_match_cea_mode(adjusted_mode) > 1)
 924                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 925                 else
 926                         intel_hdmi->color_range = 0;
 927         }
 928
 929         if (intel_hdmi->color_range)
 930                 pipe_config->limited_color_range = true;
 931
 932         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 933                 pipe_config->has_pch_encoder = true;
 934
 935         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
 936                 pipe_config->has_audio = true;
 937
 938         /*
 939          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 940          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 941          * outputs. We also need to check that the higher clock still fits
 942          * within limits.
 943          */
 944         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
 945             clock_12bpc <= portclock_limit &&
 946             hdmi_12bpc_possible(encoder->new_crtc)) {
 947                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 948                 desired_bpp = 12*3;
 949
 950                 /* Need to adjust the port link by 1.5x for 12bpc. */
 951                 pipe_config->port_clock = clock_12bpc;
 952         } else {
 953                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 954                 desired_bpp = 8*3;
 955         }
 956
 957         if (!pipe_config->bw_constrained) {
 958                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 959                 pipe_config->pipe_bpp = desired_bpp;
 960         }
 961
 962         if (adjusted_mode->crtc_clock > portclock_limit) {
 963                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 964                 return false;
 965         }
 966
 967         return true;
 968 }
 969
 970 static enum drm_connector_status
 971 intel_hdmi_detect(struct drm_connector *connector, bool force)
 972 {
 973         struct drm_device *dev = connector->dev;
 974         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 975         struct intel_digital_port *intel_dig_port =
 976                 hdmi_to_dig_port(intel_hdmi);
 977         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 978         struct drm_i915_private *dev_priv = dev->dev_private;
 979         struct edid *edid;
 980         enum intel_display_power_domain power_domain;
 981         enum drm_connector_status status = connector_status_disconnected;
 982
 983         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 984                       connector->base.id, connector->name);
 985
 986         power_domain = intel_display_port_power_domain(intel_encoder);
 987         intel_display_power_get(dev_priv, power_domain);
 988
 989         intel_hdmi->has_hdmi_sink = false;
 990         intel_hdmi->has_audio = false;
 991         intel_hdmi->rgb_quant_range_selectable = false;
 992         edid = drm_get_edid(connector,
 993                             intel_gmbus_get_adapter(dev_priv,
 994                                                     intel_hdmi->ddc_bus));
 995
 996         if (edid) {
 997                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 998                         status = connector_status_connected;
 999                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1000                                 intel_hdmi->has_hdmi_sink =
1001                                                 drm_detect_hdmi_monitor(edid);
1002                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1003                         intel_hdmi->rgb_quant_range_selectable =
1004                                 drm_rgb_quant_range_selectable(edid);
1005                 }
1006                 kfree(edid);
1007         }
1008
1009         if (status == connector_status_connected) {
1010                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1011                         intel_hdmi->has_audio =
1012                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
1013                 intel_encoder->type = INTEL_OUTPUT_HDMI;
1014         }
1015
1016         intel_display_power_put(dev_priv, power_domain);
1017
1018         return status;
1019 }
1020
1021 static int intel_hdmi_get_modes(struct drm_connector *connector)
1022 {
1023         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1024         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1025         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1026         enum intel_display_power_domain power_domain;
1027         int ret;
1028
1029         /* We should parse the EDID data and find out if it's an HDMI sink so
1030          * we can send audio to it.
1031          */
1032
1033         power_domain = intel_display_port_power_domain(intel_encoder);
1034         intel_display_power_get(dev_priv, power_domain);
1035
1036         ret = intel_ddc_get_modes(connector,
1037                                    intel_gmbus_get_adapter(dev_priv,
1038                                                            intel_hdmi->ddc_bus));
1039
1040         intel_display_power_put(dev_priv, power_domain);
1041
1042         return ret;
1043 }
1044
1045 static bool
1046 intel_hdmi_detect_audio(struct drm_connector *connector)
1047 {
1048         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1049         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1050         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1051         enum intel_display_power_domain power_domain;
1052         struct edid *edid;
1053         bool has_audio = false;
1054
1055         power_domain = intel_display_port_power_domain(intel_encoder);
1056         intel_display_power_get(dev_priv, power_domain);
1057
1058         edid = drm_get_edid(connector,
1059                             intel_gmbus_get_adapter(dev_priv,
1060                                                     intel_hdmi->ddc_bus));
1061         if (edid) {
1062                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1063                         has_audio = drm_detect_monitor_audio(edid);
1064                 kfree(edid);
1065         }
1066
1067         intel_display_power_put(dev_priv, power_domain);
1068
1069         return has_audio;
1070 }
1071
1072 static int
1073 intel_hdmi_set_property(struct drm_connector *connector,
1074                         struct drm_property *property,
1075                         uint64_t val)
1076 {
1077         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1078         struct intel_digital_port *intel_dig_port =
1079                 hdmi_to_dig_port(intel_hdmi);
1080         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1081         int ret;
1082
1083         ret = drm_object_property_set_value(&connector->base, property, val);
1084         if (ret)
1085                 return ret;
1086
1087         if (property == dev_priv->force_audio_property) {
1088                 enum hdmi_force_audio i = val;
1089                 bool has_audio;
1090
1091                 if (i == intel_hdmi->force_audio)
1092                         return 0;
1093
1094                 intel_hdmi->force_audio = i;
1095
1096                 if (i == HDMI_AUDIO_AUTO)
1097                         has_audio = intel_hdmi_detect_audio(connector);
1098                 else
1099                         has_audio = (i == HDMI_AUDIO_ON);
1100
1101                 if (i == HDMI_AUDIO_OFF_DVI)
1102                         intel_hdmi->has_hdmi_sink = 0;
1103
1104                 intel_hdmi->has_audio = has_audio;
1105                 goto done;
1106         }
1107
1108         if (property == dev_priv->broadcast_rgb_property) {
1109                 bool old_auto = intel_hdmi->color_range_auto;
1110                 uint32_t old_range = intel_hdmi->color_range;
1111
1112                 switch (val) {
1113                 case INTEL_BROADCAST_RGB_AUTO:
1114                         intel_hdmi->color_range_auto = true;
1115                         break;
1116                 case INTEL_BROADCAST_RGB_FULL:
1117                         intel_hdmi->color_range_auto = false;
1118                         intel_hdmi->color_range = 0;
1119                         break;
1120                 case INTEL_BROADCAST_RGB_LIMITED:
1121                         intel_hdmi->color_range_auto = false;
1122                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1123                         break;
1124                 default:
1125                         return -EINVAL;
1126                 }
1127
1128                 if (old_auto == intel_hdmi->color_range_auto &&
1129                     old_range == intel_hdmi->color_range)
1130                         return 0;
1131
1132                 goto done;
1133         }
1134
1135         if (property == connector->dev->mode_config.aspect_ratio_property) {
1136                 switch (val) {
1137                 case DRM_MODE_PICTURE_ASPECT_NONE:
1138                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1139                         break;
1140                 case DRM_MODE_PICTURE_ASPECT_4_3:
1141                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1142                         break;
1143                 case DRM_MODE_PICTURE_ASPECT_16_9:
1144                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1145                         break;
1146                 default:
1147                         return -EINVAL;
1148                 }
1149                 goto done;
1150         }
1151
1152         return -EINVAL;
1153
1154 done:
1155         if (intel_dig_port->base.base.crtc)
1156                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1157
1158         return 0;
1159 }
1160
1161 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1162 {
1163         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1164         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1165         struct drm_display_mode *adjusted_mode =
1166                 &intel_crtc->config.adjusted_mode;
1167
1168         intel_hdmi_prepare(encoder);
1169
1170         intel_hdmi->set_infoframes(&encoder->base,
1171                                    intel_crtc->config.has_hdmi_sink,
1172                                    adjusted_mode);
1173 }
1174
1175 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1176 {
1177         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1178         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1179         struct drm_device *dev = encoder->base.dev;
1180         struct drm_i915_private *dev_priv = dev->dev_private;
1181         struct intel_crtc *intel_crtc =
1182                 to_intel_crtc(encoder->base.crtc);
1183         struct drm_display_mode *adjusted_mode =
1184                 &intel_crtc->config.adjusted_mode;
1185         enum dpio_channel port = vlv_dport_to_channel(dport);
1186         int pipe = intel_crtc->pipe;
1187         u32 val;
1188
1189         /* Enable clock channels for this port */
1190         mutex_lock(&dev_priv->dpio_lock);
1191         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1192         val = 0;
1193         if (pipe)
1194                 val |= (1<<21);
1195         else
1196                 val &= ~(1<<21);
1197         val |= 0x001000c4;
1198         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1199
1200         /* HDMI 1.0V-2dB */
1201         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1202         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1203         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1204         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1205         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1206         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1207         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1208         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1209
1210         /* Program lane clock */
1211         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1212         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1213         mutex_unlock(&dev_priv->dpio_lock);
1214
1215         intel_hdmi->set_infoframes(&encoder->base,
1216                                    intel_crtc->config.has_hdmi_sink,
1217                                    adjusted_mode);
1218
1219         intel_enable_hdmi(encoder);
1220
1221         vlv_wait_port_ready(dev_priv, dport);
1222 }
1223
1224 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1225 {
1226         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1227         struct drm_device *dev = encoder->base.dev;
1228         struct drm_i915_private *dev_priv = dev->dev_private;
1229         struct intel_crtc *intel_crtc =
1230                 to_intel_crtc(encoder->base.crtc);
1231         enum dpio_channel port = vlv_dport_to_channel(dport);
1232         int pipe = intel_crtc->pipe;
1233
1234         intel_hdmi_prepare(encoder);
1235
1236         /* Program Tx lane resets to default */
1237         mutex_lock(&dev_priv->dpio_lock);
1238         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1239                          DPIO_PCS_TX_LANE2_RESET |
1240                          DPIO_PCS_TX_LANE1_RESET);
1241         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1242                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1243                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1244                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1245                          DPIO_PCS_CLK_SOFT_RESET);
1246
1247         /* Fix up inter-pair skew failure */
1248         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1249         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1250         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1251
1252         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1253         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1254         mutex_unlock(&dev_priv->dpio_lock);
1255 }
1256
1257 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1258 {
1259         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1260         struct drm_device *dev = encoder->base.dev;
1261         struct drm_i915_private *dev_priv = dev->dev_private;
1262         struct intel_crtc *intel_crtc =
1263                 to_intel_crtc(encoder->base.crtc);
1264         enum dpio_channel ch = vlv_dport_to_channel(dport);
1265         enum pipe pipe = intel_crtc->pipe;
1266         u32 val;
1267
1268         mutex_lock(&dev_priv->dpio_lock);
1269
1270         /* program left/right clock distribution */
1271         if (pipe != PIPE_B) {
1272                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1273                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1274                 if (ch == DPIO_CH0)
1275                         val |= CHV_BUFLEFTENA1_FORCE;
1276                 if (ch == DPIO_CH1)
1277                         val |= CHV_BUFRIGHTENA1_FORCE;
1278                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1279         } else {
1280                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1281                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1282                 if (ch == DPIO_CH0)
1283                         val |= CHV_BUFLEFTENA2_FORCE;
1284                 if (ch == DPIO_CH1)
1285                         val |= CHV_BUFRIGHTENA2_FORCE;
1286                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1287         }
1288
1289         /* program clock channel usage */
1290         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1291         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1292         if (pipe != PIPE_B)
1293                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1294         else
1295                 val |= CHV_PCS_USEDCLKCHANNEL;
1296         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1297
1298         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1299         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1300         if (pipe != PIPE_B)
1301                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1302         else
1303                 val |= CHV_PCS_USEDCLKCHANNEL;
1304         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1305
1306         /*
1307          * This a a bit weird since generally CL
1308          * matches the pipe, but here we need to
1309          * pick the CL based on the port.
1310          */
1311         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1312         if (pipe != PIPE_B)
1313                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1314         else
1315                 val |= CHV_CMN_USEDCLKCHANNEL;
1316         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1317
1318         mutex_unlock(&dev_priv->dpio_lock);
1319 }
1320
1321 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1322 {
1323         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1324         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1325         struct intel_crtc *intel_crtc =
1326                 to_intel_crtc(encoder->base.crtc);
1327         enum dpio_channel port = vlv_dport_to_channel(dport);
1328         int pipe = intel_crtc->pipe;
1329
1330         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1331         mutex_lock(&dev_priv->dpio_lock);
1332         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1333         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1334         mutex_unlock(&dev_priv->dpio_lock);
1335 }
1336
1337 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1338 {
1339         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1340         struct drm_device *dev = encoder->base.dev;
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342         struct intel_crtc *intel_crtc =
1343                 to_intel_crtc(encoder->base.crtc);
1344         enum dpio_channel ch = vlv_dport_to_channel(dport);
1345         enum pipe pipe = intel_crtc->pipe;
1346         u32 val;
1347
1348         mutex_lock(&dev_priv->dpio_lock);
1349
1350         /* Propagate soft reset to data lane reset */
1351         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1352         val |= CHV_PCS_REQ_SOFTRESET_EN;
1353         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1354
1355         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1356         val |= CHV_PCS_REQ_SOFTRESET_EN;
1357         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1358
1359         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1360         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1361         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1362
1363         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1364         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1365         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1366
1367         mutex_unlock(&dev_priv->dpio_lock);
1368 }
1369
1370 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1371 {
1372         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1373         struct drm_device *dev = encoder->base.dev;
1374         struct drm_i915_private *dev_priv = dev->dev_private;
1375         struct intel_crtc *intel_crtc =
1376                 to_intel_crtc(encoder->base.crtc);
1377         enum dpio_channel ch = vlv_dport_to_channel(dport);
1378         int pipe = intel_crtc->pipe;
1379         int data, i;
1380         u32 val;
1381
1382         mutex_lock(&dev_priv->dpio_lock);
1383
1384         /* Deassert soft data lane reset*/
1385         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1386         val |= CHV_PCS_REQ_SOFTRESET_EN;
1387         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1388
1389         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1390         val |= CHV_PCS_REQ_SOFTRESET_EN;
1391         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1392
1393         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1394         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1395         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1396
1397         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1398         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1399         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1400
1401         /* Program Tx latency optimal setting */
1402         for (i = 0; i < 4; i++) {
1403                 /* Set the latency optimal bit */
1404                 data = (i == 1) ? 0x0 : 0x6;
1405                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1406                                 data << DPIO_FRC_LATENCY_SHFIT);
1407
1408                 /* Set the upar bit */
1409                 data = (i == 1) ? 0x0 : 0x1;
1410                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1411                                 data << DPIO_UPAR_SHIFT);
1412         }
1413
1414         /* Data lane stagger programming */
1415         /* FIXME: Fix up value only after power analysis */
1416
1417         /* Clear calc init */
1418         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1419         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1420         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1421
1422         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1423         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1424         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1425
1426         /* FIXME: Program the support xxx V-dB */
1427         /* Use 800mV-0dB */
1428         for (i = 0; i < 4; i++) {
1429                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1430                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1431                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1432                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1433         }
1434
1435         for (i = 0; i < 4; i++) {
1436                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1437                 val &= ~DPIO_SWING_MARGIN_MASK;
1438                 val |= 102 << DPIO_SWING_MARGIN_SHIFT;
1439                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1440         }
1441
1442         /* Disable unique transition scale */
1443         for (i = 0; i < 4; i++) {
1444                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1445                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1446                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1447         }
1448
1449         /* Additional steps for 1200mV-0dB */
1450 #if 0
1451         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1452         if (ch)
1453                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1454         else
1455                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1456         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1457
1458         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1459                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1460                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1461 #endif
1462         /* Start swing calculation */
1463         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1464         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1465         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1466
1467         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1468         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1469         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1470
1471         /* LRC Bypass */
1472         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1473         val |= DPIO_LRC_BYPASS;
1474         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1475
1476         mutex_unlock(&dev_priv->dpio_lock);
1477
1478         intel_enable_hdmi(encoder);
1479
1480         vlv_wait_port_ready(dev_priv, dport);
1481 }
1482
1483 static void intel_hdmi_destroy(struct drm_connector *connector)
1484 {
1485         drm_connector_cleanup(connector);
1486         kfree(connector);
1487 }
1488
1489 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1490         .dpms = intel_connector_dpms,
1491         .detect = intel_hdmi_detect,
1492         .fill_modes = drm_helper_probe_single_connector_modes,
1493         .set_property = intel_hdmi_set_property,
1494         .destroy = intel_hdmi_destroy,
1495 };
1496
1497 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1498         .get_modes = intel_hdmi_get_modes,
1499         .mode_valid = intel_hdmi_mode_valid,
1500         .best_encoder = intel_best_encoder,
1501 };
1502
1503 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1504         .destroy = intel_encoder_destroy,
1505 };
1506
1507 static void
1508 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1509 {
1510         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1511                 drm_object_attach_property(&connector->base,
1512                         connector->dev->mode_config.aspect_ratio_property,
1513                         DRM_MODE_PICTURE_ASPECT_NONE);
1514 }
1515
1516 static void
1517 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1518 {
1519         intel_attach_force_audio_property(connector);
1520         intel_attach_broadcast_rgb_property(connector);
1521         intel_hdmi->color_range_auto = true;
1522         intel_attach_aspect_ratio_property(connector);
1523         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1524 }
1525
1526 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1527                                struct intel_connector *intel_connector)
1528 {
1529         struct drm_connector *connector = &intel_connector->base;
1530         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1531         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1532         struct drm_device *dev = intel_encoder->base.dev;
1533         struct drm_i915_private *dev_priv = dev->dev_private;
1534         enum port port = intel_dig_port->port;
1535
1536         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1537                            DRM_MODE_CONNECTOR_HDMIA);
1538         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1539
1540         connector->interlace_allowed = 1;
1541         connector->doublescan_allowed = 0;
1542         connector->stereo_allowed = 1;
1543
1544         switch (port) {
1545         case PORT_B:
1546                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1547                 intel_encoder->hpd_pin = HPD_PORT_B;
1548                 break;
1549         case PORT_C:
1550                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1551                 intel_encoder->hpd_pin = HPD_PORT_C;
1552                 break;
1553         case PORT_D:
1554                 if (IS_CHERRYVIEW(dev))
1555                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
1556                 else
1557                         intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1558                 intel_encoder->hpd_pin = HPD_PORT_D;
1559                 break;
1560         case PORT_A:
1561                 intel_encoder->hpd_pin = HPD_PORT_A;
1562                 /* Internal port only for eDP. */
1563         default:
1564                 BUG();
1565         }
1566
1567         if (IS_VALLEYVIEW(dev)) {
1568                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1569                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1570         } else if (IS_G4X(dev)) {
1571                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1572                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1573         } else if (HAS_DDI(dev)) {
1574                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1575                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1576         } else if (HAS_PCH_IBX(dev)) {
1577                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1578                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1579         } else {
1580                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1581                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1582         }
1583
1584         if (HAS_DDI(dev))
1585                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1586         else
1587                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1588         intel_connector->unregister = intel_connector_unregister;
1589
1590         intel_hdmi_add_properties(intel_hdmi, connector);
1591
1592         intel_connector_attach_encoder(intel_connector, intel_encoder);
1593         drm_connector_register(connector);
1594
1595         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1596          * 0xd.  Failure to do so will result in spurious interrupts being
1597          * generated on the port when a cable is not attached.
1598          */
1599         if (IS_G4X(dev) && !IS_GM45(dev)) {
1600                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1601                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1602         }
1603 }
1604
1605 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1606 {
1607         struct intel_digital_port *intel_dig_port;
1608         struct intel_encoder *intel_encoder;
1609         struct intel_connector *intel_connector;
1610
1611         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1612         if (!intel_dig_port)
1613                 return;
1614
1615         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1616         if (!intel_connector) {
1617                 kfree(intel_dig_port);
1618                 return;
1619         }
1620
1621         intel_encoder = &intel_dig_port->base;
1622
1623         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1624                          DRM_MODE_ENCODER_TMDS);
1625
1626         intel_encoder->compute_config = intel_hdmi_compute_config;
1627         intel_encoder->disable = intel_disable_hdmi;
1628         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1629         intel_encoder->get_config = intel_hdmi_get_config;
1630         if (IS_CHERRYVIEW(dev)) {
1631                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1632                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
1633                 intel_encoder->enable = vlv_enable_hdmi;
1634                 intel_encoder->post_disable = chv_hdmi_post_disable;
1635         } else if (IS_VALLEYVIEW(dev)) {
1636                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1637                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1638                 intel_encoder->enable = vlv_enable_hdmi;
1639                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1640         } else {
1641                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1642                 intel_encoder->enable = intel_enable_hdmi;
1643         }
1644
1645         intel_encoder->type = INTEL_OUTPUT_HDMI;
1646         if (IS_CHERRYVIEW(dev)) {
1647                 if (port == PORT_D)
1648                         intel_encoder->crtc_mask = 1 << 2;
1649                 else
1650                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1651         } else {
1652                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1653         }
1654         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1655         /*
1656          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
1657          * to work on real hardware. And since g4x can send infoframes to
1658          * only one port anyway, nothing is lost by allowing it.
1659          */
1660         if (IS_G4X(dev))
1661                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1662
1663         intel_dig_port->port = port;
1664         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1665         intel_dig_port->dp.output_reg = 0;
1666
1667         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1668 }