drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void gen9_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaEnableLbsSlaRetryTimerDecrement:skl */
  60         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
  61                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
  62
  63         /* WaDisableKillLogic:bxt,skl */
  64         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  65                    ECOCHK_DIS_TLB);
  66 }
  67
  68 static void skl_init_clock_gating(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         gen9_init_clock_gating(dev);
  73
  74         if (INTEL_REVID(dev) <= SKL_REVID_B0) {
  75                 /*
  76                  * WaDisableSDEUnitClockGating:skl
  77                  * WaSetGAPSunitClckGateDisable:skl
  78                  */
  79                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  80                            GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
  81                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  82
  83                 /* WaDisableVFUnitClockGating:skl */
  84                 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
  85                            GEN6_VFUNIT_CLOCK_GATE_DISABLE);
  86         }
  87
  88         if (INTEL_REVID(dev) <= SKL_REVID_D0) {
  89                 /* WaDisableHDCInvalidation:skl */
  90                 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
  91                            BDW_DISABLE_HDC_INVALIDATION);
  92
  93                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
  94                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
  95                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
  96         }
  97
  98         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
  99          * involving this register should also be added to WA batch as required.
 100          */
 101         if (INTEL_REVID(dev) <= SKL_REVID_E0)
 102                 /* WaDisableLSQCROPERFforOCL:skl */
 103                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
 104                            GEN8_LQSC_RO_PERF_DIS);
 105
 106         /* WaEnableGapsTsvCreditFix:skl */
 107         if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
 108                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 109                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
 110         }
 111 }
 112
 113 static void bxt_init_clock_gating(struct drm_device *dev)
 114 {
 115         struct drm_i915_private *dev_priv = dev->dev_private;
 116
 117         gen9_init_clock_gating(dev);
 118
 119         /* WaDisableSDEUnitClockGating:bxt */
 120         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 121                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 122
 123         /*
 124          * FIXME:
 125          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 126          */
 127         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 128                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 129
 130         if (INTEL_REVID(dev) == BXT_REVID_A0) {
 131                 /*
 132                  * Hardware specification requires this bit to be
 133                  * set to 1 for A0
 134                  */
 135                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 136         }
 137
 138         /* WaSetClckGatingDisableMedia:bxt */
 139         if (INTEL_REVID(dev) == BXT_REVID_A0) {
 140                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
 141                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
 142         }
 143 }
 144
 145 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = dev->dev_private;
 148         u32 tmp;
 149
 150         tmp = I915_READ(CLKCFG);
 151
 152         switch (tmp & CLKCFG_FSB_MASK) {
 153         case CLKCFG_FSB_533:
 154                 dev_priv->fsb_freq = 533; /* 133*4 */
 155                 break;
 156         case CLKCFG_FSB_800:
 157                 dev_priv->fsb_freq = 800; /* 200*4 */
 158                 break;
 159         case CLKCFG_FSB_667:
 160                 dev_priv->fsb_freq =  667; /* 167*4 */
 161                 break;
 162         case CLKCFG_FSB_400:
 163                 dev_priv->fsb_freq = 400; /* 100*4 */
 164                 break;
 165         }
 166
 167         switch (tmp & CLKCFG_MEM_MASK) {
 168         case CLKCFG_MEM_533:
 169                 dev_priv->mem_freq = 533;
 170                 break;
 171         case CLKCFG_MEM_667:
 172                 dev_priv->mem_freq = 667;
 173                 break;
 174         case CLKCFG_MEM_800:
 175                 dev_priv->mem_freq = 800;
 176                 break;
 177         }
 178
 179         /* detect pineview DDR3 setting */
 180         tmp = I915_READ(CSHRDDR3CTL);
 181         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 182 }
 183
 184 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 185 {
 186         struct drm_i915_private *dev_priv = dev->dev_private;
 187         u16 ddrpll, csipll;
 188
 189         ddrpll = I915_READ16(DDRMPLL1);
 190         csipll = I915_READ16(CSIPLL0);
 191
 192         switch (ddrpll & 0xff) {
 193         case 0xc:
 194                 dev_priv->mem_freq = 800;
 195                 break;
 196         case 0x10:
 197                 dev_priv->mem_freq = 1066;
 198                 break;
 199         case 0x14:
 200                 dev_priv->mem_freq = 1333;
 201                 break;
 202         case 0x18:
 203                 dev_priv->mem_freq = 1600;
 204                 break;
 205         default:
 206                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 207                                  ddrpll & 0xff);
 208                 dev_priv->mem_freq = 0;
 209                 break;
 210         }
 211
 212         dev_priv->ips.r_t = dev_priv->mem_freq;
 213
 214         switch (csipll & 0x3ff) {
 215         case 0x00c:
 216                 dev_priv->fsb_freq = 3200;
 217                 break;
 218         case 0x00e:
 219                 dev_priv->fsb_freq = 3733;
 220                 break;
 221         case 0x010:
 222                 dev_priv->fsb_freq = 4266;
 223                 break;
 224         case 0x012:
 225                 dev_priv->fsb_freq = 4800;
 226                 break;
 227         case 0x014:
 228                 dev_priv->fsb_freq = 5333;
 229                 break;
 230         case 0x016:
 231                 dev_priv->fsb_freq = 5866;
 232                 break;
 233         case 0x018:
 234                 dev_priv->fsb_freq = 6400;
 235                 break;
 236         default:
 237                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 238                                  csipll & 0x3ff);
 239                 dev_priv->fsb_freq = 0;
 240                 break;
 241         }
 242
 243         if (dev_priv->fsb_freq == 3200) {
 244                 dev_priv->ips.c_m = 0;
 245         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 246                 dev_priv->ips.c_m = 1;
 247         } else {
 248                 dev_priv->ips.c_m = 2;
 249         }
 250 }
 251
 252 static const struct cxsr_latency cxsr_latency_table[] = {
 253         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 254         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 255         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 256         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 257         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 258
 259         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 260         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 261         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 262         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 263         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 264
 265         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 266         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 267         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 268         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 269         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 270
 271         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 272         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 273         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 274         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 275         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 276
 277         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 278         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 279         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 280         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 281         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 282
 283         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 284         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 285         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 286         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 287         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 288 };
 289
 290 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 291                                                          int is_ddr3,
 292                                                          int fsb,
 293                                                          int mem)
 294 {
 295         const struct cxsr_latency *latency;
 296         int i;
 297
 298         if (fsb == 0 || mem == 0)
 299                 return NULL;
 300
 301         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 302                 latency = &cxsr_latency_table[i];
 303                 if (is_desktop == latency->is_desktop &&
 304                     is_ddr3 == latency->is_ddr3 &&
 305                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 306                         return latency;
 307         }
 308
 309         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 310
 311         return NULL;
 312 }
 313
 314 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 315 {
 316         u32 val;
 317
 318         mutex_lock(&dev_priv->rps.hw_lock);
 319
 320         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 321         if (enable)
 322                 val &= ~FORCE_DDR_HIGH_FREQ;
 323         else
 324                 val |= FORCE_DDR_HIGH_FREQ;
 325         val &= ~FORCE_DDR_LOW_FREQ;
 326         val |= FORCE_DDR_FREQ_REQ_ACK;
 327         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 328
 329         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 330                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 331                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 332
 333         mutex_unlock(&dev_priv->rps.hw_lock);
 334 }
 335
 336 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 337 {
 338         u32 val;
 339
 340         mutex_lock(&dev_priv->rps.hw_lock);
 341
 342         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 343         if (enable)
 344                 val |= DSP_MAXFIFO_PM5_ENABLE;
 345         else
 346                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 347         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 348
 349         mutex_unlock(&dev_priv->rps.hw_lock);
 350 }
 351
 352 #define FW_WM(value, plane) \
 353         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 354
 355 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 356 {
 357         struct drm_device *dev = dev_priv->dev;
 358         u32 val;
 359
 360         if (IS_VALLEYVIEW(dev)) {
 361                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 362                 POSTING_READ(FW_BLC_SELF_VLV);
 363                 dev_priv->wm.vlv.cxsr = enable;
 364         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 365                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 366                 POSTING_READ(FW_BLC_SELF);
 367         } else if (IS_PINEVIEW(dev)) {
 368                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 369                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 370                 I915_WRITE(DSPFW3, val);
 371                 POSTING_READ(DSPFW3);
 372         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 373                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 374                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 375                 I915_WRITE(FW_BLC_SELF, val);
 376                 POSTING_READ(FW_BLC_SELF);
 377         } else if (IS_I915GM(dev)) {
 378                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 379                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 380                 I915_WRITE(INSTPM, val);
 381                 POSTING_READ(INSTPM);
 382         } else {
 383                 return;
 384         }
 385
 386         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 387                       enable ? "enabled" : "disabled");
 388 }
 389
 390
 391 /*
 392  * Latency for FIFO fetches is dependent on several factors:
 393  *   - memory configuration (speed, channels)
 394  *   - chipset
 395  *   - current MCH state
 396  * It can be fairly high in some situations, so here we assume a fairly
 397  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 398  * set this value too high, the FIFO will fetch frequently to stay full)
 399  * and power consumption (set it too low to save power and we might see
 400  * FIFO underruns and display "flicker").
 401  *
 402  * A value of 5us seems to be a good balance; safe for very low end
 403  * platforms but not overly aggressive on lower latency configs.
 404  */
 405 static const int pessimal_latency_ns = 5000;
 406
 407 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 408         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 409
 410 static int vlv_get_fifo_size(struct drm_device *dev,
 411                               enum pipe pipe, int plane)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414         int sprite0_start, sprite1_start, size;
 415
 416         switch (pipe) {
 417                 uint32_t dsparb, dsparb2, dsparb3;
 418         case PIPE_A:
 419                 dsparb = I915_READ(DSPARB);
 420                 dsparb2 = I915_READ(DSPARB2);
 421                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 422                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 423                 break;
 424         case PIPE_B:
 425                 dsparb = I915_READ(DSPARB);
 426                 dsparb2 = I915_READ(DSPARB2);
 427                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 428                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 429                 break;
 430         case PIPE_C:
 431                 dsparb2 = I915_READ(DSPARB2);
 432                 dsparb3 = I915_READ(DSPARB3);
 433                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 434                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 435                 break;
 436         default:
 437                 return 0;
 438         }
 439
 440         switch (plane) {
 441         case 0:
 442                 size = sprite0_start;
 443                 break;
 444         case 1:
 445                 size = sprite1_start - sprite0_start;
 446                 break;
 447         case 2:
 448                 size = 512 - 1 - sprite1_start;
 449                 break;
 450         default:
 451                 return 0;
 452         }
 453
 454         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 455                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 456                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 457                       size);
 458
 459         return size;
 460 }
 461
 462 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 463 {
 464         struct drm_i915_private *dev_priv = dev->dev_private;
 465         uint32_t dsparb = I915_READ(DSPARB);
 466         int size;
 467
 468         size = dsparb & 0x7f;
 469         if (plane)
 470                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 471
 472         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 473                       plane ? "B" : "A", size);
 474
 475         return size;
 476 }
 477
 478 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 479 {
 480         struct drm_i915_private *dev_priv = dev->dev_private;
 481         uint32_t dsparb = I915_READ(DSPARB);
 482         int size;
 483
 484         size = dsparb & 0x1ff;
 485         if (plane)
 486                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 487         size >>= 1; /* Convert to cachelines */
 488
 489         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 490                       plane ? "B" : "A", size);
 491
 492         return size;
 493 }
 494
 495 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 496 {
 497         struct drm_i915_private *dev_priv = dev->dev_private;
 498         uint32_t dsparb = I915_READ(DSPARB);
 499         int size;
 500
 501         size = dsparb & 0x7f;
 502         size >>= 2; /* Convert to cachelines */
 503
 504         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 505                       plane ? "B" : "A",
 506                       size);
 507
 508         return size;
 509 }
 510
 511 /* Pineview has different values for various configs */
 512 static const struct intel_watermark_params pineview_display_wm = {
 513         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 514         .max_wm = PINEVIEW_MAX_WM,
 515         .default_wm = PINEVIEW_DFT_WM,
 516         .guard_size = PINEVIEW_GUARD_WM,
 517         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 518 };
 519 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 520         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 521         .max_wm = PINEVIEW_MAX_WM,
 522         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 523         .guard_size = PINEVIEW_GUARD_WM,
 524         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 525 };
 526 static const struct intel_watermark_params pineview_cursor_wm = {
 527         .fifo_size = PINEVIEW_CURSOR_FIFO,
 528         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 529         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 530         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 531         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 532 };
 533 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 534         .fifo_size = PINEVIEW_CURSOR_FIFO,
 535         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 536         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 537         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 538         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 539 };
 540 static const struct intel_watermark_params g4x_wm_info = {
 541         .fifo_size = G4X_FIFO_SIZE,
 542         .max_wm = G4X_MAX_WM,
 543         .default_wm = G4X_MAX_WM,
 544         .guard_size = 2,
 545         .cacheline_size = G4X_FIFO_LINE_SIZE,
 546 };
 547 static const struct intel_watermark_params g4x_cursor_wm_info = {
 548         .fifo_size = I965_CURSOR_FIFO,
 549         .max_wm = I965_CURSOR_MAX_WM,
 550         .default_wm = I965_CURSOR_DFT_WM,
 551         .guard_size = 2,
 552         .cacheline_size = G4X_FIFO_LINE_SIZE,
 553 };
 554 static const struct intel_watermark_params valleyview_wm_info = {
 555         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 556         .max_wm = VALLEYVIEW_MAX_WM,
 557         .default_wm = VALLEYVIEW_MAX_WM,
 558         .guard_size = 2,
 559         .cacheline_size = G4X_FIFO_LINE_SIZE,
 560 };
 561 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 562         .fifo_size = I965_CURSOR_FIFO,
 563         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 564         .default_wm = I965_CURSOR_DFT_WM,
 565         .guard_size = 2,
 566         .cacheline_size = G4X_FIFO_LINE_SIZE,
 567 };
 568 static const struct intel_watermark_params i965_cursor_wm_info = {
 569         .fifo_size = I965_CURSOR_FIFO,
 570         .max_wm = I965_CURSOR_MAX_WM,
 571         .default_wm = I965_CURSOR_DFT_WM,
 572         .guard_size = 2,
 573         .cacheline_size = I915_FIFO_LINE_SIZE,
 574 };
 575 static const struct intel_watermark_params i945_wm_info = {
 576         .fifo_size = I945_FIFO_SIZE,
 577         .max_wm = I915_MAX_WM,
 578         .default_wm = 1,
 579         .guard_size = 2,
 580         .cacheline_size = I915_FIFO_LINE_SIZE,
 581 };
 582 static const struct intel_watermark_params i915_wm_info = {
 583         .fifo_size = I915_FIFO_SIZE,
 584         .max_wm = I915_MAX_WM,
 585         .default_wm = 1,
 586         .guard_size = 2,
 587         .cacheline_size = I915_FIFO_LINE_SIZE,
 588 };
 589 static const struct intel_watermark_params i830_a_wm_info = {
 590         .fifo_size = I855GM_FIFO_SIZE,
 591         .max_wm = I915_MAX_WM,
 592         .default_wm = 1,
 593         .guard_size = 2,
 594         .cacheline_size = I830_FIFO_LINE_SIZE,
 595 };
 596 static const struct intel_watermark_params i830_bc_wm_info = {
 597         .fifo_size = I855GM_FIFO_SIZE,
 598         .max_wm = I915_MAX_WM/2,
 599         .default_wm = 1,
 600         .guard_size = 2,
 601         .cacheline_size = I830_FIFO_LINE_SIZE,
 602 };
 603 static const struct intel_watermark_params i845_wm_info = {
 604         .fifo_size = I830_FIFO_SIZE,
 605         .max_wm = I915_MAX_WM,
 606         .default_wm = 1,
 607         .guard_size = 2,
 608         .cacheline_size = I830_FIFO_LINE_SIZE,
 609 };
 610
 611 /**
 612  * intel_calculate_wm - calculate watermark level
 613  * @clock_in_khz: pixel clock
 614  * @wm: chip FIFO params
 615  * @pixel_size: display pixel size
 616  * @latency_ns: memory latency for the platform
 617  *
 618  * Calculate the watermark level (the level at which the display plane will
 619  * start fetching from memory again).  Each chip has a different display
 620  * FIFO size and allocation, so the caller needs to figure that out and pass
 621  * in the correct intel_watermark_params structure.
 622  *
 623  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 624  * on the pixel size.  When it reaches the watermark level, it'll start
 625  * fetching FIFO line sized based chunks from memory until the FIFO fills
 626  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 627  * will occur, and a display engine hang could result.
 628  */
 629 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 630                                         const struct intel_watermark_params *wm,
 631                                         int fifo_size,
 632                                         int pixel_size,
 633                                         unsigned long latency_ns)
 634 {
 635         long entries_required, wm_size;
 636
 637         /*
 638          * Note: we need to make sure we don't overflow for various clock &
 639          * latency values.
 640          * clocks go from a few thousand to several hundred thousand.
 641          * latency is usually a few thousand
 642          */
 643         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 644                 1000;
 645         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 646
 647         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 648
 649         wm_size = fifo_size - (entries_required + wm->guard_size);
 650
 651         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 652
 653         /* Don't promote wm_size to unsigned... */
 654         if (wm_size > (long)wm->max_wm)
 655                 wm_size = wm->max_wm;
 656         if (wm_size <= 0)
 657                 wm_size = wm->default_wm;
 658
 659         /*
 660          * Bspec seems to indicate that the value shouldn't be lower than
 661          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 662          * Lets go for 8 which is the burst size since certain platforms
 663          * already use a hardcoded 8 (which is what the spec says should be
 664          * done).
 665          */
 666         if (wm_size <= 8)
 667                 wm_size = 8;
 668
 669         return wm_size;
 670 }
 671
 672 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 673 {
 674         struct drm_crtc *crtc, *enabled = NULL;
 675
 676         for_each_crtc(dev, crtc) {
 677                 if (intel_crtc_active(crtc)) {
 678                         if (enabled)
 679                                 return NULL;
 680                         enabled = crtc;
 681                 }
 682         }
 683
 684         return enabled;
 685 }
 686
 687 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 688 {
 689         struct drm_device *dev = unused_crtc->dev;
 690         struct drm_i915_private *dev_priv = dev->dev_private;
 691         struct drm_crtc *crtc;
 692         const struct cxsr_latency *latency;
 693         u32 reg;
 694         unsigned long wm;
 695
 696         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 697                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 698         if (!latency) {
 699                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 700                 intel_set_memory_cxsr(dev_priv, false);
 701                 return;
 702         }
 703
 704         crtc = single_enabled_crtc(dev);
 705         if (crtc) {
 706                 const struct drm_display_mode *adjusted_mode;
 707                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 708                 int clock;
 709
 710                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 711                 clock = adjusted_mode->crtc_clock;
 712
 713                 /* Display SR */
 714                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 715                                         pineview_display_wm.fifo_size,
 716                                         pixel_size, latency->display_sr);
 717                 reg = I915_READ(DSPFW1);
 718                 reg &= ~DSPFW_SR_MASK;
 719                 reg |= FW_WM(wm, SR);
 720                 I915_WRITE(DSPFW1, reg);
 721                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 722
 723                 /* cursor SR */
 724                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 725                                         pineview_display_wm.fifo_size,
 726                                         pixel_size, latency->cursor_sr);
 727                 reg = I915_READ(DSPFW3);
 728                 reg &= ~DSPFW_CURSOR_SR_MASK;
 729                 reg |= FW_WM(wm, CURSOR_SR);
 730                 I915_WRITE(DSPFW3, reg);
 731
 732                 /* Display HPLL off SR */
 733                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 734                                         pineview_display_hplloff_wm.fifo_size,
 735                                         pixel_size, latency->display_hpll_disable);
 736                 reg = I915_READ(DSPFW3);
 737                 reg &= ~DSPFW_HPLL_SR_MASK;
 738                 reg |= FW_WM(wm, HPLL_SR);
 739                 I915_WRITE(DSPFW3, reg);
 740
 741                 /* cursor HPLL off SR */
 742                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 743                                         pineview_display_hplloff_wm.fifo_size,
 744                                         pixel_size, latency->cursor_hpll_disable);
 745                 reg = I915_READ(DSPFW3);
 746                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 747                 reg |= FW_WM(wm, HPLL_CURSOR);
 748                 I915_WRITE(DSPFW3, reg);
 749                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 750
 751                 intel_set_memory_cxsr(dev_priv, true);
 752         } else {
 753                 intel_set_memory_cxsr(dev_priv, false);
 754         }
 755 }
 756
 757 static bool g4x_compute_wm0(struct drm_device *dev,
 758                             int plane,
 759                             const struct intel_watermark_params *display,
 760                             int display_latency_ns,
 761                             const struct intel_watermark_params *cursor,
 762                             int cursor_latency_ns,
 763                             int *plane_wm,
 764                             int *cursor_wm)
 765 {
 766         struct drm_crtc *crtc;
 767         const struct drm_display_mode *adjusted_mode;
 768         int htotal, hdisplay, clock, pixel_size;
 769         int line_time_us, line_count;
 770         int entries, tlb_miss;
 771
 772         crtc = intel_get_crtc_for_plane(dev, plane);
 773         if (!intel_crtc_active(crtc)) {
 774                 *cursor_wm = cursor->guard_size;
 775                 *plane_wm = display->guard_size;
 776                 return false;
 777         }
 778
 779         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 780         clock = adjusted_mode->crtc_clock;
 781         htotal = adjusted_mode->crtc_htotal;
 782         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 783         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 784
 785         /* Use the small buffer method to calculate plane watermark */
 786         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 787         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 788         if (tlb_miss > 0)
 789                 entries += tlb_miss;
 790         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 791         *plane_wm = entries + display->guard_size;
 792         if (*plane_wm > (int)display->max_wm)
 793                 *plane_wm = display->max_wm;
 794
 795         /* Use the large buffer method to calculate cursor watermark */
 796         line_time_us = max(htotal * 1000 / clock, 1);
 797         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 798         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 799         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 800         if (tlb_miss > 0)
 801                 entries += tlb_miss;
 802         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 803         *cursor_wm = entries + cursor->guard_size;
 804         if (*cursor_wm > (int)cursor->max_wm)
 805                 *cursor_wm = (int)cursor->max_wm;
 806
 807         return true;
 808 }
 809
 810 /*
 811  * Check the wm result.
 812  *
 813  * If any calculated watermark values is larger than the maximum value that
 814  * can be programmed into the associated watermark register, that watermark
 815  * must be disabled.
 816  */
 817 static bool g4x_check_srwm(struct drm_device *dev,
 818                            int display_wm, int cursor_wm,
 819                            const struct intel_watermark_params *display,
 820                            const struct intel_watermark_params *cursor)
 821 {
 822         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 823                       display_wm, cursor_wm);
 824
 825         if (display_wm > display->max_wm) {
 826                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 827                               display_wm, display->max_wm);
 828                 return false;
 829         }
 830
 831         if (cursor_wm > cursor->max_wm) {
 832                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 833                               cursor_wm, cursor->max_wm);
 834                 return false;
 835         }
 836
 837         if (!(display_wm || cursor_wm)) {
 838                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 839                 return false;
 840         }
 841
 842         return true;
 843 }
 844
 845 static bool g4x_compute_srwm(struct drm_device *dev,
 846                              int plane,
 847                              int latency_ns,
 848                              const struct intel_watermark_params *display,
 849                              const struct intel_watermark_params *cursor,
 850                              int *display_wm, int *cursor_wm)
 851 {
 852         struct drm_crtc *crtc;
 853         const struct drm_display_mode *adjusted_mode;
 854         int hdisplay, htotal, pixel_size, clock;
 855         unsigned long line_time_us;
 856         int line_count, line_size;
 857         int small, large;
 858         int entries;
 859
 860         if (!latency_ns) {
 861                 *display_wm = *cursor_wm = 0;
 862                 return false;
 863         }
 864
 865         crtc = intel_get_crtc_for_plane(dev, plane);
 866         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 867         clock = adjusted_mode->crtc_clock;
 868         htotal = adjusted_mode->crtc_htotal;
 869         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 870         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 871
 872         line_time_us = max(htotal * 1000 / clock, 1);
 873         line_count = (latency_ns / line_time_us + 1000) / 1000;
 874         line_size = hdisplay * pixel_size;
 875
 876         /* Use the minimum of the small and large buffer method for primary */
 877         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 878         large = line_count * line_size;
 879
 880         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 881         *display_wm = entries + display->guard_size;
 882
 883         /* calculate the self-refresh watermark for display cursor */
 884         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 885         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 886         *cursor_wm = entries + cursor->guard_size;
 887
 888         return g4x_check_srwm(dev,
 889                               *display_wm, *cursor_wm,
 890                               display, cursor);
 891 }
 892
 893 #define FW_WM_VLV(value, plane) \
 894         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 895
 896 static void vlv_write_wm_values(struct intel_crtc *crtc,
 897                                 const struct vlv_wm_values *wm)
 898 {
 899         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 900         enum pipe pipe = crtc->pipe;
 901
 902         I915_WRITE(VLV_DDL(pipe),
 903                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 904                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 905                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 906                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 907
 908         I915_WRITE(DSPFW1,
 909                    FW_WM(wm->sr.plane, SR) |
 910                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 911                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 912                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 913         I915_WRITE(DSPFW2,
 914                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 915                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 916                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 917         I915_WRITE(DSPFW3,
 918                    FW_WM(wm->sr.cursor, CURSOR_SR));
 919
 920         if (IS_CHERRYVIEW(dev_priv)) {
 921                 I915_WRITE(DSPFW7_CHV,
 922                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 923                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 924                 I915_WRITE(DSPFW8_CHV,
 925                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 926                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 927                 I915_WRITE(DSPFW9_CHV,
 928                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 929                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 930                 I915_WRITE(DSPHOWM,
 931                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 932                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 933                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 934                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 935                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 936                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 937                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 938                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 939                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 940                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 941         } else {
 942                 I915_WRITE(DSPFW7,
 943                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 944                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 945                 I915_WRITE(DSPHOWM,
 946                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 947                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 948                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 949                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 950                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 951                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 952                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 953         }
 954
 955         /* zero (unused) WM1 watermarks */
 956         I915_WRITE(DSPFW4, 0);
 957         I915_WRITE(DSPFW5, 0);
 958         I915_WRITE(DSPFW6, 0);
 959         I915_WRITE(DSPHOWM1, 0);
 960
 961         POSTING_READ(DSPFW1);
 962 }
 963
 964 #undef FW_WM_VLV
 965
 966 enum vlv_wm_level {
 967         VLV_WM_LEVEL_PM2,
 968         VLV_WM_LEVEL_PM5,
 969         VLV_WM_LEVEL_DDR_DVFS,
 970 };
 971
 972 /* latency must be in 0.1us units. */
 973 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 974                                    unsigned int pipe_htotal,
 975                                    unsigned int horiz_pixels,
 976                                    unsigned int bytes_per_pixel,
 977                                    unsigned int latency)
 978 {
 979         unsigned int ret;
 980
 981         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 982         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 983         ret = DIV_ROUND_UP(ret, 64);
 984
 985         return ret;
 986 }
 987
 988 static void vlv_setup_wm_latency(struct drm_device *dev)
 989 {
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991
 992         /* all latencies in usec */
 993         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 994
 995         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 996
 997         if (IS_CHERRYVIEW(dev_priv)) {
 998                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 999                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1000
1001                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1002         }
1003 }
1004
1005 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
1006                                      struct intel_crtc *crtc,
1007                                      const struct intel_plane_state *state,
1008                                      int level)
1009 {
1010         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1011         int clock, htotal, pixel_size, width, wm;
1012
1013         if (dev_priv->wm.pri_latency[level] == 0)
1014                 return USHRT_MAX;
1015
1016         if (!state->visible)
1017                 return 0;
1018
1019         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1020         clock = crtc->config->base.adjusted_mode.crtc_clock;
1021         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1022         width = crtc->config->pipe_src_w;
1023         if (WARN_ON(htotal == 0))
1024                 htotal = 1;
1025
1026         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1027                 /*
1028                  * FIXME the formula gives values that are
1029                  * too big for the cursor FIFO, and hence we
1030                  * would never be able to use cursors. For
1031                  * now just hardcode the watermark.
1032                  */
1033                 wm = 63;
1034         } else {
1035                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1036                                     dev_priv->wm.pri_latency[level] * 10);
1037         }
1038
1039         return min_t(int, wm, USHRT_MAX);
1040 }
1041
1042 static void vlv_compute_fifo(struct intel_crtc *crtc)
1043 {
1044         struct drm_device *dev = crtc->base.dev;
1045         struct vlv_wm_state *wm_state = &crtc->wm_state;
1046         struct intel_plane *plane;
1047         unsigned int total_rate = 0;
1048         const int fifo_size = 512 - 1;
1049         int fifo_extra, fifo_left = fifo_size;
1050
1051         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1052                 struct intel_plane_state *state =
1053                         to_intel_plane_state(plane->base.state);
1054
1055                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1056                         continue;
1057
1058                 if (state->visible) {
1059                         wm_state->num_active_planes++;
1060                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1061                 }
1062         }
1063
1064         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1065                 struct intel_plane_state *state =
1066                         to_intel_plane_state(plane->base.state);
1067                 unsigned int rate;
1068
1069                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1070                         plane->wm.fifo_size = 63;
1071                         continue;
1072                 }
1073
1074                 if (!state->visible) {
1075                         plane->wm.fifo_size = 0;
1076                         continue;
1077                 }
1078
1079                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1080                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1081                 fifo_left -= plane->wm.fifo_size;
1082         }
1083
1084         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1085
1086         /* spread the remainder evenly */
1087         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1088                 int plane_extra;
1089
1090                 if (fifo_left == 0)
1091                         break;
1092
1093                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1094                         continue;
1095
1096                 /* give it all to the first plane if none are active */
1097                 if (plane->wm.fifo_size == 0 &&
1098                     wm_state->num_active_planes)
1099                         continue;
1100
1101                 plane_extra = min(fifo_extra, fifo_left);
1102                 plane->wm.fifo_size += plane_extra;
1103                 fifo_left -= plane_extra;
1104         }
1105
1106         WARN_ON(fifo_left != 0);
1107 }
1108
1109 static void vlv_invert_wms(struct intel_crtc *crtc)
1110 {
1111         struct vlv_wm_state *wm_state = &crtc->wm_state;
1112         int level;
1113
1114         for (level = 0; level < wm_state->num_levels; level++) {
1115                 struct drm_device *dev = crtc->base.dev;
1116                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1117                 struct intel_plane *plane;
1118
1119                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1120                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1121
1122                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123                         switch (plane->base.type) {
1124                                 int sprite;
1125                         case DRM_PLANE_TYPE_CURSOR:
1126                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1127                                         wm_state->wm[level].cursor;
1128                                 break;
1129                         case DRM_PLANE_TYPE_PRIMARY:
1130                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1131                                         wm_state->wm[level].primary;
1132                                 break;
1133                         case DRM_PLANE_TYPE_OVERLAY:
1134                                 sprite = plane->plane;
1135                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1136                                         wm_state->wm[level].sprite[sprite];
1137                                 break;
1138                         }
1139                 }
1140         }
1141 }
1142
1143 static void vlv_compute_wm(struct intel_crtc *crtc)
1144 {
1145         struct drm_device *dev = crtc->base.dev;
1146         struct vlv_wm_state *wm_state = &crtc->wm_state;
1147         struct intel_plane *plane;
1148         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1149         int level;
1150
1151         memset(wm_state, 0, sizeof(*wm_state));
1152
1153         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1154         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1155
1156         wm_state->num_active_planes = 0;
1157
1158         vlv_compute_fifo(crtc);
1159
1160         if (wm_state->num_active_planes != 1)
1161                 wm_state->cxsr = false;
1162
1163         if (wm_state->cxsr) {
1164                 for (level = 0; level < wm_state->num_levels; level++) {
1165                         wm_state->sr[level].plane = sr_fifo_size;
1166                         wm_state->sr[level].cursor = 63;
1167                 }
1168         }
1169
1170         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171                 struct intel_plane_state *state =
1172                         to_intel_plane_state(plane->base.state);
1173
1174                 if (!state->visible)
1175                         continue;
1176
1177                 /* normal watermarks */
1178                 for (level = 0; level < wm_state->num_levels; level++) {
1179                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1180                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1181
1182                         /* hack */
1183                         if (WARN_ON(level == 0 && wm > max_wm))
1184                                 wm = max_wm;
1185
1186                         if (wm > plane->wm.fifo_size)
1187                                 break;
1188
1189                         switch (plane->base.type) {
1190                                 int sprite;
1191                         case DRM_PLANE_TYPE_CURSOR:
1192                                 wm_state->wm[level].cursor = wm;
1193                                 break;
1194                         case DRM_PLANE_TYPE_PRIMARY:
1195                                 wm_state->wm[level].primary = wm;
1196                                 break;
1197                         case DRM_PLANE_TYPE_OVERLAY:
1198                                 sprite = plane->plane;
1199                                 wm_state->wm[level].sprite[sprite] = wm;
1200                                 break;
1201                         }
1202                 }
1203
1204                 wm_state->num_levels = level;
1205
1206                 if (!wm_state->cxsr)
1207                         continue;
1208
1209                 /* maxfifo watermarks */
1210                 switch (plane->base.type) {
1211                         int sprite, level;
1212                 case DRM_PLANE_TYPE_CURSOR:
1213                         for (level = 0; level < wm_state->num_levels; level++)
1214                                 wm_state->sr[level].cursor =
1215                                         wm_state->sr[level].cursor;
1216                         break;
1217                 case DRM_PLANE_TYPE_PRIMARY:
1218                         for (level = 0; level < wm_state->num_levels; level++)
1219                                 wm_state->sr[level].plane =
1220                                         min(wm_state->sr[level].plane,
1221                                             wm_state->wm[level].primary);
1222                         break;
1223                 case DRM_PLANE_TYPE_OVERLAY:
1224                         sprite = plane->plane;
1225                         for (level = 0; level < wm_state->num_levels; level++)
1226                                 wm_state->sr[level].plane =
1227                                         min(wm_state->sr[level].plane,
1228                                             wm_state->wm[level].sprite[sprite]);
1229                         break;
1230                 }
1231         }
1232
1233         /* clear any (partially) filled invalid levels */
1234         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1235                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1236                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1237         }
1238
1239         vlv_invert_wms(crtc);
1240 }
1241
1242 #define VLV_FIFO(plane, value) \
1243         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1244
1245 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1246 {
1247         struct drm_device *dev = crtc->base.dev;
1248         struct drm_i915_private *dev_priv = to_i915(dev);
1249         struct intel_plane *plane;
1250         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1251
1252         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1253                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1254                         WARN_ON(plane->wm.fifo_size != 63);
1255                         continue;
1256                 }
1257
1258                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1259                         sprite0_start = plane->wm.fifo_size;
1260                 else if (plane->plane == 0)
1261                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1262                 else
1263                         fifo_size = sprite1_start + plane->wm.fifo_size;
1264         }
1265
1266         WARN_ON(fifo_size != 512 - 1);
1267
1268         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1269                       pipe_name(crtc->pipe), sprite0_start,
1270                       sprite1_start, fifo_size);
1271
1272         switch (crtc->pipe) {
1273                 uint32_t dsparb, dsparb2, dsparb3;
1274         case PIPE_A:
1275                 dsparb = I915_READ(DSPARB);
1276                 dsparb2 = I915_READ(DSPARB2);
1277
1278                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1279                             VLV_FIFO(SPRITEB, 0xff));
1280                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1281                            VLV_FIFO(SPRITEB, sprite1_start));
1282
1283                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1284                              VLV_FIFO(SPRITEB_HI, 0x1));
1285                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1286                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1287
1288                 I915_WRITE(DSPARB, dsparb);
1289                 I915_WRITE(DSPARB2, dsparb2);
1290                 break;
1291         case PIPE_B:
1292                 dsparb = I915_READ(DSPARB);
1293                 dsparb2 = I915_READ(DSPARB2);
1294
1295                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1296                             VLV_FIFO(SPRITED, 0xff));
1297                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1298                            VLV_FIFO(SPRITED, sprite1_start));
1299
1300                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1301                              VLV_FIFO(SPRITED_HI, 0xff));
1302                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1303                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1304
1305                 I915_WRITE(DSPARB, dsparb);
1306                 I915_WRITE(DSPARB2, dsparb2);
1307                 break;
1308         case PIPE_C:
1309                 dsparb3 = I915_READ(DSPARB3);
1310                 dsparb2 = I915_READ(DSPARB2);
1311
1312                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1313                              VLV_FIFO(SPRITEF, 0xff));
1314                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1315                             VLV_FIFO(SPRITEF, sprite1_start));
1316
1317                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1318                              VLV_FIFO(SPRITEF_HI, 0xff));
1319                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1320                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1321
1322                 I915_WRITE(DSPARB3, dsparb3);
1323                 I915_WRITE(DSPARB2, dsparb2);
1324                 break;
1325         default:
1326                 break;
1327         }
1328 }
1329
1330 #undef VLV_FIFO
1331
1332 static void vlv_merge_wm(struct drm_device *dev,
1333                          struct vlv_wm_values *wm)
1334 {
1335         struct intel_crtc *crtc;
1336         int num_active_crtcs = 0;
1337
1338         wm->level = to_i915(dev)->wm.max_level;
1339         wm->cxsr = true;
1340
1341         for_each_intel_crtc(dev, crtc) {
1342                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1343
1344                 if (!crtc->active)
1345                         continue;
1346
1347                 if (!wm_state->cxsr)
1348                         wm->cxsr = false;
1349
1350                 num_active_crtcs++;
1351                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1352         }
1353
1354         if (num_active_crtcs != 1)
1355                 wm->cxsr = false;
1356
1357         if (num_active_crtcs > 1)
1358                 wm->level = VLV_WM_LEVEL_PM2;
1359
1360         for_each_intel_crtc(dev, crtc) {
1361                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1362                 enum pipe pipe = crtc->pipe;
1363
1364                 if (!crtc->active)
1365                         continue;
1366
1367                 wm->pipe[pipe] = wm_state->wm[wm->level];
1368                 if (wm->cxsr)
1369                         wm->sr = wm_state->sr[wm->level];
1370
1371                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1372                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1373                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1374                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1375         }
1376 }
1377
1378 static void vlv_update_wm(struct drm_crtc *crtc)
1379 {
1380         struct drm_device *dev = crtc->dev;
1381         struct drm_i915_private *dev_priv = dev->dev_private;
1382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1383         enum pipe pipe = intel_crtc->pipe;
1384         struct vlv_wm_values wm = {};
1385
1386         vlv_compute_wm(intel_crtc);
1387         vlv_merge_wm(dev, &wm);
1388
1389         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1390                 /* FIXME should be part of crtc atomic commit */
1391                 vlv_pipe_set_fifo_size(intel_crtc);
1392                 return;
1393         }
1394
1395         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1396             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1397                 chv_set_memory_dvfs(dev_priv, false);
1398
1399         if (wm.level < VLV_WM_LEVEL_PM5 &&
1400             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1401                 chv_set_memory_pm5(dev_priv, false);
1402
1403         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1404                 intel_set_memory_cxsr(dev_priv, false);
1405
1406         /* FIXME should be part of crtc atomic commit */
1407         vlv_pipe_set_fifo_size(intel_crtc);
1408
1409         vlv_write_wm_values(intel_crtc, &wm);
1410
1411         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1412                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1413                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1414                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1415                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1416
1417         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1418                 intel_set_memory_cxsr(dev_priv, true);
1419
1420         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1421             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1422                 chv_set_memory_pm5(dev_priv, true);
1423
1424         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1425             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1426                 chv_set_memory_dvfs(dev_priv, true);
1427
1428         dev_priv->wm.vlv = wm;
1429 }
1430
1431 #define single_plane_enabled(mask) is_power_of_2(mask)
1432
1433 static void g4x_update_wm(struct drm_crtc *crtc)
1434 {
1435         struct drm_device *dev = crtc->dev;
1436         static const int sr_latency_ns = 12000;
1437         struct drm_i915_private *dev_priv = dev->dev_private;
1438         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1439         int plane_sr, cursor_sr;
1440         unsigned int enabled = 0;
1441         bool cxsr_enabled;
1442
1443         if (g4x_compute_wm0(dev, PIPE_A,
1444                             &g4x_wm_info, pessimal_latency_ns,
1445                             &g4x_cursor_wm_info, pessimal_latency_ns,
1446                             &planea_wm, &cursora_wm))
1447                 enabled |= 1 << PIPE_A;
1448
1449         if (g4x_compute_wm0(dev, PIPE_B,
1450                             &g4x_wm_info, pessimal_latency_ns,
1451                             &g4x_cursor_wm_info, pessimal_latency_ns,
1452                             &planeb_wm, &cursorb_wm))
1453                 enabled |= 1 << PIPE_B;
1454
1455         if (single_plane_enabled(enabled) &&
1456             g4x_compute_srwm(dev, ffs(enabled) - 1,
1457                              sr_latency_ns,
1458                              &g4x_wm_info,
1459                              &g4x_cursor_wm_info,
1460                              &plane_sr, &cursor_sr)) {
1461                 cxsr_enabled = true;
1462         } else {
1463                 cxsr_enabled = false;
1464                 intel_set_memory_cxsr(dev_priv, false);
1465                 plane_sr = cursor_sr = 0;
1466         }
1467
1468         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1469                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1470                       planea_wm, cursora_wm,
1471                       planeb_wm, cursorb_wm,
1472                       plane_sr, cursor_sr);
1473
1474         I915_WRITE(DSPFW1,
1475                    FW_WM(plane_sr, SR) |
1476                    FW_WM(cursorb_wm, CURSORB) |
1477                    FW_WM(planeb_wm, PLANEB) |
1478                    FW_WM(planea_wm, PLANEA));
1479         I915_WRITE(DSPFW2,
1480                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1481                    FW_WM(cursora_wm, CURSORA));
1482         /* HPLL off in SR has some issues on G4x... disable it */
1483         I915_WRITE(DSPFW3,
1484                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1485                    FW_WM(cursor_sr, CURSOR_SR));
1486
1487         if (cxsr_enabled)
1488                 intel_set_memory_cxsr(dev_priv, true);
1489 }
1490
1491 static void i965_update_wm(struct drm_crtc *unused_crtc)
1492 {
1493         struct drm_device *dev = unused_crtc->dev;
1494         struct drm_i915_private *dev_priv = dev->dev_private;
1495         struct drm_crtc *crtc;
1496         int srwm = 1;
1497         int cursor_sr = 16;
1498         bool cxsr_enabled;
1499
1500         /* Calc sr entries for one plane configs */
1501         crtc = single_enabled_crtc(dev);
1502         if (crtc) {
1503                 /* self-refresh has much higher latency */
1504                 static const int sr_latency_ns = 12000;
1505                 const struct drm_display_mode *adjusted_mode =
1506                         &to_intel_crtc(crtc)->config->base.adjusted_mode;
1507                 int clock = adjusted_mode->crtc_clock;
1508                 int htotal = adjusted_mode->crtc_htotal;
1509                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1510                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1511                 unsigned long line_time_us;
1512                 int entries;
1513
1514                 line_time_us = max(htotal * 1000 / clock, 1);
1515
1516                 /* Use ns/us then divide to preserve precision */
1517                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1518                         pixel_size * hdisplay;
1519                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1520                 srwm = I965_FIFO_SIZE - entries;
1521                 if (srwm < 0)
1522                         srwm = 1;
1523                 srwm &= 0x1ff;
1524                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1525                               entries, srwm);
1526
1527                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1528                         pixel_size * crtc->cursor->state->crtc_w;
1529                 entries = DIV_ROUND_UP(entries,
1530                                           i965_cursor_wm_info.cacheline_size);
1531                 cursor_sr = i965_cursor_wm_info.fifo_size -
1532                         (entries + i965_cursor_wm_info.guard_size);
1533
1534                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1535                         cursor_sr = i965_cursor_wm_info.max_wm;
1536
1537                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1538                               "cursor %d\n", srwm, cursor_sr);
1539
1540                 cxsr_enabled = true;
1541         } else {
1542                 cxsr_enabled = false;
1543                 /* Turn off self refresh if both pipes are enabled */
1544                 intel_set_memory_cxsr(dev_priv, false);
1545         }
1546
1547         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1548                       srwm);
1549
1550         /* 965 has limitations... */
1551         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1552                    FW_WM(8, CURSORB) |
1553                    FW_WM(8, PLANEB) |
1554                    FW_WM(8, PLANEA));
1555         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1556                    FW_WM(8, PLANEC_OLD));
1557         /* update cursor SR watermark */
1558         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1559
1560         if (cxsr_enabled)
1561                 intel_set_memory_cxsr(dev_priv, true);
1562 }
1563
1564 #undef FW_WM
1565
1566 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1567 {
1568         struct drm_device *dev = unused_crtc->dev;
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570         const struct intel_watermark_params *wm_info;
1571         uint32_t fwater_lo;
1572         uint32_t fwater_hi;
1573         int cwm, srwm = 1;
1574         int fifo_size;
1575         int planea_wm, planeb_wm;
1576         struct drm_crtc *crtc, *enabled = NULL;
1577
1578         if (IS_I945GM(dev))
1579                 wm_info = &i945_wm_info;
1580         else if (!IS_GEN2(dev))
1581                 wm_info = &i915_wm_info;
1582         else
1583                 wm_info = &i830_a_wm_info;
1584
1585         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1586         crtc = intel_get_crtc_for_plane(dev, 0);
1587         if (intel_crtc_active(crtc)) {
1588                 const struct drm_display_mode *adjusted_mode;
1589                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1590                 if (IS_GEN2(dev))
1591                         cpp = 4;
1592
1593                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1594                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1595                                                wm_info, fifo_size, cpp,
1596                                                pessimal_latency_ns);
1597                 enabled = crtc;
1598         } else {
1599                 planea_wm = fifo_size - wm_info->guard_size;
1600                 if (planea_wm > (long)wm_info->max_wm)
1601                         planea_wm = wm_info->max_wm;
1602         }
1603
1604         if (IS_GEN2(dev))
1605                 wm_info = &i830_bc_wm_info;
1606
1607         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1608         crtc = intel_get_crtc_for_plane(dev, 1);
1609         if (intel_crtc_active(crtc)) {
1610                 const struct drm_display_mode *adjusted_mode;
1611                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1612                 if (IS_GEN2(dev))
1613                         cpp = 4;
1614
1615                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1616                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1617                                                wm_info, fifo_size, cpp,
1618                                                pessimal_latency_ns);
1619                 if (enabled == NULL)
1620                         enabled = crtc;
1621                 else
1622                         enabled = NULL;
1623         } else {
1624                 planeb_wm = fifo_size - wm_info->guard_size;
1625                 if (planeb_wm > (long)wm_info->max_wm)
1626                         planeb_wm = wm_info->max_wm;
1627         }
1628
1629         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1630
1631         if (IS_I915GM(dev) && enabled) {
1632                 struct drm_i915_gem_object *obj;
1633
1634                 obj = intel_fb_obj(enabled->primary->state->fb);
1635
1636                 /* self-refresh seems busted with untiled */
1637                 if (obj->tiling_mode == I915_TILING_NONE)
1638                         enabled = NULL;
1639         }
1640
1641         /*
1642          * Overlay gets an aggressive default since video jitter is bad.
1643          */
1644         cwm = 2;
1645
1646         /* Play safe and disable self-refresh before adjusting watermarks. */
1647         intel_set_memory_cxsr(dev_priv, false);
1648
1649         /* Calc sr entries for one plane configs */
1650         if (HAS_FW_BLC(dev) && enabled) {
1651                 /* self-refresh has much higher latency */
1652                 static const int sr_latency_ns = 6000;
1653                 const struct drm_display_mode *adjusted_mode =
1654                         &to_intel_crtc(enabled)->config->base.adjusted_mode;
1655                 int clock = adjusted_mode->crtc_clock;
1656                 int htotal = adjusted_mode->crtc_htotal;
1657                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1658                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1659                 unsigned long line_time_us;
1660                 int entries;
1661
1662                 line_time_us = max(htotal * 1000 / clock, 1);
1663
1664                 /* Use ns/us then divide to preserve precision */
1665                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1666                         pixel_size * hdisplay;
1667                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1668                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1669                 srwm = wm_info->fifo_size - entries;
1670                 if (srwm < 0)
1671                         srwm = 1;
1672
1673                 if (IS_I945G(dev) || IS_I945GM(dev))
1674                         I915_WRITE(FW_BLC_SELF,
1675                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1676                 else if (IS_I915GM(dev))
1677                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1678         }
1679
1680         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1681                       planea_wm, planeb_wm, cwm, srwm);
1682
1683         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1684         fwater_hi = (cwm & 0x1f);
1685
1686         /* Set request length to 8 cachelines per fetch */
1687         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1688         fwater_hi = fwater_hi | (1 << 8);
1689
1690         I915_WRITE(FW_BLC, fwater_lo);
1691         I915_WRITE(FW_BLC2, fwater_hi);
1692
1693         if (enabled)
1694                 intel_set_memory_cxsr(dev_priv, true);
1695 }
1696
1697 static void i845_update_wm(struct drm_crtc *unused_crtc)
1698 {
1699         struct drm_device *dev = unused_crtc->dev;
1700         struct drm_i915_private *dev_priv = dev->dev_private;
1701         struct drm_crtc *crtc;
1702         const struct drm_display_mode *adjusted_mode;
1703         uint32_t fwater_lo;
1704         int planea_wm;
1705
1706         crtc = single_enabled_crtc(dev);
1707         if (crtc == NULL)
1708                 return;
1709
1710         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1711         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1712                                        &i845_wm_info,
1713                                        dev_priv->display.get_fifo_size(dev, 0),
1714                                        4, pessimal_latency_ns);
1715         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1716         fwater_lo |= (3<<8) | planea_wm;
1717
1718         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1719
1720         I915_WRITE(FW_BLC, fwater_lo);
1721 }
1722
1723 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1724 {
1725         uint32_t pixel_rate;
1726
1727         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1728
1729         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1730          * adjust the pixel_rate here. */
1731
1732         if (pipe_config->pch_pfit.enabled) {
1733                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1734                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1735
1736                 pipe_w = pipe_config->pipe_src_w;
1737                 pipe_h = pipe_config->pipe_src_h;
1738
1739                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1740                 pfit_h = pfit_size & 0xFFFF;
1741                 if (pipe_w < pfit_w)
1742                         pipe_w = pfit_w;
1743                 if (pipe_h < pfit_h)
1744                         pipe_h = pfit_h;
1745
1746                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1747                                      pfit_w * pfit_h);
1748         }
1749
1750         return pixel_rate;
1751 }
1752
1753 /* latency must be in 0.1us units. */
1754 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1755                                uint32_t latency)
1756 {
1757         uint64_t ret;
1758
1759         if (WARN(latency == 0, "Latency value missing\n"))
1760                 return UINT_MAX;
1761
1762         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1763         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1764
1765         return ret;
1766 }
1767
1768 /* latency must be in 0.1us units. */
1769 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1770                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1771                                uint32_t latency)
1772 {
1773         uint32_t ret;
1774
1775         if (WARN(latency == 0, "Latency value missing\n"))
1776                 return UINT_MAX;
1777
1778         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1779         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1780         ret = DIV_ROUND_UP(ret, 64) + 2;
1781         return ret;
1782 }
1783
1784 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1785                            uint8_t bytes_per_pixel)
1786 {
1787         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1788 }
1789
1790 struct skl_pipe_wm_parameters {
1791         bool active;
1792         uint32_t pipe_htotal;
1793         uint32_t pixel_rate; /* in KHz */
1794         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1795         struct intel_plane_wm_parameters cursor;
1796 };
1797
1798 struct ilk_pipe_wm_parameters {
1799         bool active;
1800         uint32_t pipe_htotal;
1801         uint32_t pixel_rate;
1802         struct intel_plane_wm_parameters pri;
1803         struct intel_plane_wm_parameters spr;
1804         struct intel_plane_wm_parameters cur;
1805 };
1806
1807 struct ilk_wm_maximums {
1808         uint16_t pri;
1809         uint16_t spr;
1810         uint16_t cur;
1811         uint16_t fbc;
1812 };
1813
1814 /* used in computing the new watermarks state */
1815 struct intel_wm_config {
1816         unsigned int num_pipes_active;
1817         bool sprites_enabled;
1818         bool sprites_scaled;
1819 };
1820
1821 /*
1822  * For both WM_PIPE and WM_LP.
1823  * mem_value must be in 0.1us units.
1824  */
1825 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1826                                    uint32_t mem_value,
1827                                    bool is_lp)
1828 {
1829         uint32_t method1, method2;
1830
1831         if (!params->active || !params->pri.enabled)
1832                 return 0;
1833
1834         method1 = ilk_wm_method1(params->pixel_rate,
1835                                  params->pri.bytes_per_pixel,
1836                                  mem_value);
1837
1838         if (!is_lp)
1839                 return method1;
1840
1841         method2 = ilk_wm_method2(params->pixel_rate,
1842                                  params->pipe_htotal,
1843                                  params->pri.horiz_pixels,
1844                                  params->pri.bytes_per_pixel,
1845                                  mem_value);
1846
1847         return min(method1, method2);
1848 }
1849
1850 /*
1851  * For both WM_PIPE and WM_LP.
1852  * mem_value must be in 0.1us units.
1853  */
1854 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1855                                    uint32_t mem_value)
1856 {
1857         uint32_t method1, method2;
1858
1859         if (!params->active || !params->spr.enabled)
1860                 return 0;
1861
1862         method1 = ilk_wm_method1(params->pixel_rate,
1863                                  params->spr.bytes_per_pixel,
1864                                  mem_value);
1865         method2 = ilk_wm_method2(params->pixel_rate,
1866                                  params->pipe_htotal,
1867                                  params->spr.horiz_pixels,
1868                                  params->spr.bytes_per_pixel,
1869                                  mem_value);
1870         return min(method1, method2);
1871 }
1872
1873 /*
1874  * For both WM_PIPE and WM_LP.
1875  * mem_value must be in 0.1us units.
1876  */
1877 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1878                                    uint32_t mem_value)
1879 {
1880         if (!params->active || !params->cur.enabled)
1881                 return 0;
1882
1883         return ilk_wm_method2(params->pixel_rate,
1884                               params->pipe_htotal,
1885                               params->cur.horiz_pixels,
1886                               params->cur.bytes_per_pixel,
1887                               mem_value);
1888 }
1889
1890 /* Only for WM_LP. */
1891 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1892                                    uint32_t pri_val)
1893 {
1894         if (!params->active || !params->pri.enabled)
1895                 return 0;
1896
1897         return ilk_wm_fbc(pri_val,
1898                           params->pri.horiz_pixels,
1899                           params->pri.bytes_per_pixel);
1900 }
1901
1902 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1903 {
1904         if (INTEL_INFO(dev)->gen >= 8)
1905                 return 3072;
1906         else if (INTEL_INFO(dev)->gen >= 7)
1907                 return 768;
1908         else
1909                 return 512;
1910 }
1911
1912 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1913                                          int level, bool is_sprite)
1914 {
1915         if (INTEL_INFO(dev)->gen >= 8)
1916                 /* BDW primary/sprite plane watermarks */
1917                 return level == 0 ? 255 : 2047;
1918         else if (INTEL_INFO(dev)->gen >= 7)
1919                 /* IVB/HSW primary/sprite plane watermarks */
1920                 return level == 0 ? 127 : 1023;
1921         else if (!is_sprite)
1922                 /* ILK/SNB primary plane watermarks */
1923                 return level == 0 ? 127 : 511;
1924         else
1925                 /* ILK/SNB sprite plane watermarks */
1926                 return level == 0 ? 63 : 255;
1927 }
1928
1929 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1930                                           int level)
1931 {
1932         if (INTEL_INFO(dev)->gen >= 7)
1933                 return level == 0 ? 63 : 255;
1934         else
1935                 return level == 0 ? 31 : 63;
1936 }
1937
1938 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1939 {
1940         if (INTEL_INFO(dev)->gen >= 8)
1941                 return 31;
1942         else
1943                 return 15;
1944 }
1945
1946 /* Calculate the maximum primary/sprite plane watermark */
1947 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1948                                      int level,
1949                                      const struct intel_wm_config *config,
1950                                      enum intel_ddb_partitioning ddb_partitioning,
1951                                      bool is_sprite)
1952 {
1953         unsigned int fifo_size = ilk_display_fifo_size(dev);
1954
1955         /* if sprites aren't enabled, sprites get nothing */
1956         if (is_sprite && !config->sprites_enabled)
1957                 return 0;
1958
1959         /* HSW allows LP1+ watermarks even with multiple pipes */
1960         if (level == 0 || config->num_pipes_active > 1) {
1961                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1962
1963                 /*
1964                  * For some reason the non self refresh
1965                  * FIFO size is only half of the self
1966                  * refresh FIFO size on ILK/SNB.
1967                  */
1968                 if (INTEL_INFO(dev)->gen <= 6)
1969                         fifo_size /= 2;
1970         }
1971
1972         if (config->sprites_enabled) {
1973                 /* level 0 is always calculated with 1:1 split */
1974                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1975                         if (is_sprite)
1976                                 fifo_size *= 5;
1977                         fifo_size /= 6;
1978                 } else {
1979                         fifo_size /= 2;
1980                 }
1981         }
1982
1983         /* clamp to max that the registers can hold */
1984         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1985 }
1986
1987 /* Calculate the maximum cursor plane watermark */
1988 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1989                                       int level,
1990                                       const struct intel_wm_config *config)
1991 {
1992         /* HSW LP1+ watermarks w/ multiple pipes */
1993         if (level > 0 && config->num_pipes_active > 1)
1994                 return 64;
1995
1996         /* otherwise just report max that registers can hold */
1997         return ilk_cursor_wm_reg_max(dev, level);
1998 }
1999
2000 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2001                                     int level,
2002                                     const struct intel_wm_config *config,
2003                                     enum intel_ddb_partitioning ddb_partitioning,
2004                                     struct ilk_wm_maximums *max)
2005 {
2006         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2007         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2008         max->cur = ilk_cursor_wm_max(dev, level, config);
2009         max->fbc = ilk_fbc_wm_reg_max(dev);
2010 }
2011
2012 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2013                                         int level,
2014                                         struct ilk_wm_maximums *max)
2015 {
2016         max->pri = ilk_plane_wm_reg_max(dev, level, false);
2017         max->spr = ilk_plane_wm_reg_max(dev, level, true);
2018         max->cur = ilk_cursor_wm_reg_max(dev, level);
2019         max->fbc = ilk_fbc_wm_reg_max(dev);
2020 }
2021
2022 static bool ilk_validate_wm_level(int level,
2023                                   const struct ilk_wm_maximums *max,
2024                                   struct intel_wm_level *result)
2025 {
2026         bool ret;
2027
2028         /* already determined to be invalid? */
2029         if (!result->enable)
2030                 return false;
2031
2032         result->enable = result->pri_val <= max->pri &&
2033                          result->spr_val <= max->spr &&
2034                          result->cur_val <= max->cur;
2035
2036         ret = result->enable;
2037
2038         /*
2039          * HACK until we can pre-compute everything,
2040          * and thus fail gracefully if LP0 watermarks
2041          * are exceeded...
2042          */
2043         if (level == 0 && !result->enable) {
2044                 if (result->pri_val > max->pri)
2045                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2046                                       level, result->pri_val, max->pri);
2047                 if (result->spr_val > max->spr)
2048                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2049                                       level, result->spr_val, max->spr);
2050                 if (result->cur_val > max->cur)
2051                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2052                                       level, result->cur_val, max->cur);
2053
2054                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2055                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2056                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2057                 result->enable = true;
2058         }
2059
2060         return ret;
2061 }
2062
2063 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2064                                  int level,
2065                                  const struct ilk_pipe_wm_parameters *p,
2066                                  struct intel_wm_level *result)
2067 {
2068         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2069         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2070         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2071
2072         /* WM1+ latency values stored in 0.5us units */
2073         if (level > 0) {
2074                 pri_latency *= 5;
2075                 spr_latency *= 5;
2076                 cur_latency *= 5;
2077         }
2078
2079         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2080         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2081         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2082         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2083         result->enable = true;
2084 }
2085
2086 static uint32_t
2087 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2088 {
2089         struct drm_i915_private *dev_priv = dev->dev_private;
2090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2091         struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
2092         u32 linetime, ips_linetime;
2093
2094         if (!intel_crtc->active)
2095                 return 0;
2096
2097         /* The WM are computed with base on how long it takes to fill a single
2098          * row at the given clock rate, multiplied by 8.
2099          * */
2100         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2101                                      mode->crtc_clock);
2102         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2103                                          dev_priv->cdclk_freq);
2104
2105         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2106                PIPE_WM_LINETIME_TIME(linetime);
2107 }
2108
2109 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2110 {
2111         struct drm_i915_private *dev_priv = dev->dev_private;
2112
2113         if (IS_GEN9(dev)) {
2114                 uint32_t val;
2115                 int ret, i;
2116                 int level, max_level = ilk_wm_max_level(dev);
2117
2118                 /* read the first set of memory latencies[0:3] */
2119                 val = 0; /* data0 to be programmed to 0 for first set */
2120                 mutex_lock(&dev_priv->rps.hw_lock);
2121                 ret = sandybridge_pcode_read(dev_priv,
2122                                              GEN9_PCODE_READ_MEM_LATENCY,
2123                                              &val);
2124                 mutex_unlock(&dev_priv->rps.hw_lock);
2125
2126                 if (ret) {
2127                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2128                         return;
2129                 }
2130
2131                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2132                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2133                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2134                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2135                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2136                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2137                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2138
2139                 /* read the second set of memory latencies[4:7] */
2140                 val = 1; /* data0 to be programmed to 1 for second set */
2141                 mutex_lock(&dev_priv->rps.hw_lock);
2142                 ret = sandybridge_pcode_read(dev_priv,
2143                                              GEN9_PCODE_READ_MEM_LATENCY,
2144                                              &val);
2145                 mutex_unlock(&dev_priv->rps.hw_lock);
2146                 if (ret) {
2147                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2148                         return;
2149                 }
2150
2151                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2152                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2153                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2154                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2155                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2156                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2157                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2158
2159                 /*
2160                  * WaWmMemoryReadLatency:skl
2161                  *
2162                  * punit doesn't take into account the read latency so we need
2163                  * to add 2us to the various latency levels we retrieve from
2164                  * the punit.
2165                  *   - W0 is a bit special in that it's the only level that
2166                  *   can't be disabled if we want to have display working, so
2167                  *   we always add 2us there.
2168                  *   - For levels >=1, punit returns 0us latency when they are
2169                  *   disabled, so we respect that and don't add 2us then
2170                  *
2171                  * Additionally, if a level n (n > 1) has a 0us latency, all
2172                  * levels m (m >= n) need to be disabled. We make sure to
2173                  * sanitize the values out of the punit to satisfy this
2174                  * requirement.
2175                  */
2176                 wm[0] += 2;
2177                 for (level = 1; level <= max_level; level++)
2178                         if (wm[level] != 0)
2179                                 wm[level] += 2;
2180                         else {
2181                                 for (i = level + 1; i <= max_level; i++)
2182                                         wm[i] = 0;
2183
2184                                 break;
2185                         }
2186         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2187                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2188
2189                 wm[0] = (sskpd >> 56) & 0xFF;
2190                 if (wm[0] == 0)
2191                         wm[0] = sskpd & 0xF;
2192                 wm[1] = (sskpd >> 4) & 0xFF;
2193                 wm[2] = (sskpd >> 12) & 0xFF;
2194                 wm[3] = (sskpd >> 20) & 0x1FF;
2195                 wm[4] = (sskpd >> 32) & 0x1FF;
2196         } else if (INTEL_INFO(dev)->gen >= 6) {
2197                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2198
2199                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2200                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2201                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2202                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2203         } else if (INTEL_INFO(dev)->gen >= 5) {
2204                 uint32_t mltr = I915_READ(MLTR_ILK);
2205
2206                 /* ILK primary LP0 latency is 700 ns */
2207                 wm[0] = 7;
2208                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2209                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2210         }
2211 }
2212
2213 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2214 {
2215         /* ILK sprite LP0 latency is 1300 ns */
2216         if (INTEL_INFO(dev)->gen == 5)
2217                 wm[0] = 13;
2218 }
2219
2220 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2221 {
2222         /* ILK cursor LP0 latency is 1300 ns */
2223         if (INTEL_INFO(dev)->gen == 5)
2224                 wm[0] = 13;
2225
2226         /* WaDoubleCursorLP3Latency:ivb */
2227         if (IS_IVYBRIDGE(dev))
2228                 wm[3] *= 2;
2229 }
2230
2231 int ilk_wm_max_level(const struct drm_device *dev)
2232 {
2233         /* how many WM levels are we expecting */
2234         if (INTEL_INFO(dev)->gen >= 9)
2235                 return 7;
2236         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2237                 return 4;
2238         else if (INTEL_INFO(dev)->gen >= 6)
2239                 return 3;
2240         else
2241                 return 2;
2242 }
2243
2244 static void intel_print_wm_latency(struct drm_device *dev,
2245                                    const char *name,
2246                                    const uint16_t wm[8])
2247 {
2248         int level, max_level = ilk_wm_max_level(dev);
2249
2250         for (level = 0; level <= max_level; level++) {
2251                 unsigned int latency = wm[level];
2252
2253                 if (latency == 0) {
2254                         DRM_ERROR("%s WM%d latency not provided\n",
2255                                   name, level);
2256                         continue;
2257                 }
2258
2259                 /*
2260                  * - latencies are in us on gen9.
2261                  * - before then, WM1+ latency values are in 0.5us units
2262                  */
2263                 if (IS_GEN9(dev))
2264                         latency *= 10;
2265                 else if (level > 0)
2266                         latency *= 5;
2267
2268                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2269                               name, level, wm[level],
2270                               latency / 10, latency % 10);
2271         }
2272 }
2273
2274 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2275                                     uint16_t wm[5], uint16_t min)
2276 {
2277         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2278
2279         if (wm[0] >= min)
2280                 return false;
2281
2282         wm[0] = max(wm[0], min);
2283         for (level = 1; level <= max_level; level++)
2284                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2285
2286         return true;
2287 }
2288
2289 static void snb_wm_latency_quirk(struct drm_device *dev)
2290 {
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292         bool changed;
2293
2294         /*
2295          * The BIOS provided WM memory latency values are often
2296          * inadequate for high resolution displays. Adjust them.
2297          */
2298         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2299                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2300                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2301
2302         if (!changed)
2303                 return;
2304
2305         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2306         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2307         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2308         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2309 }
2310
2311 static void ilk_setup_wm_latency(struct drm_device *dev)
2312 {
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314
2315         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2316
2317         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2318                sizeof(dev_priv->wm.pri_latency));
2319         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2320                sizeof(dev_priv->wm.pri_latency));
2321
2322         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2323         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2324
2325         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2326         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2327         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2328
2329         if (IS_GEN6(dev))
2330                 snb_wm_latency_quirk(dev);
2331 }
2332
2333 static void skl_setup_wm_latency(struct drm_device *dev)
2334 {
2335         struct drm_i915_private *dev_priv = dev->dev_private;
2336
2337         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2338         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2339 }
2340
2341 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2342                                       struct ilk_pipe_wm_parameters *p)
2343 {
2344         struct drm_device *dev = crtc->dev;
2345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346         enum pipe pipe = intel_crtc->pipe;
2347         struct drm_plane *plane;
2348
2349         if (!intel_crtc->active)
2350                 return;
2351
2352         p->active = true;
2353         p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2354         p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
2355
2356         if (crtc->primary->state->fb)
2357                 p->pri.bytes_per_pixel =
2358                         crtc->primary->state->fb->bits_per_pixel / 8;
2359         else
2360                 p->pri.bytes_per_pixel = 4;
2361
2362         p->cur.bytes_per_pixel = 4;
2363         /*
2364          * TODO: for now, assume primary and cursor planes are always enabled.
2365          * Setting them to false makes the screen flicker.
2366          */
2367         p->pri.enabled = true;
2368         p->cur.enabled = true;
2369
2370         p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2371         p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2372
2373         drm_for_each_legacy_plane(plane, dev) {
2374                 struct intel_plane *intel_plane = to_intel_plane(plane);
2375
2376                 if (intel_plane->pipe == pipe) {
2377                         p->spr = intel_plane->wm;
2378                         break;
2379                 }
2380         }
2381 }
2382
2383 static void ilk_compute_wm_config(struct drm_device *dev,
2384                                   struct intel_wm_config *config)
2385 {
2386         struct intel_crtc *intel_crtc;
2387
2388         /* Compute the currently _active_ config */
2389         for_each_intel_crtc(dev, intel_crtc) {
2390                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2391
2392                 if (!wm->pipe_enabled)
2393                         continue;
2394
2395                 config->sprites_enabled |= wm->sprites_enabled;
2396                 config->sprites_scaled |= wm->sprites_scaled;
2397                 config->num_pipes_active++;
2398         }
2399 }
2400
2401 /* Compute new watermarks for the pipe */
2402 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2403                                   const struct ilk_pipe_wm_parameters *params,
2404                                   struct intel_pipe_wm *pipe_wm)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         const struct drm_i915_private *dev_priv = dev->dev_private;
2408         int level, max_level = ilk_wm_max_level(dev);
2409         /* LP0 watermark maximums depend on this pipe alone */
2410         struct intel_wm_config config = {
2411                 .num_pipes_active = 1,
2412                 .sprites_enabled = params->spr.enabled,
2413                 .sprites_scaled = params->spr.scaled,
2414         };
2415         struct ilk_wm_maximums max;
2416
2417         pipe_wm->pipe_enabled = params->active;
2418         pipe_wm->sprites_enabled = params->spr.enabled;
2419         pipe_wm->sprites_scaled = params->spr.scaled;
2420
2421         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2422         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2423                 max_level = 1;
2424
2425         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2426         if (params->spr.scaled)
2427                 max_level = 0;
2428
2429         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2430
2431         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2432                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2433
2434         /* LP0 watermarks always use 1/2 DDB partitioning */
2435         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2436
2437         /* At least LP0 must be valid */
2438         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2439                 return false;
2440
2441         ilk_compute_wm_reg_maximums(dev, 1, &max);
2442
2443         for (level = 1; level <= max_level; level++) {
2444                 struct intel_wm_level wm = {};
2445
2446                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2447
2448                 /*
2449                  * Disable any watermark level that exceeds the
2450                  * register maximums since such watermarks are
2451                  * always invalid.
2452                  */
2453                 if (!ilk_validate_wm_level(level, &max, &wm))
2454                         break;
2455
2456                 pipe_wm->wm[level] = wm;
2457         }
2458
2459         return true;
2460 }
2461
2462 /*
2463  * Merge the watermarks from all active pipes for a specific level.
2464  */
2465 static void ilk_merge_wm_level(struct drm_device *dev,
2466                                int level,
2467                                struct intel_wm_level *ret_wm)
2468 {
2469         const struct intel_crtc *intel_crtc;
2470
2471         ret_wm->enable = true;
2472
2473         for_each_intel_crtc(dev, intel_crtc) {
2474                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2475                 const struct intel_wm_level *wm = &active->wm[level];
2476
2477                 if (!active->pipe_enabled)
2478                         continue;
2479
2480                 /*
2481                  * The watermark values may have been used in the past,
2482                  * so we must maintain them in the registers for some
2483                  * time even if the level is now disabled.
2484                  */
2485                 if (!wm->enable)
2486                         ret_wm->enable = false;
2487
2488                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2489                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2490                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2491                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2492         }
2493 }
2494
2495 /*
2496  * Merge all low power watermarks for all active pipes.
2497  */
2498 static void ilk_wm_merge(struct drm_device *dev,
2499                          const struct intel_wm_config *config,
2500                          const struct ilk_wm_maximums *max,
2501                          struct intel_pipe_wm *merged)
2502 {
2503         struct drm_i915_private *dev_priv = dev->dev_private;
2504         int level, max_level = ilk_wm_max_level(dev);
2505         int last_enabled_level = max_level;
2506
2507         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2508         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2509             config->num_pipes_active > 1)
2510                 return;
2511
2512         /* ILK: FBC WM must be disabled always */
2513         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2514
2515         /* merge each WM1+ level */
2516         for (level = 1; level <= max_level; level++) {
2517                 struct intel_wm_level *wm = &merged->wm[level];
2518
2519                 ilk_merge_wm_level(dev, level, wm);
2520
2521                 if (level > last_enabled_level)
2522                         wm->enable = false;
2523                 else if (!ilk_validate_wm_level(level, max, wm))
2524                         /* make sure all following levels get disabled */
2525                         last_enabled_level = level - 1;
2526
2527                 /*
2528                  * The spec says it is preferred to disable
2529                  * FBC WMs instead of disabling a WM level.
2530                  */
2531                 if (wm->fbc_val > max->fbc) {
2532                         if (wm->enable)
2533                                 merged->fbc_wm_enabled = false;
2534                         wm->fbc_val = 0;
2535                 }
2536         }
2537
2538         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2539         /*
2540          * FIXME this is racy. FBC might get enabled later.
2541          * What we should check here is whether FBC can be
2542          * enabled sometime later.
2543          */
2544         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2545             intel_fbc_enabled(dev_priv)) {
2546                 for (level = 2; level <= max_level; level++) {
2547                         struct intel_wm_level *wm = &merged->wm[level];
2548
2549                         wm->enable = false;
2550                 }
2551         }
2552 }
2553
2554 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2555 {
2556         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2557         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2558 }
2559
2560 /* The value we need to program into the WM_LPx latency field */
2561 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2562 {
2563         struct drm_i915_private *dev_priv = dev->dev_private;
2564
2565         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2566                 return 2 * level;
2567         else
2568                 return dev_priv->wm.pri_latency[level];
2569 }
2570
2571 static void ilk_compute_wm_results(struct drm_device *dev,
2572                                    const struct intel_pipe_wm *merged,
2573                                    enum intel_ddb_partitioning partitioning,
2574                                    struct ilk_wm_values *results)
2575 {
2576         struct intel_crtc *intel_crtc;
2577         int level, wm_lp;
2578
2579         results->enable_fbc_wm = merged->fbc_wm_enabled;
2580         results->partitioning = partitioning;
2581
2582         /* LP1+ register values */
2583         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2584                 const struct intel_wm_level *r;
2585
2586                 level = ilk_wm_lp_to_level(wm_lp, merged);
2587
2588                 r = &merged->wm[level];
2589
2590                 /*
2591                  * Maintain the watermark values even if the level is
2592                  * disabled. Doing otherwise could cause underruns.
2593                  */
2594                 results->wm_lp[wm_lp - 1] =
2595                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2596                         (r->pri_val << WM1_LP_SR_SHIFT) |
2597                         r->cur_val;
2598
2599                 if (r->enable)
2600                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2601
2602                 if (INTEL_INFO(dev)->gen >= 8)
2603                         results->wm_lp[wm_lp - 1] |=
2604                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2605                 else
2606                         results->wm_lp[wm_lp - 1] |=
2607                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2608
2609                 /*
2610                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2611                  * level is disabled. Doing otherwise could cause underruns.
2612                  */
2613                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2614                         WARN_ON(wm_lp != 1);
2615                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2616                 } else
2617                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2618         }
2619
2620         /* LP0 register values */
2621         for_each_intel_crtc(dev, intel_crtc) {
2622                 enum pipe pipe = intel_crtc->pipe;
2623                 const struct intel_wm_level *r =
2624                         &intel_crtc->wm.active.wm[0];
2625
2626                 if (WARN_ON(!r->enable))
2627                         continue;
2628
2629                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2630
2631                 results->wm_pipe[pipe] =
2632                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2633                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2634                         r->cur_val;
2635         }
2636 }
2637
2638 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2639  * case both are at the same level. Prefer r1 in case they're the same. */
2640 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2641                                                   struct intel_pipe_wm *r1,
2642                                                   struct intel_pipe_wm *r2)
2643 {
2644         int level, max_level = ilk_wm_max_level(dev);
2645         int level1 = 0, level2 = 0;
2646
2647         for (level = 1; level <= max_level; level++) {
2648                 if (r1->wm[level].enable)
2649                         level1 = level;
2650                 if (r2->wm[level].enable)
2651                         level2 = level;
2652         }
2653
2654         if (level1 == level2) {
2655                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2656                         return r2;
2657                 else
2658                         return r1;
2659         } else if (level1 > level2) {
2660                 return r1;
2661         } else {
2662                 return r2;
2663         }
2664 }
2665
2666 /* dirty bits used to track which watermarks need changes */
2667 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2668 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2669 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2670 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2671 #define WM_DIRTY_FBC (1 << 24)
2672 #define WM_DIRTY_DDB (1 << 25)
2673
2674 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2675                                          const struct ilk_wm_values *old,
2676                                          const struct ilk_wm_values *new)
2677 {
2678         unsigned int dirty = 0;
2679         enum pipe pipe;
2680         int wm_lp;
2681
2682         for_each_pipe(dev_priv, pipe) {
2683                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2684                         dirty |= WM_DIRTY_LINETIME(pipe);
2685                         /* Must disable LP1+ watermarks too */
2686                         dirty |= WM_DIRTY_LP_ALL;
2687                 }
2688
2689                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2690                         dirty |= WM_DIRTY_PIPE(pipe);
2691                         /* Must disable LP1+ watermarks too */
2692                         dirty |= WM_DIRTY_LP_ALL;
2693                 }
2694         }
2695
2696         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2697                 dirty |= WM_DIRTY_FBC;
2698                 /* Must disable LP1+ watermarks too */
2699                 dirty |= WM_DIRTY_LP_ALL;
2700         }
2701
2702         if (old->partitioning != new->partitioning) {
2703                 dirty |= WM_DIRTY_DDB;
2704                 /* Must disable LP1+ watermarks too */
2705                 dirty |= WM_DIRTY_LP_ALL;
2706         }
2707
2708         /* LP1+ watermarks already deemed dirty, no need to continue */
2709         if (dirty & WM_DIRTY_LP_ALL)
2710                 return dirty;
2711
2712         /* Find the lowest numbered LP1+ watermark in need of an update... */
2713         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2714                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2715                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2716                         break;
2717         }
2718
2719         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2720         for (; wm_lp <= 3; wm_lp++)
2721                 dirty |= WM_DIRTY_LP(wm_lp);
2722
2723         return dirty;
2724 }
2725
2726 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2727                                unsigned int dirty)
2728 {
2729         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2730         bool changed = false;
2731
2732         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2733                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2734                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2735                 changed = true;
2736         }
2737         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2738                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2739                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2740                 changed = true;
2741         }
2742         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2743                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2744                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2745                 changed = true;
2746         }
2747
2748         /*
2749          * Don't touch WM1S_LP_EN here.
2750          * Doing so could cause underruns.
2751          */
2752
2753         return changed;
2754 }
2755
2756 /*
2757  * The spec says we shouldn't write when we don't need, because every write
2758  * causes WMs to be re-evaluated, expending some power.
2759  */
2760 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2761                                 struct ilk_wm_values *results)
2762 {
2763         struct drm_device *dev = dev_priv->dev;
2764         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2765         unsigned int dirty;
2766         uint32_t val;
2767
2768         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2769         if (!dirty)
2770                 return;
2771
2772         _ilk_disable_lp_wm(dev_priv, dirty);
2773
2774         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2775                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2776         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2777                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2778         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2779                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2780
2781         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2782                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2783         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2784                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2785         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2786                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2787
2788         if (dirty & WM_DIRTY_DDB) {
2789                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2790                         val = I915_READ(WM_MISC);
2791                         if (results->partitioning == INTEL_DDB_PART_1_2)
2792                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2793                         else
2794                                 val |= WM_MISC_DATA_PARTITION_5_6;
2795                         I915_WRITE(WM_MISC, val);
2796                 } else {
2797                         val = I915_READ(DISP_ARB_CTL2);
2798                         if (results->partitioning == INTEL_DDB_PART_1_2)
2799                                 val &= ~DISP_DATA_PARTITION_5_6;
2800                         else
2801                                 val |= DISP_DATA_PARTITION_5_6;
2802                         I915_WRITE(DISP_ARB_CTL2, val);
2803                 }
2804         }
2805
2806         if (dirty & WM_DIRTY_FBC) {
2807                 val = I915_READ(DISP_ARB_CTL);
2808                 if (results->enable_fbc_wm)
2809                         val &= ~DISP_FBC_WM_DIS;
2810                 else
2811                         val |= DISP_FBC_WM_DIS;
2812                 I915_WRITE(DISP_ARB_CTL, val);
2813         }
2814
2815         if (dirty & WM_DIRTY_LP(1) &&
2816             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2817                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2818
2819         if (INTEL_INFO(dev)->gen >= 7) {
2820                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2821                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2822                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2823                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2824         }
2825
2826         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2827                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2828         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2829                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2830         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2831                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2832
2833         dev_priv->wm.hw = *results;
2834 }
2835
2836 static bool ilk_disable_lp_wm(struct drm_device *dev)
2837 {
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839
2840         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2841 }
2842
2843 /*
2844  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2845  * different active planes.
2846  */
2847
2848 #define SKL_DDB_SIZE            896     /* in blocks */
2849 #define BXT_DDB_SIZE            512
2850
2851 static void
2852 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2853                                    struct drm_crtc *for_crtc,
2854                                    const struct intel_wm_config *config,
2855                                    const struct skl_pipe_wm_parameters *params,
2856                                    struct skl_ddb_entry *alloc /* out */)
2857 {
2858         struct drm_crtc *crtc;
2859         unsigned int pipe_size, ddb_size;
2860         int nth_active_pipe;
2861
2862         if (!params->active) {
2863                 alloc->start = 0;
2864                 alloc->end = 0;
2865                 return;
2866         }
2867
2868         if (IS_BROXTON(dev))
2869                 ddb_size = BXT_DDB_SIZE;
2870         else
2871                 ddb_size = SKL_DDB_SIZE;
2872
2873         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2874
2875         nth_active_pipe = 0;
2876         for_each_crtc(dev, crtc) {
2877                 if (!to_intel_crtc(crtc)->active)
2878                         continue;
2879
2880                 if (crtc == for_crtc)
2881                         break;
2882
2883                 nth_active_pipe++;
2884         }
2885
2886         pipe_size = ddb_size / config->num_pipes_active;
2887         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2888         alloc->end = alloc->start + pipe_size;
2889 }
2890
2891 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2892 {
2893         if (config->num_pipes_active == 1)
2894                 return 32;
2895
2896         return 8;
2897 }
2898
2899 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2900 {
2901         entry->start = reg & 0x3ff;
2902         entry->end = (reg >> 16) & 0x3ff;
2903         if (entry->end)
2904                 entry->end += 1;
2905 }
2906
2907 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2908                           struct skl_ddb_allocation *ddb /* out */)
2909 {
2910         enum pipe pipe;
2911         int plane;
2912         u32 val;
2913
2914         for_each_pipe(dev_priv, pipe) {
2915                 for_each_plane(dev_priv, pipe, plane) {
2916                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2917                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2918                                                    val);
2919                 }
2920
2921                 val = I915_READ(CUR_BUF_CFG(pipe));
2922                 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2923         }
2924 }
2925
2926 static unsigned int
2927 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2928 {
2929
2930         /* for planar format */
2931         if (p->y_bytes_per_pixel) {
2932                 if (y)  /* y-plane data rate */
2933                         return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2934                 else    /* uv-plane data rate */
2935                         return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2936         }
2937
2938         /* for packed formats */
2939         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2940 }
2941
2942 /*
2943  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2944  * a 8192x4096@32bpp framebuffer:
2945  *   3 * 4096 * 8192  * 4 < 2^32
2946  */
2947 static unsigned int
2948 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2949                                  const struct skl_pipe_wm_parameters *params)
2950 {
2951         unsigned int total_data_rate = 0;
2952         int plane;
2953
2954         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2955                 const struct intel_plane_wm_parameters *p;
2956
2957                 p = &params->plane[plane];
2958                 if (!p->enabled)
2959                         continue;
2960
2961                 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2962                 if (p->y_bytes_per_pixel) {
2963                         total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2964                 }
2965         }
2966
2967         return total_data_rate;
2968 }
2969
2970 static void
2971 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2972                       const struct intel_wm_config *config,
2973                       const struct skl_pipe_wm_parameters *params,
2974                       struct skl_ddb_allocation *ddb /* out */)
2975 {
2976         struct drm_device *dev = crtc->dev;
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979         enum pipe pipe = intel_crtc->pipe;
2980         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2981         uint16_t alloc_size, start, cursor_blocks;
2982         uint16_t minimum[I915_MAX_PLANES];
2983         uint16_t y_minimum[I915_MAX_PLANES];
2984         unsigned int total_data_rate;
2985         int plane;
2986
2987         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2988         alloc_size = skl_ddb_entry_size(alloc);
2989         if (alloc_size == 0) {
2990                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2991                 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2992                 return;
2993         }
2994
2995         cursor_blocks = skl_cursor_allocation(config);
2996         ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2997         ddb->cursor[pipe].end = alloc->end;
2998
2999         alloc_size -= cursor_blocks;
3000         alloc->end -= cursor_blocks;
3001
3002         /* 1. Allocate the mininum required blocks for each active plane */
3003         for_each_plane(dev_priv, pipe, plane) {
3004                 const struct intel_plane_wm_parameters *p;
3005
3006                 p = &params->plane[plane];
3007                 if (!p->enabled)
3008                         continue;
3009
3010                 minimum[plane] = 8;
3011                 alloc_size -= minimum[plane];
3012                 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
3013                 alloc_size -= y_minimum[plane];
3014         }
3015
3016         /*
3017          * 2. Distribute the remaining space in proportion to the amount of
3018          * data each plane needs to fetch from memory.
3019          *
3020          * FIXME: we may not allocate every single block here.
3021          */
3022         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3023
3024         start = alloc->start;
3025         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3026                 const struct intel_plane_wm_parameters *p;
3027                 unsigned int data_rate, y_data_rate;
3028                 uint16_t plane_blocks, y_plane_blocks = 0;
3029
3030                 p = &params->plane[plane];
3031                 if (!p->enabled)
3032                         continue;
3033
3034                 data_rate = skl_plane_relative_data_rate(p, 0);
3035
3036                 /*
3037                  * allocation for (packed formats) or (uv-plane part of planar format):
3038                  * promote the expression to 64 bits to avoid overflowing, the
3039                  * result is < available as data_rate / total_data_rate < 1
3040                  */
3041                 plane_blocks = minimum[plane];
3042                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3043                                         total_data_rate);
3044
3045                 ddb->plane[pipe][plane].start = start;
3046                 ddb->plane[pipe][plane].end = start + plane_blocks;
3047
3048                 start += plane_blocks;
3049
3050                 /*
3051                  * allocation for y_plane part of planar format:
3052                  */
3053                 if (p->y_bytes_per_pixel) {
3054                         y_data_rate = skl_plane_relative_data_rate(p, 1);
3055                         y_plane_blocks = y_minimum[plane];
3056                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3057                                                 total_data_rate);
3058
3059                         ddb->y_plane[pipe][plane].start = start;
3060                         ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3061
3062                         start += y_plane_blocks;
3063                 }
3064
3065         }
3066
3067 }
3068
3069 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3070 {
3071         /* TODO: Take into account the scalers once we support them */
3072         return config->base.adjusted_mode.crtc_clock;
3073 }
3074
3075 /*
3076  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3077  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3078  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3079  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3080 */
3081 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3082                                uint32_t latency)
3083 {
3084         uint32_t wm_intermediate_val, ret;
3085
3086         if (latency == 0)
3087                 return UINT_MAX;
3088
3089         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3090         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3091
3092         return ret;
3093 }
3094
3095 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3096                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3097                                uint64_t tiling, uint32_t latency)
3098 {
3099         uint32_t ret;
3100         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3101         uint32_t wm_intermediate_val;
3102
3103         if (latency == 0)
3104                 return UINT_MAX;
3105
3106         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3107
3108         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3109             tiling == I915_FORMAT_MOD_Yf_TILED) {
3110                 plane_bytes_per_line *= 4;
3111                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3112                 plane_blocks_per_line /= 4;
3113         } else {
3114                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3115         }
3116
3117         wm_intermediate_val = latency * pixel_rate;
3118         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3119                                 plane_blocks_per_line;
3120
3121         return ret;
3122 }
3123
3124 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3125                                        const struct intel_crtc *intel_crtc)
3126 {
3127         struct drm_device *dev = intel_crtc->base.dev;
3128         struct drm_i915_private *dev_priv = dev->dev_private;
3129         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3130         enum pipe pipe = intel_crtc->pipe;
3131
3132         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3133                    sizeof(new_ddb->plane[pipe])))
3134                 return true;
3135
3136         if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3137                     sizeof(new_ddb->cursor[pipe])))
3138                 return true;
3139
3140         return false;
3141 }
3142
3143 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3144                                              struct intel_wm_config *config)
3145 {
3146         struct drm_crtc *crtc;
3147         struct drm_plane *plane;
3148
3149         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3150                 config->num_pipes_active += to_intel_crtc(crtc)->active;
3151
3152         /* FIXME: I don't think we need those two global parameters on SKL */
3153         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3154                 struct intel_plane *intel_plane = to_intel_plane(plane);
3155
3156                 config->sprites_enabled |= intel_plane->wm.enabled;
3157                 config->sprites_scaled |= intel_plane->wm.scaled;
3158         }
3159 }
3160
3161 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3162                                            struct skl_pipe_wm_parameters *p)
3163 {
3164         struct drm_device *dev = crtc->dev;
3165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3166         enum pipe pipe = intel_crtc->pipe;
3167         struct drm_plane *plane;
3168         struct drm_framebuffer *fb;
3169         int i = 1; /* Index for sprite planes start */
3170
3171         p->active = intel_crtc->active;
3172         if (p->active) {
3173                 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3174                 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3175
3176                 fb = crtc->primary->state->fb;
3177                 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3178                 if (fb) {
3179                         p->plane[0].enabled = true;
3180                         p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3181                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3182                                 drm_format_plane_cpp(fb->pixel_format, 0);
3183                         p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3184                                 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3185                         p->plane[0].tiling = fb->modifier[0];
3186                 } else {
3187                         p->plane[0].enabled = false;
3188                         p->plane[0].bytes_per_pixel = 0;
3189                         p->plane[0].y_bytes_per_pixel = 0;
3190                         p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3191                 }
3192                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3193                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3194                 p->plane[0].rotation = crtc->primary->state->rotation;
3195
3196                 fb = crtc->cursor->state->fb;
3197                 p->cursor.y_bytes_per_pixel = 0;
3198                 if (fb) {
3199                         p->cursor.enabled = true;
3200                         p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3201                         p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3202                         p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3203                 } else {
3204                         p->cursor.enabled = false;
3205                         p->cursor.bytes_per_pixel = 0;
3206                         p->cursor.horiz_pixels = 64;
3207                         p->cursor.vert_pixels = 64;
3208                 }
3209         }
3210
3211         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3212                 struct intel_plane *intel_plane = to_intel_plane(plane);
3213
3214                 if (intel_plane->pipe == pipe &&
3215                         plane->type == DRM_PLANE_TYPE_OVERLAY)
3216                         p->plane[i++] = intel_plane->wm;
3217         }
3218 }
3219
3220 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3221                                  struct skl_pipe_wm_parameters *p,
3222                                  struct intel_plane_wm_parameters *p_params,
3223                                  uint16_t ddb_allocation,
3224                                  int level,
3225                                  uint16_t *out_blocks, /* out */
3226                                  uint8_t *out_lines /* out */)
3227 {
3228         uint32_t latency = dev_priv->wm.skl_latency[level];
3229         uint32_t method1, method2;
3230         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3231         uint32_t res_blocks, res_lines;
3232         uint32_t selected_result;
3233         uint8_t bytes_per_pixel;
3234
3235         if (latency == 0 || !p->active || !p_params->enabled)
3236                 return false;
3237
3238         bytes_per_pixel = p_params->y_bytes_per_pixel ?
3239                 p_params->y_bytes_per_pixel :
3240                 p_params->bytes_per_pixel;
3241         method1 = skl_wm_method1(p->pixel_rate,
3242                                  bytes_per_pixel,
3243                                  latency);
3244         method2 = skl_wm_method2(p->pixel_rate,
3245                                  p->pipe_htotal,
3246                                  p_params->horiz_pixels,
3247                                  bytes_per_pixel,
3248                                  p_params->tiling,
3249                                  latency);
3250
3251         plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3252         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3253
3254         if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3255             p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3256                 uint32_t min_scanlines = 4;
3257                 uint32_t y_tile_minimum;
3258                 if (intel_rotation_90_or_270(p_params->rotation)) {
3259                         switch (p_params->bytes_per_pixel) {
3260                         case 1:
3261                                 min_scanlines = 16;
3262                                 break;
3263                         case 2:
3264                                 min_scanlines = 8;
3265                                 break;
3266                         case 8:
3267                                 WARN(1, "Unsupported pixel depth for rotation");
3268                         }
3269                 }
3270                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3271                 selected_result = max(method2, y_tile_minimum);
3272         } else {
3273                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3274                         selected_result = min(method1, method2);
3275                 else
3276                         selected_result = method1;
3277         }
3278
3279         res_blocks = selected_result + 1;
3280         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3281
3282         if (level >= 1 && level <= 7) {
3283                 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3284                     p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3285                         res_lines += 4;
3286                 else
3287                         res_blocks++;
3288         }
3289
3290         if (res_blocks >= ddb_allocation || res_lines > 31)
3291                 return false;
3292
3293         *out_blocks = res_blocks;
3294         *out_lines = res_lines;
3295
3296         return true;
3297 }
3298
3299 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3300                                  struct skl_ddb_allocation *ddb,
3301                                  struct skl_pipe_wm_parameters *p,
3302                                  enum pipe pipe,
3303                                  int level,
3304                                  int num_planes,
3305                                  struct skl_wm_level *result)
3306 {
3307         uint16_t ddb_blocks;
3308         int i;
3309
3310         for (i = 0; i < num_planes; i++) {
3311                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3312
3313                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3314                                                 p, &p->plane[i],
3315                                                 ddb_blocks,
3316                                                 level,
3317                                                 &result->plane_res_b[i],
3318                                                 &result->plane_res_l[i]);
3319         }
3320
3321         ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
3322         result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3323                                                  ddb_blocks, level,
3324                                                  &result->cursor_res_b,
3325                                                  &result->cursor_res_l);
3326 }
3327
3328 static uint32_t
3329 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3330 {
3331         if (!to_intel_crtc(crtc)->active)
3332                 return 0;
3333
3334         if (WARN_ON(p->pixel_rate == 0))
3335                 return 0;
3336
3337         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3338 }
3339
3340 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3341                                       struct skl_pipe_wm_parameters *params,
3342                                       struct skl_wm_level *trans_wm /* out */)
3343 {
3344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345         int i;
3346
3347         if (!params->active)
3348                 return;
3349
3350         /* Until we know more, just disable transition WMs */
3351         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3352                 trans_wm->plane_en[i] = false;
3353         trans_wm->cursor_en = false;
3354 }
3355
3356 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3357                                 struct skl_ddb_allocation *ddb,
3358                                 struct skl_pipe_wm_parameters *params,
3359                                 struct skl_pipe_wm *pipe_wm)
3360 {
3361         struct drm_device *dev = crtc->dev;
3362         const struct drm_i915_private *dev_priv = dev->dev_private;
3363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3364         int level, max_level = ilk_wm_max_level(dev);
3365
3366         for (level = 0; level <= max_level; level++) {
3367                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3368                                      level, intel_num_planes(intel_crtc),
3369                                      &pipe_wm->wm[level]);
3370         }
3371         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3372
3373         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3374 }
3375
3376 static void skl_compute_wm_results(struct drm_device *dev,
3377                                    struct skl_pipe_wm_parameters *p,
3378                                    struct skl_pipe_wm *p_wm,
3379                                    struct skl_wm_values *r,
3380                                    struct intel_crtc *intel_crtc)
3381 {
3382         int level, max_level = ilk_wm_max_level(dev);
3383         enum pipe pipe = intel_crtc->pipe;
3384         uint32_t temp;
3385         int i;
3386
3387         for (level = 0; level <= max_level; level++) {
3388                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3389                         temp = 0;
3390
3391                         temp |= p_wm->wm[level].plane_res_l[i] <<
3392                                         PLANE_WM_LINES_SHIFT;
3393                         temp |= p_wm->wm[level].plane_res_b[i];
3394                         if (p_wm->wm[level].plane_en[i])
3395                                 temp |= PLANE_WM_EN;
3396
3397                         r->plane[pipe][i][level] = temp;
3398                 }
3399
3400                 temp = 0;
3401
3402                 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3403                 temp |= p_wm->wm[level].cursor_res_b;
3404
3405                 if (p_wm->wm[level].cursor_en)
3406                         temp |= PLANE_WM_EN;
3407
3408                 r->cursor[pipe][level] = temp;
3409
3410         }
3411
3412         /* transition WMs */
3413         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3414                 temp = 0;
3415                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3416                 temp |= p_wm->trans_wm.plane_res_b[i];
3417                 if (p_wm->trans_wm.plane_en[i])
3418                         temp |= PLANE_WM_EN;
3419
3420                 r->plane_trans[pipe][i] = temp;
3421         }
3422
3423         temp = 0;
3424         temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3425         temp |= p_wm->trans_wm.cursor_res_b;
3426         if (p_wm->trans_wm.cursor_en)
3427                 temp |= PLANE_WM_EN;
3428
3429         r->cursor_trans[pipe] = temp;
3430
3431         r->wm_linetime[pipe] = p_wm->linetime;
3432 }
3433
3434 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3435                                 const struct skl_ddb_entry *entry)
3436 {
3437         if (entry->end)
3438                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3439         else
3440                 I915_WRITE(reg, 0);
3441 }
3442
3443 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3444                                 const struct skl_wm_values *new)
3445 {
3446         struct drm_device *dev = dev_priv->dev;
3447         struct intel_crtc *crtc;
3448
3449         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3450                 int i, level, max_level = ilk_wm_max_level(dev);
3451                 enum pipe pipe = crtc->pipe;
3452
3453                 if (!new->dirty[pipe])
3454                         continue;
3455
3456                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3457
3458                 for (level = 0; level <= max_level; level++) {
3459                         for (i = 0; i < intel_num_planes(crtc); i++)
3460                                 I915_WRITE(PLANE_WM(pipe, i, level),
3461                                            new->plane[pipe][i][level]);
3462                         I915_WRITE(CUR_WM(pipe, level),
3463                                    new->cursor[pipe][level]);
3464                 }
3465                 for (i = 0; i < intel_num_planes(crtc); i++)
3466                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3467                                    new->plane_trans[pipe][i]);
3468                 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3469
3470                 for (i = 0; i < intel_num_planes(crtc); i++) {
3471                         skl_ddb_entry_write(dev_priv,
3472                                             PLANE_BUF_CFG(pipe, i),
3473                                             &new->ddb.plane[pipe][i]);
3474                         skl_ddb_entry_write(dev_priv,
3475                                             PLANE_NV12_BUF_CFG(pipe, i),
3476                                             &new->ddb.y_plane[pipe][i]);
3477                 }
3478
3479                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3480                                     &new->ddb.cursor[pipe]);
3481         }
3482 }
3483
3484 /*
3485  * When setting up a new DDB allocation arrangement, we need to correctly
3486  * sequence the times at which the new allocations for the pipes are taken into
3487  * account or we'll have pipes fetching from space previously allocated to
3488  * another pipe.
3489  *
3490  * Roughly the sequence looks like:
3491  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3492  *     overlapping with a previous light-up pipe (another way to put it is:
3493  *     pipes with their new allocation strickly included into their old ones).
3494  *  2. re-allocate the other pipes that get their allocation reduced
3495  *  3. allocate the pipes having their allocation increased
3496  *
3497  * Steps 1. and 2. are here to take care of the following case:
3498  * - Initially DDB looks like this:
3499  *     |   B    |   C    |
3500  * - enable pipe A.
3501  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3502  *   allocation
3503  *     |  A  |  B  |  C  |
3504  *
3505  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3506  */
3507
3508 static void
3509 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3510 {
3511         int plane;
3512
3513         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3514
3515         for_each_plane(dev_priv, pipe, plane) {
3516                 I915_WRITE(PLANE_SURF(pipe, plane),
3517                            I915_READ(PLANE_SURF(pipe, plane)));
3518         }
3519         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3520 }
3521
3522 static bool
3523 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3524                             const struct skl_ddb_allocation *new,
3525                             enum pipe pipe)
3526 {
3527         uint16_t old_size, new_size;
3528
3529         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3530         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3531
3532         return old_size != new_size &&
3533                new->pipe[pipe].start >= old->pipe[pipe].start &&
3534                new->pipe[pipe].end <= old->pipe[pipe].end;
3535 }
3536
3537 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3538                                 struct skl_wm_values *new_values)
3539 {
3540         struct drm_device *dev = dev_priv->dev;
3541         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3542         bool reallocated[I915_MAX_PIPES] = {};
3543         struct intel_crtc *crtc;
3544         enum pipe pipe;
3545
3546         new_ddb = &new_values->ddb;
3547         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3548
3549         /*
3550          * First pass: flush the pipes with the new allocation contained into
3551          * the old space.
3552          *
3553          * We'll wait for the vblank on those pipes to ensure we can safely
3554          * re-allocate the freed space without this pipe fetching from it.
3555          */
3556         for_each_intel_crtc(dev, crtc) {
3557                 if (!crtc->active)
3558                         continue;
3559
3560                 pipe = crtc->pipe;
3561
3562                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3563                         continue;
3564
3565                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3566                 intel_wait_for_vblank(dev, pipe);
3567
3568                 reallocated[pipe] = true;
3569         }
3570
3571
3572         /*
3573          * Second pass: flush the pipes that are having their allocation
3574          * reduced, but overlapping with a previous allocation.
3575          *
3576          * Here as well we need to wait for the vblank to make sure the freed
3577          * space is not used anymore.
3578          */
3579         for_each_intel_crtc(dev, crtc) {
3580                 if (!crtc->active)
3581                         continue;
3582
3583                 pipe = crtc->pipe;
3584
3585                 if (reallocated[pipe])
3586                         continue;
3587
3588                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3589                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3590                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3591                         intel_wait_for_vblank(dev, pipe);
3592                         reallocated[pipe] = true;
3593                 }
3594         }
3595
3596         /*
3597          * Third pass: flush the pipes that got more space allocated.
3598          *
3599          * We don't need to actively wait for the update here, next vblank
3600          * will just get more DDB space with the correct WM values.
3601          */
3602         for_each_intel_crtc(dev, crtc) {
3603                 if (!crtc->active)
3604                         continue;
3605
3606                 pipe = crtc->pipe;
3607
3608                 /*
3609                  * At this point, only the pipes more space than before are
3610                  * left to re-allocate.
3611                  */
3612                 if (reallocated[pipe])
3613                         continue;
3614
3615                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3616         }
3617 }
3618
3619 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3620                                struct skl_pipe_wm_parameters *params,
3621                                struct intel_wm_config *config,
3622                                struct skl_ddb_allocation *ddb, /* out */
3623                                struct skl_pipe_wm *pipe_wm /* out */)
3624 {
3625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626
3627         skl_compute_wm_pipe_parameters(crtc, params);
3628         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3629         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3630
3631         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3632                 return false;
3633
3634         intel_crtc->wm.skl_active = *pipe_wm;
3635
3636         return true;
3637 }
3638
3639 static void skl_update_other_pipe_wm(struct drm_device *dev,
3640                                      struct drm_crtc *crtc,
3641                                      struct intel_wm_config *config,
3642                                      struct skl_wm_values *r)
3643 {
3644         struct intel_crtc *intel_crtc;
3645         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3646
3647         /*
3648          * If the WM update hasn't changed the allocation for this_crtc (the
3649          * crtc we are currently computing the new WM values for), other
3650          * enabled crtcs will keep the same allocation and we don't need to
3651          * recompute anything for them.
3652          */
3653         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3654                 return;
3655
3656         /*
3657          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3658          * other active pipes need new DDB allocation and WM values.
3659          */
3660         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3661                                 base.head) {
3662                 struct skl_pipe_wm_parameters params = {};
3663                 struct skl_pipe_wm pipe_wm = {};
3664                 bool wm_changed;
3665
3666                 if (this_crtc->pipe == intel_crtc->pipe)
3667                         continue;
3668
3669                 if (!intel_crtc->active)
3670                         continue;
3671
3672                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3673                                                 &params, config,
3674                                                 &r->ddb, &pipe_wm);
3675
3676                 /*
3677                  * If we end up re-computing the other pipe WM values, it's
3678                  * because it was really needed, so we expect the WM values to
3679                  * be different.
3680                  */
3681                 WARN_ON(!wm_changed);
3682
3683                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3684                 r->dirty[intel_crtc->pipe] = true;
3685         }
3686 }
3687
3688 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3689 {
3690         watermarks->wm_linetime[pipe] = 0;
3691         memset(watermarks->plane[pipe], 0,
3692                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3693         memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
3694         memset(watermarks->plane_trans[pipe],
3695                0, sizeof(uint32_t) * I915_MAX_PLANES);
3696         watermarks->cursor_trans[pipe] = 0;
3697
3698         /* Clear ddb entries for pipe */
3699         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3700         memset(&watermarks->ddb.plane[pipe], 0,
3701                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3702         memset(&watermarks->ddb.y_plane[pipe], 0,
3703                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3704         memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
3705
3706 }
3707
3708 static void skl_update_wm(struct drm_crtc *crtc)
3709 {
3710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3711         struct drm_device *dev = crtc->dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         struct skl_pipe_wm_parameters params = {};
3714         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3715         struct skl_pipe_wm pipe_wm = {};
3716         struct intel_wm_config config = {};
3717
3718
3719         /* Clear all dirty flags */
3720         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3721
3722         skl_clear_wm(results, intel_crtc->pipe);
3723
3724         skl_compute_wm_global_parameters(dev, &config);
3725
3726         if (!skl_update_pipe_wm(crtc, &params, &config,
3727                                 &results->ddb, &pipe_wm))
3728                 return;
3729
3730         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3731         results->dirty[intel_crtc->pipe] = true;
3732
3733         skl_update_other_pipe_wm(dev, crtc, &config, results);
3734         skl_write_wm_values(dev_priv, results);
3735         skl_flush_wm_values(dev_priv, results);
3736
3737         /* store the new configuration */
3738         dev_priv->wm.skl_hw = *results;
3739 }
3740
3741 static void
3742 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3743                      uint32_t sprite_width, uint32_t sprite_height,
3744                      int pixel_size, bool enabled, bool scaled)
3745 {
3746         struct intel_plane *intel_plane = to_intel_plane(plane);
3747         struct drm_framebuffer *fb = plane->state->fb;
3748
3749         intel_plane->wm.enabled = enabled;
3750         intel_plane->wm.scaled = scaled;
3751         intel_plane->wm.horiz_pixels = sprite_width;
3752         intel_plane->wm.vert_pixels = sprite_height;
3753         intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3754
3755         /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3756         intel_plane->wm.bytes_per_pixel =
3757                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3758                 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3759         intel_plane->wm.y_bytes_per_pixel =
3760                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3761                 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3762
3763         /*
3764          * Framebuffer can be NULL on plane disable, but it does not
3765          * matter for watermarks if we assume no tiling in that case.
3766          */
3767         if (fb)
3768                 intel_plane->wm.tiling = fb->modifier[0];
3769         intel_plane->wm.rotation = plane->state->rotation;
3770
3771         skl_update_wm(crtc);
3772 }
3773
3774 static void ilk_update_wm(struct drm_crtc *crtc)
3775 {
3776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777         struct drm_device *dev = crtc->dev;
3778         struct drm_i915_private *dev_priv = dev->dev_private;
3779         struct ilk_wm_maximums max;
3780         struct ilk_pipe_wm_parameters params = {};
3781         struct ilk_wm_values results = {};
3782         enum intel_ddb_partitioning partitioning;
3783         struct intel_pipe_wm pipe_wm = {};
3784         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3785         struct intel_wm_config config = {};
3786
3787         ilk_compute_wm_parameters(crtc, &params);
3788
3789         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3790
3791         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3792                 return;
3793
3794         intel_crtc->wm.active = pipe_wm;
3795
3796         ilk_compute_wm_config(dev, &config);
3797
3798         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3799         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3800
3801         /* 5/6 split only in single pipe config on IVB+ */
3802         if (INTEL_INFO(dev)->gen >= 7 &&
3803             config.num_pipes_active == 1 && config.sprites_enabled) {
3804                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3805                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3806
3807                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3808         } else {
3809                 best_lp_wm = &lp_wm_1_2;
3810         }
3811
3812         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3813                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3814
3815         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3816
3817         ilk_write_wm_values(dev_priv, &results);
3818 }
3819
3820 static void
3821 ilk_update_sprite_wm(struct drm_plane *plane,
3822                      struct drm_crtc *crtc,
3823                      uint32_t sprite_width, uint32_t sprite_height,
3824                      int pixel_size, bool enabled, bool scaled)
3825 {
3826         struct drm_device *dev = plane->dev;
3827         struct intel_plane *intel_plane = to_intel_plane(plane);
3828
3829         intel_plane->wm.enabled = enabled;
3830         intel_plane->wm.scaled = scaled;
3831         intel_plane->wm.horiz_pixels = sprite_width;
3832         intel_plane->wm.vert_pixels = sprite_width;
3833         intel_plane->wm.bytes_per_pixel = pixel_size;
3834
3835         /*
3836          * IVB workaround: must disable low power watermarks for at least
3837          * one frame before enabling scaling.  LP watermarks can be re-enabled
3838          * when scaling is disabled.
3839          *
3840          * WaCxSRDisabledForSpriteScaling:ivb
3841          */
3842         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3843                 intel_wait_for_vblank(dev, intel_plane->pipe);
3844
3845         ilk_update_wm(crtc);
3846 }
3847
3848 static void skl_pipe_wm_active_state(uint32_t val,
3849                                      struct skl_pipe_wm *active,
3850                                      bool is_transwm,
3851                                      bool is_cursor,
3852                                      int i,
3853                                      int level)
3854 {
3855         bool is_enabled = (val & PLANE_WM_EN) != 0;
3856
3857         if (!is_transwm) {
3858                 if (!is_cursor) {
3859                         active->wm[level].plane_en[i] = is_enabled;
3860                         active->wm[level].plane_res_b[i] =
3861                                         val & PLANE_WM_BLOCKS_MASK;
3862                         active->wm[level].plane_res_l[i] =
3863                                         (val >> PLANE_WM_LINES_SHIFT) &
3864                                                 PLANE_WM_LINES_MASK;
3865                 } else {
3866                         active->wm[level].cursor_en = is_enabled;
3867                         active->wm[level].cursor_res_b =
3868                                         val & PLANE_WM_BLOCKS_MASK;
3869                         active->wm[level].cursor_res_l =
3870                                         (val >> PLANE_WM_LINES_SHIFT) &
3871                                                 PLANE_WM_LINES_MASK;
3872                 }
3873         } else {
3874                 if (!is_cursor) {
3875                         active->trans_wm.plane_en[i] = is_enabled;
3876                         active->trans_wm.plane_res_b[i] =
3877                                         val & PLANE_WM_BLOCKS_MASK;
3878                         active->trans_wm.plane_res_l[i] =
3879                                         (val >> PLANE_WM_LINES_SHIFT) &
3880                                                 PLANE_WM_LINES_MASK;
3881                 } else {
3882                         active->trans_wm.cursor_en = is_enabled;
3883                         active->trans_wm.cursor_res_b =
3884                                         val & PLANE_WM_BLOCKS_MASK;
3885                         active->trans_wm.cursor_res_l =
3886                                         (val >> PLANE_WM_LINES_SHIFT) &
3887                                                 PLANE_WM_LINES_MASK;
3888                 }
3889         }
3890 }
3891
3892 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3893 {
3894         struct drm_device *dev = crtc->dev;
3895         struct drm_i915_private *dev_priv = dev->dev_private;
3896         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3898         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3899         enum pipe pipe = intel_crtc->pipe;
3900         int level, i, max_level;
3901         uint32_t temp;
3902
3903         max_level = ilk_wm_max_level(dev);
3904
3905         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3906
3907         for (level = 0; level <= max_level; level++) {
3908                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3909                         hw->plane[pipe][i][level] =
3910                                         I915_READ(PLANE_WM(pipe, i, level));
3911                 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3912         }
3913
3914         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3915                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3916         hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3917
3918         if (!intel_crtc->active)
3919                 return;
3920
3921         hw->dirty[pipe] = true;
3922
3923         active->linetime = hw->wm_linetime[pipe];
3924
3925         for (level = 0; level <= max_level; level++) {
3926                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3927                         temp = hw->plane[pipe][i][level];
3928                         skl_pipe_wm_active_state(temp, active, false,
3929                                                 false, i, level);
3930                 }
3931                 temp = hw->cursor[pipe][level];
3932                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3933         }
3934
3935         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3936                 temp = hw->plane_trans[pipe][i];
3937                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3938         }
3939
3940         temp = hw->cursor_trans[pipe];
3941         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3942 }
3943
3944 void skl_wm_get_hw_state(struct drm_device *dev)
3945 {
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3948         struct drm_crtc *crtc;
3949
3950         skl_ddb_get_hw_state(dev_priv, ddb);
3951         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3952                 skl_pipe_wm_get_hw_state(crtc);
3953 }
3954
3955 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3956 {
3957         struct drm_device *dev = crtc->dev;
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3962         enum pipe pipe = intel_crtc->pipe;
3963         static const unsigned int wm0_pipe_reg[] = {
3964                 [PIPE_A] = WM0_PIPEA_ILK,
3965                 [PIPE_B] = WM0_PIPEB_ILK,
3966                 [PIPE_C] = WM0_PIPEC_IVB,
3967         };
3968
3969         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3970         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3971                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3972
3973         active->pipe_enabled = intel_crtc->active;
3974
3975         if (active->pipe_enabled) {
3976                 u32 tmp = hw->wm_pipe[pipe];
3977
3978                 /*
3979                  * For active pipes LP0 watermark is marked as
3980                  * enabled, and LP1+ watermaks as disabled since
3981                  * we can't really reverse compute them in case
3982                  * multiple pipes are active.
3983                  */
3984                 active->wm[0].enable = true;
3985                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3986                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3987                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3988                 active->linetime = hw->wm_linetime[pipe];
3989         } else {
3990                 int level, max_level = ilk_wm_max_level(dev);
3991
3992                 /*
3993                  * For inactive pipes, all watermark levels
3994                  * should be marked as enabled but zeroed,
3995                  * which is what we'd compute them to.
3996                  */
3997                 for (level = 0; level <= max_level; level++)
3998                         active->wm[level].enable = true;
3999         }
4000 }
4001
4002 #define _FW_WM(value, plane) \
4003         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4004 #define _FW_WM_VLV(value, plane) \
4005         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4006
4007 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4008                                struct vlv_wm_values *wm)
4009 {
4010         enum pipe pipe;
4011         uint32_t tmp;
4012
4013         for_each_pipe(dev_priv, pipe) {
4014                 tmp = I915_READ(VLV_DDL(pipe));
4015
4016                 wm->ddl[pipe].primary =
4017                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4018                 wm->ddl[pipe].cursor =
4019                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4020                 wm->ddl[pipe].sprite[0] =
4021                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4022                 wm->ddl[pipe].sprite[1] =
4023                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4024         }
4025
4026         tmp = I915_READ(DSPFW1);
4027         wm->sr.plane = _FW_WM(tmp, SR);
4028         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4029         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4030         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4031
4032         tmp = I915_READ(DSPFW2);
4033         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4034         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4035         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4036
4037         tmp = I915_READ(DSPFW3);
4038         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4039
4040         if (IS_CHERRYVIEW(dev_priv)) {
4041                 tmp = I915_READ(DSPFW7_CHV);
4042                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4043                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4044
4045                 tmp = I915_READ(DSPFW8_CHV);
4046                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4047                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4048
4049                 tmp = I915_READ(DSPFW9_CHV);
4050                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4051                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4052
4053                 tmp = I915_READ(DSPHOWM);
4054                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4055                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4056                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4057                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4058                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4059                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4060                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4061                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4062                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4063                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4064         } else {
4065                 tmp = I915_READ(DSPFW7);
4066                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4067                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4068
4069                 tmp = I915_READ(DSPHOWM);
4070                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4071                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4072                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4073                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4074                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4075                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4076                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4077         }
4078 }
4079
4080 #undef _FW_WM
4081 #undef _FW_WM_VLV
4082
4083 void vlv_wm_get_hw_state(struct drm_device *dev)
4084 {
4085         struct drm_i915_private *dev_priv = to_i915(dev);
4086         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4087         struct intel_plane *plane;
4088         enum pipe pipe;
4089         u32 val;
4090
4091         vlv_read_wm_values(dev_priv, wm);
4092
4093         for_each_intel_plane(dev, plane) {
4094                 switch (plane->base.type) {
4095                         int sprite;
4096                 case DRM_PLANE_TYPE_CURSOR:
4097                         plane->wm.fifo_size = 63;
4098                         break;
4099                 case DRM_PLANE_TYPE_PRIMARY:
4100                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4101                         break;
4102                 case DRM_PLANE_TYPE_OVERLAY:
4103                         sprite = plane->plane;
4104                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4105                         break;
4106                 }
4107         }
4108
4109         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4110         wm->level = VLV_WM_LEVEL_PM2;
4111
4112         if (IS_CHERRYVIEW(dev_priv)) {
4113                 mutex_lock(&dev_priv->rps.hw_lock);
4114
4115                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4116                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4117                         wm->level = VLV_WM_LEVEL_PM5;
4118
4119                 /*
4120                  * If DDR DVFS is disabled in the BIOS, Punit
4121                  * will never ack the request. So if that happens
4122                  * assume we don't have to enable/disable DDR DVFS
4123                  * dynamically. To test that just set the REQ_ACK
4124                  * bit to poke the Punit, but don't change the
4125                  * HIGH/LOW bits so that we don't actually change
4126                  * the current state.
4127                  */
4128                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4129                 val |= FORCE_DDR_FREQ_REQ_ACK;
4130                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4131
4132                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4133                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4134                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4135                                       "assuming DDR DVFS is disabled\n");
4136                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4137                 } else {
4138                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4139                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4140                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4141                 }
4142
4143                 mutex_unlock(&dev_priv->rps.hw_lock);
4144         }
4145
4146         for_each_pipe(dev_priv, pipe)
4147                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4148                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4149                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4150
4151         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4152                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4153 }
4154
4155 void ilk_wm_get_hw_state(struct drm_device *dev)
4156 {
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4159         struct drm_crtc *crtc;
4160
4161         for_each_crtc(dev, crtc)
4162                 ilk_pipe_wm_get_hw_state(crtc);
4163
4164         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4165         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4166         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4167
4168         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4169         if (INTEL_INFO(dev)->gen >= 7) {
4170                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4171                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4172         }
4173
4174         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4175                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4176                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4177         else if (IS_IVYBRIDGE(dev))
4178                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4179                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4180
4181         hw->enable_fbc_wm =
4182                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4183 }
4184
4185 /**
4186  * intel_update_watermarks - update FIFO watermark values based on current modes
4187  *
4188  * Calculate watermark values for the various WM regs based on current mode
4189  * and plane configuration.
4190  *
4191  * There are several cases to deal with here:
4192  *   - normal (i.e. non-self-refresh)
4193  *   - self-refresh (SR) mode
4194  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4195  *   - lines are small relative to FIFO size (buffer can hold more than 2
4196  *     lines), so need to account for TLB latency
4197  *
4198  *   The normal calculation is:
4199  *     watermark = dotclock * bytes per pixel * latency
4200  *   where latency is platform & configuration dependent (we assume pessimal
4201  *   values here).
4202  *
4203  *   The SR calculation is:
4204  *     watermark = (trunc(latency/line time)+1) * surface width *
4205  *       bytes per pixel
4206  *   where
4207  *     line time = htotal / dotclock
4208  *     surface width = hdisplay for normal plane and 64 for cursor
4209  *   and latency is assumed to be high, as above.
4210  *
4211  * The final value programmed to the register should always be rounded up,
4212  * and include an extra 2 entries to account for clock crossings.
4213  *
4214  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4215  * to set the non-SR watermarks to 8.
4216  */
4217 void intel_update_watermarks(struct drm_crtc *crtc)
4218 {
4219         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4220
4221         if (dev_priv->display.update_wm)
4222                 dev_priv->display.update_wm(crtc);
4223 }
4224
4225 void intel_update_sprite_watermarks(struct drm_plane *plane,
4226                                     struct drm_crtc *crtc,
4227                                     uint32_t sprite_width,
4228                                     uint32_t sprite_height,
4229                                     int pixel_size,
4230                                     bool enabled, bool scaled)
4231 {
4232         struct drm_i915_private *dev_priv = plane->dev->dev_private;
4233
4234         if (dev_priv->display.update_sprite_wm)
4235                 dev_priv->display.update_sprite_wm(plane, crtc,
4236                                                    sprite_width, sprite_height,
4237                                                    pixel_size, enabled, scaled);
4238 }
4239
4240 /**
4241  * Lock protecting IPS related data structures
4242  */
4243 DEFINE_SPINLOCK(mchdev_lock);
4244
4245 /* Global for IPS driver to get at the current i915 device. Protected by
4246  * mchdev_lock. */
4247 static struct drm_i915_private *i915_mch_dev;
4248
4249 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4250 {
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         u16 rgvswctl;
4253
4254         assert_spin_locked(&mchdev_lock);
4255
4256         rgvswctl = I915_READ16(MEMSWCTL);
4257         if (rgvswctl & MEMCTL_CMD_STS) {
4258                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4259                 return false; /* still busy with another command */
4260         }
4261
4262         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4263                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4264         I915_WRITE16(MEMSWCTL, rgvswctl);
4265         POSTING_READ16(MEMSWCTL);
4266
4267         rgvswctl |= MEMCTL_CMD_STS;
4268         I915_WRITE16(MEMSWCTL, rgvswctl);
4269
4270         return true;
4271 }
4272
4273 static void ironlake_enable_drps(struct drm_device *dev)
4274 {
4275         struct drm_i915_private *dev_priv = dev->dev_private;
4276         u32 rgvmodectl = I915_READ(MEMMODECTL);
4277         u8 fmax, fmin, fstart, vstart;
4278
4279         spin_lock_irq(&mchdev_lock);
4280
4281         /* Enable temp reporting */
4282         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4283         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4284
4285         /* 100ms RC evaluation intervals */
4286         I915_WRITE(RCUPEI, 100000);
4287         I915_WRITE(RCDNEI, 100000);
4288
4289         /* Set max/min thresholds to 90ms and 80ms respectively */
4290         I915_WRITE(RCBMAXAVG, 90000);
4291         I915_WRITE(RCBMINAVG, 80000);
4292
4293         I915_WRITE(MEMIHYST, 1);
4294
4295         /* Set up min, max, and cur for interrupt handling */
4296         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4297         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4298         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4299                 MEMMODE_FSTART_SHIFT;
4300
4301         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4302                 PXVFREQ_PX_SHIFT;
4303
4304         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4305         dev_priv->ips.fstart = fstart;
4306
4307         dev_priv->ips.max_delay = fstart;
4308         dev_priv->ips.min_delay = fmin;
4309         dev_priv->ips.cur_delay = fstart;
4310
4311         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4312                          fmax, fmin, fstart);
4313
4314         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4315
4316         /*
4317          * Interrupts will be enabled in ironlake_irq_postinstall
4318          */
4319
4320         I915_WRITE(VIDSTART, vstart);
4321         POSTING_READ(VIDSTART);
4322
4323         rgvmodectl |= MEMMODE_SWMODE_EN;
4324         I915_WRITE(MEMMODECTL, rgvmodectl);
4325
4326         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4327                 DRM_ERROR("stuck trying to change perf mode\n");
4328         mdelay(1);
4329
4330         ironlake_set_drps(dev, fstart);
4331
4332         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4333                 I915_READ(DDREC) + I915_READ(CSIEC);
4334         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4335         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4336         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4337
4338         spin_unlock_irq(&mchdev_lock);
4339 }
4340
4341 static void ironlake_disable_drps(struct drm_device *dev)
4342 {
4343         struct drm_i915_private *dev_priv = dev->dev_private;
4344         u16 rgvswctl;
4345
4346         spin_lock_irq(&mchdev_lock);
4347
4348         rgvswctl = I915_READ16(MEMSWCTL);
4349
4350         /* Ack interrupts, disable EFC interrupt */
4351         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4352         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4353         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4354         I915_WRITE(DEIIR, DE_PCU_EVENT);
4355         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4356
4357         /* Go back to the starting frequency */
4358         ironlake_set_drps(dev, dev_priv->ips.fstart);
4359         mdelay(1);
4360         rgvswctl |= MEMCTL_CMD_STS;
4361         I915_WRITE(MEMSWCTL, rgvswctl);
4362         mdelay(1);
4363
4364         spin_unlock_irq(&mchdev_lock);
4365 }
4366
4367 /* There's a funny hw issue where the hw returns all 0 when reading from
4368  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4369  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4370  * all limits and the gpu stuck at whatever frequency it is at atm).
4371  */
4372 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4373 {
4374         u32 limits;
4375
4376         /* Only set the down limit when we've reached the lowest level to avoid
4377          * getting more interrupts, otherwise leave this clear. This prevents a
4378          * race in the hw when coming out of rc6: There's a tiny window where
4379          * the hw runs at the minimal clock before selecting the desired
4380          * frequency, if the down threshold expires in that window we will not
4381          * receive a down interrupt. */
4382         if (IS_GEN9(dev_priv->dev)) {
4383                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4384                 if (val <= dev_priv->rps.min_freq_softlimit)
4385                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4386         } else {
4387                 limits = dev_priv->rps.max_freq_softlimit << 24;
4388                 if (val <= dev_priv->rps.min_freq_softlimit)
4389                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4390         }
4391
4392         return limits;
4393 }
4394
4395 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4396 {
4397         int new_power;
4398         u32 threshold_up = 0, threshold_down = 0; /* in % */
4399         u32 ei_up = 0, ei_down = 0;
4400
4401         new_power = dev_priv->rps.power;
4402         switch (dev_priv->rps.power) {
4403         case LOW_POWER:
4404                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4405                         new_power = BETWEEN;
4406                 break;
4407
4408         case BETWEEN:
4409                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4410                         new_power = LOW_POWER;
4411                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4412                         new_power = HIGH_POWER;
4413                 break;
4414
4415         case HIGH_POWER:
4416                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4417                         new_power = BETWEEN;
4418                 break;
4419         }
4420         /* Max/min bins are special */
4421         if (val <= dev_priv->rps.min_freq_softlimit)
4422                 new_power = LOW_POWER;
4423         if (val >= dev_priv->rps.max_freq_softlimit)
4424                 new_power = HIGH_POWER;
4425         if (new_power == dev_priv->rps.power)
4426                 return;
4427
4428         /* Note the units here are not exactly 1us, but 1280ns. */
4429         switch (new_power) {
4430         case LOW_POWER:
4431                 /* Upclock if more than 95% busy over 16ms */
4432                 ei_up = 16000;
4433                 threshold_up = 95;
4434
4435                 /* Downclock if less than 85% busy over 32ms */
4436                 ei_down = 32000;
4437                 threshold_down = 85;
4438                 break;
4439
4440         case BETWEEN:
4441                 /* Upclock if more than 90% busy over 13ms */
4442                 ei_up = 13000;
4443                 threshold_up = 90;
4444
4445                 /* Downclock if less than 75% busy over 32ms */
4446                 ei_down = 32000;
4447                 threshold_down = 75;
4448                 break;
4449
4450         case HIGH_POWER:
4451                 /* Upclock if more than 85% busy over 10ms */
4452                 ei_up = 10000;
4453                 threshold_up = 85;
4454
4455                 /* Downclock if less than 60% busy over 32ms */
4456                 ei_down = 32000;
4457                 threshold_down = 60;
4458                 break;
4459         }
4460
4461         I915_WRITE(GEN6_RP_UP_EI,
4462                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4463         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4464                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4465
4466         I915_WRITE(GEN6_RP_DOWN_EI,
4467                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4468         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4469                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4470
4471          I915_WRITE(GEN6_RP_CONTROL,
4472                     GEN6_RP_MEDIA_TURBO |
4473                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4474                     GEN6_RP_MEDIA_IS_GFX |
4475                     GEN6_RP_ENABLE |
4476                     GEN6_RP_UP_BUSY_AVG |
4477                     GEN6_RP_DOWN_IDLE_AVG);
4478
4479         dev_priv->rps.power = new_power;
4480         dev_priv->rps.up_threshold = threshold_up;
4481         dev_priv->rps.down_threshold = threshold_down;
4482         dev_priv->rps.last_adj = 0;
4483 }
4484
4485 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4486 {
4487         u32 mask = 0;
4488
4489         if (val > dev_priv->rps.min_freq_softlimit)
4490                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4491         if (val < dev_priv->rps.max_freq_softlimit)
4492                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4493
4494         mask &= dev_priv->pm_rps_events;
4495
4496         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4497 }
4498
4499 /* gen6_set_rps is called to update the frequency request, but should also be
4500  * called when the range (min_delay and max_delay) is modified so that we can
4501  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4502 static void gen6_set_rps(struct drm_device *dev, u8 val)
4503 {
4504         struct drm_i915_private *dev_priv = dev->dev_private;
4505
4506         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4507         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4508                 return;
4509
4510         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4511         WARN_ON(val > dev_priv->rps.max_freq);
4512         WARN_ON(val < dev_priv->rps.min_freq);
4513
4514         /* min/max delay may still have been modified so be sure to
4515          * write the limits value.
4516          */
4517         if (val != dev_priv->rps.cur_freq) {
4518                 gen6_set_rps_thresholds(dev_priv, val);
4519
4520                 if (IS_GEN9(dev))
4521                         I915_WRITE(GEN6_RPNSWREQ,
4522                                    GEN9_FREQUENCY(val));
4523                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4524                         I915_WRITE(GEN6_RPNSWREQ,
4525                                    HSW_FREQUENCY(val));
4526                 else
4527                         I915_WRITE(GEN6_RPNSWREQ,
4528                                    GEN6_FREQUENCY(val) |
4529                                    GEN6_OFFSET(0) |
4530                                    GEN6_AGGRESSIVE_TURBO);
4531         }
4532
4533         /* Make sure we continue to get interrupts
4534          * until we hit the minimum or maximum frequencies.
4535          */
4536         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4537         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4538
4539         POSTING_READ(GEN6_RPNSWREQ);
4540
4541         dev_priv->rps.cur_freq = val;
4542         trace_intel_gpu_freq_change(val * 50);
4543 }
4544
4545 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4546 {
4547         struct drm_i915_private *dev_priv = dev->dev_private;
4548
4549         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4550         WARN_ON(val > dev_priv->rps.max_freq);
4551         WARN_ON(val < dev_priv->rps.min_freq);
4552
4553         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4554                       "Odd GPU freq value\n"))
4555                 val &= ~1;
4556
4557         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4558
4559         if (val != dev_priv->rps.cur_freq) {
4560                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4561                 if (!IS_CHERRYVIEW(dev_priv))
4562                         gen6_set_rps_thresholds(dev_priv, val);
4563         }
4564
4565         dev_priv->rps.cur_freq = val;
4566         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4567 }
4568
4569 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4570  *
4571  * * If Gfx is Idle, then
4572  * 1. Forcewake Media well.
4573  * 2. Request idle freq.
4574  * 3. Release Forcewake of Media well.
4575 */
4576 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4577 {
4578         u32 val = dev_priv->rps.idle_freq;
4579
4580         if (dev_priv->rps.cur_freq <= val)
4581                 return;
4582
4583         /* Wake up the media well, as that takes a lot less
4584          * power than the Render well. */
4585         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4586         valleyview_set_rps(dev_priv->dev, val);
4587         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4588 }
4589
4590 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4591 {
4592         mutex_lock(&dev_priv->rps.hw_lock);
4593         if (dev_priv->rps.enabled) {
4594                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4595                         gen6_rps_reset_ei(dev_priv);
4596                 I915_WRITE(GEN6_PMINTRMSK,
4597                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4598         }
4599         mutex_unlock(&dev_priv->rps.hw_lock);
4600 }
4601
4602 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4603 {
4604         struct drm_device *dev = dev_priv->dev;
4605
4606         mutex_lock(&dev_priv->rps.hw_lock);
4607         if (dev_priv->rps.enabled) {
4608                 if (IS_VALLEYVIEW(dev))
4609                         vlv_set_rps_idle(dev_priv);
4610                 else
4611                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4612                 dev_priv->rps.last_adj = 0;
4613                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4614         }
4615         mutex_unlock(&dev_priv->rps.hw_lock);
4616
4617         spin_lock(&dev_priv->rps.client_lock);
4618         while (!list_empty(&dev_priv->rps.clients))
4619                 list_del_init(dev_priv->rps.clients.next);
4620         spin_unlock(&dev_priv->rps.client_lock);
4621 }
4622
4623 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4624                     struct intel_rps_client *rps,
4625                     unsigned long submitted)
4626 {
4627         /* This is intentionally racy! We peek at the state here, then
4628          * validate inside the RPS worker.
4629          */
4630         if (!(dev_priv->mm.busy &&
4631               dev_priv->rps.enabled &&
4632               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4633                 return;
4634
4635         /* Force a RPS boost (and don't count it against the client) if
4636          * the GPU is severely congested.
4637          */
4638         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4639                 rps = NULL;
4640
4641         spin_lock(&dev_priv->rps.client_lock);
4642         if (rps == NULL || list_empty(&rps->link)) {
4643                 spin_lock_irq(&dev_priv->irq_lock);
4644                 if (dev_priv->rps.interrupts_enabled) {
4645                         dev_priv->rps.client_boost = true;
4646                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4647                 }
4648                 spin_unlock_irq(&dev_priv->irq_lock);
4649
4650                 if (rps != NULL) {
4651                         list_add(&rps->link, &dev_priv->rps.clients);
4652                         rps->boosts++;
4653                 } else
4654                         dev_priv->rps.boosts++;
4655         }
4656         spin_unlock(&dev_priv->rps.client_lock);
4657 }
4658
4659 void intel_set_rps(struct drm_device *dev, u8 val)
4660 {
4661         if (IS_VALLEYVIEW(dev))
4662                 valleyview_set_rps(dev, val);
4663         else
4664                 gen6_set_rps(dev, val);
4665 }
4666
4667 static void gen9_disable_rps(struct drm_device *dev)
4668 {
4669         struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671         I915_WRITE(GEN6_RC_CONTROL, 0);
4672         I915_WRITE(GEN9_PG_ENABLE, 0);
4673 }
4674
4675 static void gen6_disable_rps(struct drm_device *dev)
4676 {
4677         struct drm_i915_private *dev_priv = dev->dev_private;
4678
4679         I915_WRITE(GEN6_RC_CONTROL, 0);
4680         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4681 }
4682
4683 static void cherryview_disable_rps(struct drm_device *dev)
4684 {
4685         struct drm_i915_private *dev_priv = dev->dev_private;
4686
4687         I915_WRITE(GEN6_RC_CONTROL, 0);
4688 }
4689
4690 static void valleyview_disable_rps(struct drm_device *dev)
4691 {
4692         struct drm_i915_private *dev_priv = dev->dev_private;
4693
4694         /* we're doing forcewake before Disabling RC6,
4695          * This what the BIOS expects when going into suspend */
4696         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4697
4698         I915_WRITE(GEN6_RC_CONTROL, 0);
4699
4700         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4701 }
4702
4703 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4704 {
4705         if (IS_VALLEYVIEW(dev)) {
4706                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4707                         mode = GEN6_RC_CTL_RC6_ENABLE;
4708                 else
4709                         mode = 0;
4710         }
4711         if (HAS_RC6p(dev))
4712                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4713                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4714                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4715                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4716
4717         else
4718                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4719                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4720 }
4721
4722 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4723 {
4724         /* No RC6 before Ironlake and code is gone for ilk. */
4725         if (INTEL_INFO(dev)->gen < 6)
4726                 return 0;
4727
4728         /* Respect the kernel parameter if it is set */
4729         if (enable_rc6 >= 0) {
4730                 int mask;
4731
4732                 if (HAS_RC6p(dev))
4733                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4734                                INTEL_RC6pp_ENABLE;
4735                 else
4736                         mask = INTEL_RC6_ENABLE;
4737
4738                 if ((enable_rc6 & mask) != enable_rc6)
4739                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4740                                       enable_rc6 & mask, enable_rc6, mask);
4741
4742                 return enable_rc6 & mask;
4743         }
4744
4745         if (IS_IVYBRIDGE(dev))
4746                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4747
4748         return INTEL_RC6_ENABLE;
4749 }
4750
4751 int intel_enable_rc6(const struct drm_device *dev)
4752 {
4753         return i915.enable_rc6;
4754 }
4755
4756 static void gen6_init_rps_frequencies(struct drm_device *dev)
4757 {
4758         struct drm_i915_private *dev_priv = dev->dev_private;
4759         uint32_t rp_state_cap;
4760         u32 ddcc_status = 0;
4761         int ret;
4762
4763         /* All of these values are in units of 50MHz */
4764         dev_priv->rps.cur_freq          = 0;
4765         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4766         if (IS_BROXTON(dev)) {
4767                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4768                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4769                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4770                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4771         } else {
4772                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4773                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4774                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4775                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4776         }
4777
4778         /* hw_max = RP0 until we check for overclocking */
4779         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4780
4781         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4782         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4783                 ret = sandybridge_pcode_read(dev_priv,
4784                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4785                                         &ddcc_status);
4786                 if (0 == ret)
4787                         dev_priv->rps.efficient_freq =
4788                                 clamp_t(u8,
4789                                         ((ddcc_status >> 8) & 0xff),
4790                                         dev_priv->rps.min_freq,
4791                                         dev_priv->rps.max_freq);
4792         }
4793
4794         if (IS_SKYLAKE(dev)) {
4795                 /* Store the frequency values in 16.66 MHZ units, which is
4796                    the natural hardware unit for SKL */
4797                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4798                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4799                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4800                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4801                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4802         }
4803
4804         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4805
4806         /* Preserve min/max settings in case of re-init */
4807         if (dev_priv->rps.max_freq_softlimit == 0)
4808                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4809
4810         if (dev_priv->rps.min_freq_softlimit == 0) {
4811                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4812                         dev_priv->rps.min_freq_softlimit =
4813                                 max_t(int, dev_priv->rps.efficient_freq,
4814                                       intel_freq_opcode(dev_priv, 450));
4815                 else
4816                         dev_priv->rps.min_freq_softlimit =
4817                                 dev_priv->rps.min_freq;
4818         }
4819 }
4820
4821 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4822 static void gen9_enable_rps(struct drm_device *dev)
4823 {
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825
4826         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4827
4828         gen6_init_rps_frequencies(dev);
4829
4830         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4831         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4832                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4833                 return;
4834         }
4835
4836         /* Program defaults and thresholds for RPS*/
4837         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4838                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4839
4840         /* 1 second timeout*/
4841         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4842                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4843
4844         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4845
4846         /* Leaning on the below call to gen6_set_rps to program/setup the
4847          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4848          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4849         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4850         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4851
4852         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4853 }
4854
4855 static void gen9_enable_rc6(struct drm_device *dev)
4856 {
4857         struct drm_i915_private *dev_priv = dev->dev_private;
4858         struct intel_engine_cs *ring;
4859         uint32_t rc6_mask = 0;
4860         int unused;
4861
4862         /* 1a: Software RC state - RC0 */
4863         I915_WRITE(GEN6_RC_STATE, 0);
4864
4865         /* 1b: Get forcewake during program sequence. Although the driver
4866          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4867         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4868
4869         /* 2a: Disable RC states. */
4870         I915_WRITE(GEN6_RC_CONTROL, 0);
4871
4872         /* 2b: Program RC6 thresholds.*/
4873
4874         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4875         if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4876                                  (INTEL_REVID(dev) <= SKL_REVID_E0)))
4877                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4878         else
4879                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4880         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4881         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4882         for_each_ring(ring, dev_priv, unused)
4883                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4884
4885         if (HAS_GUC_UCODE(dev))
4886                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4887
4888         I915_WRITE(GEN6_RC_SLEEP, 0);
4889         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4890
4891         /* 2c: Program Coarse Power Gating Policies. */
4892         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4893         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4894
4895         /* 3a: Enable RC6 */
4896         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4897                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4898         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4899                         "on" : "off");
4900
4901         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4902             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
4903                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4904                            GEN7_RC_CTL_TO_MODE |
4905                            rc6_mask);
4906         else
4907                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4908                            GEN6_RC_CTL_EI_MODE(1) |
4909                            rc6_mask);
4910
4911         /*
4912          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4913          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4914          */
4915         if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4916             ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4917                 I915_WRITE(GEN9_PG_ENABLE, 0);
4918         else
4919                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4920                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4921
4922         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4923
4924 }
4925
4926 static void gen8_enable_rps(struct drm_device *dev)
4927 {
4928         struct drm_i915_private *dev_priv = dev->dev_private;
4929         struct intel_engine_cs *ring;
4930         uint32_t rc6_mask = 0;
4931         int unused;
4932
4933         /* 1a: Software RC state - RC0 */
4934         I915_WRITE(GEN6_RC_STATE, 0);
4935
4936         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4937          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4938         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4939
4940         /* 2a: Disable RC states. */
4941         I915_WRITE(GEN6_RC_CONTROL, 0);
4942
4943         /* Initialize rps frequencies */
4944         gen6_init_rps_frequencies(dev);
4945
4946         /* 2b: Program RC6 thresholds.*/
4947         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4948         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4949         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4950         for_each_ring(ring, dev_priv, unused)
4951                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4952         I915_WRITE(GEN6_RC_SLEEP, 0);
4953         if (IS_BROADWELL(dev))
4954                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4955         else
4956                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4957
4958         /* 3: Enable RC6 */
4959         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4960                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4961         intel_print_rc6_info(dev, rc6_mask);
4962         if (IS_BROADWELL(dev))
4963                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4964                                 GEN7_RC_CTL_TO_MODE |
4965                                 rc6_mask);
4966         else
4967                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4968                                 GEN6_RC_CTL_EI_MODE(1) |
4969                                 rc6_mask);
4970
4971         /* 4 Program defaults and thresholds for RPS*/
4972         I915_WRITE(GEN6_RPNSWREQ,
4973                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4974         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4975                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4976         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4977         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4978
4979         /* Docs recommend 900MHz, and 300 MHz respectively */
4980         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4981                    dev_priv->rps.max_freq_softlimit << 24 |
4982                    dev_priv->rps.min_freq_softlimit << 16);
4983
4984         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4985         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4986         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4987         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4988
4989         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4990
4991         /* 5: Enable RPS */
4992         I915_WRITE(GEN6_RP_CONTROL,
4993                    GEN6_RP_MEDIA_TURBO |
4994                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4995                    GEN6_RP_MEDIA_IS_GFX |
4996                    GEN6_RP_ENABLE |
4997                    GEN6_RP_UP_BUSY_AVG |
4998                    GEN6_RP_DOWN_IDLE_AVG);
4999
5000         /* 6: Ring frequency + overclocking (our driver does this later */
5001
5002         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5003         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5004
5005         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5006 }
5007
5008 static void gen6_enable_rps(struct drm_device *dev)
5009 {
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         struct intel_engine_cs *ring;
5012         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5013         u32 gtfifodbg;
5014         int rc6_mode;
5015         int i, ret;
5016
5017         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5018
5019         /* Here begins a magic sequence of register writes to enable
5020          * auto-downclocking.
5021          *
5022          * Perhaps there might be some value in exposing these to
5023          * userspace...
5024          */
5025         I915_WRITE(GEN6_RC_STATE, 0);
5026
5027         /* Clear the DBG now so we don't confuse earlier errors */
5028         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5029                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5030                 I915_WRITE(GTFIFODBG, gtfifodbg);
5031         }
5032
5033         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5034
5035         /* Initialize rps frequencies */
5036         gen6_init_rps_frequencies(dev);
5037
5038         /* disable the counters and set deterministic thresholds */
5039         I915_WRITE(GEN6_RC_CONTROL, 0);
5040
5041         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5042         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5043         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5044         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5045         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5046
5047         for_each_ring(ring, dev_priv, i)
5048                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5049
5050         I915_WRITE(GEN6_RC_SLEEP, 0);
5051         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5052         if (IS_IVYBRIDGE(dev))
5053                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5054         else
5055                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5056         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5057         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5058
5059         /* Check if we are enabling RC6 */
5060         rc6_mode = intel_enable_rc6(dev_priv->dev);
5061         if (rc6_mode & INTEL_RC6_ENABLE)
5062                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5063
5064         /* We don't use those on Haswell */
5065         if (!IS_HASWELL(dev)) {
5066                 if (rc6_mode & INTEL_RC6p_ENABLE)
5067                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5068
5069                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5070                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5071         }
5072
5073         intel_print_rc6_info(dev, rc6_mask);
5074
5075         I915_WRITE(GEN6_RC_CONTROL,
5076                    rc6_mask |
5077                    GEN6_RC_CTL_EI_MODE(1) |
5078                    GEN6_RC_CTL_HW_ENABLE);
5079
5080         /* Power down if completely idle for over 50ms */
5081         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5082         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5083
5084         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5085         if (ret)
5086                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5087
5088         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5089         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5090                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5091                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5092                                  (pcu_mbox & 0xff) * 50);
5093                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5094         }
5095
5096         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5097         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5098
5099         rc6vids = 0;
5100         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5101         if (IS_GEN6(dev) && ret) {
5102                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5103         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5104                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5105                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5106                 rc6vids &= 0xffff00;
5107                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5108                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5109                 if (ret)
5110                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5111         }
5112
5113         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5114 }
5115
5116 static void __gen6_update_ring_freq(struct drm_device *dev)
5117 {
5118         struct drm_i915_private *dev_priv = dev->dev_private;
5119         int min_freq = 15;
5120         unsigned int gpu_freq;
5121         unsigned int max_ia_freq, min_ring_freq;
5122         unsigned int max_gpu_freq, min_gpu_freq;
5123         int scaling_factor = 180;
5124         struct cpufreq_policy *policy;
5125
5126         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5127
5128         policy = cpufreq_cpu_get(0);
5129         if (policy) {
5130                 max_ia_freq = policy->cpuinfo.max_freq;
5131                 cpufreq_cpu_put(policy);
5132         } else {
5133                 /*
5134                  * Default to measured freq if none found, PCU will ensure we
5135                  * don't go over
5136                  */
5137                 max_ia_freq = tsc_khz;
5138         }
5139
5140         /* Convert from kHz to MHz */
5141         max_ia_freq /= 1000;
5142
5143         min_ring_freq = I915_READ(DCLK) & 0xf;
5144         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5145         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5146
5147         if (IS_SKYLAKE(dev)) {
5148                 /* Convert GT frequency to 50 HZ units */
5149                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5150                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5151         } else {
5152                 min_gpu_freq = dev_priv->rps.min_freq;
5153                 max_gpu_freq = dev_priv->rps.max_freq;
5154         }
5155
5156         /*
5157          * For each potential GPU frequency, load a ring frequency we'd like
5158          * to use for memory access.  We do this by specifying the IA frequency
5159          * the PCU should use as a reference to determine the ring frequency.
5160          */
5161         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5162                 int diff = max_gpu_freq - gpu_freq;
5163                 unsigned int ia_freq = 0, ring_freq = 0;
5164
5165                 if (IS_SKYLAKE(dev)) {
5166                         /*
5167                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5168                          * No floor required for ring frequency on SKL.
5169                          */
5170                         ring_freq = gpu_freq;
5171                 } else if (INTEL_INFO(dev)->gen >= 8) {
5172                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5173                         ring_freq = max(min_ring_freq, gpu_freq);
5174                 } else if (IS_HASWELL(dev)) {
5175                         ring_freq = mult_frac(gpu_freq, 5, 4);
5176                         ring_freq = max(min_ring_freq, ring_freq);
5177                         /* leave ia_freq as the default, chosen by cpufreq */
5178                 } else {
5179                         /* On older processors, there is no separate ring
5180                          * clock domain, so in order to boost the bandwidth
5181                          * of the ring, we need to upclock the CPU (ia_freq).
5182                          *
5183                          * For GPU frequencies less than 750MHz,
5184                          * just use the lowest ring freq.
5185                          */
5186                         if (gpu_freq < min_freq)
5187                                 ia_freq = 800;
5188                         else
5189                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5190                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5191                 }
5192
5193                 sandybridge_pcode_write(dev_priv,
5194                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5195                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5196                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5197                                         gpu_freq);
5198         }
5199 }
5200
5201 void gen6_update_ring_freq(struct drm_device *dev)
5202 {
5203         struct drm_i915_private *dev_priv = dev->dev_private;
5204
5205         if (!HAS_CORE_RING_FREQ(dev))
5206                 return;
5207
5208         mutex_lock(&dev_priv->rps.hw_lock);
5209         __gen6_update_ring_freq(dev);
5210         mutex_unlock(&dev_priv->rps.hw_lock);
5211 }
5212
5213 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5214 {
5215         struct drm_device *dev = dev_priv->dev;
5216         u32 val, rp0;
5217
5218         if (dev->pdev->revision >= 0x20) {
5219                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5220
5221                 switch (INTEL_INFO(dev)->eu_total) {
5222                 case 8:
5223                                 /* (2 * 4) config */
5224                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5225                                 break;
5226                 case 12:
5227                                 /* (2 * 6) config */
5228                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5229                                 break;
5230                 case 16:
5231                                 /* (2 * 8) config */
5232                 default:
5233                                 /* Setting (2 * 8) Min RP0 for any other combination */
5234                                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5235                                 break;
5236                 }
5237                 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5238         } else {
5239                 /* For pre-production hardware */
5240                 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5241                 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5242                        PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5243         }
5244         return rp0;
5245 }
5246
5247 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5248 {
5249         u32 val, rpe;
5250
5251         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5252         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5253
5254         return rpe;
5255 }
5256
5257 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5258 {
5259         struct drm_device *dev = dev_priv->dev;
5260         u32 val, rp1;
5261
5262         if (dev->pdev->revision >= 0x20) {
5263                 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5264                 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5265         } else {
5266                 /* For pre-production hardware */
5267                 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5268                 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5269                        PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5270         }
5271         return rp1;
5272 }
5273
5274 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5275 {
5276         u32 val, rp1;
5277
5278         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5279
5280         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5281
5282         return rp1;
5283 }
5284
5285 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5286 {
5287         u32 val, rp0;
5288
5289         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5290
5291         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5292         /* Clamp to max */
5293         rp0 = min_t(u32, rp0, 0xea);
5294
5295         return rp0;
5296 }
5297
5298 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5299 {
5300         u32 val, rpe;
5301
5302         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5303         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5304         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5305         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5306
5307         return rpe;
5308 }
5309
5310 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5311 {
5312         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5313 }
5314
5315 /* Check that the pctx buffer wasn't move under us. */
5316 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5317 {
5318         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5319
5320         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5321                              dev_priv->vlv_pctx->stolen->start);
5322 }
5323
5324
5325 /* Check that the pcbr address is not empty. */
5326 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5327 {
5328         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5329
5330         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5331 }
5332
5333 static void cherryview_setup_pctx(struct drm_device *dev)
5334 {
5335         struct drm_i915_private *dev_priv = dev->dev_private;
5336         unsigned long pctx_paddr, paddr;
5337         struct i915_gtt *gtt = &dev_priv->gtt;
5338         u32 pcbr;
5339         int pctx_size = 32*1024;
5340
5341         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5342
5343         pcbr = I915_READ(VLV_PCBR);
5344         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5345                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5346                 paddr = (dev_priv->mm.stolen_base +
5347                          (gtt->stolen_size - pctx_size));
5348
5349                 pctx_paddr = (paddr & (~4095));
5350                 I915_WRITE(VLV_PCBR, pctx_paddr);
5351         }
5352
5353         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5354 }
5355
5356 static void valleyview_setup_pctx(struct drm_device *dev)
5357 {
5358         struct drm_i915_private *dev_priv = dev->dev_private;
5359         struct drm_i915_gem_object *pctx;
5360         unsigned long pctx_paddr;
5361         u32 pcbr;
5362         int pctx_size = 24*1024;
5363
5364         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5365
5366         pcbr = I915_READ(VLV_PCBR);
5367         if (pcbr) {
5368                 /* BIOS set it up already, grab the pre-alloc'd space */
5369                 int pcbr_offset;
5370
5371                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5372                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5373                                                                       pcbr_offset,
5374                                                                       I915_GTT_OFFSET_NONE,
5375                                                                       pctx_size);
5376                 goto out;
5377         }
5378
5379         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5380
5381         /*
5382          * From the Gunit register HAS:
5383          * The Gfx driver is expected to program this register and ensure
5384          * proper allocation within Gfx stolen memory.  For example, this
5385          * register should be programmed such than the PCBR range does not
5386          * overlap with other ranges, such as the frame buffer, protected
5387          * memory, or any other relevant ranges.
5388          */
5389         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5390         if (!pctx) {
5391                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5392                 return;
5393         }
5394
5395         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5396         I915_WRITE(VLV_PCBR, pctx_paddr);
5397
5398 out:
5399         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5400         dev_priv->vlv_pctx = pctx;
5401 }
5402
5403 static void valleyview_cleanup_pctx(struct drm_device *dev)
5404 {
5405         struct drm_i915_private *dev_priv = dev->dev_private;
5406
5407         if (WARN_ON(!dev_priv->vlv_pctx))
5408                 return;
5409
5410         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5411         dev_priv->vlv_pctx = NULL;
5412 }
5413
5414 static void valleyview_init_gt_powersave(struct drm_device *dev)
5415 {
5416         struct drm_i915_private *dev_priv = dev->dev_private;
5417         u32 val;
5418
5419         valleyview_setup_pctx(dev);
5420
5421         mutex_lock(&dev_priv->rps.hw_lock);
5422
5423         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5424         switch ((val >> 6) & 3) {
5425         case 0:
5426         case 1:
5427                 dev_priv->mem_freq = 800;
5428                 break;
5429         case 2:
5430                 dev_priv->mem_freq = 1066;
5431                 break;
5432         case 3:
5433                 dev_priv->mem_freq = 1333;
5434                 break;
5435         }
5436         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5437
5438         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5439         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5440         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5441                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5442                          dev_priv->rps.max_freq);
5443
5444         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5445         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5446                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5447                          dev_priv->rps.efficient_freq);
5448
5449         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5450         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5451                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5452                          dev_priv->rps.rp1_freq);
5453
5454         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5455         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5456                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5457                          dev_priv->rps.min_freq);
5458
5459         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5460
5461         /* Preserve min/max settings in case of re-init */
5462         if (dev_priv->rps.max_freq_softlimit == 0)
5463                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5464
5465         if (dev_priv->rps.min_freq_softlimit == 0)
5466                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5467
5468         mutex_unlock(&dev_priv->rps.hw_lock);
5469 }
5470
5471 static void cherryview_init_gt_powersave(struct drm_device *dev)
5472 {
5473         struct drm_i915_private *dev_priv = dev->dev_private;
5474         u32 val;
5475
5476         cherryview_setup_pctx(dev);
5477
5478         mutex_lock(&dev_priv->rps.hw_lock);
5479
5480         mutex_lock(&dev_priv->sb_lock);
5481         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5482         mutex_unlock(&dev_priv->sb_lock);
5483
5484         switch ((val >> 2) & 0x7) {
5485         case 0:
5486         case 1:
5487                 dev_priv->rps.cz_freq = 200;
5488                 dev_priv->mem_freq = 1600;
5489                 break;
5490         case 2:
5491                 dev_priv->rps.cz_freq = 267;
5492                 dev_priv->mem_freq = 1600;
5493                 break;
5494         case 3:
5495                 dev_priv->rps.cz_freq = 333;
5496                 dev_priv->mem_freq = 2000;
5497                 break;
5498         case 4:
5499                 dev_priv->rps.cz_freq = 320;
5500                 dev_priv->mem_freq = 1600;
5501                 break;
5502         case 5:
5503                 dev_priv->rps.cz_freq = 400;
5504                 dev_priv->mem_freq = 1600;
5505                 break;
5506         }
5507         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5508
5509         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5510         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5511         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5512                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5513                          dev_priv->rps.max_freq);
5514
5515         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5516         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5517                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5518                          dev_priv->rps.efficient_freq);
5519
5520         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5521         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5522                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5523                          dev_priv->rps.rp1_freq);
5524
5525         /* PUnit validated range is only [RPe, RP0] */
5526         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5527         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5528                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5529                          dev_priv->rps.min_freq);
5530
5531         WARN_ONCE((dev_priv->rps.max_freq |
5532                    dev_priv->rps.efficient_freq |
5533                    dev_priv->rps.rp1_freq |
5534                    dev_priv->rps.min_freq) & 1,
5535                   "Odd GPU freq values\n");
5536
5537         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5538
5539         /* Preserve min/max settings in case of re-init */
5540         if (dev_priv->rps.max_freq_softlimit == 0)
5541                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5542
5543         if (dev_priv->rps.min_freq_softlimit == 0)
5544                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5545
5546         mutex_unlock(&dev_priv->rps.hw_lock);
5547 }
5548
5549 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5550 {
5551         valleyview_cleanup_pctx(dev);
5552 }
5553
5554 static void cherryview_enable_rps(struct drm_device *dev)
5555 {
5556         struct drm_i915_private *dev_priv = dev->dev_private;
5557         struct intel_engine_cs *ring;
5558         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5559         int i;
5560
5561         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5562
5563         gtfifodbg = I915_READ(GTFIFODBG);
5564         if (gtfifodbg) {
5565                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5566                                  gtfifodbg);
5567                 I915_WRITE(GTFIFODBG, gtfifodbg);
5568         }
5569
5570         cherryview_check_pctx(dev_priv);
5571
5572         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5573          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5574         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5575
5576         /*  Disable RC states. */
5577         I915_WRITE(GEN6_RC_CONTROL, 0);
5578
5579         /* 2a: Program RC6 thresholds.*/
5580         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5581         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5582         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5583
5584         for_each_ring(ring, dev_priv, i)
5585                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5586         I915_WRITE(GEN6_RC_SLEEP, 0);
5587
5588         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5589         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5590
5591         /* allows RC6 residency counter to work */
5592         I915_WRITE(VLV_COUNTER_CONTROL,
5593                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5594                                       VLV_MEDIA_RC6_COUNT_EN |
5595                                       VLV_RENDER_RC6_COUNT_EN));
5596
5597         /* For now we assume BIOS is allocating and populating the PCBR  */
5598         pcbr = I915_READ(VLV_PCBR);
5599
5600         /* 3: Enable RC6 */
5601         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5602                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5603                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5604
5605         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5606
5607         /* 4 Program defaults and thresholds for RPS*/
5608         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5609         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5610         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5611         I915_WRITE(GEN6_RP_UP_EI, 66000);
5612         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5613
5614         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5615
5616         /* 5: Enable RPS */
5617         I915_WRITE(GEN6_RP_CONTROL,
5618                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5619                    GEN6_RP_MEDIA_IS_GFX |
5620                    GEN6_RP_ENABLE |
5621                    GEN6_RP_UP_BUSY_AVG |
5622                    GEN6_RP_DOWN_IDLE_AVG);
5623
5624         /* Setting Fixed Bias */
5625         val = VLV_OVERRIDE_EN |
5626                   VLV_SOC_TDP_EN |
5627                   CHV_BIAS_CPU_50_SOC_50;
5628         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5629
5630         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5631
5632         /* RPS code assumes GPLL is used */
5633         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5634
5635         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5636         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5637
5638         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5639         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5640                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5641                          dev_priv->rps.cur_freq);
5642
5643         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5644                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5645                          dev_priv->rps.efficient_freq);
5646
5647         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5648
5649         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5650 }
5651
5652 static void valleyview_enable_rps(struct drm_device *dev)
5653 {
5654         struct drm_i915_private *dev_priv = dev->dev_private;
5655         struct intel_engine_cs *ring;
5656         u32 gtfifodbg, val, rc6_mode = 0;
5657         int i;
5658
5659         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5660
5661         valleyview_check_pctx(dev_priv);
5662
5663         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5664                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5665                                  gtfifodbg);
5666                 I915_WRITE(GTFIFODBG, gtfifodbg);
5667         }
5668
5669         /* If VLV, Forcewake all wells, else re-direct to regular path */
5670         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5671
5672         /*  Disable RC states. */
5673         I915_WRITE(GEN6_RC_CONTROL, 0);
5674
5675         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5676         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5677         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5678         I915_WRITE(GEN6_RP_UP_EI, 66000);
5679         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5680
5681         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5682
5683         I915_WRITE(GEN6_RP_CONTROL,
5684                    GEN6_RP_MEDIA_TURBO |
5685                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5686                    GEN6_RP_MEDIA_IS_GFX |
5687                    GEN6_RP_ENABLE |
5688                    GEN6_RP_UP_BUSY_AVG |
5689                    GEN6_RP_DOWN_IDLE_CONT);
5690
5691         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5692         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5693         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5694
5695         for_each_ring(ring, dev_priv, i)
5696                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5697
5698         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5699
5700         /* allows RC6 residency counter to work */
5701         I915_WRITE(VLV_COUNTER_CONTROL,
5702                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5703                                       VLV_RENDER_RC0_COUNT_EN |
5704                                       VLV_MEDIA_RC6_COUNT_EN |
5705                                       VLV_RENDER_RC6_COUNT_EN));
5706
5707         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5708                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5709
5710         intel_print_rc6_info(dev, rc6_mode);
5711
5712         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5713
5714         /* Setting Fixed Bias */
5715         val = VLV_OVERRIDE_EN |
5716                   VLV_SOC_TDP_EN |
5717                   VLV_BIAS_CPU_125_SOC_875;
5718         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5719
5720         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5721
5722         /* RPS code assumes GPLL is used */
5723         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5724
5725         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5726         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5727
5728         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5729         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5730                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5731                          dev_priv->rps.cur_freq);
5732
5733         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5734                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5735                          dev_priv->rps.efficient_freq);
5736
5737         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5738
5739         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5740 }
5741
5742 static unsigned long intel_pxfreq(u32 vidfreq)
5743 {
5744         unsigned long freq;
5745         int div = (vidfreq & 0x3f0000) >> 16;
5746         int post = (vidfreq & 0x3000) >> 12;
5747         int pre = (vidfreq & 0x7);
5748
5749         if (!pre)
5750                 return 0;
5751
5752         freq = ((div * 133333) / ((1<<post) * pre));
5753
5754         return freq;
5755 }
5756
5757 static const struct cparams {
5758         u16 i;
5759         u16 t;
5760         u16 m;
5761         u16 c;
5762 } cparams[] = {
5763         { 1, 1333, 301, 28664 },
5764         { 1, 1066, 294, 24460 },
5765         { 1, 800, 294, 25192 },
5766         { 0, 1333, 276, 27605 },
5767         { 0, 1066, 276, 27605 },
5768         { 0, 800, 231, 23784 },
5769 };
5770
5771 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5772 {
5773         u64 total_count, diff, ret;
5774         u32 count1, count2, count3, m = 0, c = 0;
5775         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5776         int i;
5777
5778         assert_spin_locked(&mchdev_lock);
5779
5780         diff1 = now - dev_priv->ips.last_time1;
5781
5782         /* Prevent division-by-zero if we are asking too fast.
5783          * Also, we don't get interesting results if we are polling
5784          * faster than once in 10ms, so just return the saved value
5785          * in such cases.
5786          */
5787         if (diff1 <= 10)
5788                 return dev_priv->ips.chipset_power;
5789
5790         count1 = I915_READ(DMIEC);
5791         count2 = I915_READ(DDREC);
5792         count3 = I915_READ(CSIEC);
5793
5794         total_count = count1 + count2 + count3;
5795
5796         /* FIXME: handle per-counter overflow */
5797         if (total_count < dev_priv->ips.last_count1) {
5798                 diff = ~0UL - dev_priv->ips.last_count1;
5799                 diff += total_count;
5800         } else {
5801                 diff = total_count - dev_priv->ips.last_count1;
5802         }
5803
5804         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5805                 if (cparams[i].i == dev_priv->ips.c_m &&
5806                     cparams[i].t == dev_priv->ips.r_t) {
5807                         m = cparams[i].m;
5808                         c = cparams[i].c;
5809                         break;
5810                 }
5811         }
5812
5813         diff = div_u64(diff, diff1);
5814         ret = ((m * diff) + c);
5815         ret = div_u64(ret, 10);
5816
5817         dev_priv->ips.last_count1 = total_count;
5818         dev_priv->ips.last_time1 = now;
5819
5820         dev_priv->ips.chipset_power = ret;
5821
5822         return ret;
5823 }
5824
5825 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5826 {
5827         struct drm_device *dev = dev_priv->dev;
5828         unsigned long val;
5829
5830         if (INTEL_INFO(dev)->gen != 5)
5831                 return 0;
5832
5833         spin_lock_irq(&mchdev_lock);
5834
5835         val = __i915_chipset_val(dev_priv);
5836
5837         spin_unlock_irq(&mchdev_lock);
5838
5839         return val;
5840 }
5841
5842 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5843 {
5844         unsigned long m, x, b;
5845         u32 tsfs;
5846
5847         tsfs = I915_READ(TSFS);
5848
5849         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5850         x = I915_READ8(TR1);
5851
5852         b = tsfs & TSFS_INTR_MASK;
5853
5854         return ((m * x) / 127) - b;
5855 }
5856
5857 static int _pxvid_to_vd(u8 pxvid)
5858 {
5859         if (pxvid == 0)
5860                 return 0;
5861
5862         if (pxvid >= 8 && pxvid < 31)
5863                 pxvid = 31;
5864
5865         return (pxvid + 2) * 125;
5866 }
5867
5868 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5869 {
5870         struct drm_device *dev = dev_priv->dev;
5871         const int vd = _pxvid_to_vd(pxvid);
5872         const int vm = vd - 1125;
5873
5874         if (INTEL_INFO(dev)->is_mobile)
5875                 return vm > 0 ? vm : 0;
5876
5877         return vd;
5878 }
5879
5880 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5881 {
5882         u64 now, diff, diffms;
5883         u32 count;
5884
5885         assert_spin_locked(&mchdev_lock);
5886
5887         now = ktime_get_raw_ns();
5888         diffms = now - dev_priv->ips.last_time2;
5889         do_div(diffms, NSEC_PER_MSEC);
5890
5891         /* Don't divide by 0 */
5892         if (!diffms)
5893                 return;
5894
5895         count = I915_READ(GFXEC);
5896
5897         if (count < dev_priv->ips.last_count2) {
5898                 diff = ~0UL - dev_priv->ips.last_count2;
5899                 diff += count;
5900         } else {
5901                 diff = count - dev_priv->ips.last_count2;
5902         }
5903
5904         dev_priv->ips.last_count2 = count;
5905         dev_priv->ips.last_time2 = now;
5906
5907         /* More magic constants... */
5908         diff = diff * 1181;
5909         diff = div_u64(diff, diffms * 10);
5910         dev_priv->ips.gfx_power = diff;
5911 }
5912
5913 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5914 {
5915         struct drm_device *dev = dev_priv->dev;
5916
5917         if (INTEL_INFO(dev)->gen != 5)
5918                 return;
5919
5920         spin_lock_irq(&mchdev_lock);
5921
5922         __i915_update_gfx_val(dev_priv);
5923
5924         spin_unlock_irq(&mchdev_lock);
5925 }
5926
5927 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5928 {
5929         unsigned long t, corr, state1, corr2, state2;
5930         u32 pxvid, ext_v;
5931
5932         assert_spin_locked(&mchdev_lock);
5933
5934         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5935         pxvid = (pxvid >> 24) & 0x7f;
5936         ext_v = pvid_to_extvid(dev_priv, pxvid);
5937
5938         state1 = ext_v;
5939
5940         t = i915_mch_val(dev_priv);
5941
5942         /* Revel in the empirically derived constants */
5943
5944         /* Correction factor in 1/100000 units */
5945         if (t > 80)
5946                 corr = ((t * 2349) + 135940);
5947         else if (t >= 50)
5948                 corr = ((t * 964) + 29317);
5949         else /* < 50 */
5950                 corr = ((t * 301) + 1004);
5951
5952         corr = corr * ((150142 * state1) / 10000 - 78642);
5953         corr /= 100000;
5954         corr2 = (corr * dev_priv->ips.corr);
5955
5956         state2 = (corr2 * state1) / 10000;
5957         state2 /= 100; /* convert to mW */
5958
5959         __i915_update_gfx_val(dev_priv);
5960
5961         return dev_priv->ips.gfx_power + state2;
5962 }
5963
5964 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5965 {
5966         struct drm_device *dev = dev_priv->dev;
5967         unsigned long val;
5968
5969         if (INTEL_INFO(dev)->gen != 5)
5970                 return 0;
5971
5972         spin_lock_irq(&mchdev_lock);
5973
5974         val = __i915_gfx_val(dev_priv);
5975
5976         spin_unlock_irq(&mchdev_lock);
5977
5978         return val;
5979 }
5980
5981 /**
5982  * i915_read_mch_val - return value for IPS use
5983  *
5984  * Calculate and return a value for the IPS driver to use when deciding whether
5985  * we have thermal and power headroom to increase CPU or GPU power budget.
5986  */
5987 unsigned long i915_read_mch_val(void)
5988 {
5989         struct drm_i915_private *dev_priv;
5990         unsigned long chipset_val, graphics_val, ret = 0;
5991
5992         spin_lock_irq(&mchdev_lock);
5993         if (!i915_mch_dev)
5994                 goto out_unlock;
5995         dev_priv = i915_mch_dev;
5996
5997         chipset_val = __i915_chipset_val(dev_priv);
5998         graphics_val = __i915_gfx_val(dev_priv);
5999
6000         ret = chipset_val + graphics_val;
6001
6002 out_unlock:
6003         spin_unlock_irq(&mchdev_lock);
6004
6005         return ret;
6006 }
6007 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6008
6009 /**
6010  * i915_gpu_raise - raise GPU frequency limit
6011  *
6012  * Raise the limit; IPS indicates we have thermal headroom.
6013  */
6014 bool i915_gpu_raise(void)
6015 {
6016         struct drm_i915_private *dev_priv;
6017         bool ret = true;
6018
6019         spin_lock_irq(&mchdev_lock);
6020         if (!i915_mch_dev) {
6021                 ret = false;
6022                 goto out_unlock;
6023         }
6024         dev_priv = i915_mch_dev;
6025
6026         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6027                 dev_priv->ips.max_delay--;
6028
6029 out_unlock:
6030         spin_unlock_irq(&mchdev_lock);
6031
6032         return ret;
6033 }
6034 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6035
6036 /**
6037  * i915_gpu_lower - lower GPU frequency limit
6038  *
6039  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6040  * frequency maximum.
6041  */
6042 bool i915_gpu_lower(void)
6043 {
6044         struct drm_i915_private *dev_priv;
6045         bool ret = true;
6046
6047         spin_lock_irq(&mchdev_lock);
6048         if (!i915_mch_dev) {
6049                 ret = false;
6050                 goto out_unlock;
6051         }
6052         dev_priv = i915_mch_dev;
6053
6054         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6055                 dev_priv->ips.max_delay++;
6056
6057 out_unlock:
6058         spin_unlock_irq(&mchdev_lock);
6059
6060         return ret;
6061 }
6062 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6063
6064 /**
6065  * i915_gpu_busy - indicate GPU business to IPS
6066  *
6067  * Tell the IPS driver whether or not the GPU is busy.
6068  */
6069 bool i915_gpu_busy(void)
6070 {
6071         struct drm_i915_private *dev_priv;
6072         struct intel_engine_cs *ring;
6073         bool ret = false;
6074         int i;
6075
6076         spin_lock_irq(&mchdev_lock);
6077         if (!i915_mch_dev)
6078                 goto out_unlock;
6079         dev_priv = i915_mch_dev;
6080
6081         for_each_ring(ring, dev_priv, i)
6082                 ret |= !list_empty(&ring->request_list);
6083
6084 out_unlock:
6085         spin_unlock_irq(&mchdev_lock);
6086
6087         return ret;
6088 }
6089 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6090
6091 /**
6092  * i915_gpu_turbo_disable - disable graphics turbo
6093  *
6094  * Disable graphics turbo by resetting the max frequency and setting the
6095  * current frequency to the default.
6096  */
6097 bool i915_gpu_turbo_disable(void)
6098 {
6099         struct drm_i915_private *dev_priv;
6100         bool ret = true;
6101
6102         spin_lock_irq(&mchdev_lock);
6103         if (!i915_mch_dev) {
6104                 ret = false;
6105                 goto out_unlock;
6106         }
6107         dev_priv = i915_mch_dev;
6108
6109         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6110
6111         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6112                 ret = false;
6113
6114 out_unlock:
6115         spin_unlock_irq(&mchdev_lock);
6116
6117         return ret;
6118 }
6119 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6120
6121 /**
6122  * Tells the intel_ips driver that the i915 driver is now loaded, if
6123  * IPS got loaded first.
6124  *
6125  * This awkward dance is so that neither module has to depend on the
6126  * other in order for IPS to do the appropriate communication of
6127  * GPU turbo limits to i915.
6128  */
6129 static void
6130 ips_ping_for_i915_load(void)
6131 {
6132         void (*link)(void);
6133
6134         link = symbol_get(ips_link_to_i915_driver);
6135         if (link) {
6136                 link();
6137                 symbol_put(ips_link_to_i915_driver);
6138         }
6139 }
6140
6141 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6142 {
6143         /* We only register the i915 ips part with intel-ips once everything is
6144          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6145         spin_lock_irq(&mchdev_lock);
6146         i915_mch_dev = dev_priv;
6147         spin_unlock_irq(&mchdev_lock);
6148
6149         ips_ping_for_i915_load();
6150 }
6151
6152 void intel_gpu_ips_teardown(void)
6153 {
6154         spin_lock_irq(&mchdev_lock);
6155         i915_mch_dev = NULL;
6156         spin_unlock_irq(&mchdev_lock);
6157 }
6158
6159 static void intel_init_emon(struct drm_device *dev)
6160 {
6161         struct drm_i915_private *dev_priv = dev->dev_private;
6162         u32 lcfuse;
6163         u8 pxw[16];
6164         int i;
6165
6166         /* Disable to program */
6167         I915_WRITE(ECR, 0);
6168         POSTING_READ(ECR);
6169
6170         /* Program energy weights for various events */
6171         I915_WRITE(SDEW, 0x15040d00);
6172         I915_WRITE(CSIEW0, 0x007f0000);
6173         I915_WRITE(CSIEW1, 0x1e220004);
6174         I915_WRITE(CSIEW2, 0x04000004);
6175
6176         for (i = 0; i < 5; i++)
6177                 I915_WRITE(PEW(i), 0);
6178         for (i = 0; i < 3; i++)
6179                 I915_WRITE(DEW(i), 0);
6180
6181         /* Program P-state weights to account for frequency power adjustment */
6182         for (i = 0; i < 16; i++) {
6183                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6184                 unsigned long freq = intel_pxfreq(pxvidfreq);
6185                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6186                         PXVFREQ_PX_SHIFT;
6187                 unsigned long val;
6188
6189                 val = vid * vid;
6190                 val *= (freq / 1000);
6191                 val *= 255;
6192                 val /= (127*127*900);
6193                 if (val > 0xff)
6194                         DRM_ERROR("bad pxval: %ld\n", val);
6195                 pxw[i] = val;
6196         }
6197         /* Render standby states get 0 weight */
6198         pxw[14] = 0;
6199         pxw[15] = 0;
6200
6201         for (i = 0; i < 4; i++) {
6202                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6203                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6204                 I915_WRITE(PXW(i), val);
6205         }
6206
6207         /* Adjust magic regs to magic values (more experimental results) */
6208         I915_WRITE(OGW0, 0);
6209         I915_WRITE(OGW1, 0);
6210         I915_WRITE(EG0, 0x00007f00);
6211         I915_WRITE(EG1, 0x0000000e);
6212         I915_WRITE(EG2, 0x000e0000);
6213         I915_WRITE(EG3, 0x68000300);
6214         I915_WRITE(EG4, 0x42000000);
6215         I915_WRITE(EG5, 0x00140031);
6216         I915_WRITE(EG6, 0);
6217         I915_WRITE(EG7, 0);
6218
6219         for (i = 0; i < 8; i++)
6220                 I915_WRITE(PXWL(i), 0);
6221
6222         /* Enable PMON + select events */
6223         I915_WRITE(ECR, 0x80000019);
6224
6225         lcfuse = I915_READ(LCFUSE02);
6226
6227         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6228 }
6229
6230 void intel_init_gt_powersave(struct drm_device *dev)
6231 {
6232         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6233
6234         if (IS_CHERRYVIEW(dev))
6235                 cherryview_init_gt_powersave(dev);
6236         else if (IS_VALLEYVIEW(dev))
6237                 valleyview_init_gt_powersave(dev);
6238 }
6239
6240 void intel_cleanup_gt_powersave(struct drm_device *dev)
6241 {
6242         if (IS_CHERRYVIEW(dev))
6243                 return;
6244         else if (IS_VALLEYVIEW(dev))
6245                 valleyview_cleanup_gt_powersave(dev);
6246 }
6247
6248 static void gen6_suspend_rps(struct drm_device *dev)
6249 {
6250         struct drm_i915_private *dev_priv = dev->dev_private;
6251
6252         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6253
6254         gen6_disable_rps_interrupts(dev);
6255 }
6256
6257 /**
6258  * intel_suspend_gt_powersave - suspend PM work and helper threads
6259  * @dev: drm device
6260  *
6261  * We don't want to disable RC6 or other features here, we just want
6262  * to make sure any work we've queued has finished and won't bother
6263  * us while we're suspended.
6264  */
6265 void intel_suspend_gt_powersave(struct drm_device *dev)
6266 {
6267         struct drm_i915_private *dev_priv = dev->dev_private;
6268
6269         if (INTEL_INFO(dev)->gen < 6)
6270                 return;
6271
6272         gen6_suspend_rps(dev);
6273
6274         /* Force GPU to min freq during suspend */
6275         gen6_rps_idle(dev_priv);
6276 }
6277
6278 void intel_disable_gt_powersave(struct drm_device *dev)
6279 {
6280         struct drm_i915_private *dev_priv = dev->dev_private;
6281
6282         if (IS_IRONLAKE_M(dev)) {
6283                 ironlake_disable_drps(dev);
6284         } else if (INTEL_INFO(dev)->gen >= 6) {
6285                 intel_suspend_gt_powersave(dev);
6286
6287                 mutex_lock(&dev_priv->rps.hw_lock);
6288                 if (INTEL_INFO(dev)->gen >= 9)
6289                         gen9_disable_rps(dev);
6290                 else if (IS_CHERRYVIEW(dev))
6291                         cherryview_disable_rps(dev);
6292                 else if (IS_VALLEYVIEW(dev))
6293                         valleyview_disable_rps(dev);
6294                 else
6295                         gen6_disable_rps(dev);
6296
6297                 dev_priv->rps.enabled = false;
6298                 mutex_unlock(&dev_priv->rps.hw_lock);
6299         }
6300 }
6301
6302 static void intel_gen6_powersave_work(struct work_struct *work)
6303 {
6304         struct drm_i915_private *dev_priv =
6305                 container_of(work, struct drm_i915_private,
6306                              rps.delayed_resume_work.work);
6307         struct drm_device *dev = dev_priv->dev;
6308
6309         mutex_lock(&dev_priv->rps.hw_lock);
6310
6311         gen6_reset_rps_interrupts(dev);
6312
6313         if (IS_CHERRYVIEW(dev)) {
6314                 cherryview_enable_rps(dev);
6315         } else if (IS_VALLEYVIEW(dev)) {
6316                 valleyview_enable_rps(dev);
6317         } else if (INTEL_INFO(dev)->gen >= 9) {
6318                 gen9_enable_rc6(dev);
6319                 gen9_enable_rps(dev);
6320                 if (IS_SKYLAKE(dev))
6321                         __gen6_update_ring_freq(dev);
6322         } else if (IS_BROADWELL(dev)) {
6323                 gen8_enable_rps(dev);
6324                 __gen6_update_ring_freq(dev);
6325         } else {
6326                 gen6_enable_rps(dev);
6327                 __gen6_update_ring_freq(dev);
6328         }
6329
6330         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6331         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6332
6333         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6334         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6335
6336         dev_priv->rps.enabled = true;
6337
6338         gen6_enable_rps_interrupts(dev);
6339
6340         mutex_unlock(&dev_priv->rps.hw_lock);
6341
6342         intel_runtime_pm_put(dev_priv);
6343 }
6344
6345 void intel_enable_gt_powersave(struct drm_device *dev)
6346 {
6347         struct drm_i915_private *dev_priv = dev->dev_private;
6348
6349         /* Powersaving is controlled by the host when inside a VM */
6350         if (intel_vgpu_active(dev))
6351                 return;
6352
6353         if (IS_IRONLAKE_M(dev)) {
6354                 mutex_lock(&dev->struct_mutex);
6355                 ironlake_enable_drps(dev);
6356                 intel_init_emon(dev);
6357                 mutex_unlock(&dev->struct_mutex);
6358         } else if (INTEL_INFO(dev)->gen >= 6) {
6359                 /*
6360                  * PCU communication is slow and this doesn't need to be
6361                  * done at any specific time, so do this out of our fast path
6362                  * to make resume and init faster.
6363                  *
6364                  * We depend on the HW RC6 power context save/restore
6365                  * mechanism when entering D3 through runtime PM suspend. So
6366                  * disable RPM until RPS/RC6 is properly setup. We can only
6367                  * get here via the driver load/system resume/runtime resume
6368                  * paths, so the _noresume version is enough (and in case of
6369                  * runtime resume it's necessary).
6370                  */
6371                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6372                                            round_jiffies_up_relative(HZ)))
6373                         intel_runtime_pm_get_noresume(dev_priv);
6374         }
6375 }
6376
6377 void intel_reset_gt_powersave(struct drm_device *dev)
6378 {
6379         struct drm_i915_private *dev_priv = dev->dev_private;
6380
6381         if (INTEL_INFO(dev)->gen < 6)
6382                 return;
6383
6384         gen6_suspend_rps(dev);
6385         dev_priv->rps.enabled = false;
6386 }
6387
6388 static void ibx_init_clock_gating(struct drm_device *dev)
6389 {
6390         struct drm_i915_private *dev_priv = dev->dev_private;
6391
6392         /*
6393          * On Ibex Peak and Cougar Point, we need to disable clock
6394          * gating for the panel power sequencer or it will fail to
6395          * start up when no ports are active.
6396          */
6397         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6398 }
6399
6400 static void g4x_disable_trickle_feed(struct drm_device *dev)
6401 {
6402         struct drm_i915_private *dev_priv = dev->dev_private;
6403         enum pipe pipe;
6404
6405         for_each_pipe(dev_priv, pipe) {
6406                 I915_WRITE(DSPCNTR(pipe),
6407                            I915_READ(DSPCNTR(pipe)) |
6408                            DISPPLANE_TRICKLE_FEED_DISABLE);
6409
6410                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6411                 POSTING_READ(DSPSURF(pipe));
6412         }
6413 }
6414
6415 static void ilk_init_lp_watermarks(struct drm_device *dev)
6416 {
6417         struct drm_i915_private *dev_priv = dev->dev_private;
6418
6419         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6420         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6421         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6422
6423         /*
6424          * Don't touch WM1S_LP_EN here.
6425          * Doing so could cause underruns.
6426          */
6427 }
6428
6429 static void ironlake_init_clock_gating(struct drm_device *dev)
6430 {
6431         struct drm_i915_private *dev_priv = dev->dev_private;
6432         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6433
6434         /*
6435          * Required for FBC
6436          * WaFbcDisableDpfcClockGating:ilk
6437          */
6438         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6439                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6440                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6441
6442         I915_WRITE(PCH_3DCGDIS0,
6443                    MARIUNIT_CLOCK_GATE_DISABLE |
6444                    SVSMUNIT_CLOCK_GATE_DISABLE);
6445         I915_WRITE(PCH_3DCGDIS1,
6446                    VFMUNIT_CLOCK_GATE_DISABLE);
6447
6448         /*
6449          * According to the spec the following bits should be set in
6450          * order to enable memory self-refresh
6451          * The bit 22/21 of 0x42004
6452          * The bit 5 of 0x42020
6453          * The bit 15 of 0x45000
6454          */
6455         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6456                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6457                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6458         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6459         I915_WRITE(DISP_ARB_CTL,
6460                    (I915_READ(DISP_ARB_CTL) |
6461                     DISP_FBC_WM_DIS));
6462
6463         ilk_init_lp_watermarks(dev);
6464
6465         /*
6466          * Based on the document from hardware guys the following bits
6467          * should be set unconditionally in order to enable FBC.
6468          * The bit 22 of 0x42000
6469          * The bit 22 of 0x42004
6470          * The bit 7,8,9 of 0x42020.
6471          */
6472         if (IS_IRONLAKE_M(dev)) {
6473                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6474                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6475                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6476                            ILK_FBCQ_DIS);
6477                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6478                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6479                            ILK_DPARB_GATE);
6480         }
6481
6482         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6483
6484         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6485                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6486                    ILK_ELPIN_409_SELECT);
6487         I915_WRITE(_3D_CHICKEN2,
6488                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6489                    _3D_CHICKEN2_WM_READ_PIPELINED);
6490
6491         /* WaDisableRenderCachePipelinedFlush:ilk */
6492         I915_WRITE(CACHE_MODE_0,
6493                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6494
6495         /* WaDisable_RenderCache_OperationalFlush:ilk */
6496         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6497
6498         g4x_disable_trickle_feed(dev);
6499
6500         ibx_init_clock_gating(dev);
6501 }
6502
6503 static void cpt_init_clock_gating(struct drm_device *dev)
6504 {
6505         struct drm_i915_private *dev_priv = dev->dev_private;
6506         int pipe;
6507         uint32_t val;
6508
6509         /*
6510          * On Ibex Peak and Cougar Point, we need to disable clock
6511          * gating for the panel power sequencer or it will fail to
6512          * start up when no ports are active.
6513          */
6514         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6515                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6516                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6517         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6518                    DPLS_EDP_PPS_FIX_DIS);
6519         /* The below fixes the weird display corruption, a few pixels shifted
6520          * downward, on (only) LVDS of some HP laptops with IVY.
6521          */
6522         for_each_pipe(dev_priv, pipe) {
6523                 val = I915_READ(TRANS_CHICKEN2(pipe));
6524                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6525                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6526                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6527                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6528                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6529                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6530                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6531                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6532         }
6533         /* WADP0ClockGatingDisable */
6534         for_each_pipe(dev_priv, pipe) {
6535                 I915_WRITE(TRANS_CHICKEN1(pipe),
6536                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6537         }
6538 }
6539
6540 static void gen6_check_mch_setup(struct drm_device *dev)
6541 {
6542         struct drm_i915_private *dev_priv = dev->dev_private;
6543         uint32_t tmp;
6544
6545         tmp = I915_READ(MCH_SSKPD);
6546         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6547                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6548                               tmp);
6549 }
6550
6551 static void gen6_init_clock_gating(struct drm_device *dev)
6552 {
6553         struct drm_i915_private *dev_priv = dev->dev_private;
6554         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6555
6556         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6557
6558         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6559                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6560                    ILK_ELPIN_409_SELECT);
6561
6562         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6563         I915_WRITE(_3D_CHICKEN,
6564                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6565
6566         /* WaDisable_RenderCache_OperationalFlush:snb */
6567         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6568
6569         /*
6570          * BSpec recoomends 8x4 when MSAA is used,
6571          * however in practice 16x4 seems fastest.
6572          *
6573          * Note that PS/WM thread counts depend on the WIZ hashing
6574          * disable bit, which we don't touch here, but it's good
6575          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6576          */
6577         I915_WRITE(GEN6_GT_MODE,
6578                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6579
6580         ilk_init_lp_watermarks(dev);
6581
6582         I915_WRITE(CACHE_MODE_0,
6583                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6584
6585         I915_WRITE(GEN6_UCGCTL1,
6586                    I915_READ(GEN6_UCGCTL1) |
6587                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6588                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6589
6590         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6591          * gating disable must be set.  Failure to set it results in
6592          * flickering pixels due to Z write ordering failures after
6593          * some amount of runtime in the Mesa "fire" demo, and Unigine
6594          * Sanctuary and Tropics, and apparently anything else with
6595          * alpha test or pixel discard.
6596          *
6597          * According to the spec, bit 11 (RCCUNIT) must also be set,
6598          * but we didn't debug actual testcases to find it out.
6599          *
6600          * WaDisableRCCUnitClockGating:snb
6601          * WaDisableRCPBUnitClockGating:snb
6602          */
6603         I915_WRITE(GEN6_UCGCTL2,
6604                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6605                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6606
6607         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6608         I915_WRITE(_3D_CHICKEN3,
6609                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6610
6611         /*
6612          * Bspec says:
6613          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6614          * 3DSTATE_SF number of SF output attributes is more than 16."
6615          */
6616         I915_WRITE(_3D_CHICKEN3,
6617                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6618
6619         /*
6620          * According to the spec the following bits should be
6621          * set in order to enable memory self-refresh and fbc:
6622          * The bit21 and bit22 of 0x42000
6623          * The bit21 and bit22 of 0x42004
6624          * The bit5 and bit7 of 0x42020
6625          * The bit14 of 0x70180
6626          * The bit14 of 0x71180
6627          *
6628          * WaFbcAsynchFlipDisableFbcQueue:snb
6629          */
6630         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6631                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6632                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6633         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6634                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6635                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6636         I915_WRITE(ILK_DSPCLK_GATE_D,
6637                    I915_READ(ILK_DSPCLK_GATE_D) |
6638                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6639                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6640
6641         g4x_disable_trickle_feed(dev);
6642
6643         cpt_init_clock_gating(dev);
6644
6645         gen6_check_mch_setup(dev);
6646 }
6647
6648 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6649 {
6650         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6651
6652         /*
6653          * WaVSThreadDispatchOverride:ivb,vlv
6654          *
6655          * This actually overrides the dispatch
6656          * mode for all thread types.
6657          */
6658         reg &= ~GEN7_FF_SCHED_MASK;
6659         reg |= GEN7_FF_TS_SCHED_HW;
6660         reg |= GEN7_FF_VS_SCHED_HW;
6661         reg |= GEN7_FF_DS_SCHED_HW;
6662
6663         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6664 }
6665
6666 static void lpt_init_clock_gating(struct drm_device *dev)
6667 {
6668         struct drm_i915_private *dev_priv = dev->dev_private;
6669
6670         /*
6671          * TODO: this bit should only be enabled when really needed, then
6672          * disabled when not needed anymore in order to save power.
6673          */
6674         if (HAS_PCH_LPT_LP(dev))
6675                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6676                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6677                            PCH_LP_PARTITION_LEVEL_DISABLE);
6678
6679         /* WADPOClockGatingDisable:hsw */
6680         I915_WRITE(_TRANSA_CHICKEN1,
6681                    I915_READ(_TRANSA_CHICKEN1) |
6682                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6683 }
6684
6685 static void lpt_suspend_hw(struct drm_device *dev)
6686 {
6687         struct drm_i915_private *dev_priv = dev->dev_private;
6688
6689         if (HAS_PCH_LPT_LP(dev)) {
6690                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6691
6692                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6693                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6694         }
6695 }
6696
6697 static void broadwell_init_clock_gating(struct drm_device *dev)
6698 {
6699         struct drm_i915_private *dev_priv = dev->dev_private;
6700         enum pipe pipe;
6701         uint32_t misccpctl;
6702
6703         ilk_init_lp_watermarks(dev);
6704
6705         /* WaSwitchSolVfFArbitrationPriority:bdw */
6706         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6707
6708         /* WaPsrDPAMaskVBlankInSRD:bdw */
6709         I915_WRITE(CHICKEN_PAR1_1,
6710                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6711
6712         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6713         for_each_pipe(dev_priv, pipe) {
6714                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6715                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6716                            BDW_DPRS_MASK_VBLANK_SRD);
6717         }
6718
6719         /* WaVSRefCountFullforceMissDisable:bdw */
6720         /* WaDSRefCountFullforceMissDisable:bdw */
6721         I915_WRITE(GEN7_FF_THREAD_MODE,
6722                    I915_READ(GEN7_FF_THREAD_MODE) &
6723                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6724
6725         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6726                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6727
6728         /* WaDisableSDEUnitClockGating:bdw */
6729         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6730                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6731
6732         /*
6733          * WaProgramL3SqcReg1Default:bdw
6734          * WaTempDisableDOPClkGating:bdw
6735          */
6736         misccpctl = I915_READ(GEN7_MISCCPCTL);
6737         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6738         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6739         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6740
6741         /*
6742          * WaGttCachingOffByDefault:bdw
6743          * GTT cache may not work with big pages, so if those
6744          * are ever enabled GTT cache may need to be disabled.
6745          */
6746         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6747
6748         lpt_init_clock_gating(dev);
6749 }
6750
6751 static void haswell_init_clock_gating(struct drm_device *dev)
6752 {
6753         struct drm_i915_private *dev_priv = dev->dev_private;
6754
6755         ilk_init_lp_watermarks(dev);
6756
6757         /* L3 caching of data atomics doesn't work -- disable it. */
6758         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6759         I915_WRITE(HSW_ROW_CHICKEN3,
6760                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6761
6762         /* This is required by WaCatErrorRejectionIssue:hsw */
6763         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6764                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6765                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6766
6767         /* WaVSRefCountFullforceMissDisable:hsw */
6768         I915_WRITE(GEN7_FF_THREAD_MODE,
6769                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6770
6771         /* WaDisable_RenderCache_OperationalFlush:hsw */
6772         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6773
6774         /* enable HiZ Raw Stall Optimization */
6775         I915_WRITE(CACHE_MODE_0_GEN7,
6776                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6777
6778         /* WaDisable4x2SubspanOptimization:hsw */
6779         I915_WRITE(CACHE_MODE_1,
6780                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6781
6782         /*
6783          * BSpec recommends 8x4 when MSAA is used,
6784          * however in practice 16x4 seems fastest.
6785          *
6786          * Note that PS/WM thread counts depend on the WIZ hashing
6787          * disable bit, which we don't touch here, but it's good
6788          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6789          */
6790         I915_WRITE(GEN7_GT_MODE,
6791                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6792
6793         /* WaSampleCChickenBitEnable:hsw */
6794         I915_WRITE(HALF_SLICE_CHICKEN3,
6795                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6796
6797         /* WaSwitchSolVfFArbitrationPriority:hsw */
6798         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6799
6800         /* WaRsPkgCStateDisplayPMReq:hsw */
6801         I915_WRITE(CHICKEN_PAR1_1,
6802                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6803
6804         lpt_init_clock_gating(dev);
6805 }
6806
6807 static void ivybridge_init_clock_gating(struct drm_device *dev)
6808 {
6809         struct drm_i915_private *dev_priv = dev->dev_private;
6810         uint32_t snpcr;
6811
6812         ilk_init_lp_watermarks(dev);
6813
6814         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6815
6816         /* WaDisableEarlyCull:ivb */
6817         I915_WRITE(_3D_CHICKEN3,
6818                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6819
6820         /* WaDisableBackToBackFlipFix:ivb */
6821         I915_WRITE(IVB_CHICKEN3,
6822                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6823                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6824
6825         /* WaDisablePSDDualDispatchEnable:ivb */
6826         if (IS_IVB_GT1(dev))
6827                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6828                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6829
6830         /* WaDisable_RenderCache_OperationalFlush:ivb */
6831         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6832
6833         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6834         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6835                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6836
6837         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6838         I915_WRITE(GEN7_L3CNTLREG1,
6839                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6840         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6841                    GEN7_WA_L3_CHICKEN_MODE);
6842         if (IS_IVB_GT1(dev))
6843                 I915_WRITE(GEN7_ROW_CHICKEN2,
6844                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6845         else {
6846                 /* must write both registers */
6847                 I915_WRITE(GEN7_ROW_CHICKEN2,
6848                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6849                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6850                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6851         }
6852
6853         /* WaForceL3Serialization:ivb */
6854         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6855                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6856
6857         /*
6858          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6859          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6860          */
6861         I915_WRITE(GEN6_UCGCTL2,
6862                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6863
6864         /* This is required by WaCatErrorRejectionIssue:ivb */
6865         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6866                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6867                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6868
6869         g4x_disable_trickle_feed(dev);
6870
6871         gen7_setup_fixed_func_scheduler(dev_priv);
6872
6873         if (0) { /* causes HiZ corruption on ivb:gt1 */
6874                 /* enable HiZ Raw Stall Optimization */
6875                 I915_WRITE(CACHE_MODE_0_GEN7,
6876                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6877         }
6878
6879         /* WaDisable4x2SubspanOptimization:ivb */
6880         I915_WRITE(CACHE_MODE_1,
6881                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6882
6883         /*
6884          * BSpec recommends 8x4 when MSAA is used,
6885          * however in practice 16x4 seems fastest.
6886          *
6887          * Note that PS/WM thread counts depend on the WIZ hashing
6888          * disable bit, which we don't touch here, but it's good
6889          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6890          */
6891         I915_WRITE(GEN7_GT_MODE,
6892                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6893
6894         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6895         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6896         snpcr |= GEN6_MBC_SNPCR_MED;
6897         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6898
6899         if (!HAS_PCH_NOP(dev))
6900                 cpt_init_clock_gating(dev);
6901
6902         gen6_check_mch_setup(dev);
6903 }
6904
6905 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6906 {
6907         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6908
6909         /*
6910          * Disable trickle feed and enable pnd deadline calculation
6911          */
6912         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6913         I915_WRITE(CBR1_VLV, 0);
6914 }
6915
6916 static void valleyview_init_clock_gating(struct drm_device *dev)
6917 {
6918         struct drm_i915_private *dev_priv = dev->dev_private;
6919
6920         vlv_init_display_clock_gating(dev_priv);
6921
6922         /* WaDisableEarlyCull:vlv */
6923         I915_WRITE(_3D_CHICKEN3,
6924                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6925
6926         /* WaDisableBackToBackFlipFix:vlv */
6927         I915_WRITE(IVB_CHICKEN3,
6928                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6929                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6930
6931         /* WaPsdDispatchEnable:vlv */
6932         /* WaDisablePSDDualDispatchEnable:vlv */
6933         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6934                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6935                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6936
6937         /* WaDisable_RenderCache_OperationalFlush:vlv */
6938         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6939
6940         /* WaForceL3Serialization:vlv */
6941         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6942                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6943
6944         /* WaDisableDopClockGating:vlv */
6945         I915_WRITE(GEN7_ROW_CHICKEN2,
6946                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6947
6948         /* This is required by WaCatErrorRejectionIssue:vlv */
6949         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6950                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6951                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6952
6953         gen7_setup_fixed_func_scheduler(dev_priv);
6954
6955         /*
6956          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6957          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6958          */
6959         I915_WRITE(GEN6_UCGCTL2,
6960                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6961
6962         /* WaDisableL3Bank2xClockGate:vlv
6963          * Disabling L3 clock gating- MMIO 940c[25] = 1
6964          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6965         I915_WRITE(GEN7_UCGCTL4,
6966                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6967
6968         /*
6969          * BSpec says this must be set, even though
6970          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6971          */
6972         I915_WRITE(CACHE_MODE_1,
6973                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6974
6975         /*
6976          * BSpec recommends 8x4 when MSAA is used,
6977          * however in practice 16x4 seems fastest.
6978          *
6979          * Note that PS/WM thread counts depend on the WIZ hashing
6980          * disable bit, which we don't touch here, but it's good
6981          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6982          */
6983         I915_WRITE(GEN7_GT_MODE,
6984                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6985
6986         /*
6987          * WaIncreaseL3CreditsForVLVB0:vlv
6988          * This is the hardware default actually.
6989          */
6990         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6991
6992         /*
6993          * WaDisableVLVClockGating_VBIIssue:vlv
6994          * Disable clock gating on th GCFG unit to prevent a delay
6995          * in the reporting of vblank events.
6996          */
6997         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6998 }
6999
7000 static void cherryview_init_clock_gating(struct drm_device *dev)
7001 {
7002         struct drm_i915_private *dev_priv = dev->dev_private;
7003
7004         vlv_init_display_clock_gating(dev_priv);
7005
7006         /* WaVSRefCountFullforceMissDisable:chv */
7007         /* WaDSRefCountFullforceMissDisable:chv */
7008         I915_WRITE(GEN7_FF_THREAD_MODE,
7009                    I915_READ(GEN7_FF_THREAD_MODE) &
7010                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7011
7012         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7013         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7014                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7015
7016         /* WaDisableCSUnitClockGating:chv */
7017         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7018                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7019
7020         /* WaDisableSDEUnitClockGating:chv */
7021         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7022                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7023
7024         /*
7025          * GTT cache may not work with big pages, so if those
7026          * are ever enabled GTT cache may need to be disabled.
7027          */
7028         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7029 }
7030
7031 static void g4x_init_clock_gating(struct drm_device *dev)
7032 {
7033         struct drm_i915_private *dev_priv = dev->dev_private;
7034         uint32_t dspclk_gate;
7035
7036         I915_WRITE(RENCLK_GATE_D1, 0);
7037         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7038                    GS_UNIT_CLOCK_GATE_DISABLE |
7039                    CL_UNIT_CLOCK_GATE_DISABLE);
7040         I915_WRITE(RAMCLK_GATE_D, 0);
7041         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7042                 OVRUNIT_CLOCK_GATE_DISABLE |
7043                 OVCUNIT_CLOCK_GATE_DISABLE;
7044         if (IS_GM45(dev))
7045                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7046         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7047
7048         /* WaDisableRenderCachePipelinedFlush */
7049         I915_WRITE(CACHE_MODE_0,
7050                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7051
7052         /* WaDisable_RenderCache_OperationalFlush:g4x */
7053         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7054
7055         g4x_disable_trickle_feed(dev);
7056 }
7057
7058 static void crestline_init_clock_gating(struct drm_device *dev)
7059 {
7060         struct drm_i915_private *dev_priv = dev->dev_private;
7061
7062         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7063         I915_WRITE(RENCLK_GATE_D2, 0);
7064         I915_WRITE(DSPCLK_GATE_D, 0);
7065         I915_WRITE(RAMCLK_GATE_D, 0);
7066         I915_WRITE16(DEUC, 0);
7067         I915_WRITE(MI_ARB_STATE,
7068                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7069
7070         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7071         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7072 }
7073
7074 static void broadwater_init_clock_gating(struct drm_device *dev)
7075 {
7076         struct drm_i915_private *dev_priv = dev->dev_private;
7077
7078         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7079                    I965_RCC_CLOCK_GATE_DISABLE |
7080                    I965_RCPB_CLOCK_GATE_DISABLE |
7081                    I965_ISC_CLOCK_GATE_DISABLE |
7082                    I965_FBC_CLOCK_GATE_DISABLE);
7083         I915_WRITE(RENCLK_GATE_D2, 0);
7084         I915_WRITE(MI_ARB_STATE,
7085                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7086
7087         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7088         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7089 }
7090
7091 static void gen3_init_clock_gating(struct drm_device *dev)
7092 {
7093         struct drm_i915_private *dev_priv = dev->dev_private;
7094         u32 dstate = I915_READ(D_STATE);
7095
7096         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7097                 DSTATE_DOT_CLOCK_GATING;
7098         I915_WRITE(D_STATE, dstate);
7099
7100         if (IS_PINEVIEW(dev))
7101                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7102
7103         /* IIR "flip pending" means done if this bit is set */
7104         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7105
7106         /* interrupts should cause a wake up from C3 */
7107         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7108
7109         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7110         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7111
7112         I915_WRITE(MI_ARB_STATE,
7113                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7114 }
7115
7116 static void i85x_init_clock_gating(struct drm_device *dev)
7117 {
7118         struct drm_i915_private *dev_priv = dev->dev_private;
7119
7120         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7121
7122         /* interrupts should cause a wake up from C3 */
7123         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7124                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7125
7126         I915_WRITE(MEM_MODE,
7127                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7128 }
7129
7130 static void i830_init_clock_gating(struct drm_device *dev)
7131 {
7132         struct drm_i915_private *dev_priv = dev->dev_private;
7133
7134         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7135
7136         I915_WRITE(MEM_MODE,
7137                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7138                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7139 }
7140
7141 void intel_init_clock_gating(struct drm_device *dev)
7142 {
7143         struct drm_i915_private *dev_priv = dev->dev_private;
7144
7145         if (dev_priv->display.init_clock_gating)
7146                 dev_priv->display.init_clock_gating(dev);
7147 }
7148
7149 void intel_suspend_hw(struct drm_device *dev)
7150 {
7151         if (HAS_PCH_LPT(dev))
7152                 lpt_suspend_hw(dev);
7153 }
7154
7155 /* Set up chip specific power management-related functions */
7156 void intel_init_pm(struct drm_device *dev)
7157 {
7158         struct drm_i915_private *dev_priv = dev->dev_private;
7159
7160         intel_fbc_init(dev_priv);
7161
7162         /* For cxsr */
7163         if (IS_PINEVIEW(dev))
7164                 i915_pineview_get_mem_freq(dev);
7165         else if (IS_GEN5(dev))
7166                 i915_ironlake_get_mem_freq(dev);
7167
7168         /* For FIFO watermark updates */
7169         if (INTEL_INFO(dev)->gen >= 9) {
7170                 skl_setup_wm_latency(dev);
7171
7172                 if (IS_BROXTON(dev))
7173                         dev_priv->display.init_clock_gating =
7174                                 bxt_init_clock_gating;
7175                 else if (IS_SKYLAKE(dev))
7176                         dev_priv->display.init_clock_gating =
7177                                 skl_init_clock_gating;
7178                 dev_priv->display.update_wm = skl_update_wm;
7179                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7180         } else if (HAS_PCH_SPLIT(dev)) {
7181                 ilk_setup_wm_latency(dev);
7182
7183                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7184                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7185                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7186                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7187                         dev_priv->display.update_wm = ilk_update_wm;
7188                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7189                 } else {
7190                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7191                                       "Disable CxSR\n");
7192                 }
7193
7194                 if (IS_GEN5(dev))
7195                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7196                 else if (IS_GEN6(dev))
7197                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7198                 else if (IS_IVYBRIDGE(dev))
7199                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7200                 else if (IS_HASWELL(dev))
7201                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7202                 else if (INTEL_INFO(dev)->gen == 8)
7203                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7204         } else if (IS_CHERRYVIEW(dev)) {
7205                 vlv_setup_wm_latency(dev);
7206
7207                 dev_priv->display.update_wm = vlv_update_wm;
7208                 dev_priv->display.init_clock_gating =
7209                         cherryview_init_clock_gating;
7210         } else if (IS_VALLEYVIEW(dev)) {
7211                 vlv_setup_wm_latency(dev);
7212
7213                 dev_priv->display.update_wm = vlv_update_wm;
7214                 dev_priv->display.init_clock_gating =
7215                         valleyview_init_clock_gating;
7216         } else if (IS_PINEVIEW(dev)) {
7217                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7218                                             dev_priv->is_ddr3,
7219                                             dev_priv->fsb_freq,
7220                                             dev_priv->mem_freq)) {
7221                         DRM_INFO("failed to find known CxSR latency "
7222                                  "(found ddr%s fsb freq %d, mem freq %d), "
7223                                  "disabling CxSR\n",
7224                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7225                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7226                         /* Disable CxSR and never update its watermark again */
7227                         intel_set_memory_cxsr(dev_priv, false);
7228                         dev_priv->display.update_wm = NULL;
7229                 } else
7230                         dev_priv->display.update_wm = pineview_update_wm;
7231                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7232         } else if (IS_G4X(dev)) {
7233                 dev_priv->display.update_wm = g4x_update_wm;
7234                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7235         } else if (IS_GEN4(dev)) {
7236                 dev_priv->display.update_wm = i965_update_wm;
7237                 if (IS_CRESTLINE(dev))
7238                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7239                 else if (IS_BROADWATER(dev))
7240                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7241         } else if (IS_GEN3(dev)) {
7242                 dev_priv->display.update_wm = i9xx_update_wm;
7243                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7244                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7245         } else if (IS_GEN2(dev)) {
7246                 if (INTEL_INFO(dev)->num_pipes == 1) {
7247                         dev_priv->display.update_wm = i845_update_wm;
7248                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7249                 } else {
7250                         dev_priv->display.update_wm = i9xx_update_wm;
7251                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7252                 }
7253
7254                 if (IS_I85X(dev) || IS_I865G(dev))
7255                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7256                 else
7257                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7258         } else {
7259                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7260         }
7261 }
7262
7263 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7264 {
7265         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7266
7267         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7268                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7269                 return -EAGAIN;
7270         }
7271
7272         I915_WRITE(GEN6_PCODE_DATA, *val);
7273         I915_WRITE(GEN6_PCODE_DATA1, 0);
7274         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7275
7276         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7277                      500)) {
7278                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7279                 return -ETIMEDOUT;
7280         }
7281
7282         *val = I915_READ(GEN6_PCODE_DATA);
7283         I915_WRITE(GEN6_PCODE_DATA, 0);
7284
7285         return 0;
7286 }
7287
7288 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7289 {
7290         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7291
7292         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7293                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7294                 return -EAGAIN;
7295         }
7296
7297         I915_WRITE(GEN6_PCODE_DATA, val);
7298         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7299
7300         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7301                      500)) {
7302                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7303                 return -ETIMEDOUT;
7304         }
7305
7306         I915_WRITE(GEN6_PCODE_DATA, 0);
7307
7308         return 0;
7309 }
7310
7311 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7312 {
7313         switch (czclk_freq) {
7314         case 200:
7315                 return 10;
7316         case 267:
7317                 return 12;
7318         case 320:
7319         case 333:
7320                 return 16;
7321         case 400:
7322                 return 20;
7323         default:
7324                 return -1;
7325         }
7326 }
7327
7328 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7329 {
7330         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7331
7332         div = vlv_gpu_freq_div(czclk_freq);
7333         if (div < 0)
7334                 return div;
7335
7336         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7337 }
7338
7339 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7340 {
7341         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7342
7343         mul = vlv_gpu_freq_div(czclk_freq);
7344         if (mul < 0)
7345                 return mul;
7346
7347         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7348 }
7349
7350 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7351 {
7352         int div, czclk_freq = dev_priv->rps.cz_freq;
7353
7354         div = vlv_gpu_freq_div(czclk_freq) / 2;
7355         if (div < 0)
7356                 return div;
7357
7358         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7359 }
7360
7361 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7362 {
7363         int mul, czclk_freq = dev_priv->rps.cz_freq;
7364
7365         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7366         if (mul < 0)
7367                 return mul;
7368
7369         /* CHV needs even values */
7370         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7371 }
7372
7373 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7374 {
7375         if (IS_GEN9(dev_priv->dev))
7376                 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7377         else if (IS_CHERRYVIEW(dev_priv->dev))
7378                 return chv_gpu_freq(dev_priv, val);
7379         else if (IS_VALLEYVIEW(dev_priv->dev))
7380                 return byt_gpu_freq(dev_priv, val);
7381         else
7382                 return val * GT_FREQUENCY_MULTIPLIER;
7383 }
7384
7385 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7386 {
7387         if (IS_GEN9(dev_priv->dev))
7388                 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7389         else if (IS_CHERRYVIEW(dev_priv->dev))
7390                 return chv_freq_opcode(dev_priv, val);
7391         else if (IS_VALLEYVIEW(dev_priv->dev))
7392                 return byt_freq_opcode(dev_priv, val);
7393         else
7394                 return val / GT_FREQUENCY_MULTIPLIER;
7395 }
7396
7397 struct request_boost {
7398         struct work_struct work;
7399         struct drm_i915_gem_request *req;
7400 };
7401
7402 static void __intel_rps_boost_work(struct work_struct *work)
7403 {
7404         struct request_boost *boost = container_of(work, struct request_boost, work);
7405         struct drm_i915_gem_request *req = boost->req;
7406
7407         if (!i915_gem_request_completed(req, true))
7408                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7409                                req->emitted_jiffies);
7410
7411         i915_gem_request_unreference__unlocked(req);
7412         kfree(boost);
7413 }
7414
7415 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7416                                        struct drm_i915_gem_request *req)
7417 {
7418         struct request_boost *boost;
7419
7420         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7421                 return;
7422
7423         if (i915_gem_request_completed(req, true))
7424                 return;
7425
7426         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7427         if (boost == NULL)
7428                 return;
7429
7430         i915_gem_request_reference(req);
7431         boost->req = req;
7432
7433         INIT_WORK(&boost->work, __intel_rps_boost_work);
7434         queue_work(to_i915(dev)->wq, &boost->work);
7435 }
7436
7437 void intel_pm_setup(struct drm_device *dev)
7438 {
7439         struct drm_i915_private *dev_priv = dev->dev_private;
7440
7441         mutex_init(&dev_priv->rps.hw_lock);
7442         spin_lock_init(&dev_priv->rps.client_lock);
7443
7444         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7445                           intel_gen6_powersave_work);
7446         INIT_LIST_HEAD(&dev_priv->rps.clients);
7447         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7448         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7449
7450         dev_priv->pm.suspended = false;
7451 }