drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int
 284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 285                        u32 invalidate_domains, u32 flush_domains)
 286 {
 287         u32 flags = 0;
 288         struct pipe_control *pc = ring->private;
 289         u32 scratch_addr = pc->gtt_offset + 128;
 290         int ret;
 291
 292         /*
 293          * Ensure that any following seqno writes only happen when the render
 294          * cache is indeed flushed.
 295          *
 296          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 297          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 298          * don't try to be clever and just set it unconditionally.
 299          */
 300         flags |= PIPE_CONTROL_CS_STALL;
 301
 302         /* Just flush everything.  Experiments have shown that reducing the
 303          * number of bits based on the write domains has little performance
 304          * impact.
 305          */
 306         if (flush_domains) {
 307                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 308                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 309         }
 310         if (invalidate_domains) {
 311                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 312                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 /* Workaround: we must issue a pipe_control with CS-stall bit
 324                  * set before a pipe_control command that has the state cache
 325                  * invalidate bit set. */
 326                 gen7_render_ring_cs_stall_wa(ring);
 327         }
 328
 329         ret = intel_ring_begin(ring, 4);
 330         if (ret)
 331                 return ret;
 332
 333         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 334         intel_ring_emit(ring, flags);
 335         intel_ring_emit(ring, scratch_addr);
 336         intel_ring_emit(ring, 0);
 337         intel_ring_advance(ring);
 338
 339         return 0;
 340 }
 341
 342 static void ring_write_tail(struct intel_ring_buffer *ring,
 343                             u32 value)
 344 {
 345         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 346         I915_WRITE_TAIL(ring, value);
 347 }
 348
 349 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 350 {
 351         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 352         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 353                         RING_ACTHD(ring->mmio_base) : ACTHD;
 354
 355         return I915_READ(acthd_reg);
 356 }
 357
 358 static int init_ring_common(struct intel_ring_buffer *ring)
 359 {
 360         struct drm_device *dev = ring->dev;
 361         drm_i915_private_t *dev_priv = dev->dev_private;
 362         struct drm_i915_gem_object *obj = ring->obj;
 363         int ret = 0;
 364         u32 head;
 365
 366         if (HAS_FORCE_WAKE(dev))
 367                 gen6_gt_force_wake_get(dev_priv);
 368
 369         /* Stop the ring if it's running. */
 370         I915_WRITE_CTL(ring, 0);
 371         I915_WRITE_HEAD(ring, 0);
 372         ring->write_tail(ring, 0);
 373
 374         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 375
 376         /* G45 ring initialization fails to reset head to zero */
 377         if (head != 0) {
 378                 DRM_DEBUG_KMS("%s head not reset to zero "
 379                               "ctl %08x head %08x tail %08x start %08x\n",
 380                               ring->name,
 381                               I915_READ_CTL(ring),
 382                               I915_READ_HEAD(ring),
 383                               I915_READ_TAIL(ring),
 384                               I915_READ_START(ring));
 385
 386                 I915_WRITE_HEAD(ring, 0);
 387
 388                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 389                         DRM_ERROR("failed to set %s head to zero "
 390                                   "ctl %08x head %08x tail %08x start %08x\n",
 391                                   ring->name,
 392                                   I915_READ_CTL(ring),
 393                                   I915_READ_HEAD(ring),
 394                                   I915_READ_TAIL(ring),
 395                                   I915_READ_START(ring));
 396                 }
 397         }
 398
 399         /* Initialize the ring. This must happen _after_ we've cleared the ring
 400          * registers with the above sequence (the readback of the HEAD registers
 401          * also enforces ordering), otherwise the hw might lose the new ring
 402          * register values. */
 403         I915_WRITE_START(ring, obj->gtt_offset);
 404         I915_WRITE_CTL(ring,
 405                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 406                         | RING_VALID);
 407
 408         /* If the head is still not zero, the ring is dead */
 409         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 410                      I915_READ_START(ring) == obj->gtt_offset &&
 411                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 412                 DRM_ERROR("%s initialization failed "
 413                                 "ctl %08x head %08x tail %08x start %08x\n",
 414                                 ring->name,
 415                                 I915_READ_CTL(ring),
 416                                 I915_READ_HEAD(ring),
 417                                 I915_READ_TAIL(ring),
 418                                 I915_READ_START(ring));
 419                 ret = -EIO;
 420                 goto out;
 421         }
 422
 423         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 424                 i915_kernel_lost_context(ring->dev);
 425         else {
 426                 ring->head = I915_READ_HEAD(ring);
 427                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 428                 ring->space = ring_space(ring);
 429                 ring->last_retired_head = -1;
 430         }
 431
 432 out:
 433         if (HAS_FORCE_WAKE(dev))
 434                 gen6_gt_force_wake_put(dev_priv);
 435
 436         return ret;
 437 }
 438
 439 static int
 440 init_pipe_control(struct intel_ring_buffer *ring)
 441 {
 442         struct pipe_control *pc;
 443         struct drm_i915_gem_object *obj;
 444         int ret;
 445
 446         if (ring->private)
 447                 return 0;
 448
 449         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 450         if (!pc)
 451                 return -ENOMEM;
 452
 453         obj = i915_gem_alloc_object(ring->dev, 4096);
 454         if (obj == NULL) {
 455                 DRM_ERROR("Failed to allocate seqno page\n");
 456                 ret = -ENOMEM;
 457                 goto err;
 458         }
 459
 460         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 461
 462         ret = i915_gem_object_pin(obj, 4096, true, false);
 463         if (ret)
 464                 goto err_unref;
 465
 466         pc->gtt_offset = obj->gtt_offset;
 467         pc->cpu_page = kmap(sg_page(obj->pages->sgl));
 468         if (pc->cpu_page == NULL) {
 469                 ret = -ENOMEM;
 470                 goto err_unpin;
 471         }
 472
 473         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 474                          ring->name, pc->gtt_offset);
 475
 476         pc->obj = obj;
 477         ring->private = pc;
 478         return 0;
 479
 480 err_unpin:
 481         i915_gem_object_unpin(obj);
 482 err_unref:
 483         drm_gem_object_unreference(&obj->base);
 484 err:
 485         kfree(pc);
 486         return ret;
 487 }
 488
 489 static void
 490 cleanup_pipe_control(struct intel_ring_buffer *ring)
 491 {
 492         struct pipe_control *pc = ring->private;
 493         struct drm_i915_gem_object *obj;
 494
 495         if (!ring->private)
 496                 return;
 497
 498         obj = pc->obj;
 499
 500         kunmap(sg_page(obj->pages->sgl));
 501         i915_gem_object_unpin(obj);
 502         drm_gem_object_unreference(&obj->base);
 503
 504         kfree(pc);
 505         ring->private = NULL;
 506 }
 507
 508 static int init_render_ring(struct intel_ring_buffer *ring)
 509 {
 510         struct drm_device *dev = ring->dev;
 511         struct drm_i915_private *dev_priv = dev->dev_private;
 512         int ret = init_ring_common(ring);
 513
 514         if (INTEL_INFO(dev)->gen > 3)
 515                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 516
 517         /* We need to disable the AsyncFlip performance optimisations in order
 518          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 519          * programmed to '1' on all products.
 520          *
 521          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 522          */
 523         if (INTEL_INFO(dev)->gen >= 6)
 524                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 525
 526         /* Required for the hardware to program scanline values for waiting */
 527         if (INTEL_INFO(dev)->gen == 6)
 528                 I915_WRITE(GFX_MODE,
 529                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 530
 531         if (IS_GEN7(dev))
 532                 I915_WRITE(GFX_MODE_GEN7,
 533                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 534                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 535
 536         if (INTEL_INFO(dev)->gen >= 5) {
 537                 ret = init_pipe_control(ring);
 538                 if (ret)
 539                         return ret;
 540         }
 541
 542         if (IS_GEN6(dev)) {
 543                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 544                  * "If this bit is set, STCunit will have LRA as replacement
 545                  *  policy. [...] This bit must be reset.  LRA replacement
 546                  *  policy is not supported."
 547                  */
 548                 I915_WRITE(CACHE_MODE_0,
 549                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 550
 551                 /* This is not explicitly set for GEN6, so read the register.
 552                  * see intel_ring_mi_set_context() for why we care.
 553                  * TODO: consider explicitly setting the bit for GEN5
 554                  */
 555                 ring->itlb_before_ctx_switch =
 556                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 557         }
 558
 559         if (INTEL_INFO(dev)->gen >= 6)
 560                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 561
 562         if (HAS_L3_GPU_CACHE(dev))
 563                 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 564
 565         return ret;
 566 }
 567
 568 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 569 {
 570         struct drm_device *dev = ring->dev;
 571
 572         if (!ring->private)
 573                 return;
 574
 575         if (HAS_BROKEN_CS_TLB(dev))
 576                 drm_gem_object_unreference(to_gem_object(ring->private));
 577
 578         cleanup_pipe_control(ring);
 579 }
 580
 581 static void
 582 update_mboxes(struct intel_ring_buffer *ring,
 583               u32 mmio_offset)
 584 {
 585 /* NB: In order to be able to do semaphore MBOX updates for varying number
 586  * of rings, it's easiest if we round up each individual update to a
 587  * multiple of 2 (since ring updates must always be a multiple of 2)
 588  * even though the actual update only requires 3 dwords.
 589  */
 590 #define MBOX_UPDATE_DWORDS 4
 591         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 592         intel_ring_emit(ring, mmio_offset);
 593         intel_ring_emit(ring, ring->outstanding_lazy_request);
 594         intel_ring_emit(ring, MI_NOOP);
 595 }
 596
 597 /**
 598  * gen6_add_request - Update the semaphore mailbox registers
 599  *
 600  * @ring - ring that is adding a request
 601  * @seqno - return seqno stuck into the ring
 602  *
 603  * Update the mailbox registers in the *other* rings with the current seqno.
 604  * This acts like a signal in the canonical semaphore.
 605  */
 606 static int
 607 gen6_add_request(struct intel_ring_buffer *ring)
 608 {
 609         struct drm_device *dev = ring->dev;
 610         struct drm_i915_private *dev_priv = dev->dev_private;
 611         struct intel_ring_buffer *useless;
 612         int i, ret;
 613
 614         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 615                                       MBOX_UPDATE_DWORDS) +
 616                                       4);
 617         if (ret)
 618                 return ret;
 619 #undef MBOX_UPDATE_DWORDS
 620
 621         for_each_ring(useless, dev_priv, i) {
 622                 u32 mbox_reg = ring->signal_mbox[i];
 623                 if (mbox_reg != GEN6_NOSYNC)
 624                         update_mboxes(ring, mbox_reg);
 625         }
 626
 627         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 628         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 629         intel_ring_emit(ring, ring->outstanding_lazy_request);
 630         intel_ring_emit(ring, MI_USER_INTERRUPT);
 631         intel_ring_advance(ring);
 632
 633         return 0;
 634 }
 635
 636 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 637                                               u32 seqno)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         return dev_priv->last_seqno < seqno;
 641 }
 642
 643 /**
 644  * intel_ring_sync - sync the waiter to the signaller on seqno
 645  *
 646  * @waiter - ring that is waiting
 647  * @signaller - ring which has, or will signal
 648  * @seqno - seqno which the waiter will block on
 649  */
 650 static int
 651 gen6_ring_sync(struct intel_ring_buffer *waiter,
 652                struct intel_ring_buffer *signaller,
 653                u32 seqno)
 654 {
 655         int ret;
 656         u32 dw1 = MI_SEMAPHORE_MBOX |
 657                   MI_SEMAPHORE_COMPARE |
 658                   MI_SEMAPHORE_REGISTER;
 659
 660         /* Throughout all of the GEM code, seqno passed implies our current
 661          * seqno is >= the last seqno executed. However for hardware the
 662          * comparison is strictly greater than.
 663          */
 664         seqno -= 1;
 665
 666         WARN_ON(signaller->semaphore_register[waiter->id] ==
 667                 MI_SEMAPHORE_SYNC_INVALID);
 668
 669         ret = intel_ring_begin(waiter, 4);
 670         if (ret)
 671                 return ret;
 672
 673         /* If seqno wrap happened, omit the wait with no-ops */
 674         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 675                 intel_ring_emit(waiter,
 676                                 dw1 |
 677                                 signaller->semaphore_register[waiter->id]);
 678                 intel_ring_emit(waiter, seqno);
 679                 intel_ring_emit(waiter, 0);
 680                 intel_ring_emit(waiter, MI_NOOP);
 681         } else {
 682                 intel_ring_emit(waiter, MI_NOOP);
 683                 intel_ring_emit(waiter, MI_NOOP);
 684                 intel_ring_emit(waiter, MI_NOOP);
 685                 intel_ring_emit(waiter, MI_NOOP);
 686         }
 687         intel_ring_advance(waiter);
 688
 689         return 0;
 690 }
 691
 692 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 693 do {                                                                    \
 694         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 695                  PIPE_CONTROL_DEPTH_STALL);                             \
 696         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 697         intel_ring_emit(ring__, 0);                                                     \
 698         intel_ring_emit(ring__, 0);                                                     \
 699 } while (0)
 700
 701 static int
 702 pc_render_add_request(struct intel_ring_buffer *ring)
 703 {
 704         struct pipe_control *pc = ring->private;
 705         u32 scratch_addr = pc->gtt_offset + 128;
 706         int ret;
 707
 708         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 709          * incoherent with writes to memory, i.e. completely fubar,
 710          * so we need to use PIPE_NOTIFY instead.
 711          *
 712          * However, we also need to workaround the qword write
 713          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 714          * memory before requesting an interrupt.
 715          */
 716         ret = intel_ring_begin(ring, 32);
 717         if (ret)
 718                 return ret;
 719
 720         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 721                         PIPE_CONTROL_WRITE_FLUSH |
 722                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 723         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 724         intel_ring_emit(ring, ring->outstanding_lazy_request);
 725         intel_ring_emit(ring, 0);
 726         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 727         scratch_addr += 128; /* write to separate cachelines */
 728         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 729         scratch_addr += 128;
 730         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 731         scratch_addr += 128;
 732         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 733         scratch_addr += 128;
 734         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 735         scratch_addr += 128;
 736         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 737
 738         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 739                         PIPE_CONTROL_WRITE_FLUSH |
 740                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 741                         PIPE_CONTROL_NOTIFY);
 742         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 743         intel_ring_emit(ring, ring->outstanding_lazy_request);
 744         intel_ring_emit(ring, 0);
 745         intel_ring_advance(ring);
 746
 747         return 0;
 748 }
 749
 750 static u32
 751 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 752 {
 753         /* Workaround to force correct ordering between irq and seqno writes on
 754          * ivb (and maybe also on snb) by reading from a CS register (like
 755          * ACTHD) before reading the status page. */
 756         if (!lazy_coherency)
 757                 intel_ring_get_active_head(ring);
 758         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 759 }
 760
 761 static u32
 762 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 763 {
 764         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 765 }
 766
 767 static void
 768 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 769 {
 770         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 771 }
 772
 773 static u32
 774 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 775 {
 776         struct pipe_control *pc = ring->private;
 777         return pc->cpu_page[0];
 778 }
 779
 780 static void
 781 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 782 {
 783         struct pipe_control *pc = ring->private;
 784         pc->cpu_page[0] = seqno;
 785 }
 786
 787 static bool
 788 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 789 {
 790         struct drm_device *dev = ring->dev;
 791         drm_i915_private_t *dev_priv = dev->dev_private;
 792         unsigned long flags;
 793
 794         if (!dev->irq_enabled)
 795                 return false;
 796
 797         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 798         if (ring->irq_refcount.gt++ == 0) {
 799                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 800                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 801                 POSTING_READ(GTIMR);
 802         }
 803         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 804
 805         return true;
 806 }
 807
 808 static void
 809 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 810 {
 811         struct drm_device *dev = ring->dev;
 812         drm_i915_private_t *dev_priv = dev->dev_private;
 813         unsigned long flags;
 814
 815         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 816         if (--ring->irq_refcount.gt == 0) {
 817                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 818                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 819                 POSTING_READ(GTIMR);
 820         }
 821         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 822 }
 823
 824 static bool
 825 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 826 {
 827         struct drm_device *dev = ring->dev;
 828         drm_i915_private_t *dev_priv = dev->dev_private;
 829         unsigned long flags;
 830
 831         if (!dev->irq_enabled)
 832                 return false;
 833
 834         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 835         if (ring->irq_refcount.gt++ == 0) {
 836                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 837                 I915_WRITE(IMR, dev_priv->irq_mask);
 838                 POSTING_READ(IMR);
 839         }
 840         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 841
 842         return true;
 843 }
 844
 845 static void
 846 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 847 {
 848         struct drm_device *dev = ring->dev;
 849         drm_i915_private_t *dev_priv = dev->dev_private;
 850         unsigned long flags;
 851
 852         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 853         if (--ring->irq_refcount.gt == 0) {
 854                 dev_priv->irq_mask |= ring->irq_enable_mask;
 855                 I915_WRITE(IMR, dev_priv->irq_mask);
 856                 POSTING_READ(IMR);
 857         }
 858         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 859 }
 860
 861 static bool
 862 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 863 {
 864         struct drm_device *dev = ring->dev;
 865         drm_i915_private_t *dev_priv = dev->dev_private;
 866         unsigned long flags;
 867
 868         if (!dev->irq_enabled)
 869                 return false;
 870
 871         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 872         if (ring->irq_refcount.gt++ == 0) {
 873                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 874                 I915_WRITE16(IMR, dev_priv->irq_mask);
 875                 POSTING_READ16(IMR);
 876         }
 877         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 878
 879         return true;
 880 }
 881
 882 static void
 883 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 884 {
 885         struct drm_device *dev = ring->dev;
 886         drm_i915_private_t *dev_priv = dev->dev_private;
 887         unsigned long flags;
 888
 889         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 890         if (--ring->irq_refcount.gt == 0) {
 891                 dev_priv->irq_mask |= ring->irq_enable_mask;
 892                 I915_WRITE16(IMR, dev_priv->irq_mask);
 893                 POSTING_READ16(IMR);
 894         }
 895         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 896 }
 897
 898 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 899 {
 900         struct drm_device *dev = ring->dev;
 901         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 902         u32 mmio = 0;
 903
 904         /* The ring status page addresses are no longer next to the rest of
 905          * the ring registers as of gen7.
 906          */
 907         if (IS_GEN7(dev)) {
 908                 switch (ring->id) {
 909                 case RCS:
 910                         mmio = RENDER_HWS_PGA_GEN7;
 911                         break;
 912                 case BCS:
 913                         mmio = BLT_HWS_PGA_GEN7;
 914                         break;
 915                 case VCS:
 916                         mmio = BSD_HWS_PGA_GEN7;
 917                         break;
 918                 case VECS:
 919                         mmio = VEBOX_HWS_PGA_GEN7;
 920                         break;
 921                 }
 922         } else if (IS_GEN6(ring->dev)) {
 923                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 924         } else {
 925                 mmio = RING_HWS_PGA(ring->mmio_base);
 926         }
 927
 928         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 929         POSTING_READ(mmio);
 930 }
 931
 932 static int
 933 bsd_ring_flush(struct intel_ring_buffer *ring,
 934                u32     invalidate_domains,
 935                u32     flush_domains)
 936 {
 937         int ret;
 938
 939         ret = intel_ring_begin(ring, 2);
 940         if (ret)
 941                 return ret;
 942
 943         intel_ring_emit(ring, MI_FLUSH);
 944         intel_ring_emit(ring, MI_NOOP);
 945         intel_ring_advance(ring);
 946         return 0;
 947 }
 948
 949 static int
 950 i9xx_add_request(struct intel_ring_buffer *ring)
 951 {
 952         int ret;
 953
 954         ret = intel_ring_begin(ring, 4);
 955         if (ret)
 956                 return ret;
 957
 958         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 959         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 960         intel_ring_emit(ring, ring->outstanding_lazy_request);
 961         intel_ring_emit(ring, MI_USER_INTERRUPT);
 962         intel_ring_advance(ring);
 963
 964         return 0;
 965 }
 966
 967 static bool
 968 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 969 {
 970         struct drm_device *dev = ring->dev;
 971         drm_i915_private_t *dev_priv = dev->dev_private;
 972         unsigned long flags;
 973
 974         if (!dev->irq_enabled)
 975                return false;
 976
 977         /* It looks like we need to prevent the gt from suspending while waiting
 978          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 979          * blt/bsd rings on ivb. */
 980         gen6_gt_force_wake_get(dev_priv);
 981
 982         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 983         if (ring->irq_refcount.gt++ == 0) {
 984                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 985                         I915_WRITE_IMR(ring,
 986                                        ~(ring->irq_enable_mask |
 987                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
 988                 else
 989                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 990                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 991                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 992                 POSTING_READ(GTIMR);
 993         }
 994         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 995
 996         return true;
 997 }
 998
 999 static void
1000 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1001 {
1002         struct drm_device *dev = ring->dev;
1003         drm_i915_private_t *dev_priv = dev->dev_private;
1004         unsigned long flags;
1005
1006         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1007         if (--ring->irq_refcount.gt == 0) {
1008                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1009                         I915_WRITE_IMR(ring,
1010                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1011                 else
1012                         I915_WRITE_IMR(ring, ~0);
1013                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1014                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1015                 POSTING_READ(GTIMR);
1016         }
1017         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1018
1019         gen6_gt_force_wake_put(dev_priv);
1020 }
1021
1022 static bool
1023 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1024 {
1025         struct drm_device *dev = ring->dev;
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027         unsigned long flags;
1028
1029         if (!dev->irq_enabled)
1030                 return false;
1031
1032         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1033         if (ring->irq_refcount.pm++ == 0) {
1034                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1035                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1036                 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
1037                 POSTING_READ(GEN6_PMIMR);
1038         }
1039         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1040
1041         return true;
1042 }
1043
1044 static void
1045 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1046 {
1047         struct drm_device *dev = ring->dev;
1048         struct drm_i915_private *dev_priv = dev->dev_private;
1049         unsigned long flags;
1050
1051         if (!dev->irq_enabled)
1052                 return;
1053
1054         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1055         if (--ring->irq_refcount.pm == 0) {
1056                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1057                 I915_WRITE_IMR(ring, ~0);
1058                 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
1059                 POSTING_READ(GEN6_PMIMR);
1060         }
1061         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1062 }
1063
1064 static int
1065 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1066                          u32 offset, u32 length,
1067                          unsigned flags)
1068 {
1069         int ret;
1070
1071         ret = intel_ring_begin(ring, 2);
1072         if (ret)
1073                 return ret;
1074
1075         intel_ring_emit(ring,
1076                         MI_BATCH_BUFFER_START |
1077                         MI_BATCH_GTT |
1078                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1079         intel_ring_emit(ring, offset);
1080         intel_ring_advance(ring);
1081
1082         return 0;
1083 }
1084
1085 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1086 #define I830_BATCH_LIMIT (256*1024)
1087 static int
1088 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1089                                 u32 offset, u32 len,
1090                                 unsigned flags)
1091 {
1092         int ret;
1093
1094         if (flags & I915_DISPATCH_PINNED) {
1095                 ret = intel_ring_begin(ring, 4);
1096                 if (ret)
1097                         return ret;
1098
1099                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1100                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1101                 intel_ring_emit(ring, offset + len - 8);
1102                 intel_ring_emit(ring, MI_NOOP);
1103                 intel_ring_advance(ring);
1104         } else {
1105                 struct drm_i915_gem_object *obj = ring->private;
1106                 u32 cs_offset = obj->gtt_offset;
1107
1108                 if (len > I830_BATCH_LIMIT)
1109                         return -ENOSPC;
1110
1111                 ret = intel_ring_begin(ring, 9+3);
1112                 if (ret)
1113                         return ret;
1114                 /* Blit the batch (which has now all relocs applied) to the stable batch
1115                  * scratch bo area (so that the CS never stumbles over its tlb
1116                  * invalidation bug) ... */
1117                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1118                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1119                                 XY_SRC_COPY_BLT_WRITE_RGB);
1120                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1121                 intel_ring_emit(ring, 0);
1122                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1123                 intel_ring_emit(ring, cs_offset);
1124                 intel_ring_emit(ring, 0);
1125                 intel_ring_emit(ring, 4096);
1126                 intel_ring_emit(ring, offset);
1127                 intel_ring_emit(ring, MI_FLUSH);
1128
1129                 /* ... and execute it. */
1130                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1131                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1132                 intel_ring_emit(ring, cs_offset + len - 8);
1133                 intel_ring_advance(ring);
1134         }
1135
1136         return 0;
1137 }
1138
1139 static int
1140 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1141                          u32 offset, u32 len,
1142                          unsigned flags)
1143 {
1144         int ret;
1145
1146         ret = intel_ring_begin(ring, 2);
1147         if (ret)
1148                 return ret;
1149
1150         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1151         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1152         intel_ring_advance(ring);
1153
1154         return 0;
1155 }
1156
1157 static void cleanup_status_page(struct intel_ring_buffer *ring)
1158 {
1159         struct drm_i915_gem_object *obj;
1160
1161         obj = ring->status_page.obj;
1162         if (obj == NULL)
1163                 return;
1164
1165         kunmap(sg_page(obj->pages->sgl));
1166         i915_gem_object_unpin(obj);
1167         drm_gem_object_unreference(&obj->base);
1168         ring->status_page.obj = NULL;
1169 }
1170
1171 static int init_status_page(struct intel_ring_buffer *ring)
1172 {
1173         struct drm_device *dev = ring->dev;
1174         struct drm_i915_gem_object *obj;
1175         int ret;
1176
1177         obj = i915_gem_alloc_object(dev, 4096);
1178         if (obj == NULL) {
1179                 DRM_ERROR("Failed to allocate status page\n");
1180                 ret = -ENOMEM;
1181                 goto err;
1182         }
1183
1184         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1185
1186         ret = i915_gem_object_pin(obj, 4096, true, false);
1187         if (ret != 0) {
1188                 goto err_unref;
1189         }
1190
1191         ring->status_page.gfx_addr = obj->gtt_offset;
1192         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1193         if (ring->status_page.page_addr == NULL) {
1194                 ret = -ENOMEM;
1195                 goto err_unpin;
1196         }
1197         ring->status_page.obj = obj;
1198         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1199
1200         intel_ring_setup_status_page(ring);
1201         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1202                         ring->name, ring->status_page.gfx_addr);
1203
1204         return 0;
1205
1206 err_unpin:
1207         i915_gem_object_unpin(obj);
1208 err_unref:
1209         drm_gem_object_unreference(&obj->base);
1210 err:
1211         return ret;
1212 }
1213
1214 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1215 {
1216         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1217         u32 addr;
1218
1219         if (!dev_priv->status_page_dmah) {
1220                 dev_priv->status_page_dmah =
1221                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1222                 if (!dev_priv->status_page_dmah)
1223                         return -ENOMEM;
1224         }
1225
1226         addr = dev_priv->status_page_dmah->busaddr;
1227         if (INTEL_INFO(ring->dev)->gen >= 4)
1228                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1229         I915_WRITE(HWS_PGA, addr);
1230
1231         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1232         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1233
1234         return 0;
1235 }
1236
1237 static int intel_init_ring_buffer(struct drm_device *dev,
1238                                   struct intel_ring_buffer *ring)
1239 {
1240         struct drm_i915_gem_object *obj;
1241         struct drm_i915_private *dev_priv = dev->dev_private;
1242         int ret;
1243
1244         ring->dev = dev;
1245         INIT_LIST_HEAD(&ring->active_list);
1246         INIT_LIST_HEAD(&ring->request_list);
1247         ring->size = 32 * PAGE_SIZE;
1248         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1249
1250         init_waitqueue_head(&ring->irq_queue);
1251
1252         if (I915_NEED_GFX_HWS(dev)) {
1253                 ret = init_status_page(ring);
1254                 if (ret)
1255                         return ret;
1256         } else {
1257                 BUG_ON(ring->id != RCS);
1258                 ret = init_phys_hws_pga(ring);
1259                 if (ret)
1260                         return ret;
1261         }
1262
1263         obj = NULL;
1264         if (!HAS_LLC(dev))
1265                 obj = i915_gem_object_create_stolen(dev, ring->size);
1266         if (obj == NULL)
1267                 obj = i915_gem_alloc_object(dev, ring->size);
1268         if (obj == NULL) {
1269                 DRM_ERROR("Failed to allocate ringbuffer\n");
1270                 ret = -ENOMEM;
1271                 goto err_hws;
1272         }
1273
1274         ring->obj = obj;
1275
1276         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1277         if (ret)
1278                 goto err_unref;
1279
1280         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1281         if (ret)
1282                 goto err_unpin;
1283
1284         ring->virtual_start =
1285                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1286                            ring->size);
1287         if (ring->virtual_start == NULL) {
1288                 DRM_ERROR("Failed to map ringbuffer.\n");
1289                 ret = -EINVAL;
1290                 goto err_unpin;
1291         }
1292
1293         ret = ring->init(ring);
1294         if (ret)
1295                 goto err_unmap;
1296
1297         /* Workaround an erratum on the i830 which causes a hang if
1298          * the TAIL pointer points to within the last 2 cachelines
1299          * of the buffer.
1300          */
1301         ring->effective_size = ring->size;
1302         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1303                 ring->effective_size -= 128;
1304
1305         return 0;
1306
1307 err_unmap:
1308         iounmap(ring->virtual_start);
1309 err_unpin:
1310         i915_gem_object_unpin(obj);
1311 err_unref:
1312         drm_gem_object_unreference(&obj->base);
1313         ring->obj = NULL;
1314 err_hws:
1315         cleanup_status_page(ring);
1316         return ret;
1317 }
1318
1319 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1320 {
1321         struct drm_i915_private *dev_priv;
1322         int ret;
1323
1324         if (ring->obj == NULL)
1325                 return;
1326
1327         /* Disable the ring buffer. The ring must be idle at this point */
1328         dev_priv = ring->dev->dev_private;
1329         ret = intel_ring_idle(ring);
1330         if (ret)
1331                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1332                           ring->name, ret);
1333
1334         I915_WRITE_CTL(ring, 0);
1335
1336         iounmap(ring->virtual_start);
1337
1338         i915_gem_object_unpin(ring->obj);
1339         drm_gem_object_unreference(&ring->obj->base);
1340         ring->obj = NULL;
1341
1342         if (ring->cleanup)
1343                 ring->cleanup(ring);
1344
1345         cleanup_status_page(ring);
1346 }
1347
1348 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1349 {
1350         int ret;
1351
1352         ret = i915_wait_seqno(ring, seqno);
1353         if (!ret)
1354                 i915_gem_retire_requests_ring(ring);
1355
1356         return ret;
1357 }
1358
1359 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1360 {
1361         struct drm_i915_gem_request *request;
1362         u32 seqno = 0;
1363         int ret;
1364
1365         i915_gem_retire_requests_ring(ring);
1366
1367         if (ring->last_retired_head != -1) {
1368                 ring->head = ring->last_retired_head;
1369                 ring->last_retired_head = -1;
1370                 ring->space = ring_space(ring);
1371                 if (ring->space >= n)
1372                         return 0;
1373         }
1374
1375         list_for_each_entry(request, &ring->request_list, list) {
1376                 int space;
1377
1378                 if (request->tail == -1)
1379                         continue;
1380
1381                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1382                 if (space < 0)
1383                         space += ring->size;
1384                 if (space >= n) {
1385                         seqno = request->seqno;
1386                         break;
1387                 }
1388
1389                 /* Consume this request in case we need more space than
1390                  * is available and so need to prevent a race between
1391                  * updating last_retired_head and direct reads of
1392                  * I915_RING_HEAD. It also provides a nice sanity check.
1393                  */
1394                 request->tail = -1;
1395         }
1396
1397         if (seqno == 0)
1398                 return -ENOSPC;
1399
1400         ret = intel_ring_wait_seqno(ring, seqno);
1401         if (ret)
1402                 return ret;
1403
1404         if (WARN_ON(ring->last_retired_head == -1))
1405                 return -ENOSPC;
1406
1407         ring->head = ring->last_retired_head;
1408         ring->last_retired_head = -1;
1409         ring->space = ring_space(ring);
1410         if (WARN_ON(ring->space < n))
1411                 return -ENOSPC;
1412
1413         return 0;
1414 }
1415
1416 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1417 {
1418         struct drm_device *dev = ring->dev;
1419         struct drm_i915_private *dev_priv = dev->dev_private;
1420         unsigned long end;
1421         int ret;
1422
1423         ret = intel_ring_wait_request(ring, n);
1424         if (ret != -ENOSPC)
1425                 return ret;
1426
1427         trace_i915_ring_wait_begin(ring);
1428         /* With GEM the hangcheck timer should kick us out of the loop,
1429          * leaving it early runs the risk of corrupting GEM state (due
1430          * to running on almost untested codepaths). But on resume
1431          * timers don't work yet, so prevent a complete hang in that
1432          * case by choosing an insanely large timeout. */
1433         end = jiffies + 60 * HZ;
1434
1435         do {
1436                 ring->head = I915_READ_HEAD(ring);
1437                 ring->space = ring_space(ring);
1438                 if (ring->space >= n) {
1439                         trace_i915_ring_wait_end(ring);
1440                         return 0;
1441                 }
1442
1443                 if (dev->primary->master) {
1444                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1445                         if (master_priv->sarea_priv)
1446                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1447                 }
1448
1449                 msleep(1);
1450
1451                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1452                                            dev_priv->mm.interruptible);
1453                 if (ret)
1454                         return ret;
1455         } while (!time_after(jiffies, end));
1456         trace_i915_ring_wait_end(ring);
1457         return -EBUSY;
1458 }
1459
1460 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1461 {
1462         uint32_t __iomem *virt;
1463         int rem = ring->size - ring->tail;
1464
1465         if (ring->space < rem) {
1466                 int ret = ring_wait_for_space(ring, rem);
1467                 if (ret)
1468                         return ret;
1469         }
1470
1471         virt = ring->virtual_start + ring->tail;
1472         rem /= 4;
1473         while (rem--)
1474                 iowrite32(MI_NOOP, virt++);
1475
1476         ring->tail = 0;
1477         ring->space = ring_space(ring);
1478
1479         return 0;
1480 }
1481
1482 int intel_ring_idle(struct intel_ring_buffer *ring)
1483 {
1484         u32 seqno;
1485         int ret;
1486
1487         /* We need to add any requests required to flush the objects and ring */
1488         if (ring->outstanding_lazy_request) {
1489                 ret = i915_add_request(ring, NULL, NULL);
1490                 if (ret)
1491                         return ret;
1492         }
1493
1494         /* Wait upon the last request to be completed */
1495         if (list_empty(&ring->request_list))
1496                 return 0;
1497
1498         seqno = list_entry(ring->request_list.prev,
1499                            struct drm_i915_gem_request,
1500                            list)->seqno;
1501
1502         return i915_wait_seqno(ring, seqno);
1503 }
1504
1505 static int
1506 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1507 {
1508         if (ring->outstanding_lazy_request)
1509                 return 0;
1510
1511         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1512 }
1513
1514 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1515                               int bytes)
1516 {
1517         int ret;
1518
1519         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1520                 ret = intel_wrap_ring_buffer(ring);
1521                 if (unlikely(ret))
1522                         return ret;
1523         }
1524
1525         if (unlikely(ring->space < bytes)) {
1526                 ret = ring_wait_for_space(ring, bytes);
1527                 if (unlikely(ret))
1528                         return ret;
1529         }
1530
1531         ring->space -= bytes;
1532         return 0;
1533 }
1534
1535 int intel_ring_begin(struct intel_ring_buffer *ring,
1536                      int num_dwords)
1537 {
1538         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1539         int ret;
1540
1541         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1542                                    dev_priv->mm.interruptible);
1543         if (ret)
1544                 return ret;
1545
1546         /* Preallocate the olr before touching the ring */
1547         ret = intel_ring_alloc_seqno(ring);
1548         if (ret)
1549                 return ret;
1550
1551         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1552 }
1553
1554 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1555 {
1556         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1557
1558         BUG_ON(ring->outstanding_lazy_request);
1559
1560         if (INTEL_INFO(ring->dev)->gen >= 6) {
1561                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1562                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1563         }
1564
1565         ring->set_seqno(ring, seqno);
1566         ring->hangcheck.seqno = seqno;
1567 }
1568
1569 void intel_ring_advance(struct intel_ring_buffer *ring)
1570 {
1571         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1572
1573         ring->tail &= ring->size - 1;
1574         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1575                 return;
1576         ring->write_tail(ring, ring->tail);
1577 }
1578
1579
1580 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1581                                      u32 value)
1582 {
1583         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1584
1585        /* Every tail move must follow the sequence below */
1586
1587         /* Disable notification that the ring is IDLE. The GT
1588          * will then assume that it is busy and bring it out of rc6.
1589          */
1590         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1591                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1592
1593         /* Clear the context id. Here be magic! */
1594         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1595
1596         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1597         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1598                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1599                      50))
1600                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1601
1602         /* Now that the ring is fully powered up, update the tail */
1603         I915_WRITE_TAIL(ring, value);
1604         POSTING_READ(RING_TAIL(ring->mmio_base));
1605
1606         /* Let the ring send IDLE messages to the GT again,
1607          * and so let it sleep to conserve power when idle.
1608          */
1609         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1610                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1611 }
1612
1613 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1614                                u32 invalidate, u32 flush)
1615 {
1616         uint32_t cmd;
1617         int ret;
1618
1619         ret = intel_ring_begin(ring, 4);
1620         if (ret)
1621                 return ret;
1622
1623         cmd = MI_FLUSH_DW;
1624         /*
1625          * Bspec vol 1c.5 - video engine command streamer:
1626          * "If ENABLED, all TLBs will be invalidated once the flush
1627          * operation is complete. This bit is only valid when the
1628          * Post-Sync Operation field is a value of 1h or 3h."
1629          */
1630         if (invalidate & I915_GEM_GPU_DOMAINS)
1631                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1632                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1633         intel_ring_emit(ring, cmd);
1634         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1635         intel_ring_emit(ring, 0);
1636         intel_ring_emit(ring, MI_NOOP);
1637         intel_ring_advance(ring);
1638         return 0;
1639 }
1640
1641 static int
1642 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1643                               u32 offset, u32 len,
1644                               unsigned flags)
1645 {
1646         int ret;
1647
1648         ret = intel_ring_begin(ring, 2);
1649         if (ret)
1650                 return ret;
1651
1652         intel_ring_emit(ring,
1653                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1654                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1655         /* bit0-7 is the length on GEN6+ */
1656         intel_ring_emit(ring, offset);
1657         intel_ring_advance(ring);
1658
1659         return 0;
1660 }
1661
1662 static int
1663 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1664                               u32 offset, u32 len,
1665                               unsigned flags)
1666 {
1667         int ret;
1668
1669         ret = intel_ring_begin(ring, 2);
1670         if (ret)
1671                 return ret;
1672
1673         intel_ring_emit(ring,
1674                         MI_BATCH_BUFFER_START |
1675                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1676         /* bit0-7 is the length on GEN6+ */
1677         intel_ring_emit(ring, offset);
1678         intel_ring_advance(ring);
1679
1680         return 0;
1681 }
1682
1683 /* Blitter support (SandyBridge+) */
1684
1685 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1686                            u32 invalidate, u32 flush)
1687 {
1688         uint32_t cmd;
1689         int ret;
1690
1691         ret = intel_ring_begin(ring, 4);
1692         if (ret)
1693                 return ret;
1694
1695         cmd = MI_FLUSH_DW;
1696         /*
1697          * Bspec vol 1c.3 - blitter engine command streamer:
1698          * "If ENABLED, all TLBs will be invalidated once the flush
1699          * operation is complete. This bit is only valid when the
1700          * Post-Sync Operation field is a value of 1h or 3h."
1701          */
1702         if (invalidate & I915_GEM_DOMAIN_RENDER)
1703                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1704                         MI_FLUSH_DW_OP_STOREDW;
1705         intel_ring_emit(ring, cmd);
1706         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1707         intel_ring_emit(ring, 0);
1708         intel_ring_emit(ring, MI_NOOP);
1709         intel_ring_advance(ring);
1710         return 0;
1711 }
1712
1713 int intel_init_render_ring_buffer(struct drm_device *dev)
1714 {
1715         drm_i915_private_t *dev_priv = dev->dev_private;
1716         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1717
1718         ring->name = "render ring";
1719         ring->id = RCS;
1720         ring->mmio_base = RENDER_RING_BASE;
1721
1722         if (INTEL_INFO(dev)->gen >= 6) {
1723                 ring->add_request = gen6_add_request;
1724                 ring->flush = gen7_render_ring_flush;
1725                 if (INTEL_INFO(dev)->gen == 6)
1726                         ring->flush = gen6_render_ring_flush;
1727                 ring->irq_get = gen6_ring_get_irq;
1728                 ring->irq_put = gen6_ring_put_irq;
1729                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1730                 ring->get_seqno = gen6_ring_get_seqno;
1731                 ring->set_seqno = ring_set_seqno;
1732                 ring->sync_to = gen6_ring_sync;
1733                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1734                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1735                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1736                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1737                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1738                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1739                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1740                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1741         } else if (IS_GEN5(dev)) {
1742                 ring->add_request = pc_render_add_request;
1743                 ring->flush = gen4_render_ring_flush;
1744                 ring->get_seqno = pc_render_get_seqno;
1745                 ring->set_seqno = pc_render_set_seqno;
1746                 ring->irq_get = gen5_ring_get_irq;
1747                 ring->irq_put = gen5_ring_put_irq;
1748                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1749                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1750         } else {
1751                 ring->add_request = i9xx_add_request;
1752                 if (INTEL_INFO(dev)->gen < 4)
1753                         ring->flush = gen2_render_ring_flush;
1754                 else
1755                         ring->flush = gen4_render_ring_flush;
1756                 ring->get_seqno = ring_get_seqno;
1757                 ring->set_seqno = ring_set_seqno;
1758                 if (IS_GEN2(dev)) {
1759                         ring->irq_get = i8xx_ring_get_irq;
1760                         ring->irq_put = i8xx_ring_put_irq;
1761                 } else {
1762                         ring->irq_get = i9xx_ring_get_irq;
1763                         ring->irq_put = i9xx_ring_put_irq;
1764                 }
1765                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1766         }
1767         ring->write_tail = ring_write_tail;
1768         if (IS_HASWELL(dev))
1769                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1770         else if (INTEL_INFO(dev)->gen >= 6)
1771                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1772         else if (INTEL_INFO(dev)->gen >= 4)
1773                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1774         else if (IS_I830(dev) || IS_845G(dev))
1775                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1776         else
1777                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1778         ring->init = init_render_ring;
1779         ring->cleanup = render_ring_cleanup;
1780
1781         /* Workaround batchbuffer to combat CS tlb bug. */
1782         if (HAS_BROKEN_CS_TLB(dev)) {
1783                 struct drm_i915_gem_object *obj;
1784                 int ret;
1785
1786                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1787                 if (obj == NULL) {
1788                         DRM_ERROR("Failed to allocate batch bo\n");
1789                         return -ENOMEM;
1790                 }
1791
1792                 ret = i915_gem_object_pin(obj, 0, true, false);
1793                 if (ret != 0) {
1794                         drm_gem_object_unreference(&obj->base);
1795                         DRM_ERROR("Failed to ping batch bo\n");
1796                         return ret;
1797                 }
1798
1799                 ring->private = obj;
1800         }
1801
1802         return intel_init_ring_buffer(dev, ring);
1803 }
1804
1805 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1806 {
1807         drm_i915_private_t *dev_priv = dev->dev_private;
1808         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1809         int ret;
1810
1811         ring->name = "render ring";
1812         ring->id = RCS;
1813         ring->mmio_base = RENDER_RING_BASE;
1814
1815         if (INTEL_INFO(dev)->gen >= 6) {
1816                 /* non-kms not supported on gen6+ */
1817                 return -ENODEV;
1818         }
1819
1820         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1821          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1822          * the special gen5 functions. */
1823         ring->add_request = i9xx_add_request;
1824         if (INTEL_INFO(dev)->gen < 4)
1825                 ring->flush = gen2_render_ring_flush;
1826         else
1827                 ring->flush = gen4_render_ring_flush;
1828         ring->get_seqno = ring_get_seqno;
1829         ring->set_seqno = ring_set_seqno;
1830         if (IS_GEN2(dev)) {
1831                 ring->irq_get = i8xx_ring_get_irq;
1832                 ring->irq_put = i8xx_ring_put_irq;
1833         } else {
1834                 ring->irq_get = i9xx_ring_get_irq;
1835                 ring->irq_put = i9xx_ring_put_irq;
1836         }
1837         ring->irq_enable_mask = I915_USER_INTERRUPT;
1838         ring->write_tail = ring_write_tail;
1839         if (INTEL_INFO(dev)->gen >= 4)
1840                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1841         else if (IS_I830(dev) || IS_845G(dev))
1842                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1843         else
1844                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1845         ring->init = init_render_ring;
1846         ring->cleanup = render_ring_cleanup;
1847
1848         ring->dev = dev;
1849         INIT_LIST_HEAD(&ring->active_list);
1850         INIT_LIST_HEAD(&ring->request_list);
1851
1852         ring->size = size;
1853         ring->effective_size = ring->size;
1854         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1855                 ring->effective_size -= 128;
1856
1857         ring->virtual_start = ioremap_wc(start, size);
1858         if (ring->virtual_start == NULL) {
1859                 DRM_ERROR("can not ioremap virtual address for"
1860                           " ring buffer\n");
1861                 return -ENOMEM;
1862         }
1863
1864         if (!I915_NEED_GFX_HWS(dev)) {
1865                 ret = init_phys_hws_pga(ring);
1866                 if (ret)
1867                         return ret;
1868         }
1869
1870         return 0;
1871 }
1872
1873 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1874 {
1875         drm_i915_private_t *dev_priv = dev->dev_private;
1876         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1877
1878         ring->name = "bsd ring";
1879         ring->id = VCS;
1880
1881         ring->write_tail = ring_write_tail;
1882         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1883                 ring->mmio_base = GEN6_BSD_RING_BASE;
1884                 /* gen6 bsd needs a special wa for tail updates */
1885                 if (IS_GEN6(dev))
1886                         ring->write_tail = gen6_bsd_ring_write_tail;
1887                 ring->flush = gen6_bsd_ring_flush;
1888                 ring->add_request = gen6_add_request;
1889                 ring->get_seqno = gen6_ring_get_seqno;
1890                 ring->set_seqno = ring_set_seqno;
1891                 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1892                 ring->irq_get = gen6_ring_get_irq;
1893                 ring->irq_put = gen6_ring_put_irq;
1894                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1895                 ring->sync_to = gen6_ring_sync;
1896                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1897                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1898                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1899                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1900                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1901                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1902                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1903                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1904         } else {
1905                 ring->mmio_base = BSD_RING_BASE;
1906                 ring->flush = bsd_ring_flush;
1907                 ring->add_request = i9xx_add_request;
1908                 ring->get_seqno = ring_get_seqno;
1909                 ring->set_seqno = ring_set_seqno;
1910                 if (IS_GEN5(dev)) {
1911                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1912                         ring->irq_get = gen5_ring_get_irq;
1913                         ring->irq_put = gen5_ring_put_irq;
1914                 } else {
1915                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1916                         ring->irq_get = i9xx_ring_get_irq;
1917                         ring->irq_put = i9xx_ring_put_irq;
1918                 }
1919                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1920         }
1921         ring->init = init_ring_common;
1922
1923         return intel_init_ring_buffer(dev, ring);
1924 }
1925
1926 int intel_init_blt_ring_buffer(struct drm_device *dev)
1927 {
1928         drm_i915_private_t *dev_priv = dev->dev_private;
1929         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1930
1931         ring->name = "blitter ring";
1932         ring->id = BCS;
1933
1934         ring->mmio_base = BLT_RING_BASE;
1935         ring->write_tail = ring_write_tail;
1936         ring->flush = gen6_ring_flush;
1937         ring->add_request = gen6_add_request;
1938         ring->get_seqno = gen6_ring_get_seqno;
1939         ring->set_seqno = ring_set_seqno;
1940         ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1941         ring->irq_get = gen6_ring_get_irq;
1942         ring->irq_put = gen6_ring_put_irq;
1943         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1944         ring->sync_to = gen6_ring_sync;
1945         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1946         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1947         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1948         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1949         ring->signal_mbox[RCS] = GEN6_RBSYNC;
1950         ring->signal_mbox[VCS] = GEN6_VBSYNC;
1951         ring->signal_mbox[BCS] = GEN6_NOSYNC;
1952         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1953         ring->init = init_ring_common;
1954
1955         return intel_init_ring_buffer(dev, ring);
1956 }
1957
1958 int intel_init_vebox_ring_buffer(struct drm_device *dev)
1959 {
1960         drm_i915_private_t *dev_priv = dev->dev_private;
1961         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
1962
1963         ring->name = "video enhancement ring";
1964         ring->id = VECS;
1965
1966         ring->mmio_base = VEBOX_RING_BASE;
1967         ring->write_tail = ring_write_tail;
1968         ring->flush = gen6_ring_flush;
1969         ring->add_request = gen6_add_request;
1970         ring->get_seqno = gen6_ring_get_seqno;
1971         ring->set_seqno = ring_set_seqno;
1972         ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT |
1973                 PM_VEBOX_CS_ERROR_INTERRUPT;
1974         ring->irq_get = hsw_vebox_get_irq;
1975         ring->irq_put = hsw_vebox_put_irq;
1976         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1977         ring->sync_to = gen6_ring_sync;
1978         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
1979         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
1980         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
1981         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
1982         ring->signal_mbox[RCS] = GEN6_RVESYNC;
1983         ring->signal_mbox[VCS] = GEN6_VVESYNC;
1984         ring->signal_mbox[BCS] = GEN6_BVESYNC;
1985         ring->signal_mbox[VECS] = GEN6_NOSYNC;
1986         ring->init = init_ring_common;
1987
1988         return intel_init_ring_buffer(dev, ring);
1989 }
1990
1991 int
1992 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1993 {
1994         int ret;
1995
1996         if (!ring->gpu_caches_dirty)
1997                 return 0;
1998
1999         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2000         if (ret)
2001                 return ret;
2002
2003         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2004
2005         ring->gpu_caches_dirty = false;
2006         return 0;
2007 }
2008
2009 int
2010 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2011 {
2012         uint32_t flush_domains;
2013         int ret;
2014
2015         flush_domains = 0;
2016         if (ring->gpu_caches_dirty)
2017                 flush_domains = I915_GEM_GPU_DOMAINS;
2018
2019         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2020         if (ret)
2021                 return ret;
2022
2023         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2024
2025         ring->gpu_caches_dirty = false;
2026         return 0;
2027 }