drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 static inline int ring_space(struct intel_ring_buffer *ring)
  37 {
  38         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  39         if (space < 0)
  40                 space += ring->size;
  41         return space;
  42 }
  43
  44 void __intel_ring_advance(struct intel_ring_buffer *ring)
  45 {
  46         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  47
  48         ring->tail &= ring->size - 1;
  49         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
  50                 return;
  51         ring->write_tail(ring, ring->tail);
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 179         int ret;
 180
 181
 182         ret = intel_ring_begin(ring, 6);
 183         if (ret)
 184                 return ret;
 185
 186         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 187         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 188                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 189         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 190         intel_ring_emit(ring, 0); /* low dword */
 191         intel_ring_emit(ring, 0); /* high dword */
 192         intel_ring_emit(ring, MI_NOOP);
 193         intel_ring_advance(ring);
 194
 195         ret = intel_ring_begin(ring, 6);
 196         if (ret)
 197                 return ret;
 198
 199         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 200         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 201         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, MI_NOOP);
 205         intel_ring_advance(ring);
 206
 207         return 0;
 208 }
 209
 210 static int
 211 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 212                          u32 invalidate_domains, u32 flush_domains)
 213 {
 214         u32 flags = 0;
 215         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 216         int ret;
 217
 218         /* Force SNB workarounds for PIPE_CONTROL flushes */
 219         ret = intel_emit_post_sync_nonzero_flush(ring);
 220         if (ret)
 221                 return ret;
 222
 223         /* Just flush everything.  Experiments have shown that reducing the
 224          * number of bits based on the write domains has little performance
 225          * impact.
 226          */
 227         if (flush_domains) {
 228                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 229                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 230                 /*
 231                  * Ensure that any following seqno writes only happen
 232                  * when the render cache is indeed flushed.
 233                  */
 234                 flags |= PIPE_CONTROL_CS_STALL;
 235         }
 236         if (invalidate_domains) {
 237                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 238                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 239                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 240                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 243                 /*
 244                  * TLB invalidate requires a post-sync write.
 245                  */
 246                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 247         }
 248
 249         ret = intel_ring_begin(ring, 4);
 250         if (ret)
 251                 return ret;
 252
 253         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 254         intel_ring_emit(ring, flags);
 255         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 256         intel_ring_emit(ring, 0);
 257         intel_ring_advance(ring);
 258
 259         return 0;
 260 }
 261
 262 static int
 263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 264 {
 265         int ret;
 266
 267         ret = intel_ring_begin(ring, 4);
 268         if (ret)
 269                 return ret;
 270
 271         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 272         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 273                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 274         intel_ring_emit(ring, 0);
 275         intel_ring_emit(ring, 0);
 276         intel_ring_advance(ring);
 277
 278         return 0;
 279 }
 280
 281 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 282 {
 283         int ret;
 284
 285         if (!ring->fbc_dirty)
 286                 return 0;
 287
 288         ret = intel_ring_begin(ring, 4);
 289         if (ret)
 290                 return ret;
 291         intel_ring_emit(ring, MI_NOOP);
 292         /* WaFbcNukeOn3DBlt:ivb/hsw */
 293         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 294         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 295         intel_ring_emit(ring, value);
 296         intel_ring_advance(ring);
 297
 298         ring->fbc_dirty = false;
 299         return 0;
 300 }
 301
 302 static int
 303 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 304                        u32 invalidate_domains, u32 flush_domains)
 305 {
 306         u32 flags = 0;
 307         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 308         int ret;
 309
 310         /*
 311          * Ensure that any following seqno writes only happen when the render
 312          * cache is indeed flushed.
 313          *
 314          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 315          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 316          * don't try to be clever and just set it unconditionally.
 317          */
 318         flags |= PIPE_CONTROL_CS_STALL;
 319
 320         /* Just flush everything.  Experiments have shown that reducing the
 321          * number of bits based on the write domains has little performance
 322          * impact.
 323          */
 324         if (flush_domains) {
 325                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 326                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 327         }
 328         if (invalidate_domains) {
 329                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 330                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 331                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 332                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 333                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 335                 /*
 336                  * TLB invalidate requires a post-sync write.
 337                  */
 338                 flags |= PIPE_CONTROL_QW_WRITE;
 339                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 340
 341                 /* Workaround: we must issue a pipe_control with CS-stall bit
 342                  * set before a pipe_control command that has the state cache
 343                  * invalidate bit set. */
 344                 gen7_render_ring_cs_stall_wa(ring);
 345         }
 346
 347         ret = intel_ring_begin(ring, 4);
 348         if (ret)
 349                 return ret;
 350
 351         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 352         intel_ring_emit(ring, flags);
 353         intel_ring_emit(ring, scratch_addr);
 354         intel_ring_emit(ring, 0);
 355         intel_ring_advance(ring);
 356
 357         if (flush_domains)
 358                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 359
 360         return 0;
 361 }
 362
 363 static void ring_write_tail(struct intel_ring_buffer *ring,
 364                             u32 value)
 365 {
 366         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 367         I915_WRITE_TAIL(ring, value);
 368 }
 369
 370 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 371 {
 372         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 373         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 374                         RING_ACTHD(ring->mmio_base) : ACTHD;
 375
 376         return I915_READ(acthd_reg);
 377 }
 378
 379 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 380 {
 381         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 382         u32 addr;
 383
 384         addr = dev_priv->status_page_dmah->busaddr;
 385         if (INTEL_INFO(ring->dev)->gen >= 4)
 386                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 387         I915_WRITE(HWS_PGA, addr);
 388 }
 389
 390 static int init_ring_common(struct intel_ring_buffer *ring)
 391 {
 392         struct drm_device *dev = ring->dev;
 393         drm_i915_private_t *dev_priv = dev->dev_private;
 394         struct drm_i915_gem_object *obj = ring->obj;
 395         int ret = 0;
 396         u32 head;
 397
 398         gen6_gt_force_wake_get(dev_priv);
 399
 400         if (I915_NEED_GFX_HWS(dev))
 401                 intel_ring_setup_status_page(ring);
 402         else
 403                 ring_setup_phys_status_page(ring);
 404
 405         /* Stop the ring if it's running. */
 406         I915_WRITE_CTL(ring, 0);
 407         I915_WRITE_HEAD(ring, 0);
 408         ring->write_tail(ring, 0);
 409
 410         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 411
 412         /* G45 ring initialization fails to reset head to zero */
 413         if (head != 0) {
 414                 DRM_DEBUG_KMS("%s head not reset to zero "
 415                               "ctl %08x head %08x tail %08x start %08x\n",
 416                               ring->name,
 417                               I915_READ_CTL(ring),
 418                               I915_READ_HEAD(ring),
 419                               I915_READ_TAIL(ring),
 420                               I915_READ_START(ring));
 421
 422                 I915_WRITE_HEAD(ring, 0);
 423
 424                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 425                         DRM_ERROR("failed to set %s head to zero "
 426                                   "ctl %08x head %08x tail %08x start %08x\n",
 427                                   ring->name,
 428                                   I915_READ_CTL(ring),
 429                                   I915_READ_HEAD(ring),
 430                                   I915_READ_TAIL(ring),
 431                                   I915_READ_START(ring));
 432                 }
 433         }
 434
 435         /* Initialize the ring. This must happen _after_ we've cleared the ring
 436          * registers with the above sequence (the readback of the HEAD registers
 437          * also enforces ordering), otherwise the hw might lose the new ring
 438          * register values. */
 439         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 440         I915_WRITE_CTL(ring,
 441                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 442                         | RING_VALID);
 443
 444         /* If the head is still not zero, the ring is dead */
 445         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 446                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 447                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 448                 DRM_ERROR("%s initialization failed "
 449                                 "ctl %08x head %08x tail %08x start %08x\n",
 450                                 ring->name,
 451                                 I915_READ_CTL(ring),
 452                                 I915_READ_HEAD(ring),
 453                                 I915_READ_TAIL(ring),
 454                                 I915_READ_START(ring));
 455                 ret = -EIO;
 456                 goto out;
 457         }
 458
 459         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 460                 i915_kernel_lost_context(ring->dev);
 461         else {
 462                 ring->head = I915_READ_HEAD(ring);
 463                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 464                 ring->space = ring_space(ring);
 465                 ring->last_retired_head = -1;
 466         }
 467
 468         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 469
 470 out:
 471         gen6_gt_force_wake_put(dev_priv);
 472
 473         return ret;
 474 }
 475
 476 static int
 477 init_pipe_control(struct intel_ring_buffer *ring)
 478 {
 479         int ret;
 480
 481         if (ring->scratch.obj)
 482                 return 0;
 483
 484         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 485         if (ring->scratch.obj == NULL) {
 486                 DRM_ERROR("Failed to allocate seqno page\n");
 487                 ret = -ENOMEM;
 488                 goto err;
 489         }
 490
 491         i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 492
 493         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false);
 494         if (ret)
 495                 goto err_unref;
 496
 497         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 498         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 499         if (ring->scratch.cpu_page == NULL) {
 500                 ret = -ENOMEM;
 501                 goto err_unpin;
 502         }
 503
 504         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 505                          ring->name, ring->scratch.gtt_offset);
 506         return 0;
 507
 508 err_unpin:
 509         i915_gem_object_unpin(ring->scratch.obj);
 510 err_unref:
 511         drm_gem_object_unreference(&ring->scratch.obj->base);
 512 err:
 513         return ret;
 514 }
 515
 516 static int init_render_ring(struct intel_ring_buffer *ring)
 517 {
 518         struct drm_device *dev = ring->dev;
 519         struct drm_i915_private *dev_priv = dev->dev_private;
 520         int ret = init_ring_common(ring);
 521
 522         if (INTEL_INFO(dev)->gen > 3)
 523                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 524
 525         /* We need to disable the AsyncFlip performance optimisations in order
 526          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 527          * programmed to '1' on all products.
 528          *
 529          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 530          */
 531         if (INTEL_INFO(dev)->gen >= 6)
 532                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 533
 534         /* Required for the hardware to program scanline values for waiting */
 535         if (INTEL_INFO(dev)->gen == 6)
 536                 I915_WRITE(GFX_MODE,
 537                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 538
 539         if (IS_GEN7(dev))
 540                 I915_WRITE(GFX_MODE_GEN7,
 541                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 542                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 543
 544         if (INTEL_INFO(dev)->gen >= 5) {
 545                 ret = init_pipe_control(ring);
 546                 if (ret)
 547                         return ret;
 548         }
 549
 550         if (IS_GEN6(dev)) {
 551                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 552                  * "If this bit is set, STCunit will have LRA as replacement
 553                  *  policy. [...] This bit must be reset.  LRA replacement
 554                  *  policy is not supported."
 555                  */
 556                 I915_WRITE(CACHE_MODE_0,
 557                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 558
 559                 /* This is not explicitly set for GEN6, so read the register.
 560                  * see intel_ring_mi_set_context() for why we care.
 561                  * TODO: consider explicitly setting the bit for GEN5
 562                  */
 563                 ring->itlb_before_ctx_switch =
 564                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 565         }
 566
 567         if (INTEL_INFO(dev)->gen >= 6)
 568                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 569
 570         if (HAS_L3_DPF(dev))
 571                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 572
 573         return ret;
 574 }
 575
 576 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 577 {
 578         struct drm_device *dev = ring->dev;
 579
 580         if (ring->scratch.obj == NULL)
 581                 return;
 582
 583         if (INTEL_INFO(dev)->gen >= 5) {
 584                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 585                 i915_gem_object_unpin(ring->scratch.obj);
 586         }
 587
 588         drm_gem_object_unreference(&ring->scratch.obj->base);
 589         ring->scratch.obj = NULL;
 590 }
 591
 592 static void
 593 update_mboxes(struct intel_ring_buffer *ring,
 594               u32 mmio_offset)
 595 {
 596 /* NB: In order to be able to do semaphore MBOX updates for varying number
 597  * of rings, it's easiest if we round up each individual update to a
 598  * multiple of 2 (since ring updates must always be a multiple of 2)
 599  * even though the actual update only requires 3 dwords.
 600  */
 601 #define MBOX_UPDATE_DWORDS 4
 602         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 603         intel_ring_emit(ring, mmio_offset);
 604         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 605         intel_ring_emit(ring, MI_NOOP);
 606 }
 607
 608 /**
 609  * gen6_add_request - Update the semaphore mailbox registers
 610  *
 611  * @ring - ring that is adding a request
 612  * @seqno - return seqno stuck into the ring
 613  *
 614  * Update the mailbox registers in the *other* rings with the current seqno.
 615  * This acts like a signal in the canonical semaphore.
 616  */
 617 static int
 618 gen6_add_request(struct intel_ring_buffer *ring)
 619 {
 620         struct drm_device *dev = ring->dev;
 621         struct drm_i915_private *dev_priv = dev->dev_private;
 622         struct intel_ring_buffer *useless;
 623         int i, ret;
 624
 625         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 626                                       MBOX_UPDATE_DWORDS) +
 627                                       4);
 628         if (ret)
 629                 return ret;
 630 #undef MBOX_UPDATE_DWORDS
 631
 632         for_each_ring(useless, dev_priv, i) {
 633                 u32 mbox_reg = ring->signal_mbox[i];
 634                 if (mbox_reg != GEN6_NOSYNC)
 635                         update_mboxes(ring, mbox_reg);
 636         }
 637
 638         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 639         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 640         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 641         intel_ring_emit(ring, MI_USER_INTERRUPT);
 642         __intel_ring_advance(ring);
 643
 644         return 0;
 645 }
 646
 647 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 648                                               u32 seqno)
 649 {
 650         struct drm_i915_private *dev_priv = dev->dev_private;
 651         return dev_priv->last_seqno < seqno;
 652 }
 653
 654 /**
 655  * intel_ring_sync - sync the waiter to the signaller on seqno
 656  *
 657  * @waiter - ring that is waiting
 658  * @signaller - ring which has, or will signal
 659  * @seqno - seqno which the waiter will block on
 660  */
 661 static int
 662 gen6_ring_sync(struct intel_ring_buffer *waiter,
 663                struct intel_ring_buffer *signaller,
 664                u32 seqno)
 665 {
 666         int ret;
 667         u32 dw1 = MI_SEMAPHORE_MBOX |
 668                   MI_SEMAPHORE_COMPARE |
 669                   MI_SEMAPHORE_REGISTER;
 670
 671         /* Throughout all of the GEM code, seqno passed implies our current
 672          * seqno is >= the last seqno executed. However for hardware the
 673          * comparison is strictly greater than.
 674          */
 675         seqno -= 1;
 676
 677         WARN_ON(signaller->semaphore_register[waiter->id] ==
 678                 MI_SEMAPHORE_SYNC_INVALID);
 679
 680         ret = intel_ring_begin(waiter, 4);
 681         if (ret)
 682                 return ret;
 683
 684         /* If seqno wrap happened, omit the wait with no-ops */
 685         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 686                 intel_ring_emit(waiter,
 687                                 dw1 |
 688                                 signaller->semaphore_register[waiter->id]);
 689                 intel_ring_emit(waiter, seqno);
 690                 intel_ring_emit(waiter, 0);
 691                 intel_ring_emit(waiter, MI_NOOP);
 692         } else {
 693                 intel_ring_emit(waiter, MI_NOOP);
 694                 intel_ring_emit(waiter, MI_NOOP);
 695                 intel_ring_emit(waiter, MI_NOOP);
 696                 intel_ring_emit(waiter, MI_NOOP);
 697         }
 698         intel_ring_advance(waiter);
 699
 700         return 0;
 701 }
 702
 703 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 704 do {                                                                    \
 705         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 706                  PIPE_CONTROL_DEPTH_STALL);                             \
 707         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 708         intel_ring_emit(ring__, 0);                                                     \
 709         intel_ring_emit(ring__, 0);                                                     \
 710 } while (0)
 711
 712 static int
 713 pc_render_add_request(struct intel_ring_buffer *ring)
 714 {
 715         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 716         int ret;
 717
 718         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 719          * incoherent with writes to memory, i.e. completely fubar,
 720          * so we need to use PIPE_NOTIFY instead.
 721          *
 722          * However, we also need to workaround the qword write
 723          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 724          * memory before requesting an interrupt.
 725          */
 726         ret = intel_ring_begin(ring, 32);
 727         if (ret)
 728                 return ret;
 729
 730         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 731                         PIPE_CONTROL_WRITE_FLUSH |
 732                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 733         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 734         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 735         intel_ring_emit(ring, 0);
 736         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 737         scratch_addr += 128; /* write to separate cachelines */
 738         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 739         scratch_addr += 128;
 740         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 741         scratch_addr += 128;
 742         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 743         scratch_addr += 128;
 744         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 745         scratch_addr += 128;
 746         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 747
 748         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 749                         PIPE_CONTROL_WRITE_FLUSH |
 750                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 751                         PIPE_CONTROL_NOTIFY);
 752         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 753         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 754         intel_ring_emit(ring, 0);
 755         __intel_ring_advance(ring);
 756
 757         return 0;
 758 }
 759
 760 static u32
 761 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 762 {
 763         /* Workaround to force correct ordering between irq and seqno writes on
 764          * ivb (and maybe also on snb) by reading from a CS register (like
 765          * ACTHD) before reading the status page. */
 766         if (!lazy_coherency)
 767                 intel_ring_get_active_head(ring);
 768         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 769 }
 770
 771 static u32
 772 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 773 {
 774         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 775 }
 776
 777 static void
 778 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 779 {
 780         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 781 }
 782
 783 static u32
 784 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 785 {
 786         return ring->scratch.cpu_page[0];
 787 }
 788
 789 static void
 790 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 791 {
 792         ring->scratch.cpu_page[0] = seqno;
 793 }
 794
 795 static bool
 796 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 797 {
 798         struct drm_device *dev = ring->dev;
 799         drm_i915_private_t *dev_priv = dev->dev_private;
 800         unsigned long flags;
 801
 802         if (!dev->irq_enabled)
 803                 return false;
 804
 805         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 806         if (ring->irq_refcount++ == 0)
 807                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
 808         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 809
 810         return true;
 811 }
 812
 813 static void
 814 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 815 {
 816         struct drm_device *dev = ring->dev;
 817         drm_i915_private_t *dev_priv = dev->dev_private;
 818         unsigned long flags;
 819
 820         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 821         if (--ring->irq_refcount == 0)
 822                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
 823         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 824 }
 825
 826 static bool
 827 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 828 {
 829         struct drm_device *dev = ring->dev;
 830         drm_i915_private_t *dev_priv = dev->dev_private;
 831         unsigned long flags;
 832
 833         if (!dev->irq_enabled)
 834                 return false;
 835
 836         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 837         if (ring->irq_refcount++ == 0) {
 838                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 839                 I915_WRITE(IMR, dev_priv->irq_mask);
 840                 POSTING_READ(IMR);
 841         }
 842         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 843
 844         return true;
 845 }
 846
 847 static void
 848 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 849 {
 850         struct drm_device *dev = ring->dev;
 851         drm_i915_private_t *dev_priv = dev->dev_private;
 852         unsigned long flags;
 853
 854         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 855         if (--ring->irq_refcount == 0) {
 856                 dev_priv->irq_mask |= ring->irq_enable_mask;
 857                 I915_WRITE(IMR, dev_priv->irq_mask);
 858                 POSTING_READ(IMR);
 859         }
 860         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 861 }
 862
 863 static bool
 864 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 865 {
 866         struct drm_device *dev = ring->dev;
 867         drm_i915_private_t *dev_priv = dev->dev_private;
 868         unsigned long flags;
 869
 870         if (!dev->irq_enabled)
 871                 return false;
 872
 873         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 874         if (ring->irq_refcount++ == 0) {
 875                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 876                 I915_WRITE16(IMR, dev_priv->irq_mask);
 877                 POSTING_READ16(IMR);
 878         }
 879         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 880
 881         return true;
 882 }
 883
 884 static void
 885 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 886 {
 887         struct drm_device *dev = ring->dev;
 888         drm_i915_private_t *dev_priv = dev->dev_private;
 889         unsigned long flags;
 890
 891         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 892         if (--ring->irq_refcount == 0) {
 893                 dev_priv->irq_mask |= ring->irq_enable_mask;
 894                 I915_WRITE16(IMR, dev_priv->irq_mask);
 895                 POSTING_READ16(IMR);
 896         }
 897         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 898 }
 899
 900 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 901 {
 902         struct drm_device *dev = ring->dev;
 903         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 904         u32 mmio = 0;
 905
 906         /* The ring status page addresses are no longer next to the rest of
 907          * the ring registers as of gen7.
 908          */
 909         if (IS_GEN7(dev)) {
 910                 switch (ring->id) {
 911                 case RCS:
 912                         mmio = RENDER_HWS_PGA_GEN7;
 913                         break;
 914                 case BCS:
 915                         mmio = BLT_HWS_PGA_GEN7;
 916                         break;
 917                 case VCS:
 918                         mmio = BSD_HWS_PGA_GEN7;
 919                         break;
 920                 case VECS:
 921                         mmio = VEBOX_HWS_PGA_GEN7;
 922                         break;
 923                 }
 924         } else if (IS_GEN6(ring->dev)) {
 925                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 926         } else {
 927                 mmio = RING_HWS_PGA(ring->mmio_base);
 928         }
 929
 930         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 931         POSTING_READ(mmio);
 932
 933         /* Flush the TLB for this page */
 934         if (INTEL_INFO(dev)->gen >= 6) {
 935                 u32 reg = RING_INSTPM(ring->mmio_base);
 936                 I915_WRITE(reg,
 937                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 938                                               INSTPM_SYNC_FLUSH));
 939                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 940                              1000))
 941                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 942                                   ring->name);
 943         }
 944 }
 945
 946 static int
 947 bsd_ring_flush(struct intel_ring_buffer *ring,
 948                u32     invalidate_domains,
 949                u32     flush_domains)
 950 {
 951         int ret;
 952
 953         ret = intel_ring_begin(ring, 2);
 954         if (ret)
 955                 return ret;
 956
 957         intel_ring_emit(ring, MI_FLUSH);
 958         intel_ring_emit(ring, MI_NOOP);
 959         intel_ring_advance(ring);
 960         return 0;
 961 }
 962
 963 static int
 964 i9xx_add_request(struct intel_ring_buffer *ring)
 965 {
 966         int ret;
 967
 968         ret = intel_ring_begin(ring, 4);
 969         if (ret)
 970                 return ret;
 971
 972         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 973         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 974         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 975         intel_ring_emit(ring, MI_USER_INTERRUPT);
 976         __intel_ring_advance(ring);
 977
 978         return 0;
 979 }
 980
 981 static bool
 982 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 983 {
 984         struct drm_device *dev = ring->dev;
 985         drm_i915_private_t *dev_priv = dev->dev_private;
 986         unsigned long flags;
 987
 988         if (!dev->irq_enabled)
 989                return false;
 990
 991         /* It looks like we need to prevent the gt from suspending while waiting
 992          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 993          * blt/bsd rings on ivb. */
 994         gen6_gt_force_wake_get(dev_priv);
 995
 996         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 997         if (ring->irq_refcount++ == 0) {
 998                 if (HAS_L3_DPF(dev) && ring->id == RCS)
 999                         I915_WRITE_IMR(ring,
1000                                        ~(ring->irq_enable_mask |
1001                                          GT_PARITY_ERROR(dev)));
1002                 else
1003                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1004                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1005         }
1006         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1007
1008         return true;
1009 }
1010
1011 static void
1012 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1013 {
1014         struct drm_device *dev = ring->dev;
1015         drm_i915_private_t *dev_priv = dev->dev_private;
1016         unsigned long flags;
1017
1018         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1019         if (--ring->irq_refcount == 0) {
1020                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1021                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1022                 else
1023                         I915_WRITE_IMR(ring, ~0);
1024                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1025         }
1026         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1027
1028         gen6_gt_force_wake_put(dev_priv);
1029 }
1030
1031 static bool
1032 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1033 {
1034         struct drm_device *dev = ring->dev;
1035         struct drm_i915_private *dev_priv = dev->dev_private;
1036         unsigned long flags;
1037
1038         if (!dev->irq_enabled)
1039                 return false;
1040
1041         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1042         if (ring->irq_refcount++ == 0) {
1043                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1044                 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1045         }
1046         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1047
1048         return true;
1049 }
1050
1051 static void
1052 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1053 {
1054         struct drm_device *dev = ring->dev;
1055         struct drm_i915_private *dev_priv = dev->dev_private;
1056         unsigned long flags;
1057
1058         if (!dev->irq_enabled)
1059                 return;
1060
1061         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1062         if (--ring->irq_refcount == 0) {
1063                 I915_WRITE_IMR(ring, ~0);
1064                 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1065         }
1066         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1067 }
1068
1069 static int
1070 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1071                          u32 offset, u32 length,
1072                          unsigned flags)
1073 {
1074         int ret;
1075
1076         ret = intel_ring_begin(ring, 2);
1077         if (ret)
1078                 return ret;
1079
1080         intel_ring_emit(ring,
1081                         MI_BATCH_BUFFER_START |
1082                         MI_BATCH_GTT |
1083                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1084         intel_ring_emit(ring, offset);
1085         intel_ring_advance(ring);
1086
1087         return 0;
1088 }
1089
1090 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1091 #define I830_BATCH_LIMIT (256*1024)
1092 static int
1093 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1094                                 u32 offset, u32 len,
1095                                 unsigned flags)
1096 {
1097         int ret;
1098
1099         if (flags & I915_DISPATCH_PINNED) {
1100                 ret = intel_ring_begin(ring, 4);
1101                 if (ret)
1102                         return ret;
1103
1104                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1105                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1106                 intel_ring_emit(ring, offset + len - 8);
1107                 intel_ring_emit(ring, MI_NOOP);
1108                 intel_ring_advance(ring);
1109         } else {
1110                 u32 cs_offset = ring->scratch.gtt_offset;
1111
1112                 if (len > I830_BATCH_LIMIT)
1113                         return -ENOSPC;
1114
1115                 ret = intel_ring_begin(ring, 9+3);
1116                 if (ret)
1117                         return ret;
1118                 /* Blit the batch (which has now all relocs applied) to the stable batch
1119                  * scratch bo area (so that the CS never stumbles over its tlb
1120                  * invalidation bug) ... */
1121                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1122                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1123                                 XY_SRC_COPY_BLT_WRITE_RGB);
1124                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1125                 intel_ring_emit(ring, 0);
1126                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1127                 intel_ring_emit(ring, cs_offset);
1128                 intel_ring_emit(ring, 0);
1129                 intel_ring_emit(ring, 4096);
1130                 intel_ring_emit(ring, offset);
1131                 intel_ring_emit(ring, MI_FLUSH);
1132
1133                 /* ... and execute it. */
1134                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1135                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1136                 intel_ring_emit(ring, cs_offset + len - 8);
1137                 intel_ring_advance(ring);
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int
1144 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1145                          u32 offset, u32 len,
1146                          unsigned flags)
1147 {
1148         int ret;
1149
1150         ret = intel_ring_begin(ring, 2);
1151         if (ret)
1152                 return ret;
1153
1154         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1155         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1156         intel_ring_advance(ring);
1157
1158         return 0;
1159 }
1160
1161 static void cleanup_status_page(struct intel_ring_buffer *ring)
1162 {
1163         struct drm_i915_gem_object *obj;
1164
1165         obj = ring->status_page.obj;
1166         if (obj == NULL)
1167                 return;
1168
1169         kunmap(sg_page(obj->pages->sgl));
1170         i915_gem_object_unpin(obj);
1171         drm_gem_object_unreference(&obj->base);
1172         ring->status_page.obj = NULL;
1173 }
1174
1175 static int init_status_page(struct intel_ring_buffer *ring)
1176 {
1177         struct drm_device *dev = ring->dev;
1178         struct drm_i915_gem_object *obj;
1179         int ret;
1180
1181         obj = i915_gem_alloc_object(dev, 4096);
1182         if (obj == NULL) {
1183                 DRM_ERROR("Failed to allocate status page\n");
1184                 ret = -ENOMEM;
1185                 goto err;
1186         }
1187
1188         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1189
1190         ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
1191         if (ret != 0) {
1192                 goto err_unref;
1193         }
1194
1195         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1196         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1197         if (ring->status_page.page_addr == NULL) {
1198                 ret = -ENOMEM;
1199                 goto err_unpin;
1200         }
1201         ring->status_page.obj = obj;
1202         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1203
1204         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1205                         ring->name, ring->status_page.gfx_addr);
1206
1207         return 0;
1208
1209 err_unpin:
1210         i915_gem_object_unpin(obj);
1211 err_unref:
1212         drm_gem_object_unreference(&obj->base);
1213 err:
1214         return ret;
1215 }
1216
1217 static int init_phys_status_page(struct intel_ring_buffer *ring)
1218 {
1219         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1220
1221         if (!dev_priv->status_page_dmah) {
1222                 dev_priv->status_page_dmah =
1223                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1224                 if (!dev_priv->status_page_dmah)
1225                         return -ENOMEM;
1226         }
1227
1228         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1229         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1230
1231         return 0;
1232 }
1233
1234 static int intel_init_ring_buffer(struct drm_device *dev,
1235                                   struct intel_ring_buffer *ring)
1236 {
1237         struct drm_i915_gem_object *obj;
1238         struct drm_i915_private *dev_priv = dev->dev_private;
1239         int ret;
1240
1241         ring->dev = dev;
1242         INIT_LIST_HEAD(&ring->active_list);
1243         INIT_LIST_HEAD(&ring->request_list);
1244         ring->size = 32 * PAGE_SIZE;
1245         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1246
1247         init_waitqueue_head(&ring->irq_queue);
1248
1249         if (I915_NEED_GFX_HWS(dev)) {
1250                 ret = init_status_page(ring);
1251                 if (ret)
1252                         return ret;
1253         } else {
1254                 BUG_ON(ring->id != RCS);
1255                 ret = init_phys_status_page(ring);
1256                 if (ret)
1257                         return ret;
1258         }
1259
1260         obj = NULL;
1261         if (!HAS_LLC(dev))
1262                 obj = i915_gem_object_create_stolen(dev, ring->size);
1263         if (obj == NULL)
1264                 obj = i915_gem_alloc_object(dev, ring->size);
1265         if (obj == NULL) {
1266                 DRM_ERROR("Failed to allocate ringbuffer\n");
1267                 ret = -ENOMEM;
1268                 goto err_hws;
1269         }
1270
1271         ring->obj = obj;
1272
1273         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false);
1274         if (ret)
1275                 goto err_unref;
1276
1277         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1278         if (ret)
1279                 goto err_unpin;
1280
1281         ring->virtual_start =
1282                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1283                            ring->size);
1284         if (ring->virtual_start == NULL) {
1285                 DRM_ERROR("Failed to map ringbuffer.\n");
1286                 ret = -EINVAL;
1287                 goto err_unpin;
1288         }
1289
1290         ret = ring->init(ring);
1291         if (ret)
1292                 goto err_unmap;
1293
1294         /* Workaround an erratum on the i830 which causes a hang if
1295          * the TAIL pointer points to within the last 2 cachelines
1296          * of the buffer.
1297          */
1298         ring->effective_size = ring->size;
1299         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1300                 ring->effective_size -= 128;
1301
1302         return 0;
1303
1304 err_unmap:
1305         iounmap(ring->virtual_start);
1306 err_unpin:
1307         i915_gem_object_unpin(obj);
1308 err_unref:
1309         drm_gem_object_unreference(&obj->base);
1310         ring->obj = NULL;
1311 err_hws:
1312         cleanup_status_page(ring);
1313         return ret;
1314 }
1315
1316 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1317 {
1318         struct drm_i915_private *dev_priv;
1319         int ret;
1320
1321         if (ring->obj == NULL)
1322                 return;
1323
1324         /* Disable the ring buffer. The ring must be idle at this point */
1325         dev_priv = ring->dev->dev_private;
1326         ret = intel_ring_idle(ring);
1327         if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1328                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1329                           ring->name, ret);
1330
1331         I915_WRITE_CTL(ring, 0);
1332
1333         iounmap(ring->virtual_start);
1334
1335         i915_gem_object_unpin(ring->obj);
1336         drm_gem_object_unreference(&ring->obj->base);
1337         ring->obj = NULL;
1338         ring->preallocated_lazy_request = NULL;
1339         ring->outstanding_lazy_seqno = 0;
1340
1341         if (ring->cleanup)
1342                 ring->cleanup(ring);
1343
1344         cleanup_status_page(ring);
1345 }
1346
1347 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1348 {
1349         int ret;
1350
1351         ret = i915_wait_seqno(ring, seqno);
1352         if (!ret)
1353                 i915_gem_retire_requests_ring(ring);
1354
1355         return ret;
1356 }
1357
1358 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1359 {
1360         struct drm_i915_gem_request *request;
1361         u32 seqno = 0;
1362         int ret;
1363
1364         i915_gem_retire_requests_ring(ring);
1365
1366         if (ring->last_retired_head != -1) {
1367                 ring->head = ring->last_retired_head;
1368                 ring->last_retired_head = -1;
1369                 ring->space = ring_space(ring);
1370                 if (ring->space >= n)
1371                         return 0;
1372         }
1373
1374         list_for_each_entry(request, &ring->request_list, list) {
1375                 int space;
1376
1377                 if (request->tail == -1)
1378                         continue;
1379
1380                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1381                 if (space < 0)
1382                         space += ring->size;
1383                 if (space >= n) {
1384                         seqno = request->seqno;
1385                         break;
1386                 }
1387
1388                 /* Consume this request in case we need more space than
1389                  * is available and so need to prevent a race between
1390                  * updating last_retired_head and direct reads of
1391                  * I915_RING_HEAD. It also provides a nice sanity check.
1392                  */
1393                 request->tail = -1;
1394         }
1395
1396         if (seqno == 0)
1397                 return -ENOSPC;
1398
1399         ret = intel_ring_wait_seqno(ring, seqno);
1400         if (ret)
1401                 return ret;
1402
1403         if (WARN_ON(ring->last_retired_head == -1))
1404                 return -ENOSPC;
1405
1406         ring->head = ring->last_retired_head;
1407         ring->last_retired_head = -1;
1408         ring->space = ring_space(ring);
1409         if (WARN_ON(ring->space < n))
1410                 return -ENOSPC;
1411
1412         return 0;
1413 }
1414
1415 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1416 {
1417         struct drm_device *dev = ring->dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         unsigned long end;
1420         int ret;
1421
1422         ret = intel_ring_wait_request(ring, n);
1423         if (ret != -ENOSPC)
1424                 return ret;
1425
1426         /* force the tail write in case we have been skipping them */
1427         __intel_ring_advance(ring);
1428
1429         trace_i915_ring_wait_begin(ring);
1430         /* With GEM the hangcheck timer should kick us out of the loop,
1431          * leaving it early runs the risk of corrupting GEM state (due
1432          * to running on almost untested codepaths). But on resume
1433          * timers don't work yet, so prevent a complete hang in that
1434          * case by choosing an insanely large timeout. */
1435         end = jiffies + 60 * HZ;
1436
1437         do {
1438                 ring->head = I915_READ_HEAD(ring);
1439                 ring->space = ring_space(ring);
1440                 if (ring->space >= n) {
1441                         trace_i915_ring_wait_end(ring);
1442                         return 0;
1443                 }
1444
1445                 if (dev->primary->master) {
1446                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1447                         if (master_priv->sarea_priv)
1448                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1449                 }
1450
1451                 msleep(1);
1452
1453                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1454                                            dev_priv->mm.interruptible);
1455                 if (ret)
1456                         return ret;
1457         } while (!time_after(jiffies, end));
1458         trace_i915_ring_wait_end(ring);
1459         return -EBUSY;
1460 }
1461
1462 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1463 {
1464         uint32_t __iomem *virt;
1465         int rem = ring->size - ring->tail;
1466
1467         if (ring->space < rem) {
1468                 int ret = ring_wait_for_space(ring, rem);
1469                 if (ret)
1470                         return ret;
1471         }
1472
1473         virt = ring->virtual_start + ring->tail;
1474         rem /= 4;
1475         while (rem--)
1476                 iowrite32(MI_NOOP, virt++);
1477
1478         ring->tail = 0;
1479         ring->space = ring_space(ring);
1480
1481         return 0;
1482 }
1483
1484 int intel_ring_idle(struct intel_ring_buffer *ring)
1485 {
1486         u32 seqno;
1487         int ret;
1488
1489         /* We need to add any requests required to flush the objects and ring */
1490         if (ring->outstanding_lazy_seqno) {
1491                 ret = i915_add_request(ring, NULL);
1492                 if (ret)
1493                         return ret;
1494         }
1495
1496         /* Wait upon the last request to be completed */
1497         if (list_empty(&ring->request_list))
1498                 return 0;
1499
1500         seqno = list_entry(ring->request_list.prev,
1501                            struct drm_i915_gem_request,
1502                            list)->seqno;
1503
1504         return i915_wait_seqno(ring, seqno);
1505 }
1506
1507 static int
1508 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1509 {
1510         if (ring->outstanding_lazy_seqno)
1511                 return 0;
1512
1513         if (ring->preallocated_lazy_request == NULL) {
1514                 struct drm_i915_gem_request *request;
1515
1516                 request = kmalloc(sizeof(*request), GFP_KERNEL);
1517                 if (request == NULL)
1518                         return -ENOMEM;
1519
1520                 ring->preallocated_lazy_request = request;
1521         }
1522
1523         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1524 }
1525
1526 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1527                               int bytes)
1528 {
1529         int ret;
1530
1531         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1532                 ret = intel_wrap_ring_buffer(ring);
1533                 if (unlikely(ret))
1534                         return ret;
1535         }
1536
1537         if (unlikely(ring->space < bytes)) {
1538                 ret = ring_wait_for_space(ring, bytes);
1539                 if (unlikely(ret))
1540                         return ret;
1541         }
1542
1543         ring->space -= bytes;
1544         return 0;
1545 }
1546
1547 int intel_ring_begin(struct intel_ring_buffer *ring,
1548                      int num_dwords)
1549 {
1550         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1551         int ret;
1552
1553         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1554                                    dev_priv->mm.interruptible);
1555         if (ret)
1556                 return ret;
1557
1558         /* Preallocate the olr before touching the ring */
1559         ret = intel_ring_alloc_seqno(ring);
1560         if (ret)
1561                 return ret;
1562
1563         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1564 }
1565
1566 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1567 {
1568         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1569
1570         BUG_ON(ring->outstanding_lazy_seqno);
1571
1572         if (INTEL_INFO(ring->dev)->gen >= 6) {
1573                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1574                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1575                 if (HAS_VEBOX(ring->dev))
1576                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1577         }
1578
1579         ring->set_seqno(ring, seqno);
1580         ring->hangcheck.seqno = seqno;
1581 }
1582
1583 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1584                                      u32 value)
1585 {
1586         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1587
1588        /* Every tail move must follow the sequence below */
1589
1590         /* Disable notification that the ring is IDLE. The GT
1591          * will then assume that it is busy and bring it out of rc6.
1592          */
1593         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1594                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1595
1596         /* Clear the context id. Here be magic! */
1597         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1598
1599         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1600         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1601                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1602                      50))
1603                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1604
1605         /* Now that the ring is fully powered up, update the tail */
1606         I915_WRITE_TAIL(ring, value);
1607         POSTING_READ(RING_TAIL(ring->mmio_base));
1608
1609         /* Let the ring send IDLE messages to the GT again,
1610          * and so let it sleep to conserve power when idle.
1611          */
1612         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1613                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1614 }
1615
1616 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1617                                u32 invalidate, u32 flush)
1618 {
1619         uint32_t cmd;
1620         int ret;
1621
1622         ret = intel_ring_begin(ring, 4);
1623         if (ret)
1624                 return ret;
1625
1626         cmd = MI_FLUSH_DW;
1627         /*
1628          * Bspec vol 1c.5 - video engine command streamer:
1629          * "If ENABLED, all TLBs will be invalidated once the flush
1630          * operation is complete. This bit is only valid when the
1631          * Post-Sync Operation field is a value of 1h or 3h."
1632          */
1633         if (invalidate & I915_GEM_GPU_DOMAINS)
1634                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1635                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1636         intel_ring_emit(ring, cmd);
1637         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1638         intel_ring_emit(ring, 0);
1639         intel_ring_emit(ring, MI_NOOP);
1640         intel_ring_advance(ring);
1641         return 0;
1642 }
1643
1644 static int
1645 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1646                               u32 offset, u32 len,
1647                               unsigned flags)
1648 {
1649         int ret;
1650
1651         ret = intel_ring_begin(ring, 2);
1652         if (ret)
1653                 return ret;
1654
1655         intel_ring_emit(ring,
1656                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1657                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1658         /* bit0-7 is the length on GEN6+ */
1659         intel_ring_emit(ring, offset);
1660         intel_ring_advance(ring);
1661
1662         return 0;
1663 }
1664
1665 static int
1666 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1667                               u32 offset, u32 len,
1668                               unsigned flags)
1669 {
1670         int ret;
1671
1672         ret = intel_ring_begin(ring, 2);
1673         if (ret)
1674                 return ret;
1675
1676         intel_ring_emit(ring,
1677                         MI_BATCH_BUFFER_START |
1678                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1679         /* bit0-7 is the length on GEN6+ */
1680         intel_ring_emit(ring, offset);
1681         intel_ring_advance(ring);
1682
1683         return 0;
1684 }
1685
1686 /* Blitter support (SandyBridge+) */
1687
1688 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1689                            u32 invalidate, u32 flush)
1690 {
1691         struct drm_device *dev = ring->dev;
1692         uint32_t cmd;
1693         int ret;
1694
1695         ret = intel_ring_begin(ring, 4);
1696         if (ret)
1697                 return ret;
1698
1699         cmd = MI_FLUSH_DW;
1700         /*
1701          * Bspec vol 1c.3 - blitter engine command streamer:
1702          * "If ENABLED, all TLBs will be invalidated once the flush
1703          * operation is complete. This bit is only valid when the
1704          * Post-Sync Operation field is a value of 1h or 3h."
1705          */
1706         if (invalidate & I915_GEM_DOMAIN_RENDER)
1707                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1708                         MI_FLUSH_DW_OP_STOREDW;
1709         intel_ring_emit(ring, cmd);
1710         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1711         intel_ring_emit(ring, 0);
1712         intel_ring_emit(ring, MI_NOOP);
1713         intel_ring_advance(ring);
1714
1715         if (IS_GEN7(dev) && flush)
1716                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1717
1718         return 0;
1719 }
1720
1721 int intel_init_render_ring_buffer(struct drm_device *dev)
1722 {
1723         drm_i915_private_t *dev_priv = dev->dev_private;
1724         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1725
1726         ring->name = "render ring";
1727         ring->id = RCS;
1728         ring->mmio_base = RENDER_RING_BASE;
1729
1730         if (INTEL_INFO(dev)->gen >= 6) {
1731                 ring->add_request = gen6_add_request;
1732                 ring->flush = gen7_render_ring_flush;
1733                 if (INTEL_INFO(dev)->gen == 6)
1734                         ring->flush = gen6_render_ring_flush;
1735                 ring->irq_get = gen6_ring_get_irq;
1736                 ring->irq_put = gen6_ring_put_irq;
1737                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1738                 ring->get_seqno = gen6_ring_get_seqno;
1739                 ring->set_seqno = ring_set_seqno;
1740                 ring->sync_to = gen6_ring_sync;
1741                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1742                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1743                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1744                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1745                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1746                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1747                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1748                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1749         } else if (IS_GEN5(dev)) {
1750                 ring->add_request = pc_render_add_request;
1751                 ring->flush = gen4_render_ring_flush;
1752                 ring->get_seqno = pc_render_get_seqno;
1753                 ring->set_seqno = pc_render_set_seqno;
1754                 ring->irq_get = gen5_ring_get_irq;
1755                 ring->irq_put = gen5_ring_put_irq;
1756                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1757                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1758         } else {
1759                 ring->add_request = i9xx_add_request;
1760                 if (INTEL_INFO(dev)->gen < 4)
1761                         ring->flush = gen2_render_ring_flush;
1762                 else
1763                         ring->flush = gen4_render_ring_flush;
1764                 ring->get_seqno = ring_get_seqno;
1765                 ring->set_seqno = ring_set_seqno;
1766                 if (IS_GEN2(dev)) {
1767                         ring->irq_get = i8xx_ring_get_irq;
1768                         ring->irq_put = i8xx_ring_put_irq;
1769                 } else {
1770                         ring->irq_get = i9xx_ring_get_irq;
1771                         ring->irq_put = i9xx_ring_put_irq;
1772                 }
1773                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1774         }
1775         ring->write_tail = ring_write_tail;
1776         if (IS_HASWELL(dev))
1777                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1778         else if (INTEL_INFO(dev)->gen >= 6)
1779                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1780         else if (INTEL_INFO(dev)->gen >= 4)
1781                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1782         else if (IS_I830(dev) || IS_845G(dev))
1783                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1784         else
1785                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1786         ring->init = init_render_ring;
1787         ring->cleanup = render_ring_cleanup;
1788
1789         /* Workaround batchbuffer to combat CS tlb bug. */
1790         if (HAS_BROKEN_CS_TLB(dev)) {
1791                 struct drm_i915_gem_object *obj;
1792                 int ret;
1793
1794                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1795                 if (obj == NULL) {
1796                         DRM_ERROR("Failed to allocate batch bo\n");
1797                         return -ENOMEM;
1798                 }
1799
1800                 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1801                 if (ret != 0) {
1802                         drm_gem_object_unreference(&obj->base);
1803                         DRM_ERROR("Failed to ping batch bo\n");
1804                         return ret;
1805                 }
1806
1807                 ring->scratch.obj = obj;
1808                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1809         }
1810
1811         return intel_init_ring_buffer(dev, ring);
1812 }
1813
1814 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1815 {
1816         drm_i915_private_t *dev_priv = dev->dev_private;
1817         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1818         int ret;
1819
1820         ring->name = "render ring";
1821         ring->id = RCS;
1822         ring->mmio_base = RENDER_RING_BASE;
1823
1824         if (INTEL_INFO(dev)->gen >= 6) {
1825                 /* non-kms not supported on gen6+ */
1826                 return -ENODEV;
1827         }
1828
1829         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1830          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1831          * the special gen5 functions. */
1832         ring->add_request = i9xx_add_request;
1833         if (INTEL_INFO(dev)->gen < 4)
1834                 ring->flush = gen2_render_ring_flush;
1835         else
1836                 ring->flush = gen4_render_ring_flush;
1837         ring->get_seqno = ring_get_seqno;
1838         ring->set_seqno = ring_set_seqno;
1839         if (IS_GEN2(dev)) {
1840                 ring->irq_get = i8xx_ring_get_irq;
1841                 ring->irq_put = i8xx_ring_put_irq;
1842         } else {
1843                 ring->irq_get = i9xx_ring_get_irq;
1844                 ring->irq_put = i9xx_ring_put_irq;
1845         }
1846         ring->irq_enable_mask = I915_USER_INTERRUPT;
1847         ring->write_tail = ring_write_tail;
1848         if (INTEL_INFO(dev)->gen >= 4)
1849                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1850         else if (IS_I830(dev) || IS_845G(dev))
1851                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1852         else
1853                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1854         ring->init = init_render_ring;
1855         ring->cleanup = render_ring_cleanup;
1856
1857         ring->dev = dev;
1858         INIT_LIST_HEAD(&ring->active_list);
1859         INIT_LIST_HEAD(&ring->request_list);
1860
1861         ring->size = size;
1862         ring->effective_size = ring->size;
1863         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1864                 ring->effective_size -= 128;
1865
1866         ring->virtual_start = ioremap_wc(start, size);
1867         if (ring->virtual_start == NULL) {
1868                 DRM_ERROR("can not ioremap virtual address for"
1869                           " ring buffer\n");
1870                 return -ENOMEM;
1871         }
1872
1873         if (!I915_NEED_GFX_HWS(dev)) {
1874                 ret = init_phys_status_page(ring);
1875                 if (ret)
1876                         return ret;
1877         }
1878
1879         return 0;
1880 }
1881
1882 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1883 {
1884         drm_i915_private_t *dev_priv = dev->dev_private;
1885         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1886
1887         ring->name = "bsd ring";
1888         ring->id = VCS;
1889
1890         ring->write_tail = ring_write_tail;
1891         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1892                 ring->mmio_base = GEN6_BSD_RING_BASE;
1893                 /* gen6 bsd needs a special wa for tail updates */
1894                 if (IS_GEN6(dev))
1895                         ring->write_tail = gen6_bsd_ring_write_tail;
1896                 ring->flush = gen6_bsd_ring_flush;
1897                 ring->add_request = gen6_add_request;
1898                 ring->get_seqno = gen6_ring_get_seqno;
1899                 ring->set_seqno = ring_set_seqno;
1900                 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1901                 ring->irq_get = gen6_ring_get_irq;
1902                 ring->irq_put = gen6_ring_put_irq;
1903                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1904                 ring->sync_to = gen6_ring_sync;
1905                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1906                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1907                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1908                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1909                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1910                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1911                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1912                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1913         } else {
1914                 ring->mmio_base = BSD_RING_BASE;
1915                 ring->flush = bsd_ring_flush;
1916                 ring->add_request = i9xx_add_request;
1917                 ring->get_seqno = ring_get_seqno;
1918                 ring->set_seqno = ring_set_seqno;
1919                 if (IS_GEN5(dev)) {
1920                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1921                         ring->irq_get = gen5_ring_get_irq;
1922                         ring->irq_put = gen5_ring_put_irq;
1923                 } else {
1924                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1925                         ring->irq_get = i9xx_ring_get_irq;
1926                         ring->irq_put = i9xx_ring_put_irq;
1927                 }
1928                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1929         }
1930         ring->init = init_ring_common;
1931
1932         return intel_init_ring_buffer(dev, ring);
1933 }
1934
1935 int intel_init_blt_ring_buffer(struct drm_device *dev)
1936 {
1937         drm_i915_private_t *dev_priv = dev->dev_private;
1938         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1939
1940         ring->name = "blitter ring";
1941         ring->id = BCS;
1942
1943         ring->mmio_base = BLT_RING_BASE;
1944         ring->write_tail = ring_write_tail;
1945         ring->flush = gen6_ring_flush;
1946         ring->add_request = gen6_add_request;
1947         ring->get_seqno = gen6_ring_get_seqno;
1948         ring->set_seqno = ring_set_seqno;
1949         ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1950         ring->irq_get = gen6_ring_get_irq;
1951         ring->irq_put = gen6_ring_put_irq;
1952         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1953         ring->sync_to = gen6_ring_sync;
1954         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1955         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1956         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1957         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1958         ring->signal_mbox[RCS] = GEN6_RBSYNC;
1959         ring->signal_mbox[VCS] = GEN6_VBSYNC;
1960         ring->signal_mbox[BCS] = GEN6_NOSYNC;
1961         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1962         ring->init = init_ring_common;
1963
1964         return intel_init_ring_buffer(dev, ring);
1965 }
1966
1967 int intel_init_vebox_ring_buffer(struct drm_device *dev)
1968 {
1969         drm_i915_private_t *dev_priv = dev->dev_private;
1970         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
1971
1972         ring->name = "video enhancement ring";
1973         ring->id = VECS;
1974
1975         ring->mmio_base = VEBOX_RING_BASE;
1976         ring->write_tail = ring_write_tail;
1977         ring->flush = gen6_ring_flush;
1978         ring->add_request = gen6_add_request;
1979         ring->get_seqno = gen6_ring_get_seqno;
1980         ring->set_seqno = ring_set_seqno;
1981         ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
1982         ring->irq_get = hsw_vebox_get_irq;
1983         ring->irq_put = hsw_vebox_put_irq;
1984         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1985         ring->sync_to = gen6_ring_sync;
1986         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
1987         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
1988         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
1989         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
1990         ring->signal_mbox[RCS] = GEN6_RVESYNC;
1991         ring->signal_mbox[VCS] = GEN6_VVESYNC;
1992         ring->signal_mbox[BCS] = GEN6_BVESYNC;
1993         ring->signal_mbox[VECS] = GEN6_NOSYNC;
1994         ring->init = init_ring_common;
1995
1996         return intel_init_ring_buffer(dev, ring);
1997 }
1998
1999 int
2000 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2001 {
2002         int ret;
2003
2004         if (!ring->gpu_caches_dirty)
2005                 return 0;
2006
2007         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2008         if (ret)
2009                 return ret;
2010
2011         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2012
2013         ring->gpu_caches_dirty = false;
2014         return 0;
2015 }
2016
2017 int
2018 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2019 {
2020         uint32_t flush_domains;
2021         int ret;
2022
2023         flush_domains = 0;
2024         if (ring->gpu_caches_dirty)
2025                 flush_domains = I915_GEM_GPU_DOMAINS;
2026
2027         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2028         if (ret)
2029                 return ret;
2030
2031         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2032
2033         ring->gpu_caches_dirty = false;
2034         return 0;
2035 }