drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int
 284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 285                        u32 invalidate_domains, u32 flush_domains)
 286 {
 287         u32 flags = 0;
 288         struct pipe_control *pc = ring->private;
 289         u32 scratch_addr = pc->gtt_offset + 128;
 290         int ret;
 291
 292         /*
 293          * Ensure that any following seqno writes only happen when the render
 294          * cache is indeed flushed.
 295          *
 296          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 297          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 298          * don't try to be clever and just set it unconditionally.
 299          */
 300         flags |= PIPE_CONTROL_CS_STALL;
 301
 302         /* Just flush everything.  Experiments have shown that reducing the
 303          * number of bits based on the write domains has little performance
 304          * impact.
 305          */
 306         if (flush_domains) {
 307                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 308                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 309         }
 310         if (invalidate_domains) {
 311                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 312                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 322
 323                 /* Workaround: we must issue a pipe_control with CS-stall bit
 324                  * set before a pipe_control command that has the state cache
 325                  * invalidate bit set. */
 326                 gen7_render_ring_cs_stall_wa(ring);
 327         }
 328
 329         ret = intel_ring_begin(ring, 4);
 330         if (ret)
 331                 return ret;
 332
 333         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 334         intel_ring_emit(ring, flags);
 335         intel_ring_emit(ring, scratch_addr);
 336         intel_ring_emit(ring, 0);
 337         intel_ring_advance(ring);
 338
 339         return 0;
 340 }
 341
 342 static void ring_write_tail(struct intel_ring_buffer *ring,
 343                             u32 value)
 344 {
 345         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 346         I915_WRITE_TAIL(ring, value);
 347 }
 348
 349 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 350 {
 351         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 352         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 353                         RING_ACTHD(ring->mmio_base) : ACTHD;
 354
 355         return I915_READ(acthd_reg);
 356 }
 357
 358 static int init_ring_common(struct intel_ring_buffer *ring)
 359 {
 360         struct drm_device *dev = ring->dev;
 361         drm_i915_private_t *dev_priv = dev->dev_private;
 362         struct drm_i915_gem_object *obj = ring->obj;
 363         int ret = 0;
 364         u32 head;
 365
 366         if (HAS_FORCE_WAKE(dev))
 367                 gen6_gt_force_wake_get(dev_priv);
 368
 369         /* Stop the ring if it's running. */
 370         I915_WRITE_CTL(ring, 0);
 371         I915_WRITE_HEAD(ring, 0);
 372         ring->write_tail(ring, 0);
 373
 374         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 375
 376         /* G45 ring initialization fails to reset head to zero */
 377         if (head != 0) {
 378                 DRM_DEBUG_KMS("%s head not reset to zero "
 379                               "ctl %08x head %08x tail %08x start %08x\n",
 380                               ring->name,
 381                               I915_READ_CTL(ring),
 382                               I915_READ_HEAD(ring),
 383                               I915_READ_TAIL(ring),
 384                               I915_READ_START(ring));
 385
 386                 I915_WRITE_HEAD(ring, 0);
 387
 388                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 389                         DRM_ERROR("failed to set %s head to zero "
 390                                   "ctl %08x head %08x tail %08x start %08x\n",
 391                                   ring->name,
 392                                   I915_READ_CTL(ring),
 393                                   I915_READ_HEAD(ring),
 394                                   I915_READ_TAIL(ring),
 395                                   I915_READ_START(ring));
 396                 }
 397         }
 398
 399         /* Initialize the ring. This must happen _after_ we've cleared the ring
 400          * registers with the above sequence (the readback of the HEAD registers
 401          * also enforces ordering), otherwise the hw might lose the new ring
 402          * register values. */
 403         I915_WRITE_START(ring, obj->gtt_offset);
 404         I915_WRITE_CTL(ring,
 405                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 406                         | RING_VALID);
 407
 408         /* If the head is still not zero, the ring is dead */
 409         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 410                      I915_READ_START(ring) == obj->gtt_offset &&
 411                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 412                 DRM_ERROR("%s initialization failed "
 413                                 "ctl %08x head %08x tail %08x start %08x\n",
 414                                 ring->name,
 415                                 I915_READ_CTL(ring),
 416                                 I915_READ_HEAD(ring),
 417                                 I915_READ_TAIL(ring),
 418                                 I915_READ_START(ring));
 419                 ret = -EIO;
 420                 goto out;
 421         }
 422
 423         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 424                 i915_kernel_lost_context(ring->dev);
 425         else {
 426                 ring->head = I915_READ_HEAD(ring);
 427                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 428                 ring->space = ring_space(ring);
 429                 ring->last_retired_head = -1;
 430         }
 431
 432 out:
 433         if (HAS_FORCE_WAKE(dev))
 434                 gen6_gt_force_wake_put(dev_priv);
 435
 436         return ret;
 437 }
 438
 439 static int
 440 init_pipe_control(struct intel_ring_buffer *ring)
 441 {
 442         struct pipe_control *pc;
 443         struct drm_i915_gem_object *obj;
 444         int ret;
 445
 446         if (ring->private)
 447                 return 0;
 448
 449         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 450         if (!pc)
 451                 return -ENOMEM;
 452
 453         obj = i915_gem_alloc_object(ring->dev, 4096);
 454         if (obj == NULL) {
 455                 DRM_ERROR("Failed to allocate seqno page\n");
 456                 ret = -ENOMEM;
 457                 goto err;
 458         }
 459
 460         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 461
 462         ret = i915_gem_object_pin(obj, 4096, true, false);
 463         if (ret)
 464                 goto err_unref;
 465
 466         pc->gtt_offset = obj->gtt_offset;
 467         pc->cpu_page = kmap(sg_page(obj->pages->sgl));
 468         if (pc->cpu_page == NULL) {
 469                 ret = -ENOMEM;
 470                 goto err_unpin;
 471         }
 472
 473         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 474                          ring->name, pc->gtt_offset);
 475
 476         pc->obj = obj;
 477         ring->private = pc;
 478         return 0;
 479
 480 err_unpin:
 481         i915_gem_object_unpin(obj);
 482 err_unref:
 483         drm_gem_object_unreference(&obj->base);
 484 err:
 485         kfree(pc);
 486         return ret;
 487 }
 488
 489 static void
 490 cleanup_pipe_control(struct intel_ring_buffer *ring)
 491 {
 492         struct pipe_control *pc = ring->private;
 493         struct drm_i915_gem_object *obj;
 494
 495         if (!ring->private)
 496                 return;
 497
 498         obj = pc->obj;
 499
 500         kunmap(sg_page(obj->pages->sgl));
 501         i915_gem_object_unpin(obj);
 502         drm_gem_object_unreference(&obj->base);
 503
 504         kfree(pc);
 505         ring->private = NULL;
 506 }
 507
 508 static int init_render_ring(struct intel_ring_buffer *ring)
 509 {
 510         struct drm_device *dev = ring->dev;
 511         struct drm_i915_private *dev_priv = dev->dev_private;
 512         int ret = init_ring_common(ring);
 513
 514         if (INTEL_INFO(dev)->gen > 3)
 515                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 516
 517         /* We need to disable the AsyncFlip performance optimisations in order
 518          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 519          * programmed to '1' on all products.
 520          *
 521          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 522          */
 523         if (INTEL_INFO(dev)->gen >= 6)
 524                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 525
 526         /* Required for the hardware to program scanline values for waiting */
 527         if (INTEL_INFO(dev)->gen == 6)
 528                 I915_WRITE(GFX_MODE,
 529                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 530
 531         if (IS_GEN7(dev))
 532                 I915_WRITE(GFX_MODE_GEN7,
 533                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 534                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 535
 536         if (INTEL_INFO(dev)->gen >= 5) {
 537                 ret = init_pipe_control(ring);
 538                 if (ret)
 539                         return ret;
 540         }
 541
 542         if (IS_GEN6(dev)) {
 543                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 544                  * "If this bit is set, STCunit will have LRA as replacement
 545                  *  policy. [...] This bit must be reset.  LRA replacement
 546                  *  policy is not supported."
 547                  */
 548                 I915_WRITE(CACHE_MODE_0,
 549                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 550
 551                 /* This is not explicitly set for GEN6, so read the register.
 552                  * see intel_ring_mi_set_context() for why we care.
 553                  * TODO: consider explicitly setting the bit for GEN5
 554                  */
 555                 ring->itlb_before_ctx_switch =
 556                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 557         }
 558
 559         if (INTEL_INFO(dev)->gen >= 6)
 560                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 561
 562         if (HAS_L3_GPU_CACHE(dev))
 563                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 564
 565         return ret;
 566 }
 567
 568 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 569 {
 570         struct drm_device *dev = ring->dev;
 571
 572         if (!ring->private)
 573                 return;
 574
 575         if (HAS_BROKEN_CS_TLB(dev))
 576                 drm_gem_object_unreference(to_gem_object(ring->private));
 577
 578         cleanup_pipe_control(ring);
 579 }
 580
 581 static void
 582 update_mboxes(struct intel_ring_buffer *ring,
 583               u32 mmio_offset)
 584 {
 585 /* NB: In order to be able to do semaphore MBOX updates for varying number
 586  * of rings, it's easiest if we round up each individual update to a
 587  * multiple of 2 (since ring updates must always be a multiple of 2)
 588  * even though the actual update only requires 3 dwords.
 589  */
 590 #define MBOX_UPDATE_DWORDS 4
 591         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 592         intel_ring_emit(ring, mmio_offset);
 593         intel_ring_emit(ring, ring->outstanding_lazy_request);
 594         intel_ring_emit(ring, MI_NOOP);
 595 }
 596
 597 /**
 598  * gen6_add_request - Update the semaphore mailbox registers
 599  *
 600  * @ring - ring that is adding a request
 601  * @seqno - return seqno stuck into the ring
 602  *
 603  * Update the mailbox registers in the *other* rings with the current seqno.
 604  * This acts like a signal in the canonical semaphore.
 605  */
 606 static int
 607 gen6_add_request(struct intel_ring_buffer *ring)
 608 {
 609         struct drm_device *dev = ring->dev;
 610         struct drm_i915_private *dev_priv = dev->dev_private;
 611         struct intel_ring_buffer *useless;
 612         int i, ret;
 613
 614         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 615                                       MBOX_UPDATE_DWORDS) +
 616                                       4);
 617         if (ret)
 618                 return ret;
 619 #undef MBOX_UPDATE_DWORDS
 620
 621         for_each_ring(useless, dev_priv, i) {
 622                 u32 mbox_reg = ring->signal_mbox[i];
 623                 if (mbox_reg != GEN6_NOSYNC)
 624                         update_mboxes(ring, mbox_reg);
 625         }
 626
 627         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 628         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 629         intel_ring_emit(ring, ring->outstanding_lazy_request);
 630         intel_ring_emit(ring, MI_USER_INTERRUPT);
 631         intel_ring_advance(ring);
 632
 633         return 0;
 634 }
 635
 636 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 637                                               u32 seqno)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         return dev_priv->last_seqno < seqno;
 641 }
 642
 643 /**
 644  * intel_ring_sync - sync the waiter to the signaller on seqno
 645  *
 646  * @waiter - ring that is waiting
 647  * @signaller - ring which has, or will signal
 648  * @seqno - seqno which the waiter will block on
 649  */
 650 static int
 651 gen6_ring_sync(struct intel_ring_buffer *waiter,
 652                struct intel_ring_buffer *signaller,
 653                u32 seqno)
 654 {
 655         int ret;
 656         u32 dw1 = MI_SEMAPHORE_MBOX |
 657                   MI_SEMAPHORE_COMPARE |
 658                   MI_SEMAPHORE_REGISTER;
 659
 660         /* Throughout all of the GEM code, seqno passed implies our current
 661          * seqno is >= the last seqno executed. However for hardware the
 662          * comparison is strictly greater than.
 663          */
 664         seqno -= 1;
 665
 666         WARN_ON(signaller->semaphore_register[waiter->id] ==
 667                 MI_SEMAPHORE_SYNC_INVALID);
 668
 669         ret = intel_ring_begin(waiter, 4);
 670         if (ret)
 671                 return ret;
 672
 673         /* If seqno wrap happened, omit the wait with no-ops */
 674         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 675                 intel_ring_emit(waiter,
 676                                 dw1 |
 677                                 signaller->semaphore_register[waiter->id]);
 678                 intel_ring_emit(waiter, seqno);
 679                 intel_ring_emit(waiter, 0);
 680                 intel_ring_emit(waiter, MI_NOOP);
 681         } else {
 682                 intel_ring_emit(waiter, MI_NOOP);
 683                 intel_ring_emit(waiter, MI_NOOP);
 684                 intel_ring_emit(waiter, MI_NOOP);
 685                 intel_ring_emit(waiter, MI_NOOP);
 686         }
 687         intel_ring_advance(waiter);
 688
 689         return 0;
 690 }
 691
 692 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 693 do {                                                                    \
 694         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 695                  PIPE_CONTROL_DEPTH_STALL);                             \
 696         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 697         intel_ring_emit(ring__, 0);                                                     \
 698         intel_ring_emit(ring__, 0);                                                     \
 699 } while (0)
 700
 701 static int
 702 pc_render_add_request(struct intel_ring_buffer *ring)
 703 {
 704         struct pipe_control *pc = ring->private;
 705         u32 scratch_addr = pc->gtt_offset + 128;
 706         int ret;
 707
 708         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 709          * incoherent with writes to memory, i.e. completely fubar,
 710          * so we need to use PIPE_NOTIFY instead.
 711          *
 712          * However, we also need to workaround the qword write
 713          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 714          * memory before requesting an interrupt.
 715          */
 716         ret = intel_ring_begin(ring, 32);
 717         if (ret)
 718                 return ret;
 719
 720         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 721                         PIPE_CONTROL_WRITE_FLUSH |
 722                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 723         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 724         intel_ring_emit(ring, ring->outstanding_lazy_request);
 725         intel_ring_emit(ring, 0);
 726         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 727         scratch_addr += 128; /* write to separate cachelines */
 728         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 729         scratch_addr += 128;
 730         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 731         scratch_addr += 128;
 732         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 733         scratch_addr += 128;
 734         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 735         scratch_addr += 128;
 736         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 737
 738         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 739                         PIPE_CONTROL_WRITE_FLUSH |
 740                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 741                         PIPE_CONTROL_NOTIFY);
 742         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 743         intel_ring_emit(ring, ring->outstanding_lazy_request);
 744         intel_ring_emit(ring, 0);
 745         intel_ring_advance(ring);
 746
 747         return 0;
 748 }
 749
 750 static u32
 751 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 752 {
 753         /* Workaround to force correct ordering between irq and seqno writes on
 754          * ivb (and maybe also on snb) by reading from a CS register (like
 755          * ACTHD) before reading the status page. */
 756         if (!lazy_coherency)
 757                 intel_ring_get_active_head(ring);
 758         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 759 }
 760
 761 static u32
 762 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 763 {
 764         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 765 }
 766
 767 static void
 768 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 769 {
 770         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 771 }
 772
 773 static u32
 774 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 775 {
 776         struct pipe_control *pc = ring->private;
 777         return pc->cpu_page[0];
 778 }
 779
 780 static void
 781 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 782 {
 783         struct pipe_control *pc = ring->private;
 784         pc->cpu_page[0] = seqno;
 785 }
 786
 787 static bool
 788 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 789 {
 790         struct drm_device *dev = ring->dev;
 791         drm_i915_private_t *dev_priv = dev->dev_private;
 792         unsigned long flags;
 793
 794         if (!dev->irq_enabled)
 795                 return false;
 796
 797         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 798         if (ring->irq_refcount++ == 0) {
 799                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 800                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 801                 POSTING_READ(GTIMR);
 802         }
 803         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 804
 805         return true;
 806 }
 807
 808 static void
 809 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 810 {
 811         struct drm_device *dev = ring->dev;
 812         drm_i915_private_t *dev_priv = dev->dev_private;
 813         unsigned long flags;
 814
 815         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 816         if (--ring->irq_refcount == 0) {
 817                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 818                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 819                 POSTING_READ(GTIMR);
 820         }
 821         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 822 }
 823
 824 static bool
 825 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 826 {
 827         struct drm_device *dev = ring->dev;
 828         drm_i915_private_t *dev_priv = dev->dev_private;
 829         unsigned long flags;
 830
 831         if (!dev->irq_enabled)
 832                 return false;
 833
 834         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 835         if (ring->irq_refcount++ == 0) {
 836                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 837                 I915_WRITE(IMR, dev_priv->irq_mask);
 838                 POSTING_READ(IMR);
 839         }
 840         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 841
 842         return true;
 843 }
 844
 845 static void
 846 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 847 {
 848         struct drm_device *dev = ring->dev;
 849         drm_i915_private_t *dev_priv = dev->dev_private;
 850         unsigned long flags;
 851
 852         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 853         if (--ring->irq_refcount == 0) {
 854                 dev_priv->irq_mask |= ring->irq_enable_mask;
 855                 I915_WRITE(IMR, dev_priv->irq_mask);
 856                 POSTING_READ(IMR);
 857         }
 858         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 859 }
 860
 861 static bool
 862 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 863 {
 864         struct drm_device *dev = ring->dev;
 865         drm_i915_private_t *dev_priv = dev->dev_private;
 866         unsigned long flags;
 867
 868         if (!dev->irq_enabled)
 869                 return false;
 870
 871         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 872         if (ring->irq_refcount++ == 0) {
 873                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 874                 I915_WRITE16(IMR, dev_priv->irq_mask);
 875                 POSTING_READ16(IMR);
 876         }
 877         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 878
 879         return true;
 880 }
 881
 882 static void
 883 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 884 {
 885         struct drm_device *dev = ring->dev;
 886         drm_i915_private_t *dev_priv = dev->dev_private;
 887         unsigned long flags;
 888
 889         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 890         if (--ring->irq_refcount == 0) {
 891                 dev_priv->irq_mask |= ring->irq_enable_mask;
 892                 I915_WRITE16(IMR, dev_priv->irq_mask);
 893                 POSTING_READ16(IMR);
 894         }
 895         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 896 }
 897
 898 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 899 {
 900         struct drm_device *dev = ring->dev;
 901         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 902         u32 mmio = 0;
 903
 904         /* The ring status page addresses are no longer next to the rest of
 905          * the ring registers as of gen7.
 906          */
 907         if (IS_GEN7(dev)) {
 908                 switch (ring->id) {
 909                 case RCS:
 910                         mmio = RENDER_HWS_PGA_GEN7;
 911                         break;
 912                 case BCS:
 913                         mmio = BLT_HWS_PGA_GEN7;
 914                         break;
 915                 case VCS:
 916                         mmio = BSD_HWS_PGA_GEN7;
 917                         break;
 918                 case VECS:
 919                         BUG();
 920                 }
 921         } else if (IS_GEN6(ring->dev)) {
 922                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 923         } else {
 924                 mmio = RING_HWS_PGA(ring->mmio_base);
 925         }
 926
 927         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 928         POSTING_READ(mmio);
 929 }
 930
 931 static int
 932 bsd_ring_flush(struct intel_ring_buffer *ring,
 933                u32     invalidate_domains,
 934                u32     flush_domains)
 935 {
 936         int ret;
 937
 938         ret = intel_ring_begin(ring, 2);
 939         if (ret)
 940                 return ret;
 941
 942         intel_ring_emit(ring, MI_FLUSH);
 943         intel_ring_emit(ring, MI_NOOP);
 944         intel_ring_advance(ring);
 945         return 0;
 946 }
 947
 948 static int
 949 i9xx_add_request(struct intel_ring_buffer *ring)
 950 {
 951         int ret;
 952
 953         ret = intel_ring_begin(ring, 4);
 954         if (ret)
 955                 return ret;
 956
 957         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 958         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 959         intel_ring_emit(ring, ring->outstanding_lazy_request);
 960         intel_ring_emit(ring, MI_USER_INTERRUPT);
 961         intel_ring_advance(ring);
 962
 963         return 0;
 964 }
 965
 966 static bool
 967 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 968 {
 969         struct drm_device *dev = ring->dev;
 970         drm_i915_private_t *dev_priv = dev->dev_private;
 971         unsigned long flags;
 972
 973         if (!dev->irq_enabled)
 974                return false;
 975
 976         /* It looks like we need to prevent the gt from suspending while waiting
 977          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 978          * blt/bsd rings on ivb. */
 979         gen6_gt_force_wake_get(dev_priv);
 980
 981         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 982         if (ring->irq_refcount++ == 0) {
 983                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 984                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 985                                                 GEN6_RENDER_L3_PARITY_ERROR));
 986                 else
 987                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 988                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 989                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 990                 POSTING_READ(GTIMR);
 991         }
 992         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 993
 994         return true;
 995 }
 996
 997 static void
 998 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 999 {
1000         struct drm_device *dev = ring->dev;
1001         drm_i915_private_t *dev_priv = dev->dev_private;
1002         unsigned long flags;
1003
1004         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1005         if (--ring->irq_refcount == 0) {
1006                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1007                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
1008                 else
1009                         I915_WRITE_IMR(ring, ~0);
1010                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1011                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1012                 POSTING_READ(GTIMR);
1013         }
1014         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1015
1016         gen6_gt_force_wake_put(dev_priv);
1017 }
1018
1019 static int
1020 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1021                          u32 offset, u32 length,
1022                          unsigned flags)
1023 {
1024         int ret;
1025
1026         ret = intel_ring_begin(ring, 2);
1027         if (ret)
1028                 return ret;
1029
1030         intel_ring_emit(ring,
1031                         MI_BATCH_BUFFER_START |
1032                         MI_BATCH_GTT |
1033                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1034         intel_ring_emit(ring, offset);
1035         intel_ring_advance(ring);
1036
1037         return 0;
1038 }
1039
1040 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1041 #define I830_BATCH_LIMIT (256*1024)
1042 static int
1043 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1044                                 u32 offset, u32 len,
1045                                 unsigned flags)
1046 {
1047         int ret;
1048
1049         if (flags & I915_DISPATCH_PINNED) {
1050                 ret = intel_ring_begin(ring, 4);
1051                 if (ret)
1052                         return ret;
1053
1054                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1055                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1056                 intel_ring_emit(ring, offset + len - 8);
1057                 intel_ring_emit(ring, MI_NOOP);
1058                 intel_ring_advance(ring);
1059         } else {
1060                 struct drm_i915_gem_object *obj = ring->private;
1061                 u32 cs_offset = obj->gtt_offset;
1062
1063                 if (len > I830_BATCH_LIMIT)
1064                         return -ENOSPC;
1065
1066                 ret = intel_ring_begin(ring, 9+3);
1067                 if (ret)
1068                         return ret;
1069                 /* Blit the batch (which has now all relocs applied) to the stable batch
1070                  * scratch bo area (so that the CS never stumbles over its tlb
1071                  * invalidation bug) ... */
1072                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1073                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1074                                 XY_SRC_COPY_BLT_WRITE_RGB);
1075                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1076                 intel_ring_emit(ring, 0);
1077                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1078                 intel_ring_emit(ring, cs_offset);
1079                 intel_ring_emit(ring, 0);
1080                 intel_ring_emit(ring, 4096);
1081                 intel_ring_emit(ring, offset);
1082                 intel_ring_emit(ring, MI_FLUSH);
1083
1084                 /* ... and execute it. */
1085                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1086                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1087                 intel_ring_emit(ring, cs_offset + len - 8);
1088                 intel_ring_advance(ring);
1089         }
1090
1091         return 0;
1092 }
1093
1094 static int
1095 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1096                          u32 offset, u32 len,
1097                          unsigned flags)
1098 {
1099         int ret;
1100
1101         ret = intel_ring_begin(ring, 2);
1102         if (ret)
1103                 return ret;
1104
1105         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1106         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1107         intel_ring_advance(ring);
1108
1109         return 0;
1110 }
1111
1112 static void cleanup_status_page(struct intel_ring_buffer *ring)
1113 {
1114         struct drm_i915_gem_object *obj;
1115
1116         obj = ring->status_page.obj;
1117         if (obj == NULL)
1118                 return;
1119
1120         kunmap(sg_page(obj->pages->sgl));
1121         i915_gem_object_unpin(obj);
1122         drm_gem_object_unreference(&obj->base);
1123         ring->status_page.obj = NULL;
1124 }
1125
1126 static int init_status_page(struct intel_ring_buffer *ring)
1127 {
1128         struct drm_device *dev = ring->dev;
1129         struct drm_i915_gem_object *obj;
1130         int ret;
1131
1132         obj = i915_gem_alloc_object(dev, 4096);
1133         if (obj == NULL) {
1134                 DRM_ERROR("Failed to allocate status page\n");
1135                 ret = -ENOMEM;
1136                 goto err;
1137         }
1138
1139         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1140
1141         ret = i915_gem_object_pin(obj, 4096, true, false);
1142         if (ret != 0) {
1143                 goto err_unref;
1144         }
1145
1146         ring->status_page.gfx_addr = obj->gtt_offset;
1147         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1148         if (ring->status_page.page_addr == NULL) {
1149                 ret = -ENOMEM;
1150                 goto err_unpin;
1151         }
1152         ring->status_page.obj = obj;
1153         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1154
1155         intel_ring_setup_status_page(ring);
1156         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1157                         ring->name, ring->status_page.gfx_addr);
1158
1159         return 0;
1160
1161 err_unpin:
1162         i915_gem_object_unpin(obj);
1163 err_unref:
1164         drm_gem_object_unreference(&obj->base);
1165 err:
1166         return ret;
1167 }
1168
1169 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1170 {
1171         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1172         u32 addr;
1173
1174         if (!dev_priv->status_page_dmah) {
1175                 dev_priv->status_page_dmah =
1176                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1177                 if (!dev_priv->status_page_dmah)
1178                         return -ENOMEM;
1179         }
1180
1181         addr = dev_priv->status_page_dmah->busaddr;
1182         if (INTEL_INFO(ring->dev)->gen >= 4)
1183                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1184         I915_WRITE(HWS_PGA, addr);
1185
1186         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1187         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1188
1189         return 0;
1190 }
1191
1192 static int intel_init_ring_buffer(struct drm_device *dev,
1193                                   struct intel_ring_buffer *ring)
1194 {
1195         struct drm_i915_gem_object *obj;
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         int ret;
1198
1199         ring->dev = dev;
1200         INIT_LIST_HEAD(&ring->active_list);
1201         INIT_LIST_HEAD(&ring->request_list);
1202         ring->size = 32 * PAGE_SIZE;
1203         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1204
1205         init_waitqueue_head(&ring->irq_queue);
1206
1207         if (I915_NEED_GFX_HWS(dev)) {
1208                 ret = init_status_page(ring);
1209                 if (ret)
1210                         return ret;
1211         } else {
1212                 BUG_ON(ring->id != RCS);
1213                 ret = init_phys_hws_pga(ring);
1214                 if (ret)
1215                         return ret;
1216         }
1217
1218         obj = NULL;
1219         if (!HAS_LLC(dev))
1220                 obj = i915_gem_object_create_stolen(dev, ring->size);
1221         if (obj == NULL)
1222                 obj = i915_gem_alloc_object(dev, ring->size);
1223         if (obj == NULL) {
1224                 DRM_ERROR("Failed to allocate ringbuffer\n");
1225                 ret = -ENOMEM;
1226                 goto err_hws;
1227         }
1228
1229         ring->obj = obj;
1230
1231         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1232         if (ret)
1233                 goto err_unref;
1234
1235         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1236         if (ret)
1237                 goto err_unpin;
1238
1239         ring->virtual_start =
1240                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1241                            ring->size);
1242         if (ring->virtual_start == NULL) {
1243                 DRM_ERROR("Failed to map ringbuffer.\n");
1244                 ret = -EINVAL;
1245                 goto err_unpin;
1246         }
1247
1248         ret = ring->init(ring);
1249         if (ret)
1250                 goto err_unmap;
1251
1252         /* Workaround an erratum on the i830 which causes a hang if
1253          * the TAIL pointer points to within the last 2 cachelines
1254          * of the buffer.
1255          */
1256         ring->effective_size = ring->size;
1257         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1258                 ring->effective_size -= 128;
1259
1260         return 0;
1261
1262 err_unmap:
1263         iounmap(ring->virtual_start);
1264 err_unpin:
1265         i915_gem_object_unpin(obj);
1266 err_unref:
1267         drm_gem_object_unreference(&obj->base);
1268         ring->obj = NULL;
1269 err_hws:
1270         cleanup_status_page(ring);
1271         return ret;
1272 }
1273
1274 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1275 {
1276         struct drm_i915_private *dev_priv;
1277         int ret;
1278
1279         if (ring->obj == NULL)
1280                 return;
1281
1282         /* Disable the ring buffer. The ring must be idle at this point */
1283         dev_priv = ring->dev->dev_private;
1284         ret = intel_ring_idle(ring);
1285         if (ret)
1286                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1287                           ring->name, ret);
1288
1289         I915_WRITE_CTL(ring, 0);
1290
1291         iounmap(ring->virtual_start);
1292
1293         i915_gem_object_unpin(ring->obj);
1294         drm_gem_object_unreference(&ring->obj->base);
1295         ring->obj = NULL;
1296
1297         if (ring->cleanup)
1298                 ring->cleanup(ring);
1299
1300         cleanup_status_page(ring);
1301 }
1302
1303 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1304 {
1305         int ret;
1306
1307         ret = i915_wait_seqno(ring, seqno);
1308         if (!ret)
1309                 i915_gem_retire_requests_ring(ring);
1310
1311         return ret;
1312 }
1313
1314 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1315 {
1316         struct drm_i915_gem_request *request;
1317         u32 seqno = 0;
1318         int ret;
1319
1320         i915_gem_retire_requests_ring(ring);
1321
1322         if (ring->last_retired_head != -1) {
1323                 ring->head = ring->last_retired_head;
1324                 ring->last_retired_head = -1;
1325                 ring->space = ring_space(ring);
1326                 if (ring->space >= n)
1327                         return 0;
1328         }
1329
1330         list_for_each_entry(request, &ring->request_list, list) {
1331                 int space;
1332
1333                 if (request->tail == -1)
1334                         continue;
1335
1336                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1337                 if (space < 0)
1338                         space += ring->size;
1339                 if (space >= n) {
1340                         seqno = request->seqno;
1341                         break;
1342                 }
1343
1344                 /* Consume this request in case we need more space than
1345                  * is available and so need to prevent a race between
1346                  * updating last_retired_head and direct reads of
1347                  * I915_RING_HEAD. It also provides a nice sanity check.
1348                  */
1349                 request->tail = -1;
1350         }
1351
1352         if (seqno == 0)
1353                 return -ENOSPC;
1354
1355         ret = intel_ring_wait_seqno(ring, seqno);
1356         if (ret)
1357                 return ret;
1358
1359         if (WARN_ON(ring->last_retired_head == -1))
1360                 return -ENOSPC;
1361
1362         ring->head = ring->last_retired_head;
1363         ring->last_retired_head = -1;
1364         ring->space = ring_space(ring);
1365         if (WARN_ON(ring->space < n))
1366                 return -ENOSPC;
1367
1368         return 0;
1369 }
1370
1371 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1372 {
1373         struct drm_device *dev = ring->dev;
1374         struct drm_i915_private *dev_priv = dev->dev_private;
1375         unsigned long end;
1376         int ret;
1377
1378         ret = intel_ring_wait_request(ring, n);
1379         if (ret != -ENOSPC)
1380                 return ret;
1381
1382         trace_i915_ring_wait_begin(ring);
1383         /* With GEM the hangcheck timer should kick us out of the loop,
1384          * leaving it early runs the risk of corrupting GEM state (due
1385          * to running on almost untested codepaths). But on resume
1386          * timers don't work yet, so prevent a complete hang in that
1387          * case by choosing an insanely large timeout. */
1388         end = jiffies + 60 * HZ;
1389
1390         do {
1391                 ring->head = I915_READ_HEAD(ring);
1392                 ring->space = ring_space(ring);
1393                 if (ring->space >= n) {
1394                         trace_i915_ring_wait_end(ring);
1395                         return 0;
1396                 }
1397
1398                 if (dev->primary->master) {
1399                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1400                         if (master_priv->sarea_priv)
1401                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1402                 }
1403
1404                 msleep(1);
1405
1406                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1407                                            dev_priv->mm.interruptible);
1408                 if (ret)
1409                         return ret;
1410         } while (!time_after(jiffies, end));
1411         trace_i915_ring_wait_end(ring);
1412         return -EBUSY;
1413 }
1414
1415 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1416 {
1417         uint32_t __iomem *virt;
1418         int rem = ring->size - ring->tail;
1419
1420         if (ring->space < rem) {
1421                 int ret = ring_wait_for_space(ring, rem);
1422                 if (ret)
1423                         return ret;
1424         }
1425
1426         virt = ring->virtual_start + ring->tail;
1427         rem /= 4;
1428         while (rem--)
1429                 iowrite32(MI_NOOP, virt++);
1430
1431         ring->tail = 0;
1432         ring->space = ring_space(ring);
1433
1434         return 0;
1435 }
1436
1437 int intel_ring_idle(struct intel_ring_buffer *ring)
1438 {
1439         u32 seqno;
1440         int ret;
1441
1442         /* We need to add any requests required to flush the objects and ring */
1443         if (ring->outstanding_lazy_request) {
1444                 ret = i915_add_request(ring, NULL, NULL);
1445                 if (ret)
1446                         return ret;
1447         }
1448
1449         /* Wait upon the last request to be completed */
1450         if (list_empty(&ring->request_list))
1451                 return 0;
1452
1453         seqno = list_entry(ring->request_list.prev,
1454                            struct drm_i915_gem_request,
1455                            list)->seqno;
1456
1457         return i915_wait_seqno(ring, seqno);
1458 }
1459
1460 static int
1461 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1462 {
1463         if (ring->outstanding_lazy_request)
1464                 return 0;
1465
1466         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1467 }
1468
1469 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1470                               int bytes)
1471 {
1472         int ret;
1473
1474         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1475                 ret = intel_wrap_ring_buffer(ring);
1476                 if (unlikely(ret))
1477                         return ret;
1478         }
1479
1480         if (unlikely(ring->space < bytes)) {
1481                 ret = ring_wait_for_space(ring, bytes);
1482                 if (unlikely(ret))
1483                         return ret;
1484         }
1485
1486         ring->space -= bytes;
1487         return 0;
1488 }
1489
1490 int intel_ring_begin(struct intel_ring_buffer *ring,
1491                      int num_dwords)
1492 {
1493         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1494         int ret;
1495
1496         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1497                                    dev_priv->mm.interruptible);
1498         if (ret)
1499                 return ret;
1500
1501         /* Preallocate the olr before touching the ring */
1502         ret = intel_ring_alloc_seqno(ring);
1503         if (ret)
1504                 return ret;
1505
1506         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1507 }
1508
1509 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1510 {
1511         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1512
1513         BUG_ON(ring->outstanding_lazy_request);
1514
1515         if (INTEL_INFO(ring->dev)->gen >= 6) {
1516                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1517                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1518         }
1519
1520         ring->set_seqno(ring, seqno);
1521         ring->hangcheck.seqno = seqno;
1522 }
1523
1524 void intel_ring_advance(struct intel_ring_buffer *ring)
1525 {
1526         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1527
1528         ring->tail &= ring->size - 1;
1529         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1530                 return;
1531         ring->write_tail(ring, ring->tail);
1532 }
1533
1534
1535 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1536                                      u32 value)
1537 {
1538         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1539
1540        /* Every tail move must follow the sequence below */
1541
1542         /* Disable notification that the ring is IDLE. The GT
1543          * will then assume that it is busy and bring it out of rc6.
1544          */
1545         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1546                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1547
1548         /* Clear the context id. Here be magic! */
1549         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1550
1551         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1552         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1553                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1554                      50))
1555                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1556
1557         /* Now that the ring is fully powered up, update the tail */
1558         I915_WRITE_TAIL(ring, value);
1559         POSTING_READ(RING_TAIL(ring->mmio_base));
1560
1561         /* Let the ring send IDLE messages to the GT again,
1562          * and so let it sleep to conserve power when idle.
1563          */
1564         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1565                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1566 }
1567
1568 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1569                                u32 invalidate, u32 flush)
1570 {
1571         uint32_t cmd;
1572         int ret;
1573
1574         ret = intel_ring_begin(ring, 4);
1575         if (ret)
1576                 return ret;
1577
1578         cmd = MI_FLUSH_DW;
1579         /*
1580          * Bspec vol 1c.5 - video engine command streamer:
1581          * "If ENABLED, all TLBs will be invalidated once the flush
1582          * operation is complete. This bit is only valid when the
1583          * Post-Sync Operation field is a value of 1h or 3h."
1584          */
1585         if (invalidate & I915_GEM_GPU_DOMAINS)
1586                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1587                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1588         intel_ring_emit(ring, cmd);
1589         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1590         intel_ring_emit(ring, 0);
1591         intel_ring_emit(ring, MI_NOOP);
1592         intel_ring_advance(ring);
1593         return 0;
1594 }
1595
1596 static int
1597 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1598                               u32 offset, u32 len,
1599                               unsigned flags)
1600 {
1601         int ret;
1602
1603         ret = intel_ring_begin(ring, 2);
1604         if (ret)
1605                 return ret;
1606
1607         intel_ring_emit(ring,
1608                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1609                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1610         /* bit0-7 is the length on GEN6+ */
1611         intel_ring_emit(ring, offset);
1612         intel_ring_advance(ring);
1613
1614         return 0;
1615 }
1616
1617 static int
1618 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1619                               u32 offset, u32 len,
1620                               unsigned flags)
1621 {
1622         int ret;
1623
1624         ret = intel_ring_begin(ring, 2);
1625         if (ret)
1626                 return ret;
1627
1628         intel_ring_emit(ring,
1629                         MI_BATCH_BUFFER_START |
1630                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1631         /* bit0-7 is the length on GEN6+ */
1632         intel_ring_emit(ring, offset);
1633         intel_ring_advance(ring);
1634
1635         return 0;
1636 }
1637
1638 /* Blitter support (SandyBridge+) */
1639
1640 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1641                            u32 invalidate, u32 flush)
1642 {
1643         uint32_t cmd;
1644         int ret;
1645
1646         ret = intel_ring_begin(ring, 4);
1647         if (ret)
1648                 return ret;
1649
1650         cmd = MI_FLUSH_DW;
1651         /*
1652          * Bspec vol 1c.3 - blitter engine command streamer:
1653          * "If ENABLED, all TLBs will be invalidated once the flush
1654          * operation is complete. This bit is only valid when the
1655          * Post-Sync Operation field is a value of 1h or 3h."
1656          */
1657         if (invalidate & I915_GEM_DOMAIN_RENDER)
1658                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1659                         MI_FLUSH_DW_OP_STOREDW;
1660         intel_ring_emit(ring, cmd);
1661         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1662         intel_ring_emit(ring, 0);
1663         intel_ring_emit(ring, MI_NOOP);
1664         intel_ring_advance(ring);
1665         return 0;
1666 }
1667
1668 int intel_init_render_ring_buffer(struct drm_device *dev)
1669 {
1670         drm_i915_private_t *dev_priv = dev->dev_private;
1671         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1672
1673         ring->name = "render ring";
1674         ring->id = RCS;
1675         ring->mmio_base = RENDER_RING_BASE;
1676
1677         if (INTEL_INFO(dev)->gen >= 6) {
1678                 ring->add_request = gen6_add_request;
1679                 ring->flush = gen7_render_ring_flush;
1680                 if (INTEL_INFO(dev)->gen == 6)
1681                         ring->flush = gen6_render_ring_flush;
1682                 ring->irq_get = gen6_ring_get_irq;
1683                 ring->irq_put = gen6_ring_put_irq;
1684                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1685                 ring->get_seqno = gen6_ring_get_seqno;
1686                 ring->set_seqno = ring_set_seqno;
1687                 ring->sync_to = gen6_ring_sync;
1688                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1689                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1690                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1691                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1692                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1693                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1694                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1695                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1696         } else if (IS_GEN5(dev)) {
1697                 ring->add_request = pc_render_add_request;
1698                 ring->flush = gen4_render_ring_flush;
1699                 ring->get_seqno = pc_render_get_seqno;
1700                 ring->set_seqno = pc_render_set_seqno;
1701                 ring->irq_get = gen5_ring_get_irq;
1702                 ring->irq_put = gen5_ring_put_irq;
1703                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1704         } else {
1705                 ring->add_request = i9xx_add_request;
1706                 if (INTEL_INFO(dev)->gen < 4)
1707                         ring->flush = gen2_render_ring_flush;
1708                 else
1709                         ring->flush = gen4_render_ring_flush;
1710                 ring->get_seqno = ring_get_seqno;
1711                 ring->set_seqno = ring_set_seqno;
1712                 if (IS_GEN2(dev)) {
1713                         ring->irq_get = i8xx_ring_get_irq;
1714                         ring->irq_put = i8xx_ring_put_irq;
1715                 } else {
1716                         ring->irq_get = i9xx_ring_get_irq;
1717                         ring->irq_put = i9xx_ring_put_irq;
1718                 }
1719                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1720         }
1721         ring->write_tail = ring_write_tail;
1722         if (IS_HASWELL(dev))
1723                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1724         else if (INTEL_INFO(dev)->gen >= 6)
1725                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1726         else if (INTEL_INFO(dev)->gen >= 4)
1727                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1728         else if (IS_I830(dev) || IS_845G(dev))
1729                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1730         else
1731                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1732         ring->init = init_render_ring;
1733         ring->cleanup = render_ring_cleanup;
1734
1735         /* Workaround batchbuffer to combat CS tlb bug. */
1736         if (HAS_BROKEN_CS_TLB(dev)) {
1737                 struct drm_i915_gem_object *obj;
1738                 int ret;
1739
1740                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1741                 if (obj == NULL) {
1742                         DRM_ERROR("Failed to allocate batch bo\n");
1743                         return -ENOMEM;
1744                 }
1745
1746                 ret = i915_gem_object_pin(obj, 0, true, false);
1747                 if (ret != 0) {
1748                         drm_gem_object_unreference(&obj->base);
1749                         DRM_ERROR("Failed to ping batch bo\n");
1750                         return ret;
1751                 }
1752
1753                 ring->private = obj;
1754         }
1755
1756         return intel_init_ring_buffer(dev, ring);
1757 }
1758
1759 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1760 {
1761         drm_i915_private_t *dev_priv = dev->dev_private;
1762         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1763         int ret;
1764
1765         ring->name = "render ring";
1766         ring->id = RCS;
1767         ring->mmio_base = RENDER_RING_BASE;
1768
1769         if (INTEL_INFO(dev)->gen >= 6) {
1770                 /* non-kms not supported on gen6+ */
1771                 return -ENODEV;
1772         }
1773
1774         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1775          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1776          * the special gen5 functions. */
1777         ring->add_request = i9xx_add_request;
1778         if (INTEL_INFO(dev)->gen < 4)
1779                 ring->flush = gen2_render_ring_flush;
1780         else
1781                 ring->flush = gen4_render_ring_flush;
1782         ring->get_seqno = ring_get_seqno;
1783         ring->set_seqno = ring_set_seqno;
1784         if (IS_GEN2(dev)) {
1785                 ring->irq_get = i8xx_ring_get_irq;
1786                 ring->irq_put = i8xx_ring_put_irq;
1787         } else {
1788                 ring->irq_get = i9xx_ring_get_irq;
1789                 ring->irq_put = i9xx_ring_put_irq;
1790         }
1791         ring->irq_enable_mask = I915_USER_INTERRUPT;
1792         ring->write_tail = ring_write_tail;
1793         if (INTEL_INFO(dev)->gen >= 4)
1794                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1795         else if (IS_I830(dev) || IS_845G(dev))
1796                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1797         else
1798                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1799         ring->init = init_render_ring;
1800         ring->cleanup = render_ring_cleanup;
1801
1802         ring->dev = dev;
1803         INIT_LIST_HEAD(&ring->active_list);
1804         INIT_LIST_HEAD(&ring->request_list);
1805
1806         ring->size = size;
1807         ring->effective_size = ring->size;
1808         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1809                 ring->effective_size -= 128;
1810
1811         ring->virtual_start = ioremap_wc(start, size);
1812         if (ring->virtual_start == NULL) {
1813                 DRM_ERROR("can not ioremap virtual address for"
1814                           " ring buffer\n");
1815                 return -ENOMEM;
1816         }
1817
1818         if (!I915_NEED_GFX_HWS(dev)) {
1819                 ret = init_phys_hws_pga(ring);
1820                 if (ret)
1821                         return ret;
1822         }
1823
1824         return 0;
1825 }
1826
1827 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1828 {
1829         drm_i915_private_t *dev_priv = dev->dev_private;
1830         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1831
1832         ring->name = "bsd ring";
1833         ring->id = VCS;
1834
1835         ring->write_tail = ring_write_tail;
1836         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1837                 ring->mmio_base = GEN6_BSD_RING_BASE;
1838                 /* gen6 bsd needs a special wa for tail updates */
1839                 if (IS_GEN6(dev))
1840                         ring->write_tail = gen6_bsd_ring_write_tail;
1841                 ring->flush = gen6_bsd_ring_flush;
1842                 ring->add_request = gen6_add_request;
1843                 ring->get_seqno = gen6_ring_get_seqno;
1844                 ring->set_seqno = ring_set_seqno;
1845                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1846                 ring->irq_get = gen6_ring_get_irq;
1847                 ring->irq_put = gen6_ring_put_irq;
1848                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1849                 ring->sync_to = gen6_ring_sync;
1850                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1851                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1852                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1853                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1854                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1855                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1856                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1857                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1858         } else {
1859                 ring->mmio_base = BSD_RING_BASE;
1860                 ring->flush = bsd_ring_flush;
1861                 ring->add_request = i9xx_add_request;
1862                 ring->get_seqno = ring_get_seqno;
1863                 ring->set_seqno = ring_set_seqno;
1864                 if (IS_GEN5(dev)) {
1865                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1866                         ring->irq_get = gen5_ring_get_irq;
1867                         ring->irq_put = gen5_ring_put_irq;
1868                 } else {
1869                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1870                         ring->irq_get = i9xx_ring_get_irq;
1871                         ring->irq_put = i9xx_ring_put_irq;
1872                 }
1873                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1874         }
1875         ring->init = init_ring_common;
1876
1877         return intel_init_ring_buffer(dev, ring);
1878 }
1879
1880 int intel_init_blt_ring_buffer(struct drm_device *dev)
1881 {
1882         drm_i915_private_t *dev_priv = dev->dev_private;
1883         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1884
1885         ring->name = "blitter ring";
1886         ring->id = BCS;
1887
1888         ring->mmio_base = BLT_RING_BASE;
1889         ring->write_tail = ring_write_tail;
1890         ring->flush = gen6_ring_flush;
1891         ring->add_request = gen6_add_request;
1892         ring->get_seqno = gen6_ring_get_seqno;
1893         ring->set_seqno = ring_set_seqno;
1894         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1895         ring->irq_get = gen6_ring_get_irq;
1896         ring->irq_put = gen6_ring_put_irq;
1897         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1898         ring->sync_to = gen6_ring_sync;
1899         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1900         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1901         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1902         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1903         ring->signal_mbox[RCS] = GEN6_RBSYNC;
1904         ring->signal_mbox[VCS] = GEN6_VBSYNC;
1905         ring->signal_mbox[BCS] = GEN6_NOSYNC;
1906         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1907         ring->init = init_ring_common;
1908
1909         return intel_init_ring_buffer(dev, ring);
1910 }
1911
1912 int
1913 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1914 {
1915         int ret;
1916
1917         if (!ring->gpu_caches_dirty)
1918                 return 0;
1919
1920         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1921         if (ret)
1922                 return ret;
1923
1924         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1925
1926         ring->gpu_caches_dirty = false;
1927         return 0;
1928 }
1929
1930 int
1931 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1932 {
1933         uint32_t flush_domains;
1934         int ret;
1935
1936         flush_domains = 0;
1937         if (ring->gpu_caches_dirty)
1938                 flush_domains = I915_GEM_GPU_DOMAINS;
1939
1940         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1941         if (ret)
1942                 return ret;
1943
1944         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1945
1946         ring->gpu_caches_dirty = false;
1947         return 0;
1948 }