drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/client.h>
  27 #include <core/engctx.h>
  28 #include <core/ramht.h>
  29 #include <core/event.h>
  30 #include <core/class.h>
  31 #include <core/math.h>
  32
  33 #include <subdev/timer.h>
  34 #include <subdev/bar.h>
  35
  36 #include <engine/dmaobj.h>
  37 #include <engine/fifo.h>
  38
  39 #include "nv50.h"
  40
  41 /*******************************************************************************
  42  * FIFO channel objects
  43  ******************************************************************************/
  44
  45 static int
  46 nv84_fifo_context_attach(struct nouveau_object *parent,
  47                          struct nouveau_object *object)
  48 {
  49         struct nouveau_bar *bar = nouveau_bar(parent);
  50         struct nv50_fifo_base *base = (void *)parent->parent;
  51         struct nouveau_gpuobj *ectx = (void *)object;
  52         u64 limit = ectx->addr + ectx->size - 1;
  53         u64 start = ectx->addr;
  54         u32 addr;
  55
  56         switch (nv_engidx(object->engine)) {
  57         case NVDEV_ENGINE_SW   : return 0;
  58         case NVDEV_ENGINE_GR   : addr = 0x0020; break;
  59         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
  60         case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
  61         case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  67         nv_wo32(base->eng, addr + 0x00, 0x00190000);
  68         nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  69         nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  70         nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  71                                         upper_32_bits(start));
  72         nv_wo32(base->eng, addr + 0x10, 0x00000000);
  73         nv_wo32(base->eng, addr + 0x14, 0x00000000);
  74         bar->flush(bar);
  75         return 0;
  76 }
  77
  78 static int
  79 nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
  80                          struct nouveau_object *object)
  81 {
  82         struct nouveau_bar *bar = nouveau_bar(parent);
  83         struct nv50_fifo_priv *priv = (void *)parent->engine;
  84         struct nv50_fifo_base *base = (void *)parent->parent;
  85         struct nv50_fifo_chan *chan = (void *)parent;
  86         u32 addr, save, engn;
  87         bool done;
  88
  89         switch (nv_engidx(object->engine)) {
  90         case NVDEV_ENGINE_SW   : return 0;
  91         case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;
  92         case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
  93         case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
  94         case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
  95         default:
  96                 return -EINVAL;
  97         }
  98
  99         save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
 100         nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
 101         done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
 102         nv_wr32(priv, 0x002520, save);
 103         if (!done) {
 104                 nv_error(priv, "channel %d [%s] unload timeout\n",
 105                          chan->base.chid, nouveau_client_name(chan));
 106                 if (suspend)
 107                         return -EBUSY;
 108         }
 109
 110         nv_wo32(base->eng, addr + 0x00, 0x00000000);
 111         nv_wo32(base->eng, addr + 0x04, 0x00000000);
 112         nv_wo32(base->eng, addr + 0x08, 0x00000000);
 113         nv_wo32(base->eng, addr + 0x0c, 0x00000000);
 114         nv_wo32(base->eng, addr + 0x10, 0x00000000);
 115         nv_wo32(base->eng, addr + 0x14, 0x00000000);
 116         bar->flush(bar);
 117         return 0;
 118 }
 119
 120 static int
 121 nv84_fifo_object_attach(struct nouveau_object *parent,
 122                         struct nouveau_object *object, u32 handle)
 123 {
 124         struct nv50_fifo_chan *chan = (void *)parent;
 125         u32 context;
 126
 127         if (nv_iclass(object, NV_GPUOBJ_CLASS))
 128                 context = nv_gpuobj(object)->node->offset >> 4;
 129         else
 130                 context = 0x00000004; /* just non-zero */
 131
 132         switch (nv_engidx(object->engine)) {
 133         case NVDEV_ENGINE_DMAOBJ:
 134         case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 135         case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 136         case NVDEV_ENGINE_MPEG  :
 137         case NVDEV_ENGINE_PPP   : context |= 0x00200000; break;
 138         case NVDEV_ENGINE_ME    :
 139         case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
 140         case NVDEV_ENGINE_VP    : context |= 0x00400000; break;
 141         case NVDEV_ENGINE_CRYPT :
 142         case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
 143         case NVDEV_ENGINE_BSP   : context |= 0x00600000; break;
 144         default:
 145                 return -EINVAL;
 146         }
 147
 148         return nouveau_ramht_insert(chan->ramht, 0, handle, context);
 149 }
 150
 151 static int
 152 nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
 153                         struct nouveau_object *engine,
 154                         struct nouveau_oclass *oclass, void *data, u32 size,
 155                         struct nouveau_object **pobject)
 156 {
 157         struct nouveau_bar *bar = nouveau_bar(parent);
 158         struct nv50_fifo_base *base = (void *)parent;
 159         struct nv50_fifo_chan *chan;
 160         struct nv03_channel_dma_class *args = data;
 161         int ret;
 162
 163         if (size < sizeof(*args))
 164                 return -EINVAL;
 165
 166         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 167                                           0x2000, args->pushbuf,
 168                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 169                                           (1ULL << NVDEV_ENGINE_SW) |
 170                                           (1ULL << NVDEV_ENGINE_GR) |
 171                                           (1ULL << NVDEV_ENGINE_MPEG) |
 172                                           (1ULL << NVDEV_ENGINE_ME) |
 173                                           (1ULL << NVDEV_ENGINE_VP) |
 174                                           (1ULL << NVDEV_ENGINE_CRYPT) |
 175                                           (1ULL << NVDEV_ENGINE_BSP) |
 176                                           (1ULL << NVDEV_ENGINE_PPP) |
 177                                           (1ULL << NVDEV_ENGINE_COPY0) |
 178                                           (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
 179         *pobject = nv_object(chan);
 180         if (ret)
 181                 return ret;
 182
 183         ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
 184         if (ret)
 185                 return ret;
 186
 187         nv_parent(chan)->context_attach = nv84_fifo_context_attach;
 188         nv_parent(chan)->context_detach = nv84_fifo_context_detach;
 189         nv_parent(chan)->object_attach = nv84_fifo_object_attach;
 190         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 191
 192         nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
 193         nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
 194         nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
 195         nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
 196         nv_wo32(base->ramfc, 0x3c, 0x003f6078);
 197         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 198         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 199         nv_wo32(base->ramfc, 0x4c, 0xffffffff);
 200         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 201         nv_wo32(base->ramfc, 0x78, 0x00000000);
 202         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 203         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 204                                    (4 << 24) /* SEARCH_FULL */ |
 205                                    (chan->ramht->base.node->offset >> 4));
 206         nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
 207         nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
 208         bar->flush(bar);
 209         return 0;
 210 }
 211
 212 static int
 213 nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
 214                         struct nouveau_object *engine,
 215                         struct nouveau_oclass *oclass, void *data, u32 size,
 216                         struct nouveau_object **pobject)
 217 {
 218         struct nouveau_bar *bar = nouveau_bar(parent);
 219         struct nv50_fifo_base *base = (void *)parent;
 220         struct nv50_fifo_chan *chan;
 221         struct nv50_channel_ind_class *args = data;
 222         u64 ioffset, ilength;
 223         int ret;
 224
 225         if (size < sizeof(*args))
 226                 return -EINVAL;
 227
 228         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 229                                           0x2000, args->pushbuf,
 230                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 231                                           (1ULL << NVDEV_ENGINE_SW) |
 232                                           (1ULL << NVDEV_ENGINE_GR) |
 233                                           (1ULL << NVDEV_ENGINE_MPEG) |
 234                                           (1ULL << NVDEV_ENGINE_ME) |
 235                                           (1ULL << NVDEV_ENGINE_VP) |
 236                                           (1ULL << NVDEV_ENGINE_CRYPT) |
 237                                           (1ULL << NVDEV_ENGINE_BSP) |
 238                                           (1ULL << NVDEV_ENGINE_PPP) |
 239                                           (1ULL << NVDEV_ENGINE_COPY0) |
 240                                           (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
 241         *pobject = nv_object(chan);
 242         if (ret)
 243                 return ret;
 244
 245         ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht);
 246         if (ret)
 247                 return ret;
 248
 249         nv_parent(chan)->context_attach = nv84_fifo_context_attach;
 250         nv_parent(chan)->context_detach = nv84_fifo_context_detach;
 251         nv_parent(chan)->object_attach = nv84_fifo_object_attach;
 252         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 253
 254         ioffset = args->ioffset;
 255         ilength = log2i(args->ilength / 8);
 256
 257         nv_wo32(base->ramfc, 0x3c, 0x403f6078);
 258         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 259         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 260         nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
 261         nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
 262         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 263         nv_wo32(base->ramfc, 0x78, 0x00000000);
 264         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 265         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 266                                    (4 << 24) /* SEARCH_FULL */ |
 267                                    (chan->ramht->base.node->offset >> 4));
 268         nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
 269         nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
 270         bar->flush(bar);
 271         return 0;
 272 }
 273
 274 static int
 275 nv84_fifo_chan_init(struct nouveau_object *object)
 276 {
 277         struct nv50_fifo_priv *priv = (void *)object->engine;
 278         struct nv50_fifo_base *base = (void *)object->parent;
 279         struct nv50_fifo_chan *chan = (void *)object;
 280         struct nouveau_gpuobj *ramfc = base->ramfc;
 281         u32 chid = chan->base.chid;
 282         int ret;
 283
 284         ret = nouveau_fifo_channel_init(&chan->base);
 285         if (ret)
 286                 return ret;
 287
 288         nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
 289         nv50_fifo_playlist_update(priv);
 290         return 0;
 291 }
 292
 293 static struct nouveau_ofuncs
 294 nv84_fifo_ofuncs_dma = {
 295         .ctor = nv84_fifo_chan_ctor_dma,
 296         .dtor = nv50_fifo_chan_dtor,
 297         .init = nv84_fifo_chan_init,
 298         .fini = nv50_fifo_chan_fini,
 299         .rd32 = _nouveau_fifo_channel_rd32,
 300         .wr32 = _nouveau_fifo_channel_wr32,
 301 };
 302
 303 static struct nouveau_ofuncs
 304 nv84_fifo_ofuncs_ind = {
 305         .ctor = nv84_fifo_chan_ctor_ind,
 306         .dtor = nv50_fifo_chan_dtor,
 307         .init = nv84_fifo_chan_init,
 308         .fini = nv50_fifo_chan_fini,
 309         .rd32 = _nouveau_fifo_channel_rd32,
 310         .wr32 = _nouveau_fifo_channel_wr32,
 311 };
 312
 313 static struct nouveau_oclass
 314 nv84_fifo_sclass[] = {
 315         { NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma },
 316         { NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind },
 317         {}
 318 };
 319
 320 /*******************************************************************************
 321  * FIFO context - basically just the instmem reserved for the channel
 322  ******************************************************************************/
 323
 324 static int
 325 nv84_fifo_context_ctor(struct nouveau_object *parent,
 326                        struct nouveau_object *engine,
 327                        struct nouveau_oclass *oclass, void *data, u32 size,
 328                        struct nouveau_object **pobject)
 329 {
 330         struct nv50_fifo_base *base;
 331         int ret;
 332
 333         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
 334                                           0x1000, NVOBJ_FLAG_HEAP, &base);
 335         *pobject = nv_object(base);
 336         if (ret)
 337                 return ret;
 338
 339         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0200, 0,
 340                                  NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
 341         if (ret)
 342                 return ret;
 343
 344         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x4000, 0,
 345                                  0, &base->pgd);
 346         if (ret)
 347                 return ret;
 348
 349         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 350         if (ret)
 351                 return ret;
 352
 353         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x1000, 0x400,
 354                                  NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
 355         if (ret)
 356                 return ret;
 357
 358         ret = nouveau_gpuobj_new(parent, nv_object(base), 0x0100, 0x100,
 359                                  NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
 360         if (ret)
 361                 return ret;
 362
 363         return 0;
 364 }
 365
 366 static struct nouveau_oclass
 367 nv84_fifo_cclass = {
 368         .handle = NV_ENGCTX(FIFO, 0x84),
 369         .ofuncs = &(struct nouveau_ofuncs) {
 370                 .ctor = nv84_fifo_context_ctor,
 371                 .dtor = nv50_fifo_context_dtor,
 372                 .init = _nouveau_fifo_context_init,
 373                 .fini = _nouveau_fifo_context_fini,
 374                 .rd32 = _nouveau_fifo_context_rd32,
 375                 .wr32 = _nouveau_fifo_context_wr32,
 376         },
 377 };
 378
 379 /*******************************************************************************
 380  * PFIFO engine
 381  ******************************************************************************/
 382
 383 static void
 384 nv84_fifo_uevent_enable(struct nouveau_event *event, int index)
 385 {
 386         struct nv84_fifo_priv *priv = event->priv;
 387         nv_mask(priv, 0x002140, 0x40000000, 0x40000000);
 388 }
 389
 390 static void
 391 nv84_fifo_uevent_disable(struct nouveau_event *event, int index)
 392 {
 393         struct nv84_fifo_priv *priv = event->priv;
 394         nv_mask(priv, 0x002140, 0x40000000, 0x00000000);
 395 }
 396
 397 static int
 398 nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 399                struct nouveau_oclass *oclass, void *data, u32 size,
 400                struct nouveau_object **pobject)
 401 {
 402         struct nv50_fifo_priv *priv;
 403         int ret;
 404
 405         ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
 406         *pobject = nv_object(priv);
 407         if (ret)
 408                 return ret;
 409
 410         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 411                                 &priv->playlist[0]);
 412         if (ret)
 413                 return ret;
 414
 415         ret = nouveau_gpuobj_new(parent, NULL, 128 * 4, 0x1000, 0,
 416                                 &priv->playlist[1]);
 417         if (ret)
 418                 return ret;
 419
 420         priv->base.uevent->enable = nv84_fifo_uevent_enable;
 421         priv->base.uevent->disable = nv84_fifo_uevent_disable;
 422         priv->base.uevent->priv = priv;
 423
 424         nv_subdev(priv)->unit = 0x00000100;
 425         nv_subdev(priv)->intr = nv04_fifo_intr;
 426         nv_engine(priv)->cclass = &nv84_fifo_cclass;
 427         nv_engine(priv)->sclass = nv84_fifo_sclass;
 428         return 0;
 429 }
 430
 431 struct nouveau_oclass
 432 nv84_fifo_oclass = {
 433         .handle = NV_ENGINE(FIFO, 0x84),
 434         .ofuncs = &(struct nouveau_ofuncs) {
 435                 .ctor = nv84_fifo_ctor,
 436                 .dtor = nv50_fifo_dtor,
 437                 .init = nv50_fifo_init,
 438                 .fini = _nouveau_fifo_fini,
 439         },
 440 };