drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/event.h>
  31 #include <core/class.h>
  32 #include <core/math.h>
  33 #include <core/enum.h>
  34
  35 #include <subdev/timer.h>
  36 #include <subdev/bar.h>
  37 #include <subdev/vm.h>
  38
  39 #include <engine/dmaobj.h>
  40 #include <engine/fifo.h>
  41
  42 struct nvc0_fifo_priv {
  43         struct nouveau_fifo base;
  44         struct nouveau_gpuobj *playlist[2];
  45         int cur_playlist;
  46         struct {
  47                 struct nouveau_gpuobj *mem;
  48                 struct nouveau_vma bar;
  49         } user;
  50         int spoon_nr;
  51 };
  52
  53 struct nvc0_fifo_base {
  54         struct nouveau_fifo_base base;
  55         struct nouveau_gpuobj *pgd;
  56         struct nouveau_vm *vm;
  57 };
  58
  59 struct nvc0_fifo_chan {
  60         struct nouveau_fifo_chan base;
  61 };
  62
  63 /*******************************************************************************
  64  * FIFO channel objects
  65  ******************************************************************************/
  66
  67 static void
  68 nvc0_fifo_playlist_update(struct nvc0_fifo_priv *priv)
  69 {
  70         struct nouveau_bar *bar = nouveau_bar(priv);
  71         struct nouveau_gpuobj *cur;
  72         int i, p;
  73
  74         cur = priv->playlist[priv->cur_playlist];
  75         priv->cur_playlist = !priv->cur_playlist;
  76
  77         for (i = 0, p = 0; i < 128; i++) {
  78                 if (!(nv_rd32(priv, 0x003004 + (i * 8)) & 1))
  79                         continue;
  80                 nv_wo32(cur, p + 0, i);
  81                 nv_wo32(cur, p + 4, 0x00000004);
  82                 p += 8;
  83         }
  84         bar->flush(bar);
  85
  86         nv_wr32(priv, 0x002270, cur->addr >> 12);
  87         nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
  88         if (!nv_wait(priv, 0x00227c, 0x00100000, 0x00000000))
  89                 nv_error(priv, "playlist update failed\n");
  90 }
  91
  92 static int
  93 nvc0_fifo_context_attach(struct nouveau_object *parent,
  94                          struct nouveau_object *object)
  95 {
  96         struct nouveau_bar *bar = nouveau_bar(parent);
  97         struct nvc0_fifo_base *base = (void *)parent->parent;
  98         struct nouveau_engctx *ectx = (void *)object;
  99         u32 addr;
 100         int ret;
 101
 102         switch (nv_engidx(object->engine)) {
 103         case NVDEV_ENGINE_SW   : return 0;
 104         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 105         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 106         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 107         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 108         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 109         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 110         default:
 111                 return -EINVAL;
 112         }
 113
 114         if (!ectx->vma.node) {
 115                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 116                                             NV_MEM_ACCESS_RW, &ectx->vma);
 117                 if (ret)
 118                         return ret;
 119
 120                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 121         }
 122
 123         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 124         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 125         bar->flush(bar);
 126         return 0;
 127 }
 128
 129 static int
 130 nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 131                          struct nouveau_object *object)
 132 {
 133         struct nouveau_bar *bar = nouveau_bar(parent);
 134         struct nvc0_fifo_priv *priv = (void *)parent->engine;
 135         struct nvc0_fifo_base *base = (void *)parent->parent;
 136         struct nvc0_fifo_chan *chan = (void *)parent;
 137         u32 addr;
 138
 139         switch (nv_engidx(object->engine)) {
 140         case NVDEV_ENGINE_SW   : return 0;
 141         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 142         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 143         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 144         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 145         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 146         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 147         default:
 148                 return -EINVAL;
 149         }
 150
 151         nv_wr32(priv, 0x002634, chan->base.chid);
 152         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 153                 nv_error(priv, "channel %d [%s] kick timeout\n",
 154                          chan->base.chid, nouveau_client_name(chan));
 155                 if (suspend)
 156                         return -EBUSY;
 157         }
 158
 159         nv_wo32(base, addr + 0x00, 0x00000000);
 160         nv_wo32(base, addr + 0x04, 0x00000000);
 161         bar->flush(bar);
 162         return 0;
 163 }
 164
 165 static int
 166 nvc0_fifo_chan_ctor(struct nouveau_object *parent,
 167                     struct nouveau_object *engine,
 168                     struct nouveau_oclass *oclass, void *data, u32 size,
 169                     struct nouveau_object **pobject)
 170 {
 171         struct nouveau_bar *bar = nouveau_bar(parent);
 172         struct nvc0_fifo_priv *priv = (void *)engine;
 173         struct nvc0_fifo_base *base = (void *)parent;
 174         struct nvc0_fifo_chan *chan;
 175         struct nv50_channel_ind_class *args = data;
 176         u64 usermem, ioffset, ilength;
 177         int ret, i;
 178
 179         if (size < sizeof(*args))
 180                 return -EINVAL;
 181
 182         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 183                                           priv->user.bar.offset, 0x1000,
 184                                           args->pushbuf,
 185                                           (1ULL << NVDEV_ENGINE_SW) |
 186                                           (1ULL << NVDEV_ENGINE_GR) |
 187                                           (1ULL << NVDEV_ENGINE_COPY0) |
 188                                           (1ULL << NVDEV_ENGINE_COPY1) |
 189                                           (1ULL << NVDEV_ENGINE_BSP) |
 190                                           (1ULL << NVDEV_ENGINE_VP) |
 191                                           (1ULL << NVDEV_ENGINE_PPP), &chan);
 192         *pobject = nv_object(chan);
 193         if (ret)
 194                 return ret;
 195
 196         nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
 197         nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
 198
 199         usermem = chan->base.chid * 0x1000;
 200         ioffset = args->ioffset;
 201         ilength = log2i(args->ilength / 8);
 202
 203         for (i = 0; i < 0x1000; i += 4)
 204                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 205
 206         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 207         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 208         nv_wo32(base, 0x10, 0x0000face);
 209         nv_wo32(base, 0x30, 0xfffff902);
 210         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 211         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 212         nv_wo32(base, 0x54, 0x00000002);
 213         nv_wo32(base, 0x84, 0x20400000);
 214         nv_wo32(base, 0x94, 0x30000001);
 215         nv_wo32(base, 0x9c, 0x00000100);
 216         nv_wo32(base, 0xa4, 0x1f1f1f1f);
 217         nv_wo32(base, 0xa8, 0x1f1f1f1f);
 218         nv_wo32(base, 0xac, 0x0000001f);
 219         nv_wo32(base, 0xb8, 0xf8000000);
 220         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 221         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 222         bar->flush(bar);
 223         return 0;
 224 }
 225
 226 static int
 227 nvc0_fifo_chan_init(struct nouveau_object *object)
 228 {
 229         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 230         struct nvc0_fifo_priv *priv = (void *)object->engine;
 231         struct nvc0_fifo_chan *chan = (void *)object;
 232         u32 chid = chan->base.chid;
 233         int ret;
 234
 235         ret = nouveau_fifo_channel_init(&chan->base);
 236         if (ret)
 237                 return ret;
 238
 239         nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
 240         nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
 241         nvc0_fifo_playlist_update(priv);
 242         return 0;
 243 }
 244
 245 static int
 246 nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 247 {
 248         struct nvc0_fifo_priv *priv = (void *)object->engine;
 249         struct nvc0_fifo_chan *chan = (void *)object;
 250         u32 chid = chan->base.chid;
 251
 252         nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
 253         nvc0_fifo_playlist_update(priv);
 254         nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
 255
 256         return nouveau_fifo_channel_fini(&chan->base, suspend);
 257 }
 258
 259 static struct nouveau_ofuncs
 260 nvc0_fifo_ofuncs = {
 261         .ctor = nvc0_fifo_chan_ctor,
 262         .dtor = _nouveau_fifo_channel_dtor,
 263         .init = nvc0_fifo_chan_init,
 264         .fini = nvc0_fifo_chan_fini,
 265         .rd32 = _nouveau_fifo_channel_rd32,
 266         .wr32 = _nouveau_fifo_channel_wr32,
 267 };
 268
 269 static struct nouveau_oclass
 270 nvc0_fifo_sclass[] = {
 271         { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs },
 272         {}
 273 };
 274
 275 /*******************************************************************************
 276  * FIFO context - instmem heap and vm setup
 277  ******************************************************************************/
 278
 279 static int
 280 nvc0_fifo_context_ctor(struct nouveau_object *parent,
 281                        struct nouveau_object *engine,
 282                        struct nouveau_oclass *oclass, void *data, u32 size,
 283                        struct nouveau_object **pobject)
 284 {
 285         struct nvc0_fifo_base *base;
 286         int ret;
 287
 288         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 289                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC |
 290                                           NVOBJ_FLAG_HEAP, &base);
 291         *pobject = nv_object(base);
 292         if (ret)
 293                 return ret;
 294
 295         ret = nouveau_gpuobj_new(parent, NULL, 0x10000, 0x1000, 0, &base->pgd);
 296         if (ret)
 297                 return ret;
 298
 299         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 300         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 301         nv_wo32(base, 0x0208, 0xffffffff);
 302         nv_wo32(base, 0x020c, 0x000000ff);
 303
 304         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 305         if (ret)
 306                 return ret;
 307
 308         return 0;
 309 }
 310
 311 static void
 312 nvc0_fifo_context_dtor(struct nouveau_object *object)
 313 {
 314         struct nvc0_fifo_base *base = (void *)object;
 315         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 316         nouveau_gpuobj_ref(NULL, &base->pgd);
 317         nouveau_fifo_context_destroy(&base->base);
 318 }
 319
 320 static struct nouveau_oclass
 321 nvc0_fifo_cclass = {
 322         .handle = NV_ENGCTX(FIFO, 0xc0),
 323         .ofuncs = &(struct nouveau_ofuncs) {
 324                 .ctor = nvc0_fifo_context_ctor,
 325                 .dtor = nvc0_fifo_context_dtor,
 326                 .init = _nouveau_fifo_context_init,
 327                 .fini = _nouveau_fifo_context_fini,
 328                 .rd32 = _nouveau_fifo_context_rd32,
 329                 .wr32 = _nouveau_fifo_context_wr32,
 330         },
 331 };
 332
 333 /*******************************************************************************
 334  * PFIFO engine
 335  ******************************************************************************/
 336
 337 static const struct nouveau_enum nvc0_fifo_fault_unit[] = {
 338         { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
 339         { 0x03, "PEEPHOLE" },
 340         { 0x04, "BAR1" },
 341         { 0x05, "BAR3" },
 342         { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
 343         { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
 344         { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
 345         { 0x13, "PCOUNTER" },
 346         { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
 347         { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
 348         { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
 349         { 0x17, "PDAEMON" },
 350         {}
 351 };
 352
 353 static const struct nouveau_enum nvc0_fifo_fault_reason[] = {
 354         { 0x00, "PT_NOT_PRESENT" },
 355         { 0x01, "PT_TOO_SHORT" },
 356         { 0x02, "PAGE_NOT_PRESENT" },
 357         { 0x03, "VM_LIMIT_EXCEEDED" },
 358         { 0x04, "NO_CHANNEL" },
 359         { 0x05, "PAGE_SYSTEM_ONLY" },
 360         { 0x06, "PAGE_READ_ONLY" },
 361         { 0x0a, "COMPRESSED_SYSRAM" },
 362         { 0x0c, "INVALID_STORAGE_TYPE" },
 363         {}
 364 };
 365
 366 static const struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
 367         { 0x01, "PCOPY0" },
 368         { 0x02, "PCOPY1" },
 369         { 0x04, "DISPATCH" },
 370         { 0x05, "CTXCTL" },
 371         { 0x06, "PFIFO" },
 372         { 0x07, "BAR_READ" },
 373         { 0x08, "BAR_WRITE" },
 374         { 0x0b, "PVP" },
 375         { 0x0c, "PPPP" },
 376         { 0x0d, "PBSP" },
 377         { 0x11, "PCOUNTER" },
 378         { 0x12, "PDAEMON" },
 379         { 0x14, "CCACHE" },
 380         { 0x15, "CCACHE_POST" },
 381         {}
 382 };
 383
 384 static const struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
 385         { 0x01, "TEX" },
 386         { 0x0c, "ESETUP" },
 387         { 0x0e, "CTXCTL" },
 388         { 0x0f, "PROP" },
 389         {}
 390 };
 391
 392 static const struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
 393 /*      { 0x00008000, "" }      seen with null ib push */
 394         { 0x00200000, "ILLEGAL_MTHD" },
 395         { 0x00800000, "EMPTY_SUBC" },
 396         {}
 397 };
 398
 399 static void
 400 nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
 401 {
 402         u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
 403         u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
 404         u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
 405         u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
 406         u32 client = (stat & 0x00001f00) >> 8;
 407         const struct nouveau_enum *en;
 408         struct nouveau_engine *engine;
 409         struct nouveau_object *engctx = NULL;
 410
 411         switch (unit) {
 412         case 3: /* PEEPHOLE */
 413                 nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
 414                 break;
 415         case 4: /* BAR1 */
 416                 nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
 417                 break;
 418         case 5: /* BAR3 */
 419                 nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
 420                 break;
 421         default:
 422                 break;
 423         }
 424
 425         nv_error(priv, "%s fault at 0x%010llx [", (stat & 0x00000080) ?
 426                  "write" : "read", (u64)vahi << 32 | valo);
 427         nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
 428         pr_cont("] from ");
 429         en = nouveau_enum_print(nvc0_fifo_fault_unit, unit);
 430         if (stat & 0x00000040) {
 431                 pr_cont("/");
 432                 nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
 433         } else {
 434                 pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
 435                 nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
 436         }
 437
 438         if (en && en->data2) {
 439                 engine = nouveau_engine(priv, en->data2);
 440                 if (engine)
 441                         engctx = nouveau_engctx_get(engine, inst);
 442
 443         }
 444         pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
 445                         nouveau_client_name(engctx));
 446
 447         nouveau_engctx_put(engctx);
 448 }
 449
 450 static int
 451 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 452 {
 453         struct nvc0_fifo_chan *chan = NULL;
 454         struct nouveau_handle *bind;
 455         unsigned long flags;
 456         int ret = -EINVAL;
 457
 458         spin_lock_irqsave(&priv->base.lock, flags);
 459         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 460                 chan = (void *)priv->base.channel[chid];
 461         if (unlikely(!chan))
 462                 goto out;
 463
 464         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 465         if (likely(bind)) {
 466                 if (!mthd || !nv_call(bind->object, mthd, data))
 467                         ret = 0;
 468                 nouveau_namedb_put(bind);
 469         }
 470
 471 out:
 472         spin_unlock_irqrestore(&priv->base.lock, flags);
 473         return ret;
 474 }
 475
 476 static void
 477 nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
 478 {
 479         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 480         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 481         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 482         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
 483         u32 subc = (addr & 0x00070000) >> 16;
 484         u32 mthd = (addr & 0x00003ffc);
 485         u32 show = stat;
 486
 487         if (stat & 0x00200000) {
 488                 if (mthd == 0x0054) {
 489                         if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
 490                                 show &= ~0x00200000;
 491                 }
 492         }
 493
 494         if (stat & 0x00800000) {
 495                 if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
 496                         show &= ~0x00800000;
 497         }
 498
 499         if (show) {
 500                 nv_error(priv, "SUBFIFO%d:", unit);
 501                 nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
 502                 pr_cont("\n");
 503                 nv_error(priv,
 504                          "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
 505                          unit, chid,
 506                          nouveau_client_name_for_fifo_chid(&priv->base, chid),
 507                          subc, mthd, data);
 508         }
 509
 510         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 511         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 512 }
 513
 514 static void
 515 nvc0_fifo_intr(struct nouveau_subdev *subdev)
 516 {
 517         struct nvc0_fifo_priv *priv = (void *)subdev;
 518         u32 mask = nv_rd32(priv, 0x002140);
 519         u32 stat = nv_rd32(priv, 0x002100) & mask;
 520
 521         if (stat & 0x00000001) {
 522                 u32 intr = nv_rd32(priv, 0x00252c);
 523                 nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr);
 524                 nv_wr32(priv, 0x002100, 0x00000001);
 525                 stat &= ~0x00000001;
 526         }
 527
 528         if (stat & 0x00000100) {
 529                 u32 intr = nv_rd32(priv, 0x00254c);
 530                 nv_warn(priv, "INTR 0x00000100: 0x%08x\n", intr);
 531                 nv_wr32(priv, 0x002100, 0x00000100);
 532                 stat &= ~0x00000100;
 533         }
 534
 535         if (stat & 0x00010000) {
 536                 u32 intr = nv_rd32(priv, 0x00256c);
 537                 nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr);
 538                 nv_wr32(priv, 0x002100, 0x00010000);
 539                 stat &= ~0x00010000;
 540         }
 541
 542         if (stat & 0x01000000) {
 543                 u32 intr = nv_rd32(priv, 0x00258c);
 544                 nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr);
 545                 nv_wr32(priv, 0x002100, 0x01000000);
 546                 stat &= ~0x01000000;
 547         }
 548
 549         if (stat & 0x10000000) {
 550                 u32 units = nv_rd32(priv, 0x00259c);
 551                 u32 u = units;
 552
 553                 while (u) {
 554                         int i = ffs(u) - 1;
 555                         nvc0_fifo_isr_vm_fault(priv, i);
 556                         u &= ~(1 << i);
 557                 }
 558
 559                 nv_wr32(priv, 0x00259c, units);
 560                 stat &= ~0x10000000;
 561         }
 562
 563         if (stat & 0x20000000) {
 564                 u32 units = nv_rd32(priv, 0x0025a0);
 565                 u32 u = units;
 566
 567                 while (u) {
 568                         int i = ffs(u) - 1;
 569                         nvc0_fifo_isr_subfifo_intr(priv, i);
 570                         u &= ~(1 << i);
 571                 }
 572
 573                 nv_wr32(priv, 0x0025a0, units);
 574                 stat &= ~0x20000000;
 575         }
 576
 577         if (stat & 0x40000000) {
 578                 u32 intr0 = nv_rd32(priv, 0x0025a4);
 579                 u32 intr1 = nv_mask(priv, 0x002a00, 0x00000000, 0x00000);
 580                 nv_debug(priv, "INTR 0x40000000: 0x%08x 0x%08x\n",
 581                                intr0, intr1);
 582                 stat &= ~0x40000000;
 583         }
 584
 585         if (stat & 0x80000000) {
 586                 u32 intr = nv_mask(priv, 0x0025a8, 0x00000000, 0x00000000);
 587                 nouveau_event_trigger(priv->base.uevent, 0);
 588                 nv_debug(priv, "INTR 0x80000000: 0x%08x\n", intr);
 589                 stat &= ~0x80000000;
 590         }
 591
 592         if (stat) {
 593                 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
 594                 nv_wr32(priv, 0x002100, stat);
 595                 nv_wr32(priv, 0x002140, 0);
 596         }
 597 }
 598
 599 static void
 600 nvc0_fifo_uevent_enable(struct nouveau_event *event, int index)
 601 {
 602         struct nvc0_fifo_priv *priv = event->priv;
 603         nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
 604 }
 605
 606 static void
 607 nvc0_fifo_uevent_disable(struct nouveau_event *event, int index)
 608 {
 609         struct nvc0_fifo_priv *priv = event->priv;
 610         nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
 611 }
 612
 613 static int
 614 nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 615                struct nouveau_oclass *oclass, void *data, u32 size,
 616                struct nouveau_object **pobject)
 617 {
 618         struct nvc0_fifo_priv *priv;
 619         int ret;
 620
 621         ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
 622         *pobject = nv_object(priv);
 623         if (ret)
 624                 return ret;
 625
 626         ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0x1000, 0,
 627                                 &priv->playlist[0]);
 628         if (ret)
 629                 return ret;
 630
 631         ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0x1000, 0,
 632                                 &priv->playlist[1]);
 633         if (ret)
 634                 return ret;
 635
 636         ret = nouveau_gpuobj_new(parent, NULL, 128 * 0x1000, 0x1000, 0,
 637                                 &priv->user.mem);
 638         if (ret)
 639                 return ret;
 640
 641         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 642                                 &priv->user.bar);
 643         if (ret)
 644                 return ret;
 645
 646         priv->base.uevent->enable = nvc0_fifo_uevent_enable;
 647         priv->base.uevent->disable = nvc0_fifo_uevent_disable;
 648         priv->base.uevent->priv = priv;
 649
 650         nv_subdev(priv)->unit = 0x00000100;
 651         nv_subdev(priv)->intr = nvc0_fifo_intr;
 652         nv_engine(priv)->cclass = &nvc0_fifo_cclass;
 653         nv_engine(priv)->sclass = nvc0_fifo_sclass;
 654         return 0;
 655 }
 656
 657 static void
 658 nvc0_fifo_dtor(struct nouveau_object *object)
 659 {
 660         struct nvc0_fifo_priv *priv = (void *)object;
 661
 662         nouveau_gpuobj_unmap(&priv->user.bar);
 663         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 664         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 665         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 666
 667         nouveau_fifo_destroy(&priv->base);
 668 }
 669
 670 static int
 671 nvc0_fifo_init(struct nouveau_object *object)
 672 {
 673         struct nvc0_fifo_priv *priv = (void *)object;
 674         int ret, i;
 675
 676         ret = nouveau_fifo_init(&priv->base);
 677         if (ret)
 678                 return ret;
 679
 680         nv_wr32(priv, 0x000204, 0xffffffff);
 681         nv_wr32(priv, 0x002204, 0xffffffff);
 682
 683         priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
 684         nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
 685
 686         /* assign engines to subfifos */
 687         if (priv->spoon_nr >= 3) {
 688                 nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
 689                 nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
 690                 nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
 691                 nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
 692                 nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
 693                 nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
 694         }
 695
 696         /* PSUBFIFO[n] */
 697         for (i = 0; i < priv->spoon_nr; i++) {
 698                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 699                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 700                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 701         }
 702
 703         nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
 704         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 705
 706         nv_wr32(priv, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
 707         nv_wr32(priv, 0x002100, 0xffffffff);
 708         nv_wr32(priv, 0x002140, 0x3fffffff);
 709         nv_wr32(priv, 0x002628, 0x00000001); /* makes mthd 0x20 work */
 710         return 0;
 711 }
 712
 713 struct nouveau_oclass
 714 nvc0_fifo_oclass = {
 715         .handle = NV_ENGINE(FIFO, 0xc0),
 716         .ofuncs = &(struct nouveau_ofuncs) {
 717                 .ctor = nvc0_fifo_ctor,
 718                 .dtor = nvc0_fifo_dtor,
 719                 .init = nvc0_fifo_init,
 720                 .fini = _nouveau_fifo_fini,
 721         },
 722 };