drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "radeon_drm.h"
  32 #include "nid.h"
  33 #include "atom.h"
  34 #include "ni_reg.h"
  35 #include "cayman_blit_shaders.h"
  36
  37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  40 extern void evergreen_mc_program(struct radeon_device *rdev);
  41 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  42 extern int evergreen_mc_init(struct radeon_device *rdev);
  43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  45
  46 #define EVERGREEN_PFP_UCODE_SIZE 1120
  47 #define EVERGREEN_PM4_UCODE_SIZE 1376
  48 #define EVERGREEN_RLC_UCODE_SIZE 768
  49 #define BTC_MC_UCODE_SIZE 6024
  50
  51 #define CAYMAN_PFP_UCODE_SIZE 2176
  52 #define CAYMAN_PM4_UCODE_SIZE 2176
  53 #define CAYMAN_RLC_UCODE_SIZE 1024
  54 #define CAYMAN_MC_UCODE_SIZE 6037
  55
  56 /* Firmware Names */
  57 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  58 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  59 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  60 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  61 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  62 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  63 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  64 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  65 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  66 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  67 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  68 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  69 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  70 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  71
  72 #define BTC_IO_MC_REGS_SIZE 29
  73
  74 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  75         {0x00000077, 0xff010100},
  76         {0x00000078, 0x00000000},
  77         {0x00000079, 0x00001434},
  78         {0x0000007a, 0xcc08ec08},
  79         {0x0000007b, 0x00040000},
  80         {0x0000007c, 0x000080c0},
  81         {0x0000007d, 0x09000000},
  82         {0x0000007e, 0x00210404},
  83         {0x00000081, 0x08a8e800},
  84         {0x00000082, 0x00030444},
  85         {0x00000083, 0x00000000},
  86         {0x00000085, 0x00000001},
  87         {0x00000086, 0x00000002},
  88         {0x00000087, 0x48490000},
  89         {0x00000088, 0x20244647},
  90         {0x00000089, 0x00000005},
  91         {0x0000008b, 0x66030000},
  92         {0x0000008c, 0x00006603},
  93         {0x0000008d, 0x00000100},
  94         {0x0000008f, 0x00001c0a},
  95         {0x00000090, 0xff000001},
  96         {0x00000094, 0x00101101},
  97         {0x00000095, 0x00000fff},
  98         {0x00000096, 0x00116fff},
  99         {0x00000097, 0x60010000},
 100         {0x00000098, 0x10010000},
 101         {0x00000099, 0x00006000},
 102         {0x0000009a, 0x00001000},
 103         {0x0000009f, 0x00946a00}
 104 };
 105
 106 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 107         {0x00000077, 0xff010100},
 108         {0x00000078, 0x00000000},
 109         {0x00000079, 0x00001434},
 110         {0x0000007a, 0xcc08ec08},
 111         {0x0000007b, 0x00040000},
 112         {0x0000007c, 0x000080c0},
 113         {0x0000007d, 0x09000000},
 114         {0x0000007e, 0x00210404},
 115         {0x00000081, 0x08a8e800},
 116         {0x00000082, 0x00030444},
 117         {0x00000083, 0x00000000},
 118         {0x00000085, 0x00000001},
 119         {0x00000086, 0x00000002},
 120         {0x00000087, 0x48490000},
 121         {0x00000088, 0x20244647},
 122         {0x00000089, 0x00000005},
 123         {0x0000008b, 0x66030000},
 124         {0x0000008c, 0x00006603},
 125         {0x0000008d, 0x00000100},
 126         {0x0000008f, 0x00001c0a},
 127         {0x00000090, 0xff000001},
 128         {0x00000094, 0x00101101},
 129         {0x00000095, 0x00000fff},
 130         {0x00000096, 0x00116fff},
 131         {0x00000097, 0x60010000},
 132         {0x00000098, 0x10010000},
 133         {0x00000099, 0x00006000},
 134         {0x0000009a, 0x00001000},
 135         {0x0000009f, 0x00936a00}
 136 };
 137
 138 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 139         {0x00000077, 0xff010100},
 140         {0x00000078, 0x00000000},
 141         {0x00000079, 0x00001434},
 142         {0x0000007a, 0xcc08ec08},
 143         {0x0000007b, 0x00040000},
 144         {0x0000007c, 0x000080c0},
 145         {0x0000007d, 0x09000000},
 146         {0x0000007e, 0x00210404},
 147         {0x00000081, 0x08a8e800},
 148         {0x00000082, 0x00030444},
 149         {0x00000083, 0x00000000},
 150         {0x00000085, 0x00000001},
 151         {0x00000086, 0x00000002},
 152         {0x00000087, 0x48490000},
 153         {0x00000088, 0x20244647},
 154         {0x00000089, 0x00000005},
 155         {0x0000008b, 0x66030000},
 156         {0x0000008c, 0x00006603},
 157         {0x0000008d, 0x00000100},
 158         {0x0000008f, 0x00001c0a},
 159         {0x00000090, 0xff000001},
 160         {0x00000094, 0x00101101},
 161         {0x00000095, 0x00000fff},
 162         {0x00000096, 0x00116fff},
 163         {0x00000097, 0x60010000},
 164         {0x00000098, 0x10010000},
 165         {0x00000099, 0x00006000},
 166         {0x0000009a, 0x00001000},
 167         {0x0000009f, 0x00916a00}
 168 };
 169
 170 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 171         {0x00000077, 0xff010100},
 172         {0x00000078, 0x00000000},
 173         {0x00000079, 0x00001434},
 174         {0x0000007a, 0xcc08ec08},
 175         {0x0000007b, 0x00040000},
 176         {0x0000007c, 0x000080c0},
 177         {0x0000007d, 0x09000000},
 178         {0x0000007e, 0x00210404},
 179         {0x00000081, 0x08a8e800},
 180         {0x00000082, 0x00030444},
 181         {0x00000083, 0x00000000},
 182         {0x00000085, 0x00000001},
 183         {0x00000086, 0x00000002},
 184         {0x00000087, 0x48490000},
 185         {0x00000088, 0x20244647},
 186         {0x00000089, 0x00000005},
 187         {0x0000008b, 0x66030000},
 188         {0x0000008c, 0x00006603},
 189         {0x0000008d, 0x00000100},
 190         {0x0000008f, 0x00001c0a},
 191         {0x00000090, 0xff000001},
 192         {0x00000094, 0x00101101},
 193         {0x00000095, 0x00000fff},
 194         {0x00000096, 0x00116fff},
 195         {0x00000097, 0x60010000},
 196         {0x00000098, 0x10010000},
 197         {0x00000099, 0x00006000},
 198         {0x0000009a, 0x00001000},
 199         {0x0000009f, 0x00976b00}
 200 };
 201
 202 int ni_mc_load_microcode(struct radeon_device *rdev)
 203 {
 204         const __be32 *fw_data;
 205         u32 mem_type, running, blackout = 0;
 206         u32 *io_mc_regs;
 207         int i, ucode_size, regs_size;
 208
 209         if (!rdev->mc_fw)
 210                 return -EINVAL;
 211
 212         switch (rdev->family) {
 213         case CHIP_BARTS:
 214                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 215                 ucode_size = BTC_MC_UCODE_SIZE;
 216                 regs_size = BTC_IO_MC_REGS_SIZE;
 217                 break;
 218         case CHIP_TURKS:
 219                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 220                 ucode_size = BTC_MC_UCODE_SIZE;
 221                 regs_size = BTC_IO_MC_REGS_SIZE;
 222                 break;
 223         case CHIP_CAICOS:
 224         default:
 225                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 226                 ucode_size = BTC_MC_UCODE_SIZE;
 227                 regs_size = BTC_IO_MC_REGS_SIZE;
 228                 break;
 229         case CHIP_CAYMAN:
 230                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 231                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 232                 regs_size = BTC_IO_MC_REGS_SIZE;
 233                 break;
 234         }
 235
 236         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 237         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 238
 239         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 240                 if (running) {
 241                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 242                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 243                 }
 244
 245                 /* reset the engine and set to writable */
 246                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 247                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 248
 249                 /* load mc io regs */
 250                 for (i = 0; i < regs_size; i++) {
 251                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 252                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 253                 }
 254                 /* load the MC ucode */
 255                 fw_data = (const __be32 *)rdev->mc_fw->data;
 256                 for (i = 0; i < ucode_size; i++)
 257                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 258
 259                 /* put the engine back into the active state */
 260                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 261                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 262                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 263
 264                 /* wait for training to complete */
 265                 for (i = 0; i < rdev->usec_timeout; i++) {
 266                         if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
 267                                 break;
 268                         udelay(1);
 269                 }
 270
 271                 if (running)
 272                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 273         }
 274
 275         return 0;
 276 }
 277
 278 int ni_init_microcode(struct radeon_device *rdev)
 279 {
 280         struct platform_device *pdev;
 281         const char *chip_name;
 282         const char *rlc_chip_name;
 283         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 284         char fw_name[30];
 285         int err;
 286
 287         DRM_DEBUG("\n");
 288
 289         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 290         err = IS_ERR(pdev);
 291         if (err) {
 292                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 293                 return -EINVAL;
 294         }
 295
 296         switch (rdev->family) {
 297         case CHIP_BARTS:
 298                 chip_name = "BARTS";
 299                 rlc_chip_name = "BTC";
 300                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 301                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 302                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 303                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 304                 break;
 305         case CHIP_TURKS:
 306                 chip_name = "TURKS";
 307                 rlc_chip_name = "BTC";
 308                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 309                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 310                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 311                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 312                 break;
 313         case CHIP_CAICOS:
 314                 chip_name = "CAICOS";
 315                 rlc_chip_name = "BTC";
 316                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 317                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 318                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 319                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 320                 break;
 321         case CHIP_CAYMAN:
 322                 chip_name = "CAYMAN";
 323                 rlc_chip_name = "CAYMAN";
 324                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 325                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 326                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 327                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 328                 break;
 329         default: BUG();
 330         }
 331
 332         DRM_INFO("Loading %s Microcode\n", chip_name);
 333
 334         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 335         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 336         if (err)
 337                 goto out;
 338         if (rdev->pfp_fw->size != pfp_req_size) {
 339                 printk(KERN_ERR
 340                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 341                        rdev->pfp_fw->size, fw_name);
 342                 err = -EINVAL;
 343                 goto out;
 344         }
 345
 346         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 347         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 348         if (err)
 349                 goto out;
 350         if (rdev->me_fw->size != me_req_size) {
 351                 printk(KERN_ERR
 352                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 353                        rdev->me_fw->size, fw_name);
 354                 err = -EINVAL;
 355         }
 356
 357         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 358         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 359         if (err)
 360                 goto out;
 361         if (rdev->rlc_fw->size != rlc_req_size) {
 362                 printk(KERN_ERR
 363                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 364                        rdev->rlc_fw->size, fw_name);
 365                 err = -EINVAL;
 366         }
 367
 368         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 369         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 370         if (err)
 371                 goto out;
 372         if (rdev->mc_fw->size != mc_req_size) {
 373                 printk(KERN_ERR
 374                        "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 375                        rdev->mc_fw->size, fw_name);
 376                 err = -EINVAL;
 377         }
 378 out:
 379         platform_device_unregister(pdev);
 380
 381         if (err) {
 382                 if (err != -EINVAL)
 383                         printk(KERN_ERR
 384                                "ni_cp: Failed to load firmware \"%s\"\n",
 385                                fw_name);
 386                 release_firmware(rdev->pfp_fw);
 387                 rdev->pfp_fw = NULL;
 388                 release_firmware(rdev->me_fw);
 389                 rdev->me_fw = NULL;
 390                 release_firmware(rdev->rlc_fw);
 391                 rdev->rlc_fw = NULL;
 392                 release_firmware(rdev->mc_fw);
 393                 rdev->mc_fw = NULL;
 394         }
 395         return err;
 396 }
 397
 398 /*
 399  * Core functions
 400  */
 401 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 402                                                u32 num_tile_pipes,
 403                                                u32 num_backends_per_asic,
 404                                                u32 *backend_disable_mask_per_asic,
 405                                                u32 num_shader_engines)
 406 {
 407         u32 backend_map = 0;
 408         u32 enabled_backends_mask = 0;
 409         u32 enabled_backends_count = 0;
 410         u32 num_backends_per_se;
 411         u32 cur_pipe;
 412         u32 swizzle_pipe[CAYMAN_MAX_PIPES];
 413         u32 cur_backend = 0;
 414         u32 i;
 415         bool force_no_swizzle;
 416
 417         /* force legal values */
 418         if (num_tile_pipes < 1)
 419                 num_tile_pipes = 1;
 420         if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
 421                 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 422         if (num_shader_engines < 1)
 423                 num_shader_engines = 1;
 424         if (num_shader_engines > rdev->config.cayman.max_shader_engines)
 425                 num_shader_engines = rdev->config.cayman.max_shader_engines;
 426         if (num_backends_per_asic < num_shader_engines)
 427                 num_backends_per_asic = num_shader_engines;
 428         if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
 429                 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
 430
 431         /* make sure we have the same number of backends per se */
 432         num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
 433         /* set up the number of backends per se */
 434         num_backends_per_se = num_backends_per_asic / num_shader_engines;
 435         if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
 436                 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
 437                 num_backends_per_asic = num_backends_per_se * num_shader_engines;
 438         }
 439
 440         /* create enable mask and count for enabled backends */
 441         for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 442                 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
 443                         enabled_backends_mask |= (1 << i);
 444                         ++enabled_backends_count;
 445                 }
 446                 if (enabled_backends_count == num_backends_per_asic)
 447                         break;
 448         }
 449
 450         /* force the backends mask to match the current number of backends */
 451         if (enabled_backends_count != num_backends_per_asic) {
 452                 u32 this_backend_enabled;
 453                 u32 shader_engine;
 454                 u32 backend_per_se;
 455
 456                 enabled_backends_mask = 0;
 457                 enabled_backends_count = 0;
 458                 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
 459                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 460                         /* calc the current se */
 461                         shader_engine = i / rdev->config.cayman.max_backends_per_se;
 462                         /* calc the backend per se */
 463                         backend_per_se = i % rdev->config.cayman.max_backends_per_se;
 464                         /* default to not enabled */
 465                         this_backend_enabled = 0;
 466                         if ((shader_engine < num_shader_engines) &&
 467                             (backend_per_se < num_backends_per_se))
 468                                 this_backend_enabled = 1;
 469                         if (this_backend_enabled) {
 470                                 enabled_backends_mask |= (1 << i);
 471                                 *backend_disable_mask_per_asic &= ~(1 << i);
 472                                 ++enabled_backends_count;
 473                         }
 474                 }
 475         }
 476
 477
 478         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
 479         switch (rdev->family) {
 480         case CHIP_CAYMAN:
 481                 force_no_swizzle = true;
 482                 break;
 483         default:
 484                 force_no_swizzle = false;
 485                 break;
 486         }
 487         if (force_no_swizzle) {
 488                 bool last_backend_enabled = false;
 489
 490                 force_no_swizzle = false;
 491                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 492                         if (((enabled_backends_mask >> i) & 1) == 1) {
 493                                 if (last_backend_enabled)
 494                                         force_no_swizzle = true;
 495                                 last_backend_enabled = true;
 496                         } else
 497                                 last_backend_enabled = false;
 498                 }
 499         }
 500
 501         switch (num_tile_pipes) {
 502         case 1:
 503         case 3:
 504         case 5:
 505         case 7:
 506                 DRM_ERROR("odd number of pipes!\n");
 507                 break;
 508         case 2:
 509                 swizzle_pipe[0] = 0;
 510                 swizzle_pipe[1] = 1;
 511                 break;
 512         case 4:
 513                 if (force_no_swizzle) {
 514                         swizzle_pipe[0] = 0;
 515                         swizzle_pipe[1] = 1;
 516                         swizzle_pipe[2] = 2;
 517                         swizzle_pipe[3] = 3;
 518                 } else {
 519                         swizzle_pipe[0] = 0;
 520                         swizzle_pipe[1] = 2;
 521                         swizzle_pipe[2] = 1;
 522                         swizzle_pipe[3] = 3;
 523                 }
 524                 break;
 525         case 6:
 526                 if (force_no_swizzle) {
 527                         swizzle_pipe[0] = 0;
 528                         swizzle_pipe[1] = 1;
 529                         swizzle_pipe[2] = 2;
 530                         swizzle_pipe[3] = 3;
 531                         swizzle_pipe[4] = 4;
 532                         swizzle_pipe[5] = 5;
 533                 } else {
 534                         swizzle_pipe[0] = 0;
 535                         swizzle_pipe[1] = 2;
 536                         swizzle_pipe[2] = 4;
 537                         swizzle_pipe[3] = 1;
 538                         swizzle_pipe[4] = 3;
 539                         swizzle_pipe[5] = 5;
 540                 }
 541                 break;
 542         case 8:
 543                 if (force_no_swizzle) {
 544                         swizzle_pipe[0] = 0;
 545                         swizzle_pipe[1] = 1;
 546                         swizzle_pipe[2] = 2;
 547                         swizzle_pipe[3] = 3;
 548                         swizzle_pipe[4] = 4;
 549                         swizzle_pipe[5] = 5;
 550                         swizzle_pipe[6] = 6;
 551                         swizzle_pipe[7] = 7;
 552                 } else {
 553                         swizzle_pipe[0] = 0;
 554                         swizzle_pipe[1] = 2;
 555                         swizzle_pipe[2] = 4;
 556                         swizzle_pipe[3] = 6;
 557                         swizzle_pipe[4] = 1;
 558                         swizzle_pipe[5] = 3;
 559                         swizzle_pipe[6] = 5;
 560                         swizzle_pipe[7] = 7;
 561                 }
 562                 break;
 563         }
 564
 565         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 566                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 567                         cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 568
 569                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
 570
 571                 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 572         }
 573
 574         return backend_map;
 575 }
 576
 577 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
 578                                             u32 disable_mask_per_se,
 579                                             u32 max_disable_mask_per_se,
 580                                             u32 num_shader_engines)
 581 {
 582         u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
 583         u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
 584
 585         if (num_shader_engines == 1)
 586                 return disable_mask_per_asic;
 587         else if (num_shader_engines == 2)
 588                 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
 589         else
 590                 return 0xffffffff;
 591 }
 592
 593 static void cayman_gpu_init(struct radeon_device *rdev)
 594 {
 595         u32 cc_rb_backend_disable = 0;
 596         u32 cc_gc_shader_pipe_config;
 597         u32 gb_addr_config = 0;
 598         u32 mc_shared_chmap, mc_arb_ramcfg;
 599         u32 gb_backend_map;
 600         u32 cgts_tcc_disable;
 601         u32 sx_debug_1;
 602         u32 smx_dc_ctl0;
 603         u32 gc_user_shader_pipe_config;
 604         u32 gc_user_rb_backend_disable;
 605         u32 cgts_user_tcc_disable;
 606         u32 cgts_sm_ctrl_reg;
 607         u32 hdp_host_path_cntl;
 608         u32 tmp;
 609         int i, j;
 610
 611         switch (rdev->family) {
 612         case CHIP_CAYMAN:
 613         default:
 614                 rdev->config.cayman.max_shader_engines = 2;
 615                 rdev->config.cayman.max_pipes_per_simd = 4;
 616                 rdev->config.cayman.max_tile_pipes = 8;
 617                 rdev->config.cayman.max_simds_per_se = 12;
 618                 rdev->config.cayman.max_backends_per_se = 4;
 619                 rdev->config.cayman.max_texture_channel_caches = 8;
 620                 rdev->config.cayman.max_gprs = 256;
 621                 rdev->config.cayman.max_threads = 256;
 622                 rdev->config.cayman.max_gs_threads = 32;
 623                 rdev->config.cayman.max_stack_entries = 512;
 624                 rdev->config.cayman.sx_num_of_sets = 8;
 625                 rdev->config.cayman.sx_max_export_size = 256;
 626                 rdev->config.cayman.sx_max_export_pos_size = 64;
 627                 rdev->config.cayman.sx_max_export_smx_size = 192;
 628                 rdev->config.cayman.max_hw_contexts = 8;
 629                 rdev->config.cayman.sq_num_cf_insts = 2;
 630
 631                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 632                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 633                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 634                 break;
 635         }
 636
 637         /* Initialize HDP */
 638         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 639                 WREG32((0x2c14 + j), 0x00000000);
 640                 WREG32((0x2c18 + j), 0x00000000);
 641                 WREG32((0x2c1c + j), 0x00000000);
 642                 WREG32((0x2c20 + j), 0x00000000);
 643                 WREG32((0x2c24 + j), 0x00000000);
 644         }
 645
 646         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 647
 648         evergreen_fix_pci_max_read_req_size(rdev);
 649
 650         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 651         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 652
 653         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
 654         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
 655         cgts_tcc_disable = 0xff000000;
 656         gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
 657         gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
 658         cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
 659
 660         rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
 661         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
 662         rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
 663         rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 664         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
 665         rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
 666         tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 667         rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
 668         tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 669         rdev->config.cayman.backend_disable_mask_per_asic =
 670                 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
 671                                                  rdev->config.cayman.num_shader_engines);
 672         rdev->config.cayman.backend_map =
 673                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 674                                                     rdev->config.cayman.num_backends_per_se *
 675                                                     rdev->config.cayman.num_shader_engines,
 676                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 677                                                     rdev->config.cayman.num_shader_engines);
 678         tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
 679         rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
 680         tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
 681         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 682         if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
 683                 rdev->config.cayman.mem_max_burst_length_bytes = 512;
 684         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 685         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 686         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 687                 rdev->config.cayman.mem_row_size_in_kb = 4;
 688         /* XXX use MC settings? */
 689         rdev->config.cayman.shader_engine_tile_size = 32;
 690         rdev->config.cayman.num_gpus = 1;
 691         rdev->config.cayman.multi_gpu_tile_size = 64;
 692
 693         //gb_addr_config = 0x02011003
 694 #if 0
 695         gb_addr_config = RREG32(GB_ADDR_CONFIG);
 696 #else
 697         gb_addr_config = 0;
 698         switch (rdev->config.cayman.num_tile_pipes) {
 699         case 1:
 700         default:
 701                 gb_addr_config |= NUM_PIPES(0);
 702                 break;
 703         case 2:
 704                 gb_addr_config |= NUM_PIPES(1);
 705                 break;
 706         case 4:
 707                 gb_addr_config |= NUM_PIPES(2);
 708                 break;
 709         case 8:
 710                 gb_addr_config |= NUM_PIPES(3);
 711                 break;
 712         }
 713
 714         tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
 715         gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
 716         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
 717         tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
 718         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
 719         switch (rdev->config.cayman.num_gpus) {
 720         case 1:
 721         default:
 722                 gb_addr_config |= NUM_GPUS(0);
 723                 break;
 724         case 2:
 725                 gb_addr_config |= NUM_GPUS(1);
 726                 break;
 727         case 4:
 728                 gb_addr_config |= NUM_GPUS(2);
 729                 break;
 730         }
 731         switch (rdev->config.cayman.multi_gpu_tile_size) {
 732         case 16:
 733                 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
 734                 break;
 735         case 32:
 736         default:
 737                 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
 738                 break;
 739         case 64:
 740                 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
 741                 break;
 742         case 128:
 743                 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
 744                 break;
 745         }
 746         switch (rdev->config.cayman.mem_row_size_in_kb) {
 747         case 1:
 748         default:
 749                 gb_addr_config |= ROW_SIZE(0);
 750                 break;
 751         case 2:
 752                 gb_addr_config |= ROW_SIZE(1);
 753                 break;
 754         case 4:
 755                 gb_addr_config |= ROW_SIZE(2);
 756                 break;
 757         }
 758 #endif
 759
 760         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 761         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 762         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 763         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 764         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 765         rdev->config.cayman.num_shader_engines = tmp + 1;
 766         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 767         rdev->config.cayman.num_gpus = tmp + 1;
 768         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 769         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 770         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 771         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 772
 773         //gb_backend_map = 0x76541032;
 774 #if 0
 775         gb_backend_map = RREG32(GB_BACKEND_MAP);
 776 #else
 777         gb_backend_map =
 778                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 779                                                     rdev->config.cayman.num_backends_per_se *
 780                                                     rdev->config.cayman.num_shader_engines,
 781                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 782                                                     rdev->config.cayman.num_shader_engines);
 783 #endif
 784         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 785          * not have bank info, so create a custom tiling dword.
 786          * bits 3:0   num_pipes
 787          * bits 7:4   num_banks
 788          * bits 11:8  group_size
 789          * bits 15:12 row_size
 790          */
 791         rdev->config.cayman.tile_config = 0;
 792         switch (rdev->config.cayman.num_tile_pipes) {
 793         case 1:
 794         default:
 795                 rdev->config.cayman.tile_config |= (0 << 0);
 796                 break;
 797         case 2:
 798                 rdev->config.cayman.tile_config |= (1 << 0);
 799                 break;
 800         case 4:
 801                 rdev->config.cayman.tile_config |= (2 << 0);
 802                 break;
 803         case 8:
 804                 rdev->config.cayman.tile_config |= (3 << 0);
 805                 break;
 806         }
 807         rdev->config.cayman.tile_config |=
 808                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
 809         rdev->config.cayman.tile_config |=
 810                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 811         rdev->config.cayman.tile_config |=
 812                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 813
 814         rdev->config.cayman.backend_map = gb_backend_map;
 815         WREG32(GB_BACKEND_MAP, gb_backend_map);
 816         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 817         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 818         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 819
 820         /* primary versions */
 821         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 822         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 823         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 824
 825         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 826         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 827
 828         /* user versions */
 829         WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 830         WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 831         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 832
 833         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 834         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 835
 836         /* reprogram the shader complex */
 837         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 838         for (i = 0; i < 16; i++)
 839                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 840         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 841
 842         /* set HW defaults for 3D engine */
 843         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 844
 845         sx_debug_1 = RREG32(SX_DEBUG_1);
 846         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 847         WREG32(SX_DEBUG_1, sx_debug_1);
 848
 849         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 850         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 851         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 852         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 853
 854         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 855
 856         /* need to be explicitly zero-ed */
 857         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 858         WREG32(SQ_LSTMP_RING_BASE, 0);
 859         WREG32(SQ_HSTMP_RING_BASE, 0);
 860         WREG32(SQ_ESTMP_RING_BASE, 0);
 861         WREG32(SQ_GSTMP_RING_BASE, 0);
 862         WREG32(SQ_VSTMP_RING_BASE, 0);
 863         WREG32(SQ_PSTMP_RING_BASE, 0);
 864
 865         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 866
 867         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 868                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 869                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 870
 871         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 872                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 873                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 874
 875
 876         WREG32(VGT_NUM_INSTANCES, 1);
 877
 878         WREG32(CP_PERFMON_CNTL, 0);
 879
 880         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 881                                   FETCH_FIFO_HIWATER(0x4) |
 882                                   DONE_FIFO_HIWATER(0xe0) |
 883                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 884
 885         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 886         WREG32(SQ_CONFIG, (VC_ENABLE |
 887                            EXPORT_SRC_C |
 888                            GFX_PRIO(0) |
 889                            CS1_PRIO(0) |
 890                            CS2_PRIO(1)));
 891         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 892
 893         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 894                                           FORCE_EOV_MAX_REZ_CNT(255)));
 895
 896         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 897                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 898
 899         WREG32(VGT_GS_VERTEX_REUSE, 16);
 900         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 901
 902         WREG32(CB_PERF_CTR0_SEL_0, 0);
 903         WREG32(CB_PERF_CTR0_SEL_1, 0);
 904         WREG32(CB_PERF_CTR1_SEL_0, 0);
 905         WREG32(CB_PERF_CTR1_SEL_1, 0);
 906         WREG32(CB_PERF_CTR2_SEL_0, 0);
 907         WREG32(CB_PERF_CTR2_SEL_1, 0);
 908         WREG32(CB_PERF_CTR3_SEL_0, 0);
 909         WREG32(CB_PERF_CTR3_SEL_1, 0);
 910
 911         tmp = RREG32(HDP_MISC_CNTL);
 912         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
 913         WREG32(HDP_MISC_CNTL, tmp);
 914
 915         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 916         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 917
 918         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 919
 920         udelay(50);
 921 }
 922
 923 /*
 924  * GART
 925  */
 926 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
 927 {
 928         /* flush hdp cache */
 929         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 930
 931         /* bits 0-7 are the VM contexts0-7 */
 932         WREG32(VM_INVALIDATE_REQUEST, 1);
 933 }
 934
 935 int cayman_pcie_gart_enable(struct radeon_device *rdev)
 936 {
 937         int i, r;
 938
 939         if (rdev->gart.robj == NULL) {
 940                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 941                 return -EINVAL;
 942         }
 943         r = radeon_gart_table_vram_pin(rdev);
 944         if (r)
 945                 return r;
 946         radeon_gart_restore(rdev);
 947         /* Setup TLB control */
 948         WREG32(MC_VM_MX_L1_TLB_CNTL,
 949                (0xA << 7) |
 950                ENABLE_L1_TLB |
 951                ENABLE_L1_FRAGMENT_PROCESSING |
 952                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 953                ENABLE_ADVANCED_DRIVER_MODEL |
 954                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 955         /* Setup L2 cache */
 956         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
 957                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 958                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
 959                EFFECTIVE_L2_QUEUE_SIZE(7) |
 960                CONTEXT1_IDENTITY_ACCESS_MODE(1));
 961         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
 962         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
 963                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
 964         /* setup context0 */
 965         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 966         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 967         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 968         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 969                         (u32)(rdev->dummy_page.addr >> 12));
 970         WREG32(VM_CONTEXT0_CNTL2, 0);
 971         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 972                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 973
 974         WREG32(0x15D4, 0);
 975         WREG32(0x15D8, 0);
 976         WREG32(0x15DC, 0);
 977
 978         /* empty context1-7 */
 979         for (i = 1; i < 8; i++) {
 980                 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
 981                 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
 982                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
 983                         rdev->gart.table_addr >> 12);
 984         }
 985
 986         /* enable context1-7 */
 987         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 988                (u32)(rdev->dummy_page.addr >> 12));
 989         WREG32(VM_CONTEXT1_CNTL2, 0);
 990         WREG32(VM_CONTEXT1_CNTL, 0);
 991         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 992                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 993
 994         cayman_pcie_gart_tlb_flush(rdev);
 995         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 996                  (unsigned)(rdev->mc.gtt_size >> 20),
 997                  (unsigned long long)rdev->gart.table_addr);
 998         rdev->gart.ready = true;
 999         return 0;
1000 }
1001
1002 void cayman_pcie_gart_disable(struct radeon_device *rdev)
1003 {
1004         /* Disable all tables */
1005         WREG32(VM_CONTEXT0_CNTL, 0);
1006         WREG32(VM_CONTEXT1_CNTL, 0);
1007         /* Setup TLB control */
1008         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1009                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1010                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1011         /* Setup L2 cache */
1012         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1013                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1014                EFFECTIVE_L2_QUEUE_SIZE(7) |
1015                CONTEXT1_IDENTITY_ACCESS_MODE(1));
1016         WREG32(VM_L2_CNTL2, 0);
1017         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1018                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1019         radeon_gart_table_vram_unpin(rdev);
1020 }
1021
1022 void cayman_pcie_gart_fini(struct radeon_device *rdev)
1023 {
1024         cayman_pcie_gart_disable(rdev);
1025         radeon_gart_table_vram_free(rdev);
1026         radeon_gart_fini(rdev);
1027 }
1028
1029 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1030                               int ring, u32 cp_int_cntl)
1031 {
1032         u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1033
1034         WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1035         WREG32(CP_INT_CNTL, cp_int_cntl);
1036 }
1037
1038 /*
1039  * CP.
1040  */
1041 void cayman_fence_ring_emit(struct radeon_device *rdev,
1042                             struct radeon_fence *fence)
1043 {
1044         struct radeon_ring *ring = &rdev->ring[fence->ring];
1045         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1046
1047         /* flush read cache over gart for this vmid */
1048         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1049         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1050         radeon_ring_write(ring, 0);
1051         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1052         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1053         radeon_ring_write(ring, 0xFFFFFFFF);
1054         radeon_ring_write(ring, 0);
1055         radeon_ring_write(ring, 10); /* poll interval */
1056         /* EVENT_WRITE_EOP - flush caches, send int */
1057         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1058         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1059         radeon_ring_write(ring, addr & 0xffffffff);
1060         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1061         radeon_ring_write(ring, fence->seq);
1062         radeon_ring_write(ring, 0);
1063 }
1064
1065 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1066 {
1067         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1068
1069         /* set to DX10/11 mode */
1070         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1071         radeon_ring_write(ring, 1);
1072         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1073         radeon_ring_write(ring,
1074 #ifdef __BIG_ENDIAN
1075                           (2 << 0) |
1076 #endif
1077                           (ib->gpu_addr & 0xFFFFFFFC));
1078         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1079         radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1080
1081         /* flush read cache over gart for this vmid */
1082         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1083         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1084         radeon_ring_write(ring, ib->vm_id);
1085         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1086         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1087         radeon_ring_write(ring, 0xFFFFFFFF);
1088         radeon_ring_write(ring, 0);
1089         radeon_ring_write(ring, 10); /* poll interval */
1090 }
1091
1092 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1093 {
1094         if (enable)
1095                 WREG32(CP_ME_CNTL, 0);
1096         else {
1097                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1098                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1099                 WREG32(SCRATCH_UMSK, 0);
1100         }
1101 }
1102
1103 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1104 {
1105         const __be32 *fw_data;
1106         int i;
1107
1108         if (!rdev->me_fw || !rdev->pfp_fw)
1109                 return -EINVAL;
1110
1111         cayman_cp_enable(rdev, false);
1112
1113         fw_data = (const __be32 *)rdev->pfp_fw->data;
1114         WREG32(CP_PFP_UCODE_ADDR, 0);
1115         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1116                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1117         WREG32(CP_PFP_UCODE_ADDR, 0);
1118
1119         fw_data = (const __be32 *)rdev->me_fw->data;
1120         WREG32(CP_ME_RAM_WADDR, 0);
1121         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1122                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1123
1124         WREG32(CP_PFP_UCODE_ADDR, 0);
1125         WREG32(CP_ME_RAM_WADDR, 0);
1126         WREG32(CP_ME_RAM_RADDR, 0);
1127         return 0;
1128 }
1129
1130 static int cayman_cp_start(struct radeon_device *rdev)
1131 {
1132         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1133         int r, i;
1134
1135         r = radeon_ring_lock(rdev, ring, 7);
1136         if (r) {
1137                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1138                 return r;
1139         }
1140         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1141         radeon_ring_write(ring, 0x1);
1142         radeon_ring_write(ring, 0x0);
1143         radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1144         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1145         radeon_ring_write(ring, 0);
1146         radeon_ring_write(ring, 0);
1147         radeon_ring_unlock_commit(rdev, ring);
1148
1149         cayman_cp_enable(rdev, true);
1150
1151         r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1152         if (r) {
1153                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1154                 return r;
1155         }
1156
1157         /* setup clear context state */
1158         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1159         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1160
1161         for (i = 0; i < cayman_default_size; i++)
1162                 radeon_ring_write(ring, cayman_default_state[i]);
1163
1164         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1165         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1166
1167         /* set clear context state */
1168         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1169         radeon_ring_write(ring, 0);
1170
1171         /* SQ_VTX_BASE_VTX_LOC */
1172         radeon_ring_write(ring, 0xc0026f00);
1173         radeon_ring_write(ring, 0x00000000);
1174         radeon_ring_write(ring, 0x00000000);
1175         radeon_ring_write(ring, 0x00000000);
1176
1177         /* Clear consts */
1178         radeon_ring_write(ring, 0xc0036f00);
1179         radeon_ring_write(ring, 0x00000bc4);
1180         radeon_ring_write(ring, 0xffffffff);
1181         radeon_ring_write(ring, 0xffffffff);
1182         radeon_ring_write(ring, 0xffffffff);
1183
1184         radeon_ring_write(ring, 0xc0026900);
1185         radeon_ring_write(ring, 0x00000316);
1186         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1187         radeon_ring_write(ring, 0x00000010); /*  */
1188
1189         radeon_ring_unlock_commit(rdev, ring);
1190
1191         /* XXX init other rings */
1192
1193         return 0;
1194 }
1195
1196 static void cayman_cp_fini(struct radeon_device *rdev)
1197 {
1198         cayman_cp_enable(rdev, false);
1199         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1200 }
1201
1202 int cayman_cp_resume(struct radeon_device *rdev)
1203 {
1204         struct radeon_ring *ring;
1205         u32 tmp;
1206         u32 rb_bufsz;
1207         int r;
1208
1209         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1210         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1211                                  SOFT_RESET_PA |
1212                                  SOFT_RESET_SH |
1213                                  SOFT_RESET_VGT |
1214                                  SOFT_RESET_SPI |
1215                                  SOFT_RESET_SX));
1216         RREG32(GRBM_SOFT_RESET);
1217         mdelay(15);
1218         WREG32(GRBM_SOFT_RESET, 0);
1219         RREG32(GRBM_SOFT_RESET);
1220
1221         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1222
1223         /* Set the write pointer delay */
1224         WREG32(CP_RB_WPTR_DELAY, 0);
1225
1226         WREG32(CP_DEBUG, (1 << 27));
1227
1228         /* ring 0 - compute and gfx */
1229         /* Set ring buffer size */
1230         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1231         rb_bufsz = drm_order(ring->ring_size / 8);
1232         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1233 #ifdef __BIG_ENDIAN
1234         tmp |= BUF_SWAP_32BIT;
1235 #endif
1236         WREG32(CP_RB0_CNTL, tmp);
1237
1238         /* Initialize the ring buffer's read and write pointers */
1239         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1240         ring->wptr = 0;
1241         WREG32(CP_RB0_WPTR, ring->wptr);
1242
1243         /* set the wb address wether it's enabled or not */
1244         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1245         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1246         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1247
1248         if (rdev->wb.enabled)
1249                 WREG32(SCRATCH_UMSK, 0xff);
1250         else {
1251                 tmp |= RB_NO_UPDATE;
1252                 WREG32(SCRATCH_UMSK, 0);
1253         }
1254
1255         mdelay(1);
1256         WREG32(CP_RB0_CNTL, tmp);
1257
1258         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1259
1260         ring->rptr = RREG32(CP_RB0_RPTR);
1261
1262         /* ring1  - compute only */
1263         /* Set ring buffer size */
1264         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1265         rb_bufsz = drm_order(ring->ring_size / 8);
1266         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1267 #ifdef __BIG_ENDIAN
1268         tmp |= BUF_SWAP_32BIT;
1269 #endif
1270         WREG32(CP_RB1_CNTL, tmp);
1271
1272         /* Initialize the ring buffer's read and write pointers */
1273         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1274         ring->wptr = 0;
1275         WREG32(CP_RB1_WPTR, ring->wptr);
1276
1277         /* set the wb address wether it's enabled or not */
1278         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1279         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1280
1281         mdelay(1);
1282         WREG32(CP_RB1_CNTL, tmp);
1283
1284         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1285
1286         ring->rptr = RREG32(CP_RB1_RPTR);
1287
1288         /* ring2 - compute only */
1289         /* Set ring buffer size */
1290         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1291         rb_bufsz = drm_order(ring->ring_size / 8);
1292         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1293 #ifdef __BIG_ENDIAN
1294         tmp |= BUF_SWAP_32BIT;
1295 #endif
1296         WREG32(CP_RB2_CNTL, tmp);
1297
1298         /* Initialize the ring buffer's read and write pointers */
1299         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1300         ring->wptr = 0;
1301         WREG32(CP_RB2_WPTR, ring->wptr);
1302
1303         /* set the wb address wether it's enabled or not */
1304         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1305         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1306
1307         mdelay(1);
1308         WREG32(CP_RB2_CNTL, tmp);
1309
1310         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1311
1312         ring->rptr = RREG32(CP_RB2_RPTR);
1313
1314         /* start the rings */
1315         cayman_cp_start(rdev);
1316         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1317         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1318         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1319         /* this only test cp0 */
1320         r = radeon_ring_test(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1321         if (r) {
1322                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1323                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1324                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1325                 return r;
1326         }
1327
1328         return 0;
1329 }
1330
1331 bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1332 {
1333         u32 srbm_status;
1334         u32 grbm_status;
1335         u32 grbm_status_se0, grbm_status_se1;
1336         struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1337         int r;
1338
1339         srbm_status = RREG32(SRBM_STATUS);
1340         grbm_status = RREG32(GRBM_STATUS);
1341         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1342         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1343         if (!(grbm_status & GUI_ACTIVE)) {
1344                 r100_gpu_lockup_update(lockup, ring);
1345                 return false;
1346         }
1347         /* force CP activities */
1348         r = radeon_ring_lock(rdev, ring, 2);
1349         if (!r) {
1350                 /* PACKET2 NOP */
1351                 radeon_ring_write(ring, 0x80000000);
1352                 radeon_ring_write(ring, 0x80000000);
1353                 radeon_ring_unlock_commit(rdev, ring);
1354         }
1355         /* XXX deal with CP0,1,2 */
1356         ring->rptr = RREG32(ring->rptr_reg);
1357         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
1358 }
1359
1360 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1361 {
1362         struct evergreen_mc_save save;
1363         u32 grbm_reset = 0;
1364
1365         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1366                 return 0;
1367
1368         dev_info(rdev->dev, "GPU softreset \n");
1369         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1370                 RREG32(GRBM_STATUS));
1371         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1372                 RREG32(GRBM_STATUS_SE0));
1373         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1374                 RREG32(GRBM_STATUS_SE1));
1375         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1376                 RREG32(SRBM_STATUS));
1377         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
1378                  RREG32(0x14F8));
1379         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1380                  RREG32(0x14D8));
1381         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1382                  RREG32(0x14FC));
1383         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1384                  RREG32(0x14DC));
1385
1386         evergreen_mc_stop(rdev, &save);
1387         if (evergreen_mc_wait_for_idle(rdev)) {
1388                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1389         }
1390         /* Disable CP parsing/prefetching */
1391         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1392
1393         /* reset all the gfx blocks */
1394         grbm_reset = (SOFT_RESET_CP |
1395                       SOFT_RESET_CB |
1396                       SOFT_RESET_DB |
1397                       SOFT_RESET_GDS |
1398                       SOFT_RESET_PA |
1399                       SOFT_RESET_SC |
1400                       SOFT_RESET_SPI |
1401                       SOFT_RESET_SH |
1402                       SOFT_RESET_SX |
1403                       SOFT_RESET_TC |
1404                       SOFT_RESET_TA |
1405                       SOFT_RESET_VGT |
1406                       SOFT_RESET_IA);
1407
1408         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1409         WREG32(GRBM_SOFT_RESET, grbm_reset);
1410         (void)RREG32(GRBM_SOFT_RESET);
1411         udelay(50);
1412         WREG32(GRBM_SOFT_RESET, 0);
1413         (void)RREG32(GRBM_SOFT_RESET);
1414         /* Wait a little for things to settle down */
1415         udelay(50);
1416
1417         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1418                 RREG32(GRBM_STATUS));
1419         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1420                 RREG32(GRBM_STATUS_SE0));
1421         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1422                 RREG32(GRBM_STATUS_SE1));
1423         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1424                 RREG32(SRBM_STATUS));
1425         evergreen_mc_resume(rdev, &save);
1426         return 0;
1427 }
1428
1429 int cayman_asic_reset(struct radeon_device *rdev)
1430 {
1431         return cayman_gpu_soft_reset(rdev);
1432 }
1433
1434 static int cayman_startup(struct radeon_device *rdev)
1435 {
1436         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1437         int r;
1438
1439         /* enable pcie gen2 link */
1440         evergreen_pcie_gen2_enable(rdev);
1441
1442         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1443                 r = ni_init_microcode(rdev);
1444                 if (r) {
1445                         DRM_ERROR("Failed to load firmware!\n");
1446                         return r;
1447                 }
1448         }
1449         r = ni_mc_load_microcode(rdev);
1450         if (r) {
1451                 DRM_ERROR("Failed to load MC firmware!\n");
1452                 return r;
1453         }
1454
1455         r = r600_vram_scratch_init(rdev);
1456         if (r)
1457                 return r;
1458
1459         evergreen_mc_program(rdev);
1460         r = cayman_pcie_gart_enable(rdev);
1461         if (r)
1462                 return r;
1463         cayman_gpu_init(rdev);
1464
1465         r = evergreen_blit_init(rdev);
1466         if (r) {
1467                 r600_blit_fini(rdev);
1468                 rdev->asic->copy = NULL;
1469                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1470         }
1471
1472         /* allocate wb buffer */
1473         r = radeon_wb_init(rdev);
1474         if (r)
1475                 return r;
1476
1477         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1478         if (r) {
1479                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1480                 return r;
1481         }
1482
1483         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1484         if (r) {
1485                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1486                 return r;
1487         }
1488
1489         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1490         if (r) {
1491                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1492                 return r;
1493         }
1494
1495         /* Enable IRQ */
1496         r = r600_irq_init(rdev);
1497         if (r) {
1498                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1499                 radeon_irq_kms_fini(rdev);
1500                 return r;
1501         }
1502         evergreen_irq_set(rdev);
1503
1504         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1505                              CP_RB0_RPTR, CP_RB0_WPTR,
1506                              0, 0xfffff, RADEON_CP_PACKET2);
1507         if (r)
1508                 return r;
1509         r = cayman_cp_load_microcode(rdev);
1510         if (r)
1511                 return r;
1512         r = cayman_cp_resume(rdev);
1513         if (r)
1514                 return r;
1515
1516         r = radeon_ib_pool_start(rdev);
1517         if (r)
1518                 return r;
1519
1520         r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1521         if (r) {
1522                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1523                 rdev->accel_working = false;
1524                 return r;
1525         }
1526
1527         r = radeon_vm_manager_start(rdev);
1528         if (r)
1529                 return r;
1530
1531         return 0;
1532 }
1533
1534 int cayman_resume(struct radeon_device *rdev)
1535 {
1536         int r;
1537
1538         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1539          * posting will perform necessary task to bring back GPU into good
1540          * shape.
1541          */
1542         /* post card */
1543         atom_asic_init(rdev->mode_info.atom_context);
1544
1545         rdev->accel_working = true;
1546         r = cayman_startup(rdev);
1547         if (r) {
1548                 DRM_ERROR("cayman startup failed on resume\n");
1549                 return r;
1550         }
1551         return r;
1552 }
1553
1554 int cayman_suspend(struct radeon_device *rdev)
1555 {
1556         /* FIXME: we should wait for ring to be empty */
1557         radeon_ib_pool_suspend(rdev);
1558         radeon_vm_manager_suspend(rdev);
1559         r600_blit_suspend(rdev);
1560         cayman_cp_enable(rdev, false);
1561         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1562         evergreen_irq_suspend(rdev);
1563         radeon_wb_disable(rdev);
1564         cayman_pcie_gart_disable(rdev);
1565         return 0;
1566 }
1567
1568 /* Plan is to move initialization in that function and use
1569  * helper function so that radeon_device_init pretty much
1570  * do nothing more than calling asic specific function. This
1571  * should also allow to remove a bunch of callback function
1572  * like vram_info.
1573  */
1574 int cayman_init(struct radeon_device *rdev)
1575 {
1576         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1577         int r;
1578
1579         /* This don't do much */
1580         r = radeon_gem_init(rdev);
1581         if (r)
1582                 return r;
1583         /* Read BIOS */
1584         if (!radeon_get_bios(rdev)) {
1585                 if (ASIC_IS_AVIVO(rdev))
1586                         return -EINVAL;
1587         }
1588         /* Must be an ATOMBIOS */
1589         if (!rdev->is_atom_bios) {
1590                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1591                 return -EINVAL;
1592         }
1593         r = radeon_atombios_init(rdev);
1594         if (r)
1595                 return r;
1596
1597         /* Post card if necessary */
1598         if (!radeon_card_posted(rdev)) {
1599                 if (!rdev->bios) {
1600                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1601                         return -EINVAL;
1602                 }
1603                 DRM_INFO("GPU not posted. posting now...\n");
1604                 atom_asic_init(rdev->mode_info.atom_context);
1605         }
1606         /* Initialize scratch registers */
1607         r600_scratch_init(rdev);
1608         /* Initialize surface registers */
1609         radeon_surface_init(rdev);
1610         /* Initialize clocks */
1611         radeon_get_clock_info(rdev->ddev);
1612         /* Fence driver */
1613         r = radeon_fence_driver_init(rdev);
1614         if (r)
1615                 return r;
1616         /* initialize memory controller */
1617         r = evergreen_mc_init(rdev);
1618         if (r)
1619                 return r;
1620         /* Memory manager */
1621         r = radeon_bo_init(rdev);
1622         if (r)
1623                 return r;
1624
1625         r = radeon_irq_kms_init(rdev);
1626         if (r)
1627                 return r;
1628
1629         ring->ring_obj = NULL;
1630         r600_ring_init(rdev, ring, 1024 * 1024);
1631
1632         rdev->ih.ring_obj = NULL;
1633         r600_ih_ring_init(rdev, 64 * 1024);
1634
1635         r = r600_pcie_gart_init(rdev);
1636         if (r)
1637                 return r;
1638
1639         r = radeon_ib_pool_init(rdev);
1640         rdev->accel_working = true;
1641         if (r) {
1642                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1643                 rdev->accel_working = false;
1644         }
1645         r = radeon_vm_manager_init(rdev);
1646         if (r) {
1647                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1648         }
1649
1650         r = cayman_startup(rdev);
1651         if (r) {
1652                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1653                 cayman_cp_fini(rdev);
1654                 r600_irq_fini(rdev);
1655                 radeon_wb_fini(rdev);
1656                 r100_ib_fini(rdev);
1657                 radeon_vm_manager_fini(rdev);
1658                 radeon_irq_kms_fini(rdev);
1659                 cayman_pcie_gart_fini(rdev);
1660                 rdev->accel_working = false;
1661         }
1662
1663         /* Don't start up if the MC ucode is missing.
1664          * The default clocks and voltages before the MC ucode
1665          * is loaded are not suffient for advanced operations.
1666          */
1667         if (!rdev->mc_fw) {
1668                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1669                 return -EINVAL;
1670         }
1671
1672         return 0;
1673 }
1674
1675 void cayman_fini(struct radeon_device *rdev)
1676 {
1677         r600_blit_fini(rdev);
1678         cayman_cp_fini(rdev);
1679         r600_irq_fini(rdev);
1680         radeon_wb_fini(rdev);
1681         radeon_vm_manager_fini(rdev);
1682         r100_ib_fini(rdev);
1683         radeon_irq_kms_fini(rdev);
1684         cayman_pcie_gart_fini(rdev);
1685         r600_vram_scratch_fini(rdev);
1686         radeon_gem_fini(rdev);
1687         radeon_semaphore_driver_fini(rdev);
1688         radeon_fence_driver_fini(rdev);
1689         radeon_bo_fini(rdev);
1690         radeon_atombios_fini(rdev);
1691         kfree(rdev->bios);
1692         rdev->bios = NULL;
1693 }
1694
1695 /*
1696  * vm
1697  */
1698 int cayman_vm_init(struct radeon_device *rdev)
1699 {
1700         /* number of VMs */
1701         rdev->vm_manager.nvm = 8;
1702         /* base offset of vram pages */
1703         rdev->vm_manager.vram_base_offset = 0;
1704         return 0;
1705 }
1706
1707 void cayman_vm_fini(struct radeon_device *rdev)
1708 {
1709 }
1710
1711 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1712 {
1713         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1714         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1715         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1716         /* flush hdp cache */
1717         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1718         /* bits 0-7 are the VM contexts0-7 */
1719         WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1720         return 0;
1721 }
1722
1723 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1724 {
1725         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
1726         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
1727         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1728         /* flush hdp cache */
1729         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1730         /* bits 0-7 are the VM contexts0-7 */
1731         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1732 }
1733
1734 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1735 {
1736         if (vm->id == -1)
1737                 return;
1738
1739         /* flush hdp cache */
1740         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1741         /* bits 0-7 are the VM contexts0-7 */
1742         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1743 }
1744
1745 #define R600_PTE_VALID     (1 << 0)
1746 #define R600_PTE_SYSTEM    (1 << 1)
1747 #define R600_PTE_SNOOPED   (1 << 2)
1748 #define R600_PTE_READABLE  (1 << 5)
1749 #define R600_PTE_WRITEABLE (1 << 6)
1750
1751 uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
1752                               struct radeon_vm *vm,
1753                               uint32_t flags)
1754 {
1755         uint32_t r600_flags = 0;
1756
1757         r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
1758         r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1759         r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1760         if (flags & RADEON_VM_PAGE_SYSTEM) {
1761                 r600_flags |= R600_PTE_SYSTEM;
1762                 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1763         }
1764         return r600_flags;
1765 }
1766
1767 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1768                         unsigned pfn, uint64_t addr, uint32_t flags)
1769 {
1770         void __iomem *ptr = (void *)vm->pt;
1771
1772         addr = addr & 0xFFFFFFFFFFFFF000ULL;
1773         addr |= flags;
1774         writeq(addr, ptr + (pfn * 8));
1775 }