2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
36 int radeon_debugfs_ib_init(struct radeon_device *rdev);
37 int radeon_debugfs_ring_init(struct radeon_device *rdev);
39 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
41 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
42 u32 pg_idx, pg_offset;
46 pg_idx = (idx * 4) / PAGE_SIZE;
47 pg_offset = (idx * 4) % PAGE_SIZE;
49 if (ibc->kpage_idx[0] == pg_idx)
50 return ibc->kpage[0][pg_offset/4];
51 if (ibc->kpage_idx[1] == pg_idx)
52 return ibc->kpage[1][pg_offset/4];
54 new_page = radeon_cs_update_pages(p, pg_idx);
56 p->parser_error = new_page;
60 idx_value = ibc->kpage[new_page][pg_offset/4];
64 void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
67 if (ring->count_dw <= 0) {
68 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
71 ring->ring[ring->wptr++] = v;
72 ring->wptr &= ring->ptr_mask;
80 bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib)
84 /* only free ib which have been emited */
85 if (ib->fence && ib->fence->emitted) {
86 if (radeon_fence_signaled(ib->fence)) {
87 radeon_fence_unref(&ib->fence);
88 radeon_sa_bo_free(rdev, &ib->sa_bo);
95 int radeon_ib_get(struct radeon_device *rdev, int ring,
96 struct radeon_ib **ib, unsigned size)
98 struct radeon_fence *fence;
103 /* align size on 256 bytes */
104 size = ALIGN(size, 256);
106 r = radeon_fence_create(rdev, &fence, ring);
108 dev_err(rdev->dev, "failed to create fence for new IB\n");
112 mutex_lock(&rdev->ib_pool.mutex);
113 idx = rdev->ib_pool.head_id;
116 dev_err(rdev->dev, "failed to get an ib after 5 retry\n");
117 mutex_unlock(&rdev->ib_pool.mutex);
118 radeon_fence_unref(&fence);
122 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
123 radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]);
124 if (rdev->ib_pool.ibs[idx].fence == NULL) {
125 r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager,
126 &rdev->ib_pool.ibs[idx].sa_bo,
129 *ib = &rdev->ib_pool.ibs[idx];
130 (*ib)->ptr = rdev->ib_pool.sa_manager.cpu_ptr;
131 (*ib)->ptr += ((*ib)->sa_bo.offset >> 2);
132 (*ib)->gpu_addr = rdev->ib_pool.sa_manager.gpu_addr;
133 (*ib)->gpu_addr += (*ib)->sa_bo.offset;
134 (*ib)->fence = fence;
136 /* ib are most likely to be allocated in a ring fashion
137 * thus rdev->ib_pool.head_id should be the id of the
140 rdev->ib_pool.head_id = (1 + idx);
141 rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1);
142 mutex_unlock(&rdev->ib_pool.mutex);
146 idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
148 /* this should be rare event, ie all ib scheduled none signaled yet.
150 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
151 if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) {
152 r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false);
156 /* an error happened */
159 idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
161 mutex_unlock(&rdev->ib_pool.mutex);
162 radeon_fence_unref(&fence);
166 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
168 struct radeon_ib *tmp = *ib;
174 mutex_lock(&rdev->ib_pool.mutex);
175 if (tmp->fence && !tmp->fence->emitted) {
176 radeon_sa_bo_free(rdev, &tmp->sa_bo);
177 radeon_fence_unref(&tmp->fence);
179 mutex_unlock(&rdev->ib_pool.mutex);
182 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
184 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
187 if (!ib->length_dw || !ring->ready) {
188 /* TODO: Nothings in the ib we should report. */
189 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
193 /* 64 dwords should be enough for fence too */
194 r = radeon_ring_lock(rdev, ring, 64);
196 DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
199 radeon_ring_ib_execute(rdev, ib->fence->ring, ib);
200 radeon_fence_emit(rdev, ib->fence);
201 radeon_ring_unlock_commit(rdev, ring);
205 int radeon_ib_pool_init(struct radeon_device *rdev)
209 mutex_lock(&rdev->ib_pool.mutex);
210 if (rdev->ib_pool.ready) {
211 mutex_unlock(&rdev->ib_pool.mutex);
215 r = radeon_sa_bo_manager_init(rdev, &rdev->ib_pool.sa_manager,
216 RADEON_IB_POOL_SIZE*64*1024,
217 RADEON_GEM_DOMAIN_GTT);
219 mutex_unlock(&rdev->ib_pool.mutex);
223 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
224 rdev->ib_pool.ibs[i].fence = NULL;
225 rdev->ib_pool.ibs[i].idx = i;
226 rdev->ib_pool.ibs[i].length_dw = 0;
227 INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].sa_bo.list);
229 rdev->ib_pool.head_id = 0;
230 rdev->ib_pool.ready = true;
231 DRM_INFO("radeon: ib pool ready.\n");
233 if (radeon_debugfs_ib_init(rdev)) {
234 DRM_ERROR("Failed to register debugfs file for IB !\n");
236 if (radeon_debugfs_ring_init(rdev)) {
237 DRM_ERROR("Failed to register debugfs file for rings !\n");
239 mutex_unlock(&rdev->ib_pool.mutex);
243 void radeon_ib_pool_fini(struct radeon_device *rdev)
247 mutex_lock(&rdev->ib_pool.mutex);
248 if (rdev->ib_pool.ready) {
249 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
250 radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo);
251 radeon_fence_unref(&rdev->ib_pool.ibs[i].fence);
253 radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager);
254 rdev->ib_pool.ready = false;
256 mutex_unlock(&rdev->ib_pool.mutex);
259 int radeon_ib_pool_start(struct radeon_device *rdev)
261 return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager);
264 int radeon_ib_pool_suspend(struct radeon_device *rdev)
266 return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager);
272 int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring)
274 /* r1xx-r5xx only has CP ring */
275 if (rdev->family < CHIP_R600)
276 return RADEON_RING_TYPE_GFX_INDEX;
278 if (rdev->family >= CHIP_CAYMAN) {
279 if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX])
280 return CAYMAN_RING_TYPE_CP1_INDEX;
281 else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX])
282 return CAYMAN_RING_TYPE_CP2_INDEX;
284 return RADEON_RING_TYPE_GFX_INDEX;
287 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
291 if (rdev->wb.enabled)
292 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
294 rptr = RREG32(ring->rptr_reg);
295 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
296 /* This works because ring_size is a power of 2 */
297 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
298 ring->ring_free_dw -= ring->wptr;
299 ring->ring_free_dw &= ring->ptr_mask;
300 if (!ring->ring_free_dw) {
301 ring->ring_free_dw = ring->ring_size / 4;
306 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
310 /* Align requested size with padding so unlock_commit can
312 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
313 while (ndw > (ring->ring_free_dw - 1)) {
314 radeon_ring_free_size(rdev, ring);
315 if (ndw < ring->ring_free_dw) {
318 r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring));
322 ring->count_dw = ndw;
323 ring->wptr_old = ring->wptr;
327 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
331 mutex_lock(&ring->mutex);
332 r = radeon_ring_alloc(rdev, ring, ndw);
334 mutex_unlock(&ring->mutex);
340 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
342 unsigned count_dw_pad;
345 /* We pad to match fetch size */
346 count_dw_pad = (ring->align_mask + 1) -
347 (ring->wptr & ring->align_mask);
348 for (i = 0; i < count_dw_pad; i++) {
349 radeon_ring_write(ring, ring->nop);
352 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
353 (void)RREG32(ring->wptr_reg);
356 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
358 radeon_ring_commit(rdev, ring);
359 mutex_unlock(&ring->mutex);
362 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
364 ring->wptr = ring->wptr_old;
365 mutex_unlock(&ring->mutex);
368 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
369 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
370 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
374 ring->ring_size = ring_size;
375 ring->rptr_offs = rptr_offs;
376 ring->rptr_reg = rptr_reg;
377 ring->wptr_reg = wptr_reg;
378 ring->ptr_reg_shift = ptr_reg_shift;
379 ring->ptr_reg_mask = ptr_reg_mask;
381 /* Allocate ring buffer */
382 if (ring->ring_obj == NULL) {
383 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
384 RADEON_GEM_DOMAIN_GTT,
387 dev_err(rdev->dev, "(%d) ring create failed\n", r);
390 r = radeon_bo_reserve(ring->ring_obj, false);
391 if (unlikely(r != 0))
393 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
396 radeon_bo_unreserve(ring->ring_obj);
397 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
400 r = radeon_bo_kmap(ring->ring_obj,
401 (void **)&ring->ring);
402 radeon_bo_unreserve(ring->ring_obj);
404 dev_err(rdev->dev, "(%d) ring map failed\n", r);
408 ring->ptr_mask = (ring->ring_size / 4) - 1;
409 ring->ring_free_dw = ring->ring_size / 4;
413 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
416 struct radeon_bo *ring_obj;
418 mutex_lock(&ring->mutex);
419 ring_obj = ring->ring_obj;
421 ring->ring_obj = NULL;
422 mutex_unlock(&ring->mutex);
425 r = radeon_bo_reserve(ring_obj, false);
426 if (likely(r == 0)) {
427 radeon_bo_kunmap(ring_obj);
428 radeon_bo_unpin(ring_obj);
429 radeon_bo_unreserve(ring_obj);
431 radeon_bo_unref(&ring_obj);
438 #if defined(CONFIG_DEBUG_FS)
440 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
442 struct drm_info_node *node = (struct drm_info_node *) m->private;
443 struct drm_device *dev = node->minor->dev;
444 struct radeon_device *rdev = dev->dev_private;
445 int ridx = *(int*)node->info_ent->data;
446 struct radeon_ring *ring = &rdev->ring[ridx];
447 unsigned count, i, j;
449 radeon_ring_free_size(rdev, ring);
450 count = (ring->ring_size / 4) - ring->ring_free_dw;
451 seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
452 seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
453 seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
454 seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
455 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
456 seq_printf(m, "%u dwords in ring\n", count);
458 for (j = 0; j <= count; j++) {
459 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
460 i = (i + 1) & ring->ptr_mask;
465 static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
466 static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
467 static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
469 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
470 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
471 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
472 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
475 static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
477 struct drm_info_node *node = (struct drm_info_node *) m->private;
478 struct radeon_ib *ib = node->info_ent->data;
484 seq_printf(m, "IB %04u\n", ib->idx);
485 seq_printf(m, "IB fence %p\n", ib->fence);
486 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
487 for (i = 0; i < ib->length_dw; i++) {
488 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
493 static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
494 static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
497 int radeon_debugfs_ring_init(struct radeon_device *rdev)
499 #if defined(CONFIG_DEBUG_FS)
500 return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list,
501 ARRAY_SIZE(radeon_debugfs_ring_info_list));
507 int radeon_debugfs_ib_init(struct radeon_device *rdev)
509 #if defined(CONFIG_DEBUG_FS)
512 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
513 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
514 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
515 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
516 radeon_debugfs_ib_list[i].driver_features = 0;
517 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
519 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
520 RADEON_IB_POOL_SIZE);