2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/sched.h>
35 #include <linux/spinlock.h>
36 #include <linux/idr.h>
37 #include <linux/pci.h>
39 #include <linux/delay.h>
40 #include <linux/netdevice.h>
41 #include <linux/vmalloc.h>
42 #include <linux/bitmap.h>
43 #include <linux/slab.h>
44 #include <linux/module.h>
49 #include "ipath_kernel.h"
50 #include "ipath_verbs.h"
52 static void ipath_update_pio_bufs(struct ipath_devdata *);
54 const char *ipath_get_unit_name(int unit)
56 static char iname[16];
57 snprintf(iname, sizeof iname, "infinipath%u", unit);
61 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
62 #define PFX IPATH_DRV_NAME ": "
65 * The size has to be longer than this string, so we can append
66 * board/chip information to it in the init code.
68 const char ib_ipath_version[] = IPATH_IDSTR "\n";
70 static struct idr unit_table;
71 DEFINE_SPINLOCK(ipath_devs_lock);
72 LIST_HEAD(ipath_dev_list);
74 wait_queue_head_t ipath_state_wait;
76 unsigned ipath_debug = __IPATH_INFO;
78 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
79 MODULE_PARM_DESC(debug, "mask for debug prints");
80 EXPORT_SYMBOL_GPL(ipath_debug);
82 unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
83 module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
84 MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
86 static unsigned ipath_hol_timeout_ms = 13000;
87 module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
88 MODULE_PARM_DESC(hol_timeout_ms,
89 "duration of user app suspension after link failure");
91 unsigned ipath_linkrecovery = 1;
92 module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
93 MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
95 MODULE_LICENSE("GPL");
96 MODULE_AUTHOR("QLogic <support@qlogic.com>");
97 MODULE_DESCRIPTION("QLogic InfiniPath driver");
100 * Table to translate the LINKTRAININGSTATE portion of
101 * IBCStatus to a human-readable form.
103 const char *ipath_ibcstatus_str[] = {
110 "LState6", /* unused */
111 "LState7", /* unused */
117 "CfgTxRevLane", /* unused before IBA7220 */
120 /* below were added for IBA7220 */
124 "CfgWaitCfgEnhanced",
129 "LTState18", "LTState19", "LTState1A", "LTState1B",
130 "LTState1C", "LTState1D", "LTState1E", "LTState1F"
133 static void ipath_remove_one(struct pci_dev *);
134 static int ipath_init_one(struct pci_dev *, const struct pci_device_id *);
136 /* Only needed for registration, nothing else needs this info */
137 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
138 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
140 /* Number of seconds before our card status check... */
141 #define STATUS_TIMEOUT 60
143 static const struct pci_device_id ipath_pci_tbl[] = {
144 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
148 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
150 static struct pci_driver ipath_driver = {
151 .name = IPATH_DRV_NAME,
152 .probe = ipath_init_one,
153 .remove = ipath_remove_one,
154 .id_table = ipath_pci_tbl,
156 .groups = ipath_driver_attr_groups,
160 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
161 u32 *bar0, u32 *bar1)
165 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
167 ipath_dev_err(dd, "failed to read bar0 before enable: "
170 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
172 ipath_dev_err(dd, "failed to read bar1 before enable: "
175 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
178 static void ipath_free_devdata(struct pci_dev *pdev,
179 struct ipath_devdata *dd)
183 pci_set_drvdata(pdev, NULL);
185 if (dd->ipath_unit != -1) {
186 spin_lock_irqsave(&ipath_devs_lock, flags);
187 idr_remove(&unit_table, dd->ipath_unit);
188 list_del(&dd->ipath_list);
189 spin_unlock_irqrestore(&ipath_devs_lock, flags);
194 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
197 struct ipath_devdata *dd;
200 dd = vzalloc(sizeof(*dd));
202 dd = ERR_PTR(-ENOMEM);
207 idr_preload(GFP_KERNEL);
208 spin_lock_irqsave(&ipath_devs_lock, flags);
210 ret = idr_alloc(&unit_table, dd, 0, 0, GFP_NOWAIT);
212 printk(KERN_ERR IPATH_DRV_NAME
213 ": Could not allocate unit ID: error %d\n", -ret);
214 ipath_free_devdata(pdev, dd);
218 dd->ipath_unit = ret;
221 pci_set_drvdata(pdev, dd);
223 list_add(&dd->ipath_list, &ipath_dev_list);
226 spin_unlock_irqrestore(&ipath_devs_lock, flags);
232 static inline struct ipath_devdata *__ipath_lookup(int unit)
234 return idr_find(&unit_table, unit);
237 struct ipath_devdata *ipath_lookup(int unit)
239 struct ipath_devdata *dd;
242 spin_lock_irqsave(&ipath_devs_lock, flags);
243 dd = __ipath_lookup(unit);
244 spin_unlock_irqrestore(&ipath_devs_lock, flags);
249 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
251 int nunits, npresent, nup;
252 struct ipath_devdata *dd;
256 nunits = npresent = nup = maxports = 0;
258 spin_lock_irqsave(&ipath_devs_lock, flags);
260 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
262 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
265 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
268 if (dd->ipath_cfgports > maxports)
269 maxports = dd->ipath_cfgports;
272 spin_unlock_irqrestore(&ipath_devs_lock, flags);
275 *npresentp = npresent;
279 *maxportsp = maxports;
285 * These next two routines are placeholders in case we don't have per-arch
286 * code for controlling write combining. If explicit control of write
287 * combining is not available, performance will probably be awful.
290 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
295 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
300 * Perform a PIO buffer bandwidth write test, to verify proper system
301 * configuration. Even when all the setup calls work, occasionally
302 * BIOS or other issues can prevent write combining from working, or
303 * can cause other bandwidth problems to the chip.
305 * This test simply writes the same buffer over and over again, and
306 * measures close to the peak bandwidth to the chip (not testing
307 * data bandwidth to the wire). On chips that use an address-based
308 * trigger to send packets to the wire, this is easy. On chips that
309 * use a count to trigger, we want to make sure that the packet doesn't
310 * go out on the wire, or trigger flow control checks.
312 static void ipath_verify_pioperf(struct ipath_devdata *dd)
314 u32 pbnum, cnt, lcnt;
319 piobuf = ipath_getpiobuf(dd, 0, &pbnum);
321 dev_info(&dd->pcidev->dev,
322 "No PIObufs for checking perf, skipping\n");
327 * Enough to give us a reasonable test, less than piobuf size, and
328 * likely multiple of store buffer length.
334 dev_info(&dd->pcidev->dev,
335 "Couldn't get memory for checking PIO perf,"
340 preempt_disable(); /* we want reasonably accurate elapsed time */
341 msecs = 1 + jiffies_to_msecs(jiffies);
342 for (lcnt = 0; lcnt < 10000U; lcnt++) {
343 /* wait until we cross msec boundary */
344 if (jiffies_to_msecs(jiffies) >= msecs)
349 ipath_disable_armlaunch(dd);
352 * length 0, no dwords actually sent, and mark as VL15
353 * on chips where that may matter (due to IB flowcontrol)
355 if ((dd->ipath_flags & IPATH_HAS_PBC_CNT))
356 writeq(1UL << 63, piobuf);
362 * this is only roughly accurate, since even with preempt we
363 * still take interrupts that could take a while. Running for
364 * >= 5 msec seems to get us "close enough" to accurate values
366 msecs = jiffies_to_msecs(jiffies);
367 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
368 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
369 emsecs = jiffies_to_msecs(jiffies) - msecs;
372 /* 1 GiB/sec, slightly over IB SDR line rate */
373 if (lcnt < (emsecs * 1024U))
375 "Performance problem: bandwidth to PIO buffers is "
377 lcnt / (u32) emsecs);
379 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
380 lcnt / (u32) emsecs);
387 /* disarm piobuf, so it's available again */
388 ipath_disarm_piobufs(dd, pbnum, 1);
389 ipath_enable_armlaunch(dd);
392 static void cleanup_device(struct ipath_devdata *dd);
394 static int ipath_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
397 struct ipath_devdata *dd;
398 unsigned long long addr;
399 u32 bar0 = 0, bar1 = 0;
402 if (WARN(pat_enabled(),
403 "ipath needs PAT disabled, boot with nopat kernel parameter\n")) {
409 dd = ipath_alloc_devdata(pdev);
412 printk(KERN_ERR IPATH_DRV_NAME
413 ": Could not allocate devdata: error %d\n", -ret);
417 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
419 ret = pci_enable_device(pdev);
421 /* This can happen iff:
423 * We did a chip reset, and then failed to reprogram the
424 * BAR, or the chip reset due to an internal error. We then
425 * unloaded the driver and reloaded it.
427 * Both reset cases set the BAR back to initial state. For
428 * the latter case, the AER sticky error bit at offset 0x718
429 * should be set, but the Linux kernel doesn't yet know
430 * about that, it appears. If the original BAR was retained
431 * in the kernel data structures, this may be OK.
433 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
434 dd->ipath_unit, -ret);
437 addr = pci_resource_start(pdev, 0);
438 len = pci_resource_len(pdev, 0);
439 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %d, vend %x/%x "
440 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
441 ent->device, ent->driver_data);
443 read_bars(dd, pdev, &bar0, &bar1);
445 if (!bar1 && !(bar0 & ~0xf)) {
447 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
448 "rewriting as %llx\n", addr);
449 ret = pci_write_config_dword(
450 pdev, PCI_BASE_ADDRESS_0, addr);
452 ipath_dev_err(dd, "rewrite of BAR0 "
453 "failed: err %d\n", -ret);
456 ret = pci_write_config_dword(
457 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
459 ipath_dev_err(dd, "rewrite of BAR1 "
460 "failed: err %d\n", -ret);
464 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
465 "not usable until reboot\n");
471 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
473 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
474 "err %d\n", dd->ipath_unit, -ret);
478 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
481 * if the 64 bit setup fails, try 32 bit. Some systems
482 * do not setup 64 bit maps on systems with 2GB or less
485 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
488 "Unable to set DMA mask for unit %u: %d\n",
489 dd->ipath_unit, ret);
493 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
494 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
497 "Unable to set DMA consistent mask "
499 dd->ipath_unit, ret);
504 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
507 "Unable to set DMA consistent mask "
509 dd->ipath_unit, ret);
512 pci_set_master(pdev);
515 * Save BARs to rewrite after device reset. Save all 64 bits of
518 dd->ipath_pcibar0 = addr;
519 dd->ipath_pcibar1 = addr >> 32;
520 dd->ipath_deviceid = ent->device; /* save for later use */
521 dd->ipath_vendorid = ent->vendor;
523 /* setup the chip-specific functions, as early as possible. */
524 switch (ent->device) {
525 case PCI_DEVICE_ID_INFINIPATH_HT:
526 ipath_init_iba6110_funcs(dd);
530 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
531 "failing\n", ent->device);
535 for (j = 0; j < 6; j++) {
536 if (!pdev->resource[j].start)
538 ipath_cdbg(VERBOSE, "BAR %d %pR, len %llx\n",
539 j, &pdev->resource[j],
540 (unsigned long long)pci_resource_len(pdev, j));
544 ipath_dev_err(dd, "No valid address in BAR 0!\n");
549 dd->ipath_pcirev = pdev->revision;
551 #if defined(__powerpc__)
552 /* There isn't a generic way to specify writethrough mappings */
553 dd->ipath_kregbase = __ioremap(addr, len,
554 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
556 /* XXX: split this properly to enable on PAT */
557 dd->ipath_kregbase = ioremap_nocache(addr, len);
560 if (!dd->ipath_kregbase) {
561 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
566 dd->ipath_kregend = (u64 __iomem *)
567 ((void __iomem *)dd->ipath_kregbase + len);
568 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
570 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
571 addr, dd->ipath_kregbase);
573 if (dd->ipath_f_bus(dd, pdev))
574 ipath_dev_err(dd, "Failed to setup config space; "
575 "continuing anyway\n");
578 * set up our interrupt handler; IRQF_SHARED probably not needed,
579 * since MSI interrupts shouldn't be shared but won't hurt for now.
580 * check 0 irq after we return from chip-specific bus setup, since
581 * that can affect this due to setup
584 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
587 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
590 ipath_dev_err(dd, "Couldn't setup irq handler, "
591 "irq=%d: %d\n", dd->ipath_irq, ret);
596 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
600 ret = ipath_enable_wc(dd);
605 ipath_verify_pioperf(dd);
607 ipath_device_create_group(&pdev->dev, dd);
608 ipathfs_add_device(dd);
611 ipath_register_ib_device(dd);
619 dd->ipath_f_free_irq(dd);
621 if (dd->ipath_f_cleanup)
622 dd->ipath_f_cleanup(dd);
625 iounmap((volatile void __iomem *) dd->ipath_kregbase);
628 pci_release_regions(pdev);
631 pci_disable_device(pdev);
634 ipath_free_devdata(pdev, dd);
640 static void cleanup_device(struct ipath_devdata *dd)
643 struct ipath_portdata **tmp;
646 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
647 /* can't do anything more with chip; needs re-init */
648 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
649 if (dd->ipath_kregbase) {
651 * if we haven't already cleaned up before these are
652 * to ensure any register reads/writes "fail" until
655 dd->ipath_kregbase = NULL;
656 dd->ipath_uregbase = 0;
657 dd->ipath_sregbase = 0;
658 dd->ipath_cregbase = 0;
659 dd->ipath_kregsize = 0;
661 ipath_disable_wc(dd);
664 if (dd->ipath_spectriggerhit)
665 dev_info(&dd->pcidev->dev, "%lu special trigger hits\n",
666 dd->ipath_spectriggerhit);
668 if (dd->ipath_pioavailregs_dma) {
669 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
670 (void *) dd->ipath_pioavailregs_dma,
671 dd->ipath_pioavailregs_phys);
672 dd->ipath_pioavailregs_dma = NULL;
674 if (dd->ipath_dummy_hdrq) {
675 dma_free_coherent(&dd->pcidev->dev,
676 dd->ipath_pd[0]->port_rcvhdrq_size,
677 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
678 dd->ipath_dummy_hdrq = NULL;
681 if (dd->ipath_pageshadow) {
682 struct page **tmpp = dd->ipath_pageshadow;
683 dma_addr_t *tmpd = dd->ipath_physshadow;
686 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
688 for (port = 0; port < dd->ipath_cfgports; port++) {
689 int port_tidbase = port * dd->ipath_rcvtidcnt;
690 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
691 for (i = port_tidbase; i < maxtid; i++) {
694 pci_unmap_page(dd->pcidev, tmpd[i],
695 PAGE_SIZE, PCI_DMA_FROMDEVICE);
696 ipath_release_user_pages(&tmpp[i], 1);
702 ipath_stats.sps_pageunlocks += cnt;
703 ipath_cdbg(VERBOSE, "There were still %u expTID "
704 "entries locked\n", cnt);
706 if (ipath_stats.sps_pagelocks ||
707 ipath_stats.sps_pageunlocks)
708 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
709 "unlocked via ipath_m{un}lock\n",
711 ipath_stats.sps_pagelocks,
713 ipath_stats.sps_pageunlocks);
715 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
716 dd->ipath_pageshadow);
717 tmpp = dd->ipath_pageshadow;
718 dd->ipath_pageshadow = NULL;
721 dd->ipath_egrtidbase = NULL;
725 * free any resources still in use (usually just kernel ports)
726 * at unload; we do for portcnt, because that's what we allocate.
727 * We acquire lock to be really paranoid that ipath_pd isn't being
728 * accessed from some interrupt-related code (that should not happen,
729 * but best to be sure).
731 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
734 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
735 for (port = 0; port < dd->ipath_portcnt; port++) {
736 struct ipath_portdata *pd = tmp[port];
737 tmp[port] = NULL; /* debugging paranoia */
738 ipath_free_pddata(dd, pd);
743 static void ipath_remove_one(struct pci_dev *pdev)
745 struct ipath_devdata *dd = pci_get_drvdata(pdev);
747 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
750 * disable the IB link early, to be sure no new packets arrive, which
751 * complicates the shutdown process
753 ipath_shutdown_device(dd);
755 flush_workqueue(ib_wq);
758 ipath_unregister_ib_device(dd->verbs_dev);
760 ipath_diag_remove(dd);
761 ipath_user_remove(dd);
762 ipathfs_remove_device(dd);
763 ipath_device_remove_group(&pdev->dev, dd);
765 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
766 "unit %u\n", dd, (u32) dd->ipath_unit);
771 * turn off rcv, send, and interrupts for all ports, all drivers
772 * should also hard reset the chip here?
773 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
774 * for all versions of the driver, if they were allocated
777 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
778 dd->ipath_unit, dd->ipath_irq);
779 dd->ipath_f_free_irq(dd);
781 ipath_dbg("irq is 0, not doing free_irq "
782 "for unit %u\n", dd->ipath_unit);
784 * we check for NULL here, because it's outside
785 * the kregbase check, and we need to call it
786 * after the free_irq. Thus it's possible that
787 * the function pointers were never initialized.
789 if (dd->ipath_f_cleanup)
790 /* clean up chip-specific stuff */
791 dd->ipath_f_cleanup(dd);
793 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
794 iounmap((volatile void __iomem *) dd->ipath_kregbase);
795 pci_release_regions(pdev);
796 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
797 pci_disable_device(pdev);
799 ipath_free_devdata(pdev, dd);
802 /* general driver use */
803 DEFINE_MUTEX(ipath_mutex);
805 static DEFINE_SPINLOCK(ipath_pioavail_lock);
808 * ipath_disarm_piobufs - cancel a range of PIO buffers
809 * @dd: the infinipath device
810 * @first: the first PIO buffer to cancel
811 * @cnt: the number of PIO buffers to cancel
813 * cancel a range of PIO buffers, used when they might be armed, but
814 * not triggered. Used at init to ensure buffer state, and also user
815 * process close, in case it died while writing to a PIO buffer
818 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
821 unsigned i, last = first + cnt;
824 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
825 for (i = first; i < last; i++) {
826 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
828 * The disarm-related bits are write-only, so it
829 * is ok to OR them in with our copy of sendctrl
830 * while we hold the lock.
832 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
833 dd->ipath_sendctrl | INFINIPATH_S_DISARM |
834 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
835 /* can't disarm bufs back-to-back per iba7220 spec */
836 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
837 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
839 /* on some older chips, update may not happen after cancel */
840 ipath_force_pio_avail_update(dd);
844 * ipath_wait_linkstate - wait for an IB link state change to occur
845 * @dd: the infinipath device
846 * @state: the state to wait for
847 * @msecs: the number of milliseconds to wait
849 * wait up to msecs milliseconds for IB link state change to occur for
850 * now, take the easy polling route. Currently used only by
851 * ipath_set_linkstate. Returns 0 if state reached, otherwise
852 * -ETIMEDOUT state can have multiple states set, for any of several
855 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
857 dd->ipath_state_wanted = state;
858 wait_event_interruptible_timeout(ipath_state_wait,
859 (dd->ipath_flags & state),
860 msecs_to_jiffies(msecs));
861 dd->ipath_state_wanted = 0;
863 if (!(dd->ipath_flags & state)) {
865 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
867 /* test INIT ahead of DOWN, both can be set */
868 (state & IPATH_LINKINIT) ? "INIT" :
869 ((state & IPATH_LINKDOWN) ? "DOWN" :
870 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
872 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
873 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
874 (unsigned long long) ipath_read_kreg64(
875 dd, dd->ipath_kregs->kr_ibcctrl),
876 (unsigned long long) val,
877 ipath_ibcstatus_str[val & dd->ibcs_lts_mask]);
879 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
882 static void decode_sdma_errs(struct ipath_devdata *dd, ipath_err_t err,
883 char *buf, size_t blen)
885 static const struct {
889 { INFINIPATH_E_SDMAGENMISMATCH, "SDmaGenMismatch" },
890 { INFINIPATH_E_SDMAOUTOFBOUND, "SDmaOutOfBound" },
891 { INFINIPATH_E_SDMATAILOUTOFBOUND, "SDmaTailOutOfBound" },
892 { INFINIPATH_E_SDMABASE, "SDmaBase" },
893 { INFINIPATH_E_SDMA1STDESC, "SDma1stDesc" },
894 { INFINIPATH_E_SDMARPYTAG, "SDmaRpyTag" },
895 { INFINIPATH_E_SDMADWEN, "SDmaDwEn" },
896 { INFINIPATH_E_SDMAMISSINGDW, "SDmaMissingDw" },
897 { INFINIPATH_E_SDMAUNEXPDATA, "SDmaUnexpData" },
898 { INFINIPATH_E_SDMADESCADDRMISALIGN, "SDmaDescAddrMisalign" },
899 { INFINIPATH_E_SENDBUFMISUSE, "SendBufMisuse" },
900 { INFINIPATH_E_SDMADISABLED, "SDmaDisabled" },
906 for (i = 0; i < ARRAY_SIZE(errs); i++) {
907 expected = (errs[i].err != INFINIPATH_E_SDMADISABLED) ? 0 :
908 test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status);
909 if ((err & errs[i].err) && !expected)
910 bidx += snprintf(buf + bidx, blen - bidx,
916 * Decode the error status into strings, deciding whether to always
917 * print * it or not depending on "normal packet errors" vs everything
918 * else. Return 1 if "real" errors, otherwise 0 if only packet
919 * errors, so caller can decide what to print with the string.
921 int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen,
926 if (err & INFINIPATH_E_PKTERRS) {
927 if (!(err & ~INFINIPATH_E_PKTERRS))
928 iserr = 0; // if only packet errors.
929 if (ipath_debug & __IPATH_ERRPKTDBG) {
930 if (err & INFINIPATH_E_REBP)
931 strlcat(buf, "EBP ", blen);
932 if (err & INFINIPATH_E_RVCRC)
933 strlcat(buf, "VCRC ", blen);
934 if (err & INFINIPATH_E_RICRC) {
935 strlcat(buf, "CRC ", blen);
936 // clear for check below, so only once
937 err &= INFINIPATH_E_RICRC;
939 if (err & INFINIPATH_E_RSHORTPKTLEN)
940 strlcat(buf, "rshortpktlen ", blen);
941 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
942 strlcat(buf, "sdroppeddatapkt ", blen);
943 if (err & INFINIPATH_E_SPKTLEN)
944 strlcat(buf, "spktlen ", blen);
946 if ((err & INFINIPATH_E_RICRC) &&
947 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
948 strlcat(buf, "CRC ", blen);
952 if (err & INFINIPATH_E_RHDRLEN)
953 strlcat(buf, "rhdrlen ", blen);
954 if (err & INFINIPATH_E_RBADTID)
955 strlcat(buf, "rbadtid ", blen);
956 if (err & INFINIPATH_E_RBADVERSION)
957 strlcat(buf, "rbadversion ", blen);
958 if (err & INFINIPATH_E_RHDR)
959 strlcat(buf, "rhdr ", blen);
960 if (err & INFINIPATH_E_SENDSPECIALTRIGGER)
961 strlcat(buf, "sendspecialtrigger ", blen);
962 if (err & INFINIPATH_E_RLONGPKTLEN)
963 strlcat(buf, "rlongpktlen ", blen);
964 if (err & INFINIPATH_E_RMAXPKTLEN)
965 strlcat(buf, "rmaxpktlen ", blen);
966 if (err & INFINIPATH_E_RMINPKTLEN)
967 strlcat(buf, "rminpktlen ", blen);
968 if (err & INFINIPATH_E_SMINPKTLEN)
969 strlcat(buf, "sminpktlen ", blen);
970 if (err & INFINIPATH_E_RFORMATERR)
971 strlcat(buf, "rformaterr ", blen);
972 if (err & INFINIPATH_E_RUNSUPVL)
973 strlcat(buf, "runsupvl ", blen);
974 if (err & INFINIPATH_E_RUNEXPCHAR)
975 strlcat(buf, "runexpchar ", blen);
976 if (err & INFINIPATH_E_RIBFLOW)
977 strlcat(buf, "ribflow ", blen);
978 if (err & INFINIPATH_E_SUNDERRUN)
979 strlcat(buf, "sunderrun ", blen);
980 if (err & INFINIPATH_E_SPIOARMLAUNCH)
981 strlcat(buf, "spioarmlaunch ", blen);
982 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
983 strlcat(buf, "sunexperrpktnum ", blen);
984 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
985 strlcat(buf, "sdroppedsmppkt ", blen);
986 if (err & INFINIPATH_E_SMAXPKTLEN)
987 strlcat(buf, "smaxpktlen ", blen);
988 if (err & INFINIPATH_E_SUNSUPVL)
989 strlcat(buf, "sunsupVL ", blen);
990 if (err & INFINIPATH_E_INVALIDADDR)
991 strlcat(buf, "invalidaddr ", blen);
992 if (err & INFINIPATH_E_RRCVEGRFULL)
993 strlcat(buf, "rcvegrfull ", blen);
994 if (err & INFINIPATH_E_RRCVHDRFULL)
995 strlcat(buf, "rcvhdrfull ", blen);
996 if (err & INFINIPATH_E_IBSTATUSCHANGED)
997 strlcat(buf, "ibcstatuschg ", blen);
998 if (err & INFINIPATH_E_RIBLOSTLINK)
999 strlcat(buf, "riblostlink ", blen);
1000 if (err & INFINIPATH_E_HARDWARE)
1001 strlcat(buf, "hardware ", blen);
1002 if (err & INFINIPATH_E_RESET)
1003 strlcat(buf, "reset ", blen);
1004 if (err & INFINIPATH_E_SDMAERRS)
1005 decode_sdma_errs(dd, err, buf, blen);
1006 if (err & INFINIPATH_E_INVALIDEEPCMD)
1007 strlcat(buf, "invalideepromcmd ", blen);
1013 * get_rhf_errstring - decode RHF errors
1014 * @err: the err number
1015 * @msg: the output buffer
1016 * @len: the length of the output buffer
1018 * only used one place now, may want more later
1020 static void get_rhf_errstring(u32 err, char *msg, size_t len)
1022 /* if no errors, and so don't need to check what's first */
1025 if (err & INFINIPATH_RHF_H_ICRCERR)
1026 strlcat(msg, "icrcerr ", len);
1027 if (err & INFINIPATH_RHF_H_VCRCERR)
1028 strlcat(msg, "vcrcerr ", len);
1029 if (err & INFINIPATH_RHF_H_PARITYERR)
1030 strlcat(msg, "parityerr ", len);
1031 if (err & INFINIPATH_RHF_H_LENERR)
1032 strlcat(msg, "lenerr ", len);
1033 if (err & INFINIPATH_RHF_H_MTUERR)
1034 strlcat(msg, "mtuerr ", len);
1035 if (err & INFINIPATH_RHF_H_IHDRERR)
1036 /* infinipath hdr checksum error */
1037 strlcat(msg, "ipathhdrerr ", len);
1038 if (err & INFINIPATH_RHF_H_TIDERR)
1039 strlcat(msg, "tiderr ", len);
1040 if (err & INFINIPATH_RHF_H_MKERR)
1041 /* bad port, offset, etc. */
1042 strlcat(msg, "invalid ipathhdr ", len);
1043 if (err & INFINIPATH_RHF_H_IBERR)
1044 strlcat(msg, "iberr ", len);
1045 if (err & INFINIPATH_RHF_L_SWA)
1046 strlcat(msg, "swA ", len);
1047 if (err & INFINIPATH_RHF_L_SWB)
1048 strlcat(msg, "swB ", len);
1052 * ipath_get_egrbuf - get an eager buffer
1053 * @dd: the infinipath device
1054 * @bufnum: the eager buffer to get
1056 * must only be called if ipath_pd[port] is known to be allocated
1058 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
1060 return dd->ipath_port0_skbinfo ?
1061 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
1065 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1066 * @dd: the infinipath device
1067 * @gfp_mask: the sk_buff SFP mask
1069 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1072 struct sk_buff *skb;
1076 * Only fully supported way to handle this is to allocate lots
1077 * extra, align as needed, and then do skb_reserve(). That wastes
1078 * a lot of memory... I'll have to hack this into infinipath_copy
1083 * We need 2 extra bytes for ipath_ether data sent in the
1084 * key header. In order to keep everything dword aligned,
1085 * we'll reserve 4 bytes.
1087 len = dd->ipath_ibmaxlen + 4;
1089 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1090 /* We need a 2KB multiple alignment, and there is no way
1091 * to do it except to allocate extra and then skb_reserve
1092 * enough to bring it up to the right alignment.
1097 skb = __dev_alloc_skb(len, gfp_mask);
1099 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1104 skb_reserve(skb, 4);
1106 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1107 u32 una = (unsigned long)skb->data & 2047;
1109 skb_reserve(skb, 2048 - una);
1116 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1121 struct ipath_message_header *hdr)
1125 get_rhf_errstring(eflags, emsg, sizeof emsg);
1126 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1127 "tlen=%x opcode=%x egridx=%x: %s\n",
1129 ipath_hdrget_rcv_type(rhf_addr),
1130 ipath_hdrget_length_in_bytes(rhf_addr),
1131 be32_to_cpu(hdr->bth[0]) >> 24,
1134 /* Count local link integrity errors. */
1135 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1136 u8 n = (dd->ipath_ibcctrl >>
1137 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1138 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1140 if (++dd->ipath_lli_counter > n) {
1141 dd->ipath_lli_counter = 0;
1142 dd->ipath_lli_errors++;
1148 * ipath_kreceive - receive a packet
1149 * @pd: the infinipath port
1151 * called from interrupt handler for errors or receive interrupt
1153 void ipath_kreceive(struct ipath_portdata *pd)
1155 struct ipath_devdata *dd = pd->port_dd;
1158 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1159 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1160 u32 etail = -1, l, hdrqtail;
1161 struct ipath_message_header *hdr;
1162 u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
1163 static u64 totcalls; /* stats, may eventually remove */
1167 rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1168 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1169 u32 seq = ipath_hdrget_seq(rhf_addr);
1171 if (seq != pd->port_seq_cnt)
1175 hdrqtail = ipath_get_rcvhdrtail(pd);
1182 for (last = 0, i = 1; !last; i += !last) {
1183 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1184 eflags = ipath_hdrget_err_flags(rhf_addr);
1185 etype = ipath_hdrget_rcv_type(rhf_addr);
1187 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
1189 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1190 ipath_hdrget_use_egr_buf(rhf_addr) :
1191 (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
1193 * It turns out that the chip uses an eager buffer
1194 * for all non-expected packets, whether it "needs"
1195 * one or not. So always get the index, but don't
1196 * set ebuf (so we try to copy data) unless the
1197 * length requires it.
1199 etail = ipath_hdrget_index(rhf_addr);
1201 if (tlen > sizeof(*hdr) ||
1202 etype == RCVHQ_RCV_TYPE_NON_KD)
1203 ebuf = ipath_get_egrbuf(dd, etail);
1207 * both tiderr and ipathhdrerr are set for all plain IB
1208 * packets; only ipathhdrerr should be set.
1211 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1212 etype != RCVHQ_RCV_TYPE_ERROR &&
1213 ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1215 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1218 if (unlikely(eflags))
1219 ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
1220 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1221 ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
1222 if (dd->ipath_lli_counter)
1223 dd->ipath_lli_counter--;
1224 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1225 u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1226 u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
1227 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1228 "qp=%x), len %x; ignored\n",
1229 etype, opcode, qp, tlen);
1231 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1232 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1233 be32_to_cpu(hdr->bth[0]) >> 24);
1236 * error packet, type of error unknown.
1237 * Probably type 3, but we don't know, so don't
1238 * even try to print the opcode, etc.
1239 * Usually caused by a "bad packet", that has no
1240 * BTH, when the LRH says it should.
1242 ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1243 " %x, len %x hdrq+%x rhf: %Lx\n",
1244 etail, tlen, l, (unsigned long long)
1245 le64_to_cpu(*(__le64 *) rhf_addr));
1246 if (ipath_debug & __IPATH_ERRPKTDBG) {
1247 u32 j, *d, dw = rsize-2;
1248 if (rsize > (tlen>>2))
1251 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1253 for (j = 0; j < dw; j++)
1254 printk(KERN_DEBUG "%8x%s", d[j],
1255 (j%8) == 7 ? "\n" : " ");
1256 printk(KERN_DEBUG ".\n");
1262 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1263 l + dd->ipath_rhf_offset;
1264 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1265 u32 seq = ipath_hdrget_seq(rhf_addr);
1267 if (++pd->port_seq_cnt > 13)
1268 pd->port_seq_cnt = 1;
1269 if (seq != pd->port_seq_cnt)
1271 } else if (l == hdrqtail)
1274 * update head regs on last packet, and every 16 packets.
1275 * Reduce bus traffic, while still trying to prevent
1276 * rcvhdrq overflows, for when the queue is nearly full
1278 if (last || !(i & 0xf)) {
1281 /* request IBA6120 and 7220 interrupt only on last */
1283 lval |= dd->ipath_rhdrhead_intr_off;
1284 ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1287 ipath_write_ureg(dd, ur_rcvegrindexhead,
1288 etail, pd->port_port);
1294 if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1295 !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1296 /* IBA6110 workaround; we can have a race clearing chip
1297 * interrupt with another interrupt about to be delivered,
1298 * and can clear it before it is delivered on the GPIO
1299 * workaround. By doing the extra check here for the
1300 * in-memory tail register updating while we were doing
1301 * earlier packets, we "almost" guarantee we have covered
1304 u32 hqtail = ipath_get_rcvhdrtail(pd);
1305 if (hqtail != hdrqtail) {
1307 reloop = 1; /* loop 1 extra time at most */
1316 if (pkttot > ipath_stats.sps_maxpkts_call)
1317 ipath_stats.sps_maxpkts_call = pkttot;
1318 ipath_stats.sps_port0pkts += pkttot;
1319 ipath_stats.sps_avgpkts_call =
1320 ipath_stats.sps_port0pkts / ++totcalls;
1326 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1327 * @dd: the infinipath device
1329 * called whenever our local copy indicates we have run out of send buffers
1330 * NOTE: This can be called from interrupt context by some code
1331 * and from non-interrupt context by ipath_getpiobuf().
1334 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1336 unsigned long flags;
1338 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1340 /* If the generation (check) bits have changed, then we update the
1341 * busy bit for the corresponding PIO buffer. This algorithm will
1342 * modify positions to the value they already have in some cases
1343 * (i.e., no change), but it's faster than changing only the bits
1344 * that have changed.
1346 * We would like to do this atomicly, to avoid spinlocks in the
1347 * critical send path, but that's not really possible, given the
1348 * type of changes, and that this routine could be called on
1349 * multiple cpu's simultaneously, so we lock in this routine only,
1350 * to avoid conflicting updates; all we change is the shadow, and
1351 * it's a single 64 bit memory location, so by definition the update
1352 * is atomic in terms of what other cpu's can see in testing the
1353 * bits. The spin_lock overhead isn't too bad, since it only
1354 * happens when all buffers are in use, so only cpu overhead, not
1355 * latency or bandwidth is affected.
1357 if (!dd->ipath_pioavailregs_dma) {
1358 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1361 if (ipath_debug & __IPATH_VERBDBG) {
1362 /* only if packet debug and verbose */
1363 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1364 unsigned long *shadow = dd->ipath_pioavailshadow;
1366 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1367 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1369 (unsigned long long) le64_to_cpu(dma[0]),
1371 (unsigned long long) le64_to_cpu(dma[1]),
1373 (unsigned long long) le64_to_cpu(dma[2]),
1375 (unsigned long long) le64_to_cpu(dma[3]),
1379 PKT, "2nd group, dma4=%llx shad4=%lx, "
1380 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1382 (unsigned long long) le64_to_cpu(dma[4]),
1384 (unsigned long long) le64_to_cpu(dma[5]),
1386 (unsigned long long) le64_to_cpu(dma[6]),
1388 (unsigned long long) le64_to_cpu(dma[7]),
1391 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1392 for (i = 0; i < piobregs; i++) {
1393 u64 pchbusy, pchg, piov, pnew;
1395 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1397 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1398 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1400 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1401 pchg = dd->ipath_pioavailkernel[i] &
1402 ~(dd->ipath_pioavailshadow[i] ^ piov);
1403 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1404 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1405 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1406 pnew |= piov & pchbusy;
1407 dd->ipath_pioavailshadow[i] = pnew;
1410 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1414 * used to force update of pioavailshadow if we can't get a pio buffer.
1415 * Needed primarily due to exitting freeze mode after recovering
1416 * from errors. Done lazily, because it's safer (known to not
1417 * be writing pio buffers).
1419 static void ipath_reset_availshadow(struct ipath_devdata *dd)
1422 unsigned long flags;
1424 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1425 for (i = 0; i < dd->ipath_pioavregs; i++) {
1427 /* deal with 6110 chip bug on high register #s */
1428 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1430 val = le64_to_cpu(dd->ipath_pioavailregs_dma[im]);
1432 * busy out the buffers not in the kernel avail list,
1433 * without changing the generation bits.
1435 oldval = dd->ipath_pioavailshadow[i];
1436 dd->ipath_pioavailshadow[i] = val |
1437 ((~dd->ipath_pioavailkernel[i] <<
1438 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT) &
1439 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
1440 if (oldval != dd->ipath_pioavailshadow[i])
1441 ipath_dbg("shadow[%d] was %Lx, now %lx\n",
1442 i, (unsigned long long) oldval,
1443 dd->ipath_pioavailshadow[i]);
1445 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1449 * ipath_setrcvhdrsize - set the receive header size
1450 * @dd: the infinipath device
1451 * @rhdrsize: the receive header size
1453 * called from user init code, and also layered driver init
1455 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1459 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1460 if (dd->ipath_rcvhdrsize != rhdrsize) {
1461 dev_info(&dd->pcidev->dev,
1462 "Error: can't set protocol header "
1463 "size %u, already %u\n",
1464 rhdrsize, dd->ipath_rcvhdrsize);
1467 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1468 "size %u\n", dd->ipath_rcvhdrsize);
1469 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1470 (sizeof(u64) / sizeof(u32)))) {
1471 ipath_dbg("Error: can't set protocol header size %u "
1472 "(> max %u)\n", rhdrsize,
1473 dd->ipath_rcvhdrentsize -
1474 (u32) (sizeof(u64) / sizeof(u32)));
1477 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1478 dd->ipath_rcvhdrsize = rhdrsize;
1479 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1480 dd->ipath_rcvhdrsize);
1481 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1482 dd->ipath_rcvhdrsize);
1488 * debugging code and stats updates if no pio buffers available.
1490 static noinline void no_pio_bufs(struct ipath_devdata *dd)
1492 unsigned long *shadow = dd->ipath_pioavailshadow;
1493 __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1495 dd->ipath_upd_pio_shadow = 1;
1498 * not atomic, but if we lose a stat count in a while, that's OK
1500 ipath_stats.sps_nopiobufs++;
1501 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1502 ipath_force_pio_avail_update(dd); /* at start */
1503 ipath_dbg("%u tries no piobufavail ts%lx; dmacopy: "
1504 "%llx %llx %llx %llx\n"
1505 "ipath shadow: %lx %lx %lx %lx\n",
1506 dd->ipath_consec_nopiobuf,
1507 (unsigned long)get_cycles(),
1508 (unsigned long long) le64_to_cpu(dma[0]),
1509 (unsigned long long) le64_to_cpu(dma[1]),
1510 (unsigned long long) le64_to_cpu(dma[2]),
1511 (unsigned long long) le64_to_cpu(dma[3]),
1512 shadow[0], shadow[1], shadow[2], shadow[3]);
1514 * 4 buffers per byte, 4 registers above, cover rest
1517 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1518 (sizeof(shadow[0]) * 4 * 4))
1519 ipath_dbg("2nd group: dmacopy: "
1520 "%llx %llx %llx %llx\n"
1521 "ipath shadow: %lx %lx %lx %lx\n",
1522 (unsigned long long)le64_to_cpu(dma[4]),
1523 (unsigned long long)le64_to_cpu(dma[5]),
1524 (unsigned long long)le64_to_cpu(dma[6]),
1525 (unsigned long long)le64_to_cpu(dma[7]),
1526 shadow[4], shadow[5], shadow[6], shadow[7]);
1528 /* at end, so update likely happened */
1529 ipath_reset_availshadow(dd);
1534 * common code for normal driver pio buffer allocation, and reserved
1537 * do appropriate marking as busy, etc.
1538 * returns buffer number if one found (>=0), negative number is error.
1540 static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1541 u32 *pbufnum, u32 first, u32 last, u32 firsti)
1543 int i, j, updated = 0;
1545 unsigned long flags;
1546 unsigned long *shadow = dd->ipath_pioavailshadow;
1549 piobcnt = last - first;
1550 if (dd->ipath_upd_pio_shadow) {
1552 * Minor optimization. If we had no buffers on last call,
1553 * start out by doing the update; continue and do scan even
1554 * if no buffers were updated, to be paranoid
1556 ipath_update_pio_bufs(dd);
1563 * while test_and_set_bit() is atomic, we do that and then the
1564 * change_bit(), and the pair is not. See if this is the cause
1565 * of the remaining armlaunch errors.
1567 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1568 for (j = 0; j < piobcnt; j++, i++) {
1571 if (__test_and_set_bit((2 * i) + 1, shadow))
1573 /* flip generation bit */
1574 __change_bit(2 * i, shadow);
1577 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1582 * first time through; shadow exhausted, but may be
1583 * buffers available, try an update and then rescan.
1585 ipath_update_pio_bufs(dd);
1589 } else if (updated == 1 && piobcnt <=
1590 ((dd->ipath_sendctrl
1591 >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1592 INFINIPATH_S_UPDTHRESH_MASK)) {
1594 * for chips supporting and using the update
1595 * threshold we need to force an update of the
1596 * in-memory copy if the count is less than the
1597 * thershold, then check one more time.
1599 ipath_force_pio_avail_update(dd);
1600 ipath_update_pio_bufs(dd);
1609 if (i < dd->ipath_piobcnt2k)
1610 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1611 i * dd->ipath_palign);
1613 buf = (u32 __iomem *)
1614 (dd->ipath_pio4kbase +
1615 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1624 * ipath_getpiobuf - find an available pio buffer
1625 * @dd: the infinipath device
1626 * @plen: the size of the PIO buffer needed in 32-bit words
1627 * @pbufnum: the buffer number is placed here
1629 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1635 if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1636 first = dd->ipath_piobcnt2k;
1637 lasti = dd->ipath_lastpioindexl;
1640 lasti = dd->ipath_lastpioindex;
1642 nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1643 buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1647 * Set next starting place. It's just an optimization,
1648 * it doesn't matter who wins on this, so no locking
1650 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1651 dd->ipath_lastpioindexl = pnum + 1;
1653 dd->ipath_lastpioindex = pnum + 1;
1654 if (dd->ipath_upd_pio_shadow)
1655 dd->ipath_upd_pio_shadow = 0;
1656 if (dd->ipath_consec_nopiobuf)
1657 dd->ipath_consec_nopiobuf = 0;
1658 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1659 pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1668 * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1669 * @dd: the infinipath device
1670 * @start: the starting send buffer number
1671 * @len: the number of send buffers
1672 * @avail: true if the buffers are available for kernel use, false otherwise
1674 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1675 unsigned len, int avail)
1677 unsigned long flags;
1678 unsigned end, cnt = 0;
1680 /* There are two bits per send buffer (busy and generation) */
1682 end = start + len * 2;
1684 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1685 /* Set or clear the busy bit in the shadow. */
1686 while (start < end) {
1691 * the BUSY bit will never be set, because we disarm
1692 * the user buffers before we hand them back to the
1693 * kernel. We do have to make sure the generation
1694 * bit is set correctly in shadow, since it could
1695 * have changed many times while allocated to user.
1696 * We can't use the bitmap functions on the full
1697 * dma array because it is always little-endian, so
1698 * we have to flip to host-order first.
1699 * BITS_PER_LONG is slightly wrong, since it's
1700 * always 64 bits per register in chip...
1701 * We only work on 64 bit kernels, so that's OK.
1703 /* deal with 6110 chip bug on high register #s */
1704 i = start / BITS_PER_LONG;
1705 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1707 __clear_bit(INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
1708 + start, dd->ipath_pioavailshadow);
1709 dma = (unsigned long) le64_to_cpu(
1710 dd->ipath_pioavailregs_dma[im]);
1711 if (test_bit((INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1712 + start) % BITS_PER_LONG, &dma))
1713 __set_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1714 + start, dd->ipath_pioavailshadow);
1716 __clear_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1717 + start, dd->ipath_pioavailshadow);
1718 __set_bit(start, dd->ipath_pioavailkernel);
1720 __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1721 dd->ipath_pioavailshadow);
1722 __clear_bit(start, dd->ipath_pioavailkernel);
1727 if (dd->ipath_pioupd_thresh) {
1728 end = 2 * (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1729 cnt = bitmap_weight(dd->ipath_pioavailkernel, end);
1731 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1734 * When moving buffers from kernel to user, if number assigned to
1735 * the user is less than the pio update threshold, and threshold
1736 * is supported (cnt was computed > 0), drop the update threshold
1737 * so we update at least once per allocated number of buffers.
1738 * In any case, if the kernel buffers are less than the threshold,
1739 * drop the threshold. We don't bother increasing it, having once
1740 * decreased it, since it would typically just cycle back and forth.
1741 * If we don't decrease below buffers in use, we can wait a long
1742 * time for an update, until some other context uses PIO buffers.
1744 if (!avail && len < cnt)
1746 if (cnt < dd->ipath_pioupd_thresh) {
1747 dd->ipath_pioupd_thresh = cnt;
1748 ipath_dbg("Decreased pio update threshold to %u\n",
1749 dd->ipath_pioupd_thresh);
1750 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1751 dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK
1752 << INFINIPATH_S_UPDTHRESH_SHIFT);
1753 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
1754 << INFINIPATH_S_UPDTHRESH_SHIFT;
1755 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1756 dd->ipath_sendctrl);
1757 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1762 * ipath_create_rcvhdrq - create a receive header queue
1763 * @dd: the infinipath device
1764 * @pd: the port data
1766 * this must be contiguous memory (from an i/o perspective), and must be
1767 * DMA'able (which means for some systems, it will go through an IOMMU,
1768 * or be forced into a low address range).
1770 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1771 struct ipath_portdata *pd)
1775 if (!pd->port_rcvhdrq) {
1776 dma_addr_t phys_hdrqtail;
1777 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1778 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1779 sizeof(u32), PAGE_SIZE);
1781 pd->port_rcvhdrq = dma_alloc_coherent(
1782 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1785 if (!pd->port_rcvhdrq) {
1786 ipath_dev_err(dd, "attempt to allocate %d bytes "
1787 "for port %u rcvhdrq failed\n",
1788 amt, pd->port_port);
1793 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1794 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1795 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1797 if (!pd->port_rcvhdrtail_kvaddr) {
1798 ipath_dev_err(dd, "attempt to allocate 1 page "
1799 "for port %u rcvhdrqtailaddr "
1800 "failed\n", pd->port_port);
1802 dma_free_coherent(&dd->pcidev->dev, amt,
1804 pd->port_rcvhdrq_phys);
1805 pd->port_rcvhdrq = NULL;
1808 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1809 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1810 "physical\n", pd->port_port,
1811 (unsigned long long) phys_hdrqtail);
1814 pd->port_rcvhdrq_size = amt;
1816 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1817 "for port %u rcvhdr Q\n",
1818 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1819 (unsigned long) pd->port_rcvhdrq_phys,
1820 (unsigned long) pd->port_rcvhdrq_size,
1824 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1825 "hdrtailaddr@%p %llx physical\n",
1826 pd->port_port, pd->port_rcvhdrq,
1827 (unsigned long long) pd->port_rcvhdrq_phys,
1828 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1829 pd->port_rcvhdrqtailaddr_phys);
1831 /* clear for security and sanity on each use */
1832 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1833 if (pd->port_rcvhdrtail_kvaddr)
1834 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1837 * tell chip each time we init it, even if we are re-using previous
1838 * memory (we zero the register at process close)
1840 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1841 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1842 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1843 pd->port_port, pd->port_rcvhdrq_phys);
1851 * Flush all sends that might be in the ready to send state, as well as any
1852 * that are in the process of being sent. Used whenever we need to be
1853 * sure the send side is idle. Cleans up all buffer state by canceling
1854 * all pio buffers, and issuing an abort, which cleans up anything in the
1855 * launch fifo. The cancel is superfluous on some chip versions, but
1856 * it's safer to always do it.
1857 * PIOAvail bits are updated by the chip as if normal send had happened.
1859 void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
1861 unsigned long flags;
1863 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
1864 ipath_cdbg(VERBOSE, "Ignore while in autonegotiation\n");
1868 * If we have SDMA, and it's not disabled, we have to kick off the
1869 * abort state machine, provided we aren't already aborting.
1870 * If we are in the process of aborting SDMA (!DISABLED, but ABORTING),
1871 * we skip the rest of this routine. It is already "in progress"
1873 if (dd->ipath_flags & IPATH_HAS_SEND_DMA) {
1875 unsigned long *statp = &dd->ipath_sdma_status;
1877 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1879 test_and_set_bit(IPATH_SDMA_ABORTING, statp)
1880 && !test_bit(IPATH_SDMA_DISABLED, statp);
1881 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1886 ipath_dbg("Cancelling all in-progress send buffers\n");
1888 /* skip armlaunch errs for a while */
1889 dd->ipath_lastcancel = jiffies + HZ / 2;
1892 * The abort bit is auto-clearing. We also don't want pioavail
1893 * update happening during this, and we don't want any other
1894 * sends going out, so turn those off for the duration. We read
1895 * the scratch register to be sure that cancels and the abort
1896 * have taken effect in the chip. Otherwise two parts are same
1897 * as ipath_force_pio_avail_update()
1899 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1900 dd->ipath_sendctrl &= ~(INFINIPATH_S_PIOBUFAVAILUPD
1901 | INFINIPATH_S_PIOENABLE);
1902 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1903 dd->ipath_sendctrl | INFINIPATH_S_ABORT);
1904 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1905 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1907 /* disarm all send buffers */
1908 ipath_disarm_piobufs(dd, 0,
1909 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1911 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1912 set_bit(IPATH_SDMA_DISARMED, &dd->ipath_sdma_status);
1914 if (restore_sendctrl) {
1915 /* else done by caller later if needed */
1916 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1917 dd->ipath_sendctrl |= INFINIPATH_S_PIOBUFAVAILUPD |
1918 INFINIPATH_S_PIOENABLE;
1919 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1920 dd->ipath_sendctrl);
1921 /* and again, be sure all have hit the chip */
1922 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1923 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1926 if ((dd->ipath_flags & IPATH_HAS_SEND_DMA) &&
1927 !test_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status) &&
1928 test_bit(IPATH_SDMA_RUNNING, &dd->ipath_sdma_status)) {
1929 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1930 /* only wait so long for intr */
1931 dd->ipath_sdma_abort_intr_timeout = jiffies + HZ;
1932 dd->ipath_sdma_reset_wait = 200;
1933 if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status))
1934 tasklet_hi_schedule(&dd->ipath_sdma_abort_task);
1935 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1941 * Force an update of in-memory copy of the pioavail registers, when
1942 * needed for any of a variety of reasons. We read the scratch register
1943 * to make it highly likely that the update will have happened by the
1944 * time we return. If already off (as in cancel_sends above), this
1945 * routine is a nop, on the assumption that the caller will "do the
1948 void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1950 unsigned long flags;
1952 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1953 if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1954 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1955 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1956 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1957 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1958 dd->ipath_sendctrl);
1959 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1961 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1964 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1968 static const char *what[4] = {
1970 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
1971 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1972 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1975 if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
1977 * If we are told to disable, note that so link-recovery
1978 * code does not attempt to bring us back up.
1981 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
1983 } else if (linitcmd) {
1985 * Any other linkinitcmd will lead to LINKDOWN and then
1986 * to INIT (if all is well), so clear flag to let
1987 * link-recovery code attempt to bring us back up.
1990 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
1994 mod_wd = (linkcmd << dd->ibcc_lc_shift) |
1995 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
1997 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
1998 dd->ipath_unit, what[linkcmd], linitcmd,
1999 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
2000 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
2002 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2003 dd->ipath_ibcctrl | mod_wd);
2004 /* read from chip so write is flushed */
2005 (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2008 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
2014 case IPATH_IB_LINKDOWN_ONLY:
2015 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
2020 case IPATH_IB_LINKDOWN:
2021 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2022 INFINIPATH_IBCC_LINKINITCMD_POLL);
2027 case IPATH_IB_LINKDOWN_SLEEP:
2028 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2029 INFINIPATH_IBCC_LINKINITCMD_SLEEP);
2034 case IPATH_IB_LINKDOWN_DISABLE:
2035 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2036 INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2041 case IPATH_IB_LINKARM:
2042 if (dd->ipath_flags & IPATH_LINKARMED) {
2046 if (!(dd->ipath_flags &
2047 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
2051 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
2054 * Since the port can transition to ACTIVE by receiving
2055 * a non VL 15 packet, wait for either state.
2057 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
2060 case IPATH_IB_LINKACTIVE:
2061 if (dd->ipath_flags & IPATH_LINKACTIVE) {
2065 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
2069 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
2070 lstate = IPATH_LINKACTIVE;
2073 case IPATH_IB_LINK_LOOPBACK:
2074 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
2075 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
2076 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2079 /* turn heartbeat off, as it causes loopback to fail */
2080 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2081 IPATH_IB_HRTBT_OFF);
2086 case IPATH_IB_LINK_EXTERNAL:
2087 dev_info(&dd->pcidev->dev,
2088 "Disabling IB local loopback (normal)\n");
2089 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2091 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
2092 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2099 * Heartbeat can be explicitly enabled by the user via
2100 * "hrtbt_enable" "file", and if disabled, trying to enable here
2101 * will have no effect. Implicit changes (heartbeat off when
2102 * loopback on, and vice versa) are included to ease testing.
2104 case IPATH_IB_LINK_HRTBT:
2105 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2109 case IPATH_IB_LINK_NO_HRTBT:
2110 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2111 IPATH_IB_HRTBT_OFF);
2115 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
2119 ret = ipath_wait_linkstate(dd, lstate, 2000);
2126 * ipath_set_mtu - set the MTU
2127 * @dd: the infinipath device
2130 * we can handle "any" incoming size, the issue here is whether we
2131 * need to restrict our outgoing size. For now, we don't do any
2132 * sanity checking on this, and we don't deal with what happens to
2133 * programs that are already running when the size changes.
2134 * NOTE: changing the MTU will usually cause the IBC to go back to
2135 * link INIT state...
2137 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
2144 * mtu is IB data payload max. It's the largest power of 2 less
2145 * than piosize (or even larger, since it only really controls the
2146 * largest we can receive; we can send the max of the mtu and
2147 * piosize). We check that it's one of the valid IB sizes.
2149 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
2150 (arg != 4096 || !ipath_mtu4096)) {
2151 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
2155 if (dd->ipath_ibmtu == arg) {
2156 ret = 0; /* same as current */
2160 piosize = dd->ipath_ibmaxlen;
2161 dd->ipath_ibmtu = arg;
2163 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
2164 /* Only if it's not the initial value (or reset to it) */
2165 if (piosize != dd->ipath_init_ibmaxlen) {
2166 if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
2167 piosize = dd->ipath_init_ibmaxlen;
2168 dd->ipath_ibmaxlen = piosize;
2171 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
2172 piosize = arg + IPATH_PIO_MAXIBHDR;
2173 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
2174 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
2176 dd->ipath_ibmaxlen = piosize;
2181 u64 ibc = dd->ipath_ibcctrl, ibdw;
2183 * update our housekeeping variables, and set IBC max
2184 * size, same as init code; max IBC is max we allow in
2185 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2187 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
2188 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
2189 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
2190 dd->ibcc_mpl_shift);
2191 ibc |= ibdw << dd->ibcc_mpl_shift;
2192 dd->ipath_ibcctrl = ibc;
2193 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2195 dd->ipath_f_tidtemplate(dd);
2204 int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc)
2206 dd->ipath_lid = lid;
2207 dd->ipath_lmc = lmc;
2209 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid |
2210 (~((1U << lmc) - 1)) << 16);
2212 dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid);
2219 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2220 * @dd: the infinipath device
2221 * @regno: the register number to write
2222 * @port: the port containing the register
2223 * @value: the value to write
2225 * Registers that vary with the chip implementation constants (port)
2228 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2229 unsigned port, u64 value)
2233 if (port < dd->ipath_portcnt &&
2234 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2235 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2236 where = regno + port;
2240 ipath_write_kreg(dd, where, value);
2244 * Following deal with the "obviously simple" task of overriding the state
2245 * of the LEDS, which normally indicate link physical and logical status.
2246 * The complications arise in dealing with different hardware mappings
2247 * and the board-dependent routine being called from interrupts.
2248 * and then there's the requirement to _flash_ them.
2250 #define LED_OVER_FREQ_SHIFT 8
2251 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2252 /* Below is "non-zero" to force override, but both actual LEDs are off */
2253 #define LED_OVER_BOTH_OFF (8)
2255 static void ipath_run_led_override(unsigned long opaque)
2257 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2260 u64 lstate, ltstate, val;
2262 if (!(dd->ipath_flags & IPATH_INITTED))
2265 pidx = dd->ipath_led_override_phase++ & 1;
2266 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2267 timeoff = dd->ipath_led_override_timeoff;
2270 * below potentially restores the LED values per current status,
2271 * should also possibly setup the traffic-blink register,
2272 * but leave that to per-chip functions.
2274 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2275 ltstate = ipath_ib_linktrstate(dd, val);
2276 lstate = ipath_ib_linkstate(dd, val);
2278 dd->ipath_f_setextled(dd, lstate, ltstate);
2279 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2282 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2286 if (!(dd->ipath_flags & IPATH_INITTED))
2289 /* First check if we are blinking. If not, use 1HZ polling */
2291 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2294 /* For blink, set each phase from one nybble of val */
2295 dd->ipath_led_override_vals[0] = val & 0xF;
2296 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2297 timeoff = (HZ << 4)/freq;
2299 /* Non-blink set both phases the same. */
2300 dd->ipath_led_override_vals[0] = val & 0xF;
2301 dd->ipath_led_override_vals[1] = val & 0xF;
2303 dd->ipath_led_override_timeoff = timeoff;
2306 * If the timer has not already been started, do so. Use a "quick"
2307 * timeout so the function will be called soon, to look at our request.
2309 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2310 /* Need to start timer */
2311 init_timer(&dd->ipath_led_override_timer);
2312 dd->ipath_led_override_timer.function =
2313 ipath_run_led_override;
2314 dd->ipath_led_override_timer.data = (unsigned long) dd;
2315 dd->ipath_led_override_timer.expires = jiffies + 1;
2316 add_timer(&dd->ipath_led_override_timer);
2318 atomic_dec(&dd->ipath_led_override_timer_active);
2322 * ipath_shutdown_device - shut down a device
2323 * @dd: the infinipath device
2325 * This is called to make the device quiet when we are about to
2326 * unload the driver, and also when the device is administratively
2327 * disabled. It does not free any data structures.
2328 * Everything it does has to be setup again by ipath_init_chip(dd,1)
2330 void ipath_shutdown_device(struct ipath_devdata *dd)
2332 unsigned long flags;
2334 ipath_dbg("Shutting down the device\n");
2336 ipath_hol_up(dd); /* make sure user processes aren't suspended */
2338 dd->ipath_flags |= IPATH_LINKUNK;
2339 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2340 IPATH_LINKINIT | IPATH_LINKARMED |
2342 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2343 IPATH_STATUS_IB_READY);
2345 /* mask interrupts, but not errors */
2346 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2348 dd->ipath_rcvctrl = 0;
2349 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2352 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2356 * gracefully stop all sends allowing any in progress to trickle out
2359 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2360 dd->ipath_sendctrl = 0;
2361 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
2363 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2364 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2367 * enough for anything that's going to trickle out to have actually
2372 dd->ipath_f_setextled(dd, 0, 0); /* make sure LEDs are off */
2374 ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2375 ipath_cancel_sends(dd, 0);
2378 * we are shutting down, so tell components that care. We don't do
2379 * this on just a link state change, much like ethernet, a cable
2380 * unplug, etc. doesn't change driver state
2382 signal_ib_event(dd, IB_EVENT_PORT_ERR);
2385 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2386 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2387 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2390 * clear SerdesEnable and turn the leds off; do this here because
2391 * we are unloading, so don't count on interrupts to move along
2392 * Turn the LEDs off explicitly for the same reason.
2394 dd->ipath_f_quiet_serdes(dd);
2396 /* stop all the timers that might still be running */
2397 del_timer_sync(&dd->ipath_hol_timer);
2398 if (dd->ipath_stats_timer_active) {
2399 del_timer_sync(&dd->ipath_stats_timer);
2400 dd->ipath_stats_timer_active = 0;
2402 if (dd->ipath_intrchk_timer.data) {
2403 del_timer_sync(&dd->ipath_intrchk_timer);
2404 dd->ipath_intrchk_timer.data = 0;
2406 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2407 del_timer_sync(&dd->ipath_led_override_timer);
2408 atomic_set(&dd->ipath_led_override_timer_active, 0);
2412 * clear all interrupts and errors, so that the next time the driver
2413 * is loaded or device is enabled, we know that whatever is set
2414 * happened while we were unloaded
2416 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2417 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2418 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2419 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2421 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2422 ipath_update_eeprom_log(dd);
2426 * ipath_free_pddata - free a port's allocated data
2427 * @dd: the infinipath device
2428 * @pd: the portdata structure
2430 * free up any allocated data for a port
2431 * This should not touch anything that would affect a simultaneous
2432 * re-allocation of port data, because it is called after ipath_mutex
2433 * is released (and can be called from reinit as well).
2434 * It should never change any chip state, or global driver state.
2435 * (The only exception to global state is freeing the port0 port0_skbs.)
2437 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2442 if (pd->port_rcvhdrq) {
2443 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2444 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2445 (unsigned long) pd->port_rcvhdrq_size);
2446 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2447 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2448 pd->port_rcvhdrq = NULL;
2449 if (pd->port_rcvhdrtail_kvaddr) {
2450 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2451 pd->port_rcvhdrtail_kvaddr,
2452 pd->port_rcvhdrqtailaddr_phys);
2453 pd->port_rcvhdrtail_kvaddr = NULL;
2456 if (pd->port_port && pd->port_rcvegrbuf) {
2459 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2460 void *base = pd->port_rcvegrbuf[e];
2461 size_t size = pd->port_rcvegrbuf_size;
2463 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2464 "chunk %u/%u\n", base,
2465 (unsigned long) size,
2466 e, pd->port_rcvegrbuf_chunks);
2467 dma_free_coherent(&dd->pcidev->dev, size,
2468 base, pd->port_rcvegrbuf_phys[e]);
2470 kfree(pd->port_rcvegrbuf);
2471 pd->port_rcvegrbuf = NULL;
2472 kfree(pd->port_rcvegrbuf_phys);
2473 pd->port_rcvegrbuf_phys = NULL;
2474 pd->port_rcvegrbuf_chunks = 0;
2475 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2477 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2479 dd->ipath_port0_skbinfo = NULL;
2480 ipath_cdbg(VERBOSE, "free closed port %d "
2481 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2483 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2484 if (skbinfo[e].skb) {
2485 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2487 PCI_DMA_FROMDEVICE);
2488 dev_kfree_skb(skbinfo[e].skb);
2492 kfree(pd->port_tid_pg_list);
2493 vfree(pd->subport_uregbase);
2494 vfree(pd->subport_rcvegrbuf);
2495 vfree(pd->subport_rcvhdr_base);
2499 static int __init infinipath_init(void)
2503 if (ipath_debug & __IPATH_DBG)
2504 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2507 * These must be called before the driver is registered with
2508 * the PCI subsystem.
2510 idr_init(&unit_table);
2512 ret = pci_register_driver(&ipath_driver);
2514 printk(KERN_ERR IPATH_DRV_NAME
2515 ": Unable to register driver: error %d\n", -ret);
2519 ret = ipath_init_ipathfs();
2521 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2522 "ipathfs: error %d\n", -ret);
2529 pci_unregister_driver(&ipath_driver);
2532 idr_destroy(&unit_table);
2538 static void __exit infinipath_cleanup(void)
2540 ipath_exit_ipathfs();
2542 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2543 pci_unregister_driver(&ipath_driver);
2545 idr_destroy(&unit_table);
2549 * ipath_reset_device - reset the chip if possible
2550 * @unit: the device to reset
2552 * Whether or not reset is successful, we attempt to re-initialize the chip
2553 * (that is, much like a driver unload/reload). We clear the INITTED flag
2554 * so that the various entry points will fail until we reinitialize. For
2555 * now, we only allow this if no user ports are open that use chip resources
2557 int ipath_reset_device(int unit)
2560 struct ipath_devdata *dd = ipath_lookup(unit);
2561 unsigned long flags;
2568 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2569 /* Need to stop LED timer, _then_ shut off LEDs */
2570 del_timer_sync(&dd->ipath_led_override_timer);
2571 atomic_set(&dd->ipath_led_override_timer_active, 0);
2574 /* Shut off LEDs after we are sure timer is not running */
2575 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2576 dd->ipath_f_setextled(dd, 0, 0);
2578 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2580 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2581 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2582 "not initialized or not present\n", unit);
2587 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
2589 for (i = 1; i < dd->ipath_cfgports; i++) {
2590 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2592 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2593 ipath_dbg("unit %u port %d is in use "
2594 "(PID %u cmd %s), can't reset\n",
2596 pid_nr(dd->ipath_pd[i]->port_pid),
2597 dd->ipath_pd[i]->port_comm);
2601 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2603 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2606 dd->ipath_flags &= ~IPATH_INITTED;
2607 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2608 ret = dd->ipath_f_reset(dd);
2610 ipath_dbg("Reinitializing unit %u after reset attempt\n",
2612 ret = ipath_init_chip(dd, 1);
2616 ipath_dev_err(dd, "Reinitialize unit %u after "
2617 "reset failed with %d\n", unit, ret);
2619 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2620 "resetting\n", unit);
2627 * send a signal to all the processes that have the driver open
2628 * through the normal interfaces (i.e., everything other than diags
2629 * interface). Returns number of signalled processes.
2631 static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2633 int i, sub, any = 0;
2635 unsigned long flags;
2640 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
2641 for (i = 1; i < dd->ipath_cfgports; i++) {
2642 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2644 pid = dd->ipath_pd[i]->port_pid;
2648 dev_info(&dd->pcidev->dev, "context %d in use "
2649 "(PID %u), sending signal %d\n",
2650 i, pid_nr(pid), sig);
2651 kill_pid(pid, sig, 1);
2653 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2654 pid = dd->ipath_pd[i]->port_subpid[sub];
2657 dev_info(&dd->pcidev->dev, "sub-context "
2658 "%d:%d in use (PID %u), sending "
2659 "signal %d\n", i, sub, pid_nr(pid), sig);
2660 kill_pid(pid, sig, 1);
2664 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2668 static void ipath_hol_signal_down(struct ipath_devdata *dd)
2670 if (ipath_signal_procs(dd, SIGSTOP))
2671 ipath_dbg("Stopped some processes\n");
2672 ipath_cancel_sends(dd, 1);
2676 static void ipath_hol_signal_up(struct ipath_devdata *dd)
2678 if (ipath_signal_procs(dd, SIGCONT))
2679 ipath_dbg("Continued some processes\n");
2683 * link is down, stop any users processes, and flush pending sends
2684 * to prevent HoL blocking, then start the HoL timer that
2685 * periodically continues, then stop procs, so they can detect
2686 * link down if they want, and do something about it.
2687 * Timer may already be running, so use mod_timer, not add_timer.
2689 void ipath_hol_down(struct ipath_devdata *dd)
2691 dd->ipath_hol_state = IPATH_HOL_DOWN;
2692 ipath_hol_signal_down(dd);
2693 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2694 dd->ipath_hol_timer.expires = jiffies +
2695 msecs_to_jiffies(ipath_hol_timeout_ms);
2696 mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
2700 * link is up, continue any user processes, and ensure timer
2701 * is a nop, if running. Let timer keep running, if set; it
2702 * will nop when it sees the link is up
2704 void ipath_hol_up(struct ipath_devdata *dd)
2706 ipath_hol_signal_up(dd);
2707 dd->ipath_hol_state = IPATH_HOL_UP;
2711 * toggle the running/not running state of user proceses
2712 * to prevent HoL blocking on chip resources, but still allow
2713 * user processes to do link down special case handling.
2714 * Should only be called via the timer
2716 void ipath_hol_event(unsigned long opaque)
2718 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2720 if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2721 && dd->ipath_hol_state != IPATH_HOL_UP) {
2722 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2723 ipath_dbg("Stopping processes\n");
2724 ipath_hol_signal_down(dd);
2725 } else { /* may do "extra" if also in ipath_hol_up() */
2726 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2727 ipath_dbg("Continuing processes\n");
2728 ipath_hol_signal_up(dd);
2730 if (dd->ipath_hol_state == IPATH_HOL_UP)
2731 ipath_dbg("link's up, don't resched timer\n");
2733 dd->ipath_hol_timer.expires = jiffies +
2734 msecs_to_jiffies(ipath_hol_timeout_ms);
2735 mod_timer(&dd->ipath_hol_timer,
2736 dd->ipath_hol_timer.expires);
2740 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2744 if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
2746 if (dd->ipath_rx_pol_inv != new_pol_inv) {
2747 dd->ipath_rx_pol_inv = new_pol_inv;
2748 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2749 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2750 INFINIPATH_XGXS_RX_POL_SHIFT);
2751 val |= ((u64)dd->ipath_rx_pol_inv) <<
2752 INFINIPATH_XGXS_RX_POL_SHIFT;
2753 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2759 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2760 * the 7220, which is count-based, rather than trigger-based. Safe for the
2761 * driver check, since it's at init. Not completely safe when used for
2762 * user-mode checking, since some error checking can be lost, but not
2763 * particularly risky, and only has problematic side-effects in the face of
2764 * very buggy user code. There is no reference counting, but that's also
2765 * fine, given the intended use.
2767 void ipath_enable_armlaunch(struct ipath_devdata *dd)
2769 dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2770 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2771 INFINIPATH_E_SPIOARMLAUNCH);
2772 dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2773 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2774 dd->ipath_errormask);
2777 void ipath_disable_armlaunch(struct ipath_devdata *dd)
2779 /* so don't re-enable if already set */
2780 dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2781 dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2782 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2783 dd->ipath_errormask);
2786 module_init(infinipath_init);
2787 module_exit(infinipath_cleanup);