drivers/media/dvb/frontends/tda10048.c

   1 /*
   2     NXP TDA10048HN DVB OFDM demodulator driver
   3
   4     Copyright (C) 2009 Steven Toth <stoth@kernellabs.com>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19
  20 */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/slab.h>
  27 #include <linux/delay.h>
  28 #include <linux/math64.h>
  29 #include <asm/div64.h>
  30 #include "dvb_frontend.h"
  31 #include "dvb_math.h"
  32 #include "tda10048.h"
  33
  34 #define TDA10048_DEFAULT_FIRMWARE "dvb-fe-tda10048-1.0.fw"
  35 #define TDA10048_DEFAULT_FIRMWARE_SIZE 24878
  36
  37 /* Register name definitions */
  38 #define TDA10048_IDENTITY          0x00
  39 #define TDA10048_VERSION           0x01
  40 #define TDA10048_DSP_CODE_CPT      0x0C
  41 #define TDA10048_DSP_CODE_IN       0x0E
  42 #define TDA10048_IN_CONF1          0x10
  43 #define TDA10048_IN_CONF2          0x11
  44 #define TDA10048_IN_CONF3          0x12
  45 #define TDA10048_OUT_CONF1         0x14
  46 #define TDA10048_OUT_CONF2         0x15
  47 #define TDA10048_OUT_CONF3         0x16
  48 #define TDA10048_AUTO              0x18
  49 #define TDA10048_SYNC_STATUS       0x1A
  50 #define TDA10048_CONF_C4_1         0x1E
  51 #define TDA10048_CONF_C4_2         0x1F
  52 #define TDA10048_CODE_IN_RAM       0x20
  53 #define TDA10048_CHANNEL_INFO1_R   0x22
  54 #define TDA10048_CHANNEL_INFO2_R   0x23
  55 #define TDA10048_CHANNEL_INFO1     0x24
  56 #define TDA10048_CHANNEL_INFO2     0x25
  57 #define TDA10048_TIME_ERROR_R      0x26
  58 #define TDA10048_TIME_ERROR        0x27
  59 #define TDA10048_FREQ_ERROR_LSB_R  0x28
  60 #define TDA10048_FREQ_ERROR_MSB_R  0x29
  61 #define TDA10048_FREQ_ERROR_LSB    0x2A
  62 #define TDA10048_FREQ_ERROR_MSB    0x2B
  63 #define TDA10048_IT_SEL            0x30
  64 #define TDA10048_IT_STAT           0x32
  65 #define TDA10048_DSP_AD_LSB        0x3C
  66 #define TDA10048_DSP_AD_MSB        0x3D
  67 #define TDA10048_DSP_REG_LSB       0x3E
  68 #define TDA10048_DSP_REG_MSB       0x3F
  69 #define TDA10048_CONF_TRISTATE1    0x44
  70 #define TDA10048_CONF_TRISTATE2    0x45
  71 #define TDA10048_CONF_POLARITY     0x46
  72 #define TDA10048_GPIO_SP_DS0       0x48
  73 #define TDA10048_GPIO_SP_DS1       0x49
  74 #define TDA10048_GPIO_SP_DS2       0x4A
  75 #define TDA10048_GPIO_SP_DS3       0x4B
  76 #define TDA10048_GPIO_OUT_SEL      0x4C
  77 #define TDA10048_GPIO_SELECT       0x4D
  78 #define TDA10048_IC_MODE           0x4E
  79 #define TDA10048_CONF_XO           0x50
  80 #define TDA10048_CONF_PLL1         0x51
  81 #define TDA10048_CONF_PLL2         0x52
  82 #define TDA10048_CONF_PLL3         0x53
  83 #define TDA10048_CONF_ADC          0x54
  84 #define TDA10048_CONF_ADC_2        0x55
  85 #define TDA10048_CONF_C1_1         0x60
  86 #define TDA10048_CONF_C1_3         0x62
  87 #define TDA10048_AGC_CONF          0x70
  88 #define TDA10048_AGC_THRESHOLD_LSB 0x72
  89 #define TDA10048_AGC_THRESHOLD_MSB 0x73
  90 #define TDA10048_AGC_RENORM        0x74
  91 #define TDA10048_AGC_GAINS         0x76
  92 #define TDA10048_AGC_TUN_MIN       0x78
  93 #define TDA10048_AGC_TUN_MAX       0x79
  94 #define TDA10048_AGC_IF_MIN        0x7A
  95 #define TDA10048_AGC_IF_MAX        0x7B
  96 #define TDA10048_AGC_TUN_LEVEL     0x7E
  97 #define TDA10048_AGC_IF_LEVEL      0x7F
  98 #define TDA10048_DIG_AGC_LEVEL     0x81
  99 #define TDA10048_FREQ_PHY2_LSB     0x86
 100 #define TDA10048_FREQ_PHY2_MSB     0x87
 101 #define TDA10048_TIME_INVWREF_LSB  0x88
 102 #define TDA10048_TIME_INVWREF_MSB  0x89
 103 #define TDA10048_TIME_WREF_LSB     0x8A
 104 #define TDA10048_TIME_WREF_MID1    0x8B
 105 #define TDA10048_TIME_WREF_MID2    0x8C
 106 #define TDA10048_TIME_WREF_MSB     0x8D
 107 #define TDA10048_NP_OUT            0xA2
 108 #define TDA10048_CELL_ID_LSB       0xA4
 109 #define TDA10048_CELL_ID_MSB       0xA5
 110 #define TDA10048_EXTTPS_ODD        0xAA
 111 #define TDA10048_EXTTPS_EVEN       0xAB
 112 #define TDA10048_TPS_LENGTH        0xAC
 113 #define TDA10048_FREE_REG_1        0xB2
 114 #define TDA10048_FREE_REG_2        0xB3
 115 #define TDA10048_CONF_C3_1         0xC0
 116 #define TDA10048_CVBER_CTRL        0xC2
 117 #define TDA10048_CBER_NMAX_LSB     0xC4
 118 #define TDA10048_CBER_NMAX_MSB     0xC5
 119 #define TDA10048_CBER_LSB          0xC6
 120 #define TDA10048_CBER_MSB          0xC7
 121 #define TDA10048_VBER_LSB          0xC8
 122 #define TDA10048_VBER_MID          0xC9
 123 #define TDA10048_VBER_MSB          0xCA
 124 #define TDA10048_CVBER_LUT         0xCC
 125 #define TDA10048_UNCOR_CTRL        0xCD
 126 #define TDA10048_UNCOR_CPT_LSB     0xCE
 127 #define TDA10048_UNCOR_CPT_MSB     0xCF
 128 #define TDA10048_SOFT_IT_C3        0xD6
 129 #define TDA10048_CONF_TS2          0xE0
 130 #define TDA10048_CONF_TS1          0xE1
 131
 132 static unsigned int debug;
 133
 134 #define dprintk(level, fmt, arg...)\
 135         do { if (debug >= level)\
 136                 printk(KERN_DEBUG "tda10048: " fmt, ## arg);\
 137         } while (0)
 138
 139 struct tda10048_state {
 140
 141         struct i2c_adapter *i2c;
 142
 143         /* We'll cache and update the attach config settings */
 144         struct tda10048_config config;
 145         struct dvb_frontend frontend;
 146
 147         int fwloaded;
 148
 149         u32 freq_if_hz;
 150         u32 xtal_hz;
 151         u32 pll_mfactor;
 152         u32 pll_nfactor;
 153         u32 pll_pfactor;
 154         u32 sample_freq;
 155
 156         enum fe_bandwidth bandwidth;
 157 };
 158
 159 static struct init_tab {
 160         u8      reg;
 161         u16     data;
 162 } init_tab[] = {
 163         { TDA10048_CONF_PLL1, 0x08 },
 164         { TDA10048_CONF_ADC_2, 0x00 },
 165         { TDA10048_CONF_C4_1, 0x00 },
 166         { TDA10048_CONF_PLL1, 0x0f },
 167         { TDA10048_CONF_PLL2, 0x0a },
 168         { TDA10048_CONF_PLL3, 0x43 },
 169         { TDA10048_FREQ_PHY2_LSB, 0x02 },
 170         { TDA10048_FREQ_PHY2_MSB, 0x0a },
 171         { TDA10048_TIME_WREF_LSB, 0xbd },
 172         { TDA10048_TIME_WREF_MID1, 0xe4 },
 173         { TDA10048_TIME_WREF_MID2, 0xa8 },
 174         { TDA10048_TIME_WREF_MSB, 0x02 },
 175         { TDA10048_TIME_INVWREF_LSB, 0x04 },
 176         { TDA10048_TIME_INVWREF_MSB, 0x06 },
 177         { TDA10048_CONF_C4_1, 0x00 },
 178         { TDA10048_CONF_C1_1, 0xa8 },
 179         { TDA10048_AGC_CONF, 0x16 },
 180         { TDA10048_CONF_C1_3, 0x0b },
 181         { TDA10048_AGC_TUN_MIN, 0x00 },
 182         { TDA10048_AGC_TUN_MAX, 0xff },
 183         { TDA10048_AGC_IF_MIN, 0x00 },
 184         { TDA10048_AGC_IF_MAX, 0xff },
 185         { TDA10048_AGC_THRESHOLD_MSB, 0x00 },
 186         { TDA10048_AGC_THRESHOLD_LSB, 0x70 },
 187         { TDA10048_CVBER_CTRL, 0x38 },
 188         { TDA10048_AGC_GAINS, 0x12 },
 189         { TDA10048_CONF_XO, 0x00 },
 190         { TDA10048_CONF_TS1, 0x07 },
 191         { TDA10048_IC_MODE, 0x00 },
 192         { TDA10048_CONF_TS2, 0xc0 },
 193         { TDA10048_CONF_TRISTATE1, 0x21 },
 194         { TDA10048_CONF_TRISTATE2, 0x00 },
 195         { TDA10048_CONF_POLARITY, 0x00 },
 196         { TDA10048_CONF_C4_2, 0x04 },
 197         { TDA10048_CONF_ADC, 0x60 },
 198         { TDA10048_CONF_ADC_2, 0x10 },
 199         { TDA10048_CONF_ADC, 0x60 },
 200         { TDA10048_CONF_ADC_2, 0x00 },
 201         { TDA10048_CONF_C1_1, 0xa8 },
 202         { TDA10048_UNCOR_CTRL, 0x00 },
 203         { TDA10048_CONF_C4_2, 0x04 },
 204 };
 205
 206 static struct pll_tab {
 207         u32     clk_freq_khz;
 208         u32     if_freq_khz;
 209 } pll_tab[] = {
 210         { TDA10048_CLK_4000,  TDA10048_IF_36130 },
 211         { TDA10048_CLK_16000, TDA10048_IF_3300 },
 212         { TDA10048_CLK_16000, TDA10048_IF_3500 },
 213         { TDA10048_CLK_16000, TDA10048_IF_3800 },
 214         { TDA10048_CLK_16000, TDA10048_IF_4000 },
 215         { TDA10048_CLK_16000, TDA10048_IF_4300 },
 216         { TDA10048_CLK_16000, TDA10048_IF_4500 },
 217         { TDA10048_CLK_16000, TDA10048_IF_5000 },
 218         { TDA10048_CLK_16000, TDA10048_IF_36130 },
 219 };
 220
 221 static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
 222 {
 223         struct tda10048_config *config = &state->config;
 224         int ret;
 225         u8 buf[] = { reg, data };
 226         struct i2c_msg msg = {
 227                 .addr = config->demod_address,
 228                 .flags = 0, .buf = buf, .len = 2 };
 229
 230         dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
 231
 232         ret = i2c_transfer(state->i2c, &msg, 1);
 233
 234         if (ret != 1)
 235                 printk("%s: writereg error (ret == %i)\n", __func__, ret);
 236
 237         return (ret != 1) ? -1 : 0;
 238 }
 239
 240 static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
 241 {
 242         struct tda10048_config *config = &state->config;
 243         int ret;
 244         u8 b0[] = { reg };
 245         u8 b1[] = { 0 };
 246         struct i2c_msg msg[] = {
 247                 { .addr = config->demod_address,
 248                         .flags = 0, .buf = b0, .len = 1 },
 249                 { .addr = config->demod_address,
 250                         .flags = I2C_M_RD, .buf = b1, .len = 1 } };
 251
 252         dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
 253
 254         ret = i2c_transfer(state->i2c, msg, 2);
 255
 256         if (ret != 2)
 257                 printk(KERN_ERR "%s: readreg error (ret == %i)\n",
 258                         __func__, ret);
 259
 260         return b1[0];
 261 }
 262
 263 static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
 264                                  const u8 *data, u16 len)
 265 {
 266         struct tda10048_config *config = &state->config;
 267         int ret = -EREMOTEIO;
 268         struct i2c_msg msg;
 269         u8 *buf;
 270
 271         dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len);
 272
 273         buf = kmalloc(len + 1, GFP_KERNEL);
 274         if (buf == NULL) {
 275                 ret = -ENOMEM;
 276                 goto error;
 277         }
 278
 279         *buf = reg;
 280         memcpy(buf + 1, data, len);
 281
 282         msg.addr = config->demod_address;
 283         msg.flags = 0;
 284         msg.buf = buf;
 285         msg.len = len + 1;
 286
 287         dprintk(2, "%s():  write len = %d\n",
 288                 __func__, msg.len);
 289
 290         ret = i2c_transfer(state->i2c, &msg, 1);
 291         if (ret != 1) {
 292                 printk(KERN_ERR "%s(): writereg error err %i\n",
 293                          __func__, ret);
 294                 ret = -EREMOTEIO;
 295         }
 296
 297 error:
 298         kfree(buf);
 299
 300         return ret;
 301 }
 302
 303 static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
 304                              u32 if_hz)
 305 {
 306         struct tda10048_state *state = fe->demodulator_priv;
 307         u64 t;
 308
 309         dprintk(1, "%s()\n", __func__);
 310
 311         if (sample_freq_hz == 0)
 312                 return -EINVAL;
 313
 314         if (if_hz < (sample_freq_hz / 2)) {
 315                 /* PHY2 = (if2/fs) * 2^15 */
 316                 t = if_hz;
 317                 t *= 10;
 318                 t *= 32768;
 319                 do_div(t, sample_freq_hz);
 320                 t += 5;
 321                 do_div(t, 10);
 322         } else {
 323                 /* PHY2 = ((IF1-fs)/fs) * 2^15 */
 324                 t = sample_freq_hz - if_hz;
 325                 t *= 10;
 326                 t *= 32768;
 327                 do_div(t, sample_freq_hz);
 328                 t += 5;
 329                 do_div(t, 10);
 330                 t = ~t + 1;
 331         }
 332
 333         tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
 334         tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
 335
 336         return 0;
 337 }
 338
 339 static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
 340                              u32 bw)
 341 {
 342         struct tda10048_state *state = fe->demodulator_priv;
 343         u64 t, z;
 344         u32 b = 8000000;
 345
 346         dprintk(1, "%s()\n", __func__);
 347
 348         if (sample_freq_hz == 0)
 349                 return -EINVAL;
 350
 351         if (bw == BANDWIDTH_6_MHZ)
 352                 b = 6000000;
 353         else
 354         if (bw == BANDWIDTH_7_MHZ)
 355                 b = 7000000;
 356
 357         /* WREF = (B / (7 * fs)) * 2^31 */
 358         t = b * 10;
 359         /* avoid warning: this decimal constant is unsigned only in ISO C90 */
 360         /* t *= 2147483648 on 32bit platforms */
 361         t *= (2048 * 1024);
 362         t *= 1024;
 363         z = 7 * sample_freq_hz;
 364         do_div(t, z);
 365         t += 5;
 366         do_div(t, 10);
 367
 368         tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
 369         tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
 370         tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
 371         tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
 372
 373         return 0;
 374 }
 375
 376 static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
 377                                 u32 bw)
 378 {
 379         struct tda10048_state *state = fe->demodulator_priv;
 380         u64 t;
 381         u32 b = 8000000;
 382
 383         dprintk(1, "%s()\n", __func__);
 384
 385         if (sample_freq_hz == 0)
 386                 return -EINVAL;
 387
 388         if (bw == BANDWIDTH_6_MHZ)
 389                 b = 6000000;
 390         else
 391         if (bw == BANDWIDTH_7_MHZ)
 392                 b = 7000000;
 393
 394         /* INVWREF = ((7 * fs) / B) * 2^5 */
 395         t = sample_freq_hz;
 396         t *= 7;
 397         t *= 32;
 398         t *= 10;
 399         do_div(t, b);
 400         t += 5;
 401         do_div(t, 10);
 402
 403         tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
 404         tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
 405
 406         return 0;
 407 }
 408
 409 static int tda10048_set_bandwidth(struct dvb_frontend *fe,
 410         enum fe_bandwidth bw)
 411 {
 412         struct tda10048_state *state = fe->demodulator_priv;
 413         dprintk(1, "%s(bw=%d)\n", __func__, bw);
 414
 415         /* Bandwidth setting may need to be adjusted */
 416         switch (bw) {
 417         case BANDWIDTH_6_MHZ:
 418         case BANDWIDTH_7_MHZ:
 419         case BANDWIDTH_8_MHZ:
 420                 tda10048_set_wref(fe, state->sample_freq, bw);
 421                 tda10048_set_invwref(fe, state->sample_freq, bw);
 422                 break;
 423         default:
 424                 printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
 425                 return -EINVAL;
 426         }
 427
 428         state->bandwidth = bw;
 429
 430         return 0;
 431 }
 432
 433 static int tda10048_set_if(struct dvb_frontend *fe, enum fe_bandwidth bw)
 434 {
 435         struct tda10048_state *state = fe->demodulator_priv;
 436         struct tda10048_config *config = &state->config;
 437         int i;
 438         u32 if_freq_khz;
 439
 440         dprintk(1, "%s(bw = %d)\n", __func__, bw);
 441
 442         /* based on target bandwidth and clk we calculate pll factors */
 443         switch (bw) {
 444         case BANDWIDTH_6_MHZ:
 445                 if_freq_khz = config->dtv6_if_freq_khz;
 446                 break;
 447         case BANDWIDTH_7_MHZ:
 448                 if_freq_khz = config->dtv7_if_freq_khz;
 449                 break;
 450         case BANDWIDTH_8_MHZ:
 451                 if_freq_khz = config->dtv8_if_freq_khz;
 452                 break;
 453         default:
 454                 printk(KERN_ERR "%s() no default\n", __func__);
 455                 return -EINVAL;
 456         }
 457
 458         for (i = 0; i < ARRAY_SIZE(pll_tab); i++) {
 459                 if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) &&
 460                         (pll_tab[i].if_freq_khz == if_freq_khz)) {
 461
 462                         state->freq_if_hz = pll_tab[i].if_freq_khz * 1000;
 463                         state->xtal_hz = pll_tab[i].clk_freq_khz * 1000;
 464                         break;
 465                 }
 466         }
 467         if (i == ARRAY_SIZE(pll_tab)) {
 468                 printk(KERN_ERR "%s() Incorrect attach settings\n",
 469                         __func__);
 470                 return -EINVAL;
 471         }
 472
 473         dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
 474         dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
 475         dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
 476         dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
 477         dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
 478
 479         /* Calculate the sample frequency */
 480         state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
 481         state->sample_freq /= (state->pll_nfactor + 1);
 482         state->sample_freq /= (state->pll_pfactor + 4);
 483         dprintk(1, "- sample_freq = %d\n", state->sample_freq);
 484
 485         /* Update the I/F */
 486         tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz);
 487
 488         return 0;
 489 }
 490
 491 static int tda10048_firmware_upload(struct dvb_frontend *fe)
 492 {
 493         struct tda10048_state *state = fe->demodulator_priv;
 494         struct tda10048_config *config = &state->config;
 495         const struct firmware *fw;
 496         int ret;
 497         int pos = 0;
 498         int cnt;
 499         u8 wlen = config->fwbulkwritelen;
 500
 501         if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
 502                 wlen = TDA10048_BULKWRITE_200;
 503
 504         /* request the firmware, this will block and timeout */
 505         printk(KERN_INFO "%s: waiting for firmware upload (%s)...\n",
 506                 __func__,
 507                 TDA10048_DEFAULT_FIRMWARE);
 508
 509         ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
 510                 state->i2c->dev.parent);
 511         if (ret) {
 512                 printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
 513                         __func__);
 514                 return -EIO;
 515         } else {
 516                 printk(KERN_INFO "%s: firmware read %Zu bytes.\n",
 517                         __func__,
 518                         fw->size);
 519                 ret = 0;
 520         }
 521
 522         if (fw->size != TDA10048_DEFAULT_FIRMWARE_SIZE) {
 523                 printk(KERN_ERR "%s: firmware incorrect size\n", __func__);
 524                 ret = -EIO;
 525         } else {
 526                 printk(KERN_INFO "%s: firmware uploading\n", __func__);
 527
 528                 /* Soft reset */
 529                 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
 530                         tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
 531                                 & 0xfe);
 532                 tda10048_writereg(state, TDA10048_CONF_TRISTATE1,
 533                         tda10048_readreg(state, TDA10048_CONF_TRISTATE1)
 534                                 | 0x01);
 535
 536                 /* Put the demod into host download mode */
 537                 tda10048_writereg(state, TDA10048_CONF_C4_1,
 538                         tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xf9);
 539
 540                 /* Boot the DSP */
 541                 tda10048_writereg(state, TDA10048_CONF_C4_1,
 542                         tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x08);
 543
 544                 /* Prepare for download */
 545                 tda10048_writereg(state, TDA10048_DSP_CODE_CPT, 0);
 546
 547                 /* Download the firmware payload */
 548                 while (pos < fw->size) {
 549
 550                         if ((fw->size - pos) > wlen)
 551                                 cnt = wlen;
 552                         else
 553                                 cnt = fw->size - pos;
 554
 555                         tda10048_writeregbulk(state, TDA10048_DSP_CODE_IN,
 556                                 &fw->data[pos], cnt);
 557
 558                         pos += cnt;
 559                 }
 560
 561                 ret = -EIO;
 562                 /* Wait up to 250ms for the DSP to boot */
 563                 for (cnt = 0; cnt < 250 ; cnt += 10) {
 564
 565                         msleep(10);
 566
 567                         if (tda10048_readreg(state, TDA10048_SYNC_STATUS)
 568                                 & 0x40) {
 569                                 ret = 0;
 570                                 break;
 571                         }
 572                 }
 573         }
 574
 575         release_firmware(fw);
 576
 577         if (ret == 0) {
 578                 printk(KERN_INFO "%s: firmware uploaded\n", __func__);
 579                 state->fwloaded = 1;
 580         } else
 581                 printk(KERN_ERR "%s: firmware upload failed\n", __func__);
 582
 583         return ret;
 584 }
 585
 586 static int tda10048_set_inversion(struct dvb_frontend *fe, int inversion)
 587 {
 588         struct tda10048_state *state = fe->demodulator_priv;
 589
 590         dprintk(1, "%s(%d)\n", __func__, inversion);
 591
 592         if (inversion == TDA10048_INVERSION_ON)
 593                 tda10048_writereg(state, TDA10048_CONF_C1_1,
 594                         tda10048_readreg(state, TDA10048_CONF_C1_1) | 0x20);
 595         else
 596                 tda10048_writereg(state, TDA10048_CONF_C1_1,
 597                         tda10048_readreg(state, TDA10048_CONF_C1_1) & 0xdf);
 598
 599         return 0;
 600 }
 601
 602 /* Retrieve the demod settings */
 603 static int tda10048_get_tps(struct tda10048_state *state,
 604         struct dvb_ofdm_parameters *p)
 605 {
 606         u8 val;
 607
 608         /* Make sure the TPS regs are valid */
 609         if (!(tda10048_readreg(state, TDA10048_AUTO) & 0x01))
 610                 return -EAGAIN;
 611
 612         val = tda10048_readreg(state, TDA10048_OUT_CONF2);
 613         switch ((val & 0x60) >> 5) {
 614         case 0:
 615                 p->constellation = QPSK;
 616                 break;
 617         case 1:
 618                 p->constellation = QAM_16;
 619                 break;
 620         case 2:
 621                 p->constellation = QAM_64;
 622                 break;
 623         }
 624         switch ((val & 0x18) >> 3) {
 625         case 0:
 626                 p->hierarchy_information = HIERARCHY_NONE;
 627                 break;
 628         case 1:
 629                 p->hierarchy_information = HIERARCHY_1;
 630                 break;
 631         case 2:
 632                 p->hierarchy_information = HIERARCHY_2;
 633                 break;
 634         case 3:
 635                 p->hierarchy_information = HIERARCHY_4;
 636                 break;
 637         }
 638         switch (val & 0x07) {
 639         case 0:
 640                 p->code_rate_HP = FEC_1_2;
 641                 break;
 642         case 1:
 643                 p->code_rate_HP = FEC_2_3;
 644                 break;
 645         case 2:
 646                 p->code_rate_HP = FEC_3_4;
 647                 break;
 648         case 3:
 649                 p->code_rate_HP = FEC_5_6;
 650                 break;
 651         case 4:
 652                 p->code_rate_HP = FEC_7_8;
 653                 break;
 654         }
 655
 656         val = tda10048_readreg(state, TDA10048_OUT_CONF3);
 657         switch (val & 0x07) {
 658         case 0:
 659                 p->code_rate_LP = FEC_1_2;
 660                 break;
 661         case 1:
 662                 p->code_rate_LP = FEC_2_3;
 663                 break;
 664         case 2:
 665                 p->code_rate_LP = FEC_3_4;
 666                 break;
 667         case 3:
 668                 p->code_rate_LP = FEC_5_6;
 669                 break;
 670         case 4:
 671                 p->code_rate_LP = FEC_7_8;
 672                 break;
 673         }
 674
 675         val = tda10048_readreg(state, TDA10048_OUT_CONF1);
 676         switch ((val & 0x0c) >> 2) {
 677         case 0:
 678                 p->guard_interval = GUARD_INTERVAL_1_32;
 679                 break;
 680         case 1:
 681                 p->guard_interval = GUARD_INTERVAL_1_16;
 682                 break;
 683         case 2:
 684                 p->guard_interval =  GUARD_INTERVAL_1_8;
 685                 break;
 686         case 3:
 687                 p->guard_interval =  GUARD_INTERVAL_1_4;
 688                 break;
 689         }
 690         switch (val & 0x03) {
 691         case 0:
 692                 p->transmission_mode = TRANSMISSION_MODE_2K;
 693                 break;
 694         case 1:
 695                 p->transmission_mode = TRANSMISSION_MODE_8K;
 696                 break;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 703 {
 704         struct tda10048_state *state = fe->demodulator_priv;
 705         struct tda10048_config *config = &state->config;
 706         dprintk(1, "%s(%d)\n", __func__, enable);
 707
 708         if (config->disable_gate_access)
 709                 return 0;
 710
 711         if (enable)
 712                 return tda10048_writereg(state, TDA10048_CONF_C4_1,
 713                         tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
 714         else
 715                 return tda10048_writereg(state, TDA10048_CONF_C4_1,
 716                         tda10048_readreg(state, TDA10048_CONF_C4_1) & 0xfd);
 717 }
 718
 719 static int tda10048_output_mode(struct dvb_frontend *fe, int serial)
 720 {
 721         struct tda10048_state *state = fe->demodulator_priv;
 722         dprintk(1, "%s(%d)\n", __func__, serial);
 723
 724         /* Ensure pins are out of tri-state */
 725         tda10048_writereg(state, TDA10048_CONF_TRISTATE1, 0x21);
 726         tda10048_writereg(state, TDA10048_CONF_TRISTATE2, 0x00);
 727
 728         if (serial) {
 729                 tda10048_writereg(state, TDA10048_IC_MODE, 0x80 | 0x20);
 730                 tda10048_writereg(state, TDA10048_CONF_TS2, 0xc0);
 731         } else {
 732                 tda10048_writereg(state, TDA10048_IC_MODE, 0x00);
 733                 tda10048_writereg(state, TDA10048_CONF_TS2, 0x01);
 734         }
 735
 736         return 0;
 737 }
 738
 739 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
 740 /* TODO: Support manual tuning with specific params */
 741 static int tda10048_set_frontend(struct dvb_frontend *fe,
 742         struct dvb_frontend_parameters *p)
 743 {
 744         struct tda10048_state *state = fe->demodulator_priv;
 745
 746         dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
 747
 748         /* Update the I/F pll's if the bandwidth changes */
 749         if (p->u.ofdm.bandwidth != state->bandwidth) {
 750                 tda10048_set_if(fe, p->u.ofdm.bandwidth);
 751                 tda10048_set_bandwidth(fe, p->u.ofdm.bandwidth);
 752         }
 753
 754         if (fe->ops.tuner_ops.set_params) {
 755
 756                 if (fe->ops.i2c_gate_ctrl)
 757                         fe->ops.i2c_gate_ctrl(fe, 1);
 758
 759                 fe->ops.tuner_ops.set_params(fe, p);
 760
 761                 if (fe->ops.i2c_gate_ctrl)
 762                         fe->ops.i2c_gate_ctrl(fe, 0);
 763         }
 764
 765         /* Enable demod TPS auto detection and begin acquisition */
 766         tda10048_writereg(state, TDA10048_AUTO, 0x57);
 767         /* trigger cber and vber acquisition */
 768         tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x3B);
 769
 770         return 0;
 771 }
 772
 773 /* Establish sane defaults and load firmware. */
 774 static int tda10048_init(struct dvb_frontend *fe)
 775 {
 776         struct tda10048_state *state = fe->demodulator_priv;
 777         struct tda10048_config *config = &state->config;
 778         int ret = 0, i;
 779
 780         dprintk(1, "%s()\n", __func__);
 781
 782         /* PLL */
 783         init_tab[4].data = (u8)(state->pll_mfactor);
 784         init_tab[5].data = (u8)(state->pll_nfactor) | 0x40;
 785
 786         /* Apply register defaults */
 787         for (i = 0; i < ARRAY_SIZE(init_tab); i++)
 788                 tda10048_writereg(state, init_tab[i].reg, init_tab[i].data);
 789
 790         if (state->fwloaded == 0)
 791                 ret = tda10048_firmware_upload(fe);
 792
 793         /* Set either serial or parallel */
 794         tda10048_output_mode(fe, config->output_mode);
 795
 796         /* Set inversion */
 797         tda10048_set_inversion(fe, config->inversion);
 798
 799         /* Establish default RF values */
 800         tda10048_set_if(fe, BANDWIDTH_8_MHZ);
 801         tda10048_set_bandwidth(fe, BANDWIDTH_8_MHZ);
 802
 803         /* Ensure we leave the gate closed */
 804         tda10048_i2c_gate_ctrl(fe, 0);
 805
 806         return ret;
 807 }
 808
 809 static int tda10048_read_status(struct dvb_frontend *fe, fe_status_t *status)
 810 {
 811         struct tda10048_state *state = fe->demodulator_priv;
 812         u8 reg;
 813
 814         *status = 0;
 815
 816         reg = tda10048_readreg(state, TDA10048_SYNC_STATUS);
 817
 818         dprintk(1, "%s() status =0x%02x\n", __func__, reg);
 819
 820         if (reg & 0x02)
 821                 *status |= FE_HAS_CARRIER;
 822
 823         if (reg & 0x04)
 824                 *status |= FE_HAS_SIGNAL;
 825
 826         if (reg & 0x08) {
 827                 *status |= FE_HAS_LOCK;
 828                 *status |= FE_HAS_VITERBI;
 829                 *status |= FE_HAS_SYNC;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int tda10048_read_ber(struct dvb_frontend *fe, u32 *ber)
 836 {
 837         struct tda10048_state *state = fe->demodulator_priv;
 838         static u32 cber_current;
 839         u32 cber_nmax;
 840         u64 cber_tmp;
 841
 842         dprintk(1, "%s()\n", __func__);
 843
 844         /* update cber on interrupt */
 845         if (tda10048_readreg(state, TDA10048_SOFT_IT_C3) & 0x01) {
 846                 cber_tmp = tda10048_readreg(state, TDA10048_CBER_MSB) << 8 |
 847                         tda10048_readreg(state, TDA10048_CBER_LSB);
 848                 cber_nmax = tda10048_readreg(state, TDA10048_CBER_NMAX_MSB) << 8 |
 849                         tda10048_readreg(state, TDA10048_CBER_NMAX_LSB);
 850                 cber_tmp *= 100000000;
 851                 cber_tmp *= 2;
 852                 cber_tmp = div_u64(cber_tmp, (cber_nmax * 32) + 1);
 853                 cber_current = (u32)cber_tmp;
 854                 /* retrigger cber acquisition */
 855                 tda10048_writereg(state, TDA10048_CVBER_CTRL, 0x39);
 856         }
 857         /* actual cber is (*ber)/1e8 */
 858         *ber = cber_current;
 859
 860         return 0;
 861 }
 862
 863 static int tda10048_read_signal_strength(struct dvb_frontend *fe,
 864         u16 *signal_strength)
 865 {
 866         struct tda10048_state *state = fe->demodulator_priv;
 867         u8 v;
 868
 869         dprintk(1, "%s()\n", __func__);
 870
 871         *signal_strength = 65535;
 872
 873         v = tda10048_readreg(state, TDA10048_NP_OUT);
 874         if (v > 0)
 875                 *signal_strength -= (v << 8) | v;
 876
 877         return 0;
 878 }
 879
 880 /* SNR lookup table */
 881 static struct snr_tab {
 882         u8 val;
 883         u8 data;
 884 } snr_tab[] = {
 885         {   0,   0 },
 886         {   1, 246 },
 887         {   2, 215 },
 888         {   3, 198 },
 889         {   4, 185 },
 890         {   5, 176 },
 891         {   6, 168 },
 892         {   7, 161 },
 893         {   8, 155 },
 894         {   9, 150 },
 895         {  10, 146 },
 896         {  11, 141 },
 897         {  12, 138 },
 898         {  13, 134 },
 899         {  14, 131 },
 900         {  15, 128 },
 901         {  16, 125 },
 902         {  17, 122 },
 903         {  18, 120 },
 904         {  19, 118 },
 905         {  20, 115 },
 906         {  21, 113 },
 907         {  22, 111 },
 908         {  23, 109 },
 909         {  24, 107 },
 910         {  25, 106 },
 911         {  26, 104 },
 912         {  27, 102 },
 913         {  28, 101 },
 914         {  29,  99 },
 915         {  30,  98 },
 916         {  31,  96 },
 917         {  32,  95 },
 918         {  33,  94 },
 919         {  34,  92 },
 920         {  35,  91 },
 921         {  36,  90 },
 922         {  37,  89 },
 923         {  38,  88 },
 924         {  39,  86 },
 925         {  40,  85 },
 926         {  41,  84 },
 927         {  42,  83 },
 928         {  43,  82 },
 929         {  44,  81 },
 930         {  45,  80 },
 931         {  46,  79 },
 932         {  47,  78 },
 933         {  48,  77 },
 934         {  49,  76 },
 935         {  50,  76 },
 936         {  51,  75 },
 937         {  52,  74 },
 938         {  53,  73 },
 939         {  54,  72 },
 940         {  56,  71 },
 941         {  57,  70 },
 942         {  58,  69 },
 943         {  60,  68 },
 944         {  61,  67 },
 945         {  63,  66 },
 946         {  64,  65 },
 947         {  66,  64 },
 948         {  67,  63 },
 949         {  68,  62 },
 950         {  69,  62 },
 951         {  70,  61 },
 952         {  72,  60 },
 953         {  74,  59 },
 954         {  75,  58 },
 955         {  77,  57 },
 956         {  79,  56 },
 957         {  81,  55 },
 958         {  83,  54 },
 959         {  85,  53 },
 960         {  87,  52 },
 961         {  89,  51 },
 962         {  91,  50 },
 963         {  93,  49 },
 964         {  95,  48 },
 965         {  97,  47 },
 966         { 100,  46 },
 967         { 102,  45 },
 968         { 104,  44 },
 969         { 107,  43 },
 970         { 109,  42 },
 971         { 112,  41 },
 972         { 114,  40 },
 973         { 117,  39 },
 974         { 120,  38 },
 975         { 123,  37 },
 976         { 125,  36 },
 977         { 128,  35 },
 978         { 131,  34 },
 979         { 134,  33 },
 980         { 138,  32 },
 981         { 141,  31 },
 982         { 144,  30 },
 983         { 147,  29 },
 984         { 151,  28 },
 985         { 154,  27 },
 986         { 158,  26 },
 987         { 162,  25 },
 988         { 165,  24 },
 989         { 169,  23 },
 990         { 173,  22 },
 991         { 177,  21 },
 992         { 181,  20 },
 993         { 186,  19 },
 994         { 190,  18 },
 995         { 194,  17 },
 996         { 199,  16 },
 997         { 204,  15 },
 998         { 208,  14 },
 999         { 213,  13 },
1000         { 218,  12 },
1001         { 223,  11 },
1002         { 229,  10 },
1003         { 234,   9 },
1004         { 239,   8 },
1005         { 245,   7 },
1006         { 251,   6 },
1007         { 255,   5 },
1008 };
1009
1010 static int tda10048_read_snr(struct dvb_frontend *fe, u16 *snr)
1011 {
1012         struct tda10048_state *state = fe->demodulator_priv;
1013         u8 v;
1014         int i, ret = -EINVAL;
1015
1016         dprintk(1, "%s()\n", __func__);
1017
1018         v = tda10048_readreg(state, TDA10048_NP_OUT);
1019         for (i = 0; i < ARRAY_SIZE(snr_tab); i++) {
1020                 if (v <= snr_tab[i].val) {
1021                         *snr = snr_tab[i].data;
1022                         ret = 0;
1023                         break;
1024                 }
1025         }
1026
1027         return ret;
1028 }
1029
1030 static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1031 {
1032         struct tda10048_state *state = fe->demodulator_priv;
1033
1034         dprintk(1, "%s()\n", __func__);
1035
1036         *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 |
1037                 tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB);
1038         /* clear the uncorrected TS packets counter when saturated */
1039         if (*ucblocks == 0xFFFF)
1040                 tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80);
1041
1042         return 0;
1043 }
1044
1045 static int tda10048_get_frontend(struct dvb_frontend *fe,
1046         struct dvb_frontend_parameters *p)
1047 {
1048         struct tda10048_state *state = fe->demodulator_priv;
1049
1050         dprintk(1, "%s()\n", __func__);
1051
1052         p->inversion = tda10048_readreg(state, TDA10048_CONF_C1_1)
1053                 & 0x20 ? INVERSION_ON : INVERSION_OFF;
1054
1055         return tda10048_get_tps(state, &p->u.ofdm);
1056 }
1057
1058 static int tda10048_get_tune_settings(struct dvb_frontend *fe,
1059         struct dvb_frontend_tune_settings *tune)
1060 {
1061         tune->min_delay_ms = 1000;
1062         return 0;
1063 }
1064
1065 static void tda10048_release(struct dvb_frontend *fe)
1066 {
1067         struct tda10048_state *state = fe->demodulator_priv;
1068         dprintk(1, "%s()\n", __func__);
1069         kfree(state);
1070 }
1071
1072 static void tda10048_establish_defaults(struct dvb_frontend *fe)
1073 {
1074         struct tda10048_state *state = fe->demodulator_priv;
1075         struct tda10048_config *config = &state->config;
1076
1077         /* Validate/default the config */
1078         if (config->dtv6_if_freq_khz == 0) {
1079                 config->dtv6_if_freq_khz = TDA10048_IF_4300;
1080                 printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz "
1081                         "is not set (defaulting to %d)\n",
1082                         __func__,
1083                         config->dtv6_if_freq_khz);
1084         }
1085
1086         if (config->dtv7_if_freq_khz == 0) {
1087                 config->dtv7_if_freq_khz = TDA10048_IF_4300;
1088                 printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz "
1089                         "is not set (defaulting to %d)\n",
1090                         __func__,
1091                         config->dtv7_if_freq_khz);
1092         }
1093
1094         if (config->dtv8_if_freq_khz == 0) {
1095                 config->dtv8_if_freq_khz = TDA10048_IF_4300;
1096                 printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz "
1097                         "is not set (defaulting to %d)\n",
1098                         __func__,
1099                         config->dtv8_if_freq_khz);
1100         }
1101
1102         if (config->clk_freq_khz == 0) {
1103                 config->clk_freq_khz = TDA10048_CLK_16000;
1104                 printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz "
1105                         "is not set (defaulting to %d)\n",
1106                         __func__,
1107                         config->clk_freq_khz);
1108         }
1109 }
1110
1111 static struct dvb_frontend_ops tda10048_ops;
1112
1113 struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
1114         struct i2c_adapter *i2c)
1115 {
1116         struct tda10048_state *state = NULL;
1117
1118         dprintk(1, "%s()\n", __func__);
1119
1120         /* allocate memory for the internal state */
1121         state = kzalloc(sizeof(struct tda10048_state), GFP_KERNEL);
1122         if (state == NULL)
1123                 goto error;
1124
1125         /* setup the state and clone the config */
1126         memcpy(&state->config, config, sizeof(*config));
1127         state->i2c = i2c;
1128         state->fwloaded = config->no_firmware;
1129         state->bandwidth = BANDWIDTH_8_MHZ;
1130
1131         /* check if the demod is present */
1132         if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
1133                 goto error;
1134
1135         /* create dvb_frontend */
1136         memcpy(&state->frontend.ops, &tda10048_ops,
1137                 sizeof(struct dvb_frontend_ops));
1138         state->frontend.demodulator_priv = state;
1139
1140         /* set pll */
1141         if (config->set_pll) {
1142                 state->pll_mfactor = config->pll_m;
1143                 state->pll_nfactor = config->pll_n;
1144                 state->pll_pfactor = config->pll_p;
1145         } else {
1146                 state->pll_mfactor = 10;
1147                 state->pll_nfactor = 3;
1148                 state->pll_pfactor = 0;
1149         }
1150
1151         /* Establish any defaults the the user didn't pass */
1152         tda10048_establish_defaults(&state->frontend);
1153
1154         /* Set the xtal and freq defaults */
1155         if (tda10048_set_if(&state->frontend, BANDWIDTH_8_MHZ) != 0)
1156                 goto error;
1157
1158         /* Default bandwidth */
1159         if (tda10048_set_bandwidth(&state->frontend, BANDWIDTH_8_MHZ) != 0)
1160                 goto error;
1161
1162         /* Leave the gate closed */
1163         tda10048_i2c_gate_ctrl(&state->frontend, 0);
1164
1165         return &state->frontend;
1166
1167 error:
1168         kfree(state);
1169         return NULL;
1170 }
1171 EXPORT_SYMBOL(tda10048_attach);
1172
1173 static struct dvb_frontend_ops tda10048_ops = {
1174
1175         .info = {
1176                 .name                   = "NXP TDA10048HN DVB-T",
1177                 .type                   = FE_OFDM,
1178                 .frequency_min          = 177000000,
1179                 .frequency_max          = 858000000,
1180                 .frequency_stepsize     = 166666,
1181                 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1182                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1183                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1184                 FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
1185                 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
1186         },
1187
1188         .release = tda10048_release,
1189         .init = tda10048_init,
1190         .i2c_gate_ctrl = tda10048_i2c_gate_ctrl,
1191         .set_frontend = tda10048_set_frontend,
1192         .get_frontend = tda10048_get_frontend,
1193         .get_tune_settings = tda10048_get_tune_settings,
1194         .read_status = tda10048_read_status,
1195         .read_ber = tda10048_read_ber,
1196         .read_signal_strength = tda10048_read_signal_strength,
1197         .read_snr = tda10048_read_snr,
1198         .read_ucblocks = tda10048_read_ucblocks,
1199 };
1200
1201 module_param(debug, int, 0644);
1202 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
1203
1204 MODULE_DESCRIPTION("NXP TDA10048HN DVB-T Demodulator driver");
1205 MODULE_AUTHOR("Steven Toth");
1206 MODULE_LICENSE("GPL");