drivers/mfd/rtsx_pcr.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  */
  21
  22 #include <linux/pci.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/highmem.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/idr.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/mfd/core.h>
  32 #include <linux/mfd/rtsx_pci.h>
  33 #include <asm/unaligned.h>
  34
  35 #include "rtsx_pcr.h"
  36
  37 static bool msi_en = true;
  38 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  39 MODULE_PARM_DESC(msi_en, "Enable MSI");
  40
  41 static DEFINE_IDR(rtsx_pci_idr);
  42 static DEFINE_SPINLOCK(rtsx_pci_lock);
  43
  44 static struct mfd_cell rtsx_pcr_cells[] = {
  45         [RTSX_SD_CARD] = {
  46                 .name = DRV_NAME_RTSX_PCI_SDMMC,
  47         },
  48         [RTSX_MS_CARD] = {
  49                 .name = DRV_NAME_RTSX_PCI_MS,
  50         },
  51 };
  52
  53 static const struct pci_device_id rtsx_pci_ids[] = {
  54         { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  55         { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56         { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57         { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58         { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  59         { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  60         { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  61         { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  62         { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  63         { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  64         { 0, }
  65 };
  66
  67 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  68
  69 static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
  70 {
  71         rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
  72                 0xFC, pcr->aspm_en);
  73 }
  74
  75 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
  76 {
  77         rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
  78                 0xFC, 0);
  79 }
  80
  81 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  82 {
  83         /* If pci device removed, don't queue idle work any more */
  84         if (pcr->remove_pci)
  85                 return;
  86
  87         if (pcr->state != PDEV_STAT_RUN) {
  88                 pcr->state = PDEV_STAT_RUN;
  89                 if (pcr->ops->enable_auto_blink)
  90                         pcr->ops->enable_auto_blink(pcr);
  91
  92                 if (pcr->aspm_en)
  93                         rtsx_pci_disable_aspm(pcr);
  94         }
  95
  96         mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  97 }
  98 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  99
 100 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
 101 {
 102         int i;
 103         u32 val = HAIMR_WRITE_START;
 104
 105         val |= (u32)(addr & 0x3FFF) << 16;
 106         val |= (u32)mask << 8;
 107         val |= (u32)data;
 108
 109         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 110
 111         for (i = 0; i < MAX_RW_REG_CNT; i++) {
 112                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 113                 if ((val & HAIMR_TRANS_END) == 0) {
 114                         if (data != (u8)val)
 115                                 return -EIO;
 116                         return 0;
 117                 }
 118         }
 119
 120         return -ETIMEDOUT;
 121 }
 122 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 123
 124 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 125 {
 126         u32 val = HAIMR_READ_START;
 127         int i;
 128
 129         val |= (u32)(addr & 0x3FFF) << 16;
 130         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 131
 132         for (i = 0; i < MAX_RW_REG_CNT; i++) {
 133                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 134                 if ((val & HAIMR_TRANS_END) == 0)
 135                         break;
 136         }
 137
 138         if (i >= MAX_RW_REG_CNT)
 139                 return -ETIMEDOUT;
 140
 141         if (data)
 142                 *data = (u8)(val & 0xFF);
 143
 144         return 0;
 145 }
 146 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 147
 148 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 149 {
 150         int err, i, finished = 0;
 151         u8 tmp;
 152
 153         rtsx_pci_init_cmd(pcr);
 154
 155         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
 156         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
 157         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 158         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
 159
 160         err = rtsx_pci_send_cmd(pcr, 100);
 161         if (err < 0)
 162                 return err;
 163
 164         for (i = 0; i < 100000; i++) {
 165                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 166                 if (err < 0)
 167                         return err;
 168
 169                 if (!(tmp & 0x80)) {
 170                         finished = 1;
 171                         break;
 172                 }
 173         }
 174
 175         if (!finished)
 176                 return -ETIMEDOUT;
 177
 178         return 0;
 179 }
 180
 181 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 182 {
 183         if (pcr->ops->write_phy)
 184                 return pcr->ops->write_phy(pcr, addr, val);
 185
 186         return __rtsx_pci_write_phy_register(pcr, addr, val);
 187 }
 188 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 189
 190 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 191 {
 192         int err, i, finished = 0;
 193         u16 data;
 194         u8 *ptr, tmp;
 195
 196         rtsx_pci_init_cmd(pcr);
 197
 198         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 199         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
 200
 201         err = rtsx_pci_send_cmd(pcr, 100);
 202         if (err < 0)
 203                 return err;
 204
 205         for (i = 0; i < 100000; i++) {
 206                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 207                 if (err < 0)
 208                         return err;
 209
 210                 if (!(tmp & 0x80)) {
 211                         finished = 1;
 212                         break;
 213                 }
 214         }
 215
 216         if (!finished)
 217                 return -ETIMEDOUT;
 218
 219         rtsx_pci_init_cmd(pcr);
 220
 221         rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
 222         rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
 223
 224         err = rtsx_pci_send_cmd(pcr, 100);
 225         if (err < 0)
 226                 return err;
 227
 228         ptr = rtsx_pci_get_cmd_data(pcr);
 229         data = ((u16)ptr[1] << 8) | ptr[0];
 230
 231         if (val)
 232                 *val = data;
 233
 234         return 0;
 235 }
 236
 237 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 238 {
 239         if (pcr->ops->read_phy)
 240                 return pcr->ops->read_phy(pcr, addr, val);
 241
 242         return __rtsx_pci_read_phy_register(pcr, addr, val);
 243 }
 244 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 245
 246 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 247 {
 248         rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 249         rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 250
 251         rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 252         rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 253 }
 254 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 255
 256 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 257                 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 258 {
 259         unsigned long flags;
 260         u32 val = 0;
 261         u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 262
 263         val |= (u32)(cmd_type & 0x03) << 30;
 264         val |= (u32)(reg_addr & 0x3FFF) << 16;
 265         val |= (u32)mask << 8;
 266         val |= (u32)data;
 267
 268         spin_lock_irqsave(&pcr->lock, flags);
 269         ptr += pcr->ci;
 270         if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 271                 put_unaligned_le32(val, ptr);
 272                 ptr++;
 273                 pcr->ci++;
 274         }
 275         spin_unlock_irqrestore(&pcr->lock, flags);
 276 }
 277 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 278
 279 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 280 {
 281         u32 val = 1 << 31;
 282
 283         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 284
 285         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 286         /* Hardware Auto Response */
 287         val |= 0x40000000;
 288         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 289 }
 290 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 291
 292 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 293 {
 294         struct completion trans_done;
 295         u32 val = 1 << 31;
 296         long timeleft;
 297         unsigned long flags;
 298         int err = 0;
 299
 300         spin_lock_irqsave(&pcr->lock, flags);
 301
 302         /* set up data structures for the wakeup system */
 303         pcr->done = &trans_done;
 304         pcr->trans_result = TRANS_NOT_READY;
 305         init_completion(&trans_done);
 306
 307         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 308
 309         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 310         /* Hardware Auto Response */
 311         val |= 0x40000000;
 312         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 313
 314         spin_unlock_irqrestore(&pcr->lock, flags);
 315
 316         /* Wait for TRANS_OK_INT */
 317         timeleft = wait_for_completion_interruptible_timeout(
 318                         &trans_done, msecs_to_jiffies(timeout));
 319         if (timeleft <= 0) {
 320                 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
 321                 err = -ETIMEDOUT;
 322                 goto finish_send_cmd;
 323         }
 324
 325         spin_lock_irqsave(&pcr->lock, flags);
 326         if (pcr->trans_result == TRANS_RESULT_FAIL)
 327                 err = -EINVAL;
 328         else if (pcr->trans_result == TRANS_RESULT_OK)
 329                 err = 0;
 330         else if (pcr->trans_result == TRANS_NO_DEVICE)
 331                 err = -ENODEV;
 332         spin_unlock_irqrestore(&pcr->lock, flags);
 333
 334 finish_send_cmd:
 335         spin_lock_irqsave(&pcr->lock, flags);
 336         pcr->done = NULL;
 337         spin_unlock_irqrestore(&pcr->lock, flags);
 338
 339         if ((err < 0) && (err != -ENODEV))
 340                 rtsx_pci_stop_cmd(pcr);
 341
 342         if (pcr->finish_me)
 343                 complete(pcr->finish_me);
 344
 345         return err;
 346 }
 347 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 348
 349 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 350                 dma_addr_t addr, unsigned int len, int end)
 351 {
 352         u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 353         u64 val;
 354         u8 option = SG_VALID | SG_TRANS_DATA;
 355
 356         pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
 357
 358         if (end)
 359                 option |= SG_END;
 360         val = ((u64)addr << 32) | ((u64)len << 12) | option;
 361
 362         put_unaligned_le64(val, ptr);
 363         pcr->sgi++;
 364 }
 365
 366 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 367                 int num_sg, bool read, int timeout)
 368 {
 369         int err = 0, count;
 370
 371         pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
 372         count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
 373         if (count < 1)
 374                 return -EINVAL;
 375         pcr_dbg(pcr, "DMA mapping count: %d\n", count);
 376
 377         err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
 378
 379         rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
 380
 381         return err;
 382 }
 383 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 384
 385 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 386                 int num_sg, bool read)
 387 {
 388         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 389
 390         if (pcr->remove_pci)
 391                 return -EINVAL;
 392
 393         if ((sglist == NULL) || (num_sg <= 0))
 394                 return -EINVAL;
 395
 396         return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
 397 }
 398 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
 399
 400 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 401                 int num_sg, bool read)
 402 {
 403         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 404
 405         dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
 406 }
 407 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
 408
 409 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 410                 int count, bool read, int timeout)
 411 {
 412         struct completion trans_done;
 413         struct scatterlist *sg;
 414         dma_addr_t addr;
 415         long timeleft;
 416         unsigned long flags;
 417         unsigned int len;
 418         int i, err = 0;
 419         u32 val;
 420         u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
 421
 422         if (pcr->remove_pci)
 423                 return -ENODEV;
 424
 425         if ((sglist == NULL) || (count < 1))
 426                 return -EINVAL;
 427
 428         val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 429         pcr->sgi = 0;
 430         for_each_sg(sglist, sg, count, i) {
 431                 addr = sg_dma_address(sg);
 432                 len = sg_dma_len(sg);
 433                 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 434         }
 435
 436         spin_lock_irqsave(&pcr->lock, flags);
 437
 438         pcr->done = &trans_done;
 439         pcr->trans_result = TRANS_NOT_READY;
 440         init_completion(&trans_done);
 441         rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 442         rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 443
 444         spin_unlock_irqrestore(&pcr->lock, flags);
 445
 446         timeleft = wait_for_completion_interruptible_timeout(
 447                         &trans_done, msecs_to_jiffies(timeout));
 448         if (timeleft <= 0) {
 449                 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
 450                 err = -ETIMEDOUT;
 451                 goto out;
 452         }
 453
 454         spin_lock_irqsave(&pcr->lock, flags);
 455         if (pcr->trans_result == TRANS_RESULT_FAIL)
 456                 err = -EINVAL;
 457         else if (pcr->trans_result == TRANS_NO_DEVICE)
 458                 err = -ENODEV;
 459         spin_unlock_irqrestore(&pcr->lock, flags);
 460
 461 out:
 462         spin_lock_irqsave(&pcr->lock, flags);
 463         pcr->done = NULL;
 464         spin_unlock_irqrestore(&pcr->lock, flags);
 465
 466         if ((err < 0) && (err != -ENODEV))
 467                 rtsx_pci_stop_cmd(pcr);
 468
 469         if (pcr->finish_me)
 470                 complete(pcr->finish_me);
 471
 472         return err;
 473 }
 474 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
 475
 476 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 477 {
 478         int err;
 479         int i, j;
 480         u16 reg;
 481         u8 *ptr;
 482
 483         if (buf_len > 512)
 484                 buf_len = 512;
 485
 486         ptr = buf;
 487         reg = PPBUF_BASE2;
 488         for (i = 0; i < buf_len / 256; i++) {
 489                 rtsx_pci_init_cmd(pcr);
 490
 491                 for (j = 0; j < 256; j++)
 492                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 493
 494                 err = rtsx_pci_send_cmd(pcr, 250);
 495                 if (err < 0)
 496                         return err;
 497
 498                 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 499                 ptr += 256;
 500         }
 501
 502         if (buf_len % 256) {
 503                 rtsx_pci_init_cmd(pcr);
 504
 505                 for (j = 0; j < buf_len % 256; j++)
 506                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 507
 508                 err = rtsx_pci_send_cmd(pcr, 250);
 509                 if (err < 0)
 510                         return err;
 511         }
 512
 513         memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 514
 515         return 0;
 516 }
 517 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 518
 519 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 520 {
 521         int err;
 522         int i, j;
 523         u16 reg;
 524         u8 *ptr;
 525
 526         if (buf_len > 512)
 527                 buf_len = 512;
 528
 529         ptr = buf;
 530         reg = PPBUF_BASE2;
 531         for (i = 0; i < buf_len / 256; i++) {
 532                 rtsx_pci_init_cmd(pcr);
 533
 534                 for (j = 0; j < 256; j++) {
 535                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 536                                         reg++, 0xFF, *ptr);
 537                         ptr++;
 538                 }
 539
 540                 err = rtsx_pci_send_cmd(pcr, 250);
 541                 if (err < 0)
 542                         return err;
 543         }
 544
 545         if (buf_len % 256) {
 546                 rtsx_pci_init_cmd(pcr);
 547
 548                 for (j = 0; j < buf_len % 256; j++) {
 549                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 550                                         reg++, 0xFF, *ptr);
 551                         ptr++;
 552                 }
 553
 554                 err = rtsx_pci_send_cmd(pcr, 250);
 555                 if (err < 0)
 556                         return err;
 557         }
 558
 559         return 0;
 560 }
 561 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 562
 563 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 564 {
 565         int err;
 566
 567         rtsx_pci_init_cmd(pcr);
 568
 569         while (*tbl & 0xFFFF0000) {
 570                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 571                                 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 572                 tbl++;
 573         }
 574
 575         return rtsx_pci_send_cmd(pcr, 100);
 576 }
 577
 578 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 579 {
 580         const u32 *tbl;
 581
 582         if (card == RTSX_SD_CARD)
 583                 tbl = pcr->sd_pull_ctl_enable_tbl;
 584         else if (card == RTSX_MS_CARD)
 585                 tbl = pcr->ms_pull_ctl_enable_tbl;
 586         else
 587                 return -EINVAL;
 588
 589         return rtsx_pci_set_pull_ctl(pcr, tbl);
 590 }
 591 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 592
 593 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 594 {
 595         const u32 *tbl;
 596
 597         if (card == RTSX_SD_CARD)
 598                 tbl = pcr->sd_pull_ctl_disable_tbl;
 599         else if (card == RTSX_MS_CARD)
 600                 tbl = pcr->ms_pull_ctl_disable_tbl;
 601         else
 602                 return -EINVAL;
 603
 604
 605         return rtsx_pci_set_pull_ctl(pcr, tbl);
 606 }
 607 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 608
 609 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 610 {
 611         pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
 612
 613         if (pcr->num_slots > 1)
 614                 pcr->bier |= MS_INT_EN;
 615
 616         /* Enable Bus Interrupt */
 617         rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 618
 619         pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
 620 }
 621
 622 static inline u8 double_ssc_depth(u8 depth)
 623 {
 624         return ((depth > 1) ? (depth - 1) : depth);
 625 }
 626
 627 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 628 {
 629         if (div > CLK_DIV_1) {
 630                 if (ssc_depth > (div - 1))
 631                         ssc_depth -= (div - 1);
 632                 else
 633                         ssc_depth = SSC_DEPTH_4M;
 634         }
 635
 636         return ssc_depth;
 637 }
 638
 639 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 640                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 641 {
 642         int err, clk;
 643         u8 n, clk_divider, mcu_cnt, div;
 644         u8 depth[] = {
 645                 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 646                 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 647                 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 648                 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 649                 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 650         };
 651
 652         if (initial_mode) {
 653                 /* We use 250k(around) here, in initial stage */
 654                 clk_divider = SD_CLK_DIVIDE_128;
 655                 card_clock = 30000000;
 656         } else {
 657                 clk_divider = SD_CLK_DIVIDE_0;
 658         }
 659         err = rtsx_pci_write_register(pcr, SD_CFG1,
 660                         SD_CLK_DIVIDE_MASK, clk_divider);
 661         if (err < 0)
 662                 return err;
 663
 664         card_clock /= 1000000;
 665         pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
 666
 667         clk = card_clock;
 668         if (!initial_mode && double_clk)
 669                 clk = card_clock * 2;
 670         pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 671                 clk, pcr->cur_clock);
 672
 673         if (clk == pcr->cur_clock)
 674                 return 0;
 675
 676         if (pcr->ops->conv_clk_and_div_n)
 677                 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 678         else
 679                 n = (u8)(clk - 2);
 680         if ((clk <= 2) || (n > MAX_DIV_N_PCR))
 681                 return -EINVAL;
 682
 683         mcu_cnt = (u8)(125/clk + 3);
 684         if (mcu_cnt > 15)
 685                 mcu_cnt = 15;
 686
 687         /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
 688         div = CLK_DIV_1;
 689         while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
 690                 if (pcr->ops->conv_clk_and_div_n) {
 691                         int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
 692                                         DIV_N_TO_CLK) * 2;
 693                         n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 694                                         CLK_TO_DIV_N);
 695                 } else {
 696                         n = (n + 2) * 2 - 2;
 697                 }
 698                 div++;
 699         }
 700         pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
 701
 702         ssc_depth = depth[ssc_depth];
 703         if (double_clk)
 704                 ssc_depth = double_ssc_depth(ssc_depth);
 705
 706         ssc_depth = revise_ssc_depth(ssc_depth, div);
 707         pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
 708
 709         rtsx_pci_init_cmd(pcr);
 710         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 711                         CLK_LOW_FREQ, CLK_LOW_FREQ);
 712         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 713                         0xFF, (div << 4) | mcu_cnt);
 714         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 715         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 716                         SSC_DEPTH_MASK, ssc_depth);
 717         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
 718         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 719         if (vpclk) {
 720                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 721                                 PHASE_NOT_RESET, 0);
 722                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 723                                 PHASE_NOT_RESET, PHASE_NOT_RESET);
 724         }
 725
 726         err = rtsx_pci_send_cmd(pcr, 2000);
 727         if (err < 0)
 728                 return err;
 729
 730         /* Wait SSC clock stable */
 731         udelay(10);
 732         err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 733         if (err < 0)
 734                 return err;
 735
 736         pcr->cur_clock = clk;
 737         return 0;
 738 }
 739 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 740
 741 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 742 {
 743         if (pcr->ops->card_power_on)
 744                 return pcr->ops->card_power_on(pcr, card);
 745
 746         return 0;
 747 }
 748 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 749
 750 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 751 {
 752         if (pcr->ops->card_power_off)
 753                 return pcr->ops->card_power_off(pcr, card);
 754
 755         return 0;
 756 }
 757 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 758
 759 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
 760 {
 761         unsigned int cd_mask[] = {
 762                 [RTSX_SD_CARD] = SD_EXIST,
 763                 [RTSX_MS_CARD] = MS_EXIST
 764         };
 765
 766         if (!(pcr->flags & PCR_MS_PMOS)) {
 767                 /* When using single PMOS, accessing card is not permitted
 768                  * if the existing card is not the designated one.
 769                  */
 770                 if (pcr->card_exist & (~cd_mask[card]))
 771                         return -EIO;
 772         }
 773
 774         return 0;
 775 }
 776 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
 777
 778 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 779 {
 780         if (pcr->ops->switch_output_voltage)
 781                 return pcr->ops->switch_output_voltage(pcr, voltage);
 782
 783         return 0;
 784 }
 785 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 786
 787 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 788 {
 789         unsigned int val;
 790
 791         val = rtsx_pci_readl(pcr, RTSX_BIPR);
 792         if (pcr->ops->cd_deglitch)
 793                 val = pcr->ops->cd_deglitch(pcr);
 794
 795         return val;
 796 }
 797 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 798
 799 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 800 {
 801         struct completion finish;
 802
 803         pcr->finish_me = &finish;
 804         init_completion(&finish);
 805
 806         if (pcr->done)
 807                 complete(pcr->done);
 808
 809         if (!pcr->remove_pci)
 810                 rtsx_pci_stop_cmd(pcr);
 811
 812         wait_for_completion_interruptible_timeout(&finish,
 813                         msecs_to_jiffies(2));
 814         pcr->finish_me = NULL;
 815 }
 816 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 817
 818 static void rtsx_pci_card_detect(struct work_struct *work)
 819 {
 820         struct delayed_work *dwork;
 821         struct rtsx_pcr *pcr;
 822         unsigned long flags;
 823         unsigned int card_detect = 0, card_inserted, card_removed;
 824         u32 irq_status;
 825
 826         dwork = to_delayed_work(work);
 827         pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 828
 829         pcr_dbg(pcr, "--> %s\n", __func__);
 830
 831         mutex_lock(&pcr->pcr_mutex);
 832         spin_lock_irqsave(&pcr->lock, flags);
 833
 834         irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 835         pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
 836
 837         irq_status &= CARD_EXIST;
 838         card_inserted = pcr->card_inserted & irq_status;
 839         card_removed = pcr->card_removed;
 840         pcr->card_inserted = 0;
 841         pcr->card_removed = 0;
 842
 843         spin_unlock_irqrestore(&pcr->lock, flags);
 844
 845         if (card_inserted || card_removed) {
 846                 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
 847                         card_inserted, card_removed);
 848
 849                 if (pcr->ops->cd_deglitch)
 850                         card_inserted = pcr->ops->cd_deglitch(pcr);
 851
 852                 card_detect = card_inserted | card_removed;
 853
 854                 pcr->card_exist |= card_inserted;
 855                 pcr->card_exist &= ~card_removed;
 856         }
 857
 858         mutex_unlock(&pcr->pcr_mutex);
 859
 860         if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 861                 pcr->slots[RTSX_SD_CARD].card_event(
 862                                 pcr->slots[RTSX_SD_CARD].p_dev);
 863         if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 864                 pcr->slots[RTSX_MS_CARD].card_event(
 865                                 pcr->slots[RTSX_MS_CARD].p_dev);
 866 }
 867
 868 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 869 {
 870         struct rtsx_pcr *pcr = dev_id;
 871         u32 int_reg;
 872
 873         if (!pcr)
 874                 return IRQ_NONE;
 875
 876         spin_lock(&pcr->lock);
 877
 878         int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 879         /* Clear interrupt flag */
 880         rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 881         if ((int_reg & pcr->bier) == 0) {
 882                 spin_unlock(&pcr->lock);
 883                 return IRQ_NONE;
 884         }
 885         if (int_reg == 0xFFFFFFFF) {
 886                 spin_unlock(&pcr->lock);
 887                 return IRQ_HANDLED;
 888         }
 889
 890         int_reg &= (pcr->bier | 0x7FFFFF);
 891
 892         if (int_reg & SD_INT) {
 893                 if (int_reg & SD_EXIST) {
 894                         pcr->card_inserted |= SD_EXIST;
 895                 } else {
 896                         pcr->card_removed |= SD_EXIST;
 897                         pcr->card_inserted &= ~SD_EXIST;
 898                 }
 899         }
 900
 901         if (int_reg & MS_INT) {
 902                 if (int_reg & MS_EXIST) {
 903                         pcr->card_inserted |= MS_EXIST;
 904                 } else {
 905                         pcr->card_removed |= MS_EXIST;
 906                         pcr->card_inserted &= ~MS_EXIST;
 907                 }
 908         }
 909
 910         if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
 911                 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
 912                         pcr->trans_result = TRANS_RESULT_FAIL;
 913                         if (pcr->done)
 914                                 complete(pcr->done);
 915                 } else if (int_reg & TRANS_OK_INT) {
 916                         pcr->trans_result = TRANS_RESULT_OK;
 917                         if (pcr->done)
 918                                 complete(pcr->done);
 919                 }
 920         }
 921
 922         if (pcr->card_inserted || pcr->card_removed)
 923                 schedule_delayed_work(&pcr->carddet_work,
 924                                 msecs_to_jiffies(200));
 925
 926         spin_unlock(&pcr->lock);
 927         return IRQ_HANDLED;
 928 }
 929
 930 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
 931 {
 932         dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
 933                         __func__, pcr->msi_en, pcr->pci->irq);
 934
 935         if (request_irq(pcr->pci->irq, rtsx_pci_isr,
 936                         pcr->msi_en ? 0 : IRQF_SHARED,
 937                         DRV_NAME_RTSX_PCI, pcr)) {
 938                 dev_err(&(pcr->pci->dev),
 939                         "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
 940                         pcr->pci->irq);
 941                 return -1;
 942         }
 943
 944         pcr->irq = pcr->pci->irq;
 945         pci_intx(pcr->pci, !pcr->msi_en);
 946
 947         return 0;
 948 }
 949
 950 static void rtsx_pci_idle_work(struct work_struct *work)
 951 {
 952         struct delayed_work *dwork = to_delayed_work(work);
 953         struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 954
 955         pcr_dbg(pcr, "--> %s\n", __func__);
 956
 957         mutex_lock(&pcr->pcr_mutex);
 958
 959         pcr->state = PDEV_STAT_IDLE;
 960
 961         if (pcr->ops->disable_auto_blink)
 962                 pcr->ops->disable_auto_blink(pcr);
 963         if (pcr->ops->turn_off_led)
 964                 pcr->ops->turn_off_led(pcr);
 965
 966         if (pcr->aspm_en)
 967                 rtsx_pci_enable_aspm(pcr);
 968
 969         mutex_unlock(&pcr->pcr_mutex);
 970 }
 971
 972 #ifdef CONFIG_PM
 973 static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
 974 {
 975         if (pcr->ops->turn_off_led)
 976                 pcr->ops->turn_off_led(pcr);
 977
 978         rtsx_pci_writel(pcr, RTSX_BIER, 0);
 979         pcr->bier = 0;
 980
 981         rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
 982         rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
 983
 984         if (pcr->ops->force_power_down)
 985                 pcr->ops->force_power_down(pcr, pm_state);
 986 }
 987 #endif
 988
 989 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 990 {
 991         int err;
 992
 993         pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
 994         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 995
 996         rtsx_pci_enable_bus_int(pcr);
 997
 998         /* Power on SSC */
 999         err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1000         if (err < 0)
1001                 return err;
1002
1003         /* Wait SSC power stable */
1004         udelay(200);
1005
1006         rtsx_pci_disable_aspm(pcr);
1007         if (pcr->ops->optimize_phy) {
1008                 err = pcr->ops->optimize_phy(pcr);
1009                 if (err < 0)
1010                         return err;
1011         }
1012
1013         rtsx_pci_init_cmd(pcr);
1014
1015         /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1016         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1017
1018         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1019         /* Disable card clock */
1020         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1021         /* Reset delink mode */
1022         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1023         /* Card driving select */
1024         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1025                         0xFF, pcr->card_drive_sel);
1026         /* Enable SSC Clock */
1027         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1028                         0xFF, SSC_8X_EN | SSC_SEL_4M);
1029         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1030         /* Disable cd_pwr_save */
1031         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1032         /* Clear Link Ready Interrupt */
1033         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1034                         LINK_RDY_INT, LINK_RDY_INT);
1035         /* Enlarge the estimation window of PERST# glitch
1036          * to reduce the chance of invalid card interrupt
1037          */
1038         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1039         /* Update RC oscillator to 400k
1040          * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1041          *                1: 2M  0: 400k
1042          */
1043         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1044         /* Set interrupt write clear
1045          * bit 1: U_elbi_if_rd_clr_en
1046          *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1047          *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1048          */
1049         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1050
1051         err = rtsx_pci_send_cmd(pcr, 100);
1052         if (err < 0)
1053                 return err;
1054
1055         /* Enable clk_request_n to enable clock power management */
1056         rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
1057         /* Enter L1 when host tx idle */
1058         rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1059
1060         if (pcr->ops->extra_init_hw) {
1061                 err = pcr->ops->extra_init_hw(pcr);
1062                 if (err < 0)
1063                         return err;
1064         }
1065
1066         /* No CD interrupt if probing driver with card inserted.
1067          * So we need to initialize pcr->card_exist here.
1068          */
1069         if (pcr->ops->cd_deglitch)
1070                 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1071         else
1072                 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1073
1074         return 0;
1075 }
1076
1077 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1078 {
1079         int err;
1080
1081         spin_lock_init(&pcr->lock);
1082         mutex_init(&pcr->pcr_mutex);
1083
1084         switch (PCI_PID(pcr)) {
1085         default:
1086         case 0x5209:
1087                 rts5209_init_params(pcr);
1088                 break;
1089
1090         case 0x5229:
1091                 rts5229_init_params(pcr);
1092                 break;
1093
1094         case 0x5289:
1095                 rtl8411_init_params(pcr);
1096                 break;
1097
1098         case 0x5227:
1099                 rts5227_init_params(pcr);
1100                 break;
1101
1102         case 0x522A:
1103                 rts522a_init_params(pcr);
1104                 break;
1105
1106         case 0x5249:
1107                 rts5249_init_params(pcr);
1108                 break;
1109
1110         case 0x524A:
1111                 rts524a_init_params(pcr);
1112                 break;
1113
1114         case 0x525A:
1115                 rts525a_init_params(pcr);
1116                 break;
1117
1118         case 0x5287:
1119                 rtl8411b_init_params(pcr);
1120                 break;
1121
1122         case 0x5286:
1123                 rtl8402_init_params(pcr);
1124                 break;
1125         }
1126
1127         pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1128                         PCI_PID(pcr), pcr->ic_version);
1129
1130         pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1131                         GFP_KERNEL);
1132         if (!pcr->slots)
1133                 return -ENOMEM;
1134
1135         if (pcr->ops->fetch_vendor_settings)
1136                 pcr->ops->fetch_vendor_settings(pcr);
1137
1138         pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1139         pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1140                         pcr->sd30_drive_sel_1v8);
1141         pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1142                         pcr->sd30_drive_sel_3v3);
1143         pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1144                         pcr->card_drive_sel);
1145         pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1146
1147         pcr->state = PDEV_STAT_IDLE;
1148         err = rtsx_pci_init_hw(pcr);
1149         if (err < 0) {
1150                 kfree(pcr->slots);
1151                 return err;
1152         }
1153
1154         return 0;
1155 }
1156
1157 static int rtsx_pci_probe(struct pci_dev *pcidev,
1158                           const struct pci_device_id *id)
1159 {
1160         struct rtsx_pcr *pcr;
1161         struct pcr_handle *handle;
1162         u32 base, len;
1163         int ret, i, bar = 0;
1164
1165         dev_dbg(&(pcidev->dev),
1166                 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1167                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1168                 (int)pcidev->revision);
1169
1170         ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1171         if (ret < 0)
1172                 return ret;
1173
1174         ret = pci_enable_device(pcidev);
1175         if (ret)
1176                 return ret;
1177
1178         ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1179         if (ret)
1180                 goto disable;
1181
1182         pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1183         if (!pcr) {
1184                 ret = -ENOMEM;
1185                 goto release_pci;
1186         }
1187
1188         handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1189         if (!handle) {
1190                 ret = -ENOMEM;
1191                 goto free_pcr;
1192         }
1193         handle->pcr = pcr;
1194
1195         idr_preload(GFP_KERNEL);
1196         spin_lock(&rtsx_pci_lock);
1197         ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1198         if (ret >= 0)
1199                 pcr->id = ret;
1200         spin_unlock(&rtsx_pci_lock);
1201         idr_preload_end();
1202         if (ret < 0)
1203                 goto free_handle;
1204
1205         pcr->pci = pcidev;
1206         dev_set_drvdata(&pcidev->dev, handle);
1207
1208         if (CHK_PCI_PID(pcr, 0x525A))
1209                 bar = 1;
1210         len = pci_resource_len(pcidev, bar);
1211         base = pci_resource_start(pcidev, bar);
1212         pcr->remap_addr = ioremap_nocache(base, len);
1213         if (!pcr->remap_addr) {
1214                 ret = -ENOMEM;
1215                 goto free_handle;
1216         }
1217
1218         pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1219                         RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1220                         GFP_KERNEL);
1221         if (pcr->rtsx_resv_buf == NULL) {
1222                 ret = -ENXIO;
1223                 goto unmap;
1224         }
1225         pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1226         pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1227         pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1228         pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1229
1230         pcr->card_inserted = 0;
1231         pcr->card_removed = 0;
1232         INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1233         INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1234
1235         pcr->msi_en = msi_en;
1236         if (pcr->msi_en) {
1237                 ret = pci_enable_msi(pcidev);
1238                 if (ret)
1239                         pcr->msi_en = false;
1240         }
1241
1242         ret = rtsx_pci_acquire_irq(pcr);
1243         if (ret < 0)
1244                 goto disable_msi;
1245
1246         pci_set_master(pcidev);
1247         synchronize_irq(pcr->irq);
1248
1249         ret = rtsx_pci_init_chip(pcr);
1250         if (ret < 0)
1251                 goto disable_irq;
1252
1253         for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1254                 rtsx_pcr_cells[i].platform_data = handle;
1255                 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1256         }
1257         ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1258                         ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1259         if (ret < 0)
1260                 goto disable_irq;
1261
1262         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1263
1264         return 0;
1265
1266 disable_irq:
1267         free_irq(pcr->irq, (void *)pcr);
1268 disable_msi:
1269         if (pcr->msi_en)
1270                 pci_disable_msi(pcr->pci);
1271         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1272                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1273 unmap:
1274         iounmap(pcr->remap_addr);
1275 free_handle:
1276         kfree(handle);
1277 free_pcr:
1278         kfree(pcr);
1279 release_pci:
1280         pci_release_regions(pcidev);
1281 disable:
1282         pci_disable_device(pcidev);
1283
1284         return ret;
1285 }
1286
1287 static void rtsx_pci_remove(struct pci_dev *pcidev)
1288 {
1289         struct pcr_handle *handle = pci_get_drvdata(pcidev);
1290         struct rtsx_pcr *pcr = handle->pcr;
1291
1292         pcr->remove_pci = true;
1293
1294         /* Disable interrupts at the pcr level */
1295         spin_lock_irq(&pcr->lock);
1296         rtsx_pci_writel(pcr, RTSX_BIER, 0);
1297         pcr->bier = 0;
1298         spin_unlock_irq(&pcr->lock);
1299
1300         cancel_delayed_work_sync(&pcr->carddet_work);
1301         cancel_delayed_work_sync(&pcr->idle_work);
1302
1303         mfd_remove_devices(&pcidev->dev);
1304
1305         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1306                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1307         free_irq(pcr->irq, (void *)pcr);
1308         if (pcr->msi_en)
1309                 pci_disable_msi(pcr->pci);
1310         iounmap(pcr->remap_addr);
1311
1312         pci_release_regions(pcidev);
1313         pci_disable_device(pcidev);
1314
1315         spin_lock(&rtsx_pci_lock);
1316         idr_remove(&rtsx_pci_idr, pcr->id);
1317         spin_unlock(&rtsx_pci_lock);
1318
1319         kfree(pcr->slots);
1320         kfree(pcr);
1321         kfree(handle);
1322
1323         dev_dbg(&(pcidev->dev),
1324                 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1325                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1326 }
1327
1328 #ifdef CONFIG_PM
1329
1330 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1331 {
1332         struct pcr_handle *handle;
1333         struct rtsx_pcr *pcr;
1334
1335         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1336
1337         handle = pci_get_drvdata(pcidev);
1338         pcr = handle->pcr;
1339
1340         cancel_delayed_work(&pcr->carddet_work);
1341         cancel_delayed_work(&pcr->idle_work);
1342
1343         mutex_lock(&pcr->pcr_mutex);
1344
1345         rtsx_pci_power_off(pcr, HOST_ENTER_S3);
1346
1347         pci_save_state(pcidev);
1348         pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1349         pci_disable_device(pcidev);
1350         pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1351
1352         mutex_unlock(&pcr->pcr_mutex);
1353         return 0;
1354 }
1355
1356 static int rtsx_pci_resume(struct pci_dev *pcidev)
1357 {
1358         struct pcr_handle *handle;
1359         struct rtsx_pcr *pcr;
1360         int ret = 0;
1361
1362         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1363
1364         handle = pci_get_drvdata(pcidev);
1365         pcr = handle->pcr;
1366
1367         mutex_lock(&pcr->pcr_mutex);
1368
1369         pci_set_power_state(pcidev, PCI_D0);
1370         pci_restore_state(pcidev);
1371         ret = pci_enable_device(pcidev);
1372         if (ret)
1373                 goto out;
1374         pci_set_master(pcidev);
1375
1376         ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1377         if (ret)
1378                 goto out;
1379
1380         ret = rtsx_pci_init_hw(pcr);
1381         if (ret)
1382                 goto out;
1383
1384         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1385
1386 out:
1387         mutex_unlock(&pcr->pcr_mutex);
1388         return ret;
1389 }
1390
1391 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1392 {
1393         struct pcr_handle *handle;
1394         struct rtsx_pcr *pcr;
1395
1396         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1397
1398         handle = pci_get_drvdata(pcidev);
1399         pcr = handle->pcr;
1400         rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1401
1402         pci_disable_device(pcidev);
1403 }
1404
1405 #else /* CONFIG_PM */
1406
1407 #define rtsx_pci_suspend NULL
1408 #define rtsx_pci_resume NULL
1409 #define rtsx_pci_shutdown NULL
1410
1411 #endif /* CONFIG_PM */
1412
1413 static struct pci_driver rtsx_pci_driver = {
1414         .name = DRV_NAME_RTSX_PCI,
1415         .id_table = rtsx_pci_ids,
1416         .probe = rtsx_pci_probe,
1417         .remove = rtsx_pci_remove,
1418         .suspend = rtsx_pci_suspend,
1419         .resume = rtsx_pci_resume,
1420         .shutdown = rtsx_pci_shutdown,
1421 };
1422 module_pci_driver(rtsx_pci_driver);
1423
1424 MODULE_LICENSE("GPL");
1425 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1426 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");