2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_bridge.h>
14 #include <linux/jiffies.h>
15 #include <linux/list.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/phy.h>
20 #include "mv88e6xxx.h"
22 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
23 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
24 * will be directly accessible on some {device address,register address}
25 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
26 * will only respond to SMI transactions to that specific address, and
27 * an indirect addressing mechanism needs to be used to access its
30 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
35 for (i = 0; i < 16; i++) {
36 ret = mdiobus_read(bus, sw_addr, SMI_CMD);
40 if ((ret & SMI_CMD_BUSY) == 0)
47 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
52 return mdiobus_read(bus, addr, reg);
54 /* Wait for the bus to become free. */
55 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
59 /* Transmit the read command. */
60 ret = mdiobus_write(bus, sw_addr, SMI_CMD,
61 SMI_CMD_OP_22_READ | (addr << 5) | reg);
65 /* Wait for the read command to complete. */
66 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
71 ret = mdiobus_read(bus, sw_addr, SMI_DATA);
78 /* Must be called with SMI mutex held */
79 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
81 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
87 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
91 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
97 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
99 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
102 mutex_lock(&ps->smi_mutex);
103 ret = _mv88e6xxx_reg_read(ds, addr, reg);
104 mutex_unlock(&ps->smi_mutex);
109 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
115 return mdiobus_write(bus, addr, reg, val);
117 /* Wait for the bus to become free. */
118 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
122 /* Transmit the data to write. */
123 ret = mdiobus_write(bus, sw_addr, SMI_DATA, val);
127 /* Transmit the write command. */
128 ret = mdiobus_write(bus, sw_addr, SMI_CMD,
129 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
133 /* Wait for the write command to complete. */
134 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
141 /* Must be called with SMI mutex held */
142 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
145 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
150 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
153 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
156 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
158 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
161 mutex_lock(&ps->smi_mutex);
162 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
163 mutex_unlock(&ps->smi_mutex);
168 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
170 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
171 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
172 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
177 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
182 for (i = 0; i < 6; i++) {
185 /* Write the MAC address byte. */
186 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
187 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
189 /* Wait for the write to complete. */
190 for (j = 0; j < 16; j++) {
191 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
192 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
202 /* Must be called with SMI mutex held */
203 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
206 return _mv88e6xxx_reg_read(ds, addr, regnum);
210 /* Must be called with SMI mutex held */
211 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
215 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
219 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
220 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
223 unsigned long timeout;
225 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
226 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
227 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
229 timeout = jiffies + 1 * HZ;
230 while (time_before(jiffies, timeout)) {
231 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
232 usleep_range(1000, 2000);
233 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
234 GLOBAL_STATUS_PPU_POLLING)
241 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
244 unsigned long timeout;
246 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
247 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
249 timeout = jiffies + 1 * HZ;
250 while (time_before(jiffies, timeout)) {
251 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
252 usleep_range(1000, 2000);
253 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
254 GLOBAL_STATUS_PPU_POLLING)
261 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
263 struct mv88e6xxx_priv_state *ps;
265 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
266 if (mutex_trylock(&ps->ppu_mutex)) {
267 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
269 if (mv88e6xxx_ppu_enable(ds) == 0)
270 ps->ppu_disabled = 0;
271 mutex_unlock(&ps->ppu_mutex);
275 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
277 struct mv88e6xxx_priv_state *ps = (void *)_ps;
279 schedule_work(&ps->ppu_work);
282 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
284 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
287 mutex_lock(&ps->ppu_mutex);
289 /* If the PHY polling unit is enabled, disable it so that
290 * we can access the PHY registers. If it was already
291 * disabled, cancel the timer that is going to re-enable
294 if (!ps->ppu_disabled) {
295 ret = mv88e6xxx_ppu_disable(ds);
297 mutex_unlock(&ps->ppu_mutex);
300 ps->ppu_disabled = 1;
302 del_timer(&ps->ppu_timer);
309 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
311 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
313 /* Schedule a timer to re-enable the PHY polling unit. */
314 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
315 mutex_unlock(&ps->ppu_mutex);
318 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
320 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
322 mutex_init(&ps->ppu_mutex);
323 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
324 init_timer(&ps->ppu_timer);
325 ps->ppu_timer.data = (unsigned long)ps;
326 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
329 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
333 ret = mv88e6xxx_ppu_access_get(ds);
335 ret = mv88e6xxx_reg_read(ds, addr, regnum);
336 mv88e6xxx_ppu_access_put(ds);
342 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
347 ret = mv88e6xxx_ppu_access_get(ds);
349 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
350 mv88e6xxx_ppu_access_put(ds);
357 void mv88e6xxx_poll_link(struct dsa_switch *ds)
361 for (i = 0; i < DSA_MAX_PORTS; i++) {
362 struct net_device *dev;
363 int uninitialized_var(port_status);
374 if (dev->flags & IFF_UP) {
375 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i),
380 link = !!(port_status & PORT_STATUS_LINK);
384 if (netif_carrier_ok(dev)) {
385 netdev_info(dev, "link down\n");
386 netif_carrier_off(dev);
391 switch (port_status & PORT_STATUS_SPEED_MASK) {
392 case PORT_STATUS_SPEED_10:
395 case PORT_STATUS_SPEED_100:
398 case PORT_STATUS_SPEED_1000:
405 duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0;
406 fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0;
408 if (!netif_carrier_ok(dev)) {
410 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
412 duplex ? "full" : "half",
414 netif_carrier_on(dev);
419 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
421 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
424 case PORT_SWITCH_ID_6031:
425 case PORT_SWITCH_ID_6061:
426 case PORT_SWITCH_ID_6035:
427 case PORT_SWITCH_ID_6065:
433 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
435 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
438 case PORT_SWITCH_ID_6092:
439 case PORT_SWITCH_ID_6095:
445 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
450 case PORT_SWITCH_ID_6046:
451 case PORT_SWITCH_ID_6085:
452 case PORT_SWITCH_ID_6096:
453 case PORT_SWITCH_ID_6097:
459 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
461 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
464 case PORT_SWITCH_ID_6123:
465 case PORT_SWITCH_ID_6161:
466 case PORT_SWITCH_ID_6165:
472 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
474 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
477 case PORT_SWITCH_ID_6121:
478 case PORT_SWITCH_ID_6122:
479 case PORT_SWITCH_ID_6152:
480 case PORT_SWITCH_ID_6155:
481 case PORT_SWITCH_ID_6182:
482 case PORT_SWITCH_ID_6185:
483 case PORT_SWITCH_ID_6108:
484 case PORT_SWITCH_ID_6131:
490 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
495 case PORT_SWITCH_ID_6171:
496 case PORT_SWITCH_ID_6175:
497 case PORT_SWITCH_ID_6350:
498 case PORT_SWITCH_ID_6351:
504 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
506 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
509 case PORT_SWITCH_ID_6172:
510 case PORT_SWITCH_ID_6176:
511 case PORT_SWITCH_ID_6240:
512 case PORT_SWITCH_ID_6352:
518 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
523 for (i = 0; i < 10; i++) {
524 ret = REG_READ(REG_GLOBAL, GLOBAL_STATS_OP);
525 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
532 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
536 if (mv88e6xxx_6352_family(ds))
537 port = (port + 1) << 5;
539 /* Snapshot the hardware statistics counters for this port. */
540 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP,
541 GLOBAL_STATS_OP_CAPTURE_PORT |
542 GLOBAL_STATS_OP_HIST_RX_TX | port);
544 /* Wait for the snapshotting to complete. */
545 ret = mv88e6xxx_stats_wait(ds);
552 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
559 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
560 GLOBAL_STATS_OP_READ_CAPTURED |
561 GLOBAL_STATS_OP_HIST_RX_TX | stat);
565 ret = mv88e6xxx_stats_wait(ds);
569 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
575 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
582 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
583 { "in_good_octets", 8, 0x00, },
584 { "in_bad_octets", 4, 0x02, },
585 { "in_unicast", 4, 0x04, },
586 { "in_broadcasts", 4, 0x06, },
587 { "in_multicasts", 4, 0x07, },
588 { "in_pause", 4, 0x16, },
589 { "in_undersize", 4, 0x18, },
590 { "in_fragments", 4, 0x19, },
591 { "in_oversize", 4, 0x1a, },
592 { "in_jabber", 4, 0x1b, },
593 { "in_rx_error", 4, 0x1c, },
594 { "in_fcs_error", 4, 0x1d, },
595 { "out_octets", 8, 0x0e, },
596 { "out_unicast", 4, 0x10, },
597 { "out_broadcasts", 4, 0x13, },
598 { "out_multicasts", 4, 0x12, },
599 { "out_pause", 4, 0x15, },
600 { "excessive", 4, 0x11, },
601 { "collisions", 4, 0x1e, },
602 { "deferred", 4, 0x05, },
603 { "single", 4, 0x14, },
604 { "multiple", 4, 0x17, },
605 { "out_fcs_error", 4, 0x03, },
606 { "late", 4, 0x1f, },
607 { "hist_64bytes", 4, 0x08, },
608 { "hist_65_127bytes", 4, 0x09, },
609 { "hist_128_255bytes", 4, 0x0a, },
610 { "hist_256_511bytes", 4, 0x0b, },
611 { "hist_512_1023bytes", 4, 0x0c, },
612 { "hist_1024_max_bytes", 4, 0x0d, },
613 /* Not all devices have the following counters */
614 { "sw_in_discards", 4, 0x110, },
615 { "sw_in_filtered", 2, 0x112, },
616 { "sw_out_filtered", 2, 0x113, },
620 static bool have_sw_in_discards(struct dsa_switch *ds)
622 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
625 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
626 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
627 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
628 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
629 case PORT_SWITCH_ID_6352:
636 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
638 struct mv88e6xxx_hw_stat *stats,
639 int port, uint8_t *data)
643 for (i = 0; i < nr_stats; i++) {
644 memcpy(data + i * ETH_GSTRING_LEN,
645 stats[i].string, ETH_GSTRING_LEN);
649 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
651 struct mv88e6xxx_hw_stat *stats,
652 int port, uint64_t *data)
654 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
658 mutex_lock(&ps->stats_mutex);
660 ret = mv88e6xxx_stats_snapshot(ds, port);
662 mutex_unlock(&ps->stats_mutex);
666 /* Read each of the counters. */
667 for (i = 0; i < nr_stats; i++) {
668 struct mv88e6xxx_hw_stat *s = stats + i;
672 if (s->reg >= 0x100) {
673 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
678 if (s->sizeof_stat == 4) {
679 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
685 data[i] = (((u64)high) << 16) | low;
688 mv88e6xxx_stats_read(ds, s->reg, &low);
689 if (s->sizeof_stat == 8)
690 mv88e6xxx_stats_read(ds, s->reg + 1, &high);
692 data[i] = (((u64)high) << 32) | low;
695 mutex_unlock(&ps->stats_mutex);
698 /* All the statistics in the table */
700 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
702 if (have_sw_in_discards(ds))
703 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
704 mv88e6xxx_hw_stats, port, data);
706 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
707 mv88e6xxx_hw_stats, port, data);
710 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
712 if (have_sw_in_discards(ds))
713 return ARRAY_SIZE(mv88e6xxx_hw_stats);
714 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
718 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
719 int port, uint64_t *data)
721 if (have_sw_in_discards(ds))
722 _mv88e6xxx_get_ethtool_stats(
723 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
724 mv88e6xxx_hw_stats, port, data);
726 _mv88e6xxx_get_ethtool_stats(
727 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
728 mv88e6xxx_hw_stats, port, data);
731 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
733 return 32 * sizeof(u16);
736 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
737 struct ethtool_regs *regs, void *_p)
744 memset(p, 0xff, 32 * sizeof(u16));
746 for (i = 0; i < 32; i++) {
749 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
755 #ifdef CONFIG_NET_DSA_HWMON
757 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
759 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
765 mutex_lock(&ps->smi_mutex);
767 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
771 /* Enable temperature sensor */
772 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
776 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
780 /* Wait for temperature to stabilize */
781 usleep_range(10000, 12000);
783 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
789 /* Disable temperature sensor */
790 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
794 *temp = ((val & 0x1f) - 5) * 5;
797 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
798 mutex_unlock(&ps->smi_mutex);
801 #endif /* CONFIG_NET_DSA_HWMON */
803 /* Must be called with SMI lock held */
804 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
807 unsigned long timeout = jiffies + HZ / 10;
809 while (time_before(jiffies, timeout)) {
812 ret = _mv88e6xxx_reg_read(ds, reg, offset);
818 usleep_range(1000, 2000);
823 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
825 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
828 mutex_lock(&ps->smi_mutex);
829 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
830 mutex_unlock(&ps->smi_mutex);
835 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
837 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
838 GLOBAL2_SMI_OP_BUSY);
841 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
843 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
844 GLOBAL2_EEPROM_OP_LOAD);
847 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
849 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
850 GLOBAL2_EEPROM_OP_BUSY);
853 /* Must be called with SMI lock held */
854 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
856 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
860 /* Must be called with SMI mutex held */
861 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
866 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
867 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
872 ret = _mv88e6xxx_phy_wait(ds);
876 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
879 /* Must be called with SMI mutex held */
880 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
885 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
889 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
890 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
893 return _mv88e6xxx_phy_wait(ds);
896 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
898 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
901 mutex_lock(&ps->smi_mutex);
903 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
907 e->eee_enabled = !!(reg & 0x0200);
908 e->tx_lpi_enabled = !!(reg & 0x0100);
910 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
914 e->eee_active = !!(reg & PORT_STATUS_EEE);
918 mutex_unlock(&ps->smi_mutex);
922 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
923 struct phy_device *phydev, struct ethtool_eee *e)
925 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
929 mutex_lock(&ps->smi_mutex);
931 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
938 if (e->tx_lpi_enabled)
941 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
943 mutex_unlock(&ps->smi_mutex);
948 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
952 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
956 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
960 return _mv88e6xxx_atu_wait(ds);
963 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
967 ret = _mv88e6xxx_atu_wait(ds);
971 return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB);
974 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
976 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
980 mutex_lock(&ps->smi_mutex);
982 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
988 oldstate = reg & PORT_CONTROL_STATE_MASK;
989 if (oldstate != state) {
990 /* Flush forwarding database if we're moving a port
991 * from Learning or Forwarding state to Disabled or
992 * Blocking or Listening state.
994 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
995 state <= PORT_CONTROL_STATE_BLOCKING) {
996 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
1000 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1001 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1006 mutex_unlock(&ps->smi_mutex);
1010 /* Must be called with smi lock held */
1011 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
1013 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1014 u8 fid = ps->fid[port];
1015 u16 reg = fid << 12;
1017 if (dsa_is_cpu_port(ds, port))
1018 reg |= ds->phys_port_mask;
1020 reg |= (ps->bridge_mask[fid] |
1021 (1 << dsa_upstream_port(ds))) & ~(1 << port);
1023 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1026 /* Must be called with smi lock held */
1027 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
1029 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1034 mask = ds->phys_port_mask;
1037 mask &= ~(1 << port);
1038 if (ps->fid[port] != fid)
1041 ret = _mv88e6xxx_update_port_config(ds, port);
1046 return _mv88e6xxx_flush_fid(ds, fid);
1049 /* Bridge handling functions */
1051 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1053 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1058 /* If the bridge group is not empty, join that group.
1059 * Otherwise create a new group.
1061 fid = ps->fid[port];
1062 nmask = br_port_mask & ~(1 << port);
1064 fid = ps->fid[__ffs(nmask)];
1066 nmask = ps->bridge_mask[fid] | (1 << port);
1067 if (nmask != br_port_mask) {
1068 netdev_err(ds->ports[port],
1069 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1070 fid, br_port_mask, nmask);
1074 mutex_lock(&ps->smi_mutex);
1076 ps->bridge_mask[fid] = br_port_mask;
1078 if (fid != ps->fid[port]) {
1079 ps->fid_mask |= 1 << ps->fid[port];
1080 ps->fid[port] = fid;
1081 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1084 mutex_unlock(&ps->smi_mutex);
1089 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
1091 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1095 fid = ps->fid[port];
1097 if (ps->bridge_mask[fid] != br_port_mask) {
1098 netdev_err(ds->ports[port],
1099 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
1100 fid, br_port_mask, ps->bridge_mask[fid]);
1104 /* If the port was the last port of a bridge, we are done.
1105 * Otherwise assign a new fid to the port, and fix up
1106 * the bridge configuration.
1108 if (br_port_mask == (1 << port))
1111 mutex_lock(&ps->smi_mutex);
1113 newfid = __ffs(ps->fid_mask);
1114 ps->fid[port] = newfid;
1115 ps->fid_mask &= (1 << newfid);
1116 ps->bridge_mask[fid] &= ~(1 << port);
1117 ps->bridge_mask[newfid] = 1 << port;
1119 ret = _mv88e6xxx_update_bridge_config(ds, fid);
1121 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
1123 mutex_unlock(&ps->smi_mutex);
1128 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1130 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1134 case BR_STATE_DISABLED:
1135 stp_state = PORT_CONTROL_STATE_DISABLED;
1137 case BR_STATE_BLOCKING:
1138 case BR_STATE_LISTENING:
1139 stp_state = PORT_CONTROL_STATE_BLOCKING;
1141 case BR_STATE_LEARNING:
1142 stp_state = PORT_CONTROL_STATE_LEARNING;
1144 case BR_STATE_FORWARDING:
1146 stp_state = PORT_CONTROL_STATE_FORWARDING;
1150 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1152 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1153 * so we can not update the port state directly but need to schedule it.
1155 ps->port_state[port] = stp_state;
1156 set_bit(port, &ps->port_state_update_mask);
1157 schedule_work(&ps->bridge_work);
1162 static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
1163 const unsigned char *addr)
1167 for (i = 0; i < 3; i++) {
1168 ret = _mv88e6xxx_reg_write(
1169 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1170 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1178 static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
1182 for (i = 0; i < 3; i++) {
1183 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1184 GLOBAL_ATU_MAC_01 + i);
1187 addr[i * 2] = ret >> 8;
1188 addr[i * 2 + 1] = ret & 0xff;
1194 static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
1195 const unsigned char *addr, int state)
1197 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1198 u8 fid = ps->fid[port];
1201 ret = _mv88e6xxx_atu_wait(ds);
1205 ret = __mv88e6xxx_write_addr(ds, addr);
1209 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA,
1210 (0x10 << port) | state);
1214 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB);
1219 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1220 const unsigned char *addr, u16 vid)
1222 int state = is_multicast_ether_addr(addr) ?
1223 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1224 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1225 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1228 mutex_lock(&ps->smi_mutex);
1229 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
1230 mutex_unlock(&ps->smi_mutex);
1235 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1236 const unsigned char *addr, u16 vid)
1238 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1241 mutex_lock(&ps->smi_mutex);
1242 ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr,
1243 GLOBAL_ATU_DATA_STATE_UNUSED);
1244 mutex_unlock(&ps->smi_mutex);
1249 static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
1250 unsigned char *addr, bool *is_static)
1252 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1253 u8 fid = ps->fid[port];
1256 ret = _mv88e6xxx_atu_wait(ds);
1260 ret = __mv88e6xxx_write_addr(ds, addr);
1265 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1269 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1272 state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1273 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
1275 } while (!(((ret >> 4) & 0xff) & (1 << port)));
1277 ret = __mv88e6xxx_read_addr(ds, addr);
1281 *is_static = state == (is_multicast_ether_addr(addr) ?
1282 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1283 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1288 /* get next entry for port */
1289 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1290 unsigned char *addr, bool *is_static)
1292 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1295 mutex_lock(&ps->smi_mutex);
1296 ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
1297 mutex_unlock(&ps->smi_mutex);
1302 static void mv88e6xxx_bridge_work(struct work_struct *work)
1304 struct mv88e6xxx_priv_state *ps;
1305 struct dsa_switch *ds;
1308 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1309 ds = ((struct dsa_switch *)ps) - 1;
1311 while (ps->port_state_update_mask) {
1312 port = __ffs(ps->port_state_update_mask);
1313 clear_bit(port, &ps->port_state_update_mask);
1314 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1318 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1320 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1324 mutex_lock(&ps->smi_mutex);
1326 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1327 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1328 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1329 mv88e6xxx_6065_family(ds)) {
1330 /* MAC Forcing register: don't force link, speed,
1331 * duplex or flow control state to any particular
1332 * values on physical ports, but force the CPU port
1333 * and all DSA ports to their maximum bandwidth and
1336 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1337 if (dsa_is_cpu_port(ds, port) ||
1338 ds->dsa_port_mask & (1 << port)) {
1339 reg |= PORT_PCS_CTRL_FORCE_LINK |
1340 PORT_PCS_CTRL_LINK_UP |
1341 PORT_PCS_CTRL_DUPLEX_FULL |
1342 PORT_PCS_CTRL_FORCE_DUPLEX;
1343 if (mv88e6xxx_6065_family(ds))
1344 reg |= PORT_PCS_CTRL_100;
1346 reg |= PORT_PCS_CTRL_1000;
1348 reg |= PORT_PCS_CTRL_UNFORCED;
1351 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1352 PORT_PCS_CTRL, reg);
1357 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1358 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1359 * tunneling, determine priority by looking at 802.1p and IP
1360 * priority fields (IP prio has precedence), and set STP state
1363 * If this is the CPU link, use DSA or EDSA tagging depending
1364 * on which tagging mode was configured.
1366 * If this is a link to another switch, use DSA tagging mode.
1368 * If this is the upstream port for this switch, enable
1369 * forwarding of unknown unicasts and multicasts.
1372 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1373 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1374 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1375 mv88e6xxx_6185_family(ds))
1376 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1377 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1378 PORT_CONTROL_STATE_FORWARDING;
1379 if (dsa_is_cpu_port(ds, port)) {
1380 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1381 reg |= PORT_CONTROL_DSA_TAG;
1382 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1383 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1384 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1385 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1387 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1390 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1391 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1392 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1393 mv88e6xxx_6185_family(ds)) {
1394 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1395 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1398 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1399 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1400 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds)) {
1401 if (ds->dsa_port_mask & (1 << port))
1402 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1403 if (port == dsa_upstream_port(ds))
1404 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1405 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1408 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1414 /* Port Control 2: don't force a good FCS, set the maximum
1415 * frame size to 10240 bytes, don't let the switch add or
1416 * strip 802.1q tags, don't discard tagged or untagged frames
1417 * on this port, do a destination address lookup on all
1418 * received packets as usual, disable ARP mirroring and don't
1419 * send a copy of all transmitted/received frames on this port
1423 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1424 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1425 mv88e6xxx_6095_family(ds))
1426 reg = PORT_CONTROL_2_MAP_DA;
1428 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1429 mv88e6xxx_6165_family(ds))
1430 reg |= PORT_CONTROL_2_JUMBO_10240;
1432 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1433 /* Set the upstream port this port should use */
1434 reg |= dsa_upstream_port(ds);
1435 /* enable forwarding of unknown multicast addresses to
1438 if (port == dsa_upstream_port(ds))
1439 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1443 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1444 PORT_CONTROL_2, reg);
1449 /* Port Association Vector: when learning source addresses
1450 * of packets, add the address to the address database using
1451 * a port bitmap that has only the bit for this port set and
1452 * the other bits clear.
1454 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1459 /* Egress rate control 2: disable egress rate control. */
1460 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
1465 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1466 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1467 /* Do not limit the period of time that this port can
1468 * be paused for by the remote end or the period of
1469 * time that this port can pause the remote end.
1471 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1472 PORT_PAUSE_CTRL, 0x0000);
1476 /* Port ATU control: disable limiting the number of
1477 * address database entries that this port is allowed
1480 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1481 PORT_ATU_CONTROL, 0x0000);
1482 /* Priority Override: disable DA, SA and VTU priority
1485 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1486 PORT_PRI_OVERRIDE, 0x0000);
1490 /* Port Ethertype: use the Ethertype DSA Ethertype
1493 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1494 PORT_ETH_TYPE, ETH_P_EDSA);
1497 /* Tag Remap: use an identity 802.1p prio -> switch
1500 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1501 PORT_TAG_REGMAP_0123, 0x3210);
1505 /* Tag Remap 2: use an identity 802.1p prio -> switch
1508 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1509 PORT_TAG_REGMAP_4567, 0x7654);
1514 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1515 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1516 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
1517 /* Rate Control: disable ingress rate limiting. */
1518 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1519 PORT_RATE_CONTROL, 0x0001);
1524 /* Port Control 1: disable trunking, disable sending
1525 * learning messages to this port.
1527 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
1531 /* Port based VLAN map: give each port its own address
1532 * database, allow the CPU port to talk to each of the 'real'
1533 * ports, and allow each of the 'real' ports to only talk to
1534 * the upstream port.
1536 fid = __ffs(ps->fid_mask);
1537 ps->fid[port] = fid;
1538 ps->fid_mask &= ~(1 << fid);
1540 if (!dsa_is_cpu_port(ds, port))
1541 ps->bridge_mask[fid] = 1 << port;
1543 ret = _mv88e6xxx_update_port_config(ds, port);
1547 /* Default VLAN ID and priority: don't set a default VLAN
1548 * ID, and set the default packet priority to zero.
1550 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1553 mutex_unlock(&ps->smi_mutex);
1557 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
1559 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1563 for (i = 0; i < ps->num_ports; i++) {
1564 ret = mv88e6xxx_setup_port(ds, i);
1571 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1573 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1575 mutex_init(&ps->smi_mutex);
1576 mutex_init(&ps->stats_mutex);
1578 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
1580 ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1582 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1587 int mv88e6xxx_setup_global(struct dsa_switch *ds)
1589 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1592 /* Set the default address aging time to 5 minutes, and
1593 * enable address learn messages to be sent to all message
1596 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
1597 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
1599 /* Configure the IP ToS mapping registers. */
1600 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
1601 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
1602 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
1603 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
1604 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
1605 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
1606 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
1607 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
1609 /* Configure the IEEE 802.1p priority mapping register. */
1610 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
1612 /* Send all frames with destination addresses matching
1613 * 01:80:c2:00:00:0x to the CPU port.
1615 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
1617 /* Ignore removed tag data on doubly tagged packets, disable
1618 * flow control messages, force flow control priority to the
1619 * highest, and send all special multicast frames to the CPU
1620 * port at the highest priority.
1622 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
1623 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
1624 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
1626 /* Program the DSA routing table. */
1627 for (i = 0; i < 32; i++) {
1630 if (ds->pd->rtable &&
1631 i != ds->index && i < ds->dst->pd->nr_chips)
1632 nexthop = ds->pd->rtable[i] & 0x1f;
1634 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
1635 GLOBAL2_DEVICE_MAPPING_UPDATE |
1636 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
1640 /* Clear all trunk masks. */
1641 for (i = 0; i < 8; i++)
1642 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
1643 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
1644 ((1 << ps->num_ports) - 1));
1646 /* Clear all trunk mappings. */
1647 for (i = 0; i < 16; i++)
1648 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
1649 GLOBAL2_TRUNK_MAPPING_UPDATE |
1650 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
1652 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1653 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds)) {
1654 /* Send all frames with destination addresses matching
1655 * 01:80:c2:00:00:2x to the CPU port.
1657 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
1659 /* Initialise cross-chip port VLAN table to reset
1662 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
1664 /* Clear the priority override table. */
1665 for (i = 0; i < 16; i++)
1666 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
1670 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1671 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1672 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds)) {
1673 /* Disable ingress rate limiting by resetting all
1674 * ingress rate limit registers to their initial
1677 for (i = 0; i < ps->num_ports; i++)
1678 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
1685 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
1687 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1688 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
1689 unsigned long timeout;
1693 /* Set all ports to the disabled state. */
1694 for (i = 0; i < ps->num_ports; i++) {
1695 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
1696 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
1699 /* Wait for transmit queues to drain. */
1700 usleep_range(2000, 4000);
1702 /* Reset the switch. Keep the PPU active if requested. The PPU
1703 * needs to be active to support indirect phy register access
1704 * through global registers 0x18 and 0x19.
1707 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
1709 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
1711 /* Wait up to one second for reset to complete. */
1712 timeout = jiffies + 1 * HZ;
1713 while (time_before(jiffies, timeout)) {
1714 ret = REG_READ(REG_GLOBAL, 0x00);
1715 if ((ret & is_reset) == is_reset)
1717 usleep_range(1000, 2000);
1719 if (time_after(jiffies, timeout))
1725 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
1727 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1730 mutex_lock(&ps->smi_mutex);
1731 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
1734 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
1736 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
1737 mutex_unlock(&ps->smi_mutex);
1741 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
1744 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1747 mutex_lock(&ps->smi_mutex);
1748 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
1752 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
1754 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
1755 mutex_unlock(&ps->smi_mutex);
1759 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
1761 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1763 if (port >= 0 && port < ps->num_ports)
1769 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
1771 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1772 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1778 mutex_lock(&ps->smi_mutex);
1779 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
1780 mutex_unlock(&ps->smi_mutex);
1785 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
1787 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1788 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1794 mutex_lock(&ps->smi_mutex);
1795 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
1796 mutex_unlock(&ps->smi_mutex);
1801 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
1803 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1804 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1810 mutex_lock(&ps->smi_mutex);
1811 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
1812 mutex_unlock(&ps->smi_mutex);
1817 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
1820 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1821 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
1827 mutex_lock(&ps->smi_mutex);
1828 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
1829 mutex_unlock(&ps->smi_mutex);
1833 static int __init mv88e6xxx_init(void)
1835 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1836 register_switch_driver(&mv88e6131_switch_driver);
1838 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1839 register_switch_driver(&mv88e6123_61_65_switch_driver);
1841 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1842 register_switch_driver(&mv88e6352_switch_driver);
1844 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1845 register_switch_driver(&mv88e6171_switch_driver);
1849 module_init(mv88e6xxx_init);
1851 static void __exit mv88e6xxx_cleanup(void)
1853 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1854 unregister_switch_driver(&mv88e6171_switch_driver);
1856 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1857 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
1859 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1860 unregister_switch_driver(&mv88e6131_switch_driver);
1863 module_exit(mv88e6xxx_cleanup);
1865 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
1866 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
1867 MODULE_LICENSE("GPL");