2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
36 #define MACB_RX_BUFFER_SIZE 128
37 #define RX_BUFFER_MULTIPLE 64 /* bytes */
38 #define RX_RING_SIZE 512 /* must be power of 2 */
39 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41 #define TX_RING_SIZE 128 /* must be power of 2 */
42 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44 /* level of occupied TX descriptors under which we wake up TX process */
45 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
52 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
55 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
58 * Graceful stop timeouts in us. We should allow up to
59 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
61 #define MACB_HALT_TIMEOUT 1230
63 /* Ring buffer accessors */
64 static unsigned int macb_tx_ring_wrap(unsigned int index)
66 return index & (TX_RING_SIZE - 1);
69 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
72 return &queue->tx_ring[macb_tx_ring_wrap(index)];
75 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
78 return &queue->tx_skb[macb_tx_ring_wrap(index)];
81 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
85 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
87 return queue->tx_ring_dma + offset;
90 static unsigned int macb_rx_ring_wrap(unsigned int index)
92 return index & (RX_RING_SIZE - 1);
95 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
97 return &bp->rx_ring[macb_rx_ring_wrap(index)];
100 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
102 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
105 static void macb_set_hwaddr(struct macb *bp)
110 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
111 macb_or_gem_writel(bp, SA1B, bottom);
112 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
113 macb_or_gem_writel(bp, SA1T, top);
115 /* Clear unused address register sets */
116 macb_or_gem_writel(bp, SA2B, 0);
117 macb_or_gem_writel(bp, SA2T, 0);
118 macb_or_gem_writel(bp, SA3B, 0);
119 macb_or_gem_writel(bp, SA3T, 0);
120 macb_or_gem_writel(bp, SA4B, 0);
121 macb_or_gem_writel(bp, SA4T, 0);
124 static void macb_get_hwaddr(struct macb *bp)
126 struct macb_platform_data *pdata;
132 pdata = dev_get_platdata(&bp->pdev->dev);
134 /* Check all 4 address register for vaild address */
135 for (i = 0; i < 4; i++) {
136 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
137 top = macb_or_gem_readl(bp, SA1T + i * 8);
139 if (pdata && pdata->rev_eth_addr) {
140 addr[5] = bottom & 0xff;
141 addr[4] = (bottom >> 8) & 0xff;
142 addr[3] = (bottom >> 16) & 0xff;
143 addr[2] = (bottom >> 24) & 0xff;
144 addr[1] = top & 0xff;
145 addr[0] = (top & 0xff00) >> 8;
147 addr[0] = bottom & 0xff;
148 addr[1] = (bottom >> 8) & 0xff;
149 addr[2] = (bottom >> 16) & 0xff;
150 addr[3] = (bottom >> 24) & 0xff;
151 addr[4] = top & 0xff;
152 addr[5] = (top >> 8) & 0xff;
155 if (is_valid_ether_addr(addr)) {
156 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
161 netdev_info(bp->dev, "invalid hw address, using random\n");
162 eth_hw_addr_random(bp->dev);
165 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
167 struct macb *bp = bus->priv;
170 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
171 | MACB_BF(RW, MACB_MAN_READ)
172 | MACB_BF(PHYA, mii_id)
173 | MACB_BF(REGA, regnum)
174 | MACB_BF(CODE, MACB_MAN_CODE)));
176 /* wait for end of transfer */
177 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
180 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
185 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
188 struct macb *bp = bus->priv;
190 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
191 | MACB_BF(RW, MACB_MAN_WRITE)
192 | MACB_BF(PHYA, mii_id)
193 | MACB_BF(REGA, regnum)
194 | MACB_BF(CODE, MACB_MAN_CODE)
195 | MACB_BF(DATA, value)));
197 /* wait for end of transfer */
198 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
205 * macb_set_tx_clk() - Set a clock to a new frequency
206 * @clk Pointer to the clock to change
207 * @rate New frequency in Hz
208 * @dev Pointer to the struct net_device
210 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
212 long ferr, rate, rate_rounded;
231 rate_rounded = clk_round_rate(clk, rate);
232 if (rate_rounded < 0)
235 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
238 ferr = abs(rate_rounded - rate);
239 ferr = DIV_ROUND_UP(ferr, rate / 100000);
241 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
244 if (clk_set_rate(clk, rate_rounded))
245 netdev_err(dev, "adjusting tx_clk failed.\n");
248 static void macb_handle_link_change(struct net_device *dev)
250 struct macb *bp = netdev_priv(dev);
251 struct phy_device *phydev = bp->phy_dev;
254 int status_change = 0;
256 spin_lock_irqsave(&bp->lock, flags);
259 if ((bp->speed != phydev->speed) ||
260 (bp->duplex != phydev->duplex)) {
263 reg = macb_readl(bp, NCFGR);
264 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
266 reg &= ~GEM_BIT(GBE);
270 if (phydev->speed == SPEED_100)
271 reg |= MACB_BIT(SPD);
272 if (phydev->speed == SPEED_1000 &&
273 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
276 macb_or_gem_writel(bp, NCFGR, reg);
278 bp->speed = phydev->speed;
279 bp->duplex = phydev->duplex;
284 if (phydev->link != bp->link) {
289 bp->link = phydev->link;
294 spin_unlock_irqrestore(&bp->lock, flags);
296 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
300 netif_carrier_on(dev);
301 netdev_info(dev, "link up (%d/%s)\n",
303 phydev->duplex == DUPLEX_FULL ?
306 netif_carrier_off(dev);
307 netdev_info(dev, "link down\n");
312 /* based on au1000_eth. c*/
313 static int macb_mii_probe(struct net_device *dev)
315 struct macb *bp = netdev_priv(dev);
316 struct macb_platform_data *pdata;
317 struct phy_device *phydev;
321 phydev = phy_find_first(bp->mii_bus);
323 netdev_err(dev, "no PHY found\n");
327 pdata = dev_get_platdata(&bp->pdev->dev);
328 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
329 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
331 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
332 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
336 /* attach the mac to the phy */
337 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
340 netdev_err(dev, "Could not attach to PHY\n");
344 /* mask with MAC supported features */
345 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
346 phydev->supported &= PHY_GBIT_FEATURES;
348 phydev->supported &= PHY_BASIC_FEATURES;
350 phydev->advertising = phydev->supported;
355 bp->phy_dev = phydev;
360 static int macb_mii_init(struct macb *bp)
362 struct macb_platform_data *pdata;
363 struct device_node *np;
366 /* Enable management port */
367 macb_writel(bp, NCR, MACB_BIT(MPE));
369 bp->mii_bus = mdiobus_alloc();
370 if (bp->mii_bus == NULL) {
375 bp->mii_bus->name = "MACB_mii_bus";
376 bp->mii_bus->read = &macb_mdio_read;
377 bp->mii_bus->write = &macb_mdio_write;
378 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
379 bp->pdev->name, bp->pdev->id);
380 bp->mii_bus->priv = bp;
381 bp->mii_bus->parent = &bp->dev->dev;
382 pdata = dev_get_platdata(&bp->pdev->dev);
384 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
385 if (!bp->mii_bus->irq) {
387 goto err_out_free_mdiobus;
390 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
392 np = bp->pdev->dev.of_node;
394 /* try dt phy registration */
395 err = of_mdiobus_register(bp->mii_bus, np);
397 /* fallback to standard phy registration if no phy were
398 found during dt phy registration */
399 if (!err && !phy_find_first(bp->mii_bus)) {
400 for (i = 0; i < PHY_MAX_ADDR; i++) {
401 struct phy_device *phydev;
403 phydev = mdiobus_scan(bp->mii_bus, i);
404 if (IS_ERR(phydev)) {
405 err = PTR_ERR(phydev);
411 goto err_out_unregister_bus;
414 for (i = 0; i < PHY_MAX_ADDR; i++)
415 bp->mii_bus->irq[i] = PHY_POLL;
418 bp->mii_bus->phy_mask = pdata->phy_mask;
420 err = mdiobus_register(bp->mii_bus);
424 goto err_out_free_mdio_irq;
426 err = macb_mii_probe(bp->dev);
428 goto err_out_unregister_bus;
432 err_out_unregister_bus:
433 mdiobus_unregister(bp->mii_bus);
434 err_out_free_mdio_irq:
435 kfree(bp->mii_bus->irq);
436 err_out_free_mdiobus:
437 mdiobus_free(bp->mii_bus);
442 static void macb_update_stats(struct macb *bp)
444 u32 __iomem *reg = bp->regs + MACB_PFR;
445 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
446 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
448 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
450 for(; p < end; p++, reg++)
451 *p += readl_relaxed(reg);
454 static int macb_halt_tx(struct macb *bp)
456 unsigned long halt_time, timeout;
459 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
461 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
464 status = macb_readl(bp, TSR);
465 if (!(status & MACB_BIT(TGO)))
468 usleep_range(10, 250);
469 } while (time_before(halt_time, timeout));
474 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
476 if (tx_skb->mapping) {
477 if (tx_skb->mapped_as_page)
478 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
479 tx_skb->size, DMA_TO_DEVICE);
481 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
482 tx_skb->size, DMA_TO_DEVICE);
487 dev_kfree_skb_any(tx_skb->skb);
492 static void macb_tx_error_task(struct work_struct *work)
494 struct macb_queue *queue = container_of(work, struct macb_queue,
496 struct macb *bp = queue->bp;
497 struct macb_tx_skb *tx_skb;
498 struct macb_dma_desc *desc;
503 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
504 (unsigned int)(queue - bp->queues),
505 queue->tx_tail, queue->tx_head);
507 /* Prevent the queue IRQ handlers from running: each of them may call
508 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
509 * As explained below, we have to halt the transmission before updating
510 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
511 * network engine about the macb/gem being halted.
513 spin_lock_irqsave(&bp->lock, flags);
515 /* Make sure nobody is trying to queue up new packets */
516 netif_tx_stop_all_queues(bp->dev);
519 * Stop transmission now
520 * (in case we have just queued new packets)
521 * macb/gem must be halted to write TBQP register
523 if (macb_halt_tx(bp))
524 /* Just complain for now, reinitializing TX path can be good */
525 netdev_err(bp->dev, "BUG: halt tx timed out\n");
528 * Treat frames in TX queue including the ones that caused the error.
529 * Free transmit buffers in upper layer.
531 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
534 desc = macb_tx_desc(queue, tail);
536 tx_skb = macb_tx_skb(queue, tail);
539 if (ctrl & MACB_BIT(TX_USED)) {
540 /* skb is set for the last buffer of the frame */
542 macb_tx_unmap(bp, tx_skb);
544 tx_skb = macb_tx_skb(queue, tail);
548 /* ctrl still refers to the first buffer descriptor
549 * since it's the only one written back by the hardware
551 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
552 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
553 macb_tx_ring_wrap(tail), skb->data);
554 bp->stats.tx_packets++;
555 bp->stats.tx_bytes += skb->len;
559 * "Buffers exhausted mid-frame" errors may only happen
560 * if the driver is buggy, so complain loudly about those.
561 * Statistics are updated by hardware.
563 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
565 "BUG: TX buffers exhausted mid-frame\n");
567 desc->ctrl = ctrl | MACB_BIT(TX_USED);
570 macb_tx_unmap(bp, tx_skb);
573 /* Set end of TX queue */
574 desc = macb_tx_desc(queue, 0);
576 desc->ctrl = MACB_BIT(TX_USED);
578 /* Make descriptor updates visible to hardware */
581 /* Reinitialize the TX desc queue */
582 queue_writel(queue, TBQP, queue->tx_ring_dma);
583 /* Make TX ring reflect state of hardware */
587 /* Housework before enabling TX IRQ */
588 macb_writel(bp, TSR, macb_readl(bp, TSR));
589 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
591 /* Now we are ready to start transmission again */
592 netif_tx_start_all_queues(bp->dev);
593 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
595 spin_unlock_irqrestore(&bp->lock, flags);
598 static void macb_tx_interrupt(struct macb_queue *queue)
603 struct macb *bp = queue->bp;
604 u16 queue_index = queue - bp->queues;
606 status = macb_readl(bp, TSR);
607 macb_writel(bp, TSR, status);
609 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
610 queue_writel(queue, ISR, MACB_BIT(TCOMP));
612 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
613 (unsigned long)status);
615 head = queue->tx_head;
616 for (tail = queue->tx_tail; tail != head; tail++) {
617 struct macb_tx_skb *tx_skb;
619 struct macb_dma_desc *desc;
622 desc = macb_tx_desc(queue, tail);
624 /* Make hw descriptor updates visible to CPU */
629 /* TX_USED bit is only set by hardware on the very first buffer
630 * descriptor of the transmitted frame.
632 if (!(ctrl & MACB_BIT(TX_USED)))
635 /* Process all buffers of the current transmitted frame */
637 tx_skb = macb_tx_skb(queue, tail);
640 /* First, update TX stats if needed */
642 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
643 macb_tx_ring_wrap(tail), skb->data);
644 bp->stats.tx_packets++;
645 bp->stats.tx_bytes += skb->len;
648 /* Now we can safely release resources */
649 macb_tx_unmap(bp, tx_skb);
651 /* skb is set only for the last buffer of the frame.
652 * WARNING: at this point skb has been freed by
660 queue->tx_tail = tail;
661 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
662 CIRC_CNT(queue->tx_head, queue->tx_tail,
663 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
664 netif_wake_subqueue(bp->dev, queue_index);
667 static void gem_rx_refill(struct macb *bp)
673 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
674 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
676 /* Make hw descriptor updates visible to CPU */
679 bp->rx_prepared_head++;
681 if (bp->rx_skbuff[entry] == NULL) {
682 /* allocate sk_buff for this free entry in ring */
683 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
684 if (unlikely(skb == NULL)) {
686 "Unable to allocate sk_buff\n");
690 /* now fill corresponding descriptor entry */
691 paddr = dma_map_single(&bp->pdev->dev, skb->data,
692 bp->rx_buffer_size, DMA_FROM_DEVICE);
693 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
698 bp->rx_skbuff[entry] = skb;
700 if (entry == RX_RING_SIZE - 1)
701 paddr |= MACB_BIT(RX_WRAP);
702 bp->rx_ring[entry].addr = paddr;
703 bp->rx_ring[entry].ctrl = 0;
705 /* properly align Ethernet header */
706 skb_reserve(skb, NET_IP_ALIGN);
710 /* Make descriptor updates visible to hardware */
713 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
714 bp->rx_prepared_head, bp->rx_tail);
717 /* Mark DMA descriptors from begin up to and not including end as unused */
718 static void discard_partial_frame(struct macb *bp, unsigned int begin,
723 for (frag = begin; frag != end; frag++) {
724 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
725 desc->addr &= ~MACB_BIT(RX_USED);
728 /* Make descriptor updates visible to hardware */
732 * When this happens, the hardware stats registers for
733 * whatever caused this is updated, so we don't have to record
738 static int gem_rx(struct macb *bp, int budget)
743 struct macb_dma_desc *desc;
746 while (count < budget) {
749 entry = macb_rx_ring_wrap(bp->rx_tail);
750 desc = &bp->rx_ring[entry];
752 /* Make hw descriptor updates visible to CPU */
758 if (!(addr & MACB_BIT(RX_USED)))
764 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
766 "not whole frame pointed by descriptor\n");
767 bp->stats.rx_dropped++;
770 skb = bp->rx_skbuff[entry];
771 if (unlikely(!skb)) {
773 "inconsistent Rx descriptor chain\n");
774 bp->stats.rx_dropped++;
777 /* now everything is ready for receiving packet */
778 bp->rx_skbuff[entry] = NULL;
779 len = MACB_BFEXT(RX_FRMLEN, ctrl);
781 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
784 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
785 dma_unmap_single(&bp->pdev->dev, addr,
786 bp->rx_buffer_size, DMA_FROM_DEVICE);
788 skb->protocol = eth_type_trans(skb, bp->dev);
789 skb_checksum_none_assert(skb);
790 if (bp->dev->features & NETIF_F_RXCSUM &&
791 !(bp->dev->flags & IFF_PROMISC) &&
792 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
793 skb->ip_summed = CHECKSUM_UNNECESSARY;
795 bp->stats.rx_packets++;
796 bp->stats.rx_bytes += skb->len;
798 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
799 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
800 skb->len, skb->csum);
801 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
802 skb_mac_header(skb), 16, true);
803 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
804 skb->data, 32, true);
807 netif_receive_skb(skb);
815 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
816 unsigned int last_frag)
822 struct macb_dma_desc *desc;
824 desc = macb_rx_desc(bp, last_frag);
825 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
827 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
828 macb_rx_ring_wrap(first_frag),
829 macb_rx_ring_wrap(last_frag), len);
832 * The ethernet header starts NET_IP_ALIGN bytes into the
833 * first buffer. Since the header is 14 bytes, this makes the
834 * payload word-aligned.
836 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
837 * the two padding bytes into the skb so that we avoid hitting
838 * the slowpath in memcpy(), and pull them off afterwards.
840 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
842 bp->stats.rx_dropped++;
843 for (frag = first_frag; ; frag++) {
844 desc = macb_rx_desc(bp, frag);
845 desc->addr &= ~MACB_BIT(RX_USED);
846 if (frag == last_frag)
850 /* Make descriptor updates visible to hardware */
858 skb_checksum_none_assert(skb);
861 for (frag = first_frag; ; frag++) {
862 unsigned int frag_len = bp->rx_buffer_size;
864 if (offset + frag_len > len) {
865 BUG_ON(frag != last_frag);
866 frag_len = len - offset;
868 skb_copy_to_linear_data_offset(skb, offset,
869 macb_rx_buffer(bp, frag), frag_len);
870 offset += bp->rx_buffer_size;
871 desc = macb_rx_desc(bp, frag);
872 desc->addr &= ~MACB_BIT(RX_USED);
874 if (frag == last_frag)
878 /* Make descriptor updates visible to hardware */
881 __skb_pull(skb, NET_IP_ALIGN);
882 skb->protocol = eth_type_trans(skb, bp->dev);
884 bp->stats.rx_packets++;
885 bp->stats.rx_bytes += skb->len;
886 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
887 skb->len, skb->csum);
888 netif_receive_skb(skb);
893 static int macb_rx(struct macb *bp, int budget)
899 for (tail = bp->rx_tail; budget > 0; tail++) {
900 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
903 /* Make hw descriptor updates visible to CPU */
909 if (!(addr & MACB_BIT(RX_USED)))
912 if (ctrl & MACB_BIT(RX_SOF)) {
913 if (first_frag != -1)
914 discard_partial_frame(bp, first_frag, tail);
918 if (ctrl & MACB_BIT(RX_EOF)) {
920 BUG_ON(first_frag == -1);
922 dropped = macb_rx_frame(bp, first_frag, tail);
931 if (first_frag != -1)
932 bp->rx_tail = first_frag;
939 static int macb_poll(struct napi_struct *napi, int budget)
941 struct macb *bp = container_of(napi, struct macb, napi);
945 status = macb_readl(bp, RSR);
946 macb_writel(bp, RSR, status);
950 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
951 (unsigned long)status, budget);
953 work_done = bp->macbgem_ops.mog_rx(bp, budget);
954 if (work_done < budget) {
957 /* Packets received while interrupts were disabled */
958 status = macb_readl(bp, RSR);
960 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
961 macb_writel(bp, ISR, MACB_BIT(RCOMP));
962 napi_reschedule(napi);
964 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
968 /* TODO: Handle errors */
973 static irqreturn_t macb_interrupt(int irq, void *dev_id)
975 struct macb_queue *queue = dev_id;
976 struct macb *bp = queue->bp;
977 struct net_device *dev = bp->dev;
980 status = queue_readl(queue, ISR);
982 if (unlikely(!status))
985 spin_lock(&bp->lock);
988 /* close possible race with dev_close */
989 if (unlikely(!netif_running(dev))) {
990 queue_writel(queue, IDR, -1);
994 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
995 (unsigned int)(queue - bp->queues),
996 (unsigned long)status);
998 if (status & MACB_RX_INT_FLAGS) {
1000 * There's no point taking any more interrupts
1001 * until we have processed the buffers. The
1002 * scheduling call may fail if the poll routine
1003 * is already scheduled, so disable interrupts
1006 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1007 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1008 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1010 if (napi_schedule_prep(&bp->napi)) {
1011 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1012 __napi_schedule(&bp->napi);
1016 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1017 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1018 schedule_work(&queue->tx_error_task);
1020 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1021 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1026 if (status & MACB_BIT(TCOMP))
1027 macb_tx_interrupt(queue);
1030 * Link change detection isn't possible with RMII, so we'll
1031 * add that if/when we get our hands on a full-blown MII PHY.
1034 if (status & MACB_BIT(ISR_ROVR)) {
1035 /* We missed at least one packet */
1036 if (macb_is_gem(bp))
1037 bp->hw_stats.gem.rx_overruns++;
1039 bp->hw_stats.macb.rx_overruns++;
1041 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1042 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1045 if (status & MACB_BIT(HRESP)) {
1047 * TODO: Reset the hardware, and maybe move the
1048 * netdev_err to a lower-priority context as well
1051 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1053 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1054 queue_writel(queue, ISR, MACB_BIT(HRESP));
1057 status = queue_readl(queue, ISR);
1060 spin_unlock(&bp->lock);
1065 #ifdef CONFIG_NET_POLL_CONTROLLER
1067 * Polling receive - used by netconsole and other diagnostic tools
1068 * to allow network i/o with interrupts disabled.
1070 static void macb_poll_controller(struct net_device *dev)
1072 struct macb *bp = netdev_priv(dev);
1073 struct macb_queue *queue;
1074 unsigned long flags;
1077 local_irq_save(flags);
1078 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1079 macb_interrupt(dev->irq, queue);
1080 local_irq_restore(flags);
1084 static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1087 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1090 static unsigned int macb_tx_map(struct macb *bp,
1091 struct macb_queue *queue,
1092 struct sk_buff *skb)
1095 unsigned int len, entry, i, tx_head = queue->tx_head;
1096 struct macb_tx_skb *tx_skb = NULL;
1097 struct macb_dma_desc *desc;
1098 unsigned int offset, size, count = 0;
1099 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1100 unsigned int eof = 1;
1103 /* First, map non-paged data */
1104 len = skb_headlen(skb);
1107 size = min(len, bp->max_tx_length);
1108 entry = macb_tx_ring_wrap(tx_head);
1109 tx_skb = &queue->tx_skb[entry];
1111 mapping = dma_map_single(&bp->pdev->dev,
1113 size, DMA_TO_DEVICE);
1114 if (dma_mapping_error(&bp->pdev->dev, mapping))
1117 /* Save info to properly release resources */
1119 tx_skb->mapping = mapping;
1120 tx_skb->size = size;
1121 tx_skb->mapped_as_page = false;
1129 /* Then, map paged data from fragments */
1130 for (f = 0; f < nr_frags; f++) {
1131 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1133 len = skb_frag_size(frag);
1136 size = min(len, bp->max_tx_length);
1137 entry = macb_tx_ring_wrap(tx_head);
1138 tx_skb = &queue->tx_skb[entry];
1140 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1141 offset, size, DMA_TO_DEVICE);
1142 if (dma_mapping_error(&bp->pdev->dev, mapping))
1145 /* Save info to properly release resources */
1147 tx_skb->mapping = mapping;
1148 tx_skb->size = size;
1149 tx_skb->mapped_as_page = true;
1158 /* Should never happen */
1159 if (unlikely(tx_skb == NULL)) {
1160 netdev_err(bp->dev, "BUG! empty skb!\n");
1164 /* This is the last buffer of the frame: save socket buffer */
1167 /* Update TX ring: update buffer descriptors in reverse order
1168 * to avoid race condition
1171 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1172 * to set the end of TX queue
1175 entry = macb_tx_ring_wrap(i);
1176 ctrl = MACB_BIT(TX_USED);
1177 desc = &queue->tx_ring[entry];
1182 entry = macb_tx_ring_wrap(i);
1183 tx_skb = &queue->tx_skb[entry];
1184 desc = &queue->tx_ring[entry];
1186 ctrl = (u32)tx_skb->size;
1188 ctrl |= MACB_BIT(TX_LAST);
1191 if (unlikely(entry == (TX_RING_SIZE - 1)))
1192 ctrl |= MACB_BIT(TX_WRAP);
1194 /* Set TX buffer descriptor */
1195 desc->addr = tx_skb->mapping;
1196 /* desc->addr must be visible to hardware before clearing
1197 * 'TX_USED' bit in desc->ctrl.
1201 } while (i != queue->tx_head);
1203 queue->tx_head = tx_head;
1208 netdev_err(bp->dev, "TX DMA map failed\n");
1210 for (i = queue->tx_head; i != tx_head; i++) {
1211 tx_skb = macb_tx_skb(queue, i);
1213 macb_tx_unmap(bp, tx_skb);
1219 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1221 u16 queue_index = skb_get_queue_mapping(skb);
1222 struct macb *bp = netdev_priv(dev);
1223 struct macb_queue *queue = &bp->queues[queue_index];
1224 unsigned long flags;
1225 unsigned int count, nr_frags, frag_size, f;
1227 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1228 netdev_vdbg(bp->dev,
1229 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1230 queue_index, skb->len, skb->head, skb->data,
1231 skb_tail_pointer(skb), skb_end_pointer(skb));
1232 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1233 skb->data, 16, true);
1236 /* Count how many TX buffer descriptors are needed to send this
1237 * socket buffer: skb fragments of jumbo frames may need to be
1238 * splitted into many buffer descriptors.
1240 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1241 nr_frags = skb_shinfo(skb)->nr_frags;
1242 for (f = 0; f < nr_frags; f++) {
1243 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1244 count += macb_count_tx_descriptors(bp, frag_size);
1247 spin_lock_irqsave(&bp->lock, flags);
1249 /* This is a hard error, log it. */
1250 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1251 netif_stop_subqueue(dev, queue_index);
1252 spin_unlock_irqrestore(&bp->lock, flags);
1253 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1254 queue->tx_head, queue->tx_tail);
1255 return NETDEV_TX_BUSY;
1258 /* Map socket buffer for DMA transfer */
1259 if (!macb_tx_map(bp, queue, skb)) {
1260 dev_kfree_skb_any(skb);
1264 /* Make newly initialized descriptor visible to hardware */
1267 skb_tx_timestamp(skb);
1269 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1271 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1272 netif_stop_subqueue(dev, queue_index);
1275 spin_unlock_irqrestore(&bp->lock, flags);
1277 return NETDEV_TX_OK;
1280 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1282 if (!macb_is_gem(bp)) {
1283 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1285 bp->rx_buffer_size = size;
1287 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1289 "RX buffer must be multiple of %d bytes, expanding\n",
1290 RX_BUFFER_MULTIPLE);
1291 bp->rx_buffer_size =
1292 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1296 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1297 bp->dev->mtu, bp->rx_buffer_size);
1300 static void gem_free_rx_buffers(struct macb *bp)
1302 struct sk_buff *skb;
1303 struct macb_dma_desc *desc;
1310 for (i = 0; i < RX_RING_SIZE; i++) {
1311 skb = bp->rx_skbuff[i];
1316 desc = &bp->rx_ring[i];
1317 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1318 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1320 dev_kfree_skb_any(skb);
1324 kfree(bp->rx_skbuff);
1325 bp->rx_skbuff = NULL;
1328 static void macb_free_rx_buffers(struct macb *bp)
1330 if (bp->rx_buffers) {
1331 dma_free_coherent(&bp->pdev->dev,
1332 RX_RING_SIZE * bp->rx_buffer_size,
1333 bp->rx_buffers, bp->rx_buffers_dma);
1334 bp->rx_buffers = NULL;
1338 static void macb_free_consistent(struct macb *bp)
1340 struct macb_queue *queue;
1343 bp->macbgem_ops.mog_free_rx_buffers(bp);
1345 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1346 bp->rx_ring, bp->rx_ring_dma);
1350 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1351 kfree(queue->tx_skb);
1352 queue->tx_skb = NULL;
1353 if (queue->tx_ring) {
1354 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1355 queue->tx_ring, queue->tx_ring_dma);
1356 queue->tx_ring = NULL;
1361 static int gem_alloc_rx_buffers(struct macb *bp)
1365 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1366 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1371 "Allocated %d RX struct sk_buff entries at %p\n",
1372 RX_RING_SIZE, bp->rx_skbuff);
1376 static int macb_alloc_rx_buffers(struct macb *bp)
1380 size = RX_RING_SIZE * bp->rx_buffer_size;
1381 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1382 &bp->rx_buffers_dma, GFP_KERNEL);
1383 if (!bp->rx_buffers)
1387 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1388 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1392 static int macb_alloc_consistent(struct macb *bp)
1394 struct macb_queue *queue;
1398 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1399 size = TX_RING_BYTES;
1400 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1401 &queue->tx_ring_dma,
1403 if (!queue->tx_ring)
1406 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1407 q, size, (unsigned long)queue->tx_ring_dma,
1410 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1411 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1416 size = RX_RING_BYTES;
1417 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1418 &bp->rx_ring_dma, GFP_KERNEL);
1422 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1423 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1425 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1431 macb_free_consistent(bp);
1435 static void gem_init_rings(struct macb *bp)
1437 struct macb_queue *queue;
1441 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1442 for (i = 0; i < TX_RING_SIZE; i++) {
1443 queue->tx_ring[i].addr = 0;
1444 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1446 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1452 bp->rx_prepared_head = 0;
1457 static void macb_init_rings(struct macb *bp)
1462 addr = bp->rx_buffers_dma;
1463 for (i = 0; i < RX_RING_SIZE; i++) {
1464 bp->rx_ring[i].addr = addr;
1465 bp->rx_ring[i].ctrl = 0;
1466 addr += bp->rx_buffer_size;
1468 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1470 for (i = 0; i < TX_RING_SIZE; i++) {
1471 bp->queues[0].tx_ring[i].addr = 0;
1472 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1473 bp->queues[0].tx_head = 0;
1474 bp->queues[0].tx_tail = 0;
1476 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1481 static void macb_reset_hw(struct macb *bp)
1483 struct macb_queue *queue;
1487 * Disable RX and TX (XXX: Should we halt the transmission
1490 macb_writel(bp, NCR, 0);
1492 /* Clear the stats registers (XXX: Update stats first?) */
1493 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1495 /* Clear all status flags */
1496 macb_writel(bp, TSR, -1);
1497 macb_writel(bp, RSR, -1);
1499 /* Disable all interrupts */
1500 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1501 queue_writel(queue, IDR, -1);
1502 queue_readl(queue, ISR);
1506 static u32 gem_mdc_clk_div(struct macb *bp)
1509 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1511 if (pclk_hz <= 20000000)
1512 config = GEM_BF(CLK, GEM_CLK_DIV8);
1513 else if (pclk_hz <= 40000000)
1514 config = GEM_BF(CLK, GEM_CLK_DIV16);
1515 else if (pclk_hz <= 80000000)
1516 config = GEM_BF(CLK, GEM_CLK_DIV32);
1517 else if (pclk_hz <= 120000000)
1518 config = GEM_BF(CLK, GEM_CLK_DIV48);
1519 else if (pclk_hz <= 160000000)
1520 config = GEM_BF(CLK, GEM_CLK_DIV64);
1522 config = GEM_BF(CLK, GEM_CLK_DIV96);
1527 static u32 macb_mdc_clk_div(struct macb *bp)
1530 unsigned long pclk_hz;
1532 if (macb_is_gem(bp))
1533 return gem_mdc_clk_div(bp);
1535 pclk_hz = clk_get_rate(bp->pclk);
1536 if (pclk_hz <= 20000000)
1537 config = MACB_BF(CLK, MACB_CLK_DIV8);
1538 else if (pclk_hz <= 40000000)
1539 config = MACB_BF(CLK, MACB_CLK_DIV16);
1540 else if (pclk_hz <= 80000000)
1541 config = MACB_BF(CLK, MACB_CLK_DIV32);
1543 config = MACB_BF(CLK, MACB_CLK_DIV64);
1549 * Get the DMA bus width field of the network configuration register that we
1550 * should program. We find the width from decoding the design configuration
1551 * register to find the maximum supported data bus width.
1553 static u32 macb_dbw(struct macb *bp)
1555 if (!macb_is_gem(bp))
1558 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1560 return GEM_BF(DBW, GEM_DBW128);
1562 return GEM_BF(DBW, GEM_DBW64);
1565 return GEM_BF(DBW, GEM_DBW32);
1570 * Configure the receive DMA engine
1571 * - use the correct receive buffer size
1572 * - set best burst length for DMA operations
1573 * (if not supported by FIFO, it will fallback to default)
1574 * - set both rx/tx packet buffers to full memory size
1575 * These are configurable parameters for GEM.
1577 static void macb_configure_dma(struct macb *bp)
1582 if (macb_is_gem(bp)) {
1583 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1584 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1585 if (bp->dma_burst_length)
1586 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1587 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1588 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1590 /* Find the CPU endianness by using the loopback bit of net_ctrl
1591 * register. save it first. When the CPU is in big endian we
1592 * need to program swaped mode for management descriptor access.
1594 ncr = macb_readl(bp, NCR);
1595 __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
1596 tmp = __raw_readl(bp->regs + MACB_NCR);
1598 if (tmp == MACB_BIT(LLB))
1599 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1601 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1603 /* Restore net_ctrl */
1604 macb_writel(bp, NCR, ncr);
1606 if (bp->dev->features & NETIF_F_HW_CSUM)
1607 dmacfg |= GEM_BIT(TXCOEN);
1609 dmacfg &= ~GEM_BIT(TXCOEN);
1610 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1612 gem_writel(bp, DMACFG, dmacfg);
1616 static void macb_init_hw(struct macb *bp)
1618 struct macb_queue *queue;
1624 macb_set_hwaddr(bp);
1626 config = macb_mdc_clk_div(bp);
1627 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1628 config |= MACB_BIT(PAE); /* PAuse Enable */
1629 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1630 config |= MACB_BIT(BIG); /* Receive oversized frames */
1631 if (bp->dev->flags & IFF_PROMISC)
1632 config |= MACB_BIT(CAF); /* Copy All Frames */
1633 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1634 config |= GEM_BIT(RXCOEN);
1635 if (!(bp->dev->flags & IFF_BROADCAST))
1636 config |= MACB_BIT(NBC); /* No BroadCast */
1637 config |= macb_dbw(bp);
1638 macb_writel(bp, NCFGR, config);
1639 bp->speed = SPEED_10;
1640 bp->duplex = DUPLEX_HALF;
1642 macb_configure_dma(bp);
1644 /* Initialize TX and RX buffers */
1645 macb_writel(bp, RBQP, bp->rx_ring_dma);
1646 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1647 queue_writel(queue, TBQP, queue->tx_ring_dma);
1649 /* Enable interrupts */
1650 queue_writel(queue, IER,
1656 /* Enable TX and RX */
1657 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1661 * The hash address register is 64 bits long and takes up two
1662 * locations in the memory map. The least significant bits are stored
1663 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1665 * The unicast hash enable and the multicast hash enable bits in the
1666 * network configuration register enable the reception of hash matched
1667 * frames. The destination address is reduced to a 6 bit index into
1668 * the 64 bit hash register using the following hash function. The
1669 * hash function is an exclusive or of every sixth bit of the
1670 * destination address.
1672 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1673 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1674 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1675 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1676 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1677 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1679 * da[0] represents the least significant bit of the first byte
1680 * received, that is, the multicast/unicast indicator, and da[47]
1681 * represents the most significant bit of the last byte received. If
1682 * the hash index, hi[n], points to a bit that is set in the hash
1683 * register then the frame will be matched according to whether the
1684 * frame is multicast or unicast. A multicast match will be signalled
1685 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1686 * index points to a bit set in the hash register. A unicast match
1687 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1688 * and the hash index points to a bit set in the hash register. To
1689 * receive all multicast frames, the hash register should be set with
1690 * all ones and the multicast hash enable bit should be set in the
1691 * network configuration register.
1694 static inline int hash_bit_value(int bitnr, __u8 *addr)
1696 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1702 * Return the hash index value for the specified address.
1704 static int hash_get_index(__u8 *addr)
1709 for (j = 0; j < 6; j++) {
1710 for (i = 0, bitval = 0; i < 8; i++)
1711 bitval ^= hash_bit_value(i * 6 + j, addr);
1713 hash_index |= (bitval << j);
1720 * Add multicast addresses to the internal multicast-hash table.
1722 static void macb_sethashtable(struct net_device *dev)
1724 struct netdev_hw_addr *ha;
1725 unsigned long mc_filter[2];
1727 struct macb *bp = netdev_priv(dev);
1729 mc_filter[0] = mc_filter[1] = 0;
1731 netdev_for_each_mc_addr(ha, dev) {
1732 bitnr = hash_get_index(ha->addr);
1733 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1736 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1737 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1741 * Enable/Disable promiscuous and multicast modes.
1743 static void macb_set_rx_mode(struct net_device *dev)
1746 struct macb *bp = netdev_priv(dev);
1748 cfg = macb_readl(bp, NCFGR);
1750 if (dev->flags & IFF_PROMISC) {
1751 /* Enable promiscuous mode */
1752 cfg |= MACB_BIT(CAF);
1754 /* Disable RX checksum offload */
1755 if (macb_is_gem(bp))
1756 cfg &= ~GEM_BIT(RXCOEN);
1758 /* Disable promiscuous mode */
1759 cfg &= ~MACB_BIT(CAF);
1761 /* Enable RX checksum offload only if requested */
1762 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1763 cfg |= GEM_BIT(RXCOEN);
1766 if (dev->flags & IFF_ALLMULTI) {
1767 /* Enable all multicast mode */
1768 macb_or_gem_writel(bp, HRB, -1);
1769 macb_or_gem_writel(bp, HRT, -1);
1770 cfg |= MACB_BIT(NCFGR_MTI);
1771 } else if (!netdev_mc_empty(dev)) {
1772 /* Enable specific multicasts */
1773 macb_sethashtable(dev);
1774 cfg |= MACB_BIT(NCFGR_MTI);
1775 } else if (dev->flags & (~IFF_ALLMULTI)) {
1776 /* Disable all multicast mode */
1777 macb_or_gem_writel(bp, HRB, 0);
1778 macb_or_gem_writel(bp, HRT, 0);
1779 cfg &= ~MACB_BIT(NCFGR_MTI);
1782 macb_writel(bp, NCFGR, cfg);
1785 static int macb_open(struct net_device *dev)
1787 struct macb *bp = netdev_priv(dev);
1788 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1791 netdev_dbg(bp->dev, "open\n");
1793 /* carrier starts down */
1794 netif_carrier_off(dev);
1796 /* if the phy is not yet register, retry later*/
1800 /* RX buffers initialization */
1801 macb_init_rx_buffer_size(bp, bufsz);
1803 err = macb_alloc_consistent(bp);
1805 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1810 napi_enable(&bp->napi);
1812 bp->macbgem_ops.mog_init_rings(bp);
1815 /* schedule a link state check */
1816 phy_start(bp->phy_dev);
1818 netif_tx_start_all_queues(dev);
1823 static int macb_close(struct net_device *dev)
1825 struct macb *bp = netdev_priv(dev);
1826 unsigned long flags;
1828 netif_tx_stop_all_queues(dev);
1829 napi_disable(&bp->napi);
1832 phy_stop(bp->phy_dev);
1834 spin_lock_irqsave(&bp->lock, flags);
1836 netif_carrier_off(dev);
1837 spin_unlock_irqrestore(&bp->lock, flags);
1839 macb_free_consistent(bp);
1844 static void gem_update_stats(struct macb *bp)
1847 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1849 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1850 u32 offset = gem_statistics[i].offset;
1851 u64 val = readl_relaxed(bp->regs + offset);
1853 bp->ethtool_stats[i] += val;
1856 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1857 /* Add GEM_OCTTXH, GEM_OCTRXH */
1858 val = readl_relaxed(bp->regs + offset + 4);
1859 bp->ethtool_stats[i] += ((u64)val) << 32;
1865 static struct net_device_stats *gem_get_stats(struct macb *bp)
1867 struct gem_stats *hwstat = &bp->hw_stats.gem;
1868 struct net_device_stats *nstat = &bp->stats;
1870 gem_update_stats(bp);
1872 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1873 hwstat->rx_alignment_errors +
1874 hwstat->rx_resource_errors +
1875 hwstat->rx_overruns +
1876 hwstat->rx_oversize_frames +
1877 hwstat->rx_jabbers +
1878 hwstat->rx_undersized_frames +
1879 hwstat->rx_length_field_frame_errors);
1880 nstat->tx_errors = (hwstat->tx_late_collisions +
1881 hwstat->tx_excessive_collisions +
1882 hwstat->tx_underrun +
1883 hwstat->tx_carrier_sense_errors);
1884 nstat->multicast = hwstat->rx_multicast_frames;
1885 nstat->collisions = (hwstat->tx_single_collision_frames +
1886 hwstat->tx_multiple_collision_frames +
1887 hwstat->tx_excessive_collisions);
1888 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1889 hwstat->rx_jabbers +
1890 hwstat->rx_undersized_frames +
1891 hwstat->rx_length_field_frame_errors);
1892 nstat->rx_over_errors = hwstat->rx_resource_errors;
1893 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1894 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1895 nstat->rx_fifo_errors = hwstat->rx_overruns;
1896 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1897 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1898 nstat->tx_fifo_errors = hwstat->tx_underrun;
1903 static void gem_get_ethtool_stats(struct net_device *dev,
1904 struct ethtool_stats *stats, u64 *data)
1908 bp = netdev_priv(dev);
1909 gem_update_stats(bp);
1910 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
1913 static int gem_get_sset_count(struct net_device *dev, int sset)
1917 return GEM_STATS_LEN;
1923 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
1929 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
1930 memcpy(p, gem_statistics[i].stat_string,
1936 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1938 struct macb *bp = netdev_priv(dev);
1939 struct net_device_stats *nstat = &bp->stats;
1940 struct macb_stats *hwstat = &bp->hw_stats.macb;
1942 if (macb_is_gem(bp))
1943 return gem_get_stats(bp);
1945 /* read stats from hardware */
1946 macb_update_stats(bp);
1948 /* Convert HW stats into netdevice stats */
1949 nstat->rx_errors = (hwstat->rx_fcs_errors +
1950 hwstat->rx_align_errors +
1951 hwstat->rx_resource_errors +
1952 hwstat->rx_overruns +
1953 hwstat->rx_oversize_pkts +
1954 hwstat->rx_jabbers +
1955 hwstat->rx_undersize_pkts +
1956 hwstat->sqe_test_errors +
1957 hwstat->rx_length_mismatch);
1958 nstat->tx_errors = (hwstat->tx_late_cols +
1959 hwstat->tx_excessive_cols +
1960 hwstat->tx_underruns +
1961 hwstat->tx_carrier_errors);
1962 nstat->collisions = (hwstat->tx_single_cols +
1963 hwstat->tx_multiple_cols +
1964 hwstat->tx_excessive_cols);
1965 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1966 hwstat->rx_jabbers +
1967 hwstat->rx_undersize_pkts +
1968 hwstat->rx_length_mismatch);
1969 nstat->rx_over_errors = hwstat->rx_resource_errors +
1970 hwstat->rx_overruns;
1971 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1972 nstat->rx_frame_errors = hwstat->rx_align_errors;
1973 nstat->rx_fifo_errors = hwstat->rx_overruns;
1974 /* XXX: What does "missed" mean? */
1975 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1976 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1977 nstat->tx_fifo_errors = hwstat->tx_underruns;
1978 /* Don't know about heartbeat or window errors... */
1983 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1985 struct macb *bp = netdev_priv(dev);
1986 struct phy_device *phydev = bp->phy_dev;
1991 return phy_ethtool_gset(phydev, cmd);
1994 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1996 struct macb *bp = netdev_priv(dev);
1997 struct phy_device *phydev = bp->phy_dev;
2002 return phy_ethtool_sset(phydev, cmd);
2005 static int macb_get_regs_len(struct net_device *netdev)
2007 return MACB_GREGS_NBR * sizeof(u32);
2010 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2013 struct macb *bp = netdev_priv(dev);
2014 unsigned int tail, head;
2017 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2018 | MACB_GREGS_VERSION;
2020 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2021 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2023 regs_buff[0] = macb_readl(bp, NCR);
2024 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2025 regs_buff[2] = macb_readl(bp, NSR);
2026 regs_buff[3] = macb_readl(bp, TSR);
2027 regs_buff[4] = macb_readl(bp, RBQP);
2028 regs_buff[5] = macb_readl(bp, TBQP);
2029 regs_buff[6] = macb_readl(bp, RSR);
2030 regs_buff[7] = macb_readl(bp, IMR);
2032 regs_buff[8] = tail;
2033 regs_buff[9] = head;
2034 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2035 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2037 if (macb_is_gem(bp)) {
2038 regs_buff[12] = gem_readl(bp, USRIO);
2039 regs_buff[13] = gem_readl(bp, DMACFG);
2043 static const struct ethtool_ops macb_ethtool_ops = {
2044 .get_settings = macb_get_settings,
2045 .set_settings = macb_set_settings,
2046 .get_regs_len = macb_get_regs_len,
2047 .get_regs = macb_get_regs,
2048 .get_link = ethtool_op_get_link,
2049 .get_ts_info = ethtool_op_get_ts_info,
2052 static const struct ethtool_ops gem_ethtool_ops = {
2053 .get_settings = macb_get_settings,
2054 .set_settings = macb_set_settings,
2055 .get_regs_len = macb_get_regs_len,
2056 .get_regs = macb_get_regs,
2057 .get_link = ethtool_op_get_link,
2058 .get_ts_info = ethtool_op_get_ts_info,
2059 .get_ethtool_stats = gem_get_ethtool_stats,
2060 .get_strings = gem_get_ethtool_strings,
2061 .get_sset_count = gem_get_sset_count,
2064 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2066 struct macb *bp = netdev_priv(dev);
2067 struct phy_device *phydev = bp->phy_dev;
2069 if (!netif_running(dev))
2075 return phy_mii_ioctl(phydev, rq, cmd);
2078 static int macb_set_features(struct net_device *netdev,
2079 netdev_features_t features)
2081 struct macb *bp = netdev_priv(netdev);
2082 netdev_features_t changed = features ^ netdev->features;
2084 /* TX checksum offload */
2085 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2088 dmacfg = gem_readl(bp, DMACFG);
2089 if (features & NETIF_F_HW_CSUM)
2090 dmacfg |= GEM_BIT(TXCOEN);
2092 dmacfg &= ~GEM_BIT(TXCOEN);
2093 gem_writel(bp, DMACFG, dmacfg);
2096 /* RX checksum offload */
2097 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2100 netcfg = gem_readl(bp, NCFGR);
2101 if (features & NETIF_F_RXCSUM &&
2102 !(netdev->flags & IFF_PROMISC))
2103 netcfg |= GEM_BIT(RXCOEN);
2105 netcfg &= ~GEM_BIT(RXCOEN);
2106 gem_writel(bp, NCFGR, netcfg);
2112 static const struct net_device_ops macb_netdev_ops = {
2113 .ndo_open = macb_open,
2114 .ndo_stop = macb_close,
2115 .ndo_start_xmit = macb_start_xmit,
2116 .ndo_set_rx_mode = macb_set_rx_mode,
2117 .ndo_get_stats = macb_get_stats,
2118 .ndo_do_ioctl = macb_ioctl,
2119 .ndo_validate_addr = eth_validate_addr,
2120 .ndo_change_mtu = eth_change_mtu,
2121 .ndo_set_mac_address = eth_mac_addr,
2122 #ifdef CONFIG_NET_POLL_CONTROLLER
2123 .ndo_poll_controller = macb_poll_controller,
2125 .ndo_set_features = macb_set_features,
2129 * Configure peripheral capacities according to device tree
2130 * and integration options used
2132 static void macb_configure_caps(struct macb *bp)
2134 const struct of_device_id *match;
2135 const struct macb_config *config;
2138 if (bp->pdev->dev.of_node) {
2139 match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node);
2140 if (match && match->data) {
2141 config = match->data;
2143 bp->caps = config->caps;
2145 * As we have access to the matching node, configure
2146 * DMA burst length as well
2148 bp->dma_burst_length = config->dma_burst_length;
2152 if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
2153 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2155 if (macb_is_gem(bp)) {
2156 dcfg = gem_readl(bp, DCFG1);
2157 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2158 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2159 dcfg = gem_readl(bp, DCFG2);
2160 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2161 bp->caps |= MACB_CAPS_FIFO_MODE;
2164 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2167 static void macb_probe_queues(void __iomem *mem,
2168 unsigned int *queue_mask,
2169 unsigned int *num_queues)
2177 /* is it macb or gem ? */
2178 mid = readl_relaxed(mem + MACB_MID);
2180 if (MACB_BFEXT(IDNUM, mid) < 0x2)
2183 /* bit 0 is never set but queue 0 always exists */
2184 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2188 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2189 if (*queue_mask & (1 << hw_q))
2193 static int macb_init(struct platform_device *pdev)
2195 struct net_device *dev = platform_get_drvdata(pdev);
2196 unsigned int hw_q, queue_mask, q, num_queues;
2197 struct macb *bp = netdev_priv(dev);
2198 struct macb_queue *queue;
2202 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
2203 if (IS_ERR(bp->pclk)) {
2204 err = PTR_ERR(bp->pclk);
2205 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2209 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
2210 if (IS_ERR(bp->hclk)) {
2211 err = PTR_ERR(bp->hclk);
2212 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2216 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2217 if (IS_ERR(bp->tx_clk))
2220 err = clk_prepare_enable(bp->pclk);
2222 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2226 err = clk_prepare_enable(bp->hclk);
2228 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2229 goto err_disable_pclk;
2232 err = clk_prepare_enable(bp->tx_clk);
2234 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2235 goto err_disable_hclk;
2238 /* set the queue register mapping once for all: queue0 has a special
2239 * register mapping but we don't want to test the queue index then
2240 * compute the corresponding register offset at run time.
2242 macb_probe_queues(bp->regs, &queue_mask, &num_queues);
2244 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2245 if (!(queue_mask & (1 << hw_q)))
2248 queue = &bp->queues[q];
2251 queue->ISR = GEM_ISR(hw_q - 1);
2252 queue->IER = GEM_IER(hw_q - 1);
2253 queue->IDR = GEM_IDR(hw_q - 1);
2254 queue->IMR = GEM_IMR(hw_q - 1);
2255 queue->TBQP = GEM_TBQP(hw_q - 1);
2257 /* queue0 uses legacy registers */
2258 queue->ISR = MACB_ISR;
2259 queue->IER = MACB_IER;
2260 queue->IDR = MACB_IDR;
2261 queue->IMR = MACB_IMR;
2262 queue->TBQP = MACB_TBQP;
2265 /* get irq: here we use the linux queue index, not the hardware
2266 * queue index. the queue irq definitions in the device tree
2267 * must remove the optional gaps that could exist in the
2268 * hardware queue mask.
2270 queue->irq = platform_get_irq(pdev, q);
2271 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2272 IRQF_SHARED, dev->name, queue);
2275 "Unable to request IRQ %d (error %d)\n",
2277 goto err_disable_tx_clk;
2280 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2284 dev->netdev_ops = &macb_netdev_ops;
2285 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2287 /* setup appropriated routines according to adapter type */
2288 if (macb_is_gem(bp)) {
2289 bp->max_tx_length = GEM_MAX_TX_LEN;
2290 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2291 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2292 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2293 bp->macbgem_ops.mog_rx = gem_rx;
2294 dev->ethtool_ops = &gem_ethtool_ops;
2296 bp->max_tx_length = MACB_MAX_TX_LEN;
2297 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2298 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2299 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2300 bp->macbgem_ops.mog_rx = macb_rx;
2301 dev->ethtool_ops = &macb_ethtool_ops;
2305 dev->hw_features = NETIF_F_SG;
2306 /* Checksum offload is only available on gem with packet buffer */
2307 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2308 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2309 if (bp->caps & MACB_CAPS_SG_DISABLED)
2310 dev->hw_features &= ~NETIF_F_SG;
2311 dev->features = dev->hw_features;
2314 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2315 val = GEM_BIT(RGMII);
2316 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2317 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2318 val = MACB_BIT(RMII);
2319 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2320 val = MACB_BIT(MII);
2322 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2323 val |= MACB_BIT(CLKEN);
2325 macb_or_gem_writel(bp, USRIO, val);
2327 /* setup capacities */
2328 macb_configure_caps(bp);
2330 /* Set MII management clock divider */
2331 val = macb_mdc_clk_div(bp);
2332 val |= macb_dbw(bp);
2333 macb_writel(bp, NCFGR, val);
2338 clk_disable_unprepare(bp->tx_clk);
2341 clk_disable_unprepare(bp->hclk);
2344 clk_disable_unprepare(bp->pclk);
2349 #if defined(CONFIG_OF)
2350 /* 1518 rounded up */
2351 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2352 /* max number of receive buffers */
2353 #define AT91ETHER_MAX_RX_DESCR 9
2355 /* Initialize and start the Receiver and Transmit subsystems */
2356 static int at91ether_start(struct net_device *dev)
2358 struct macb *lp = netdev_priv(dev);
2363 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2364 (AT91ETHER_MAX_RX_DESCR *
2365 sizeof(struct macb_dma_desc)),
2366 &lp->rx_ring_dma, GFP_KERNEL);
2370 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2371 AT91ETHER_MAX_RX_DESCR *
2372 AT91ETHER_MAX_RBUFF_SZ,
2373 &lp->rx_buffers_dma, GFP_KERNEL);
2374 if (!lp->rx_buffers) {
2375 dma_free_coherent(&lp->pdev->dev,
2376 AT91ETHER_MAX_RX_DESCR *
2377 sizeof(struct macb_dma_desc),
2378 lp->rx_ring, lp->rx_ring_dma);
2383 addr = lp->rx_buffers_dma;
2384 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2385 lp->rx_ring[i].addr = addr;
2386 lp->rx_ring[i].ctrl = 0;
2387 addr += AT91ETHER_MAX_RBUFF_SZ;
2390 /* Set the Wrap bit on the last descriptor */
2391 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2393 /* Reset buffer index */
2396 /* Program address of descriptor list in Rx Buffer Queue register */
2397 macb_writel(lp, RBQP, lp->rx_ring_dma);
2399 /* Enable Receive and Transmit */
2400 ctl = macb_readl(lp, NCR);
2401 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2406 /* Open the ethernet interface */
2407 static int at91ether_open(struct net_device *dev)
2409 struct macb *lp = netdev_priv(dev);
2413 /* Clear internal statistics */
2414 ctl = macb_readl(lp, NCR);
2415 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2417 macb_set_hwaddr(lp);
2419 ret = at91ether_start(dev);
2423 /* Enable MAC interrupts */
2424 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2426 MACB_BIT(ISR_TUND) |
2429 MACB_BIT(ISR_ROVR) |
2432 /* schedule a link state check */
2433 phy_start(lp->phy_dev);
2435 netif_start_queue(dev);
2440 /* Close the interface */
2441 static int at91ether_close(struct net_device *dev)
2443 struct macb *lp = netdev_priv(dev);
2446 /* Disable Receiver and Transmitter */
2447 ctl = macb_readl(lp, NCR);
2448 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2450 /* Disable MAC interrupts */
2451 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2453 MACB_BIT(ISR_TUND) |
2456 MACB_BIT(ISR_ROVR) |
2459 netif_stop_queue(dev);
2461 dma_free_coherent(&lp->pdev->dev,
2462 AT91ETHER_MAX_RX_DESCR *
2463 sizeof(struct macb_dma_desc),
2464 lp->rx_ring, lp->rx_ring_dma);
2467 dma_free_coherent(&lp->pdev->dev,
2468 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2469 lp->rx_buffers, lp->rx_buffers_dma);
2470 lp->rx_buffers = NULL;
2475 /* Transmit packet */
2476 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2478 struct macb *lp = netdev_priv(dev);
2480 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2481 netif_stop_queue(dev);
2483 /* Store packet information (to free when Tx completed) */
2485 lp->skb_length = skb->len;
2486 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2489 /* Set address of the data in the Transmit Address register */
2490 macb_writel(lp, TAR, lp->skb_physaddr);
2491 /* Set length of the packet in the Transmit Control register */
2492 macb_writel(lp, TCR, skb->len);
2495 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2496 return NETDEV_TX_BUSY;
2499 return NETDEV_TX_OK;
2502 /* Extract received frame from buffer descriptors and sent to upper layers.
2503 * (Called from interrupt context)
2505 static void at91ether_rx(struct net_device *dev)
2507 struct macb *lp = netdev_priv(dev);
2508 unsigned char *p_recv;
2509 struct sk_buff *skb;
2510 unsigned int pktlen;
2512 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2513 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2514 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2515 skb = netdev_alloc_skb(dev, pktlen + 2);
2517 skb_reserve(skb, 2);
2518 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2520 skb->protocol = eth_type_trans(skb, dev);
2521 lp->stats.rx_packets++;
2522 lp->stats.rx_bytes += pktlen;
2525 lp->stats.rx_dropped++;
2528 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2529 lp->stats.multicast++;
2531 /* reset ownership bit */
2532 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2534 /* wrap after last buffer */
2535 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2542 /* MAC interrupt handler */
2543 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2545 struct net_device *dev = dev_id;
2546 struct macb *lp = netdev_priv(dev);
2549 /* MAC Interrupt Status register indicates what interrupts are pending.
2550 * It is automatically cleared once read.
2552 intstatus = macb_readl(lp, ISR);
2554 /* Receive complete */
2555 if (intstatus & MACB_BIT(RCOMP))
2558 /* Transmit complete */
2559 if (intstatus & MACB_BIT(TCOMP)) {
2560 /* The TCOM bit is set even if the transmission failed */
2561 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2562 lp->stats.tx_errors++;
2565 dev_kfree_skb_irq(lp->skb);
2567 dma_unmap_single(NULL, lp->skb_physaddr,
2568 lp->skb_length, DMA_TO_DEVICE);
2569 lp->stats.tx_packets++;
2570 lp->stats.tx_bytes += lp->skb_length;
2572 netif_wake_queue(dev);
2575 /* Work-around for EMAC Errata section 41.3.1 */
2576 if (intstatus & MACB_BIT(RXUBR)) {
2577 ctl = macb_readl(lp, NCR);
2578 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2579 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2582 if (intstatus & MACB_BIT(ISR_ROVR))
2583 netdev_err(dev, "ROVR error\n");
2588 #ifdef CONFIG_NET_POLL_CONTROLLER
2589 static void at91ether_poll_controller(struct net_device *dev)
2591 unsigned long flags;
2593 local_irq_save(flags);
2594 at91ether_interrupt(dev->irq, dev);
2595 local_irq_restore(flags);
2599 static const struct net_device_ops at91ether_netdev_ops = {
2600 .ndo_open = at91ether_open,
2601 .ndo_stop = at91ether_close,
2602 .ndo_start_xmit = at91ether_start_xmit,
2603 .ndo_get_stats = macb_get_stats,
2604 .ndo_set_rx_mode = macb_set_rx_mode,
2605 .ndo_set_mac_address = eth_mac_addr,
2606 .ndo_do_ioctl = macb_ioctl,
2607 .ndo_validate_addr = eth_validate_addr,
2608 .ndo_change_mtu = eth_change_mtu,
2609 #ifdef CONFIG_NET_POLL_CONTROLLER
2610 .ndo_poll_controller = at91ether_poll_controller,
2614 static int at91ether_init(struct platform_device *pdev)
2616 struct net_device *dev = platform_get_drvdata(pdev);
2617 struct macb *bp = netdev_priv(dev);
2621 bp->pclk = devm_clk_get(&pdev->dev, "ether_clk");
2622 if (IS_ERR(bp->pclk))
2623 return PTR_ERR(bp->pclk);
2625 err = clk_prepare_enable(bp->pclk);
2627 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2631 dev->netdev_ops = &at91ether_netdev_ops;
2632 dev->ethtool_ops = &macb_ethtool_ops;
2634 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2637 goto err_disable_clk;
2639 macb_writel(bp, NCR, 0);
2641 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2642 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2643 reg |= MACB_BIT(RM9200_RMII);
2645 macb_writel(bp, NCFGR, reg);
2650 clk_disable_unprepare(bp->pclk);
2655 static const struct macb_config at91sam9260_config = {
2656 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
2660 static const struct macb_config pc302gem_config = {
2661 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2662 .dma_burst_length = 16,
2666 static const struct macb_config sama5d3_config = {
2667 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2668 .dma_burst_length = 16,
2672 static const struct macb_config sama5d4_config = {
2674 .dma_burst_length = 4,
2678 static const struct macb_config emac_config = {
2679 .init = at91ether_init,
2682 static const struct of_device_id macb_dt_ids[] = {
2683 { .compatible = "cdns,at32ap7000-macb" },
2684 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2685 { .compatible = "cdns,macb" },
2686 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2687 { .compatible = "cdns,gem", .data = &pc302gem_config },
2688 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2689 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2690 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2691 { .compatible = "cdns,emac", .data = &emac_config },
2694 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2695 #endif /* CONFIG_OF */
2697 static int macb_probe(struct platform_device *pdev)
2699 int (*init)(struct platform_device *) = macb_init;
2700 struct device_node *np = pdev->dev.of_node;
2701 const struct macb_config *macb_config = NULL;
2702 unsigned int queue_mask, num_queues;
2703 struct macb_platform_data *pdata;
2704 struct phy_device *phydev;
2705 struct net_device *dev;
2706 struct resource *regs;
2712 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2713 mem = devm_ioremap_resource(&pdev->dev, regs);
2715 return PTR_ERR(mem);
2717 macb_probe_queues(mem, &queue_mask, &num_queues);
2718 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2722 dev->base_addr = regs->start;
2724 SET_NETDEV_DEV(dev, &pdev->dev);
2726 bp = netdev_priv(dev);
2730 bp->num_queues = num_queues;
2731 spin_lock_init(&bp->lock);
2733 platform_set_drvdata(pdev, dev);
2735 dev->irq = platform_get_irq(pdev, 0);
2739 mac = of_get_mac_address(np);
2741 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2743 macb_get_hwaddr(bp);
2745 err = of_get_phy_mode(np);
2747 pdata = dev_get_platdata(&pdev->dev);
2748 if (pdata && pdata->is_rmii)
2749 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2751 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2753 bp->phy_interface = err;
2757 const struct of_device_id *match;
2759 match = of_match_node(macb_dt_ids, np);
2761 macb_config = match->data;
2765 bp->caps = macb_config->caps;
2766 bp->dma_burst_length = macb_config->dma_burst_length;
2767 init = macb_config->init;
2770 /* IP specific init */
2773 goto err_out_free_netdev;
2775 err = register_netdev(dev);
2777 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2778 goto err_disable_clocks;
2781 err = macb_mii_init(bp);
2783 goto err_out_unregister_netdev;
2785 netif_carrier_off(dev);
2787 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2788 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2789 dev->base_addr, dev->irq, dev->dev_addr);
2791 phydev = bp->phy_dev;
2792 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2793 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2797 err_out_unregister_netdev:
2798 unregister_netdev(dev);
2801 clk_disable_unprepare(bp->tx_clk);
2802 clk_disable_unprepare(bp->hclk);
2803 clk_disable_unprepare(bp->pclk);
2805 err_out_free_netdev:
2811 static int macb_remove(struct platform_device *pdev)
2813 struct net_device *dev;
2816 dev = platform_get_drvdata(pdev);
2819 bp = netdev_priv(dev);
2821 phy_disconnect(bp->phy_dev);
2822 mdiobus_unregister(bp->mii_bus);
2823 kfree(bp->mii_bus->irq);
2824 mdiobus_free(bp->mii_bus);
2825 unregister_netdev(dev);
2826 clk_disable_unprepare(bp->tx_clk);
2827 clk_disable_unprepare(bp->hclk);
2828 clk_disable_unprepare(bp->pclk);
2835 static int __maybe_unused macb_suspend(struct device *dev)
2837 struct platform_device *pdev = to_platform_device(dev);
2838 struct net_device *netdev = platform_get_drvdata(pdev);
2839 struct macb *bp = netdev_priv(netdev);
2841 netif_carrier_off(netdev);
2842 netif_device_detach(netdev);
2844 clk_disable_unprepare(bp->tx_clk);
2845 clk_disable_unprepare(bp->hclk);
2846 clk_disable_unprepare(bp->pclk);
2851 static int __maybe_unused macb_resume(struct device *dev)
2853 struct platform_device *pdev = to_platform_device(dev);
2854 struct net_device *netdev = platform_get_drvdata(pdev);
2855 struct macb *bp = netdev_priv(netdev);
2857 clk_prepare_enable(bp->pclk);
2858 clk_prepare_enable(bp->hclk);
2859 clk_prepare_enable(bp->tx_clk);
2861 netif_device_attach(netdev);
2866 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2868 static struct platform_driver macb_driver = {
2869 .probe = macb_probe,
2870 .remove = macb_remove,
2873 .of_match_table = of_match_ptr(macb_dt_ids),
2878 module_platform_driver(macb_driver);
2880 MODULE_LICENSE("GPL");
2881 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2882 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2883 MODULE_ALIAS("platform:macb");