2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
50 #include <linux/net_tstamp.h>
52 #include "cxgb4_uld.h"
54 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
57 MAX_NPORTS = 4, /* max # of ports */
58 SERNUM_LEN = 24, /* Serial # length */
59 EC_LEN = 16, /* E/C length */
60 ID_LEN = 16, /* ID length */
61 PN_LEN = 16, /* Part Number length */
62 MACADDR_LEN = 12, /* MAC Address length */
66 T4_REGMAP_SIZE = (160 * 1024),
67 T5_REGMAP_SIZE = (332 * 1024),
79 MEMWIN0_APERTURE = 2048,
80 MEMWIN0_BASE = 0x1b800,
81 MEMWIN1_APERTURE = 32768,
82 MEMWIN1_BASE = 0x28000,
83 MEMWIN1_BASE_T5 = 0x52000,
84 MEMWIN2_APERTURE = 65536,
85 MEMWIN2_BASE = 0x30000,
86 MEMWIN2_APERTURE_T5 = 131072,
87 MEMWIN2_BASE_T5 = 0x60000,
105 PAUSE_AUTONEG = 1 << 2
109 u64 tx_octets; /* total # of octets in good frames */
110 u64 tx_frames; /* all good frames */
111 u64 tx_bcast_frames; /* all broadcast frames */
112 u64 tx_mcast_frames; /* all multicast frames */
113 u64 tx_ucast_frames; /* all unicast frames */
114 u64 tx_error_frames; /* all error frames */
116 u64 tx_frames_64; /* # of Tx frames in a particular range */
117 u64 tx_frames_65_127;
118 u64 tx_frames_128_255;
119 u64 tx_frames_256_511;
120 u64 tx_frames_512_1023;
121 u64 tx_frames_1024_1518;
122 u64 tx_frames_1519_max;
124 u64 tx_drop; /* # of dropped Tx frames */
125 u64 tx_pause; /* # of transmitted pause frames */
126 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
127 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
128 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
129 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
130 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
131 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
132 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
133 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
135 u64 rx_octets; /* total # of octets in good frames */
136 u64 rx_frames; /* all good frames */
137 u64 rx_bcast_frames; /* all broadcast frames */
138 u64 rx_mcast_frames; /* all multicast frames */
139 u64 rx_ucast_frames; /* all unicast frames */
140 u64 rx_too_long; /* # of frames exceeding MTU */
141 u64 rx_jabber; /* # of jabber frames */
142 u64 rx_fcs_err; /* # of received frames with bad FCS */
143 u64 rx_len_err; /* # of received frames with length error */
144 u64 rx_symbol_err; /* symbol errors */
145 u64 rx_runt; /* # of short frames */
147 u64 rx_frames_64; /* # of Rx frames in a particular range */
148 u64 rx_frames_65_127;
149 u64 rx_frames_128_255;
150 u64 rx_frames_256_511;
151 u64 rx_frames_512_1023;
152 u64 rx_frames_1024_1518;
153 u64 rx_frames_1519_max;
155 u64 rx_pause; /* # of received pause frames */
156 u64 rx_ppp0; /* # of received PPP prio 0 frames */
157 u64 rx_ppp1; /* # of received PPP prio 1 frames */
158 u64 rx_ppp2; /* # of received PPP prio 2 frames */
159 u64 rx_ppp3; /* # of received PPP prio 3 frames */
160 u64 rx_ppp4; /* # of received PPP prio 4 frames */
161 u64 rx_ppp5; /* # of received PPP prio 5 frames */
162 u64 rx_ppp6; /* # of received PPP prio 6 frames */
163 u64 rx_ppp7; /* # of received PPP prio 7 frames */
165 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
166 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
167 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
168 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
169 u64 rx_trunc0; /* buffer-group 0 truncated packets */
170 u64 rx_trunc1; /* buffer-group 1 truncated packets */
171 u64 rx_trunc2; /* buffer-group 2 truncated packets */
172 u64 rx_trunc3; /* buffer-group 3 truncated packets */
175 struct lb_port_stats {
188 u64 frames_1024_1518;
203 struct tp_tcp_stats {
207 u64 tcp_retrans_segs;
210 struct tp_usm_stats {
216 struct tp_fcoe_stats {
222 struct tp_err_stats {
226 u32 tnl_cong_drops[4];
227 u32 ofld_chan_drops[4];
229 u32 ofld_vlan_drops[4];
235 struct tp_cpl_stats {
240 struct tp_rdma_stats {
246 u32 hps; /* host page size for our PF/VF */
247 u32 eq_qpp; /* egress queues/page for our PF/VF */
248 u32 iq_qpp; /* egress queues/page for our PF/VF */
252 unsigned int tre; /* log2 of core clocks per TP tick */
253 unsigned int la_mask; /* what events are recorded by TP LA */
254 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
257 uint32_t dack_re; /* DACK timer resolution */
258 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
260 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
261 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
263 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
264 * subset of the set of fields which may be present in the Compressed
265 * Filter Tuple portion of filters and TCP TCB connections. The
266 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
267 * Since a variable number of fields may or may not be present, their
268 * shifted field positions within the Compressed Filter Tuple may
269 * vary, or not even be present if the field isn't selected in
270 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
271 * places we store their offsets here, or a -1 if the field isn't
283 u8 sn[SERNUM_LEN + 1];
286 u8 na[MACADDR_LEN + 1];
294 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
295 #define CHELSIO_CHIP_FPGA 0x100
296 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
297 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
299 #define CHELSIO_T4 0x4
300 #define CHELSIO_T5 0x5
301 #define CHELSIO_T6 0x6
304 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
305 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
306 T4_FIRST_REV = T4_A1,
309 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
310 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
311 T5_FIRST_REV = T5_A0,
314 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
315 T6_FIRST_REV = T6_A0,
319 struct devlog_params {
320 u32 memtype; /* which memory (EDC0, EDC1, MC) */
321 u32 start; /* start of log in firmware memory */
322 u32 size; /* size of log */
325 /* Stores chip specific parameters */
326 struct arch_specific_params {
334 struct adapter_params {
335 struct sge_params sge;
337 struct vpd_params vpd;
338 struct pci_params pci;
339 struct devlog_params devlog;
340 enum pcie_memwin drv_memwin;
342 unsigned int cim_la_size;
344 unsigned int sf_size; /* serial flash size in bytes */
345 unsigned int sf_nsec; /* # of flash sectors */
346 unsigned int sf_fw_start; /* start of FW image in flash */
348 unsigned int fw_vers;
349 unsigned int tp_vers;
352 unsigned short mtus[NMTUS];
353 unsigned short a_wnd[NCCTRL_WIN];
354 unsigned short b_wnd[NCCTRL_WIN];
356 unsigned char nports; /* # of ethernet ports */
357 unsigned char portvec;
358 enum chip_type chip; /* chip code */
359 struct arch_specific_params arch; /* chip specific params */
360 unsigned char offload;
362 unsigned char bypass;
364 unsigned int ofldq_wr_cred;
365 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
367 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
368 unsigned int max_ird_adapter; /* Max read depth per adapter */
371 /* State needed to monitor the forward progress of SGE Ingress DMA activities
372 * and possible hangs.
374 struct sge_idma_monitor_state {
375 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
376 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
377 unsigned int idma_state[2]; /* IDMA Hang detect state */
378 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
379 unsigned int idma_warn[2]; /* time to warning in HZ */
382 #include "t4fw_api.h"
384 #define FW_VERSION(chip) ( \
385 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
386 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
387 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
388 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
389 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
395 struct fw_hdr fw_hdr;
399 struct trace_params {
400 u32 data[TRACE_LEN / 4];
401 u32 mask[TRACE_LEN / 4];
402 unsigned short snap_len;
403 unsigned short min_len;
404 unsigned char skip_ofst;
405 unsigned char skip_len;
406 unsigned char invert;
411 unsigned short supported; /* link capabilities */
412 unsigned short advertising; /* advertised capabilities */
413 unsigned short requested_speed; /* speed user has requested */
414 unsigned short speed; /* actual link speed */
415 unsigned char requested_fc; /* flow control user has requested */
416 unsigned char fc; /* actual link flow control */
417 unsigned char autoneg; /* autonegotiating? */
418 unsigned char link_ok; /* link up? */
421 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
424 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
425 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
426 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
427 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
428 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
429 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
433 MAX_TXQ_ENTRIES = 16384,
434 MAX_CTRL_TXQ_ENTRIES = 1024,
435 MAX_RSPQ_ENTRIES = 16384,
436 MAX_RX_BUFFERS = 16384,
437 MIN_TXQ_ENTRIES = 32,
438 MIN_CTRL_TXQ_ENTRIES = 32,
439 MIN_RSPQ_ENTRIES = 128,
444 INGQ_EXTRAS = 2, /* firmware event queue and */
445 /* forwarded interrupts */
446 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
447 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
453 #include "cxgb4_dcb.h"
455 #ifdef CONFIG_CHELSIO_T4_FCOE
456 #include "cxgb4_fcoe.h"
457 #endif /* CONFIG_CHELSIO_T4_FCOE */
460 struct adapter *adapter;
462 s16 xact_addr_filt; /* index of exact MAC address filter */
463 u16 rss_size; /* size of VI's RSS table slice */
465 enum fw_port_type port_type;
469 u8 lport; /* associated offload logical port */
470 u8 nqsets; /* # of qsets */
471 u8 first_qset; /* index of first qset */
473 struct link_config link_cfg;
475 struct port_stats stats_base;
476 #ifdef CONFIG_CHELSIO_T4_DCB
477 struct port_dcb_info dcb; /* Data Center Bridging support */
479 #ifdef CONFIG_CHELSIO_T4_FCOE
480 struct cxgb_fcoe fcoe;
481 #endif /* CONFIG_CHELSIO_T4_FCOE */
482 bool rxtstamp; /* Enable TS */
483 struct hwtstamp_config tstamp_config;
489 enum { /* adapter flags */
490 FULL_INIT_DONE = (1 << 0),
491 DEV_ENABLED = (1 << 1),
492 USING_MSI = (1 << 2),
493 USING_MSIX = (1 << 3),
495 RSS_TNLALLLOOKUP = (1 << 5),
496 USING_SOFT_PARAMS = (1 << 6),
497 MASTER_PF = (1 << 7),
498 FW_OFLD_CONN = (1 << 9),
503 struct sge_fl { /* SGE free-buffer queue state */
504 unsigned int avail; /* # of available Rx buffers */
505 unsigned int pend_cred; /* new buffers since last FL DB ring */
506 unsigned int cidx; /* consumer index */
507 unsigned int pidx; /* producer index */
508 unsigned long alloc_failed; /* # of times buffer allocation failed */
509 unsigned long large_alloc_failed;
510 unsigned long starving;
512 unsigned int cntxt_id; /* SGE context id for the free list */
513 unsigned int size; /* capacity of free list */
514 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
515 __be64 *desc; /* address of HW Rx descriptor ring */
516 dma_addr_t addr; /* bus address of HW ring start */
517 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
518 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
521 /* A packet gather list */
523 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
524 struct page_frag frags[MAX_SKB_FRAGS];
525 void *va; /* virtual address of first byte */
526 unsigned int nfrags; /* # of fragments */
527 unsigned int tot_len; /* total length of fragments */
530 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
531 const struct pkt_gl *gl);
533 struct sge_rspq { /* state for an SGE response queue */
534 struct napi_struct napi;
535 const __be64 *cur_desc; /* current descriptor in queue */
536 unsigned int cidx; /* consumer index */
537 u8 gen; /* current generation bit */
538 u8 intr_params; /* interrupt holdoff parameters */
539 u8 next_intr_params; /* holdoff params for next interrupt */
541 u8 pktcnt_idx; /* interrupt packet threshold */
542 u8 uld; /* ULD handling this queue */
543 u8 idx; /* queue index within its group */
544 int offset; /* offset into current Rx buffer */
545 u16 cntxt_id; /* SGE context id for the response q */
546 u16 abs_id; /* absolute SGE id for the response q */
547 __be64 *desc; /* address of HW response ring */
548 dma_addr_t phys_addr; /* physical address of the ring */
549 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
550 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
551 unsigned int iqe_len; /* entry size */
552 unsigned int size; /* capacity of response queue */
553 struct adapter *adap;
554 struct net_device *netdev; /* associated net device */
555 rspq_handler_t handler;
556 #ifdef CONFIG_NET_RX_BUSY_POLL
557 #define CXGB_POLL_STATE_IDLE 0
558 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
559 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
560 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
561 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
562 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
563 CXGB_POLL_STATE_POLL_YIELD)
564 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
565 CXGB_POLL_STATE_POLL)
566 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
567 CXGB_POLL_STATE_POLL_YIELD)
568 unsigned int bpoll_state;
569 spinlock_t bpoll_lock; /* lock for busy poll */
570 #endif /* CONFIG_NET_RX_BUSY_POLL */
574 struct sge_eth_stats { /* Ethernet queue statistics */
575 unsigned long pkts; /* # of ethernet packets */
576 unsigned long lro_pkts; /* # of LRO super packets */
577 unsigned long lro_merged; /* # of wire packets merged by LRO */
578 unsigned long rx_cso; /* # of Rx checksum offloads */
579 unsigned long vlan_ex; /* # of Rx VLAN extractions */
580 unsigned long rx_drops; /* # of packets dropped due to no mem */
583 struct sge_eth_rxq { /* SW Ethernet Rx queue */
584 struct sge_rspq rspq;
586 struct sge_eth_stats stats;
587 } ____cacheline_aligned_in_smp;
589 struct sge_ofld_stats { /* offload queue statistics */
590 unsigned long pkts; /* # of packets */
591 unsigned long imm; /* # of immediate-data packets */
592 unsigned long an; /* # of asynchronous notifications */
593 unsigned long nomem; /* # of responses deferred due to no mem */
596 struct sge_ofld_rxq { /* SW offload Rx queue */
597 struct sge_rspq rspq;
599 struct sge_ofld_stats stats;
600 } ____cacheline_aligned_in_smp;
609 unsigned int in_use; /* # of in-use Tx descriptors */
610 unsigned int size; /* # of descriptors */
611 unsigned int cidx; /* SW consumer index */
612 unsigned int pidx; /* producer index */
613 unsigned long stops; /* # of times q has been stopped */
614 unsigned long restarts; /* # of queue restarts */
615 unsigned int cntxt_id; /* SGE context id for the Tx q */
616 struct tx_desc *desc; /* address of HW Tx descriptor ring */
617 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
618 struct sge_qstat *stat; /* queue status entry */
619 dma_addr_t phys_addr; /* physical address of the ring */
622 unsigned short db_pidx;
623 unsigned short db_pidx_inc;
624 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
625 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
628 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
630 struct netdev_queue *txq; /* associated netdev TX queue */
631 #ifdef CONFIG_CHELSIO_T4_DCB
632 u8 dcb_prio; /* DCB Priority bound to queue */
634 unsigned long tso; /* # of TSO requests */
635 unsigned long tx_cso; /* # of Tx checksum offloads */
636 unsigned long vlan_ins; /* # of Tx VLAN insertions */
637 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
638 } ____cacheline_aligned_in_smp;
640 struct sge_ofld_txq { /* state for an SGE offload Tx queue */
642 struct adapter *adap;
643 struct sk_buff_head sendq; /* list of backpressured packets */
644 struct tasklet_struct qresume_tsk; /* restarts the queue */
645 u8 full; /* the Tx ring is full */
646 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
647 } ____cacheline_aligned_in_smp;
649 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
651 struct adapter *adap;
652 struct sk_buff_head sendq; /* list of backpressured packets */
653 struct tasklet_struct qresume_tsk; /* restarts the queue */
654 u8 full; /* the Tx ring is full */
655 } ____cacheline_aligned_in_smp;
658 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
659 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
660 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
662 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
663 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
664 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
665 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
666 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
668 struct sge_rspq intrq ____cacheline_aligned_in_smp;
669 spinlock_t intrq_lock;
671 u16 max_ethqsets; /* # of available Ethernet queue sets */
672 u16 ethqsets; /* # of active Ethernet queue sets */
673 u16 ethtxq_rover; /* Tx queue to clean up next */
674 u16 ofldqsets; /* # of active offload queue sets */
675 u16 rdmaqs; /* # of available RDMA Rx queues */
676 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
677 u16 ofld_rxq[MAX_OFLD_QSETS];
678 u16 rdma_rxq[MAX_RDMA_QUEUES];
679 u16 rdma_ciq[MAX_RDMA_CIQS];
680 u16 timer_val[SGE_NTIMERS];
681 u8 counter_val[SGE_NCOUNTERS];
682 u32 fl_pg_order; /* large page allocation size */
683 u32 stat_len; /* length of status page at ring end */
684 u32 pktshift; /* padding between CPL & packet data */
685 u32 fl_align; /* response queue message alignment */
686 u32 fl_starve_thres; /* Free List starvation threshold */
688 struct sge_idma_monitor_state idma_monitor;
689 unsigned int egr_start;
691 unsigned int ingr_start;
692 unsigned int ingr_sz;
693 void **egr_map; /* qid->queue egress queue map */
694 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
695 unsigned long *starving_fl;
696 unsigned long *txq_maperr;
697 unsigned long *blocked_fl;
698 struct timer_list rx_timer; /* refills starving FLs */
699 struct timer_list tx_timer; /* checks Tx queues */
702 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
703 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
704 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
705 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
709 #ifdef CONFIG_PCI_IOV
711 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
712 * Configuration initialization for T5 only has SR-IOV functionality enabled
713 * on PF0-3 in order to simplify everything.
715 #define NUM_OF_PF_WITH_SRIOV 4
719 struct doorbell_stats {
729 struct pci_dev *pdev;
730 struct device *pdev_dev;
738 struct adapter_params params;
739 struct cxgb4_virt_res vres;
744 char desc[IFNAMSIZ + 10];
745 } msix_info[MAX_INGQ + 1];
747 struct doorbell_stats db_stats;
750 struct net_device *port[MAX_NPORTS];
751 u8 chan_map[NCHAN]; /* channel -> port map */
754 unsigned int l2t_start;
755 unsigned int l2t_end;
756 struct l2t_data *l2t;
757 unsigned int clipt_start;
758 unsigned int clipt_end;
759 struct clip_tbl *clipt;
760 void *uld_handle[CXGB4_ULD_MAX];
761 struct list_head list_node;
762 struct list_head rcu_node;
764 struct tid_info tids;
765 void **tid_release_head;
766 spinlock_t tid_release_lock;
767 struct workqueue_struct *workq;
768 struct work_struct tid_release_task;
769 struct work_struct db_full_task;
770 struct work_struct db_drop_task;
771 bool tid_release_task_busy;
773 struct dentry *debugfs_root;
774 u32 use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
775 u32 trace_rss; /* 1 implies that different RSS flit per filter is
776 * used per filter else if 0 default RSS flit is
777 * used for all 4 filters.
780 spinlock_t stats_lock;
781 spinlock_t win0_lock ____cacheline_aligned_in_smp;
784 /* Defined bit width of user definable filter tuples
786 #define ETHTYPE_BITWIDTH 16
787 #define FRAG_BITWIDTH 1
788 #define MACIDX_BITWIDTH 9
789 #define FCOE_BITWIDTH 1
790 #define IPORT_BITWIDTH 3
791 #define MATCHTYPE_BITWIDTH 3
792 #define PROTO_BITWIDTH 8
793 #define TOS_BITWIDTH 8
794 #define PF_BITWIDTH 8
795 #define VF_BITWIDTH 8
796 #define IVLAN_BITWIDTH 16
797 #define OVLAN_BITWIDTH 16
799 /* Filter matching rules. These consist of a set of ingress packet field
800 * (value, mask) tuples. The associated ingress packet field matches the
801 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
802 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
803 * matches an ingress packet when all of the individual individual field
804 * matching rules are true.
806 * Partial field masks are always valid, however, while it may be easy to
807 * understand their meanings for some fields (e.g. IP address to match a
808 * subnet), for others making sensible partial masks is less intuitive (e.g.
809 * MPS match type) ...
811 * Most of the following data structures are modeled on T4 capabilities.
812 * Drivers for earlier chips use the subsets which make sense for those chips.
813 * We really need to come up with a hardware-independent mechanism to
814 * represent hardware filter capabilities ...
816 struct ch_filter_tuple {
817 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
818 * register selects which of these fields will participate in the
819 * filter match rules -- up to a maximum of 36 bits. Because
820 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
823 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
824 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
825 uint32_t ivlan_vld:1; /* inner VLAN valid */
826 uint32_t ovlan_vld:1; /* outer VLAN valid */
827 uint32_t pfvf_vld:1; /* PF/VF valid */
828 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
829 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
830 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
831 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
832 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
833 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
834 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
835 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
836 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
837 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
839 /* Uncompressed header matching field rules. These are always
840 * available for field rules.
842 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
843 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
844 uint16_t lport; /* local port */
845 uint16_t fport; /* foreign port */
848 /* A filter ioctl command.
850 struct ch_filter_specification {
851 /* Administrative fields for filter.
853 uint32_t hitcnts:1; /* count filter hits in TCB */
854 uint32_t prio:1; /* filter has priority over active/server */
856 /* Fundamental filter typing. This is the one element of filter
857 * matching that doesn't exist as a (value, mask) tuple.
859 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
861 /* Packet dispatch information. Ingress packets which match the
862 * filter rules will be dropped, passed to the host or switched back
863 * out as egress packets.
865 uint32_t action:2; /* drop, pass, switch */
867 uint32_t rpttid:1; /* report TID in RSS hash field */
869 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
870 uint32_t iq:10; /* ingress queue */
872 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
873 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
874 /* 1 => TCB contains IQ ID */
876 /* Switch proxy/rewrite fields. An ingress packet which matches a
877 * filter with "switch" set will be looped back out as an egress
878 * packet -- potentially with some Ethernet header rewriting.
880 uint32_t eport:2; /* egress port to switch packet out */
881 uint32_t newdmac:1; /* rewrite destination MAC address */
882 uint32_t newsmac:1; /* rewrite source MAC address */
883 uint32_t newvlan:2; /* rewrite VLAN Tag */
884 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
885 uint8_t smac[ETH_ALEN]; /* new source MAC address */
886 uint16_t vlan; /* VLAN Tag to insert */
888 /* Filter rule value/mask pairs.
890 struct ch_filter_tuple val;
891 struct ch_filter_tuple mask;
895 FILTER_PASS = 0, /* default */
901 VLAN_NOCHANGE = 0, /* default */
907 static inline int is_offload(const struct adapter *adap)
909 return adap->params.offload;
912 static inline int is_t6(enum chip_type chip)
914 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
917 static inline int is_t5(enum chip_type chip)
919 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
922 static inline int is_t4(enum chip_type chip)
924 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
927 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
929 return readl(adap->regs + reg_addr);
932 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
934 writel(val, adap->regs + reg_addr);
938 static inline u64 readq(const volatile void __iomem *addr)
940 return readl(addr) + ((u64)readl(addr + 4) << 32);
943 static inline void writeq(u64 val, volatile void __iomem *addr)
946 writel(val >> 32, addr + 4);
950 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
952 return readq(adap->regs + reg_addr);
955 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
957 writeq(val, adap->regs + reg_addr);
961 * t4_set_hw_addr - store a port's MAC address in SW
962 * @adapter: the adapter
963 * @port_idx: the port index
964 * @hw_addr: the Ethernet address
966 * Store the Ethernet address of the given port in SW. Called by the common
967 * code when it retrieves a port's Ethernet address from EEPROM.
969 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
972 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
973 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
977 * netdev2pinfo - return the port_info structure associated with a net_device
980 * Return the struct port_info associated with a net_device
982 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
984 return netdev_priv(dev);
988 * adap2pinfo - return the port_info of a port
990 * @idx: the port index
992 * Return the port_info structure for the port of the given index.
994 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
996 return netdev_priv(adap->port[idx]);
1000 * netdev2adap - return the adapter structure associated with a net_device
1003 * Return the struct adapter associated with a net_device
1005 static inline struct adapter *netdev2adap(const struct net_device *dev)
1007 return netdev2pinfo(dev)->adapter;
1010 #ifdef CONFIG_NET_RX_BUSY_POLL
1011 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1013 spin_lock_init(&q->bpoll_lock);
1014 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1017 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1021 spin_lock(&q->bpoll_lock);
1022 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1023 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1026 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1028 spin_unlock(&q->bpoll_lock);
1032 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1036 spin_lock(&q->bpoll_lock);
1037 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1039 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1040 spin_unlock(&q->bpoll_lock);
1044 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1048 spin_lock_bh(&q->bpoll_lock);
1049 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1050 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1053 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1055 spin_unlock_bh(&q->bpoll_lock);
1059 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1063 spin_lock_bh(&q->bpoll_lock);
1064 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1066 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1067 spin_unlock_bh(&q->bpoll_lock);
1071 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1073 return q->bpoll_state & CXGB_POLL_USER_PEND;
1076 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1080 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1085 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1090 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1095 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1100 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1104 #endif /* CONFIG_NET_RX_BUSY_POLL */
1106 /* Return a version number to identify the type of adapter. The scheme is:
1107 * - bits 0..9: chip version
1108 * - bits 10..15: chip revision
1109 * - bits 16..23: register dump version
1111 static inline unsigned int mk_adap_vers(struct adapter *ap)
1113 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1114 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1117 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1118 static inline unsigned int qtimer_val(const struct adapter *adap,
1119 const struct sge_rspq *q)
1121 unsigned int idx = q->intr_params >> 1;
1123 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1126 /* driver version & name used for ethtool_drvinfo */
1127 extern char cxgb4_driver_name[];
1128 extern const char cxgb4_driver_version[];
1130 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1131 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1133 void *t4_alloc_mem(size_t size);
1135 void t4_free_sge_resources(struct adapter *adap);
1136 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1137 irq_handler_t t4_intr_handler(struct adapter *adap);
1138 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1139 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1140 const struct pkt_gl *gl);
1141 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1142 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1143 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1144 struct net_device *dev, int intr_idx,
1145 struct sge_fl *fl, rspq_handler_t hnd, int cong);
1146 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1147 struct net_device *dev, struct netdev_queue *netdevq,
1149 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1150 struct net_device *dev, unsigned int iqid,
1151 unsigned int cmplqid);
1152 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1153 struct net_device *dev, unsigned int iqid);
1154 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1155 int t4_sge_init(struct adapter *adap);
1156 void t4_sge_start(struct adapter *adap);
1157 void t4_sge_stop(struct adapter *adap);
1158 int cxgb_busy_poll(struct napi_struct *napi);
1159 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1161 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1162 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1163 extern int dbfifo_int_thresh;
1165 #define for_each_port(adapter, iter) \
1166 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1168 static inline int is_bypass(struct adapter *adap)
1170 return adap->params.bypass;
1173 static inline int is_bypass_device(int device)
1175 /* this should be set based upon device capabilities */
1185 static inline int is_10gbt_device(int device)
1187 /* this should be set based upon device capabilities */
1198 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1200 return adap->params.vpd.cclk / 1000;
1203 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1206 return (us * adap->params.vpd.cclk) / 1000;
1209 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1212 /* add Core Clock / 2 to round ticks to nearest uS */
1213 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1214 adapter->params.vpd.cclk);
1217 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1220 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1221 int size, void *rpl, bool sleep_ok, int timeout);
1222 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1223 void *rpl, bool sleep_ok);
1225 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1226 const void *cmd, int size, void *rpl,
1229 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1233 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1234 int size, void *rpl)
1236 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1239 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1240 int size, void *rpl)
1242 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1245 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1246 unsigned int data_reg, const u32 *vals,
1247 unsigned int nregs, unsigned int start_idx);
1248 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1249 unsigned int data_reg, u32 *vals, unsigned int nregs,
1250 unsigned int start_idx);
1251 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1253 struct fw_filter_wr;
1255 void t4_intr_enable(struct adapter *adapter);
1256 void t4_intr_disable(struct adapter *adapter);
1257 int t4_slow_intr_handler(struct adapter *adapter);
1259 int t4_wait_dev_ready(void __iomem *regs);
1260 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1261 struct link_config *lc);
1262 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1264 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1265 u32 t4_get_util_window(struct adapter *adap);
1266 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1268 #define T4_MEMORY_WRITE 0
1269 #define T4_MEMORY_READ 1
1270 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1271 void *buf, int dir);
1272 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1273 u32 len, __be32 *buf)
1275 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1278 unsigned int t4_get_regs_len(struct adapter *adapter);
1279 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1281 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1282 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1283 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1284 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1285 unsigned int nwords, u32 *data, int byte_oriented);
1286 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1287 int t4_load_phy_fw(struct adapter *adap,
1288 int win, spinlock_t *lock,
1289 int (*phy_fw_version)(const u8 *, size_t),
1290 const u8 *phy_fw_data, size_t phy_fw_size);
1291 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1292 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1293 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1294 const u8 *fw_data, unsigned int size, int force);
1295 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1296 int t4_check_fw_version(struct adapter *adap);
1297 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1298 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1299 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1300 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1301 const u8 *fw_data, unsigned int fw_size,
1302 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1303 int t4_prep_adapter(struct adapter *adapter);
1305 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1306 int t4_bar2_sge_qregs(struct adapter *adapter,
1308 enum t4_bar2_qtype qtype,
1311 unsigned int *pbar2_qid);
1313 unsigned int qtimer_val(const struct adapter *adap,
1314 const struct sge_rspq *q);
1316 int t4_init_devlog_params(struct adapter *adapter);
1317 int t4_init_sge_params(struct adapter *adapter);
1318 int t4_init_tp_params(struct adapter *adap);
1319 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1320 int t4_init_rss_mode(struct adapter *adap, int mbox);
1321 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1322 void t4_fatal_err(struct adapter *adapter);
1323 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1324 int start, int n, const u16 *rspq, unsigned int nrspq);
1325 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1326 unsigned int flags);
1327 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1328 unsigned int flags, unsigned int defq);
1329 int t4_read_rss(struct adapter *adapter, u16 *entries);
1330 void t4_read_rss_key(struct adapter *adapter, u32 *key);
1331 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1332 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1334 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1335 u32 *vfl, u32 *vfh);
1336 u32 t4_read_rss_pf_map(struct adapter *adapter);
1337 u32 t4_read_rss_pf_mask(struct adapter *adapter);
1339 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
1340 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1341 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1342 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1344 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1346 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1347 unsigned int *valp);
1348 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1349 const unsigned int *valp);
1350 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1351 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1352 unsigned int *pif_req_wrptr,
1353 unsigned int *pif_rsp_wrptr);
1354 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1355 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1356 const char *t4_get_port_type_description(enum fw_port_type port_type);
1357 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1358 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1359 struct port_stats *stats,
1360 struct port_stats *offset);
1361 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1362 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1363 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1364 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1365 unsigned int mask, unsigned int val);
1366 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1367 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
1368 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
1369 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1370 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
1371 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1372 struct tp_tcp_stats *v6);
1373 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1374 struct tp_fcoe_stats *st);
1375 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1376 const unsigned short *alpha, const unsigned short *beta);
1378 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1380 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1381 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1383 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1385 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1386 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1388 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1389 enum dev_master master, enum dev_state *state);
1390 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1391 int t4_early_init(struct adapter *adap, unsigned int mbox);
1392 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1393 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1394 unsigned int cache_line_size);
1395 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1396 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1397 unsigned int vf, unsigned int nparams, const u32 *params,
1399 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1400 unsigned int vf, unsigned int nparams, const u32 *params,
1402 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1403 unsigned int pf, unsigned int vf,
1404 unsigned int nparams, const u32 *params,
1405 const u32 *val, int timeout);
1406 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1407 unsigned int vf, unsigned int nparams, const u32 *params,
1409 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1410 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1411 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1412 unsigned int vi, unsigned int cmask, unsigned int pmask,
1413 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1414 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1415 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1416 unsigned int *rss_size);
1417 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1418 unsigned int pf, unsigned int vf,
1420 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1421 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1423 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1424 unsigned int viid, bool free, unsigned int naddr,
1425 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1426 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1427 int idx, const u8 *addr, bool persist, bool add_smt);
1428 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1429 bool ucast, u64 vec, bool sleep_ok);
1430 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1431 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1432 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1433 bool rx_en, bool tx_en);
1434 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1435 unsigned int nblinks);
1436 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1437 unsigned int mmd, unsigned int reg, u16 *valp);
1438 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1439 unsigned int mmd, unsigned int reg, u16 val);
1440 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1441 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1442 unsigned int fl0id, unsigned int fl1id);
1443 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1444 unsigned int vf, unsigned int eqid);
1445 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1446 unsigned int vf, unsigned int eqid);
1447 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1448 unsigned int vf, unsigned int eqid);
1449 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
1450 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1451 void t4_db_full(struct adapter *adapter);
1452 void t4_db_dropped(struct adapter *adapter);
1453 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1454 int filter_index, int enable);
1455 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1456 int filter_index, int *enabled);
1457 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1459 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1460 void t4_free_mem(void *addr);
1461 void t4_idma_monitor_init(struct adapter *adapter,
1462 struct sge_idma_monitor_state *idma);
1463 void t4_idma_monitor(struct adapter *adapter,
1464 struct sge_idma_monitor_state *idma,
1466 #endif /* __CXGB4_H__ */