drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <asm/uaccess.h>
  66
  67 #include "cxgb4.h"
  68 #include "t4_regs.h"
  69 #include "t4_msg.h"
  70 #include "t4fw_api.h"
  71 #include "cxgb4_dcb.h"
  72 #include "cxgb4_debugfs.h"
  73 #include "l2t.h"
  74
  75 #ifdef DRV_VERSION
  76 #undef DRV_VERSION
  77 #endif
  78 #define DRV_VERSION "2.0.0-ko"
  79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
  80
  81 /*
  82  * Max interrupt hold-off timer value in us.  Queues fall back to this value
  83  * under extreme memory pressure so it's largish to give the system time to
  84  * recover.
  85  */
  86 #define MAX_SGE_TIMERVAL 200U
  87
  88 enum {
  89         /*
  90          * Physical Function provisioning constants.
  91          */
  92         PFRES_NVI = 4,                  /* # of Virtual Interfaces */
  93         PFRES_NETHCTRL = 128,           /* # of EQs used for ETH or CTRL Qs */
  94         PFRES_NIQFLINT = 128,           /* # of ingress Qs/w Free List(s)/intr
  95                                          */
  96         PFRES_NEQ = 256,                /* # of egress queues */
  97         PFRES_NIQ = 0,                  /* # of ingress queues */
  98         PFRES_TC = 0,                   /* PCI-E traffic class */
  99         PFRES_NEXACTF = 128,            /* # of exact MPS filters */
 100
 101         PFRES_R_CAPS = FW_CMD_CAP_PF,
 102         PFRES_WX_CAPS = FW_CMD_CAP_PF,
 103
 104 #ifdef CONFIG_PCI_IOV
 105         /*
 106          * Virtual Function provisioning constants.  We need two extra Ingress
 107          * Queues with Interrupt capability to serve as the VF's Firmware
 108          * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
 109          * neither will have Free Lists associated with them).  For each
 110          * Ethernet/Control Egress Queue and for each Free List, we need an
 111          * Egress Context.
 112          */
 113         VFRES_NPORTS = 1,               /* # of "ports" per VF */
 114         VFRES_NQSETS = 2,               /* # of "Queue Sets" per VF */
 115
 116         VFRES_NVI = VFRES_NPORTS,       /* # of Virtual Interfaces */
 117         VFRES_NETHCTRL = VFRES_NQSETS,  /* # of EQs used for ETH or CTRL Qs */
 118         VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
 119         VFRES_NEQ = VFRES_NQSETS*2,     /* # of egress queues */
 120         VFRES_NIQ = 0,                  /* # of non-fl/int ingress queues */
 121         VFRES_TC = 0,                   /* PCI-E traffic class */
 122         VFRES_NEXACTF = 16,             /* # of exact MPS filters */
 123
 124         VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
 125         VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
 126 #endif
 127 };
 128
 129 /*
 130  * Provide a Port Access Rights Mask for the specified PF/VF.  This is very
 131  * static and likely not to be useful in the long run.  We really need to
 132  * implement some form of persistent configuration which the firmware
 133  * controls.
 134  */
 135 static unsigned int pfvfres_pmask(struct adapter *adapter,
 136                                   unsigned int pf, unsigned int vf)
 137 {
 138         unsigned int portn, portvec;
 139
 140         /*
 141          * Give PF's access to all of the ports.
 142          */
 143         if (vf == 0)
 144                 return FW_PFVF_CMD_PMASK_M;
 145
 146         /*
 147          * For VFs, we'll assign them access to the ports based purely on the
 148          * PF.  We assign active ports in order, wrapping around if there are
 149          * fewer active ports than PFs: e.g. active port[pf % nports].
 150          * Unfortunately the adapter's port_info structs haven't been
 151          * initialized yet so we have to compute this.
 152          */
 153         if (adapter->params.nports == 0)
 154                 return 0;
 155
 156         portn = pf % adapter->params.nports;
 157         portvec = adapter->params.portvec;
 158         for (;;) {
 159                 /*
 160                  * Isolate the lowest set bit in the port vector.  If we're at
 161                  * the port number that we want, return that as the pmask.
 162                  * otherwise mask that bit out of the port vector and
 163                  * decrement our port number ...
 164                  */
 165                 unsigned int pmask = portvec ^ (portvec & (portvec-1));
 166                 if (portn == 0)
 167                         return pmask;
 168                 portn--;
 169                 portvec &= ~pmask;
 170         }
 171         /*NOTREACHED*/
 172 }
 173
 174 enum {
 175         MAX_TXQ_ENTRIES      = 16384,
 176         MAX_CTRL_TXQ_ENTRIES = 1024,
 177         MAX_RSPQ_ENTRIES     = 16384,
 178         MAX_RX_BUFFERS       = 16384,
 179         MIN_TXQ_ENTRIES      = 32,
 180         MIN_CTRL_TXQ_ENTRIES = 32,
 181         MIN_RSPQ_ENTRIES     = 128,
 182         MIN_FL_ENTRIES       = 16
 183 };
 184
 185 /* Host shadow copy of ingress filter entry.  This is in host native format
 186  * and doesn't match the ordering or bit order, etc. of the hardware of the
 187  * firmware command.  The use of bit-field structure elements is purely to
 188  * remind ourselves of the field size limitations and save memory in the case
 189  * where the filter table is large.
 190  */
 191 struct filter_entry {
 192         /* Administrative fields for filter.
 193          */
 194         u32 valid:1;            /* filter allocated and valid */
 195         u32 locked:1;           /* filter is administratively locked */
 196
 197         u32 pending:1;          /* filter action is pending firmware reply */
 198         u32 smtidx:8;           /* Source MAC Table index for smac */
 199         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 200
 201         /* The filter itself.  Most of this is a straight copy of information
 202          * provided by the extended ioctl().  Some fields are translated to
 203          * internal forms -- for instance the Ingress Queue ID passed in from
 204          * the ioctl() is translated into the Absolute Ingress Queue ID.
 205          */
 206         struct ch_filter_specification fs;
 207 };
 208
 209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
 210                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
 211                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 212
 213 /* Macros needed to support the PCI Device ID Table ...
 214  */
 215 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
 216         static struct pci_device_id cxgb4_pci_tbl[] = {
 217 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
 218
 219 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 220  * called for both.
 221  */
 222 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 223
 224 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 225                 {PCI_VDEVICE(CHELSIO, (devid)), 4}
 226
 227 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 228                 { 0, } \
 229         }
 230
 231 #include "t4_pci_id_tbl.h"
 232
 233 #define FW4_FNAME "cxgb4/t4fw.bin"
 234 #define FW5_FNAME "cxgb4/t5fw.bin"
 235 #define FW4_CFNAME "cxgb4/t4-config.txt"
 236 #define FW5_CFNAME "cxgb4/t5-config.txt"
 237
 238 MODULE_DESCRIPTION(DRV_DESC);
 239 MODULE_AUTHOR("Chelsio Communications");
 240 MODULE_LICENSE("Dual BSD/GPL");
 241 MODULE_VERSION(DRV_VERSION);
 242 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 243 MODULE_FIRMWARE(FW4_FNAME);
 244 MODULE_FIRMWARE(FW5_FNAME);
 245
 246 /*
 247  * Normally we're willing to become the firmware's Master PF but will be happy
 248  * if another PF has already become the Master and initialized the adapter.
 249  * Setting "force_init" will cause this driver to forcibly establish itself as
 250  * the Master PF and initialize the adapter.
 251  */
 252 static uint force_init;
 253
 254 module_param(force_init, uint, 0644);
 255 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
 256
 257 /*
 258  * Normally if the firmware we connect to has Configuration File support, we
 259  * use that and only fall back to the old Driver-based initialization if the
 260  * Configuration File fails for some reason.  If force_old_init is set, then
 261  * we'll always use the old Driver-based initialization sequence.
 262  */
 263 static uint force_old_init;
 264
 265 module_param(force_old_init, uint, 0644);
 266 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
 267
 268 static int dflt_msg_enable = DFLT_MSG_ENABLE;
 269
 270 module_param(dflt_msg_enable, int, 0644);
 271 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
 272
 273 /*
 274  * The driver uses the best interrupt scheme available on a platform in the
 275  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 276  * of these schemes the driver may consider as follows:
 277  *
 278  * msi = 2: choose from among all three options
 279  * msi = 1: only consider MSI and INTx interrupts
 280  * msi = 0: force INTx interrupts
 281  */
 282 static int msi = 2;
 283
 284 module_param(msi, int, 0644);
 285 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 286
 287 /*
 288  * Queue interrupt hold-off timer values.  Queues default to the first of these
 289  * upon creation.
 290  */
 291 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
 292
 293 module_param_array(intr_holdoff, uint, NULL, 0644);
 294 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
 295                  "0..4 in microseconds");
 296
 297 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
 298
 299 module_param_array(intr_cnt, uint, NULL, 0644);
 300 MODULE_PARM_DESC(intr_cnt,
 301                  "thresholds 1..3 for queue interrupt packet counters");
 302
 303 /*
 304  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 305  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 306  * boundaries.  This is a requirement for many architectures which will throw
 307  * a machine check fault if an attempt is made to access one of the 4-byte IP
 308  * header fields on a non-4-byte boundary.  And it's a major performance issue
 309  * even on some architectures which allow it like some implementations of the
 310  * x86 ISA.  However, some architectures don't mind this and for some very
 311  * edge-case performance sensitive applications (like forwarding large volumes
 312  * of small packets), setting this DMA offset to 0 will decrease the number of
 313  * PCI-E Bus transfers enough to measurably affect performance.
 314  */
 315 static int rx_dma_offset = 2;
 316
 317 static bool vf_acls;
 318
 319 #ifdef CONFIG_PCI_IOV
 320 module_param(vf_acls, bool, 0644);
 321 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
 322
 323 /* Configure the number of PCI-E Virtual Function which are to be instantiated
 324  * on SR-IOV Capable Physical Functions.
 325  */
 326 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
 327
 328 module_param_array(num_vf, uint, NULL, 0644);
 329 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
 330 #endif
 331
 332 /* TX Queue select used to determine what algorithm to use for selecting TX
 333  * queue. Select between the kernel provided function (select_queue=0) or user
 334  * cxgb_select_queue function (select_queue=1)
 335  *
 336  * Default: select_queue=0
 337  */
 338 static int select_queue;
 339 module_param(select_queue, int, 0644);
 340 MODULE_PARM_DESC(select_queue,
 341                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 342
 343 /*
 344  * The filter TCAM has a fixed portion and a variable portion.  The fixed
 345  * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
 346  * ports.  The variable portion is 36 bits which can include things like Exact
 347  * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
 348  * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
 349  * far exceed the 36-bit budget for this "compressed" header portion of the
 350  * filter.  Thus, we have a scarce resource which must be carefully managed.
 351  *
 352  * By default we set this up to mostly match the set of filter matching
 353  * capabilities of T3 but with accommodations for some of T4's more
 354  * interesting features:
 355  *
 356  *   { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
 357  *     [Inner] VLAN (17), Port (3), FCoE (1) }
 358  */
 359 enum {
 360         TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
 361         TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
 362         TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
 363 };
 364
 365 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
 366
 367 module_param(tp_vlan_pri_map, uint, 0644);
 368 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
 369
 370 static struct dentry *cxgb4_debugfs_root;
 371
 372 static LIST_HEAD(adapter_list);
 373 static DEFINE_MUTEX(uld_mutex);
 374 /* Adapter list to be accessed from atomic context */
 375 static LIST_HEAD(adap_rcu_list);
 376 static DEFINE_SPINLOCK(adap_rcu_lock);
 377 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
 378 static const char *uld_str[] = { "RDMA", "iSCSI" };
 379
 380 static void link_report(struct net_device *dev)
 381 {
 382         if (!netif_carrier_ok(dev))
 383                 netdev_info(dev, "link down\n");
 384         else {
 385                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 386
 387                 const char *s = "10Mbps";
 388                 const struct port_info *p = netdev_priv(dev);
 389
 390                 switch (p->link_cfg.speed) {
 391                 case 10000:
 392                         s = "10Gbps";
 393                         break;
 394                 case 1000:
 395                         s = "1000Mbps";
 396                         break;
 397                 case 100:
 398                         s = "100Mbps";
 399                         break;
 400                 case 40000:
 401                         s = "40Gbps";
 402                         break;
 403                 }
 404
 405                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 406                             fc[p->link_cfg.fc]);
 407         }
 408 }
 409
 410 #ifdef CONFIG_CHELSIO_T4_DCB
 411 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 412 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 413 {
 414         struct port_info *pi = netdev_priv(dev);
 415         struct adapter *adap = pi->adapter;
 416         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 417         int i;
 418
 419         /* We use a simple mapping of Port TX Queue Index to DCB
 420          * Priority when we're enabling DCB.
 421          */
 422         for (i = 0; i < pi->nqsets; i++, txq++) {
 423                 u32 name, value;
 424                 int err;
 425
 426                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 427                         FW_PARAMS_PARAM_X_V(
 428                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 429                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 430                 value = enable ? i : 0xffffffff;
 431
 432                 /* Since we can be called while atomic (from "interrupt
 433                  * level") we need to issue the Set Parameters Commannd
 434                  * without sleeping (timeout < 0).
 435                  */
 436                 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
 437                                             &name, &value);
 438
 439                 if (err)
 440                         dev_err(adap->pdev_dev,
 441                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 442                                 enable ? "set" : "unset", pi->port_id, i, -err);
 443                 else
 444                         txq->dcb_prio = value;
 445         }
 446 }
 447 #endif /* CONFIG_CHELSIO_T4_DCB */
 448
 449 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 450 {
 451         struct net_device *dev = adapter->port[port_id];
 452
 453         /* Skip changes from disabled ports. */
 454         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 455                 if (link_stat)
 456                         netif_carrier_on(dev);
 457                 else {
 458 #ifdef CONFIG_CHELSIO_T4_DCB
 459                         cxgb4_dcb_state_init(dev);
 460                         dcb_tx_queue_prio_enable(dev, false);
 461 #endif /* CONFIG_CHELSIO_T4_DCB */
 462                         netif_carrier_off(dev);
 463                 }
 464
 465                 link_report(dev);
 466         }
 467 }
 468
 469 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 470 {
 471         static const char *mod_str[] = {
 472                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 473         };
 474
 475         const struct net_device *dev = adap->port[port_id];
 476         const struct port_info *pi = netdev_priv(dev);
 477
 478         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 479                 netdev_info(dev, "port module unplugged\n");
 480         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 481                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 482 }
 483
 484 /*
 485  * Configure the exact and hash address filters to handle a port's multicast
 486  * and secondary unicast MAC addresses.
 487  */
 488 static int set_addr_filters(const struct net_device *dev, bool sleep)
 489 {
 490         u64 mhash = 0;
 491         u64 uhash = 0;
 492         bool free = true;
 493         u16 filt_idx[7];
 494         const u8 *addr[7];
 495         int ret, naddr = 0;
 496         const struct netdev_hw_addr *ha;
 497         int uc_cnt = netdev_uc_count(dev);
 498         int mc_cnt = netdev_mc_count(dev);
 499         const struct port_info *pi = netdev_priv(dev);
 500         unsigned int mb = pi->adapter->fn;
 501
 502         /* first do the secondary unicast addresses */
 503         netdev_for_each_uc_addr(ha, dev) {
 504                 addr[naddr++] = ha->addr;
 505                 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 506                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 507                                         naddr, addr, filt_idx, &uhash, sleep);
 508                         if (ret < 0)
 509                                 return ret;
 510
 511                         free = false;
 512                         naddr = 0;
 513                 }
 514         }
 515
 516         /* next set up the multicast addresses */
 517         netdev_for_each_mc_addr(ha, dev) {
 518                 addr[naddr++] = ha->addr;
 519                 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 520                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 521                                         naddr, addr, filt_idx, &mhash, sleep);
 522                         if (ret < 0)
 523                                 return ret;
 524
 525                         free = false;
 526                         naddr = 0;
 527                 }
 528         }
 529
 530         return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
 531                                 uhash | mhash, sleep);
 532 }
 533
 534 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 535 module_param(dbfifo_int_thresh, int, 0644);
 536 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 537
 538 /*
 539  * usecs to sleep while draining the dbfifo
 540  */
 541 static int dbfifo_drain_delay = 1000;
 542 module_param(dbfifo_drain_delay, int, 0644);
 543 MODULE_PARM_DESC(dbfifo_drain_delay,
 544                  "usecs to sleep while draining the dbfifo");
 545
 546 /*
 547  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 548  * If @mtu is -1 it is left unchanged.
 549  */
 550 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 551 {
 552         int ret;
 553         struct port_info *pi = netdev_priv(dev);
 554
 555         ret = set_addr_filters(dev, sleep_ok);
 556         if (ret == 0)
 557                 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
 558                                     (dev->flags & IFF_PROMISC) ? 1 : 0,
 559                                     (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 560                                     sleep_ok);
 561         return ret;
 562 }
 563
 564 /**
 565  *      link_start - enable a port
 566  *      @dev: the port to enable
 567  *
 568  *      Performs the MAC and PHY actions needed to enable a port.
 569  */
 570 static int link_start(struct net_device *dev)
 571 {
 572         int ret;
 573         struct port_info *pi = netdev_priv(dev);
 574         unsigned int mb = pi->adapter->fn;
 575
 576         /*
 577          * We do not set address filters and promiscuity here, the stack does
 578          * that step explicitly.
 579          */
 580         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 581                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 582         if (ret == 0) {
 583                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 584                                     pi->xact_addr_filt, dev->dev_addr, true,
 585                                     true);
 586                 if (ret >= 0) {
 587                         pi->xact_addr_filt = ret;
 588                         ret = 0;
 589                 }
 590         }
 591         if (ret == 0)
 592                 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
 593                                     &pi->link_cfg);
 594         if (ret == 0) {
 595                 local_bh_disable();
 596                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 597                                           true, CXGB4_DCB_ENABLED);
 598                 local_bh_enable();
 599         }
 600
 601         return ret;
 602 }
 603
 604 int cxgb4_dcb_enabled(const struct net_device *dev)
 605 {
 606 #ifdef CONFIG_CHELSIO_T4_DCB
 607         struct port_info *pi = netdev_priv(dev);
 608
 609         if (!pi->dcb.enabled)
 610                 return 0;
 611
 612         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 613                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 614 #else
 615         return 0;
 616 #endif
 617 }
 618 EXPORT_SYMBOL(cxgb4_dcb_enabled);
 619
 620 #ifdef CONFIG_CHELSIO_T4_DCB
 621 /* Handle a Data Center Bridging update message from the firmware. */
 622 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 623 {
 624         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 625         struct net_device *dev = adap->port[port];
 626         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 627         int new_dcb_enabled;
 628
 629         cxgb4_dcb_handle_fw_update(adap, pcmd);
 630         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 631
 632         /* If the DCB has become enabled or disabled on the port then we're
 633          * going to need to set up/tear down DCB Priority parameters for the
 634          * TX Queues associated with the port.
 635          */
 636         if (new_dcb_enabled != old_dcb_enabled)
 637                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 638 }
 639 #endif /* CONFIG_CHELSIO_T4_DCB */
 640
 641 /* Clear a filter and release any of its resources that we own.  This also
 642  * clears the filter's "pending" status.
 643  */
 644 static void clear_filter(struct adapter *adap, struct filter_entry *f)
 645 {
 646         /* If the new or old filter have loopback rewriteing rules then we'll
 647          * need to free any existing Layer Two Table (L2T) entries of the old
 648          * filter rule.  The firmware will handle freeing up any Source MAC
 649          * Table (SMT) entries used for rewriting Source MAC Addresses in
 650          * loopback rules.
 651          */
 652         if (f->l2t)
 653                 cxgb4_l2t_release(f->l2t);
 654
 655         /* The zeroing of the filter rule below clears the filter valid,
 656          * pending, locked flags, l2t pointer, etc. so it's all we need for
 657          * this operation.
 658          */
 659         memset(f, 0, sizeof(*f));
 660 }
 661
 662 /* Handle a filter write/deletion reply.
 663  */
 664 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
 665 {
 666         unsigned int idx = GET_TID(rpl);
 667         unsigned int nidx = idx - adap->tids.ftid_base;
 668         unsigned int ret;
 669         struct filter_entry *f;
 670
 671         if (idx >= adap->tids.ftid_base && nidx <
 672            (adap->tids.nftids + adap->tids.nsftids)) {
 673                 idx = nidx;
 674                 ret = GET_TCB_COOKIE(rpl->cookie);
 675                 f = &adap->tids.ftid_tab[idx];
 676
 677                 if (ret == FW_FILTER_WR_FLT_DELETED) {
 678                         /* Clear the filter when we get confirmation from the
 679                          * hardware that the filter has been deleted.
 680                          */
 681                         clear_filter(adap, f);
 682                 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
 683                         dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
 684                                 idx);
 685                         clear_filter(adap, f);
 686                 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
 687                         f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
 688                         f->pending = 0;  /* asynchronous setup completed */
 689                         f->valid = 1;
 690                 } else {
 691                         /* Something went wrong.  Issue a warning about the
 692                          * problem and clear everything out.
 693                          */
 694                         dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
 695                                 idx, ret);
 696                         clear_filter(adap, f);
 697                 }
 698         }
 699 }
 700
 701 /* Response queue handler for the FW event queue.
 702  */
 703 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 704                           const struct pkt_gl *gl)
 705 {
 706         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 707
 708         rsp++;                                          /* skip RSS header */
 709
 710         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 711          */
 712         if (unlikely(opcode == CPL_FW4_MSG &&
 713            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 714                 rsp++;
 715                 opcode = ((const struct rss_header *)rsp)->opcode;
 716                 rsp++;
 717                 if (opcode != CPL_SGE_EGR_UPDATE) {
 718                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 719                                 , opcode);
 720                         goto out;
 721                 }
 722         }
 723
 724         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 725                 const struct cpl_sge_egr_update *p = (void *)rsp;
 726                 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
 727                 struct sge_txq *txq;
 728
 729                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 730                 txq->restarts++;
 731                 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
 732                         struct sge_eth_txq *eq;
 733
 734                         eq = container_of(txq, struct sge_eth_txq, q);
 735                         netif_tx_wake_queue(eq->txq);
 736                 } else {
 737                         struct sge_ofld_txq *oq;
 738
 739                         oq = container_of(txq, struct sge_ofld_txq, q);
 740                         tasklet_schedule(&oq->qresume_tsk);
 741                 }
 742         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 743                 const struct cpl_fw6_msg *p = (void *)rsp;
 744
 745 #ifdef CONFIG_CHELSIO_T4_DCB
 746                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 747                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 748                 unsigned int action =
 749                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 750
 751                 if (cmd == FW_PORT_CMD &&
 752                     action == FW_PORT_ACTION_GET_PORT_INFO) {
 753                         int port = FW_PORT_CMD_PORTID_G(
 754                                         be32_to_cpu(pcmd->op_to_portid));
 755                         struct net_device *dev = q->adap->port[port];
 756                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
 757                                             FW_PORT_CMD_DCBXDIS_F)
 758                                            ? CXGB4_DCB_INPUT_FW_DISABLED
 759                                            : CXGB4_DCB_INPUT_FW_ENABLED);
 760
 761                         cxgb4_dcb_state_fsm(dev, state_input);
 762                 }
 763
 764                 if (cmd == FW_PORT_CMD &&
 765                     action == FW_PORT_ACTION_L2_DCB_CFG)
 766                         dcb_rpl(q->adap, pcmd);
 767                 else
 768 #endif
 769                         if (p->type == 0)
 770                                 t4_handle_fw_rpl(q->adap, p->data);
 771         } else if (opcode == CPL_L2T_WRITE_RPL) {
 772                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 773
 774                 do_l2t_write_rpl(q->adap, p);
 775         } else if (opcode == CPL_SET_TCB_RPL) {
 776                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 777
 778                 filter_rpl(q->adap, p);
 779         } else
 780                 dev_err(q->adap->pdev_dev,
 781                         "unexpected CPL %#x on FW event queue\n", opcode);
 782 out:
 783         return 0;
 784 }
 785
 786 /**
 787  *      uldrx_handler - response queue handler for ULD queues
 788  *      @q: the response queue that received the packet
 789  *      @rsp: the response queue descriptor holding the offload message
 790  *      @gl: the gather list of packet fragments
 791  *
 792  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 793  *      the ULD, we just maintain statistics.
 794  */
 795 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 796                          const struct pkt_gl *gl)
 797 {
 798         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 799
 800         /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
 801          */
 802         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
 803             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
 804                 rsp += 2;
 805
 806         if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
 807                 rxq->stats.nomem++;
 808                 return -1;
 809         }
 810         if (gl == NULL)
 811                 rxq->stats.imm++;
 812         else if (gl == CXGB4_MSG_AN)
 813                 rxq->stats.an++;
 814         else
 815                 rxq->stats.pkts++;
 816         return 0;
 817 }
 818
 819 static void disable_msi(struct adapter *adapter)
 820 {
 821         if (adapter->flags & USING_MSIX) {
 822                 pci_disable_msix(adapter->pdev);
 823                 adapter->flags &= ~USING_MSIX;
 824         } else if (adapter->flags & USING_MSI) {
 825                 pci_disable_msi(adapter->pdev);
 826                 adapter->flags &= ~USING_MSI;
 827         }
 828 }
 829
 830 /*
 831  * Interrupt handler for non-data events used with MSI-X.
 832  */
 833 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 834 {
 835         struct adapter *adap = cookie;
 836
 837         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
 838         if (v & PFSW) {
 839                 adap->swintr = 1;
 840                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
 841         }
 842         t4_slow_intr_handler(adap);
 843         return IRQ_HANDLED;
 844 }
 845
 846 /*
 847  * Name the MSI-X interrupts.
 848  */
 849 static void name_msix_vecs(struct adapter *adap)
 850 {
 851         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 852
 853         /* non-data interrupts */
 854         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 855
 856         /* FW events */
 857         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 858                  adap->port[0]->name);
 859
 860         /* Ethernet queues */
 861         for_each_port(adap, j) {
 862                 struct net_device *d = adap->port[j];
 863                 const struct port_info *pi = netdev_priv(d);
 864
 865                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 866                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 867                                  d->name, i);
 868         }
 869
 870         /* offload queues */
 871         for_each_ofldrxq(&adap->sge, i)
 872                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
 873                          adap->port[0]->name, i);
 874
 875         for_each_rdmarxq(&adap->sge, i)
 876                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
 877                          adap->port[0]->name, i);
 878
 879         for_each_rdmaciq(&adap->sge, i)
 880                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
 881                          adap->port[0]->name, i);
 882 }
 883
 884 static int request_msix_queue_irqs(struct adapter *adap)
 885 {
 886         struct sge *s = &adap->sge;
 887         int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
 888         int msi_index = 2;
 889
 890         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 891                           adap->msix_info[1].desc, &s->fw_evtq);
 892         if (err)
 893                 return err;
 894
 895         for_each_ethrxq(s, ethqidx) {
 896                 err = request_irq(adap->msix_info[msi_index].vec,
 897                                   t4_sge_intr_msix, 0,
 898                                   adap->msix_info[msi_index].desc,
 899                                   &s->ethrxq[ethqidx].rspq);
 900                 if (err)
 901                         goto unwind;
 902                 msi_index++;
 903         }
 904         for_each_ofldrxq(s, ofldqidx) {
 905                 err = request_irq(adap->msix_info[msi_index].vec,
 906                                   t4_sge_intr_msix, 0,
 907                                   adap->msix_info[msi_index].desc,
 908                                   &s->ofldrxq[ofldqidx].rspq);
 909                 if (err)
 910                         goto unwind;
 911                 msi_index++;
 912         }
 913         for_each_rdmarxq(s, rdmaqidx) {
 914                 err = request_irq(adap->msix_info[msi_index].vec,
 915                                   t4_sge_intr_msix, 0,
 916                                   adap->msix_info[msi_index].desc,
 917                                   &s->rdmarxq[rdmaqidx].rspq);
 918                 if (err)
 919                         goto unwind;
 920                 msi_index++;
 921         }
 922         for_each_rdmaciq(s, rdmaciqqidx) {
 923                 err = request_irq(adap->msix_info[msi_index].vec,
 924                                   t4_sge_intr_msix, 0,
 925                                   adap->msix_info[msi_index].desc,
 926                                   &s->rdmaciq[rdmaciqqidx].rspq);
 927                 if (err)
 928                         goto unwind;
 929                 msi_index++;
 930         }
 931         return 0;
 932
 933 unwind:
 934         while (--rdmaciqqidx >= 0)
 935                 free_irq(adap->msix_info[--msi_index].vec,
 936                          &s->rdmaciq[rdmaciqqidx].rspq);
 937         while (--rdmaqidx >= 0)
 938                 free_irq(adap->msix_info[--msi_index].vec,
 939                          &s->rdmarxq[rdmaqidx].rspq);
 940         while (--ofldqidx >= 0)
 941                 free_irq(adap->msix_info[--msi_index].vec,
 942                          &s->ofldrxq[ofldqidx].rspq);
 943         while (--ethqidx >= 0)
 944                 free_irq(adap->msix_info[--msi_index].vec,
 945                          &s->ethrxq[ethqidx].rspq);
 946         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 947         return err;
 948 }
 949
 950 static void free_msix_queue_irqs(struct adapter *adap)
 951 {
 952         int i, msi_index = 2;
 953         struct sge *s = &adap->sge;
 954
 955         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 956         for_each_ethrxq(s, i)
 957                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
 958         for_each_ofldrxq(s, i)
 959                 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
 960         for_each_rdmarxq(s, i)
 961                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
 962         for_each_rdmaciq(s, i)
 963                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
 964 }
 965
 966 /**
 967  *      write_rss - write the RSS table for a given port
 968  *      @pi: the port
 969  *      @queues: array of queue indices for RSS
 970  *
 971  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 972  *      packets to the Rx queues in @queues.
 973  */
 974 static int write_rss(const struct port_info *pi, const u16 *queues)
 975 {
 976         u16 *rss;
 977         int i, err;
 978         const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
 979
 980         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
 981         if (!rss)
 982                 return -ENOMEM;
 983
 984         /* map the queue indices to queue ids */
 985         for (i = 0; i < pi->rss_size; i++, queues++)
 986                 rss[i] = q[*queues].rspq.abs_id;
 987
 988         err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
 989                                   pi->rss_size, rss, pi->rss_size);
 990         kfree(rss);
 991         return err;
 992 }
 993
 994 /**
 995  *      setup_rss - configure RSS
 996  *      @adap: the adapter
 997  *
 998  *      Sets up RSS for each port.
 999  */
1000 static int setup_rss(struct adapter *adap)
1001 {
1002         int i, err;
1003
1004         for_each_port(adap, i) {
1005                 const struct port_info *pi = adap2pinfo(adap, i);
1006
1007                 err = write_rss(pi, pi->rss);
1008                 if (err)
1009                         return err;
1010         }
1011         return 0;
1012 }
1013
1014 /*
1015  * Return the channel of the ingress queue with the given qid.
1016  */
1017 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1018 {
1019         qid -= p->ingr_start;
1020         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1021 }
1022
1023 /*
1024  * Wait until all NAPI handlers are descheduled.
1025  */
1026 static void quiesce_rx(struct adapter *adap)
1027 {
1028         int i;
1029
1030         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1031                 struct sge_rspq *q = adap->sge.ingr_map[i];
1032
1033                 if (q && q->handler)
1034                         napi_disable(&q->napi);
1035         }
1036 }
1037
1038 /*
1039  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1040  */
1041 static void enable_rx(struct adapter *adap)
1042 {
1043         int i;
1044
1045         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1046                 struct sge_rspq *q = adap->sge.ingr_map[i];
1047
1048                 if (!q)
1049                         continue;
1050                 if (q->handler)
1051                         napi_enable(&q->napi);
1052                 /* 0-increment GTS to start the timer and enable interrupts */
1053                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1054                              SEINTARM(q->intr_params) |
1055                              INGRESSQID(q->cntxt_id));
1056         }
1057 }
1058
1059 /**
1060  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1061  *      @adap: the adapter
1062  *
1063  *      Determines how many sets of SGE queues to use and initializes them.
1064  *      We support multiple queue sets per port if we have MSI-X, otherwise
1065  *      just one queue set per port.
1066  */
1067 static int setup_sge_queues(struct adapter *adap)
1068 {
1069         int err, msi_idx, i, j;
1070         struct sge *s = &adap->sge;
1071
1072         bitmap_zero(s->starving_fl, MAX_EGRQ);
1073         bitmap_zero(s->txq_maperr, MAX_EGRQ);
1074
1075         if (adap->flags & USING_MSIX)
1076                 msi_idx = 1;         /* vector 0 is for non-queue interrupts */
1077         else {
1078                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1079                                        NULL, NULL);
1080                 if (err)
1081                         return err;
1082                 msi_idx = -((int)s->intrq.abs_id + 1);
1083         }
1084
1085         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1086                                msi_idx, NULL, fwevtq_handler);
1087         if (err) {
1088 freeout:        t4_free_sge_resources(adap);
1089                 return err;
1090         }
1091
1092         for_each_port(adap, i) {
1093                 struct net_device *dev = adap->port[i];
1094                 struct port_info *pi = netdev_priv(dev);
1095                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1096                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1097
1098                 for (j = 0; j < pi->nqsets; j++, q++) {
1099                         if (msi_idx > 0)
1100                                 msi_idx++;
1101                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1102                                                msi_idx, &q->fl,
1103                                                t4_ethrx_handler);
1104                         if (err)
1105                                 goto freeout;
1106                         q->rspq.idx = j;
1107                         memset(&q->stats, 0, sizeof(q->stats));
1108                 }
1109                 for (j = 0; j < pi->nqsets; j++, t++) {
1110                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1111                                         netdev_get_tx_queue(dev, j),
1112                                         s->fw_evtq.cntxt_id);
1113                         if (err)
1114                                 goto freeout;
1115                 }
1116         }
1117
1118         j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1119         for_each_ofldrxq(s, i) {
1120                 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1121                 struct net_device *dev = adap->port[i / j];
1122
1123                 if (msi_idx > 0)
1124                         msi_idx++;
1125                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1126                                        q->fl.size ? &q->fl : NULL,
1127                                        uldrx_handler);
1128                 if (err)
1129                         goto freeout;
1130                 memset(&q->stats, 0, sizeof(q->stats));
1131                 s->ofld_rxq[i] = q->rspq.abs_id;
1132                 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1133                                             s->fw_evtq.cntxt_id);
1134                 if (err)
1135                         goto freeout;
1136         }
1137
1138         for_each_rdmarxq(s, i) {
1139                 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1140
1141                 if (msi_idx > 0)
1142                         msi_idx++;
1143                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1144                                        msi_idx, q->fl.size ? &q->fl : NULL,
1145                                        uldrx_handler);
1146                 if (err)
1147                         goto freeout;
1148                 memset(&q->stats, 0, sizeof(q->stats));
1149                 s->rdma_rxq[i] = q->rspq.abs_id;
1150         }
1151
1152         for_each_rdmaciq(s, i) {
1153                 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1154
1155                 if (msi_idx > 0)
1156                         msi_idx++;
1157                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1158                                        msi_idx, q->fl.size ? &q->fl : NULL,
1159                                        uldrx_handler);
1160                 if (err)
1161                         goto freeout;
1162                 memset(&q->stats, 0, sizeof(q->stats));
1163                 s->rdma_ciq[i] = q->rspq.abs_id;
1164         }
1165
1166         for_each_port(adap, i) {
1167                 /*
1168                  * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1169                  * have RDMA queues, and that's the right value.
1170                  */
1171                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1172                                             s->fw_evtq.cntxt_id,
1173                                             s->rdmarxq[i].rspq.cntxt_id);
1174                 if (err)
1175                         goto freeout;
1176         }
1177
1178         t4_write_reg(adap, is_t4(adap->params.chip) ?
1179                                 MPS_TRC_RSS_CONTROL :
1180                                 MPS_T5_TRC_RSS_CONTROL,
1181                      RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1182                      QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1183         return 0;
1184 }
1185
1186 /*
1187  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1188  * The allocated memory is cleared.
1189  */
1190 void *t4_alloc_mem(size_t size)
1191 {
1192         void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1193
1194         if (!p)
1195                 p = vzalloc(size);
1196         return p;
1197 }
1198
1199 /*
1200  * Free memory allocated through alloc_mem().
1201  */
1202 void t4_free_mem(void *addr)
1203 {
1204         if (is_vmalloc_addr(addr))
1205                 vfree(addr);
1206         else
1207                 kfree(addr);
1208 }
1209
1210 /* Send a Work Request to write the filter at a specified index.  We construct
1211  * a Firmware Filter Work Request to have the work done and put the indicated
1212  * filter into "pending" mode which will prevent any further actions against
1213  * it till we get a reply from the firmware on the completion status of the
1214  * request.
1215  */
1216 static int set_filter_wr(struct adapter *adapter, int fidx)
1217 {
1218         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1219         struct sk_buff *skb;
1220         struct fw_filter_wr *fwr;
1221         unsigned int ftid;
1222
1223         /* If the new filter requires loopback Destination MAC and/or VLAN
1224          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1225          * the filter.
1226          */
1227         if (f->fs.newdmac || f->fs.newvlan) {
1228                 /* allocate L2T entry for new filter */
1229                 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1230                 if (f->l2t == NULL)
1231                         return -EAGAIN;
1232                 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1233                                         f->fs.eport, f->fs.dmac)) {
1234                         cxgb4_l2t_release(f->l2t);
1235                         f->l2t = NULL;
1236                         return -ENOMEM;
1237                 }
1238         }
1239
1240         ftid = adapter->tids.ftid_base + fidx;
1241
1242         skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1243         fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1244         memset(fwr, 0, sizeof(*fwr));
1245
1246         /* It would be nice to put most of the following in t4_hw.c but most
1247          * of the work is translating the cxgbtool ch_filter_specification
1248          * into the Work Request and the definition of that structure is
1249          * currently in cxgbtool.h which isn't appropriate to pull into the
1250          * common code.  We may eventually try to come up with a more neutral
1251          * filter specification structure but for now it's easiest to simply
1252          * put this fairly direct code in line ...
1253          */
1254         fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1255         fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1256         fwr->tid_to_iq =
1257                 htonl(FW_FILTER_WR_TID_V(ftid) |
1258                       FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1259                       FW_FILTER_WR_NOREPLY_V(0) |
1260                       FW_FILTER_WR_IQ_V(f->fs.iq));
1261         fwr->del_filter_to_l2tix =
1262                 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1263                       FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1264                       FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1265                       FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1266                       FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1267                       FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1268                       FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1269                       FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1270                       FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1271                                              f->fs.newvlan == VLAN_REWRITE) |
1272                       FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1273                                             f->fs.newvlan == VLAN_REWRITE) |
1274                       FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1275                       FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1276                       FW_FILTER_WR_PRIO_V(f->fs.prio) |
1277                       FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1278         fwr->ethtype = htons(f->fs.val.ethtype);
1279         fwr->ethtypem = htons(f->fs.mask.ethtype);
1280         fwr->frag_to_ovlan_vldm =
1281                 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1282                  FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1283                  FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1284                  FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1285                  FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1286                  FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1287         fwr->smac_sel = 0;
1288         fwr->rx_chan_rx_rpl_iq =
1289                 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1290                       FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1291         fwr->maci_to_matchtypem =
1292                 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1293                       FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1294                       FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1295                       FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1296                       FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1297                       FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1298                       FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1299                       FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1300         fwr->ptcl = f->fs.val.proto;
1301         fwr->ptclm = f->fs.mask.proto;
1302         fwr->ttyp = f->fs.val.tos;
1303         fwr->ttypm = f->fs.mask.tos;
1304         fwr->ivlan = htons(f->fs.val.ivlan);
1305         fwr->ivlanm = htons(f->fs.mask.ivlan);
1306         fwr->ovlan = htons(f->fs.val.ovlan);
1307         fwr->ovlanm = htons(f->fs.mask.ovlan);
1308         memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1309         memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1310         memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1311         memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1312         fwr->lp = htons(f->fs.val.lport);
1313         fwr->lpm = htons(f->fs.mask.lport);
1314         fwr->fp = htons(f->fs.val.fport);
1315         fwr->fpm = htons(f->fs.mask.fport);
1316         if (f->fs.newsmac)
1317                 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1318
1319         /* Mark the filter as "pending" and ship off the Filter Work Request.
1320          * When we get the Work Request Reply we'll clear the pending status.
1321          */
1322         f->pending = 1;
1323         set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1324         t4_ofld_send(adapter, skb);
1325         return 0;
1326 }
1327
1328 /* Delete the filter at a specified index.
1329  */
1330 static int del_filter_wr(struct adapter *adapter, int fidx)
1331 {
1332         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1333         struct sk_buff *skb;
1334         struct fw_filter_wr *fwr;
1335         unsigned int len, ftid;
1336
1337         len = sizeof(*fwr);
1338         ftid = adapter->tids.ftid_base + fidx;
1339
1340         skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1341         fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1342         t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1343
1344         /* Mark the filter as "pending" and ship off the Filter Work Request.
1345          * When we get the Work Request Reply we'll clear the pending status.
1346          */
1347         f->pending = 1;
1348         t4_mgmt_tx(adapter, skb);
1349         return 0;
1350 }
1351
1352 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1353                              void *accel_priv, select_queue_fallback_t fallback)
1354 {
1355         int txq;
1356
1357 #ifdef CONFIG_CHELSIO_T4_DCB
1358         /* If a Data Center Bridging has been successfully negotiated on this
1359          * link then we'll use the skb's priority to map it to a TX Queue.
1360          * The skb's priority is determined via the VLAN Tag Priority Code
1361          * Point field.
1362          */
1363         if (cxgb4_dcb_enabled(dev)) {
1364                 u16 vlan_tci;
1365                 int err;
1366
1367                 err = vlan_get_tag(skb, &vlan_tci);
1368                 if (unlikely(err)) {
1369                         if (net_ratelimit())
1370                                 netdev_warn(dev,
1371                                             "TX Packet without VLAN Tag on DCB Link\n");
1372                         txq = 0;
1373                 } else {
1374                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1375                 }
1376                 return txq;
1377         }
1378 #endif /* CONFIG_CHELSIO_T4_DCB */
1379
1380         if (select_queue) {
1381                 txq = (skb_rx_queue_recorded(skb)
1382                         ? skb_get_rx_queue(skb)
1383                         : smp_processor_id());
1384
1385                 while (unlikely(txq >= dev->real_num_tx_queues))
1386                         txq -= dev->real_num_tx_queues;
1387
1388                 return txq;
1389         }
1390
1391         return fallback(dev, skb) % dev->real_num_tx_queues;
1392 }
1393
1394 static inline int is_offload(const struct adapter *adap)
1395 {
1396         return adap->params.offload;
1397 }
1398
1399 /*
1400  * Implementation of ethtool operations.
1401  */
1402
1403 static u32 get_msglevel(struct net_device *dev)
1404 {
1405         return netdev2adap(dev)->msg_enable;
1406 }
1407
1408 static void set_msglevel(struct net_device *dev, u32 val)
1409 {
1410         netdev2adap(dev)->msg_enable = val;
1411 }
1412
1413 static char stats_strings[][ETH_GSTRING_LEN] = {
1414         "TxOctetsOK         ",
1415         "TxFramesOK         ",
1416         "TxBroadcastFrames  ",
1417         "TxMulticastFrames  ",
1418         "TxUnicastFrames    ",
1419         "TxErrorFrames      ",
1420
1421         "TxFrames64         ",
1422         "TxFrames65To127    ",
1423         "TxFrames128To255   ",
1424         "TxFrames256To511   ",
1425         "TxFrames512To1023  ",
1426         "TxFrames1024To1518 ",
1427         "TxFrames1519ToMax  ",
1428
1429         "TxFramesDropped    ",
1430         "TxPauseFrames      ",
1431         "TxPPP0Frames       ",
1432         "TxPPP1Frames       ",
1433         "TxPPP2Frames       ",
1434         "TxPPP3Frames       ",
1435         "TxPPP4Frames       ",
1436         "TxPPP5Frames       ",
1437         "TxPPP6Frames       ",
1438         "TxPPP7Frames       ",
1439
1440         "RxOctetsOK         ",
1441         "RxFramesOK         ",
1442         "RxBroadcastFrames  ",
1443         "RxMulticastFrames  ",
1444         "RxUnicastFrames    ",
1445
1446         "RxFramesTooLong    ",
1447         "RxJabberErrors     ",
1448         "RxFCSErrors        ",
1449         "RxLengthErrors     ",
1450         "RxSymbolErrors     ",
1451         "RxRuntFrames       ",
1452
1453         "RxFrames64         ",
1454         "RxFrames65To127    ",
1455         "RxFrames128To255   ",
1456         "RxFrames256To511   ",
1457         "RxFrames512To1023  ",
1458         "RxFrames1024To1518 ",
1459         "RxFrames1519ToMax  ",
1460
1461         "RxPauseFrames      ",
1462         "RxPPP0Frames       ",
1463         "RxPPP1Frames       ",
1464         "RxPPP2Frames       ",
1465         "RxPPP3Frames       ",
1466         "RxPPP4Frames       ",
1467         "RxPPP5Frames       ",
1468         "RxPPP6Frames       ",
1469         "RxPPP7Frames       ",
1470
1471         "RxBG0FramesDropped ",
1472         "RxBG1FramesDropped ",
1473         "RxBG2FramesDropped ",
1474         "RxBG3FramesDropped ",
1475         "RxBG0FramesTrunc   ",
1476         "RxBG1FramesTrunc   ",
1477         "RxBG2FramesTrunc   ",
1478         "RxBG3FramesTrunc   ",
1479
1480         "TSO                ",
1481         "TxCsumOffload      ",
1482         "RxCsumGood         ",
1483         "VLANextractions    ",
1484         "VLANinsertions     ",
1485         "GROpackets         ",
1486         "GROmerged          ",
1487         "WriteCoalSuccess   ",
1488         "WriteCoalFail      ",
1489 };
1490
1491 static int get_sset_count(struct net_device *dev, int sset)
1492 {
1493         switch (sset) {
1494         case ETH_SS_STATS:
1495                 return ARRAY_SIZE(stats_strings);
1496         default:
1497                 return -EOPNOTSUPP;
1498         }
1499 }
1500
1501 #define T4_REGMAP_SIZE (160 * 1024)
1502 #define T5_REGMAP_SIZE (332 * 1024)
1503
1504 static int get_regs_len(struct net_device *dev)
1505 {
1506         struct adapter *adap = netdev2adap(dev);
1507         if (is_t4(adap->params.chip))
1508                 return T4_REGMAP_SIZE;
1509         else
1510                 return T5_REGMAP_SIZE;
1511 }
1512
1513 static int get_eeprom_len(struct net_device *dev)
1514 {
1515         return EEPROMSIZE;
1516 }
1517
1518 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1519 {
1520         struct adapter *adapter = netdev2adap(dev);
1521
1522         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1523         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1524         strlcpy(info->bus_info, pci_name(adapter->pdev),
1525                 sizeof(info->bus_info));
1526
1527         if (adapter->params.fw_vers)
1528                 snprintf(info->fw_version, sizeof(info->fw_version),
1529                         "%u.%u.%u.%u, TP %u.%u.%u.%u",
1530                         FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
1531                         FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
1532                         FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
1533                         FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers),
1534                         FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
1535                         FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
1536                         FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
1537                         FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
1538 }
1539
1540 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1541 {
1542         if (stringset == ETH_SS_STATS)
1543                 memcpy(data, stats_strings, sizeof(stats_strings));
1544 }
1545
1546 /*
1547  * port stats maintained per queue of the port.  They should be in the same
1548  * order as in stats_strings above.
1549  */
1550 struct queue_port_stats {
1551         u64 tso;
1552         u64 tx_csum;
1553         u64 rx_csum;
1554         u64 vlan_ex;
1555         u64 vlan_ins;
1556         u64 gro_pkts;
1557         u64 gro_merged;
1558 };
1559
1560 static void collect_sge_port_stats(const struct adapter *adap,
1561                 const struct port_info *p, struct queue_port_stats *s)
1562 {
1563         int i;
1564         const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1565         const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1566
1567         memset(s, 0, sizeof(*s));
1568         for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1569                 s->tso += tx->tso;
1570                 s->tx_csum += tx->tx_cso;
1571                 s->rx_csum += rx->stats.rx_cso;
1572                 s->vlan_ex += rx->stats.vlan_ex;
1573                 s->vlan_ins += tx->vlan_ins;
1574                 s->gro_pkts += rx->stats.lro_pkts;
1575                 s->gro_merged += rx->stats.lro_merged;
1576         }
1577 }
1578
1579 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1580                       u64 *data)
1581 {
1582         struct port_info *pi = netdev_priv(dev);
1583         struct adapter *adapter = pi->adapter;
1584         u32 val1, val2;
1585
1586         t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1587
1588         data += sizeof(struct port_stats) / sizeof(u64);
1589         collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1590         data += sizeof(struct queue_port_stats) / sizeof(u64);
1591         if (!is_t4(adapter->params.chip)) {
1592                 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1593                 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1594                 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1595                 *data = val1 - val2;
1596                 data++;
1597                 *data = val2;
1598                 data++;
1599         } else {
1600                 memset(data, 0, 2 * sizeof(u64));
1601                 *data += 2;
1602         }
1603 }
1604
1605 /*
1606  * Return a version number to identify the type of adapter.  The scheme is:
1607  * - bits 0..9: chip version
1608  * - bits 10..15: chip revision
1609  * - bits 16..23: register dump version
1610  */
1611 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1612 {
1613         return CHELSIO_CHIP_VERSION(ap->params.chip) |
1614                 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1615 }
1616
1617 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1618                            unsigned int end)
1619 {
1620         u32 *p = buf + start;
1621
1622         for ( ; start <= end; start += sizeof(u32))
1623                 *p++ = t4_read_reg(ap, start);
1624 }
1625
1626 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1627                      void *buf)
1628 {
1629         static const unsigned int t4_reg_ranges[] = {
1630                 0x1008, 0x1108,
1631                 0x1180, 0x11b4,
1632                 0x11fc, 0x123c,
1633                 0x1300, 0x173c,
1634                 0x1800, 0x18fc,
1635                 0x3000, 0x30d8,
1636                 0x30e0, 0x5924,
1637                 0x5960, 0x59d4,
1638                 0x5a00, 0x5af8,
1639                 0x6000, 0x6098,
1640                 0x6100, 0x6150,
1641                 0x6200, 0x6208,
1642                 0x6240, 0x6248,
1643                 0x6280, 0x6338,
1644                 0x6370, 0x638c,
1645                 0x6400, 0x643c,
1646                 0x6500, 0x6524,
1647                 0x6a00, 0x6a38,
1648                 0x6a60, 0x6a78,
1649                 0x6b00, 0x6b84,
1650                 0x6bf0, 0x6c84,
1651                 0x6cf0, 0x6d84,
1652                 0x6df0, 0x6e84,
1653                 0x6ef0, 0x6f84,
1654                 0x6ff0, 0x7084,
1655                 0x70f0, 0x7184,
1656                 0x71f0, 0x7284,
1657                 0x72f0, 0x7384,
1658                 0x73f0, 0x7450,
1659                 0x7500, 0x7530,
1660                 0x7600, 0x761c,
1661                 0x7680, 0x76cc,
1662                 0x7700, 0x7798,
1663                 0x77c0, 0x77fc,
1664                 0x7900, 0x79fc,
1665                 0x7b00, 0x7c38,
1666                 0x7d00, 0x7efc,
1667                 0x8dc0, 0x8e1c,
1668                 0x8e30, 0x8e78,
1669                 0x8ea0, 0x8f6c,
1670                 0x8fc0, 0x9074,
1671                 0x90fc, 0x90fc,
1672                 0x9400, 0x9458,
1673                 0x9600, 0x96bc,
1674                 0x9800, 0x9808,
1675                 0x9820, 0x983c,
1676                 0x9850, 0x9864,
1677                 0x9c00, 0x9c6c,
1678                 0x9c80, 0x9cec,
1679                 0x9d00, 0x9d6c,
1680                 0x9d80, 0x9dec,
1681                 0x9e00, 0x9e6c,
1682                 0x9e80, 0x9eec,
1683                 0x9f00, 0x9f6c,
1684                 0x9f80, 0x9fec,
1685                 0xd004, 0xd03c,
1686                 0xdfc0, 0xdfe0,
1687                 0xe000, 0xea7c,
1688                 0xf000, 0x11110,
1689                 0x11118, 0x11190,
1690                 0x19040, 0x1906c,
1691                 0x19078, 0x19080,
1692                 0x1908c, 0x19124,
1693                 0x19150, 0x191b0,
1694                 0x191d0, 0x191e8,
1695                 0x19238, 0x1924c,
1696                 0x193f8, 0x19474,
1697                 0x19490, 0x194f8,
1698                 0x19800, 0x19f30,
1699                 0x1a000, 0x1a06c,
1700                 0x1a0b0, 0x1a120,
1701                 0x1a128, 0x1a138,
1702                 0x1a190, 0x1a1c4,
1703                 0x1a1fc, 0x1a1fc,
1704                 0x1e040, 0x1e04c,
1705                 0x1e284, 0x1e28c,
1706                 0x1e2c0, 0x1e2c0,
1707                 0x1e2e0, 0x1e2e0,
1708                 0x1e300, 0x1e384,
1709                 0x1e3c0, 0x1e3c8,
1710                 0x1e440, 0x1e44c,
1711                 0x1e684, 0x1e68c,
1712                 0x1e6c0, 0x1e6c0,
1713                 0x1e6e0, 0x1e6e0,
1714                 0x1e700, 0x1e784,
1715                 0x1e7c0, 0x1e7c8,
1716                 0x1e840, 0x1e84c,
1717                 0x1ea84, 0x1ea8c,
1718                 0x1eac0, 0x1eac0,
1719                 0x1eae0, 0x1eae0,
1720                 0x1eb00, 0x1eb84,
1721                 0x1ebc0, 0x1ebc8,
1722                 0x1ec40, 0x1ec4c,
1723                 0x1ee84, 0x1ee8c,
1724                 0x1eec0, 0x1eec0,
1725                 0x1eee0, 0x1eee0,
1726                 0x1ef00, 0x1ef84,
1727                 0x1efc0, 0x1efc8,
1728                 0x1f040, 0x1f04c,
1729                 0x1f284, 0x1f28c,
1730                 0x1f2c0, 0x1f2c0,
1731                 0x1f2e0, 0x1f2e0,
1732                 0x1f300, 0x1f384,
1733                 0x1f3c0, 0x1f3c8,
1734                 0x1f440, 0x1f44c,
1735                 0x1f684, 0x1f68c,
1736                 0x1f6c0, 0x1f6c0,
1737                 0x1f6e0, 0x1f6e0,
1738                 0x1f700, 0x1f784,
1739                 0x1f7c0, 0x1f7c8,
1740                 0x1f840, 0x1f84c,
1741                 0x1fa84, 0x1fa8c,
1742                 0x1fac0, 0x1fac0,
1743                 0x1fae0, 0x1fae0,
1744                 0x1fb00, 0x1fb84,
1745                 0x1fbc0, 0x1fbc8,
1746                 0x1fc40, 0x1fc4c,
1747                 0x1fe84, 0x1fe8c,
1748                 0x1fec0, 0x1fec0,
1749                 0x1fee0, 0x1fee0,
1750                 0x1ff00, 0x1ff84,
1751                 0x1ffc0, 0x1ffc8,
1752                 0x20000, 0x2002c,
1753                 0x20100, 0x2013c,
1754                 0x20190, 0x201c8,
1755                 0x20200, 0x20318,
1756                 0x20400, 0x20528,
1757                 0x20540, 0x20614,
1758                 0x21000, 0x21040,
1759                 0x2104c, 0x21060,
1760                 0x210c0, 0x210ec,
1761                 0x21200, 0x21268,
1762                 0x21270, 0x21284,
1763                 0x212fc, 0x21388,
1764                 0x21400, 0x21404,
1765                 0x21500, 0x21518,
1766                 0x2152c, 0x2153c,
1767                 0x21550, 0x21554,
1768                 0x21600, 0x21600,
1769                 0x21608, 0x21628,
1770                 0x21630, 0x2163c,
1771                 0x21700, 0x2171c,
1772                 0x21780, 0x2178c,
1773                 0x21800, 0x21c38,
1774                 0x21c80, 0x21d7c,
1775                 0x21e00, 0x21e04,
1776                 0x22000, 0x2202c,
1777                 0x22100, 0x2213c,
1778                 0x22190, 0x221c8,
1779                 0x22200, 0x22318,
1780                 0x22400, 0x22528,
1781                 0x22540, 0x22614,
1782                 0x23000, 0x23040,
1783                 0x2304c, 0x23060,
1784                 0x230c0, 0x230ec,
1785                 0x23200, 0x23268,
1786                 0x23270, 0x23284,
1787                 0x232fc, 0x23388,
1788                 0x23400, 0x23404,
1789                 0x23500, 0x23518,
1790                 0x2352c, 0x2353c,
1791                 0x23550, 0x23554,
1792                 0x23600, 0x23600,
1793                 0x23608, 0x23628,
1794                 0x23630, 0x2363c,
1795                 0x23700, 0x2371c,
1796                 0x23780, 0x2378c,
1797                 0x23800, 0x23c38,
1798                 0x23c80, 0x23d7c,
1799                 0x23e00, 0x23e04,
1800                 0x24000, 0x2402c,
1801                 0x24100, 0x2413c,
1802                 0x24190, 0x241c8,
1803                 0x24200, 0x24318,
1804                 0x24400, 0x24528,
1805                 0x24540, 0x24614,
1806                 0x25000, 0x25040,
1807                 0x2504c, 0x25060,
1808                 0x250c0, 0x250ec,
1809                 0x25200, 0x25268,
1810                 0x25270, 0x25284,
1811                 0x252fc, 0x25388,
1812                 0x25400, 0x25404,
1813                 0x25500, 0x25518,
1814                 0x2552c, 0x2553c,
1815                 0x25550, 0x25554,
1816                 0x25600, 0x25600,
1817                 0x25608, 0x25628,
1818                 0x25630, 0x2563c,
1819                 0x25700, 0x2571c,
1820                 0x25780, 0x2578c,
1821                 0x25800, 0x25c38,
1822                 0x25c80, 0x25d7c,
1823                 0x25e00, 0x25e04,
1824                 0x26000, 0x2602c,
1825                 0x26100, 0x2613c,
1826                 0x26190, 0x261c8,
1827                 0x26200, 0x26318,
1828                 0x26400, 0x26528,
1829                 0x26540, 0x26614,
1830                 0x27000, 0x27040,
1831                 0x2704c, 0x27060,
1832                 0x270c0, 0x270ec,
1833                 0x27200, 0x27268,
1834                 0x27270, 0x27284,
1835                 0x272fc, 0x27388,
1836                 0x27400, 0x27404,
1837                 0x27500, 0x27518,
1838                 0x2752c, 0x2753c,
1839                 0x27550, 0x27554,
1840                 0x27600, 0x27600,
1841                 0x27608, 0x27628,
1842                 0x27630, 0x2763c,
1843                 0x27700, 0x2771c,
1844                 0x27780, 0x2778c,
1845                 0x27800, 0x27c38,
1846                 0x27c80, 0x27d7c,
1847                 0x27e00, 0x27e04
1848         };
1849
1850         static const unsigned int t5_reg_ranges[] = {
1851                 0x1008, 0x1148,
1852                 0x1180, 0x11b4,
1853                 0x11fc, 0x123c,
1854                 0x1280, 0x173c,
1855                 0x1800, 0x18fc,
1856                 0x3000, 0x3028,
1857                 0x3060, 0x30d8,
1858                 0x30e0, 0x30fc,
1859                 0x3140, 0x357c,
1860                 0x35a8, 0x35cc,
1861                 0x35ec, 0x35ec,
1862                 0x3600, 0x5624,
1863                 0x56cc, 0x575c,
1864                 0x580c, 0x5814,
1865                 0x5890, 0x58bc,
1866                 0x5940, 0x59dc,
1867                 0x59fc, 0x5a18,
1868                 0x5a60, 0x5a9c,
1869                 0x5b9c, 0x5bfc,
1870                 0x6000, 0x6040,
1871                 0x6058, 0x614c,
1872                 0x7700, 0x7798,
1873                 0x77c0, 0x78fc,
1874                 0x7b00, 0x7c54,
1875                 0x7d00, 0x7efc,
1876                 0x8dc0, 0x8de0,
1877                 0x8df8, 0x8e84,
1878                 0x8ea0, 0x8f84,
1879                 0x8fc0, 0x90f8,
1880                 0x9400, 0x9470,
1881                 0x9600, 0x96f4,
1882                 0x9800, 0x9808,
1883                 0x9820, 0x983c,
1884                 0x9850, 0x9864,
1885                 0x9c00, 0x9c6c,
1886                 0x9c80, 0x9cec,
1887                 0x9d00, 0x9d6c,
1888                 0x9d80, 0x9dec,
1889                 0x9e00, 0x9e6c,
1890                 0x9e80, 0x9eec,
1891                 0x9f00, 0x9f6c,
1892                 0x9f80, 0xa020,
1893                 0xd004, 0xd03c,
1894                 0xdfc0, 0xdfe0,
1895                 0xe000, 0x11088,
1896                 0x1109c, 0x11110,
1897                 0x11118, 0x1117c,
1898                 0x11190, 0x11204,
1899                 0x19040, 0x1906c,
1900                 0x19078, 0x19080,
1901                 0x1908c, 0x19124,
1902                 0x19150, 0x191b0,
1903                 0x191d0, 0x191e8,
1904                 0x19238, 0x19290,
1905                 0x193f8, 0x19474,
1906                 0x19490, 0x194cc,
1907                 0x194f0, 0x194f8,
1908                 0x19c00, 0x19c60,
1909                 0x19c94, 0x19e10,
1910                 0x19e50, 0x19f34,
1911                 0x19f40, 0x19f50,
1912                 0x19f90, 0x19fe4,
1913                 0x1a000, 0x1a06c,
1914                 0x1a0b0, 0x1a120,
1915                 0x1a128, 0x1a138,
1916                 0x1a190, 0x1a1c4,
1917                 0x1a1fc, 0x1a1fc,
1918                 0x1e008, 0x1e00c,
1919                 0x1e040, 0x1e04c,
1920                 0x1e284, 0x1e290,
1921                 0x1e2c0, 0x1e2c0,
1922                 0x1e2e0, 0x1e2e0,
1923                 0x1e300, 0x1e384,
1924                 0x1e3c0, 0x1e3c8,
1925                 0x1e408, 0x1e40c,
1926                 0x1e440, 0x1e44c,
1927                 0x1e684, 0x1e690,
1928                 0x1e6c0, 0x1e6c0,
1929                 0x1e6e0, 0x1e6e0,
1930                 0x1e700, 0x1e784,
1931                 0x1e7c0, 0x1e7c8,
1932                 0x1e808, 0x1e80c,
1933                 0x1e840, 0x1e84c,
1934                 0x1ea84, 0x1ea90,
1935                 0x1eac0, 0x1eac0,
1936                 0x1eae0, 0x1eae0,
1937                 0x1eb00, 0x1eb84,
1938                 0x1ebc0, 0x1ebc8,
1939                 0x1ec08, 0x1ec0c,
1940                 0x1ec40, 0x1ec4c,
1941                 0x1ee84, 0x1ee90,
1942                 0x1eec0, 0x1eec0,
1943                 0x1eee0, 0x1eee0,
1944                 0x1ef00, 0x1ef84,
1945                 0x1efc0, 0x1efc8,
1946                 0x1f008, 0x1f00c,
1947                 0x1f040, 0x1f04c,
1948                 0x1f284, 0x1f290,
1949                 0x1f2c0, 0x1f2c0,
1950                 0x1f2e0, 0x1f2e0,
1951                 0x1f300, 0x1f384,
1952                 0x1f3c0, 0x1f3c8,
1953                 0x1f408, 0x1f40c,
1954                 0x1f440, 0x1f44c,
1955                 0x1f684, 0x1f690,
1956                 0x1f6c0, 0x1f6c0,
1957                 0x1f6e0, 0x1f6e0,
1958                 0x1f700, 0x1f784,
1959                 0x1f7c0, 0x1f7c8,
1960                 0x1f808, 0x1f80c,
1961                 0x1f840, 0x1f84c,
1962                 0x1fa84, 0x1fa90,
1963                 0x1fac0, 0x1fac0,
1964                 0x1fae0, 0x1fae0,
1965                 0x1fb00, 0x1fb84,
1966                 0x1fbc0, 0x1fbc8,
1967                 0x1fc08, 0x1fc0c,
1968                 0x1fc40, 0x1fc4c,
1969                 0x1fe84, 0x1fe90,
1970                 0x1fec0, 0x1fec0,
1971                 0x1fee0, 0x1fee0,
1972                 0x1ff00, 0x1ff84,
1973                 0x1ffc0, 0x1ffc8,
1974                 0x30000, 0x30030,
1975                 0x30100, 0x30144,
1976                 0x30190, 0x301d0,
1977                 0x30200, 0x30318,
1978                 0x30400, 0x3052c,
1979                 0x30540, 0x3061c,
1980                 0x30800, 0x30834,
1981                 0x308c0, 0x30908,
1982                 0x30910, 0x309ac,
1983                 0x30a00, 0x30a04,
1984                 0x30a0c, 0x30a2c,
1985                 0x30a44, 0x30a50,
1986                 0x30a74, 0x30c24,
1987                 0x30d08, 0x30d14,
1988                 0x30d1c, 0x30d20,
1989                 0x30d3c, 0x30d50,
1990                 0x31200, 0x3120c,
1991                 0x31220, 0x31220,
1992                 0x31240, 0x31240,
1993                 0x31600, 0x31600,
1994                 0x31608, 0x3160c,
1995                 0x31a00, 0x31a1c,
1996                 0x31e04, 0x31e20,
1997                 0x31e38, 0x31e3c,
1998                 0x31e80, 0x31e80,
1999                 0x31e88, 0x31ea8,
2000                 0x31eb0, 0x31eb4,
2001                 0x31ec8, 0x31ed4,
2002                 0x31fb8, 0x32004,
2003                 0x32208, 0x3223c,
2004                 0x32600, 0x32630,
2005                 0x32a00, 0x32abc,
2006                 0x32b00, 0x32b70,
2007                 0x33000, 0x33048,
2008                 0x33060, 0x3309c,
2009                 0x330f0, 0x33148,
2010                 0x33160, 0x3319c,
2011                 0x331f0, 0x332e4,
2012                 0x332f8, 0x333e4,
2013                 0x333f8, 0x33448,
2014                 0x33460, 0x3349c,
2015                 0x334f0, 0x33548,
2016                 0x33560, 0x3359c,
2017                 0x335f0, 0x336e4,
2018                 0x336f8, 0x337e4,
2019                 0x337f8, 0x337fc,
2020                 0x33814, 0x33814,
2021                 0x3382c, 0x3382c,
2022                 0x33880, 0x3388c,
2023                 0x338e8, 0x338ec,
2024                 0x33900, 0x33948,
2025                 0x33960, 0x3399c,
2026                 0x339f0, 0x33ae4,
2027                 0x33af8, 0x33b10,
2028                 0x33b28, 0x33b28,
2029                 0x33b3c, 0x33b50,
2030                 0x33bf0, 0x33c10,
2031                 0x33c28, 0x33c28,
2032                 0x33c3c, 0x33c50,
2033                 0x33cf0, 0x33cfc,
2034                 0x34000, 0x34030,
2035                 0x34100, 0x34144,
2036                 0x34190, 0x341d0,
2037                 0x34200, 0x34318,
2038                 0x34400, 0x3452c,
2039                 0x34540, 0x3461c,
2040                 0x34800, 0x34834,
2041                 0x348c0, 0x34908,
2042                 0x34910, 0x349ac,
2043                 0x34a00, 0x34a04,
2044                 0x34a0c, 0x34a2c,
2045                 0x34a44, 0x34a50,
2046                 0x34a74, 0x34c24,
2047                 0x34d08, 0x34d14,
2048                 0x34d1c, 0x34d20,
2049                 0x34d3c, 0x34d50,
2050                 0x35200, 0x3520c,
2051                 0x35220, 0x35220,
2052                 0x35240, 0x35240,
2053                 0x35600, 0x35600,
2054                 0x35608, 0x3560c,
2055                 0x35a00, 0x35a1c,
2056                 0x35e04, 0x35e20,
2057                 0x35e38, 0x35e3c,
2058                 0x35e80, 0x35e80,
2059                 0x35e88, 0x35ea8,
2060                 0x35eb0, 0x35eb4,
2061                 0x35ec8, 0x35ed4,
2062                 0x35fb8, 0x36004,
2063                 0x36208, 0x3623c,
2064                 0x36600, 0x36630,
2065                 0x36a00, 0x36abc,
2066                 0x36b00, 0x36b70,
2067                 0x37000, 0x37048,
2068                 0x37060, 0x3709c,
2069                 0x370f0, 0x37148,
2070                 0x37160, 0x3719c,
2071                 0x371f0, 0x372e4,
2072                 0x372f8, 0x373e4,
2073                 0x373f8, 0x37448,
2074                 0x37460, 0x3749c,
2075                 0x374f0, 0x37548,
2076                 0x37560, 0x3759c,
2077                 0x375f0, 0x376e4,
2078                 0x376f8, 0x377e4,
2079                 0x377f8, 0x377fc,
2080                 0x37814, 0x37814,
2081                 0x3782c, 0x3782c,
2082                 0x37880, 0x3788c,
2083                 0x378e8, 0x378ec,
2084                 0x37900, 0x37948,
2085                 0x37960, 0x3799c,
2086                 0x379f0, 0x37ae4,
2087                 0x37af8, 0x37b10,
2088                 0x37b28, 0x37b28,
2089                 0x37b3c, 0x37b50,
2090                 0x37bf0, 0x37c10,
2091                 0x37c28, 0x37c28,
2092                 0x37c3c, 0x37c50,
2093                 0x37cf0, 0x37cfc,
2094                 0x38000, 0x38030,
2095                 0x38100, 0x38144,
2096                 0x38190, 0x381d0,
2097                 0x38200, 0x38318,
2098                 0x38400, 0x3852c,
2099                 0x38540, 0x3861c,
2100                 0x38800, 0x38834,
2101                 0x388c0, 0x38908,
2102                 0x38910, 0x389ac,
2103                 0x38a00, 0x38a04,
2104                 0x38a0c, 0x38a2c,
2105                 0x38a44, 0x38a50,
2106                 0x38a74, 0x38c24,
2107                 0x38d08, 0x38d14,
2108                 0x38d1c, 0x38d20,
2109                 0x38d3c, 0x38d50,
2110                 0x39200, 0x3920c,
2111                 0x39220, 0x39220,
2112                 0x39240, 0x39240,
2113                 0x39600, 0x39600,
2114                 0x39608, 0x3960c,
2115                 0x39a00, 0x39a1c,
2116                 0x39e04, 0x39e20,
2117                 0x39e38, 0x39e3c,
2118                 0x39e80, 0x39e80,
2119                 0x39e88, 0x39ea8,
2120                 0x39eb0, 0x39eb4,
2121                 0x39ec8, 0x39ed4,
2122                 0x39fb8, 0x3a004,
2123                 0x3a208, 0x3a23c,
2124                 0x3a600, 0x3a630,
2125                 0x3aa00, 0x3aabc,
2126                 0x3ab00, 0x3ab70,
2127                 0x3b000, 0x3b048,
2128                 0x3b060, 0x3b09c,
2129                 0x3b0f0, 0x3b148,
2130                 0x3b160, 0x3b19c,
2131                 0x3b1f0, 0x3b2e4,
2132                 0x3b2f8, 0x3b3e4,
2133                 0x3b3f8, 0x3b448,
2134                 0x3b460, 0x3b49c,
2135                 0x3b4f0, 0x3b548,
2136                 0x3b560, 0x3b59c,
2137                 0x3b5f0, 0x3b6e4,
2138                 0x3b6f8, 0x3b7e4,
2139                 0x3b7f8, 0x3b7fc,
2140                 0x3b814, 0x3b814,
2141                 0x3b82c, 0x3b82c,
2142                 0x3b880, 0x3b88c,
2143                 0x3b8e8, 0x3b8ec,
2144                 0x3b900, 0x3b948,
2145                 0x3b960, 0x3b99c,
2146                 0x3b9f0, 0x3bae4,
2147                 0x3baf8, 0x3bb10,
2148                 0x3bb28, 0x3bb28,
2149                 0x3bb3c, 0x3bb50,
2150                 0x3bbf0, 0x3bc10,
2151                 0x3bc28, 0x3bc28,
2152                 0x3bc3c, 0x3bc50,
2153                 0x3bcf0, 0x3bcfc,
2154                 0x3c000, 0x3c030,
2155                 0x3c100, 0x3c144,
2156                 0x3c190, 0x3c1d0,
2157                 0x3c200, 0x3c318,
2158                 0x3c400, 0x3c52c,
2159                 0x3c540, 0x3c61c,
2160                 0x3c800, 0x3c834,
2161                 0x3c8c0, 0x3c908,
2162                 0x3c910, 0x3c9ac,
2163                 0x3ca00, 0x3ca04,
2164                 0x3ca0c, 0x3ca2c,
2165                 0x3ca44, 0x3ca50,
2166                 0x3ca74, 0x3cc24,
2167                 0x3cd08, 0x3cd14,
2168                 0x3cd1c, 0x3cd20,
2169                 0x3cd3c, 0x3cd50,
2170                 0x3d200, 0x3d20c,
2171                 0x3d220, 0x3d220,
2172                 0x3d240, 0x3d240,
2173                 0x3d600, 0x3d600,
2174                 0x3d608, 0x3d60c,
2175                 0x3da00, 0x3da1c,
2176                 0x3de04, 0x3de20,
2177                 0x3de38, 0x3de3c,
2178                 0x3de80, 0x3de80,
2179                 0x3de88, 0x3dea8,
2180                 0x3deb0, 0x3deb4,
2181                 0x3dec8, 0x3ded4,
2182                 0x3dfb8, 0x3e004,
2183                 0x3e208, 0x3e23c,
2184                 0x3e600, 0x3e630,
2185                 0x3ea00, 0x3eabc,
2186                 0x3eb00, 0x3eb70,
2187                 0x3f000, 0x3f048,
2188                 0x3f060, 0x3f09c,
2189                 0x3f0f0, 0x3f148,
2190                 0x3f160, 0x3f19c,
2191                 0x3f1f0, 0x3f2e4,
2192                 0x3f2f8, 0x3f3e4,
2193                 0x3f3f8, 0x3f448,
2194                 0x3f460, 0x3f49c,
2195                 0x3f4f0, 0x3f548,
2196                 0x3f560, 0x3f59c,
2197                 0x3f5f0, 0x3f6e4,
2198                 0x3f6f8, 0x3f7e4,
2199                 0x3f7f8, 0x3f7fc,
2200                 0x3f814, 0x3f814,
2201                 0x3f82c, 0x3f82c,
2202                 0x3f880, 0x3f88c,
2203                 0x3f8e8, 0x3f8ec,
2204                 0x3f900, 0x3f948,
2205                 0x3f960, 0x3f99c,
2206                 0x3f9f0, 0x3fae4,
2207                 0x3faf8, 0x3fb10,
2208                 0x3fb28, 0x3fb28,
2209                 0x3fb3c, 0x3fb50,
2210                 0x3fbf0, 0x3fc10,
2211                 0x3fc28, 0x3fc28,
2212                 0x3fc3c, 0x3fc50,
2213                 0x3fcf0, 0x3fcfc,
2214                 0x40000, 0x4000c,
2215                 0x40040, 0x40068,
2216                 0x40080, 0x40144,
2217                 0x40180, 0x4018c,
2218                 0x40200, 0x40298,
2219                 0x402ac, 0x4033c,
2220                 0x403f8, 0x403fc,
2221                 0x41304, 0x413c4,
2222                 0x41400, 0x4141c,
2223                 0x41480, 0x414d0,
2224                 0x44000, 0x44078,
2225                 0x440c0, 0x44278,
2226                 0x442c0, 0x44478,
2227                 0x444c0, 0x44678,
2228                 0x446c0, 0x44878,
2229                 0x448c0, 0x449fc,
2230                 0x45000, 0x45068,
2231                 0x45080, 0x45084,
2232                 0x450a0, 0x450b0,
2233                 0x45200, 0x45268,
2234                 0x45280, 0x45284,
2235                 0x452a0, 0x452b0,
2236                 0x460c0, 0x460e4,
2237                 0x47000, 0x4708c,
2238                 0x47200, 0x47250,
2239                 0x47400, 0x47420,
2240                 0x47600, 0x47618,
2241                 0x47800, 0x47814,
2242                 0x48000, 0x4800c,
2243                 0x48040, 0x48068,
2244                 0x48080, 0x48144,
2245                 0x48180, 0x4818c,
2246                 0x48200, 0x48298,
2247                 0x482ac, 0x4833c,
2248                 0x483f8, 0x483fc,
2249                 0x49304, 0x493c4,
2250                 0x49400, 0x4941c,
2251                 0x49480, 0x494d0,
2252                 0x4c000, 0x4c078,
2253                 0x4c0c0, 0x4c278,
2254                 0x4c2c0, 0x4c478,
2255                 0x4c4c0, 0x4c678,
2256                 0x4c6c0, 0x4c878,
2257                 0x4c8c0, 0x4c9fc,
2258                 0x4d000, 0x4d068,
2259                 0x4d080, 0x4d084,
2260                 0x4d0a0, 0x4d0b0,
2261                 0x4d200, 0x4d268,
2262                 0x4d280, 0x4d284,
2263                 0x4d2a0, 0x4d2b0,
2264                 0x4e0c0, 0x4e0e4,
2265                 0x4f000, 0x4f08c,
2266                 0x4f200, 0x4f250,
2267                 0x4f400, 0x4f420,
2268                 0x4f600, 0x4f618,
2269                 0x4f800, 0x4f814,
2270                 0x50000, 0x500cc,
2271                 0x50400, 0x50400,
2272                 0x50800, 0x508cc,
2273                 0x50c00, 0x50c00,
2274                 0x51000, 0x5101c,
2275                 0x51300, 0x51308,
2276         };
2277
2278         int i;
2279         struct adapter *ap = netdev2adap(dev);
2280         static const unsigned int *reg_ranges;
2281         int arr_size = 0, buf_size = 0;
2282
2283         if (is_t4(ap->params.chip)) {
2284                 reg_ranges = &t4_reg_ranges[0];
2285                 arr_size = ARRAY_SIZE(t4_reg_ranges);
2286                 buf_size = T4_REGMAP_SIZE;
2287         } else {
2288                 reg_ranges = &t5_reg_ranges[0];
2289                 arr_size = ARRAY_SIZE(t5_reg_ranges);
2290                 buf_size = T5_REGMAP_SIZE;
2291         }
2292
2293         regs->version = mk_adap_vers(ap);
2294
2295         memset(buf, 0, buf_size);
2296         for (i = 0; i < arr_size; i += 2)
2297                 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2298 }
2299
2300 static int restart_autoneg(struct net_device *dev)
2301 {
2302         struct port_info *p = netdev_priv(dev);
2303
2304         if (!netif_running(dev))
2305                 return -EAGAIN;
2306         if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2307                 return -EINVAL;
2308         t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2309         return 0;
2310 }
2311
2312 static int identify_port(struct net_device *dev,
2313                          enum ethtool_phys_id_state state)
2314 {
2315         unsigned int val;
2316         struct adapter *adap = netdev2adap(dev);
2317
2318         if (state == ETHTOOL_ID_ACTIVE)
2319                 val = 0xffff;
2320         else if (state == ETHTOOL_ID_INACTIVE)
2321                 val = 0;
2322         else
2323                 return -EINVAL;
2324
2325         return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2326 }
2327
2328 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2329 {
2330         unsigned int v = 0;
2331
2332         if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2333             type == FW_PORT_TYPE_BT_XAUI) {
2334                 v |= SUPPORTED_TP;
2335                 if (caps & FW_PORT_CAP_SPEED_100M)
2336                         v |= SUPPORTED_100baseT_Full;
2337                 if (caps & FW_PORT_CAP_SPEED_1G)
2338                         v |= SUPPORTED_1000baseT_Full;
2339                 if (caps & FW_PORT_CAP_SPEED_10G)
2340                         v |= SUPPORTED_10000baseT_Full;
2341         } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2342                 v |= SUPPORTED_Backplane;
2343                 if (caps & FW_PORT_CAP_SPEED_1G)
2344                         v |= SUPPORTED_1000baseKX_Full;
2345                 if (caps & FW_PORT_CAP_SPEED_10G)
2346                         v |= SUPPORTED_10000baseKX4_Full;
2347         } else if (type == FW_PORT_TYPE_KR)
2348                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2349         else if (type == FW_PORT_TYPE_BP_AP)
2350                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2351                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2352         else if (type == FW_PORT_TYPE_BP4_AP)
2353                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2354                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2355                      SUPPORTED_10000baseKX4_Full;
2356         else if (type == FW_PORT_TYPE_FIBER_XFI ||
2357                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2358                 v |= SUPPORTED_FIBRE;
2359         else if (type == FW_PORT_TYPE_BP40_BA)
2360                 v |= SUPPORTED_40000baseSR4_Full;
2361
2362         if (caps & FW_PORT_CAP_ANEG)
2363                 v |= SUPPORTED_Autoneg;
2364         return v;
2365 }
2366
2367 static unsigned int to_fw_linkcaps(unsigned int caps)
2368 {
2369         unsigned int v = 0;
2370
2371         if (caps & ADVERTISED_100baseT_Full)
2372                 v |= FW_PORT_CAP_SPEED_100M;
2373         if (caps & ADVERTISED_1000baseT_Full)
2374                 v |= FW_PORT_CAP_SPEED_1G;
2375         if (caps & ADVERTISED_10000baseT_Full)
2376                 v |= FW_PORT_CAP_SPEED_10G;
2377         if (caps & ADVERTISED_40000baseSR4_Full)
2378                 v |= FW_PORT_CAP_SPEED_40G;
2379         return v;
2380 }
2381
2382 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2383 {
2384         const struct port_info *p = netdev_priv(dev);
2385
2386         if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2387             p->port_type == FW_PORT_TYPE_BT_XFI ||
2388             p->port_type == FW_PORT_TYPE_BT_XAUI)
2389                 cmd->port = PORT_TP;
2390         else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2391                  p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2392                 cmd->port = PORT_FIBRE;
2393         else if (p->port_type == FW_PORT_TYPE_SFP ||
2394                  p->port_type == FW_PORT_TYPE_QSFP_10G ||
2395                  p->port_type == FW_PORT_TYPE_QSFP) {
2396                 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2397                     p->mod_type == FW_PORT_MOD_TYPE_SR ||
2398                     p->mod_type == FW_PORT_MOD_TYPE_ER ||
2399                     p->mod_type == FW_PORT_MOD_TYPE_LRM)
2400                         cmd->port = PORT_FIBRE;
2401                 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2402                          p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2403                         cmd->port = PORT_DA;
2404                 else
2405                         cmd->port = PORT_OTHER;
2406         } else
2407                 cmd->port = PORT_OTHER;
2408
2409         if (p->mdio_addr >= 0) {
2410                 cmd->phy_address = p->mdio_addr;
2411                 cmd->transceiver = XCVR_EXTERNAL;
2412                 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2413                         MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2414         } else {
2415                 cmd->phy_address = 0;  /* not really, but no better option */
2416                 cmd->transceiver = XCVR_INTERNAL;
2417                 cmd->mdio_support = 0;
2418         }
2419
2420         cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2421         cmd->advertising = from_fw_linkcaps(p->port_type,
2422                                             p->link_cfg.advertising);
2423         ethtool_cmd_speed_set(cmd,
2424                               netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2425         cmd->duplex = DUPLEX_FULL;
2426         cmd->autoneg = p->link_cfg.autoneg;
2427         cmd->maxtxpkt = 0;
2428         cmd->maxrxpkt = 0;
2429         return 0;
2430 }
2431
2432 static unsigned int speed_to_caps(int speed)
2433 {
2434         if (speed == 100)
2435                 return FW_PORT_CAP_SPEED_100M;
2436         if (speed == 1000)
2437                 return FW_PORT_CAP_SPEED_1G;
2438         if (speed == 10000)
2439                 return FW_PORT_CAP_SPEED_10G;
2440         if (speed == 40000)
2441                 return FW_PORT_CAP_SPEED_40G;
2442         return 0;
2443 }
2444
2445 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2446 {
2447         unsigned int cap;
2448         struct port_info *p = netdev_priv(dev);
2449         struct link_config *lc = &p->link_cfg;
2450         u32 speed = ethtool_cmd_speed(cmd);
2451
2452         if (cmd->duplex != DUPLEX_FULL)     /* only full-duplex supported */
2453                 return -EINVAL;
2454
2455         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2456                 /*
2457                  * PHY offers a single speed.  See if that's what's
2458                  * being requested.
2459                  */
2460                 if (cmd->autoneg == AUTONEG_DISABLE &&
2461                     (lc->supported & speed_to_caps(speed)))
2462                         return 0;
2463                 return -EINVAL;
2464         }
2465
2466         if (cmd->autoneg == AUTONEG_DISABLE) {
2467                 cap = speed_to_caps(speed);
2468
2469                 if (!(lc->supported & cap) ||
2470                     (speed == 1000) ||
2471                     (speed == 10000) ||
2472                     (speed == 40000))
2473                         return -EINVAL;
2474                 lc->requested_speed = cap;
2475                 lc->advertising = 0;
2476         } else {
2477                 cap = to_fw_linkcaps(cmd->advertising);
2478                 if (!(lc->supported & cap))
2479                         return -EINVAL;
2480                 lc->requested_speed = 0;
2481                 lc->advertising = cap | FW_PORT_CAP_ANEG;
2482         }
2483         lc->autoneg = cmd->autoneg;
2484
2485         if (netif_running(dev))
2486                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2487                                      lc);
2488         return 0;
2489 }
2490
2491 static void get_pauseparam(struct net_device *dev,
2492                            struct ethtool_pauseparam *epause)
2493 {
2494         struct port_info *p = netdev_priv(dev);
2495
2496         epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2497         epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2498         epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2499 }
2500
2501 static int set_pauseparam(struct net_device *dev,
2502                           struct ethtool_pauseparam *epause)
2503 {
2504         struct port_info *p = netdev_priv(dev);
2505         struct link_config *lc = &p->link_cfg;
2506
2507         if (epause->autoneg == AUTONEG_DISABLE)
2508                 lc->requested_fc = 0;
2509         else if (lc->supported & FW_PORT_CAP_ANEG)
2510                 lc->requested_fc = PAUSE_AUTONEG;
2511         else
2512                 return -EINVAL;
2513
2514         if (epause->rx_pause)
2515                 lc->requested_fc |= PAUSE_RX;
2516         if (epause->tx_pause)
2517                 lc->requested_fc |= PAUSE_TX;
2518         if (netif_running(dev))
2519                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2520                                      lc);
2521         return 0;
2522 }
2523
2524 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2525 {
2526         const struct port_info *pi = netdev_priv(dev);
2527         const struct sge *s = &pi->adapter->sge;
2528
2529         e->rx_max_pending = MAX_RX_BUFFERS;
2530         e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2531         e->rx_jumbo_max_pending = 0;
2532         e->tx_max_pending = MAX_TXQ_ENTRIES;
2533
2534         e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2535         e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2536         e->rx_jumbo_pending = 0;
2537         e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2538 }
2539
2540 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2541 {
2542         int i;
2543         const struct port_info *pi = netdev_priv(dev);
2544         struct adapter *adapter = pi->adapter;
2545         struct sge *s = &adapter->sge;
2546
2547         if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2548             e->tx_pending > MAX_TXQ_ENTRIES ||
2549             e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2550             e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2551             e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2552                 return -EINVAL;
2553
2554         if (adapter->flags & FULL_INIT_DONE)
2555                 return -EBUSY;
2556
2557         for (i = 0; i < pi->nqsets; ++i) {
2558                 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2559                 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2560                 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2561         }
2562         return 0;
2563 }
2564
2565 static int closest_timer(const struct sge *s, int time)
2566 {
2567         int i, delta, match = 0, min_delta = INT_MAX;
2568
2569         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2570                 delta = time - s->timer_val[i];
2571                 if (delta < 0)
2572                         delta = -delta;
2573                 if (delta < min_delta) {
2574                         min_delta = delta;
2575                         match = i;
2576                 }
2577         }
2578         return match;
2579 }
2580
2581 static int closest_thres(const struct sge *s, int thres)
2582 {
2583         int i, delta, match = 0, min_delta = INT_MAX;
2584
2585         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2586                 delta = thres - s->counter_val[i];
2587                 if (delta < 0)
2588                         delta = -delta;
2589                 if (delta < min_delta) {
2590                         min_delta = delta;
2591                         match = i;
2592                 }
2593         }
2594         return match;
2595 }
2596
2597 /*
2598  * Return a queue's interrupt hold-off time in us.  0 means no timer.
2599  */
2600 static unsigned int qtimer_val(const struct adapter *adap,
2601                                const struct sge_rspq *q)
2602 {
2603         unsigned int idx = q->intr_params >> 1;
2604
2605         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2606 }
2607
2608 /**
2609  *      set_rspq_intr_params - set a queue's interrupt holdoff parameters
2610  *      @q: the Rx queue
2611  *      @us: the hold-off time in us, or 0 to disable timer
2612  *      @cnt: the hold-off packet count, or 0 to disable counter
2613  *
2614  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
2615  *      one of the two needs to be enabled for the queue to generate interrupts.
2616  */
2617 static int set_rspq_intr_params(struct sge_rspq *q,
2618                                 unsigned int us, unsigned int cnt)
2619 {
2620         struct adapter *adap = q->adap;
2621
2622         if ((us | cnt) == 0)
2623                 cnt = 1;
2624
2625         if (cnt) {
2626                 int err;
2627                 u32 v, new_idx;
2628
2629                 new_idx = closest_thres(&adap->sge, cnt);
2630                 if (q->desc && q->pktcnt_idx != new_idx) {
2631                         /* the queue has already been created, update it */
2632                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
2633                             FW_PARAMS_PARAM_X_V(
2634                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2635                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
2636                         err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2637                                             &new_idx);
2638                         if (err)
2639                                 return err;
2640                 }
2641                 q->pktcnt_idx = new_idx;
2642         }
2643
2644         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2645         q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2646         return 0;
2647 }
2648
2649 /**
2650  * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2651  * @dev: the network device
2652  * @us: the hold-off time in us, or 0 to disable timer
2653  * @cnt: the hold-off packet count, or 0 to disable counter
2654  *
2655  * Set the RX interrupt hold-off parameters for a network device.
2656  */
2657 static int set_rx_intr_params(struct net_device *dev,
2658                               unsigned int us, unsigned int cnt)
2659 {
2660         int i, err;
2661         struct port_info *pi = netdev_priv(dev);
2662         struct adapter *adap = pi->adapter;
2663         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2664
2665         for (i = 0; i < pi->nqsets; i++, q++) {
2666                 err = set_rspq_intr_params(&q->rspq, us, cnt);
2667                 if (err)
2668                         return err;
2669         }
2670         return 0;
2671 }
2672
2673 static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
2674 {
2675         int i;
2676         struct port_info *pi = netdev_priv(dev);
2677         struct adapter *adap = pi->adapter;
2678         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2679
2680         for (i = 0; i < pi->nqsets; i++, q++)
2681                 q->rspq.adaptive_rx = adaptive_rx;
2682
2683         return 0;
2684 }
2685
2686 static int get_adaptive_rx_setting(struct net_device *dev)
2687 {
2688         struct port_info *pi = netdev_priv(dev);
2689         struct adapter *adap = pi->adapter;
2690         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2691
2692         return q->rspq.adaptive_rx;
2693 }
2694
2695 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2696 {
2697         set_adaptive_rx_setting(dev, c->use_adaptive_rx_coalesce);
2698         return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2699                                   c->rx_max_coalesced_frames);
2700 }
2701
2702 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2703 {
2704         const struct port_info *pi = netdev_priv(dev);
2705         const struct adapter *adap = pi->adapter;
2706         const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2707
2708         c->rx_coalesce_usecs = qtimer_val(adap, rq);
2709         c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2710                 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2711         c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
2712         return 0;
2713 }
2714
2715 /**
2716  *      eeprom_ptov - translate a physical EEPROM address to virtual
2717  *      @phys_addr: the physical EEPROM address
2718  *      @fn: the PCI function number
2719  *      @sz: size of function-specific area
2720  *
2721  *      Translate a physical EEPROM address to virtual.  The first 1K is
2722  *      accessed through virtual addresses starting at 31K, the rest is
2723  *      accessed through virtual addresses starting at 0.
2724  *
2725  *      The mapping is as follows:
2726  *      [0..1K) -> [31K..32K)
2727  *      [1K..1K+A) -> [31K-A..31K)
2728  *      [1K+A..ES) -> [0..ES-A-1K)
2729  *
2730  *      where A = @fn * @sz, and ES = EEPROM size.
2731  */
2732 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2733 {
2734         fn *= sz;
2735         if (phys_addr < 1024)
2736                 return phys_addr + (31 << 10);
2737         if (phys_addr < 1024 + fn)
2738                 return 31744 - fn + phys_addr - 1024;
2739         if (phys_addr < EEPROMSIZE)
2740                 return phys_addr - 1024 - fn;
2741         return -EINVAL;
2742 }
2743
2744 /*
2745  * The next two routines implement eeprom read/write from physical addresses.
2746  */
2747 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2748 {
2749         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2750
2751         if (vaddr >= 0)
2752                 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2753         return vaddr < 0 ? vaddr : 0;
2754 }
2755
2756 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2757 {
2758         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2759
2760         if (vaddr >= 0)
2761                 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2762         return vaddr < 0 ? vaddr : 0;
2763 }
2764
2765 #define EEPROM_MAGIC 0x38E2F10C
2766
2767 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2768                       u8 *data)
2769 {
2770         int i, err = 0;
2771         struct adapter *adapter = netdev2adap(dev);
2772
2773         u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2774         if (!buf)
2775                 return -ENOMEM;
2776
2777         e->magic = EEPROM_MAGIC;
2778         for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2779                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2780
2781         if (!err)
2782                 memcpy(data, buf + e->offset, e->len);
2783         kfree(buf);
2784         return err;
2785 }
2786
2787 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2788                       u8 *data)
2789 {
2790         u8 *buf;
2791         int err = 0;
2792         u32 aligned_offset, aligned_len, *p;
2793         struct adapter *adapter = netdev2adap(dev);
2794
2795         if (eeprom->magic != EEPROM_MAGIC)
2796                 return -EINVAL;
2797
2798         aligned_offset = eeprom->offset & ~3;
2799         aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2800
2801         if (adapter->fn > 0) {
2802                 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2803
2804                 if (aligned_offset < start ||
2805                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
2806                         return -EPERM;
2807         }
2808
2809         if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2810                 /*
2811                  * RMW possibly needed for first or last words.
2812                  */
2813                 buf = kmalloc(aligned_len, GFP_KERNEL);
2814                 if (!buf)
2815                         return -ENOMEM;
2816                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2817                 if (!err && aligned_len > 4)
2818                         err = eeprom_rd_phys(adapter,
2819                                              aligned_offset + aligned_len - 4,
2820                                              (u32 *)&buf[aligned_len - 4]);
2821                 if (err)
2822                         goto out;
2823                 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2824         } else
2825                 buf = data;
2826
2827         err = t4_seeprom_wp(adapter, false);
2828         if (err)
2829                 goto out;
2830
2831         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2832                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2833                 aligned_offset += 4;
2834         }
2835
2836         if (!err)
2837                 err = t4_seeprom_wp(adapter, true);
2838 out:
2839         if (buf != data)
2840                 kfree(buf);
2841         return err;
2842 }
2843
2844 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2845 {
2846         int ret;
2847         const struct firmware *fw;
2848         struct adapter *adap = netdev2adap(netdev);
2849         unsigned int mbox = PCIE_FW_MASTER_M + 1;
2850
2851         ef->data[sizeof(ef->data) - 1] = '\0';
2852         ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2853         if (ret < 0)
2854                 return ret;
2855
2856         /* If the adapter has been fully initialized then we'll go ahead and
2857          * try to get the firmware's cooperation in upgrading to the new
2858          * firmware image otherwise we'll try to do the entire job from the
2859          * host ... and we always "force" the operation in this path.
2860          */
2861         if (adap->flags & FULL_INIT_DONE)
2862                 mbox = adap->mbox;
2863
2864         ret = t4_fw_upgrade(adap, mbox, fw->data, fw->size, 1);
2865         release_firmware(fw);
2866         if (!ret)
2867                 dev_info(adap->pdev_dev, "loaded firmware %s,"
2868                          " reload cxgb4 driver\n", ef->data);
2869         return ret;
2870 }
2871
2872 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2873 #define BCAST_CRC 0xa0ccc1a6
2874
2875 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2876 {
2877         wol->supported = WAKE_BCAST | WAKE_MAGIC;
2878         wol->wolopts = netdev2adap(dev)->wol;
2879         memset(&wol->sopass, 0, sizeof(wol->sopass));
2880 }
2881
2882 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2883 {
2884         int err = 0;
2885         struct port_info *pi = netdev_priv(dev);
2886
2887         if (wol->wolopts & ~WOL_SUPPORTED)
2888                 return -EINVAL;
2889         t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2890                             (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2891         if (wol->wolopts & WAKE_BCAST) {
2892                 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2893                                         ~0ULL, 0, false);
2894                 if (!err)
2895                         err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2896                                                 ~6ULL, ~0ULL, BCAST_CRC, true);
2897         } else
2898                 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2899         return err;
2900 }
2901
2902 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2903 {
2904         const struct port_info *pi = netdev_priv(dev);
2905         netdev_features_t changed = dev->features ^ features;
2906         int err;
2907
2908         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2909                 return 0;
2910
2911         err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2912                             -1, -1, -1,
2913                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2914         if (unlikely(err))
2915                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
2916         return err;
2917 }
2918
2919 static u32 get_rss_table_size(struct net_device *dev)
2920 {
2921         const struct port_info *pi = netdev_priv(dev);
2922
2923         return pi->rss_size;
2924 }
2925
2926 static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
2927 {
2928         const struct port_info *pi = netdev_priv(dev);
2929         unsigned int n = pi->rss_size;
2930
2931         while (n--)
2932                 p[n] = pi->rss[n];
2933         return 0;
2934 }
2935
2936 static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
2937 {
2938         unsigned int i;
2939         struct port_info *pi = netdev_priv(dev);
2940
2941         for (i = 0; i < pi->rss_size; i++)
2942                 pi->rss[i] = p[i];
2943         if (pi->adapter->flags & FULL_INIT_DONE)
2944                 return write_rss(pi, pi->rss);
2945         return 0;
2946 }
2947
2948 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2949                      u32 *rules)
2950 {
2951         const struct port_info *pi = netdev_priv(dev);
2952
2953         switch (info->cmd) {
2954         case ETHTOOL_GRXFH: {
2955                 unsigned int v = pi->rss_mode;
2956
2957                 info->data = 0;
2958                 switch (info->flow_type) {
2959                 case TCP_V4_FLOW:
2960                         if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F)
2961                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2962                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2963                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2964                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2965                         break;
2966                 case UDP_V4_FLOW:
2967                         if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) &&
2968                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
2969                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2970                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2971                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2972                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2973                         break;
2974                 case SCTP_V4_FLOW:
2975                 case AH_ESP_V4_FLOW:
2976                 case IPV4_FLOW:
2977                         if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2978                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2979                         break;
2980                 case TCP_V6_FLOW:
2981                         if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F)
2982                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2983                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2984                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
2985                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2986                         break;
2987                 case UDP_V6_FLOW:
2988                         if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) &&
2989                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
2990                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2991                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2992                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
2993                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2994                         break;
2995                 case SCTP_V6_FLOW:
2996                 case AH_ESP_V6_FLOW:
2997                 case IPV6_FLOW:
2998                         if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
2999                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3000                         break;
3001                 }
3002                 return 0;
3003         }
3004         case ETHTOOL_GRXRINGS:
3005                 info->data = pi->nqsets;
3006                 return 0;
3007         }
3008         return -EOPNOTSUPP;
3009 }
3010
3011 static const struct ethtool_ops cxgb_ethtool_ops = {
3012         .get_settings      = get_settings,
3013         .set_settings      = set_settings,
3014         .get_drvinfo       = get_drvinfo,
3015         .get_msglevel      = get_msglevel,
3016         .set_msglevel      = set_msglevel,
3017         .get_ringparam     = get_sge_param,
3018         .set_ringparam     = set_sge_param,
3019         .get_coalesce      = get_coalesce,
3020         .set_coalesce      = set_coalesce,
3021         .get_eeprom_len    = get_eeprom_len,
3022         .get_eeprom        = get_eeprom,
3023         .set_eeprom        = set_eeprom,
3024         .get_pauseparam    = get_pauseparam,
3025         .set_pauseparam    = set_pauseparam,
3026         .get_link          = ethtool_op_get_link,
3027         .get_strings       = get_strings,
3028         .set_phys_id       = identify_port,
3029         .nway_reset        = restart_autoneg,
3030         .get_sset_count    = get_sset_count,
3031         .get_ethtool_stats = get_stats,
3032         .get_regs_len      = get_regs_len,
3033         .get_regs          = get_regs,
3034         .get_wol           = get_wol,
3035         .set_wol           = set_wol,
3036         .get_rxnfc         = get_rxnfc,
3037         .get_rxfh_indir_size = get_rss_table_size,
3038         .get_rxfh          = get_rss_table,
3039         .set_rxfh          = set_rss_table,
3040         .flash_device      = set_flash,
3041 };
3042
3043 static int setup_debugfs(struct adapter *adap)
3044 {
3045         if (IS_ERR_OR_NULL(adap->debugfs_root))
3046                 return -1;
3047
3048 #ifdef CONFIG_DEBUG_FS
3049         t4_setup_debugfs(adap);
3050 #endif
3051         return 0;
3052 }
3053
3054 /*
3055  * upper-layer driver support
3056  */
3057
3058 /*
3059  * Allocate an active-open TID and set it to the supplied value.
3060  */
3061 int cxgb4_alloc_atid(struct tid_info *t, void *data)
3062 {
3063         int atid = -1;
3064
3065         spin_lock_bh(&t->atid_lock);
3066         if (t->afree) {
3067                 union aopen_entry *p = t->afree;
3068
3069                 atid = (p - t->atid_tab) + t->atid_base;
3070                 t->afree = p->next;
3071                 p->data = data;
3072                 t->atids_in_use++;
3073         }
3074         spin_unlock_bh(&t->atid_lock);
3075         return atid;
3076 }
3077 EXPORT_SYMBOL(cxgb4_alloc_atid);
3078
3079 /*
3080  * Release an active-open TID.
3081  */
3082 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3083 {
3084         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
3085
3086         spin_lock_bh(&t->atid_lock);
3087         p->next = t->afree;
3088         t->afree = p;
3089         t->atids_in_use--;
3090         spin_unlock_bh(&t->atid_lock);
3091 }
3092 EXPORT_SYMBOL(cxgb4_free_atid);
3093
3094 /*
3095  * Allocate a server TID and set it to the supplied value.
3096  */
3097 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3098 {
3099         int stid;
3100
3101         spin_lock_bh(&t->stid_lock);
3102         if (family == PF_INET) {
3103                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3104                 if (stid < t->nstids)
3105                         __set_bit(stid, t->stid_bmap);
3106                 else
3107                         stid = -1;
3108         } else {
3109                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3110                 if (stid < 0)
3111                         stid = -1;
3112         }
3113         if (stid >= 0) {
3114                 t->stid_tab[stid].data = data;
3115                 stid += t->stid_base;
3116                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3117                  * This is equivalent to 4 TIDs. With CLIP enabled it
3118                  * needs 2 TIDs.
3119                  */
3120                 if (family == PF_INET)
3121                         t->stids_in_use++;
3122                 else
3123                         t->stids_in_use += 4;
3124         }
3125         spin_unlock_bh(&t->stid_lock);
3126         return stid;
3127 }
3128 EXPORT_SYMBOL(cxgb4_alloc_stid);
3129
3130 /* Allocate a server filter TID and set it to the supplied value.
3131  */
3132 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3133 {
3134         int stid;
3135
3136         spin_lock_bh(&t->stid_lock);
3137         if (family == PF_INET) {
3138                 stid = find_next_zero_bit(t->stid_bmap,
3139                                 t->nstids + t->nsftids, t->nstids);
3140                 if (stid < (t->nstids + t->nsftids))
3141                         __set_bit(stid, t->stid_bmap);
3142                 else
3143                         stid = -1;
3144         } else {
3145                 stid = -1;
3146         }
3147         if (stid >= 0) {
3148                 t->stid_tab[stid].data = data;
3149                 stid -= t->nstids;
3150                 stid += t->sftid_base;
3151                 t->stids_in_use++;
3152         }
3153         spin_unlock_bh(&t->stid_lock);
3154         return stid;
3155 }
3156 EXPORT_SYMBOL(cxgb4_alloc_sftid);
3157
3158 /* Release a server TID.
3159  */
3160 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3161 {
3162         /* Is it a server filter TID? */
3163         if (t->nsftids && (stid >= t->sftid_base)) {
3164                 stid -= t->sftid_base;
3165                 stid += t->nstids;
3166         } else {
3167                 stid -= t->stid_base;
3168         }
3169
3170         spin_lock_bh(&t->stid_lock);
3171         if (family == PF_INET)
3172                 __clear_bit(stid, t->stid_bmap);
3173         else
3174                 bitmap_release_region(t->stid_bmap, stid, 2);
3175         t->stid_tab[stid].data = NULL;
3176         if (family == PF_INET)
3177                 t->stids_in_use--;
3178         else
3179                 t->stids_in_use -= 4;
3180         spin_unlock_bh(&t->stid_lock);
3181 }
3182 EXPORT_SYMBOL(cxgb4_free_stid);
3183
3184 /*
3185  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
3186  */
3187 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3188                            unsigned int tid)
3189 {
3190         struct cpl_tid_release *req;
3191
3192         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3193         req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3194         INIT_TP_WR(req, tid);
3195         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3196 }
3197
3198 /*
3199  * Queue a TID release request and if necessary schedule a work queue to
3200  * process it.
3201  */
3202 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3203                                     unsigned int tid)
3204 {
3205         void **p = &t->tid_tab[tid];
3206         struct adapter *adap = container_of(t, struct adapter, tids);
3207
3208         spin_lock_bh(&adap->tid_release_lock);
3209         *p = adap->tid_release_head;
3210         /* Low 2 bits encode the Tx channel number */
3211         adap->tid_release_head = (void **)((uintptr_t)p | chan);
3212         if (!adap->tid_release_task_busy) {
3213                 adap->tid_release_task_busy = true;
3214                 queue_work(adap->workq, &adap->tid_release_task);
3215         }
3216         spin_unlock_bh(&adap->tid_release_lock);
3217 }
3218
3219 /*
3220  * Process the list of pending TID release requests.
3221  */
3222 static void process_tid_release_list(struct work_struct *work)
3223 {
3224         struct sk_buff *skb;
3225         struct adapter *adap;
3226
3227         adap = container_of(work, struct adapter, tid_release_task);
3228
3229         spin_lock_bh(&adap->tid_release_lock);
3230         while (adap->tid_release_head) {
3231                 void **p = adap->tid_release_head;
3232                 unsigned int chan = (uintptr_t)p & 3;
3233                 p = (void *)p - chan;
3234
3235                 adap->tid_release_head = *p;
3236                 *p = NULL;
3237                 spin_unlock_bh(&adap->tid_release_lock);
3238
3239                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3240                                          GFP_KERNEL)))
3241                         schedule_timeout_uninterruptible(1);
3242
3243                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3244                 t4_ofld_send(adap, skb);
3245                 spin_lock_bh(&adap->tid_release_lock);
3246         }
3247         adap->tid_release_task_busy = false;
3248         spin_unlock_bh(&adap->tid_release_lock);
3249 }
3250
3251 /*
3252  * Release a TID and inform HW.  If we are unable to allocate the release
3253  * message we defer to a work queue.
3254  */
3255 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3256 {
3257         void *old;
3258         struct sk_buff *skb;
3259         struct adapter *adap = container_of(t, struct adapter, tids);
3260
3261         old = t->tid_tab[tid];
3262         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3263         if (likely(skb)) {
3264                 t->tid_tab[tid] = NULL;
3265                 mk_tid_release(skb, chan, tid);
3266                 t4_ofld_send(adap, skb);
3267         } else
3268                 cxgb4_queue_tid_release(t, chan, tid);
3269         if (old)
3270                 atomic_dec(&t->tids_in_use);
3271 }
3272 EXPORT_SYMBOL(cxgb4_remove_tid);
3273
3274 /*
3275  * Allocate and initialize the TID tables.  Returns 0 on success.
3276  */
3277 static int tid_init(struct tid_info *t)
3278 {
3279         size_t size;
3280         unsigned int stid_bmap_size;
3281         unsigned int natids = t->natids;
3282         struct adapter *adap = container_of(t, struct adapter, tids);
3283
3284         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
3285         size = t->ntids * sizeof(*t->tid_tab) +
3286                natids * sizeof(*t->atid_tab) +
3287                t->nstids * sizeof(*t->stid_tab) +
3288                t->nsftids * sizeof(*t->stid_tab) +
3289                stid_bmap_size * sizeof(long) +
3290                t->nftids * sizeof(*t->ftid_tab) +
3291                t->nsftids * sizeof(*t->ftid_tab);
3292
3293         t->tid_tab = t4_alloc_mem(size);
3294         if (!t->tid_tab)
3295                 return -ENOMEM;
3296
3297         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3298         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
3299         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
3300         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
3301         spin_lock_init(&t->stid_lock);
3302         spin_lock_init(&t->atid_lock);
3303
3304         t->stids_in_use = 0;
3305         t->afree = NULL;
3306         t->atids_in_use = 0;
3307         atomic_set(&t->tids_in_use, 0);
3308
3309         /* Setup the free list for atid_tab and clear the stid bitmap. */
3310         if (natids) {
3311                 while (--natids)
3312                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3313                 t->afree = t->atid_tab;
3314         }
3315         bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
3316         /* Reserve stid 0 for T4/T5 adapters */
3317         if (!t->stid_base &&
3318             (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3319                 __set_bit(0, t->stid_bmap);
3320
3321         return 0;
3322 }
3323
3324 int cxgb4_clip_get(const struct net_device *dev,
3325                    const struct in6_addr *lip)
3326 {
3327         struct adapter *adap;
3328         struct fw_clip_cmd c;
3329
3330         adap = netdev2adap(dev);
3331         memset(&c, 0, sizeof(c));
3332         c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3333                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3334         c.alloc_to_len16 = htonl(FW_CLIP_CMD_ALLOC_F | FW_LEN16(c));
3335         c.ip_hi = *(__be64 *)(lip->s6_addr);
3336         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3337         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3338 }
3339 EXPORT_SYMBOL(cxgb4_clip_get);
3340
3341 int cxgb4_clip_release(const struct net_device *dev,
3342                        const struct in6_addr *lip)
3343 {
3344         struct adapter *adap;
3345         struct fw_clip_cmd c;
3346
3347         adap = netdev2adap(dev);
3348         memset(&c, 0, sizeof(c));
3349         c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3350                         FW_CMD_REQUEST_F | FW_CMD_READ_F);
3351         c.alloc_to_len16 = htonl(FW_CLIP_CMD_FREE_F | FW_LEN16(c));
3352         c.ip_hi = *(__be64 *)(lip->s6_addr);
3353         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3354         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3355 }
3356 EXPORT_SYMBOL(cxgb4_clip_release);
3357
3358 /**
3359  *      cxgb4_create_server - create an IP server
3360  *      @dev: the device
3361  *      @stid: the server TID
3362  *      @sip: local IP address to bind server to
3363  *      @sport: the server's TCP port
3364  *      @queue: queue to direct messages from this server to
3365  *
3366  *      Create an IP server for the given port and address.
3367  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3368  */
3369 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
3370                         __be32 sip, __be16 sport, __be16 vlan,
3371                         unsigned int queue)
3372 {
3373         unsigned int chan;
3374         struct sk_buff *skb;
3375         struct adapter *adap;
3376         struct cpl_pass_open_req *req;
3377         int ret;
3378
3379         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3380         if (!skb)
3381                 return -ENOMEM;
3382
3383         adap = netdev2adap(dev);
3384         req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3385         INIT_TP_WR(req, 0);
3386         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3387         req->local_port = sport;
3388         req->peer_port = htons(0);
3389         req->local_ip = sip;
3390         req->peer_ip = htonl(0);
3391         chan = rxq_to_chan(&adap->sge, queue);
3392         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3393         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3394                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3395         ret = t4_mgmt_tx(adap, skb);
3396         return net_xmit_eval(ret);
3397 }
3398 EXPORT_SYMBOL(cxgb4_create_server);
3399
3400 /*      cxgb4_create_server6 - create an IPv6 server
3401  *      @dev: the device
3402  *      @stid: the server TID
3403  *      @sip: local IPv6 address to bind server to
3404  *      @sport: the server's TCP port
3405  *      @queue: queue to direct messages from this server to
3406  *
3407  *      Create an IPv6 server for the given port and address.
3408  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3409  */
3410 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3411                          const struct in6_addr *sip, __be16 sport,
3412                          unsigned int queue)
3413 {
3414         unsigned int chan;
3415         struct sk_buff *skb;
3416         struct adapter *adap;
3417         struct cpl_pass_open_req6 *req;
3418         int ret;
3419
3420         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3421         if (!skb)
3422                 return -ENOMEM;
3423
3424         adap = netdev2adap(dev);
3425         req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3426         INIT_TP_WR(req, 0);
3427         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3428         req->local_port = sport;
3429         req->peer_port = htons(0);
3430         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3431         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3432         req->peer_ip_hi = cpu_to_be64(0);
3433         req->peer_ip_lo = cpu_to_be64(0);
3434         chan = rxq_to_chan(&adap->sge, queue);
3435         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3436         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3437                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3438         ret = t4_mgmt_tx(adap, skb);
3439         return net_xmit_eval(ret);
3440 }
3441 EXPORT_SYMBOL(cxgb4_create_server6);
3442
3443 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3444                         unsigned int queue, bool ipv6)
3445 {
3446         struct sk_buff *skb;
3447         struct adapter *adap;
3448         struct cpl_close_listsvr_req *req;
3449         int ret;
3450
3451         adap = netdev2adap(dev);
3452
3453         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3454         if (!skb)
3455                 return -ENOMEM;
3456
3457         req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3458         INIT_TP_WR(req, 0);
3459         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3460         req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3461                                 LISTSVR_IPV6(0)) | QUEUENO(queue));
3462         ret = t4_mgmt_tx(adap, skb);
3463         return net_xmit_eval(ret);
3464 }
3465 EXPORT_SYMBOL(cxgb4_remove_server);
3466
3467 /**
3468  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3469  *      @mtus: the HW MTU table
3470  *      @mtu: the target MTU
3471  *      @idx: index of selected entry in the MTU table
3472  *
3473  *      Returns the index and the value in the HW MTU table that is closest to
3474  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
3475  *      table, in which case that smallest available value is selected.
3476  */
3477 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3478                             unsigned int *idx)
3479 {
3480         unsigned int i = 0;
3481
3482         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3483                 ++i;
3484         if (idx)
3485                 *idx = i;
3486         return mtus[i];
3487 }
3488 EXPORT_SYMBOL(cxgb4_best_mtu);
3489
3490 /**
3491  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3492  *     @mtus: the HW MTU table
3493  *     @header_size: Header Size
3494  *     @data_size_max: maximum Data Segment Size
3495  *     @data_size_align: desired Data Segment Size Alignment (2^N)
3496  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3497  *
3498  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
3499  *     MTU Table based solely on a Maximum MTU parameter, we break that
3500  *     parameter up into a Header Size and Maximum Data Segment Size, and
3501  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
3502  *     the Hardware MTU Table which will result in a Data Segment Size with
3503  *     the requested alignment _and_ that MTU isn't "too far" from the
3504  *     closest MTU, then we'll return that rather than the closest MTU.
3505  */
3506 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3507                                     unsigned short header_size,
3508                                     unsigned short data_size_max,
3509                                     unsigned short data_size_align,
3510                                     unsigned int *mtu_idxp)
3511 {
3512         unsigned short max_mtu = header_size + data_size_max;
3513         unsigned short data_size_align_mask = data_size_align - 1;
3514         int mtu_idx, aligned_mtu_idx;
3515
3516         /* Scan the MTU Table till we find an MTU which is larger than our
3517          * Maximum MTU or we reach the end of the table.  Along the way,
3518          * record the last MTU found, if any, which will result in a Data
3519          * Segment Length matching the requested alignment.
3520          */
3521         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3522                 unsigned short data_size = mtus[mtu_idx] - header_size;
3523
3524                 /* If this MTU minus the Header Size would result in a
3525                  * Data Segment Size of the desired alignment, remember it.
3526                  */
3527                 if ((data_size & data_size_align_mask) == 0)
3528                         aligned_mtu_idx = mtu_idx;
3529
3530                 /* If we're not at the end of the Hardware MTU Table and the
3531                  * next element is larger than our Maximum MTU, drop out of
3532                  * the loop.
3533                  */
3534                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3535                         break;
3536         }
3537
3538         /* If we fell out of the loop because we ran to the end of the table,
3539          * then we just have to use the last [largest] entry.
3540          */
3541         if (mtu_idx == NMTUS)
3542                 mtu_idx--;
3543
3544         /* If we found an MTU which resulted in the requested Data Segment
3545          * Length alignment and that's "not far" from the largest MTU which is
3546          * less than or equal to the maximum MTU, then use that.
3547          */
3548         if (aligned_mtu_idx >= 0 &&
3549             mtu_idx - aligned_mtu_idx <= 1)
3550                 mtu_idx = aligned_mtu_idx;
3551
3552         /* If the caller has passed in an MTU Index pointer, pass the
3553          * MTU Index back.  Return the MTU value.
3554          */
3555         if (mtu_idxp)
3556                 *mtu_idxp = mtu_idx;
3557         return mtus[mtu_idx];
3558 }
3559 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3560
3561 /**
3562  *      cxgb4_port_chan - get the HW channel of a port
3563  *      @dev: the net device for the port
3564  *
3565  *      Return the HW Tx channel of the given port.
3566  */
3567 unsigned int cxgb4_port_chan(const struct net_device *dev)
3568 {
3569         return netdev2pinfo(dev)->tx_chan;
3570 }
3571 EXPORT_SYMBOL(cxgb4_port_chan);
3572
3573 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3574 {
3575         struct adapter *adap = netdev2adap(dev);
3576         u32 v1, v2, lp_count, hp_count;
3577
3578         v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3579         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3580         if (is_t4(adap->params.chip)) {
3581                 lp_count = G_LP_COUNT(v1);
3582                 hp_count = G_HP_COUNT(v1);
3583         } else {
3584                 lp_count = G_LP_COUNT_T5(v1);
3585                 hp_count = G_HP_COUNT_T5(v2);
3586         }
3587         return lpfifo ? lp_count : hp_count;
3588 }
3589 EXPORT_SYMBOL(cxgb4_dbfifo_count);
3590
3591 /**
3592  *      cxgb4_port_viid - get the VI id of a port
3593  *      @dev: the net device for the port
3594  *
3595  *      Return the VI id of the given port.
3596  */
3597 unsigned int cxgb4_port_viid(const struct net_device *dev)
3598 {
3599         return netdev2pinfo(dev)->viid;
3600 }
3601 EXPORT_SYMBOL(cxgb4_port_viid);
3602
3603 /**
3604  *      cxgb4_port_idx - get the index of a port
3605  *      @dev: the net device for the port
3606  *
3607  *      Return the index of the given port.
3608  */
3609 unsigned int cxgb4_port_idx(const struct net_device *dev)
3610 {
3611         return netdev2pinfo(dev)->port_id;
3612 }
3613 EXPORT_SYMBOL(cxgb4_port_idx);
3614
3615 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3616                          struct tp_tcp_stats *v6)
3617 {
3618         struct adapter *adap = pci_get_drvdata(pdev);
3619
3620         spin_lock(&adap->stats_lock);
3621         t4_tp_get_tcp_stats(adap, v4, v6);
3622         spin_unlock(&adap->stats_lock);
3623 }
3624 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3625
3626 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3627                       const unsigned int *pgsz_order)
3628 {
3629         struct adapter *adap = netdev2adap(dev);
3630
3631         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3632         t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3633                      HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3634                      HPZ3(pgsz_order[3]));
3635 }
3636 EXPORT_SYMBOL(cxgb4_iscsi_init);
3637
3638 int cxgb4_flush_eq_cache(struct net_device *dev)
3639 {
3640         struct adapter *adap = netdev2adap(dev);
3641         int ret;
3642
3643         ret = t4_fwaddrspace_write(adap, adap->mbox,
3644                                    0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3645         return ret;
3646 }
3647 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3648
3649 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3650 {
3651         u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3652         __be64 indices;
3653         int ret;
3654
3655         spin_lock(&adap->win0_lock);
3656         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3657                            sizeof(indices), (__be32 *)&indices,
3658                            T4_MEMORY_READ);
3659         spin_unlock(&adap->win0_lock);
3660         if (!ret) {
3661                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3662                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3663         }
3664         return ret;
3665 }
3666
3667 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3668                         u16 size)
3669 {
3670         struct adapter *adap = netdev2adap(dev);
3671         u16 hw_pidx, hw_cidx;
3672         int ret;
3673
3674         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3675         if (ret)
3676                 goto out;
3677
3678         if (pidx != hw_pidx) {
3679                 u16 delta;
3680
3681                 if (pidx >= hw_pidx)
3682                         delta = pidx - hw_pidx;
3683                 else
3684                         delta = size - hw_pidx + pidx;
3685                 wmb();
3686                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3687                              QID(qid) | PIDX(delta));
3688         }
3689 out:
3690         return ret;
3691 }
3692 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3693
3694 void cxgb4_disable_db_coalescing(struct net_device *dev)
3695 {
3696         struct adapter *adap;
3697
3698         adap = netdev2adap(dev);
3699         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3700                          F_NOCOALESCE);
3701 }
3702 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3703
3704 void cxgb4_enable_db_coalescing(struct net_device *dev)
3705 {
3706         struct adapter *adap;
3707
3708         adap = netdev2adap(dev);
3709         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3710 }
3711 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3712
3713 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
3714 {
3715         struct adapter *adap;
3716         u32 offset, memtype, memaddr;
3717         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
3718         u32 edc0_end, edc1_end, mc0_end, mc1_end;
3719         int ret;
3720
3721         adap = netdev2adap(dev);
3722
3723         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
3724
3725         /* Figure out where the offset lands in the Memory Type/Address scheme.
3726          * This code assumes that the memory is laid out starting at offset 0
3727          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3728          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
3729          * MC0, and some have both MC0 and MC1.
3730          */
3731         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
3732         edc0_size = EDRAM0_SIZE_G(size) << 20;
3733         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
3734         edc1_size = EDRAM1_SIZE_G(size) << 20;
3735         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
3736         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
3737
3738         edc0_end = edc0_size;
3739         edc1_end = edc0_end + edc1_size;
3740         mc0_end = edc1_end + mc0_size;
3741
3742         if (offset < edc0_end) {
3743                 memtype = MEM_EDC0;
3744                 memaddr = offset;
3745         } else if (offset < edc1_end) {
3746                 memtype = MEM_EDC1;
3747                 memaddr = offset - edc0_end;
3748         } else {
3749                 if (offset < mc0_end) {
3750                         memtype = MEM_MC0;
3751                         memaddr = offset - edc1_end;
3752                 } else if (is_t4(adap->params.chip)) {
3753                         /* T4 only has a single memory channel */
3754                         goto err;
3755                 } else {
3756                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
3757                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
3758                         mc1_end = mc0_end + mc1_size;
3759                         if (offset < mc1_end) {
3760                                 memtype = MEM_MC1;
3761                                 memaddr = offset - mc0_end;
3762                         } else {
3763                                 /* offset beyond the end of any memory */
3764                                 goto err;
3765                         }
3766                 }
3767         }
3768
3769         spin_lock(&adap->win0_lock);
3770         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
3771         spin_unlock(&adap->win0_lock);
3772         return ret;
3773
3774 err:
3775         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
3776                 stag, offset);
3777         return -EINVAL;
3778 }
3779 EXPORT_SYMBOL(cxgb4_read_tpte);
3780
3781 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
3782 {
3783         u32 hi, lo;
3784         struct adapter *adap;
3785
3786         adap = netdev2adap(dev);
3787         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
3788         hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
3789
3790         return ((u64)hi << 32) | (u64)lo;
3791 }
3792 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
3793
3794 static struct pci_driver cxgb4_driver;
3795
3796 static void check_neigh_update(struct neighbour *neigh)
3797 {
3798         const struct device *parent;
3799         const struct net_device *netdev = neigh->dev;
3800
3801         if (netdev->priv_flags & IFF_802_1Q_VLAN)
3802                 netdev = vlan_dev_real_dev(netdev);
3803         parent = netdev->dev.parent;
3804         if (parent && parent->driver == &cxgb4_driver.driver)
3805                 t4_l2t_update(dev_get_drvdata(parent), neigh);
3806 }
3807
3808 static int netevent_cb(struct notifier_block *nb, unsigned long event,
3809                        void *data)
3810 {
3811         switch (event) {
3812         case NETEVENT_NEIGH_UPDATE:
3813                 check_neigh_update(data);
3814                 break;
3815         case NETEVENT_REDIRECT:
3816         default:
3817                 break;
3818         }
3819         return 0;
3820 }
3821
3822 static bool netevent_registered;
3823 static struct notifier_block cxgb4_netevent_nb = {
3824         .notifier_call = netevent_cb
3825 };
3826
3827 static void drain_db_fifo(struct adapter *adap, int usecs)
3828 {
3829         u32 v1, v2, lp_count, hp_count;
3830
3831         do {
3832                 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3833                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3834                 if (is_t4(adap->params.chip)) {
3835                         lp_count = G_LP_COUNT(v1);
3836                         hp_count = G_HP_COUNT(v1);
3837                 } else {
3838                         lp_count = G_LP_COUNT_T5(v1);
3839                         hp_count = G_HP_COUNT_T5(v2);
3840                 }
3841
3842                 if (lp_count == 0 && hp_count == 0)
3843                         break;
3844                 set_current_state(TASK_UNINTERRUPTIBLE);
3845                 schedule_timeout(usecs_to_jiffies(usecs));
3846         } while (1);
3847 }
3848
3849 static void disable_txq_db(struct sge_txq *q)
3850 {
3851         unsigned long flags;
3852
3853         spin_lock_irqsave(&q->db_lock, flags);
3854         q->db_disabled = 1;
3855         spin_unlock_irqrestore(&q->db_lock, flags);
3856 }
3857
3858 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3859 {
3860         spin_lock_irq(&q->db_lock);
3861         if (q->db_pidx_inc) {
3862                 /* Make sure that all writes to the TX descriptors
3863                  * are committed before we tell HW about them.
3864                  */
3865                 wmb();
3866                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3867                              QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3868                 q->db_pidx_inc = 0;
3869         }
3870         q->db_disabled = 0;
3871         spin_unlock_irq(&q->db_lock);
3872 }
3873
3874 static void disable_dbs(struct adapter *adap)
3875 {
3876         int i;
3877
3878         for_each_ethrxq(&adap->sge, i)
3879                 disable_txq_db(&adap->sge.ethtxq[i].q);
3880         for_each_ofldrxq(&adap->sge, i)
3881                 disable_txq_db(&adap->sge.ofldtxq[i].q);
3882         for_each_port(adap, i)
3883                 disable_txq_db(&adap->sge.ctrlq[i].q);
3884 }
3885
3886 static void enable_dbs(struct adapter *adap)
3887 {
3888         int i;
3889
3890         for_each_ethrxq(&adap->sge, i)
3891                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3892         for_each_ofldrxq(&adap->sge, i)
3893                 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3894         for_each_port(adap, i)
3895                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
3896 }
3897
3898 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3899 {
3900         if (adap->uld_handle[CXGB4_ULD_RDMA])
3901                 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3902                                 cmd);
3903 }
3904
3905 static void process_db_full(struct work_struct *work)
3906 {
3907         struct adapter *adap;
3908
3909         adap = container_of(work, struct adapter, db_full_task);
3910
3911         drain_db_fifo(adap, dbfifo_drain_delay);
3912         enable_dbs(adap);
3913         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3914         t4_set_reg_field(adap, SGE_INT_ENABLE3,
3915                          DBFIFO_HP_INT | DBFIFO_LP_INT,
3916                          DBFIFO_HP_INT | DBFIFO_LP_INT);
3917 }
3918
3919 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
3920 {
3921         u16 hw_pidx, hw_cidx;
3922         int ret;
3923
3924         spin_lock_irq(&q->db_lock);
3925         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
3926         if (ret)
3927                 goto out;
3928         if (q->db_pidx != hw_pidx) {
3929                 u16 delta;
3930
3931                 if (q->db_pidx >= hw_pidx)
3932                         delta = q->db_pidx - hw_pidx;
3933                 else
3934                         delta = q->size - hw_pidx + q->db_pidx;
3935                 wmb();
3936                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3937                              QID(q->cntxt_id) | PIDX(delta));
3938         }
3939 out:
3940         q->db_disabled = 0;
3941         q->db_pidx_inc = 0;
3942         spin_unlock_irq(&q->db_lock);
3943         if (ret)
3944                 CH_WARN(adap, "DB drop recovery failed.\n");
3945 }
3946 static void recover_all_queues(struct adapter *adap)
3947 {
3948         int i;
3949
3950         for_each_ethrxq(&adap->sge, i)
3951                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
3952         for_each_ofldrxq(&adap->sge, i)
3953                 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
3954         for_each_port(adap, i)
3955                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
3956 }
3957
3958 static void process_db_drop(struct work_struct *work)
3959 {
3960         struct adapter *adap;
3961
3962         adap = container_of(work, struct adapter, db_drop_task);
3963
3964         if (is_t4(adap->params.chip)) {
3965                 drain_db_fifo(adap, dbfifo_drain_delay);
3966                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
3967                 drain_db_fifo(adap, dbfifo_drain_delay);
3968                 recover_all_queues(adap);
3969                 drain_db_fifo(adap, dbfifo_drain_delay);
3970                 enable_dbs(adap);
3971                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3972         } else {
3973                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
3974                 u16 qid = (dropped_db >> 15) & 0x1ffff;
3975                 u16 pidx_inc = dropped_db & 0x1fff;
3976                 unsigned int s_qpp;
3977                 unsigned short udb_density;
3978                 unsigned long qpshift;
3979                 int page;
3980                 u32 udb;
3981
3982                 dev_warn(adap->pdev_dev,
3983                          "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
3984                          dropped_db, qid,
3985                          (dropped_db >> 14) & 1,
3986                          (dropped_db >> 13) & 1,
3987                          pidx_inc);
3988
3989                 drain_db_fifo(adap, 1);
3990
3991                 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
3992                 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
3993                                 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
3994                 qpshift = PAGE_SHIFT - ilog2(udb_density);
3995                 udb = qid << qpshift;
3996                 udb &= PAGE_MASK;
3997                 page = udb / PAGE_SIZE;
3998                 udb += (qid - (page * udb_density)) * 128;
3999
4000                 writel(PIDX(pidx_inc),  adap->bar2 + udb + 8);
4001
4002                 /* Re-enable BAR2 WC */
4003                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4004         }
4005
4006         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
4007 }
4008
4009 void t4_db_full(struct adapter *adap)
4010 {
4011         if (is_t4(adap->params.chip)) {
4012                 disable_dbs(adap);
4013                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4014                 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4015                                  DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4016                 queue_work(adap->workq, &adap->db_full_task);
4017         }
4018 }
4019
4020 void t4_db_dropped(struct adapter *adap)
4021 {
4022         if (is_t4(adap->params.chip)) {
4023                 disable_dbs(adap);
4024                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4025         }
4026         queue_work(adap->workq, &adap->db_drop_task);
4027 }
4028
4029 static void uld_attach(struct adapter *adap, unsigned int uld)
4030 {
4031         void *handle;
4032         struct cxgb4_lld_info lli;
4033         unsigned short i;
4034
4035         lli.pdev = adap->pdev;
4036         lli.pf = adap->fn;
4037         lli.l2t = adap->l2t;
4038         lli.tids = &adap->tids;
4039         lli.ports = adap->port;
4040         lli.vr = &adap->vres;
4041         lli.mtus = adap->params.mtus;
4042         if (uld == CXGB4_ULD_RDMA) {
4043                 lli.rxq_ids = adap->sge.rdma_rxq;
4044                 lli.ciq_ids = adap->sge.rdma_ciq;
4045                 lli.nrxq = adap->sge.rdmaqs;
4046                 lli.nciq = adap->sge.rdmaciqs;
4047         } else if (uld == CXGB4_ULD_ISCSI) {
4048                 lli.rxq_ids = adap->sge.ofld_rxq;
4049                 lli.nrxq = adap->sge.ofldqsets;
4050         }
4051         lli.ntxq = adap->sge.ofldqsets;
4052         lli.nchan = adap->params.nports;
4053         lli.nports = adap->params.nports;
4054         lli.wr_cred = adap->params.ofldq_wr_cred;
4055         lli.adapter_type = adap->params.chip;
4056         lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4057         lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
4058         lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
4059                         t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4060                         (adap->fn * 4));
4061         lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
4062                         t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4063                         (adap->fn * 4));
4064         lli.filt_mode = adap->params.tp.vlan_pri_map;
4065         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4066         for (i = 0; i < NCHAN; i++)
4067                 lli.tx_modq[i] = i;
4068         lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4069         lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4070         lli.fw_vers = adap->params.fw_vers;
4071         lli.dbfifo_int_thresh = dbfifo_int_thresh;
4072         lli.sge_ingpadboundary = adap->sge.fl_align;
4073         lli.sge_egrstatuspagesize = adap->sge.stat_len;
4074         lli.sge_pktshift = adap->sge.pktshift;
4075         lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4076         lli.max_ordird_qp = adap->params.max_ordird_qp;
4077         lli.max_ird_adapter = adap->params.max_ird_adapter;
4078         lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
4079
4080         handle = ulds[uld].add(&lli);
4081         if (IS_ERR(handle)) {
4082                 dev_warn(adap->pdev_dev,
4083                          "could not attach to the %s driver, error %ld\n",
4084                          uld_str[uld], PTR_ERR(handle));
4085                 return;
4086         }
4087
4088         adap->uld_handle[uld] = handle;
4089
4090         if (!netevent_registered) {
4091                 register_netevent_notifier(&cxgb4_netevent_nb);
4092                 netevent_registered = true;
4093         }
4094
4095         if (adap->flags & FULL_INIT_DONE)
4096                 ulds[uld].state_change(handle, CXGB4_STATE_UP);
4097 }
4098
4099 static void attach_ulds(struct adapter *adap)
4100 {
4101         unsigned int i;
4102
4103         spin_lock(&adap_rcu_lock);
4104         list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4105         spin_unlock(&adap_rcu_lock);
4106
4107         mutex_lock(&uld_mutex);
4108         list_add_tail(&adap->list_node, &adapter_list);
4109         for (i = 0; i < CXGB4_ULD_MAX; i++)
4110                 if (ulds[i].add)
4111                         uld_attach(adap, i);
4112         mutex_unlock(&uld_mutex);
4113 }
4114
4115 static void detach_ulds(struct adapter *adap)
4116 {
4117         unsigned int i;
4118
4119         mutex_lock(&uld_mutex);
4120         list_del(&adap->list_node);
4121         for (i = 0; i < CXGB4_ULD_MAX; i++)
4122                 if (adap->uld_handle[i]) {
4123                         ulds[i].state_change(adap->uld_handle[i],
4124                                              CXGB4_STATE_DETACH);
4125                         adap->uld_handle[i] = NULL;
4126                 }
4127         if (netevent_registered && list_empty(&adapter_list)) {
4128                 unregister_netevent_notifier(&cxgb4_netevent_nb);
4129                 netevent_registered = false;
4130         }
4131         mutex_unlock(&uld_mutex);
4132
4133         spin_lock(&adap_rcu_lock);
4134         list_del_rcu(&adap->rcu_node);
4135         spin_unlock(&adap_rcu_lock);
4136 }
4137
4138 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4139 {
4140         unsigned int i;
4141
4142         mutex_lock(&uld_mutex);
4143         for (i = 0; i < CXGB4_ULD_MAX; i++)
4144                 if (adap->uld_handle[i])
4145                         ulds[i].state_change(adap->uld_handle[i], new_state);
4146         mutex_unlock(&uld_mutex);
4147 }
4148
4149 /**
4150  *      cxgb4_register_uld - register an upper-layer driver
4151  *      @type: the ULD type
4152  *      @p: the ULD methods
4153  *
4154  *      Registers an upper-layer driver with this driver and notifies the ULD
4155  *      about any presently available devices that support its type.  Returns
4156  *      %-EBUSY if a ULD of the same type is already registered.
4157  */
4158 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4159 {
4160         int ret = 0;
4161         struct adapter *adap;
4162
4163         if (type >= CXGB4_ULD_MAX)
4164                 return -EINVAL;
4165         mutex_lock(&uld_mutex);
4166         if (ulds[type].add) {
4167                 ret = -EBUSY;
4168                 goto out;
4169         }
4170         ulds[type] = *p;
4171         list_for_each_entry(adap, &adapter_list, list_node)
4172                 uld_attach(adap, type);
4173 out:    mutex_unlock(&uld_mutex);
4174         return ret;
4175 }
4176 EXPORT_SYMBOL(cxgb4_register_uld);
4177
4178 /**
4179  *      cxgb4_unregister_uld - unregister an upper-layer driver
4180  *      @type: the ULD type
4181  *
4182  *      Unregisters an existing upper-layer driver.
4183  */
4184 int cxgb4_unregister_uld(enum cxgb4_uld type)
4185 {
4186         struct adapter *adap;
4187
4188         if (type >= CXGB4_ULD_MAX)
4189                 return -EINVAL;
4190         mutex_lock(&uld_mutex);
4191         list_for_each_entry(adap, &adapter_list, list_node)
4192                 adap->uld_handle[type] = NULL;
4193         ulds[type].add = NULL;
4194         mutex_unlock(&uld_mutex);
4195         return 0;
4196 }
4197 EXPORT_SYMBOL(cxgb4_unregister_uld);
4198
4199 /* Check if netdev on which event is occured belongs to us or not. Return
4200  * success (true) if it belongs otherwise failure (false).
4201  * Called with rcu_read_lock() held.
4202  */
4203 #if IS_ENABLED(CONFIG_IPV6)
4204 static bool cxgb4_netdev(const struct net_device *netdev)
4205 {
4206         struct adapter *adap;
4207         int i;
4208
4209         list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4210                 for (i = 0; i < MAX_NPORTS; i++)
4211                         if (adap->port[i] == netdev)
4212                                 return true;
4213         return false;
4214 }
4215
4216 static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4217                     unsigned long event)
4218 {
4219         int ret = NOTIFY_DONE;
4220
4221         rcu_read_lock();
4222         if (cxgb4_netdev(event_dev)) {
4223                 switch (event) {
4224                 case NETDEV_UP:
4225                         ret = cxgb4_clip_get(event_dev, &ifa->addr);
4226                         if (ret < 0) {
4227                                 rcu_read_unlock();
4228                                 return ret;
4229                         }
4230                         ret = NOTIFY_OK;
4231                         break;
4232                 case NETDEV_DOWN:
4233                         cxgb4_clip_release(event_dev, &ifa->addr);
4234                         ret = NOTIFY_OK;
4235                         break;
4236                 default:
4237                         break;
4238                 }
4239         }
4240         rcu_read_unlock();
4241         return ret;
4242 }
4243
4244 static int cxgb4_inet6addr_handler(struct notifier_block *this,
4245                 unsigned long event, void *data)
4246 {
4247         struct inet6_ifaddr *ifa = data;
4248         struct net_device *event_dev;
4249         int ret = NOTIFY_DONE;
4250         struct bonding *bond = netdev_priv(ifa->idev->dev);
4251         struct list_head *iter;
4252         struct slave *slave;
4253         struct pci_dev *first_pdev = NULL;
4254
4255         if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4256                 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4257                 ret = clip_add(event_dev, ifa, event);
4258         } else if (ifa->idev->dev->flags & IFF_MASTER) {
4259                 /* It is possible that two different adapters are bonded in one
4260                  * bond. We need to find such different adapters and add clip
4261                  * in all of them only once.
4262                  */
4263                 bond_for_each_slave(bond, slave, iter) {
4264                         if (!first_pdev) {
4265                                 ret = clip_add(slave->dev, ifa, event);
4266                                 /* If clip_add is success then only initialize
4267                                  * first_pdev since it means it is our device
4268                                  */
4269                                 if (ret == NOTIFY_OK)
4270                                         first_pdev = to_pci_dev(
4271                                                         slave->dev->dev.parent);
4272                         } else if (first_pdev !=
4273                                    to_pci_dev(slave->dev->dev.parent))
4274                                         ret = clip_add(slave->dev, ifa, event);
4275                 }
4276         } else
4277                 ret = clip_add(ifa->idev->dev, ifa, event);
4278
4279         return ret;
4280 }
4281
4282 static struct notifier_block cxgb4_inet6addr_notifier = {
4283         .notifier_call = cxgb4_inet6addr_handler
4284 };
4285
4286 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4287  * a physical device.
4288  * The physical device reference is needed to send the actul CLIP command.
4289  */
4290 static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4291 {
4292         struct inet6_dev *idev = NULL;
4293         struct inet6_ifaddr *ifa;
4294         int ret = 0;
4295
4296         idev = __in6_dev_get(root_dev);
4297         if (!idev)
4298                 return ret;
4299
4300         read_lock_bh(&idev->lock);
4301         list_for_each_entry(ifa, &idev->addr_list, if_list) {
4302                 ret = cxgb4_clip_get(dev, &ifa->addr);
4303                 if (ret < 0)
4304                         break;
4305         }
4306         read_unlock_bh(&idev->lock);
4307
4308         return ret;
4309 }
4310
4311 static int update_root_dev_clip(struct net_device *dev)
4312 {
4313         struct net_device *root_dev = NULL;
4314         int i, ret = 0;
4315
4316         /* First populate the real net device's IPv6 addresses */
4317         ret = update_dev_clip(dev, dev);
4318         if (ret)
4319                 return ret;
4320
4321         /* Parse all bond and vlan devices layered on top of the physical dev */
4322         root_dev = netdev_master_upper_dev_get_rcu(dev);
4323         if (root_dev) {
4324                 ret = update_dev_clip(root_dev, dev);
4325                 if (ret)
4326                         return ret;
4327         }
4328
4329         for (i = 0; i < VLAN_N_VID; i++) {
4330                 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
4331                 if (!root_dev)
4332                         continue;
4333
4334                 ret = update_dev_clip(root_dev, dev);
4335                 if (ret)
4336                         break;
4337         }
4338         return ret;
4339 }
4340
4341 static void update_clip(const struct adapter *adap)
4342 {
4343         int i;
4344         struct net_device *dev;
4345         int ret;
4346
4347         rcu_read_lock();
4348
4349         for (i = 0; i < MAX_NPORTS; i++) {
4350                 dev = adap->port[i];
4351                 ret = 0;
4352
4353                 if (dev)
4354                         ret = update_root_dev_clip(dev);
4355
4356                 if (ret < 0)
4357                         break;
4358         }
4359         rcu_read_unlock();
4360 }
4361 #endif /* IS_ENABLED(CONFIG_IPV6) */
4362
4363 /**
4364  *      cxgb_up - enable the adapter
4365  *      @adap: adapter being enabled
4366  *
4367  *      Called when the first port is enabled, this function performs the
4368  *      actions necessary to make an adapter operational, such as completing
4369  *      the initialization of HW modules, and enabling interrupts.
4370  *
4371  *      Must be called with the rtnl lock held.
4372  */
4373 static int cxgb_up(struct adapter *adap)
4374 {
4375         int err;
4376
4377         err = setup_sge_queues(adap);
4378         if (err)
4379                 goto out;
4380         err = setup_rss(adap);
4381         if (err)
4382                 goto freeq;
4383
4384         if (adap->flags & USING_MSIX) {
4385                 name_msix_vecs(adap);
4386                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4387                                   adap->msix_info[0].desc, adap);
4388                 if (err)
4389                         goto irq_err;
4390
4391                 err = request_msix_queue_irqs(adap);
4392                 if (err) {
4393                         free_irq(adap->msix_info[0].vec, adap);
4394                         goto irq_err;
4395                 }
4396         } else {
4397                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4398                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
4399                                   adap->port[0]->name, adap);
4400                 if (err)
4401                         goto irq_err;
4402         }
4403         enable_rx(adap);
4404         t4_sge_start(adap);
4405         t4_intr_enable(adap);
4406         adap->flags |= FULL_INIT_DONE;
4407         notify_ulds(adap, CXGB4_STATE_UP);
4408 #if IS_ENABLED(CONFIG_IPV6)
4409         update_clip(adap);
4410 #endif
4411  out:
4412         return err;
4413  irq_err:
4414         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
4415  freeq:
4416         t4_free_sge_resources(adap);
4417         goto out;
4418 }
4419
4420 static void cxgb_down(struct adapter *adapter)
4421 {
4422         t4_intr_disable(adapter);
4423         cancel_work_sync(&adapter->tid_release_task);
4424         cancel_work_sync(&adapter->db_full_task);
4425         cancel_work_sync(&adapter->db_drop_task);
4426         adapter->tid_release_task_busy = false;
4427         adapter->tid_release_head = NULL;
4428
4429         if (adapter->flags & USING_MSIX) {
4430                 free_msix_queue_irqs(adapter);
4431                 free_irq(adapter->msix_info[0].vec, adapter);
4432         } else
4433                 free_irq(adapter->pdev->irq, adapter);
4434         quiesce_rx(adapter);
4435         t4_sge_stop(adapter);
4436         t4_free_sge_resources(adapter);
4437         adapter->flags &= ~FULL_INIT_DONE;
4438 }
4439
4440 /*
4441  * net_device operations
4442  */
4443 static int cxgb_open(struct net_device *dev)
4444 {
4445         int err;
4446         struct port_info *pi = netdev_priv(dev);
4447         struct adapter *adapter = pi->adapter;
4448
4449         netif_carrier_off(dev);
4450
4451         if (!(adapter->flags & FULL_INIT_DONE)) {
4452                 err = cxgb_up(adapter);
4453                 if (err < 0)
4454                         return err;
4455         }
4456
4457         err = link_start(dev);
4458         if (!err)
4459                 netif_tx_start_all_queues(dev);
4460         return err;
4461 }
4462
4463 static int cxgb_close(struct net_device *dev)
4464 {
4465         struct port_info *pi = netdev_priv(dev);
4466         struct adapter *adapter = pi->adapter;
4467
4468         netif_tx_stop_all_queues(dev);
4469         netif_carrier_off(dev);
4470         return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
4471 }
4472
4473 /* Return an error number if the indicated filter isn't writable ...
4474  */
4475 static int writable_filter(struct filter_entry *f)
4476 {
4477         if (f->locked)
4478                 return -EPERM;
4479         if (f->pending)
4480                 return -EBUSY;
4481
4482         return 0;
4483 }
4484
4485 /* Delete the filter at the specified index (if valid).  The checks for all
4486  * the common problems with doing this like the filter being locked, currently
4487  * pending in another operation, etc.
4488  */
4489 static int delete_filter(struct adapter *adapter, unsigned int fidx)
4490 {
4491         struct filter_entry *f;
4492         int ret;
4493
4494         if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
4495                 return -EINVAL;
4496
4497         f = &adapter->tids.ftid_tab[fidx];
4498         ret = writable_filter(f);
4499         if (ret)
4500                 return ret;
4501         if (f->valid)
4502                 return del_filter_wr(adapter, fidx);
4503
4504         return 0;
4505 }
4506
4507 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
4508                 __be32 sip, __be16 sport, __be16 vlan,
4509                 unsigned int queue, unsigned char port, unsigned char mask)
4510 {
4511         int ret;
4512         struct filter_entry *f;
4513         struct adapter *adap;
4514         int i;
4515         u8 *val;
4516
4517         adap = netdev2adap(dev);
4518
4519         /* Adjust stid to correct filter index */
4520         stid -= adap->tids.sftid_base;
4521         stid += adap->tids.nftids;
4522
4523         /* Check to make sure the filter requested is writable ...
4524          */
4525         f = &adap->tids.ftid_tab[stid];
4526         ret = writable_filter(f);
4527         if (ret)
4528                 return ret;
4529
4530         /* Clear out any old resources being used by the filter before
4531          * we start constructing the new filter.
4532          */
4533         if (f->valid)
4534                 clear_filter(adap, f);
4535
4536         /* Clear out filter specifications */
4537         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4538         f->fs.val.lport = cpu_to_be16(sport);
4539         f->fs.mask.lport  = ~0;
4540         val = (u8 *)&sip;
4541         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
4542                 for (i = 0; i < 4; i++) {
4543                         f->fs.val.lip[i] = val[i];
4544                         f->fs.mask.lip[i] = ~0;
4545                 }
4546                 if (adap->params.tp.vlan_pri_map & F_PORT) {
4547                         f->fs.val.iport = port;
4548                         f->fs.mask.iport = mask;
4549                 }
4550         }
4551
4552         if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
4553                 f->fs.val.proto = IPPROTO_TCP;
4554                 f->fs.mask.proto = ~0;
4555         }
4556
4557         f->fs.dirsteer = 1;
4558         f->fs.iq = queue;
4559         /* Mark filter as locked */
4560         f->locked = 1;
4561         f->fs.rpttid = 1;
4562
4563         ret = set_filter_wr(adap, stid);
4564         if (ret) {
4565                 clear_filter(adap, f);
4566                 return ret;
4567         }
4568
4569         return 0;
4570 }
4571 EXPORT_SYMBOL(cxgb4_create_server_filter);
4572
4573 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4574                 unsigned int queue, bool ipv6)
4575 {
4576         int ret;
4577         struct filter_entry *f;
4578         struct adapter *adap;
4579
4580         adap = netdev2adap(dev);
4581
4582         /* Adjust stid to correct filter index */
4583         stid -= adap->tids.sftid_base;
4584         stid += adap->tids.nftids;
4585
4586         f = &adap->tids.ftid_tab[stid];
4587         /* Unlock the filter */
4588         f->locked = 0;
4589
4590         ret = delete_filter(adap, stid);
4591         if (ret)
4592                 return ret;
4593
4594         return 0;
4595 }
4596 EXPORT_SYMBOL(cxgb4_remove_server_filter);
4597
4598 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4599                                                 struct rtnl_link_stats64 *ns)
4600 {
4601         struct port_stats stats;
4602         struct port_info *p = netdev_priv(dev);
4603         struct adapter *adapter = p->adapter;
4604
4605         /* Block retrieving statistics during EEH error
4606          * recovery. Otherwise, the recovery might fail
4607          * and the PCI device will be removed permanently
4608          */
4609         spin_lock(&adapter->stats_lock);
4610         if (!netif_device_present(dev)) {
4611                 spin_unlock(&adapter->stats_lock);
4612                 return ns;
4613         }
4614         t4_get_port_stats(adapter, p->tx_chan, &stats);
4615         spin_unlock(&adapter->stats_lock);
4616
4617         ns->tx_bytes   = stats.tx_octets;
4618         ns->tx_packets = stats.tx_frames;
4619         ns->rx_bytes   = stats.rx_octets;
4620         ns->rx_packets = stats.rx_frames;
4621         ns->multicast  = stats.rx_mcast_frames;
4622
4623         /* detailed rx_errors */
4624         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4625                                stats.rx_runt;
4626         ns->rx_over_errors   = 0;
4627         ns->rx_crc_errors    = stats.rx_fcs_err;
4628         ns->rx_frame_errors  = stats.rx_symbol_err;
4629         ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
4630                                stats.rx_ovflow2 + stats.rx_ovflow3 +
4631                                stats.rx_trunc0 + stats.rx_trunc1 +
4632                                stats.rx_trunc2 + stats.rx_trunc3;
4633         ns->rx_missed_errors = 0;
4634
4635         /* detailed tx_errors */
4636         ns->tx_aborted_errors   = 0;
4637         ns->tx_carrier_errors   = 0;
4638         ns->tx_fifo_errors      = 0;
4639         ns->tx_heartbeat_errors = 0;
4640         ns->tx_window_errors    = 0;
4641
4642         ns->tx_errors = stats.tx_error_frames;
4643         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4644                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4645         return ns;
4646 }
4647
4648 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4649 {
4650         unsigned int mbox;
4651         int ret = 0, prtad, devad;
4652         struct port_info *pi = netdev_priv(dev);
4653         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4654
4655         switch (cmd) {
4656         case SIOCGMIIPHY:
4657                 if (pi->mdio_addr < 0)
4658                         return -EOPNOTSUPP;
4659                 data->phy_id = pi->mdio_addr;
4660                 break;
4661         case SIOCGMIIREG:
4662         case SIOCSMIIREG:
4663                 if (mdio_phy_id_is_c45(data->phy_id)) {
4664                         prtad = mdio_phy_id_prtad(data->phy_id);
4665                         devad = mdio_phy_id_devad(data->phy_id);
4666                 } else if (data->phy_id < 32) {
4667                         prtad = data->phy_id;
4668                         devad = 0;
4669                         data->reg_num &= 0x1f;
4670                 } else
4671                         return -EINVAL;
4672
4673                 mbox = pi->adapter->fn;
4674                 if (cmd == SIOCGMIIREG)
4675                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
4676                                          data->reg_num, &data->val_out);
4677                 else
4678                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
4679                                          data->reg_num, data->val_in);
4680                 break;
4681         default:
4682                 return -EOPNOTSUPP;
4683         }
4684         return ret;
4685 }
4686
4687 static void cxgb_set_rxmode(struct net_device *dev)
4688 {
4689         /* unfortunately we can't return errors to the stack */
4690         set_rxmode(dev, -1, false);
4691 }
4692
4693 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4694 {
4695         int ret;
4696         struct port_info *pi = netdev_priv(dev);
4697
4698         if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
4699                 return -EINVAL;
4700         ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4701                             -1, -1, -1, true);
4702         if (!ret)
4703                 dev->mtu = new_mtu;
4704         return ret;
4705 }
4706
4707 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4708 {
4709         int ret;
4710         struct sockaddr *addr = p;
4711         struct port_info *pi = netdev_priv(dev);
4712
4713         if (!is_valid_ether_addr(addr->sa_data))
4714                 return -EADDRNOTAVAIL;
4715
4716         ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4717                             pi->xact_addr_filt, addr->sa_data, true, true);
4718         if (ret < 0)
4719                 return ret;
4720
4721         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4722         pi->xact_addr_filt = ret;
4723         return 0;
4724 }
4725
4726 #ifdef CONFIG_NET_POLL_CONTROLLER
4727 static void cxgb_netpoll(struct net_device *dev)
4728 {
4729         struct port_info *pi = netdev_priv(dev);
4730         struct adapter *adap = pi->adapter;
4731
4732         if (adap->flags & USING_MSIX) {
4733                 int i;
4734                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4735
4736                 for (i = pi->nqsets; i; i--, rx++)
4737                         t4_sge_intr_msix(0, &rx->rspq);
4738         } else
4739                 t4_intr_handler(adap)(0, adap);
4740 }
4741 #endif
4742
4743 static const struct net_device_ops cxgb4_netdev_ops = {
4744         .ndo_open             = cxgb_open,
4745         .ndo_stop             = cxgb_close,
4746         .ndo_start_xmit       = t4_eth_xmit,
4747         .ndo_select_queue     = cxgb_select_queue,
4748         .ndo_get_stats64      = cxgb_get_stats,
4749         .ndo_set_rx_mode      = cxgb_set_rxmode,
4750         .ndo_set_mac_address  = cxgb_set_mac_addr,
4751         .ndo_set_features     = cxgb_set_features,
4752         .ndo_validate_addr    = eth_validate_addr,
4753         .ndo_do_ioctl         = cxgb_ioctl,
4754         .ndo_change_mtu       = cxgb_change_mtu,
4755 #ifdef CONFIG_NET_POLL_CONTROLLER
4756         .ndo_poll_controller  = cxgb_netpoll,
4757 #endif
4758 };
4759
4760 void t4_fatal_err(struct adapter *adap)
4761 {
4762         t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4763         t4_intr_disable(adap);
4764         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4765 }
4766
4767 /* Return the specified PCI-E Configuration Space register from our Physical
4768  * Function.  We try first via a Firmware LDST Command since we prefer to let
4769  * the firmware own all of these registers, but if that fails we go for it
4770  * directly ourselves.
4771  */
4772 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4773 {
4774         struct fw_ldst_cmd ldst_cmd;
4775         u32 val;
4776         int ret;
4777
4778         /* Construct and send the Firmware LDST Command to retrieve the
4779          * specified PCI-E Configuration Space register.
4780          */
4781         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4782         ldst_cmd.op_to_addrspace =
4783                 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
4784                       FW_CMD_REQUEST_F |
4785                       FW_CMD_READ_F |
4786                       FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
4787         ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4788         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
4789         ldst_cmd.u.pcie.ctrl_to_fn =
4790                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
4791         ldst_cmd.u.pcie.r = reg;
4792         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4793                          &ldst_cmd);
4794
4795         /* If the LDST Command suucceeded, exctract the returned register
4796          * value.  Otherwise read it directly ourself.
4797          */
4798         if (ret == 0)
4799                 val = ntohl(ldst_cmd.u.pcie.data[0]);
4800         else
4801                 t4_hw_pci_read_cfg4(adap, reg, &val);
4802
4803         return val;
4804 }
4805
4806 static void setup_memwin(struct adapter *adap)
4807 {
4808         u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
4809
4810         if (is_t4(adap->params.chip)) {
4811                 u32 bar0;
4812
4813                 /* Truncation intentional: we only read the bottom 32-bits of
4814                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
4815                  * mechanism to read BAR0 instead of using
4816                  * pci_resource_start() because we could be operating from
4817                  * within a Virtual Machine which is trapping our accesses to
4818                  * our Configuration Space and we need to set up the PCI-E
4819                  * Memory Window decoders with the actual addresses which will
4820                  * be coming across the PCI-E link.
4821                  */
4822                 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4823                 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4824                 adap->t4_bar0 = bar0;
4825
4826                 mem_win0_base = bar0 + MEMWIN0_BASE;
4827                 mem_win1_base = bar0 + MEMWIN1_BASE;
4828                 mem_win2_base = bar0 + MEMWIN2_BASE;
4829                 mem_win2_aperture = MEMWIN2_APERTURE;
4830         } else {
4831                 /* For T5, only relative offset inside the PCIe BAR is passed */
4832                 mem_win0_base = MEMWIN0_BASE;
4833                 mem_win1_base = MEMWIN1_BASE;
4834                 mem_win2_base = MEMWIN2_BASE_T5;
4835                 mem_win2_aperture = MEMWIN2_APERTURE_T5;
4836         }
4837         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
4838                      mem_win0_base | BIR(0) |
4839                      WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4840         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
4841                      mem_win1_base | BIR(0) |
4842                      WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4843         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
4844                      mem_win2_base | BIR(0) |
4845                      WINDOW(ilog2(mem_win2_aperture) - 10));
4846         t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
4847 }
4848
4849 static void setup_memwin_rdma(struct adapter *adap)
4850 {
4851         if (adap->vres.ocq.size) {
4852                 u32 start;
4853                 unsigned int sz_kb;
4854
4855                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4856                 start &= PCI_BASE_ADDRESS_MEM_MASK;
4857                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4858                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4859                 t4_write_reg(adap,
4860                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4861                              start | BIR(1) | WINDOW(ilog2(sz_kb)));
4862                 t4_write_reg(adap,
4863                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4864                              adap->vres.ocq.start);
4865                 t4_read_reg(adap,
4866                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4867         }
4868 }
4869
4870 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4871 {
4872         u32 v;
4873         int ret;
4874
4875         /* get device capabilities */
4876         memset(c, 0, sizeof(*c));
4877         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4878                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
4879         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
4880         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
4881         if (ret < 0)
4882                 return ret;
4883
4884         /* select capabilities we'll be using */
4885         if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4886                 if (!vf_acls)
4887                         c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4888                 else
4889                         c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4890         } else if (vf_acls) {
4891                 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4892                 return ret;
4893         }
4894         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4895                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4896         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
4897         if (ret < 0)
4898                 return ret;
4899
4900         ret = t4_config_glbl_rss(adap, adap->fn,
4901                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4902                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
4903                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
4904         if (ret < 0)
4905                 return ret;
4906
4907         ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4908                           0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
4909         if (ret < 0)
4910                 return ret;
4911
4912         t4_sge_init(adap);
4913
4914         /* tweak some settings */
4915         t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
4916         t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4917         t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
4918         v = t4_read_reg(adap, TP_PIO_DATA);
4919         t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
4920
4921         /* first 4 Tx modulation queues point to consecutive Tx channels */
4922         adap->params.tp.tx_modq_map = 0xE4;
4923         t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
4924                      V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
4925
4926         /* associate each Tx modulation queue with consecutive Tx channels */
4927         v = 0x84218421;
4928         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4929                           &v, 1, A_TP_TX_SCHED_HDR);
4930         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4931                           &v, 1, A_TP_TX_SCHED_FIFO);
4932         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4933                           &v, 1, A_TP_TX_SCHED_PCMD);
4934
4935 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4936         if (is_offload(adap)) {
4937                 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
4938                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4939                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4940                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4941                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4942                 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
4943                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4944                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4945                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4946                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4947         }
4948
4949         /* get basic stuff going */
4950         return t4_early_init(adap, adap->fn);
4951 }
4952
4953 /*
4954  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
4955  */
4956 #define MAX_ATIDS 8192U
4957
4958 /*
4959  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4960  *
4961  * If the firmware we're dealing with has Configuration File support, then
4962  * we use that to perform all configuration
4963  */
4964
4965 /*
4966  * Tweak configuration based on module parameters, etc.  Most of these have
4967  * defaults assigned to them by Firmware Configuration Files (if we're using
4968  * them) but need to be explicitly set if we're using hard-coded
4969  * initialization.  But even in the case of using Firmware Configuration
4970  * Files, we'd like to expose the ability to change these via module
4971  * parameters so these are essentially common tweaks/settings for
4972  * Configuration Files and hard-coded initialization ...
4973  */
4974 static int adap_init0_tweaks(struct adapter *adapter)
4975 {
4976         /*
4977          * Fix up various Host-Dependent Parameters like Page Size, Cache
4978          * Line Size, etc.  The firmware default is for a 4KB Page Size and
4979          * 64B Cache Line Size ...
4980          */
4981         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4982
4983         /*
4984          * Process module parameters which affect early initialization.
4985          */
4986         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
4987                 dev_err(&adapter->pdev->dev,
4988                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
4989                         rx_dma_offset);
4990                 rx_dma_offset = 2;
4991         }
4992         t4_set_reg_field(adapter, SGE_CONTROL,
4993                          PKTSHIFT_MASK,
4994                          PKTSHIFT(rx_dma_offset));
4995
4996         /*
4997          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
4998          * adds the pseudo header itself.
4999          */
5000         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5001                                CSUM_HAS_PSEUDO_HDR, 0);
5002
5003         return 0;
5004 }
5005
5006 /*
5007  * Attempt to initialize the adapter via a Firmware Configuration File.
5008  */
5009 static int adap_init0_config(struct adapter *adapter, int reset)
5010 {
5011         struct fw_caps_config_cmd caps_cmd;
5012         const struct firmware *cf;
5013         unsigned long mtype = 0, maddr = 0;
5014         u32 finiver, finicsum, cfcsum;
5015         int ret;
5016         int config_issued = 0;
5017         char *fw_config_file, fw_config_file_path[256];
5018         char *config_name = NULL;
5019
5020         /*
5021          * Reset device if necessary.
5022          */
5023         if (reset) {
5024                 ret = t4_fw_reset(adapter, adapter->mbox,
5025                                   PIORSTMODE | PIORST);
5026                 if (ret < 0)
5027                         goto bye;
5028         }
5029
5030         /*
5031          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5032          * then use that.  Otherwise, use the configuration file stored
5033          * in the adapter flash ...
5034          */
5035         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
5036         case CHELSIO_T4:
5037                 fw_config_file = FW4_CFNAME;
5038                 break;
5039         case CHELSIO_T5:
5040                 fw_config_file = FW5_CFNAME;
5041                 break;
5042         default:
5043                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5044                        adapter->pdev->device);
5045                 ret = -EINVAL;
5046                 goto bye;
5047         }
5048
5049         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
5050         if (ret < 0) {
5051                 config_name = "On FLASH";
5052                 mtype = FW_MEMTYPE_CF_FLASH;
5053                 maddr = t4_flash_cfg_addr(adapter);
5054         } else {
5055                 u32 params[7], val[7];
5056
5057                 sprintf(fw_config_file_path,
5058                         "/lib/firmware/%s", fw_config_file);
5059                 config_name = fw_config_file_path;
5060
5061                 if (cf->size >= FLASH_CFG_MAX_SIZE)
5062                         ret = -ENOMEM;
5063                 else {
5064                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5065                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
5066                         ret = t4_query_params(adapter, adapter->mbox,
5067                                               adapter->fn, 0, 1, params, val);
5068                         if (ret == 0) {
5069                                 /*
5070                                  * For t4_memory_rw() below addresses and
5071                                  * sizes have to be in terms of multiples of 4
5072                                  * bytes.  So, if the Configuration File isn't
5073                                  * a multiple of 4 bytes in length we'll have
5074                                  * to write that out separately since we can't
5075                                  * guarantee that the bytes following the
5076                                  * residual byte in the buffer returned by
5077                                  * request_firmware() are zeroed out ...
5078                                  */
5079                                 size_t resid = cf->size & 0x3;
5080                                 size_t size = cf->size & ~0x3;
5081                                 __be32 *data = (__be32 *)cf->data;
5082
5083                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
5084                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
5085
5086                                 spin_lock(&adapter->win0_lock);
5087                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5088                                                    size, data, T4_MEMORY_WRITE);
5089                                 if (ret == 0 && resid != 0) {
5090                                         union {
5091                                                 __be32 word;
5092                                                 char buf[4];
5093                                         } last;
5094                                         int i;
5095
5096                                         last.word = data[size >> 2];
5097                                         for (i = resid; i < 4; i++)
5098                                                 last.buf[i] = 0;
5099                                         ret = t4_memory_rw(adapter, 0, mtype,
5100                                                            maddr + size,
5101                                                            4, &last.word,
5102                                                            T4_MEMORY_WRITE);
5103                                 }
5104                                 spin_unlock(&adapter->win0_lock);
5105                         }
5106                 }
5107
5108                 release_firmware(cf);
5109                 if (ret)
5110                         goto bye;
5111         }
5112
5113         /*
5114          * Issue a Capability Configuration command to the firmware to get it
5115          * to parse the Configuration File.  We don't use t4_fw_config_file()
5116          * because we want the ability to modify various features after we've
5117          * processed the configuration file ...
5118          */
5119         memset(&caps_cmd, 0, sizeof(caps_cmd));
5120         caps_cmd.op_to_write =
5121                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5122                       FW_CMD_REQUEST_F |
5123                       FW_CMD_READ_F);
5124         caps_cmd.cfvalid_to_len16 =
5125                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
5126                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
5127                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
5128                       FW_LEN16(caps_cmd));
5129         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5130                          &caps_cmd);
5131
5132         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5133          * Configuration File in FLASH), our last gasp effort is to use the
5134          * Firmware Configuration File which is embedded in the firmware.  A
5135          * very few early versions of the firmware didn't have one embedded
5136          * but we can ignore those.
5137          */
5138         if (ret == -ENOENT) {
5139                 memset(&caps_cmd, 0, sizeof(caps_cmd));
5140                 caps_cmd.op_to_write =
5141                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5142                                         FW_CMD_REQUEST_F |
5143                                         FW_CMD_READ_F);
5144                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5145                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5146                                 sizeof(caps_cmd), &caps_cmd);
5147                 config_name = "Firmware Default";
5148         }
5149
5150         config_issued = 1;
5151         if (ret < 0)
5152                 goto bye;
5153
5154         finiver = ntohl(caps_cmd.finiver);
5155         finicsum = ntohl(caps_cmd.finicsum);
5156         cfcsum = ntohl(caps_cmd.cfcsum);
5157         if (finicsum != cfcsum)
5158                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5159                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5160                          finicsum, cfcsum);
5161
5162         /*
5163          * And now tell the firmware to use the configuration we just loaded.
5164          */
5165         caps_cmd.op_to_write =
5166                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5167                       FW_CMD_REQUEST_F |
5168                       FW_CMD_WRITE_F);
5169         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5170         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5171                          NULL);
5172         if (ret < 0)
5173                 goto bye;
5174
5175         /*
5176          * Tweak configuration based on system architecture, module
5177          * parameters, etc.
5178          */
5179         ret = adap_init0_tweaks(adapter);
5180         if (ret < 0)
5181                 goto bye;
5182
5183         /*
5184          * And finally tell the firmware to initialize itself using the
5185          * parameters from the Configuration File.
5186          */
5187         ret = t4_fw_initialize(adapter, adapter->mbox);
5188         if (ret < 0)
5189                 goto bye;
5190
5191         /*
5192          * Return successfully and note that we're operating with parameters
5193          * not supplied by the driver, rather than from hard-wired
5194          * initialization constants burried in the driver.
5195          */
5196         adapter->flags |= USING_SOFT_PARAMS;
5197         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
5198                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5199                  config_name, finiver, cfcsum);
5200         return 0;
5201
5202         /*
5203          * Something bad happened.  Return the error ...  (If the "error"
5204          * is that there's no Configuration File on the adapter we don't
5205          * want to issue a warning since this is fairly common.)
5206          */
5207 bye:
5208         if (config_issued && ret != -ENOENT)
5209                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5210                          config_name, -ret);
5211         return ret;
5212 }
5213
5214 /*
5215  * Attempt to initialize the adapter via hard-coded, driver supplied
5216  * parameters ...
5217  */
5218 static int adap_init0_no_config(struct adapter *adapter, int reset)
5219 {
5220         struct sge *s = &adapter->sge;
5221         struct fw_caps_config_cmd caps_cmd;
5222         u32 v;
5223         int i, ret;
5224
5225         /*
5226          * Reset device if necessary
5227          */
5228         if (reset) {
5229                 ret = t4_fw_reset(adapter, adapter->mbox,
5230                                   PIORSTMODE | PIORST);
5231                 if (ret < 0)
5232                         goto bye;
5233         }
5234
5235         /*
5236          * Get device capabilities and select which we'll be using.
5237          */
5238         memset(&caps_cmd, 0, sizeof(caps_cmd));
5239         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5240                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
5241         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5242         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5243                          &caps_cmd);
5244         if (ret < 0)
5245                 goto bye;
5246
5247         if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5248                 if (!vf_acls)
5249                         caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5250                 else
5251                         caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5252         } else if (vf_acls) {
5253                 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5254                 goto bye;
5255         }
5256         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5257                               FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5258         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5259                          NULL);
5260         if (ret < 0)
5261                 goto bye;
5262
5263         /*
5264          * Tweak configuration based on system architecture, module
5265          * parameters, etc.
5266          */
5267         ret = adap_init0_tweaks(adapter);
5268         if (ret < 0)
5269                 goto bye;
5270
5271         /*
5272          * Select RSS Global Mode we want to use.  We use "Basic Virtual"
5273          * mode which maps each Virtual Interface to its own section of
5274          * the RSS Table and we turn on all map and hash enables ...
5275          */
5276         adapter->flags |= RSS_TNLALLLOOKUP;
5277         ret = t4_config_glbl_rss(adapter, adapter->mbox,
5278                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5279                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
5280                                  FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F |
5281                                  ((adapter->flags & RSS_TNLALLLOOKUP) ?
5282                                         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F : 0));
5283         if (ret < 0)
5284                 goto bye;
5285
5286         /*
5287          * Set up our own fundamental resource provisioning ...
5288          */
5289         ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5290                           PFRES_NEQ, PFRES_NETHCTRL,
5291                           PFRES_NIQFLINT, PFRES_NIQ,
5292                           PFRES_TC, PFRES_NVI,
5293                           FW_PFVF_CMD_CMASK_M,
5294                           pfvfres_pmask(adapter, adapter->fn, 0),
5295                           PFRES_NEXACTF,
5296                           PFRES_R_CAPS, PFRES_WX_CAPS);
5297         if (ret < 0)
5298                 goto bye;
5299
5300         /*
5301          * Perform low level SGE initialization.  We need to do this before we
5302          * send the firmware the INITIALIZE command because that will cause
5303          * any other PF Drivers which are waiting for the Master
5304          * Initialization to proceed forward.
5305          */
5306         for (i = 0; i < SGE_NTIMERS - 1; i++)
5307                 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5308         s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5309         s->counter_val[0] = 1;
5310         for (i = 1; i < SGE_NCOUNTERS; i++)
5311                 s->counter_val[i] = min(intr_cnt[i - 1],
5312                                         THRESHOLD_0_GET(THRESHOLD_0_MASK));
5313         t4_sge_init(adapter);
5314
5315 #ifdef CONFIG_PCI_IOV
5316         /*
5317          * Provision resource limits for Virtual Functions.  We currently
5318          * grant them all the same static resource limits except for the Port
5319          * Access Rights Mask which we're assigning based on the PF.  All of
5320          * the static provisioning stuff for both the PF and VF really needs
5321          * to be managed in a persistent manner for each device which the
5322          * firmware controls.
5323          */
5324         {
5325                 int pf, vf;
5326
5327                 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
5328                         if (num_vf[pf] <= 0)
5329                                 continue;
5330
5331                         /* VF numbering starts at 1! */
5332                         for (vf = 1; vf <= num_vf[pf]; vf++) {
5333                                 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5334                                                   pf, vf,
5335                                                   VFRES_NEQ, VFRES_NETHCTRL,
5336                                                   VFRES_NIQFLINT, VFRES_NIQ,
5337                                                   VFRES_TC, VFRES_NVI,
5338                                                   FW_PFVF_CMD_CMASK_M,
5339                                                   pfvfres_pmask(
5340                                                   adapter, pf, vf),
5341                                                   VFRES_NEXACTF,
5342                                                   VFRES_R_CAPS, VFRES_WX_CAPS);
5343                                 if (ret < 0)
5344                                         dev_warn(adapter->pdev_dev,
5345                                                  "failed to "\
5346                                                  "provision pf/vf=%d/%d; "
5347                                                  "err=%d\n", pf, vf, ret);
5348                         }
5349                 }
5350         }
5351 #endif
5352
5353         /*
5354          * Set up the default filter mode.  Later we'll want to implement this
5355          * via a firmware command, etc. ...  This needs to be done before the
5356          * firmare initialization command ...  If the selected set of fields
5357          * isn't equal to the default value, we'll need to make sure that the
5358          * field selections will fit in the 36-bit budget.
5359          */
5360         if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
5361                 int j, bits = 0;
5362
5363                 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5364                         switch (tp_vlan_pri_map & (1 << j)) {
5365                         case 0:
5366                                 /* compressed filter field not enabled */
5367                                 break;
5368                         case FCOE_MASK:
5369                                 bits +=  1;
5370                                 break;
5371                         case PORT_MASK:
5372                                 bits +=  3;
5373                                 break;
5374                         case VNIC_ID_MASK:
5375                                 bits += 17;
5376                                 break;
5377                         case VLAN_MASK:
5378                                 bits += 17;
5379                                 break;
5380                         case TOS_MASK:
5381                                 bits +=  8;
5382                                 break;
5383                         case PROTOCOL_MASK:
5384                                 bits +=  8;
5385                                 break;
5386                         case ETHERTYPE_MASK:
5387                                 bits += 16;
5388                                 break;
5389                         case MACMATCH_MASK:
5390                                 bits +=  9;
5391                                 break;
5392                         case MPSHITTYPE_MASK:
5393                                 bits +=  3;
5394                                 break;
5395                         case FRAGMENTATION_MASK:
5396                                 bits +=  1;
5397                                 break;
5398                         }
5399
5400                 if (bits > 36) {
5401                         dev_err(adapter->pdev_dev,
5402                                 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5403                                 " using %#x\n", tp_vlan_pri_map, bits,
5404                                 TP_VLAN_PRI_MAP_DEFAULT);
5405                         tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5406                 }
5407         }
5408         v = tp_vlan_pri_map;
5409         t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5410                           &v, 1, TP_VLAN_PRI_MAP);
5411
5412         /*
5413          * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5414          * to support any of the compressed filter fields above.  Newer
5415          * versions of the firmware do this automatically but it doesn't hurt
5416          * to set it here.  Meanwhile, we do _not_ need to set Lookup Every
5417          * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5418          * since the firmware automatically turns this on and off when we have
5419          * a non-zero number of filters active (since it does have a
5420          * performance impact).
5421          */
5422         if (tp_vlan_pri_map)
5423                 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5424                                  FIVETUPLELOOKUP_MASK,
5425                                  FIVETUPLELOOKUP_MASK);
5426
5427         /*
5428          * Tweak some settings.
5429          */
5430         t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5431                      RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5432                      PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5433                      KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5434
5435         /*
5436          * Get basic stuff going by issuing the Firmware Initialize command.
5437          * Note that this _must_ be after all PFVF commands ...
5438          */
5439         ret = t4_fw_initialize(adapter, adapter->mbox);
5440         if (ret < 0)
5441                 goto bye;
5442
5443         /*
5444          * Return successfully!
5445          */
5446         dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5447                  "driver parameters\n");
5448         return 0;
5449
5450         /*
5451          * Something bad happened.  Return the error ...
5452          */
5453 bye:
5454         return ret;
5455 }
5456
5457 static struct fw_info fw_info_array[] = {
5458         {
5459                 .chip = CHELSIO_T4,
5460                 .fs_name = FW4_CFNAME,
5461                 .fw_mod_name = FW4_FNAME,
5462                 .fw_hdr = {
5463                         .chip = FW_HDR_CHIP_T4,
5464                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5465                         .intfver_nic = FW_INTFVER(T4, NIC),
5466                         .intfver_vnic = FW_INTFVER(T4, VNIC),
5467                         .intfver_ri = FW_INTFVER(T4, RI),
5468                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5469                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
5470                 },
5471         }, {
5472                 .chip = CHELSIO_T5,
5473                 .fs_name = FW5_CFNAME,
5474                 .fw_mod_name = FW5_FNAME,
5475                 .fw_hdr = {
5476                         .chip = FW_HDR_CHIP_T5,
5477                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5478                         .intfver_nic = FW_INTFVER(T5, NIC),
5479                         .intfver_vnic = FW_INTFVER(T5, VNIC),
5480                         .intfver_ri = FW_INTFVER(T5, RI),
5481                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5482                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
5483                 },
5484         }
5485 };
5486
5487 static struct fw_info *find_fw_info(int chip)
5488 {
5489         int i;
5490
5491         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5492                 if (fw_info_array[i].chip == chip)
5493                         return &fw_info_array[i];
5494         }
5495         return NULL;
5496 }
5497
5498 /*
5499  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5500  */
5501 static int adap_init0(struct adapter *adap)
5502 {
5503         int ret;
5504         u32 v, port_vec;
5505         enum dev_state state;
5506         u32 params[7], val[7];
5507         struct fw_caps_config_cmd caps_cmd;
5508         int reset = 1;
5509
5510         /*
5511          * Contact FW, advertising Master capability (and potentially forcing
5512          * ourselves as the Master PF if our module parameter force_init is
5513          * set).
5514          */
5515         ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5516                           force_init ? MASTER_MUST : MASTER_MAY,
5517                           &state);
5518         if (ret < 0) {
5519                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5520                         ret);
5521                 return ret;
5522         }
5523         if (ret == adap->mbox)
5524                 adap->flags |= MASTER_PF;
5525         if (force_init && state == DEV_STATE_INIT)
5526                 state = DEV_STATE_UNINIT;
5527
5528         /*
5529          * If we're the Master PF Driver and the device is uninitialized,
5530          * then let's consider upgrading the firmware ...  (We always want
5531          * to check the firmware version number in order to A. get it for
5532          * later reporting and B. to warn if the currently loaded firmware
5533          * is excessively mismatched relative to the driver.)
5534          */
5535         t4_get_fw_version(adap, &adap->params.fw_vers);
5536         t4_get_tp_version(adap, &adap->params.tp_vers);
5537         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
5538                 struct fw_info *fw_info;
5539                 struct fw_hdr *card_fw;
5540                 const struct firmware *fw;
5541                 const u8 *fw_data = NULL;
5542                 unsigned int fw_size = 0;
5543
5544                 /* This is the firmware whose headers the driver was compiled
5545                  * against
5546                  */
5547                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5548                 if (fw_info == NULL) {
5549                         dev_err(adap->pdev_dev,
5550                                 "unable to get firmware info for chip %d.\n",
5551                                 CHELSIO_CHIP_VERSION(adap->params.chip));
5552                         return -EINVAL;
5553                 }
5554
5555                 /* allocate memory to read the header of the firmware on the
5556                  * card
5557                  */
5558                 card_fw = t4_alloc_mem(sizeof(*card_fw));
5559
5560                 /* Get FW from from /lib/firmware/ */
5561                 ret = request_firmware(&fw, fw_info->fw_mod_name,
5562                                        adap->pdev_dev);
5563                 if (ret < 0) {
5564                         dev_err(adap->pdev_dev,
5565                                 "unable to load firmware image %s, error %d\n",
5566                                 fw_info->fw_mod_name, ret);
5567                 } else {
5568                         fw_data = fw->data;
5569                         fw_size = fw->size;
5570                 }
5571
5572                 /* upgrade FW logic */
5573                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5574                                  state, &reset);
5575
5576                 /* Cleaning up */
5577                 if (fw != NULL)
5578                         release_firmware(fw);
5579                 t4_free_mem(card_fw);
5580
5581                 if (ret < 0)
5582                         goto bye;
5583         }
5584
5585         /*
5586          * Grab VPD parameters.  This should be done after we establish a
5587          * connection to the firmware since some of the VPD parameters
5588          * (notably the Core Clock frequency) are retrieved via requests to
5589          * the firmware.  On the other hand, we need these fairly early on
5590          * so we do this right after getting ahold of the firmware.
5591          */
5592         ret = get_vpd_params(adap, &adap->params.vpd);
5593         if (ret < 0)
5594                 goto bye;
5595
5596         /*
5597          * Find out what ports are available to us.  Note that we need to do
5598          * this before calling adap_init0_no_config() since it needs nports
5599          * and portvec ...
5600          */
5601         v =
5602             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5603             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
5604         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
5605         if (ret < 0)
5606                 goto bye;
5607
5608         adap->params.nports = hweight32(port_vec);
5609         adap->params.portvec = port_vec;
5610
5611         /*
5612          * If the firmware is initialized already (and we're not forcing a
5613          * master initialization), note that we're living with existing
5614          * adapter parameters.  Otherwise, it's time to try initializing the
5615          * adapter ...
5616          */
5617         if (state == DEV_STATE_INIT) {
5618                 dev_info(adap->pdev_dev, "Coming up as %s: "\
5619                          "Adapter already initialized\n",
5620                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5621                 adap->flags |= USING_SOFT_PARAMS;
5622         } else {
5623                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5624                          "Initializing adapter\n");
5625                 /*
5626                  * If the firmware doesn't support Configuration
5627                  * Files warn user and exit,
5628                  */
5629                 if (ret < 0)
5630                         dev_warn(adap->pdev_dev, "Firmware doesn't support "
5631                                  "configuration file.\n");
5632                 if (force_old_init)
5633                         ret = adap_init0_no_config(adap, reset);
5634                 else {
5635                         /*
5636                          * Find out whether we're dealing with a version of
5637                          * the firmware which has configuration file support.
5638                          */
5639                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5640                                      FW_PARAMS_PARAM_X_V(
5641                                              FW_PARAMS_PARAM_DEV_CF));
5642                         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5643                                               params, val);
5644
5645                         /*
5646                          * If the firmware doesn't support Configuration
5647                          * Files, use the old Driver-based, hard-wired
5648                          * initialization.  Otherwise, try using the
5649                          * Configuration File support and fall back to the
5650                          * Driver-based initialization if there's no
5651                          * Configuration File found.
5652                          */
5653                         if (ret < 0)
5654                                 ret = adap_init0_no_config(adap, reset);
5655                         else {
5656                                 /*
5657                                  * The firmware provides us with a memory
5658                                  * buffer where we can load a Configuration
5659                                  * File from the host if we want to override
5660                                  * the Configuration File in flash.
5661                                  */
5662
5663                                 ret = adap_init0_config(adap, reset);
5664                                 if (ret == -ENOENT) {
5665                                         dev_info(adap->pdev_dev,
5666                                             "No Configuration File present "
5667                                             "on adapter. Using hard-wired "
5668                                             "configuration parameters.\n");
5669                                         ret = adap_init0_no_config(adap, reset);
5670                                 }
5671                         }
5672                 }
5673                 if (ret < 0) {
5674                         dev_err(adap->pdev_dev,
5675                                 "could not initialize adapter, error %d\n",
5676                                 -ret);
5677                         goto bye;
5678                 }
5679         }
5680
5681         /*
5682          * If we're living with non-hard-coded parameters (either from a
5683          * Firmware Configuration File or values programmed by a different PF
5684          * Driver), give the SGE code a chance to pull in anything that it
5685          * needs ...  Note that this must be called after we retrieve our VPD
5686          * parameters in order to know how to convert core ticks to seconds.
5687          */
5688         if (adap->flags & USING_SOFT_PARAMS) {
5689                 ret = t4_sge_init(adap);
5690                 if (ret < 0)
5691                         goto bye;
5692         }
5693
5694         if (is_bypass_device(adap->pdev->device))
5695                 adap->params.bypass = 1;
5696
5697         /*
5698          * Grab some of our basic fundamental operating parameters.
5699          */
5700 #define FW_PARAM_DEV(param) \
5701         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
5702         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
5703
5704 #define FW_PARAM_PFVF(param) \
5705         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
5706         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
5707         FW_PARAMS_PARAM_Y_V(0) | \
5708         FW_PARAMS_PARAM_Z_V(0)
5709
5710         params[0] = FW_PARAM_PFVF(EQ_START);
5711         params[1] = FW_PARAM_PFVF(L2T_START);
5712         params[2] = FW_PARAM_PFVF(L2T_END);
5713         params[3] = FW_PARAM_PFVF(FILTER_START);
5714         params[4] = FW_PARAM_PFVF(FILTER_END);
5715         params[5] = FW_PARAM_PFVF(IQFLINT_START);
5716         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
5717         if (ret < 0)
5718                 goto bye;
5719         adap->sge.egr_start = val[0];
5720         adap->l2t_start = val[1];
5721         adap->l2t_end = val[2];
5722         adap->tids.ftid_base = val[3];
5723         adap->tids.nftids = val[4] - val[3] + 1;
5724         adap->sge.ingr_start = val[5];
5725
5726         /* query params related to active filter region */
5727         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5728         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5729         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5730         /* If Active filter size is set we enable establishing
5731          * offload connection through firmware work request
5732          */
5733         if ((val[0] != val[1]) && (ret >= 0)) {
5734                 adap->flags |= FW_OFLD_CONN;
5735                 adap->tids.aftid_base = val[0];
5736                 adap->tids.aftid_end = val[1];
5737         }
5738
5739         /* If we're running on newer firmware, let it know that we're
5740          * prepared to deal with encapsulated CPL messages.  Older
5741          * firmware won't understand this and we'll just get
5742          * unencapsulated messages ...
5743          */
5744         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5745         val[0] = 1;
5746         (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5747
5748         /*
5749          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5750          * capability.  Earlier versions of the firmware didn't have the
5751          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5752          * permission to use ULPTX MEMWRITE DSGL.
5753          */
5754         if (is_t4(adap->params.chip)) {
5755                 adap->params.ulptx_memwrite_dsgl = false;
5756         } else {
5757                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5758                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5759                                       1, params, val);
5760                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5761         }
5762
5763         /*
5764          * Get device capabilities so we can determine what resources we need
5765          * to manage.
5766          */
5767         memset(&caps_cmd, 0, sizeof(caps_cmd));
5768         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5769                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
5770         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5771         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5772                          &caps_cmd);
5773         if (ret < 0)
5774                 goto bye;
5775
5776         if (caps_cmd.ofldcaps) {
5777                 /* query offload-related parameters */
5778                 params[0] = FW_PARAM_DEV(NTID);
5779                 params[1] = FW_PARAM_PFVF(SERVER_START);
5780                 params[2] = FW_PARAM_PFVF(SERVER_END);
5781                 params[3] = FW_PARAM_PFVF(TDDP_START);
5782                 params[4] = FW_PARAM_PFVF(TDDP_END);
5783                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5784                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5785                                       params, val);
5786                 if (ret < 0)
5787                         goto bye;
5788                 adap->tids.ntids = val[0];
5789                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5790                 adap->tids.stid_base = val[1];
5791                 adap->tids.nstids = val[2] - val[1] + 1;
5792                 /*
5793                  * Setup server filter region. Divide the availble filter
5794                  * region into two parts. Regular filters get 1/3rd and server
5795                  * filters get 2/3rd part. This is only enabled if workarond
5796                  * path is enabled.
5797                  * 1. For regular filters.
5798                  * 2. Server filter: This are special filters which are used
5799                  * to redirect SYN packets to offload queue.
5800                  */
5801                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5802                         adap->tids.sftid_base = adap->tids.ftid_base +
5803                                         DIV_ROUND_UP(adap->tids.nftids, 3);
5804                         adap->tids.nsftids = adap->tids.nftids -
5805                                          DIV_ROUND_UP(adap->tids.nftids, 3);
5806                         adap->tids.nftids = adap->tids.sftid_base -
5807                                                 adap->tids.ftid_base;
5808                 }
5809                 adap->vres.ddp.start = val[3];
5810                 adap->vres.ddp.size = val[4] - val[3] + 1;
5811                 adap->params.ofldq_wr_cred = val[5];
5812
5813                 adap->params.offload = 1;
5814         }
5815         if (caps_cmd.rdmacaps) {
5816                 params[0] = FW_PARAM_PFVF(STAG_START);
5817                 params[1] = FW_PARAM_PFVF(STAG_END);
5818                 params[2] = FW_PARAM_PFVF(RQ_START);
5819                 params[3] = FW_PARAM_PFVF(RQ_END);
5820                 params[4] = FW_PARAM_PFVF(PBL_START);
5821                 params[5] = FW_PARAM_PFVF(PBL_END);
5822                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5823                                       params, val);
5824                 if (ret < 0)
5825                         goto bye;
5826                 adap->vres.stag.start = val[0];
5827                 adap->vres.stag.size = val[1] - val[0] + 1;
5828                 adap->vres.rq.start = val[2];
5829                 adap->vres.rq.size = val[3] - val[2] + 1;
5830                 adap->vres.pbl.start = val[4];
5831                 adap->vres.pbl.size = val[5] - val[4] + 1;
5832
5833                 params[0] = FW_PARAM_PFVF(SQRQ_START);
5834                 params[1] = FW_PARAM_PFVF(SQRQ_END);
5835                 params[2] = FW_PARAM_PFVF(CQ_START);
5836                 params[3] = FW_PARAM_PFVF(CQ_END);
5837                 params[4] = FW_PARAM_PFVF(OCQ_START);
5838                 params[5] = FW_PARAM_PFVF(OCQ_END);
5839                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
5840                                       val);
5841                 if (ret < 0)
5842                         goto bye;
5843                 adap->vres.qp.start = val[0];
5844                 adap->vres.qp.size = val[1] - val[0] + 1;
5845                 adap->vres.cq.start = val[2];
5846                 adap->vres.cq.size = val[3] - val[2] + 1;
5847                 adap->vres.ocq.start = val[4];
5848                 adap->vres.ocq.size = val[5] - val[4] + 1;
5849
5850                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5851                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5852                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
5853                                       val);
5854                 if (ret < 0) {
5855                         adap->params.max_ordird_qp = 8;
5856                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5857                         ret = 0;
5858                 } else {
5859                         adap->params.max_ordird_qp = val[0];
5860                         adap->params.max_ird_adapter = val[1];
5861                 }
5862                 dev_info(adap->pdev_dev,
5863                          "max_ordird_qp %d max_ird_adapter %d\n",
5864                          adap->params.max_ordird_qp,
5865                          adap->params.max_ird_adapter);
5866         }
5867         if (caps_cmd.iscsicaps) {
5868                 params[0] = FW_PARAM_PFVF(ISCSI_START);
5869                 params[1] = FW_PARAM_PFVF(ISCSI_END);
5870                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5871                                       params, val);
5872                 if (ret < 0)
5873                         goto bye;
5874                 adap->vres.iscsi.start = val[0];
5875                 adap->vres.iscsi.size = val[1] - val[0] + 1;
5876         }
5877 #undef FW_PARAM_PFVF
5878 #undef FW_PARAM_DEV
5879
5880         /* The MTU/MSS Table is initialized by now, so load their values.  If
5881          * we're initializing the adapter, then we'll make any modifications
5882          * we want to the MTU/MSS Table and also initialize the congestion
5883          * parameters.
5884          */
5885         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5886         if (state != DEV_STATE_INIT) {
5887                 int i;
5888
5889                 /* The default MTU Table contains values 1492 and 1500.
5890                  * However, for TCP, it's better to have two values which are
5891                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5892                  * This allows us to have a TCP Data Payload which is a
5893                  * multiple of 8 regardless of what combination of TCP Options
5894                  * are in use (always a multiple of 4 bytes) which is
5895                  * important for performance reasons.  For instance, if no
5896                  * options are in use, then we have a 20-byte IP header and a
5897                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
5898                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5899                  * which is not a multiple of 8.  So using an MSS of 1488 in
5900                  * this case results in a TCP Data Payload of 1448 bytes which
5901                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
5902                  * Stamps have been negotiated, then an MTU of 1500 bytes
5903                  * results in a TCP Data Payload of 1448 bytes which, as
5904                  * above, is a multiple of 8 bytes ...
5905                  */
5906                 for (i = 0; i < NMTUS; i++)
5907                         if (adap->params.mtus[i] == 1492) {
5908                                 adap->params.mtus[i] = 1488;
5909                                 break;
5910                         }
5911
5912                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5913                              adap->params.b_wnd);
5914         }
5915         t4_init_tp_params(adap);
5916         adap->flags |= FW_OK;
5917         return 0;
5918
5919         /*
5920          * Something bad happened.  If a command timed out or failed with EIO
5921          * FW does not operate within its spec or something catastrophic
5922          * happened to HW/FW, stop issuing commands.
5923          */
5924 bye:
5925         if (ret != -ETIMEDOUT && ret != -EIO)
5926                 t4_fw_bye(adap, adap->mbox);
5927         return ret;
5928 }
5929
5930 /* EEH callbacks */
5931
5932 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5933                                          pci_channel_state_t state)
5934 {
5935         int i;
5936         struct adapter *adap = pci_get_drvdata(pdev);
5937
5938         if (!adap)
5939                 goto out;
5940
5941         rtnl_lock();
5942         adap->flags &= ~FW_OK;
5943         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5944         spin_lock(&adap->stats_lock);
5945         for_each_port(adap, i) {
5946                 struct net_device *dev = adap->port[i];
5947
5948                 netif_device_detach(dev);
5949                 netif_carrier_off(dev);
5950         }
5951         spin_unlock(&adap->stats_lock);
5952         if (adap->flags & FULL_INIT_DONE)
5953                 cxgb_down(adap);
5954         rtnl_unlock();
5955         if ((adap->flags & DEV_ENABLED)) {
5956                 pci_disable_device(pdev);
5957                 adap->flags &= ~DEV_ENABLED;
5958         }
5959 out:    return state == pci_channel_io_perm_failure ?
5960                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5961 }
5962
5963 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5964 {
5965         int i, ret;
5966         struct fw_caps_config_cmd c;
5967         struct adapter *adap = pci_get_drvdata(pdev);
5968
5969         if (!adap) {
5970                 pci_restore_state(pdev);
5971                 pci_save_state(pdev);
5972                 return PCI_ERS_RESULT_RECOVERED;
5973         }
5974
5975         if (!(adap->flags & DEV_ENABLED)) {
5976                 if (pci_enable_device(pdev)) {
5977                         dev_err(&pdev->dev, "Cannot reenable PCI "
5978                                             "device after reset\n");
5979                         return PCI_ERS_RESULT_DISCONNECT;
5980                 }
5981                 adap->flags |= DEV_ENABLED;
5982         }
5983
5984         pci_set_master(pdev);
5985         pci_restore_state(pdev);
5986         pci_save_state(pdev);
5987         pci_cleanup_aer_uncorrect_error_status(pdev);
5988
5989         if (t4_wait_dev_ready(adap->regs) < 0)
5990                 return PCI_ERS_RESULT_DISCONNECT;
5991         if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
5992                 return PCI_ERS_RESULT_DISCONNECT;
5993         adap->flags |= FW_OK;
5994         if (adap_init1(adap, &c))
5995                 return PCI_ERS_RESULT_DISCONNECT;
5996
5997         for_each_port(adap, i) {
5998                 struct port_info *p = adap2pinfo(adap, i);
5999
6000                 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6001                                   NULL, NULL);
6002                 if (ret < 0)
6003                         return PCI_ERS_RESULT_DISCONNECT;
6004                 p->viid = ret;
6005                 p->xact_addr_filt = -1;
6006         }
6007
6008         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6009                      adap->params.b_wnd);
6010         setup_memwin(adap);
6011         if (cxgb_up(adap))
6012                 return PCI_ERS_RESULT_DISCONNECT;
6013         return PCI_ERS_RESULT_RECOVERED;
6014 }
6015
6016 static void eeh_resume(struct pci_dev *pdev)
6017 {
6018         int i;
6019         struct adapter *adap = pci_get_drvdata(pdev);
6020
6021         if (!adap)
6022                 return;
6023
6024         rtnl_lock();
6025         for_each_port(adap, i) {
6026                 struct net_device *dev = adap->port[i];
6027
6028                 if (netif_running(dev)) {
6029                         link_start(dev);
6030                         cxgb_set_rxmode(dev);
6031                 }
6032                 netif_device_attach(dev);
6033         }
6034         rtnl_unlock();
6035 }
6036
6037 static const struct pci_error_handlers cxgb4_eeh = {
6038         .error_detected = eeh_err_detected,
6039         .slot_reset     = eeh_slot_reset,
6040         .resume         = eeh_resume,
6041 };
6042
6043 static inline bool is_x_10g_port(const struct link_config *lc)
6044 {
6045         return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6046                (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
6047 }
6048
6049 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6050                              unsigned int us, unsigned int cnt,
6051                              unsigned int size, unsigned int iqe_size)
6052 {
6053         q->adap = adap;
6054         set_rspq_intr_params(q, us, cnt);
6055         q->iqe_len = iqe_size;
6056         q->size = size;
6057 }
6058
6059 /*
6060  * Perform default configuration of DMA queues depending on the number and type
6061  * of ports we found and the number of available CPUs.  Most settings can be
6062  * modified by the admin prior to actual use.
6063  */
6064 static void cfg_queues(struct adapter *adap)
6065 {
6066         struct sge *s = &adap->sge;
6067         int i, n10g = 0, qidx = 0;
6068 #ifndef CONFIG_CHELSIO_T4_DCB
6069         int q10g = 0;
6070 #endif
6071         int ciq_size;
6072
6073         for_each_port(adap, i)
6074                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
6075 #ifdef CONFIG_CHELSIO_T4_DCB
6076         /* For Data Center Bridging support we need to be able to support up
6077          * to 8 Traffic Priorities; each of which will be assigned to its
6078          * own TX Queue in order to prevent Head-Of-Line Blocking.
6079          */
6080         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6081                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6082                         MAX_ETH_QSETS, adap->params.nports * 8);
6083                 BUG_ON(1);
6084         }
6085
6086         for_each_port(adap, i) {
6087                 struct port_info *pi = adap2pinfo(adap, i);
6088
6089                 pi->first_qset = qidx;
6090                 pi->nqsets = 8;
6091                 qidx += pi->nqsets;
6092         }
6093 #else /* !CONFIG_CHELSIO_T4_DCB */
6094         /*
6095          * We default to 1 queue per non-10G port and up to # of cores queues
6096          * per 10G port.
6097          */
6098         if (n10g)
6099                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
6100         if (q10g > netif_get_num_default_rss_queues())
6101                 q10g = netif_get_num_default_rss_queues();
6102
6103         for_each_port(adap, i) {
6104                 struct port_info *pi = adap2pinfo(adap, i);
6105
6106                 pi->first_qset = qidx;
6107                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
6108                 qidx += pi->nqsets;
6109         }
6110 #endif /* !CONFIG_CHELSIO_T4_DCB */
6111
6112         s->ethqsets = qidx;
6113         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
6114
6115         if (is_offload(adap)) {
6116                 /*
6117                  * For offload we use 1 queue/channel if all ports are up to 1G,
6118                  * otherwise we divide all available queues amongst the channels
6119                  * capped by the number of available cores.
6120                  */
6121                 if (n10g) {
6122                         i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6123                                   num_online_cpus());
6124                         s->ofldqsets = roundup(i, adap->params.nports);
6125                 } else
6126                         s->ofldqsets = adap->params.nports;
6127                 /* For RDMA one Rx queue per channel suffices */
6128                 s->rdmaqs = adap->params.nports;
6129                 s->rdmaciqs = adap->params.nports;
6130         }
6131
6132         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6133                 struct sge_eth_rxq *r = &s->ethrxq[i];
6134
6135                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
6136                 r->fl.size = 72;
6137         }
6138
6139         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6140                 s->ethtxq[i].q.size = 1024;
6141
6142         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6143                 s->ctrlq[i].q.size = 512;
6144
6145         for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6146                 s->ofldtxq[i].q.size = 1024;
6147
6148         for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6149                 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6150
6151                 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
6152                 r->rspq.uld = CXGB4_ULD_ISCSI;
6153                 r->fl.size = 72;
6154         }
6155
6156         for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6157                 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6158
6159                 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
6160                 r->rspq.uld = CXGB4_ULD_RDMA;
6161                 r->fl.size = 72;
6162         }
6163
6164         ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6165         if (ciq_size > SGE_MAX_IQ_SIZE) {
6166                 CH_WARN(adap, "CIQ size too small for available IQs\n");
6167                 ciq_size = SGE_MAX_IQ_SIZE;
6168         }
6169
6170         for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6171                 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6172
6173                 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
6174                 r->rspq.uld = CXGB4_ULD_RDMA;
6175         }
6176
6177         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6178         init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
6179 }
6180
6181 /*
6182  * Reduce the number of Ethernet queues across all ports to at most n.
6183  * n provides at least one queue per port.
6184  */
6185 static void reduce_ethqs(struct adapter *adap, int n)
6186 {
6187         int i;
6188         struct port_info *pi;
6189
6190         while (n < adap->sge.ethqsets)
6191                 for_each_port(adap, i) {
6192                         pi = adap2pinfo(adap, i);
6193                         if (pi->nqsets > 1) {
6194                                 pi->nqsets--;
6195                                 adap->sge.ethqsets--;
6196                                 if (adap->sge.ethqsets <= n)
6197                                         break;
6198                         }
6199                 }
6200
6201         n = 0;
6202         for_each_port(adap, i) {
6203                 pi = adap2pinfo(adap, i);
6204                 pi->first_qset = n;
6205                 n += pi->nqsets;
6206         }
6207 }
6208
6209 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6210 #define EXTRA_VECS 2
6211
6212 static int enable_msix(struct adapter *adap)
6213 {
6214         int ofld_need = 0;
6215         int i, want, need;
6216         struct sge *s = &adap->sge;
6217         unsigned int nchan = adap->params.nports;
6218         struct msix_entry entries[MAX_INGQ + 1];
6219
6220         for (i = 0; i < ARRAY_SIZE(entries); ++i)
6221                 entries[i].entry = i;
6222
6223         want = s->max_ethqsets + EXTRA_VECS;
6224         if (is_offload(adap)) {
6225                 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
6226                 /* need nchan for each possible ULD */
6227                 ofld_need = 3 * nchan;
6228         }
6229 #ifdef CONFIG_CHELSIO_T4_DCB
6230         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6231          * each port.
6232          */
6233         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6234 #else
6235         need = adap->params.nports + EXTRA_VECS + ofld_need;
6236 #endif
6237         want = pci_enable_msix_range(adap->pdev, entries, need, want);
6238         if (want < 0)
6239                 return want;
6240
6241         /*
6242          * Distribute available vectors to the various queue groups.
6243          * Every group gets its minimum requirement and NIC gets top
6244          * priority for leftovers.
6245          */
6246         i = want - EXTRA_VECS - ofld_need;
6247         if (i < s->max_ethqsets) {
6248                 s->max_ethqsets = i;
6249                 if (i < s->ethqsets)
6250                         reduce_ethqs(adap, i);
6251         }
6252         if (is_offload(adap)) {
6253                 i = want - EXTRA_VECS - s->max_ethqsets;
6254                 i -= ofld_need - nchan;
6255                 s->ofldqsets = (i / nchan) * nchan;  /* round down */
6256         }
6257         for (i = 0; i < want; ++i)
6258                 adap->msix_info[i].vec = entries[i].vector;
6259
6260         return 0;
6261 }
6262
6263 #undef EXTRA_VECS
6264
6265 static int init_rss(struct adapter *adap)
6266 {
6267         unsigned int i, j;
6268
6269         for_each_port(adap, i) {
6270                 struct port_info *pi = adap2pinfo(adap, i);
6271
6272                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6273                 if (!pi->rss)
6274                         return -ENOMEM;
6275                 for (j = 0; j < pi->rss_size; j++)
6276                         pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
6277         }
6278         return 0;
6279 }
6280
6281 static void print_port_info(const struct net_device *dev)
6282 {
6283         char buf[80];
6284         char *bufp = buf;
6285         const char *spd = "";
6286         const struct port_info *pi = netdev_priv(dev);
6287         const struct adapter *adap = pi->adapter;
6288
6289         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6290                 spd = " 2.5 GT/s";
6291         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6292                 spd = " 5 GT/s";
6293         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6294                 spd = " 8 GT/s";
6295
6296         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6297                 bufp += sprintf(bufp, "100/");
6298         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6299                 bufp += sprintf(bufp, "1000/");
6300         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6301                 bufp += sprintf(bufp, "10G/");
6302         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6303                 bufp += sprintf(bufp, "40G/");
6304         if (bufp != buf)
6305                 --bufp;
6306         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
6307
6308         netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6309                     adap->params.vpd.id,
6310                     CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
6311                     is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6312                     (adap->flags & USING_MSIX) ? " MSI-X" :
6313                     (adap->flags & USING_MSI) ? " MSI" : "");
6314         netdev_info(dev, "S/N: %s, P/N: %s\n",
6315                     adap->params.vpd.sn, adap->params.vpd.pn);
6316 }
6317
6318 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
6319 {
6320         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
6321 }
6322
6323 /*
6324  * Free the following resources:
6325  * - memory used for tables
6326  * - MSI/MSI-X
6327  * - net devices
6328  * - resources FW is holding for us
6329  */
6330 static void free_some_resources(struct adapter *adapter)
6331 {
6332         unsigned int i;
6333
6334         t4_free_mem(adapter->l2t);
6335         t4_free_mem(adapter->tids.tid_tab);
6336         disable_msi(adapter);
6337
6338         for_each_port(adapter, i)
6339                 if (adapter->port[i]) {
6340                         kfree(adap2pinfo(adapter, i)->rss);
6341                         free_netdev(adapter->port[i]);
6342                 }
6343         if (adapter->flags & FW_OK)
6344                 t4_fw_bye(adapter, adapter->fn);
6345 }
6346
6347 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6348 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6349                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6350 #define SEGMENT_SIZE 128
6351
6352 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6353 {
6354         int func, i, err, s_qpp, qpp, num_seg;
6355         struct port_info *pi;
6356         bool highdma = false;
6357         struct adapter *adapter = NULL;
6358         void __iomem *regs;
6359
6360         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6361
6362         err = pci_request_regions(pdev, KBUILD_MODNAME);
6363         if (err) {
6364                 /* Just info, some other driver may have claimed the device. */
6365                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6366                 return err;
6367         }
6368
6369         err = pci_enable_device(pdev);
6370         if (err) {
6371                 dev_err(&pdev->dev, "cannot enable PCI device\n");
6372                 goto out_release_regions;
6373         }
6374
6375         regs = pci_ioremap_bar(pdev, 0);
6376         if (!regs) {
6377                 dev_err(&pdev->dev, "cannot map device registers\n");
6378                 err = -ENOMEM;
6379                 goto out_disable_device;
6380         }
6381
6382         err = t4_wait_dev_ready(regs);
6383         if (err < 0)
6384                 goto out_unmap_bar0;
6385
6386         /* We control everything through one PF */
6387         func = SOURCEPF_GET(readl(regs + PL_WHOAMI));
6388         if (func != ent->driver_data) {
6389                 iounmap(regs);
6390                 pci_disable_device(pdev);
6391                 pci_save_state(pdev);        /* to restore SR-IOV later */
6392                 goto sriov;
6393         }
6394
6395         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6396                 highdma = true;
6397                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6398                 if (err) {
6399                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6400                                 "coherent allocations\n");
6401                         goto out_unmap_bar0;
6402                 }
6403         } else {
6404                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6405                 if (err) {
6406                         dev_err(&pdev->dev, "no usable DMA configuration\n");
6407                         goto out_unmap_bar0;
6408                 }
6409         }
6410
6411         pci_enable_pcie_error_reporting(pdev);
6412         enable_pcie_relaxed_ordering(pdev);
6413         pci_set_master(pdev);
6414         pci_save_state(pdev);
6415
6416         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6417         if (!adapter) {
6418                 err = -ENOMEM;
6419                 goto out_unmap_bar0;
6420         }
6421
6422         adapter->workq = create_singlethread_workqueue("cxgb4");
6423         if (!adapter->workq) {
6424                 err = -ENOMEM;
6425                 goto out_free_adapter;
6426         }
6427
6428         /* PCI device has been enabled */
6429         adapter->flags |= DEV_ENABLED;
6430
6431         adapter->regs = regs;
6432         adapter->pdev = pdev;
6433         adapter->pdev_dev = &pdev->dev;
6434         adapter->mbox = func;
6435         adapter->fn = func;
6436         adapter->msg_enable = dflt_msg_enable;
6437         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6438
6439         spin_lock_init(&adapter->stats_lock);
6440         spin_lock_init(&adapter->tid_release_lock);
6441         spin_lock_init(&adapter->win0_lock);
6442
6443         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6444         INIT_WORK(&adapter->db_full_task, process_db_full);
6445         INIT_WORK(&adapter->db_drop_task, process_db_drop);
6446
6447         err = t4_prep_adapter(adapter);
6448         if (err)
6449                 goto out_free_adapter;
6450
6451
6452         if (!is_t4(adapter->params.chip)) {
6453                 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6454                 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6455                       SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6456                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6457
6458                 /* Each segment size is 128B. Write coalescing is enabled only
6459                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6460                  * queue is less no of segments that can be accommodated in
6461                  * a page size.
6462                  */
6463                 if (qpp > num_seg) {
6464                         dev_err(&pdev->dev,
6465                                 "Incorrect number of egress queues per page\n");
6466                         err = -EINVAL;
6467                         goto out_free_adapter;
6468                 }
6469                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6470                 pci_resource_len(pdev, 2));
6471                 if (!adapter->bar2) {
6472                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
6473                         err = -ENOMEM;
6474                         goto out_free_adapter;
6475                 }
6476         }
6477
6478         setup_memwin(adapter);
6479         err = adap_init0(adapter);
6480         setup_memwin_rdma(adapter);
6481         if (err)
6482                 goto out_unmap_bar;
6483
6484         for_each_port(adapter, i) {
6485                 struct net_device *netdev;
6486
6487                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6488                                            MAX_ETH_QSETS);
6489                 if (!netdev) {
6490                         err = -ENOMEM;
6491                         goto out_free_dev;
6492                 }
6493
6494                 SET_NETDEV_DEV(netdev, &pdev->dev);
6495
6496                 adapter->port[i] = netdev;
6497                 pi = netdev_priv(netdev);
6498                 pi->adapter = adapter;
6499                 pi->xact_addr_filt = -1;
6500                 pi->port_id = i;
6501                 netdev->irq = pdev->irq;
6502
6503                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6504                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6505                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
6506                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6507                 if (highdma)
6508                         netdev->hw_features |= NETIF_F_HIGHDMA;
6509                 netdev->features |= netdev->hw_features;
6510                 netdev->vlan_features = netdev->features & VLAN_FEAT;
6511
6512                 netdev->priv_flags |= IFF_UNICAST_FLT;
6513
6514                 netdev->netdev_ops = &cxgb4_netdev_ops;
6515 #ifdef CONFIG_CHELSIO_T4_DCB
6516                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6517                 cxgb4_dcb_state_init(netdev);
6518 #endif
6519                 netdev->ethtool_ops = &cxgb_ethtool_ops;
6520         }
6521
6522         pci_set_drvdata(pdev, adapter);
6523
6524         if (adapter->flags & FW_OK) {
6525                 err = t4_port_init(adapter, func, func, 0);
6526                 if (err)
6527                         goto out_free_dev;
6528         }
6529
6530         /*
6531          * Configure queues and allocate tables now, they can be needed as
6532          * soon as the first register_netdev completes.
6533          */
6534         cfg_queues(adapter);
6535
6536         adapter->l2t = t4_init_l2t();
6537         if (!adapter->l2t) {
6538                 /* We tolerate a lack of L2T, giving up some functionality */
6539                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6540                 adapter->params.offload = 0;
6541         }
6542
6543         if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6544                 dev_warn(&pdev->dev, "could not allocate TID table, "
6545                          "continuing\n");
6546                 adapter->params.offload = 0;
6547         }
6548
6549         /* See what interrupts we'll be using */
6550         if (msi > 1 && enable_msix(adapter) == 0)
6551                 adapter->flags |= USING_MSIX;
6552         else if (msi > 0 && pci_enable_msi(pdev) == 0)
6553                 adapter->flags |= USING_MSI;
6554
6555         err = init_rss(adapter);
6556         if (err)
6557                 goto out_free_dev;
6558
6559         /*
6560          * The card is now ready to go.  If any errors occur during device
6561          * registration we do not fail the whole card but rather proceed only
6562          * with the ports we manage to register successfully.  However we must
6563          * register at least one net device.
6564          */
6565         for_each_port(adapter, i) {
6566                 pi = adap2pinfo(adapter, i);
6567                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6568                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6569
6570                 err = register_netdev(adapter->port[i]);
6571                 if (err)
6572                         break;
6573                 adapter->chan_map[pi->tx_chan] = i;
6574                 print_port_info(adapter->port[i]);
6575         }
6576         if (i == 0) {
6577                 dev_err(&pdev->dev, "could not register any net devices\n");
6578                 goto out_free_dev;
6579         }
6580         if (err) {
6581                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6582                 err = 0;
6583         }
6584
6585         if (cxgb4_debugfs_root) {
6586                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6587                                                            cxgb4_debugfs_root);
6588                 setup_debugfs(adapter);
6589         }
6590
6591         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6592         pdev->needs_freset = 1;
6593
6594         if (is_offload(adapter))
6595                 attach_ulds(adapter);
6596
6597 sriov:
6598 #ifdef CONFIG_PCI_IOV
6599         if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
6600                 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6601                         dev_info(&pdev->dev,
6602                                  "instantiated %u virtual functions\n",
6603                                  num_vf[func]);
6604 #endif
6605         return 0;
6606
6607  out_free_dev:
6608         free_some_resources(adapter);
6609  out_unmap_bar:
6610         if (!is_t4(adapter->params.chip))
6611                 iounmap(adapter->bar2);
6612  out_free_adapter:
6613         if (adapter->workq)
6614                 destroy_workqueue(adapter->workq);
6615
6616         kfree(adapter);
6617  out_unmap_bar0:
6618         iounmap(regs);
6619  out_disable_device:
6620         pci_disable_pcie_error_reporting(pdev);
6621         pci_disable_device(pdev);
6622  out_release_regions:
6623         pci_release_regions(pdev);
6624         return err;
6625 }
6626
6627 static void remove_one(struct pci_dev *pdev)
6628 {
6629         struct adapter *adapter = pci_get_drvdata(pdev);
6630
6631 #ifdef CONFIG_PCI_IOV
6632         pci_disable_sriov(pdev);
6633
6634 #endif
6635
6636         if (adapter) {
6637                 int i;
6638
6639                 /* Tear down per-adapter Work Queue first since it can contain
6640                  * references to our adapter data structure.
6641                  */
6642                 destroy_workqueue(adapter->workq);
6643
6644                 if (is_offload(adapter))
6645                         detach_ulds(adapter);
6646
6647                 for_each_port(adapter, i)
6648                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6649                                 unregister_netdev(adapter->port[i]);
6650
6651                 debugfs_remove_recursive(adapter->debugfs_root);
6652
6653                 /* If we allocated filters, free up state associated with any
6654                  * valid filters ...
6655                  */
6656                 if (adapter->tids.ftid_tab) {
6657                         struct filter_entry *f = &adapter->tids.ftid_tab[0];
6658                         for (i = 0; i < (adapter->tids.nftids +
6659                                         adapter->tids.nsftids); i++, f++)
6660                                 if (f->valid)
6661                                         clear_filter(adapter, f);
6662                 }
6663
6664                 if (adapter->flags & FULL_INIT_DONE)
6665                         cxgb_down(adapter);
6666
6667                 free_some_resources(adapter);
6668                 iounmap(adapter->regs);
6669                 if (!is_t4(adapter->params.chip))
6670                         iounmap(adapter->bar2);
6671                 pci_disable_pcie_error_reporting(pdev);
6672                 if ((adapter->flags & DEV_ENABLED)) {
6673                         pci_disable_device(pdev);
6674                         adapter->flags &= ~DEV_ENABLED;
6675                 }
6676                 pci_release_regions(pdev);
6677                 synchronize_rcu();
6678                 kfree(adapter);
6679         } else
6680                 pci_release_regions(pdev);
6681 }
6682
6683 static struct pci_driver cxgb4_driver = {
6684         .name     = KBUILD_MODNAME,
6685         .id_table = cxgb4_pci_tbl,
6686         .probe    = init_one,
6687         .remove   = remove_one,
6688         .shutdown = remove_one,
6689         .err_handler = &cxgb4_eeh,
6690 };
6691
6692 static int __init cxgb4_init_module(void)
6693 {
6694         int ret;
6695
6696         /* Debugfs support is optional, just warn if this fails */
6697         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6698         if (!cxgb4_debugfs_root)
6699                 pr_warn("could not create debugfs entry, continuing\n");
6700
6701         ret = pci_register_driver(&cxgb4_driver);
6702         if (ret < 0)
6703                 debugfs_remove(cxgb4_debugfs_root);
6704
6705 #if IS_ENABLED(CONFIG_IPV6)
6706         register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6707 #endif
6708
6709         return ret;
6710 }
6711
6712 static void __exit cxgb4_cleanup_module(void)
6713 {
6714 #if IS_ENABLED(CONFIG_IPV6)
6715         unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6716 #endif
6717         pci_unregister_driver(&cxgb4_driver);
6718         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6719 }
6720
6721 module_init(cxgb4_init_module);
6722 module_exit(cxgb4_cleanup_module);