2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <asm/uaccess.h>
71 #include "cxgb4_dcb.h"
72 #include "cxgb4_debugfs.h"
78 #define DRV_VERSION "2.0.0-ko"
79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
82 * Max interrupt hold-off timer value in us. Queues fall back to this value
83 * under extreme memory pressure so it's largish to give the system time to
86 #define MAX_SGE_TIMERVAL 200U
90 * Physical Function provisioning constants.
92 PFRES_NVI = 4, /* # of Virtual Interfaces */
93 PFRES_NETHCTRL = 128, /* # of EQs used for ETH or CTRL Qs */
94 PFRES_NIQFLINT = 128, /* # of ingress Qs/w Free List(s)/intr
96 PFRES_NEQ = 256, /* # of egress queues */
97 PFRES_NIQ = 0, /* # of ingress queues */
98 PFRES_TC = 0, /* PCI-E traffic class */
99 PFRES_NEXACTF = 128, /* # of exact MPS filters */
101 PFRES_R_CAPS = FW_CMD_CAP_PF,
102 PFRES_WX_CAPS = FW_CMD_CAP_PF,
104 #ifdef CONFIG_PCI_IOV
106 * Virtual Function provisioning constants. We need two extra Ingress
107 * Queues with Interrupt capability to serve as the VF's Firmware
108 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109 * neither will have Free Lists associated with them). For each
110 * Ethernet/Control Egress Queue and for each Free List, we need an
113 VFRES_NPORTS = 1, /* # of "ports" per VF */
114 VFRES_NQSETS = 2, /* # of "Queue Sets" per VF */
116 VFRES_NVI = VFRES_NPORTS, /* # of Virtual Interfaces */
117 VFRES_NETHCTRL = VFRES_NQSETS, /* # of EQs used for ETH or CTRL Qs */
118 VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
119 VFRES_NEQ = VFRES_NQSETS*2, /* # of egress queues */
120 VFRES_NIQ = 0, /* # of non-fl/int ingress queues */
121 VFRES_TC = 0, /* PCI-E traffic class */
122 VFRES_NEXACTF = 16, /* # of exact MPS filters */
124 VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
125 VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
130 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
131 * static and likely not to be useful in the long run. We really need to
132 * implement some form of persistent configuration which the firmware
135 static unsigned int pfvfres_pmask(struct adapter *adapter,
136 unsigned int pf, unsigned int vf)
138 unsigned int portn, portvec;
141 * Give PF's access to all of the ports.
144 return FW_PFVF_CMD_PMASK_M;
147 * For VFs, we'll assign them access to the ports based purely on the
148 * PF. We assign active ports in order, wrapping around if there are
149 * fewer active ports than PFs: e.g. active port[pf % nports].
150 * Unfortunately the adapter's port_info structs haven't been
151 * initialized yet so we have to compute this.
153 if (adapter->params.nports == 0)
156 portn = pf % adapter->params.nports;
157 portvec = adapter->params.portvec;
160 * Isolate the lowest set bit in the port vector. If we're at
161 * the port number that we want, return that as the pmask.
162 * otherwise mask that bit out of the port vector and
163 * decrement our port number ...
165 unsigned int pmask = portvec ^ (portvec & (portvec-1));
175 MAX_TXQ_ENTRIES = 16384,
176 MAX_CTRL_TXQ_ENTRIES = 1024,
177 MAX_RSPQ_ENTRIES = 16384,
178 MAX_RX_BUFFERS = 16384,
179 MIN_TXQ_ENTRIES = 32,
180 MIN_CTRL_TXQ_ENTRIES = 32,
181 MIN_RSPQ_ENTRIES = 128,
185 /* Host shadow copy of ingress filter entry. This is in host native format
186 * and doesn't match the ordering or bit order, etc. of the hardware of the
187 * firmware command. The use of bit-field structure elements is purely to
188 * remind ourselves of the field size limitations and save memory in the case
189 * where the filter table is large.
191 struct filter_entry {
192 /* Administrative fields for filter.
194 u32 valid:1; /* filter allocated and valid */
195 u32 locked:1; /* filter is administratively locked */
197 u32 pending:1; /* filter action is pending firmware reply */
198 u32 smtidx:8; /* Source MAC Table index for smac */
199 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
201 /* The filter itself. Most of this is a straight copy of information
202 * provided by the extended ioctl(). Some fields are translated to
203 * internal forms -- for instance the Ingress Queue ID passed in from
204 * the ioctl() is translated into the Absolute Ingress Queue ID.
206 struct ch_filter_specification fs;
209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
213 /* Macros needed to support the PCI Device ID Table ...
215 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
216 static struct pci_device_id cxgb4_pci_tbl[] = {
217 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
219 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
222 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
224 #define CH_PCI_ID_TABLE_ENTRY(devid) \
225 {PCI_VDEVICE(CHELSIO, (devid)), 4}
227 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
231 #include "t4_pci_id_tbl.h"
233 #define FW4_FNAME "cxgb4/t4fw.bin"
234 #define FW5_FNAME "cxgb4/t5fw.bin"
235 #define FW4_CFNAME "cxgb4/t4-config.txt"
236 #define FW5_CFNAME "cxgb4/t5-config.txt"
238 MODULE_DESCRIPTION(DRV_DESC);
239 MODULE_AUTHOR("Chelsio Communications");
240 MODULE_LICENSE("Dual BSD/GPL");
241 MODULE_VERSION(DRV_VERSION);
242 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
243 MODULE_FIRMWARE(FW4_FNAME);
244 MODULE_FIRMWARE(FW5_FNAME);
247 * Normally we're willing to become the firmware's Master PF but will be happy
248 * if another PF has already become the Master and initialized the adapter.
249 * Setting "force_init" will cause this driver to forcibly establish itself as
250 * the Master PF and initialize the adapter.
252 static uint force_init;
254 module_param(force_init, uint, 0644);
255 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
258 * Normally if the firmware we connect to has Configuration File support, we
259 * use that and only fall back to the old Driver-based initialization if the
260 * Configuration File fails for some reason. If force_old_init is set, then
261 * we'll always use the old Driver-based initialization sequence.
263 static uint force_old_init;
265 module_param(force_old_init, uint, 0644);
266 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
268 static int dflt_msg_enable = DFLT_MSG_ENABLE;
270 module_param(dflt_msg_enable, int, 0644);
271 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
274 * The driver uses the best interrupt scheme available on a platform in the
275 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
276 * of these schemes the driver may consider as follows:
278 * msi = 2: choose from among all three options
279 * msi = 1: only consider MSI and INTx interrupts
280 * msi = 0: force INTx interrupts
284 module_param(msi, int, 0644);
285 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
288 * Queue interrupt hold-off timer values. Queues default to the first of these
291 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
293 module_param_array(intr_holdoff, uint, NULL, 0644);
294 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
295 "0..4 in microseconds");
297 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
299 module_param_array(intr_cnt, uint, NULL, 0644);
300 MODULE_PARM_DESC(intr_cnt,
301 "thresholds 1..3 for queue interrupt packet counters");
304 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
305 * offset by 2 bytes in order to have the IP headers line up on 4-byte
306 * boundaries. This is a requirement for many architectures which will throw
307 * a machine check fault if an attempt is made to access one of the 4-byte IP
308 * header fields on a non-4-byte boundary. And it's a major performance issue
309 * even on some architectures which allow it like some implementations of the
310 * x86 ISA. However, some architectures don't mind this and for some very
311 * edge-case performance sensitive applications (like forwarding large volumes
312 * of small packets), setting this DMA offset to 0 will decrease the number of
313 * PCI-E Bus transfers enough to measurably affect performance.
315 static int rx_dma_offset = 2;
319 #ifdef CONFIG_PCI_IOV
320 module_param(vf_acls, bool, 0644);
321 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
323 /* Configure the number of PCI-E Virtual Function which are to be instantiated
324 * on SR-IOV Capable Physical Functions.
326 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
328 module_param_array(num_vf, uint, NULL, 0644);
329 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
332 /* TX Queue select used to determine what algorithm to use for selecting TX
333 * queue. Select between the kernel provided function (select_queue=0) or user
334 * cxgb_select_queue function (select_queue=1)
336 * Default: select_queue=0
338 static int select_queue;
339 module_param(select_queue, int, 0644);
340 MODULE_PARM_DESC(select_queue,
341 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
344 * The filter TCAM has a fixed portion and a variable portion. The fixed
345 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
346 * ports. The variable portion is 36 bits which can include things like Exact
347 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
348 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
349 * far exceed the 36-bit budget for this "compressed" header portion of the
350 * filter. Thus, we have a scarce resource which must be carefully managed.
352 * By default we set this up to mostly match the set of filter matching
353 * capabilities of T3 but with accommodations for some of T4's more
354 * interesting features:
356 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
357 * [Inner] VLAN (17), Port (3), FCoE (1) }
360 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
361 TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
362 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
365 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
367 module_param(tp_vlan_pri_map, uint, 0644);
368 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
370 static struct dentry *cxgb4_debugfs_root;
372 static LIST_HEAD(adapter_list);
373 static DEFINE_MUTEX(uld_mutex);
374 /* Adapter list to be accessed from atomic context */
375 static LIST_HEAD(adap_rcu_list);
376 static DEFINE_SPINLOCK(adap_rcu_lock);
377 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
378 static const char *uld_str[] = { "RDMA", "iSCSI" };
380 static void link_report(struct net_device *dev)
382 if (!netif_carrier_ok(dev))
383 netdev_info(dev, "link down\n");
385 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
387 const char *s = "10Mbps";
388 const struct port_info *p = netdev_priv(dev);
390 switch (p->link_cfg.speed) {
405 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
410 #ifdef CONFIG_CHELSIO_T4_DCB
411 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
412 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
414 struct port_info *pi = netdev_priv(dev);
415 struct adapter *adap = pi->adapter;
416 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
419 /* We use a simple mapping of Port TX Queue Index to DCB
420 * Priority when we're enabling DCB.
422 for (i = 0; i < pi->nqsets; i++, txq++) {
426 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
428 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
429 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
430 value = enable ? i : 0xffffffff;
432 /* Since we can be called while atomic (from "interrupt
433 * level") we need to issue the Set Parameters Commannd
434 * without sleeping (timeout < 0).
436 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
440 dev_err(adap->pdev_dev,
441 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
442 enable ? "set" : "unset", pi->port_id, i, -err);
444 txq->dcb_prio = value;
447 #endif /* CONFIG_CHELSIO_T4_DCB */
449 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
451 struct net_device *dev = adapter->port[port_id];
453 /* Skip changes from disabled ports. */
454 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
456 netif_carrier_on(dev);
458 #ifdef CONFIG_CHELSIO_T4_DCB
459 cxgb4_dcb_state_init(dev);
460 dcb_tx_queue_prio_enable(dev, false);
461 #endif /* CONFIG_CHELSIO_T4_DCB */
462 netif_carrier_off(dev);
469 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
471 static const char *mod_str[] = {
472 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
475 const struct net_device *dev = adap->port[port_id];
476 const struct port_info *pi = netdev_priv(dev);
478 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
479 netdev_info(dev, "port module unplugged\n");
480 else if (pi->mod_type < ARRAY_SIZE(mod_str))
481 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
485 * Configure the exact and hash address filters to handle a port's multicast
486 * and secondary unicast MAC addresses.
488 static int set_addr_filters(const struct net_device *dev, bool sleep)
496 const struct netdev_hw_addr *ha;
497 int uc_cnt = netdev_uc_count(dev);
498 int mc_cnt = netdev_mc_count(dev);
499 const struct port_info *pi = netdev_priv(dev);
500 unsigned int mb = pi->adapter->fn;
502 /* first do the secondary unicast addresses */
503 netdev_for_each_uc_addr(ha, dev) {
504 addr[naddr++] = ha->addr;
505 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
506 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
507 naddr, addr, filt_idx, &uhash, sleep);
516 /* next set up the multicast addresses */
517 netdev_for_each_mc_addr(ha, dev) {
518 addr[naddr++] = ha->addr;
519 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
520 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
521 naddr, addr, filt_idx, &mhash, sleep);
530 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
531 uhash | mhash, sleep);
534 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
535 module_param(dbfifo_int_thresh, int, 0644);
536 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
539 * usecs to sleep while draining the dbfifo
541 static int dbfifo_drain_delay = 1000;
542 module_param(dbfifo_drain_delay, int, 0644);
543 MODULE_PARM_DESC(dbfifo_drain_delay,
544 "usecs to sleep while draining the dbfifo");
547 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
548 * If @mtu is -1 it is left unchanged.
550 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
553 struct port_info *pi = netdev_priv(dev);
555 ret = set_addr_filters(dev, sleep_ok);
557 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
558 (dev->flags & IFF_PROMISC) ? 1 : 0,
559 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
565 * link_start - enable a port
566 * @dev: the port to enable
568 * Performs the MAC and PHY actions needed to enable a port.
570 static int link_start(struct net_device *dev)
573 struct port_info *pi = netdev_priv(dev);
574 unsigned int mb = pi->adapter->fn;
577 * We do not set address filters and promiscuity here, the stack does
578 * that step explicitly.
580 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
581 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
583 ret = t4_change_mac(pi->adapter, mb, pi->viid,
584 pi->xact_addr_filt, dev->dev_addr, true,
587 pi->xact_addr_filt = ret;
592 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
596 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
597 true, CXGB4_DCB_ENABLED);
604 int cxgb4_dcb_enabled(const struct net_device *dev)
606 #ifdef CONFIG_CHELSIO_T4_DCB
607 struct port_info *pi = netdev_priv(dev);
609 if (!pi->dcb.enabled)
612 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
613 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
618 EXPORT_SYMBOL(cxgb4_dcb_enabled);
620 #ifdef CONFIG_CHELSIO_T4_DCB
621 /* Handle a Data Center Bridging update message from the firmware. */
622 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
624 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
625 struct net_device *dev = adap->port[port];
626 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
629 cxgb4_dcb_handle_fw_update(adap, pcmd);
630 new_dcb_enabled = cxgb4_dcb_enabled(dev);
632 /* If the DCB has become enabled or disabled on the port then we're
633 * going to need to set up/tear down DCB Priority parameters for the
634 * TX Queues associated with the port.
636 if (new_dcb_enabled != old_dcb_enabled)
637 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
639 #endif /* CONFIG_CHELSIO_T4_DCB */
641 /* Clear a filter and release any of its resources that we own. This also
642 * clears the filter's "pending" status.
644 static void clear_filter(struct adapter *adap, struct filter_entry *f)
646 /* If the new or old filter have loopback rewriteing rules then we'll
647 * need to free any existing Layer Two Table (L2T) entries of the old
648 * filter rule. The firmware will handle freeing up any Source MAC
649 * Table (SMT) entries used for rewriting Source MAC Addresses in
653 cxgb4_l2t_release(f->l2t);
655 /* The zeroing of the filter rule below clears the filter valid,
656 * pending, locked flags, l2t pointer, etc. so it's all we need for
659 memset(f, 0, sizeof(*f));
662 /* Handle a filter write/deletion reply.
664 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
666 unsigned int idx = GET_TID(rpl);
667 unsigned int nidx = idx - adap->tids.ftid_base;
669 struct filter_entry *f;
671 if (idx >= adap->tids.ftid_base && nidx <
672 (adap->tids.nftids + adap->tids.nsftids)) {
674 ret = GET_TCB_COOKIE(rpl->cookie);
675 f = &adap->tids.ftid_tab[idx];
677 if (ret == FW_FILTER_WR_FLT_DELETED) {
678 /* Clear the filter when we get confirmation from the
679 * hardware that the filter has been deleted.
681 clear_filter(adap, f);
682 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
683 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
685 clear_filter(adap, f);
686 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
687 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
688 f->pending = 0; /* asynchronous setup completed */
691 /* Something went wrong. Issue a warning about the
692 * problem and clear everything out.
694 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
696 clear_filter(adap, f);
701 /* Response queue handler for the FW event queue.
703 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
704 const struct pkt_gl *gl)
706 u8 opcode = ((const struct rss_header *)rsp)->opcode;
708 rsp++; /* skip RSS header */
710 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
712 if (unlikely(opcode == CPL_FW4_MSG &&
713 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
715 opcode = ((const struct rss_header *)rsp)->opcode;
717 if (opcode != CPL_SGE_EGR_UPDATE) {
718 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
724 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
725 const struct cpl_sge_egr_update *p = (void *)rsp;
726 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
729 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
731 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
732 struct sge_eth_txq *eq;
734 eq = container_of(txq, struct sge_eth_txq, q);
735 netif_tx_wake_queue(eq->txq);
737 struct sge_ofld_txq *oq;
739 oq = container_of(txq, struct sge_ofld_txq, q);
740 tasklet_schedule(&oq->qresume_tsk);
742 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
743 const struct cpl_fw6_msg *p = (void *)rsp;
745 #ifdef CONFIG_CHELSIO_T4_DCB
746 const struct fw_port_cmd *pcmd = (const void *)p->data;
747 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
748 unsigned int action =
749 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
751 if (cmd == FW_PORT_CMD &&
752 action == FW_PORT_ACTION_GET_PORT_INFO) {
753 int port = FW_PORT_CMD_PORTID_G(
754 be32_to_cpu(pcmd->op_to_portid));
755 struct net_device *dev = q->adap->port[port];
756 int state_input = ((pcmd->u.info.dcbxdis_pkd &
757 FW_PORT_CMD_DCBXDIS_F)
758 ? CXGB4_DCB_INPUT_FW_DISABLED
759 : CXGB4_DCB_INPUT_FW_ENABLED);
761 cxgb4_dcb_state_fsm(dev, state_input);
764 if (cmd == FW_PORT_CMD &&
765 action == FW_PORT_ACTION_L2_DCB_CFG)
766 dcb_rpl(q->adap, pcmd);
770 t4_handle_fw_rpl(q->adap, p->data);
771 } else if (opcode == CPL_L2T_WRITE_RPL) {
772 const struct cpl_l2t_write_rpl *p = (void *)rsp;
774 do_l2t_write_rpl(q->adap, p);
775 } else if (opcode == CPL_SET_TCB_RPL) {
776 const struct cpl_set_tcb_rpl *p = (void *)rsp;
778 filter_rpl(q->adap, p);
780 dev_err(q->adap->pdev_dev,
781 "unexpected CPL %#x on FW event queue\n", opcode);
787 * uldrx_handler - response queue handler for ULD queues
788 * @q: the response queue that received the packet
789 * @rsp: the response queue descriptor holding the offload message
790 * @gl: the gather list of packet fragments
792 * Deliver an ingress offload packet to a ULD. All processing is done by
793 * the ULD, we just maintain statistics.
795 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
796 const struct pkt_gl *gl)
798 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
800 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
802 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
803 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
806 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
812 else if (gl == CXGB4_MSG_AN)
819 static void disable_msi(struct adapter *adapter)
821 if (adapter->flags & USING_MSIX) {
822 pci_disable_msix(adapter->pdev);
823 adapter->flags &= ~USING_MSIX;
824 } else if (adapter->flags & USING_MSI) {
825 pci_disable_msi(adapter->pdev);
826 adapter->flags &= ~USING_MSI;
831 * Interrupt handler for non-data events used with MSI-X.
833 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
835 struct adapter *adap = cookie;
837 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
840 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
842 t4_slow_intr_handler(adap);
847 * Name the MSI-X interrupts.
849 static void name_msix_vecs(struct adapter *adap)
851 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
853 /* non-data interrupts */
854 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
857 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
858 adap->port[0]->name);
860 /* Ethernet queues */
861 for_each_port(adap, j) {
862 struct net_device *d = adap->port[j];
863 const struct port_info *pi = netdev_priv(d);
865 for (i = 0; i < pi->nqsets; i++, msi_idx++)
866 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
871 for_each_ofldrxq(&adap->sge, i)
872 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
873 adap->port[0]->name, i);
875 for_each_rdmarxq(&adap->sge, i)
876 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
877 adap->port[0]->name, i);
879 for_each_rdmaciq(&adap->sge, i)
880 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
881 adap->port[0]->name, i);
884 static int request_msix_queue_irqs(struct adapter *adap)
886 struct sge *s = &adap->sge;
887 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
890 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
891 adap->msix_info[1].desc, &s->fw_evtq);
895 for_each_ethrxq(s, ethqidx) {
896 err = request_irq(adap->msix_info[msi_index].vec,
898 adap->msix_info[msi_index].desc,
899 &s->ethrxq[ethqidx].rspq);
904 for_each_ofldrxq(s, ofldqidx) {
905 err = request_irq(adap->msix_info[msi_index].vec,
907 adap->msix_info[msi_index].desc,
908 &s->ofldrxq[ofldqidx].rspq);
913 for_each_rdmarxq(s, rdmaqidx) {
914 err = request_irq(adap->msix_info[msi_index].vec,
916 adap->msix_info[msi_index].desc,
917 &s->rdmarxq[rdmaqidx].rspq);
922 for_each_rdmaciq(s, rdmaciqqidx) {
923 err = request_irq(adap->msix_info[msi_index].vec,
925 adap->msix_info[msi_index].desc,
926 &s->rdmaciq[rdmaciqqidx].rspq);
934 while (--rdmaciqqidx >= 0)
935 free_irq(adap->msix_info[--msi_index].vec,
936 &s->rdmaciq[rdmaciqqidx].rspq);
937 while (--rdmaqidx >= 0)
938 free_irq(adap->msix_info[--msi_index].vec,
939 &s->rdmarxq[rdmaqidx].rspq);
940 while (--ofldqidx >= 0)
941 free_irq(adap->msix_info[--msi_index].vec,
942 &s->ofldrxq[ofldqidx].rspq);
943 while (--ethqidx >= 0)
944 free_irq(adap->msix_info[--msi_index].vec,
945 &s->ethrxq[ethqidx].rspq);
946 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
950 static void free_msix_queue_irqs(struct adapter *adap)
952 int i, msi_index = 2;
953 struct sge *s = &adap->sge;
955 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
956 for_each_ethrxq(s, i)
957 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
958 for_each_ofldrxq(s, i)
959 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
960 for_each_rdmarxq(s, i)
961 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
962 for_each_rdmaciq(s, i)
963 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
967 * write_rss - write the RSS table for a given port
969 * @queues: array of queue indices for RSS
971 * Sets up the portion of the HW RSS table for the port's VI to distribute
972 * packets to the Rx queues in @queues.
974 static int write_rss(const struct port_info *pi, const u16 *queues)
978 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
980 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
984 /* map the queue indices to queue ids */
985 for (i = 0; i < pi->rss_size; i++, queues++)
986 rss[i] = q[*queues].rspq.abs_id;
988 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
989 pi->rss_size, rss, pi->rss_size);
995 * setup_rss - configure RSS
998 * Sets up RSS for each port.
1000 static int setup_rss(struct adapter *adap)
1004 for_each_port(adap, i) {
1005 const struct port_info *pi = adap2pinfo(adap, i);
1007 err = write_rss(pi, pi->rss);
1015 * Return the channel of the ingress queue with the given qid.
1017 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1019 qid -= p->ingr_start;
1020 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1024 * Wait until all NAPI handlers are descheduled.
1026 static void quiesce_rx(struct adapter *adap)
1030 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1031 struct sge_rspq *q = adap->sge.ingr_map[i];
1033 if (q && q->handler)
1034 napi_disable(&q->napi);
1039 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1041 static void enable_rx(struct adapter *adap)
1045 for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1046 struct sge_rspq *q = adap->sge.ingr_map[i];
1051 napi_enable(&q->napi);
1052 /* 0-increment GTS to start the timer and enable interrupts */
1053 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1054 SEINTARM(q->intr_params) |
1055 INGRESSQID(q->cntxt_id));
1060 * setup_sge_queues - configure SGE Tx/Rx/response queues
1061 * @adap: the adapter
1063 * Determines how many sets of SGE queues to use and initializes them.
1064 * We support multiple queue sets per port if we have MSI-X, otherwise
1065 * just one queue set per port.
1067 static int setup_sge_queues(struct adapter *adap)
1069 int err, msi_idx, i, j;
1070 struct sge *s = &adap->sge;
1072 bitmap_zero(s->starving_fl, MAX_EGRQ);
1073 bitmap_zero(s->txq_maperr, MAX_EGRQ);
1075 if (adap->flags & USING_MSIX)
1076 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1078 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1082 msi_idx = -((int)s->intrq.abs_id + 1);
1085 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1086 msi_idx, NULL, fwevtq_handler);
1088 freeout: t4_free_sge_resources(adap);
1092 for_each_port(adap, i) {
1093 struct net_device *dev = adap->port[i];
1094 struct port_info *pi = netdev_priv(dev);
1095 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1096 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1098 for (j = 0; j < pi->nqsets; j++, q++) {
1101 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1107 memset(&q->stats, 0, sizeof(q->stats));
1109 for (j = 0; j < pi->nqsets; j++, t++) {
1110 err = t4_sge_alloc_eth_txq(adap, t, dev,
1111 netdev_get_tx_queue(dev, j),
1112 s->fw_evtq.cntxt_id);
1118 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1119 for_each_ofldrxq(s, i) {
1120 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1121 struct net_device *dev = adap->port[i / j];
1125 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1126 q->fl.size ? &q->fl : NULL,
1130 memset(&q->stats, 0, sizeof(q->stats));
1131 s->ofld_rxq[i] = q->rspq.abs_id;
1132 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1133 s->fw_evtq.cntxt_id);
1138 for_each_rdmarxq(s, i) {
1139 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1143 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1144 msi_idx, q->fl.size ? &q->fl : NULL,
1148 memset(&q->stats, 0, sizeof(q->stats));
1149 s->rdma_rxq[i] = q->rspq.abs_id;
1152 for_each_rdmaciq(s, i) {
1153 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1157 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1158 msi_idx, q->fl.size ? &q->fl : NULL,
1162 memset(&q->stats, 0, sizeof(q->stats));
1163 s->rdma_ciq[i] = q->rspq.abs_id;
1166 for_each_port(adap, i) {
1168 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1169 * have RDMA queues, and that's the right value.
1171 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1172 s->fw_evtq.cntxt_id,
1173 s->rdmarxq[i].rspq.cntxt_id);
1178 t4_write_reg(adap, is_t4(adap->params.chip) ?
1179 MPS_TRC_RSS_CONTROL :
1180 MPS_T5_TRC_RSS_CONTROL,
1181 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1182 QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1187 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1188 * The allocated memory is cleared.
1190 void *t4_alloc_mem(size_t size)
1192 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1200 * Free memory allocated through alloc_mem().
1202 void t4_free_mem(void *addr)
1204 if (is_vmalloc_addr(addr))
1210 /* Send a Work Request to write the filter at a specified index. We construct
1211 * a Firmware Filter Work Request to have the work done and put the indicated
1212 * filter into "pending" mode which will prevent any further actions against
1213 * it till we get a reply from the firmware on the completion status of the
1216 static int set_filter_wr(struct adapter *adapter, int fidx)
1218 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1219 struct sk_buff *skb;
1220 struct fw_filter_wr *fwr;
1223 /* If the new filter requires loopback Destination MAC and/or VLAN
1224 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1227 if (f->fs.newdmac || f->fs.newvlan) {
1228 /* allocate L2T entry for new filter */
1229 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1232 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1233 f->fs.eport, f->fs.dmac)) {
1234 cxgb4_l2t_release(f->l2t);
1240 ftid = adapter->tids.ftid_base + fidx;
1242 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1243 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1244 memset(fwr, 0, sizeof(*fwr));
1246 /* It would be nice to put most of the following in t4_hw.c but most
1247 * of the work is translating the cxgbtool ch_filter_specification
1248 * into the Work Request and the definition of that structure is
1249 * currently in cxgbtool.h which isn't appropriate to pull into the
1250 * common code. We may eventually try to come up with a more neutral
1251 * filter specification structure but for now it's easiest to simply
1252 * put this fairly direct code in line ...
1254 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1255 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1257 htonl(FW_FILTER_WR_TID_V(ftid) |
1258 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1259 FW_FILTER_WR_NOREPLY_V(0) |
1260 FW_FILTER_WR_IQ_V(f->fs.iq));
1261 fwr->del_filter_to_l2tix =
1262 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1263 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1264 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1265 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1266 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1267 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1268 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1269 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1270 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1271 f->fs.newvlan == VLAN_REWRITE) |
1272 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1273 f->fs.newvlan == VLAN_REWRITE) |
1274 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1275 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1276 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1277 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1278 fwr->ethtype = htons(f->fs.val.ethtype);
1279 fwr->ethtypem = htons(f->fs.mask.ethtype);
1280 fwr->frag_to_ovlan_vldm =
1281 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1282 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1283 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1284 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1285 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1286 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1288 fwr->rx_chan_rx_rpl_iq =
1289 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1290 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1291 fwr->maci_to_matchtypem =
1292 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1293 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1294 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1295 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1296 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1297 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1298 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1299 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1300 fwr->ptcl = f->fs.val.proto;
1301 fwr->ptclm = f->fs.mask.proto;
1302 fwr->ttyp = f->fs.val.tos;
1303 fwr->ttypm = f->fs.mask.tos;
1304 fwr->ivlan = htons(f->fs.val.ivlan);
1305 fwr->ivlanm = htons(f->fs.mask.ivlan);
1306 fwr->ovlan = htons(f->fs.val.ovlan);
1307 fwr->ovlanm = htons(f->fs.mask.ovlan);
1308 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1309 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1310 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1311 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1312 fwr->lp = htons(f->fs.val.lport);
1313 fwr->lpm = htons(f->fs.mask.lport);
1314 fwr->fp = htons(f->fs.val.fport);
1315 fwr->fpm = htons(f->fs.mask.fport);
1317 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1319 /* Mark the filter as "pending" and ship off the Filter Work Request.
1320 * When we get the Work Request Reply we'll clear the pending status.
1323 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1324 t4_ofld_send(adapter, skb);
1328 /* Delete the filter at a specified index.
1330 static int del_filter_wr(struct adapter *adapter, int fidx)
1332 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1333 struct sk_buff *skb;
1334 struct fw_filter_wr *fwr;
1335 unsigned int len, ftid;
1338 ftid = adapter->tids.ftid_base + fidx;
1340 skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1341 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1342 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1344 /* Mark the filter as "pending" and ship off the Filter Work Request.
1345 * When we get the Work Request Reply we'll clear the pending status.
1348 t4_mgmt_tx(adapter, skb);
1352 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1353 void *accel_priv, select_queue_fallback_t fallback)
1357 #ifdef CONFIG_CHELSIO_T4_DCB
1358 /* If a Data Center Bridging has been successfully negotiated on this
1359 * link then we'll use the skb's priority to map it to a TX Queue.
1360 * The skb's priority is determined via the VLAN Tag Priority Code
1363 if (cxgb4_dcb_enabled(dev)) {
1367 err = vlan_get_tag(skb, &vlan_tci);
1368 if (unlikely(err)) {
1369 if (net_ratelimit())
1371 "TX Packet without VLAN Tag on DCB Link\n");
1374 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1378 #endif /* CONFIG_CHELSIO_T4_DCB */
1381 txq = (skb_rx_queue_recorded(skb)
1382 ? skb_get_rx_queue(skb)
1383 : smp_processor_id());
1385 while (unlikely(txq >= dev->real_num_tx_queues))
1386 txq -= dev->real_num_tx_queues;
1391 return fallback(dev, skb) % dev->real_num_tx_queues;
1394 static inline int is_offload(const struct adapter *adap)
1396 return adap->params.offload;
1400 * Implementation of ethtool operations.
1403 static u32 get_msglevel(struct net_device *dev)
1405 return netdev2adap(dev)->msg_enable;
1408 static void set_msglevel(struct net_device *dev, u32 val)
1410 netdev2adap(dev)->msg_enable = val;
1413 static char stats_strings[][ETH_GSTRING_LEN] = {
1416 "TxBroadcastFrames ",
1417 "TxMulticastFrames ",
1423 "TxFrames128To255 ",
1424 "TxFrames256To511 ",
1425 "TxFrames512To1023 ",
1426 "TxFrames1024To1518 ",
1427 "TxFrames1519ToMax ",
1442 "RxBroadcastFrames ",
1443 "RxMulticastFrames ",
1455 "RxFrames128To255 ",
1456 "RxFrames256To511 ",
1457 "RxFrames512To1023 ",
1458 "RxFrames1024To1518 ",
1459 "RxFrames1519ToMax ",
1471 "RxBG0FramesDropped ",
1472 "RxBG1FramesDropped ",
1473 "RxBG2FramesDropped ",
1474 "RxBG3FramesDropped ",
1475 "RxBG0FramesTrunc ",
1476 "RxBG1FramesTrunc ",
1477 "RxBG2FramesTrunc ",
1478 "RxBG3FramesTrunc ",
1487 "WriteCoalSuccess ",
1491 static int get_sset_count(struct net_device *dev, int sset)
1495 return ARRAY_SIZE(stats_strings);
1501 #define T4_REGMAP_SIZE (160 * 1024)
1502 #define T5_REGMAP_SIZE (332 * 1024)
1504 static int get_regs_len(struct net_device *dev)
1506 struct adapter *adap = netdev2adap(dev);
1507 if (is_t4(adap->params.chip))
1508 return T4_REGMAP_SIZE;
1510 return T5_REGMAP_SIZE;
1513 static int get_eeprom_len(struct net_device *dev)
1518 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1520 struct adapter *adapter = netdev2adap(dev);
1522 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1523 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1524 strlcpy(info->bus_info, pci_name(adapter->pdev),
1525 sizeof(info->bus_info));
1527 if (adapter->params.fw_vers)
1528 snprintf(info->fw_version, sizeof(info->fw_version),
1529 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1530 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
1531 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
1532 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
1533 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers),
1534 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
1535 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
1536 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
1537 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
1540 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1542 if (stringset == ETH_SS_STATS)
1543 memcpy(data, stats_strings, sizeof(stats_strings));
1547 * port stats maintained per queue of the port. They should be in the same
1548 * order as in stats_strings above.
1550 struct queue_port_stats {
1560 static void collect_sge_port_stats(const struct adapter *adap,
1561 const struct port_info *p, struct queue_port_stats *s)
1564 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1565 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1567 memset(s, 0, sizeof(*s));
1568 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1570 s->tx_csum += tx->tx_cso;
1571 s->rx_csum += rx->stats.rx_cso;
1572 s->vlan_ex += rx->stats.vlan_ex;
1573 s->vlan_ins += tx->vlan_ins;
1574 s->gro_pkts += rx->stats.lro_pkts;
1575 s->gro_merged += rx->stats.lro_merged;
1579 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1582 struct port_info *pi = netdev_priv(dev);
1583 struct adapter *adapter = pi->adapter;
1586 t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1588 data += sizeof(struct port_stats) / sizeof(u64);
1589 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1590 data += sizeof(struct queue_port_stats) / sizeof(u64);
1591 if (!is_t4(adapter->params.chip)) {
1592 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1593 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1594 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1595 *data = val1 - val2;
1600 memset(data, 0, 2 * sizeof(u64));
1606 * Return a version number to identify the type of adapter. The scheme is:
1607 * - bits 0..9: chip version
1608 * - bits 10..15: chip revision
1609 * - bits 16..23: register dump version
1611 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1613 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1614 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1617 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1620 u32 *p = buf + start;
1622 for ( ; start <= end; start += sizeof(u32))
1623 *p++ = t4_read_reg(ap, start);
1626 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1629 static const unsigned int t4_reg_ranges[] = {
1850 static const unsigned int t5_reg_ranges[] = {
2279 struct adapter *ap = netdev2adap(dev);
2280 static const unsigned int *reg_ranges;
2281 int arr_size = 0, buf_size = 0;
2283 if (is_t4(ap->params.chip)) {
2284 reg_ranges = &t4_reg_ranges[0];
2285 arr_size = ARRAY_SIZE(t4_reg_ranges);
2286 buf_size = T4_REGMAP_SIZE;
2288 reg_ranges = &t5_reg_ranges[0];
2289 arr_size = ARRAY_SIZE(t5_reg_ranges);
2290 buf_size = T5_REGMAP_SIZE;
2293 regs->version = mk_adap_vers(ap);
2295 memset(buf, 0, buf_size);
2296 for (i = 0; i < arr_size; i += 2)
2297 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2300 static int restart_autoneg(struct net_device *dev)
2302 struct port_info *p = netdev_priv(dev);
2304 if (!netif_running(dev))
2306 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2308 t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2312 static int identify_port(struct net_device *dev,
2313 enum ethtool_phys_id_state state)
2316 struct adapter *adap = netdev2adap(dev);
2318 if (state == ETHTOOL_ID_ACTIVE)
2320 else if (state == ETHTOOL_ID_INACTIVE)
2325 return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2328 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2332 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2333 type == FW_PORT_TYPE_BT_XAUI) {
2335 if (caps & FW_PORT_CAP_SPEED_100M)
2336 v |= SUPPORTED_100baseT_Full;
2337 if (caps & FW_PORT_CAP_SPEED_1G)
2338 v |= SUPPORTED_1000baseT_Full;
2339 if (caps & FW_PORT_CAP_SPEED_10G)
2340 v |= SUPPORTED_10000baseT_Full;
2341 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2342 v |= SUPPORTED_Backplane;
2343 if (caps & FW_PORT_CAP_SPEED_1G)
2344 v |= SUPPORTED_1000baseKX_Full;
2345 if (caps & FW_PORT_CAP_SPEED_10G)
2346 v |= SUPPORTED_10000baseKX4_Full;
2347 } else if (type == FW_PORT_TYPE_KR)
2348 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2349 else if (type == FW_PORT_TYPE_BP_AP)
2350 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2351 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2352 else if (type == FW_PORT_TYPE_BP4_AP)
2353 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2354 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2355 SUPPORTED_10000baseKX4_Full;
2356 else if (type == FW_PORT_TYPE_FIBER_XFI ||
2357 type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2358 v |= SUPPORTED_FIBRE;
2359 else if (type == FW_PORT_TYPE_BP40_BA)
2360 v |= SUPPORTED_40000baseSR4_Full;
2362 if (caps & FW_PORT_CAP_ANEG)
2363 v |= SUPPORTED_Autoneg;
2367 static unsigned int to_fw_linkcaps(unsigned int caps)
2371 if (caps & ADVERTISED_100baseT_Full)
2372 v |= FW_PORT_CAP_SPEED_100M;
2373 if (caps & ADVERTISED_1000baseT_Full)
2374 v |= FW_PORT_CAP_SPEED_1G;
2375 if (caps & ADVERTISED_10000baseT_Full)
2376 v |= FW_PORT_CAP_SPEED_10G;
2377 if (caps & ADVERTISED_40000baseSR4_Full)
2378 v |= FW_PORT_CAP_SPEED_40G;
2382 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2384 const struct port_info *p = netdev_priv(dev);
2386 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2387 p->port_type == FW_PORT_TYPE_BT_XFI ||
2388 p->port_type == FW_PORT_TYPE_BT_XAUI)
2389 cmd->port = PORT_TP;
2390 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2391 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2392 cmd->port = PORT_FIBRE;
2393 else if (p->port_type == FW_PORT_TYPE_SFP ||
2394 p->port_type == FW_PORT_TYPE_QSFP_10G ||
2395 p->port_type == FW_PORT_TYPE_QSFP) {
2396 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2397 p->mod_type == FW_PORT_MOD_TYPE_SR ||
2398 p->mod_type == FW_PORT_MOD_TYPE_ER ||
2399 p->mod_type == FW_PORT_MOD_TYPE_LRM)
2400 cmd->port = PORT_FIBRE;
2401 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2402 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2403 cmd->port = PORT_DA;
2405 cmd->port = PORT_OTHER;
2407 cmd->port = PORT_OTHER;
2409 if (p->mdio_addr >= 0) {
2410 cmd->phy_address = p->mdio_addr;
2411 cmd->transceiver = XCVR_EXTERNAL;
2412 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2413 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2415 cmd->phy_address = 0; /* not really, but no better option */
2416 cmd->transceiver = XCVR_INTERNAL;
2417 cmd->mdio_support = 0;
2420 cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2421 cmd->advertising = from_fw_linkcaps(p->port_type,
2422 p->link_cfg.advertising);
2423 ethtool_cmd_speed_set(cmd,
2424 netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2425 cmd->duplex = DUPLEX_FULL;
2426 cmd->autoneg = p->link_cfg.autoneg;
2432 static unsigned int speed_to_caps(int speed)
2435 return FW_PORT_CAP_SPEED_100M;
2437 return FW_PORT_CAP_SPEED_1G;
2439 return FW_PORT_CAP_SPEED_10G;
2441 return FW_PORT_CAP_SPEED_40G;
2445 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2448 struct port_info *p = netdev_priv(dev);
2449 struct link_config *lc = &p->link_cfg;
2450 u32 speed = ethtool_cmd_speed(cmd);
2452 if (cmd->duplex != DUPLEX_FULL) /* only full-duplex supported */
2455 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2457 * PHY offers a single speed. See if that's what's
2460 if (cmd->autoneg == AUTONEG_DISABLE &&
2461 (lc->supported & speed_to_caps(speed)))
2466 if (cmd->autoneg == AUTONEG_DISABLE) {
2467 cap = speed_to_caps(speed);
2469 if (!(lc->supported & cap) ||
2474 lc->requested_speed = cap;
2475 lc->advertising = 0;
2477 cap = to_fw_linkcaps(cmd->advertising);
2478 if (!(lc->supported & cap))
2480 lc->requested_speed = 0;
2481 lc->advertising = cap | FW_PORT_CAP_ANEG;
2483 lc->autoneg = cmd->autoneg;
2485 if (netif_running(dev))
2486 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2491 static void get_pauseparam(struct net_device *dev,
2492 struct ethtool_pauseparam *epause)
2494 struct port_info *p = netdev_priv(dev);
2496 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2497 epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2498 epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2501 static int set_pauseparam(struct net_device *dev,
2502 struct ethtool_pauseparam *epause)
2504 struct port_info *p = netdev_priv(dev);
2505 struct link_config *lc = &p->link_cfg;
2507 if (epause->autoneg == AUTONEG_DISABLE)
2508 lc->requested_fc = 0;
2509 else if (lc->supported & FW_PORT_CAP_ANEG)
2510 lc->requested_fc = PAUSE_AUTONEG;
2514 if (epause->rx_pause)
2515 lc->requested_fc |= PAUSE_RX;
2516 if (epause->tx_pause)
2517 lc->requested_fc |= PAUSE_TX;
2518 if (netif_running(dev))
2519 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2524 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2526 const struct port_info *pi = netdev_priv(dev);
2527 const struct sge *s = &pi->adapter->sge;
2529 e->rx_max_pending = MAX_RX_BUFFERS;
2530 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2531 e->rx_jumbo_max_pending = 0;
2532 e->tx_max_pending = MAX_TXQ_ENTRIES;
2534 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2535 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2536 e->rx_jumbo_pending = 0;
2537 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2540 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2543 const struct port_info *pi = netdev_priv(dev);
2544 struct adapter *adapter = pi->adapter;
2545 struct sge *s = &adapter->sge;
2547 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2548 e->tx_pending > MAX_TXQ_ENTRIES ||
2549 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2550 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2551 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2554 if (adapter->flags & FULL_INIT_DONE)
2557 for (i = 0; i < pi->nqsets; ++i) {
2558 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2559 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2560 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2565 static int closest_timer(const struct sge *s, int time)
2567 int i, delta, match = 0, min_delta = INT_MAX;
2569 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2570 delta = time - s->timer_val[i];
2573 if (delta < min_delta) {
2581 static int closest_thres(const struct sge *s, int thres)
2583 int i, delta, match = 0, min_delta = INT_MAX;
2585 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2586 delta = thres - s->counter_val[i];
2589 if (delta < min_delta) {
2598 * Return a queue's interrupt hold-off time in us. 0 means no timer.
2600 static unsigned int qtimer_val(const struct adapter *adap,
2601 const struct sge_rspq *q)
2603 unsigned int idx = q->intr_params >> 1;
2605 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2609 * set_rspq_intr_params - set a queue's interrupt holdoff parameters
2611 * @us: the hold-off time in us, or 0 to disable timer
2612 * @cnt: the hold-off packet count, or 0 to disable counter
2614 * Sets an Rx queue's interrupt hold-off time and packet count. At least
2615 * one of the two needs to be enabled for the queue to generate interrupts.
2617 static int set_rspq_intr_params(struct sge_rspq *q,
2618 unsigned int us, unsigned int cnt)
2620 struct adapter *adap = q->adap;
2622 if ((us | cnt) == 0)
2629 new_idx = closest_thres(&adap->sge, cnt);
2630 if (q->desc && q->pktcnt_idx != new_idx) {
2631 /* the queue has already been created, update it */
2632 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
2633 FW_PARAMS_PARAM_X_V(
2634 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2635 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
2636 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2641 q->pktcnt_idx = new_idx;
2644 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2645 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2650 * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2651 * @dev: the network device
2652 * @us: the hold-off time in us, or 0 to disable timer
2653 * @cnt: the hold-off packet count, or 0 to disable counter
2655 * Set the RX interrupt hold-off parameters for a network device.
2657 static int set_rx_intr_params(struct net_device *dev,
2658 unsigned int us, unsigned int cnt)
2661 struct port_info *pi = netdev_priv(dev);
2662 struct adapter *adap = pi->adapter;
2663 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2665 for (i = 0; i < pi->nqsets; i++, q++) {
2666 err = set_rspq_intr_params(&q->rspq, us, cnt);
2673 static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
2676 struct port_info *pi = netdev_priv(dev);
2677 struct adapter *adap = pi->adapter;
2678 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2680 for (i = 0; i < pi->nqsets; i++, q++)
2681 q->rspq.adaptive_rx = adaptive_rx;
2686 static int get_adaptive_rx_setting(struct net_device *dev)
2688 struct port_info *pi = netdev_priv(dev);
2689 struct adapter *adap = pi->adapter;
2690 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2692 return q->rspq.adaptive_rx;
2695 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2697 set_adaptive_rx_setting(dev, c->use_adaptive_rx_coalesce);
2698 return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2699 c->rx_max_coalesced_frames);
2702 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2704 const struct port_info *pi = netdev_priv(dev);
2705 const struct adapter *adap = pi->adapter;
2706 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2708 c->rx_coalesce_usecs = qtimer_val(adap, rq);
2709 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2710 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2711 c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
2716 * eeprom_ptov - translate a physical EEPROM address to virtual
2717 * @phys_addr: the physical EEPROM address
2718 * @fn: the PCI function number
2719 * @sz: size of function-specific area
2721 * Translate a physical EEPROM address to virtual. The first 1K is
2722 * accessed through virtual addresses starting at 31K, the rest is
2723 * accessed through virtual addresses starting at 0.
2725 * The mapping is as follows:
2726 * [0..1K) -> [31K..32K)
2727 * [1K..1K+A) -> [31K-A..31K)
2728 * [1K+A..ES) -> [0..ES-A-1K)
2730 * where A = @fn * @sz, and ES = EEPROM size.
2732 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2735 if (phys_addr < 1024)
2736 return phys_addr + (31 << 10);
2737 if (phys_addr < 1024 + fn)
2738 return 31744 - fn + phys_addr - 1024;
2739 if (phys_addr < EEPROMSIZE)
2740 return phys_addr - 1024 - fn;
2745 * The next two routines implement eeprom read/write from physical addresses.
2747 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2749 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2752 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2753 return vaddr < 0 ? vaddr : 0;
2756 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2758 int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2761 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2762 return vaddr < 0 ? vaddr : 0;
2765 #define EEPROM_MAGIC 0x38E2F10C
2767 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2771 struct adapter *adapter = netdev2adap(dev);
2773 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2777 e->magic = EEPROM_MAGIC;
2778 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2779 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2782 memcpy(data, buf + e->offset, e->len);
2787 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2792 u32 aligned_offset, aligned_len, *p;
2793 struct adapter *adapter = netdev2adap(dev);
2795 if (eeprom->magic != EEPROM_MAGIC)
2798 aligned_offset = eeprom->offset & ~3;
2799 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2801 if (adapter->fn > 0) {
2802 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2804 if (aligned_offset < start ||
2805 aligned_offset + aligned_len > start + EEPROMPFSIZE)
2809 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2811 * RMW possibly needed for first or last words.
2813 buf = kmalloc(aligned_len, GFP_KERNEL);
2816 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2817 if (!err && aligned_len > 4)
2818 err = eeprom_rd_phys(adapter,
2819 aligned_offset + aligned_len - 4,
2820 (u32 *)&buf[aligned_len - 4]);
2823 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2827 err = t4_seeprom_wp(adapter, false);
2831 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2832 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2833 aligned_offset += 4;
2837 err = t4_seeprom_wp(adapter, true);
2844 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2847 const struct firmware *fw;
2848 struct adapter *adap = netdev2adap(netdev);
2849 unsigned int mbox = PCIE_FW_MASTER_M + 1;
2851 ef->data[sizeof(ef->data) - 1] = '\0';
2852 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2856 /* If the adapter has been fully initialized then we'll go ahead and
2857 * try to get the firmware's cooperation in upgrading to the new
2858 * firmware image otherwise we'll try to do the entire job from the
2859 * host ... and we always "force" the operation in this path.
2861 if (adap->flags & FULL_INIT_DONE)
2864 ret = t4_fw_upgrade(adap, mbox, fw->data, fw->size, 1);
2865 release_firmware(fw);
2867 dev_info(adap->pdev_dev, "loaded firmware %s,"
2868 " reload cxgb4 driver\n", ef->data);
2872 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2873 #define BCAST_CRC 0xa0ccc1a6
2875 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2877 wol->supported = WAKE_BCAST | WAKE_MAGIC;
2878 wol->wolopts = netdev2adap(dev)->wol;
2879 memset(&wol->sopass, 0, sizeof(wol->sopass));
2882 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2885 struct port_info *pi = netdev_priv(dev);
2887 if (wol->wolopts & ~WOL_SUPPORTED)
2889 t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2890 (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2891 if (wol->wolopts & WAKE_BCAST) {
2892 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2895 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2896 ~6ULL, ~0ULL, BCAST_CRC, true);
2898 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2902 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2904 const struct port_info *pi = netdev_priv(dev);
2905 netdev_features_t changed = dev->features ^ features;
2908 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2911 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2913 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2915 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
2919 static u32 get_rss_table_size(struct net_device *dev)
2921 const struct port_info *pi = netdev_priv(dev);
2923 return pi->rss_size;
2926 static int get_rss_table(struct net_device *dev, u32 *p, u8 *key, u8 *hfunc)
2928 const struct port_info *pi = netdev_priv(dev);
2929 unsigned int n = pi->rss_size;
2932 *hfunc = ETH_RSS_HASH_TOP;
2940 static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key,
2944 struct port_info *pi = netdev_priv(dev);
2946 /* We require at least one supported parameter to be changed and no
2947 * change in any of the unsupported parameters
2950 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
2955 for (i = 0; i < pi->rss_size; i++)
2957 if (pi->adapter->flags & FULL_INIT_DONE)
2958 return write_rss(pi, pi->rss);
2962 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2965 const struct port_info *pi = netdev_priv(dev);
2967 switch (info->cmd) {
2968 case ETHTOOL_GRXFH: {
2969 unsigned int v = pi->rss_mode;
2972 switch (info->flow_type) {
2974 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F)
2975 info->data = RXH_IP_SRC | RXH_IP_DST |
2976 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2977 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2978 info->data = RXH_IP_SRC | RXH_IP_DST;
2981 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) &&
2982 (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
2983 info->data = RXH_IP_SRC | RXH_IP_DST |
2984 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2985 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2986 info->data = RXH_IP_SRC | RXH_IP_DST;
2989 case AH_ESP_V4_FLOW:
2991 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
2992 info->data = RXH_IP_SRC | RXH_IP_DST;
2995 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F)
2996 info->data = RXH_IP_SRC | RXH_IP_DST |
2997 RXH_L4_B_0_1 | RXH_L4_B_2_3;
2998 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
2999 info->data = RXH_IP_SRC | RXH_IP_DST;
3002 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) &&
3003 (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
3004 info->data = RXH_IP_SRC | RXH_IP_DST |
3005 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3006 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
3007 info->data = RXH_IP_SRC | RXH_IP_DST;
3010 case AH_ESP_V6_FLOW:
3012 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
3013 info->data = RXH_IP_SRC | RXH_IP_DST;
3018 case ETHTOOL_GRXRINGS:
3019 info->data = pi->nqsets;
3025 static const struct ethtool_ops cxgb_ethtool_ops = {
3026 .get_settings = get_settings,
3027 .set_settings = set_settings,
3028 .get_drvinfo = get_drvinfo,
3029 .get_msglevel = get_msglevel,
3030 .set_msglevel = set_msglevel,
3031 .get_ringparam = get_sge_param,
3032 .set_ringparam = set_sge_param,
3033 .get_coalesce = get_coalesce,
3034 .set_coalesce = set_coalesce,
3035 .get_eeprom_len = get_eeprom_len,
3036 .get_eeprom = get_eeprom,
3037 .set_eeprom = set_eeprom,
3038 .get_pauseparam = get_pauseparam,
3039 .set_pauseparam = set_pauseparam,
3040 .get_link = ethtool_op_get_link,
3041 .get_strings = get_strings,
3042 .set_phys_id = identify_port,
3043 .nway_reset = restart_autoneg,
3044 .get_sset_count = get_sset_count,
3045 .get_ethtool_stats = get_stats,
3046 .get_regs_len = get_regs_len,
3047 .get_regs = get_regs,
3050 .get_rxnfc = get_rxnfc,
3051 .get_rxfh_indir_size = get_rss_table_size,
3052 .get_rxfh = get_rss_table,
3053 .set_rxfh = set_rss_table,
3054 .flash_device = set_flash,
3057 static int setup_debugfs(struct adapter *adap)
3059 if (IS_ERR_OR_NULL(adap->debugfs_root))
3062 #ifdef CONFIG_DEBUG_FS
3063 t4_setup_debugfs(adap);
3069 * upper-layer driver support
3073 * Allocate an active-open TID and set it to the supplied value.
3075 int cxgb4_alloc_atid(struct tid_info *t, void *data)
3079 spin_lock_bh(&t->atid_lock);
3081 union aopen_entry *p = t->afree;
3083 atid = (p - t->atid_tab) + t->atid_base;
3088 spin_unlock_bh(&t->atid_lock);
3091 EXPORT_SYMBOL(cxgb4_alloc_atid);
3094 * Release an active-open TID.
3096 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3098 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
3100 spin_lock_bh(&t->atid_lock);
3104 spin_unlock_bh(&t->atid_lock);
3106 EXPORT_SYMBOL(cxgb4_free_atid);
3109 * Allocate a server TID and set it to the supplied value.
3111 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3115 spin_lock_bh(&t->stid_lock);
3116 if (family == PF_INET) {
3117 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3118 if (stid < t->nstids)
3119 __set_bit(stid, t->stid_bmap);
3123 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3128 t->stid_tab[stid].data = data;
3129 stid += t->stid_base;
3130 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3131 * This is equivalent to 4 TIDs. With CLIP enabled it
3134 if (family == PF_INET)
3137 t->stids_in_use += 4;
3139 spin_unlock_bh(&t->stid_lock);
3142 EXPORT_SYMBOL(cxgb4_alloc_stid);
3144 /* Allocate a server filter TID and set it to the supplied value.
3146 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3150 spin_lock_bh(&t->stid_lock);
3151 if (family == PF_INET) {
3152 stid = find_next_zero_bit(t->stid_bmap,
3153 t->nstids + t->nsftids, t->nstids);
3154 if (stid < (t->nstids + t->nsftids))
3155 __set_bit(stid, t->stid_bmap);
3162 t->stid_tab[stid].data = data;
3164 stid += t->sftid_base;
3167 spin_unlock_bh(&t->stid_lock);
3170 EXPORT_SYMBOL(cxgb4_alloc_sftid);
3172 /* Release a server TID.
3174 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3176 /* Is it a server filter TID? */
3177 if (t->nsftids && (stid >= t->sftid_base)) {
3178 stid -= t->sftid_base;
3181 stid -= t->stid_base;
3184 spin_lock_bh(&t->stid_lock);
3185 if (family == PF_INET)
3186 __clear_bit(stid, t->stid_bmap);
3188 bitmap_release_region(t->stid_bmap, stid, 2);
3189 t->stid_tab[stid].data = NULL;
3190 if (family == PF_INET)
3193 t->stids_in_use -= 4;
3194 spin_unlock_bh(&t->stid_lock);
3196 EXPORT_SYMBOL(cxgb4_free_stid);
3199 * Populate a TID_RELEASE WR. Caller must properly size the skb.
3201 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3204 struct cpl_tid_release *req;
3206 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3207 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3208 INIT_TP_WR(req, tid);
3209 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3213 * Queue a TID release request and if necessary schedule a work queue to
3216 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3219 void **p = &t->tid_tab[tid];
3220 struct adapter *adap = container_of(t, struct adapter, tids);
3222 spin_lock_bh(&adap->tid_release_lock);
3223 *p = adap->tid_release_head;
3224 /* Low 2 bits encode the Tx channel number */
3225 adap->tid_release_head = (void **)((uintptr_t)p | chan);
3226 if (!adap->tid_release_task_busy) {
3227 adap->tid_release_task_busy = true;
3228 queue_work(adap->workq, &adap->tid_release_task);
3230 spin_unlock_bh(&adap->tid_release_lock);
3234 * Process the list of pending TID release requests.
3236 static void process_tid_release_list(struct work_struct *work)
3238 struct sk_buff *skb;
3239 struct adapter *adap;
3241 adap = container_of(work, struct adapter, tid_release_task);
3243 spin_lock_bh(&adap->tid_release_lock);
3244 while (adap->tid_release_head) {
3245 void **p = adap->tid_release_head;
3246 unsigned int chan = (uintptr_t)p & 3;
3247 p = (void *)p - chan;
3249 adap->tid_release_head = *p;
3251 spin_unlock_bh(&adap->tid_release_lock);
3253 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3255 schedule_timeout_uninterruptible(1);
3257 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3258 t4_ofld_send(adap, skb);
3259 spin_lock_bh(&adap->tid_release_lock);
3261 adap->tid_release_task_busy = false;
3262 spin_unlock_bh(&adap->tid_release_lock);
3266 * Release a TID and inform HW. If we are unable to allocate the release
3267 * message we defer to a work queue.
3269 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3272 struct sk_buff *skb;
3273 struct adapter *adap = container_of(t, struct adapter, tids);
3275 old = t->tid_tab[tid];
3276 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3278 t->tid_tab[tid] = NULL;
3279 mk_tid_release(skb, chan, tid);
3280 t4_ofld_send(adap, skb);
3282 cxgb4_queue_tid_release(t, chan, tid);
3284 atomic_dec(&t->tids_in_use);
3286 EXPORT_SYMBOL(cxgb4_remove_tid);
3289 * Allocate and initialize the TID tables. Returns 0 on success.
3291 static int tid_init(struct tid_info *t)
3294 unsigned int stid_bmap_size;
3295 unsigned int natids = t->natids;
3296 struct adapter *adap = container_of(t, struct adapter, tids);
3298 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
3299 size = t->ntids * sizeof(*t->tid_tab) +
3300 natids * sizeof(*t->atid_tab) +
3301 t->nstids * sizeof(*t->stid_tab) +
3302 t->nsftids * sizeof(*t->stid_tab) +
3303 stid_bmap_size * sizeof(long) +
3304 t->nftids * sizeof(*t->ftid_tab) +
3305 t->nsftids * sizeof(*t->ftid_tab);
3307 t->tid_tab = t4_alloc_mem(size);
3311 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3312 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
3313 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
3314 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
3315 spin_lock_init(&t->stid_lock);
3316 spin_lock_init(&t->atid_lock);
3318 t->stids_in_use = 0;
3320 t->atids_in_use = 0;
3321 atomic_set(&t->tids_in_use, 0);
3323 /* Setup the free list for atid_tab and clear the stid bitmap. */
3326 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3327 t->afree = t->atid_tab;
3329 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
3330 /* Reserve stid 0 for T4/T5 adapters */
3331 if (!t->stid_base &&
3332 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3333 __set_bit(0, t->stid_bmap);
3338 int cxgb4_clip_get(const struct net_device *dev,
3339 const struct in6_addr *lip)
3341 struct adapter *adap;
3342 struct fw_clip_cmd c;
3344 adap = netdev2adap(dev);
3345 memset(&c, 0, sizeof(c));
3346 c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3347 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3348 c.alloc_to_len16 = htonl(FW_CLIP_CMD_ALLOC_F | FW_LEN16(c));
3349 c.ip_hi = *(__be64 *)(lip->s6_addr);
3350 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3351 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3353 EXPORT_SYMBOL(cxgb4_clip_get);
3355 int cxgb4_clip_release(const struct net_device *dev,
3356 const struct in6_addr *lip)
3358 struct adapter *adap;
3359 struct fw_clip_cmd c;
3361 adap = netdev2adap(dev);
3362 memset(&c, 0, sizeof(c));
3363 c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3364 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3365 c.alloc_to_len16 = htonl(FW_CLIP_CMD_FREE_F | FW_LEN16(c));
3366 c.ip_hi = *(__be64 *)(lip->s6_addr);
3367 c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3368 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3370 EXPORT_SYMBOL(cxgb4_clip_release);
3373 * cxgb4_create_server - create an IP server
3375 * @stid: the server TID
3376 * @sip: local IP address to bind server to
3377 * @sport: the server's TCP port
3378 * @queue: queue to direct messages from this server to
3380 * Create an IP server for the given port and address.
3381 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3383 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
3384 __be32 sip, __be16 sport, __be16 vlan,
3388 struct sk_buff *skb;
3389 struct adapter *adap;
3390 struct cpl_pass_open_req *req;
3393 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3397 adap = netdev2adap(dev);
3398 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3400 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3401 req->local_port = sport;
3402 req->peer_port = htons(0);
3403 req->local_ip = sip;
3404 req->peer_ip = htonl(0);
3405 chan = rxq_to_chan(&adap->sge, queue);
3406 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3407 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3408 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3409 ret = t4_mgmt_tx(adap, skb);
3410 return net_xmit_eval(ret);
3412 EXPORT_SYMBOL(cxgb4_create_server);
3414 /* cxgb4_create_server6 - create an IPv6 server
3416 * @stid: the server TID
3417 * @sip: local IPv6 address to bind server to
3418 * @sport: the server's TCP port
3419 * @queue: queue to direct messages from this server to
3421 * Create an IPv6 server for the given port and address.
3422 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3424 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3425 const struct in6_addr *sip, __be16 sport,
3429 struct sk_buff *skb;
3430 struct adapter *adap;
3431 struct cpl_pass_open_req6 *req;
3434 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3438 adap = netdev2adap(dev);
3439 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3441 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3442 req->local_port = sport;
3443 req->peer_port = htons(0);
3444 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3445 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3446 req->peer_ip_hi = cpu_to_be64(0);
3447 req->peer_ip_lo = cpu_to_be64(0);
3448 chan = rxq_to_chan(&adap->sge, queue);
3449 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3450 req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3451 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3452 ret = t4_mgmt_tx(adap, skb);
3453 return net_xmit_eval(ret);
3455 EXPORT_SYMBOL(cxgb4_create_server6);
3457 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3458 unsigned int queue, bool ipv6)
3460 struct sk_buff *skb;
3461 struct adapter *adap;
3462 struct cpl_close_listsvr_req *req;
3465 adap = netdev2adap(dev);
3467 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3471 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3473 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3474 req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3475 LISTSVR_IPV6(0)) | QUEUENO(queue));
3476 ret = t4_mgmt_tx(adap, skb);
3477 return net_xmit_eval(ret);
3479 EXPORT_SYMBOL(cxgb4_remove_server);
3482 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3483 * @mtus: the HW MTU table
3484 * @mtu: the target MTU
3485 * @idx: index of selected entry in the MTU table
3487 * Returns the index and the value in the HW MTU table that is closest to
3488 * but does not exceed @mtu, unless @mtu is smaller than any value in the
3489 * table, in which case that smallest available value is selected.
3491 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3496 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3502 EXPORT_SYMBOL(cxgb4_best_mtu);
3505 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3506 * @mtus: the HW MTU table
3507 * @header_size: Header Size
3508 * @data_size_max: maximum Data Segment Size
3509 * @data_size_align: desired Data Segment Size Alignment (2^N)
3510 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3512 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
3513 * MTU Table based solely on a Maximum MTU parameter, we break that
3514 * parameter up into a Header Size and Maximum Data Segment Size, and
3515 * provide a desired Data Segment Size Alignment. If we find an MTU in
3516 * the Hardware MTU Table which will result in a Data Segment Size with
3517 * the requested alignment _and_ that MTU isn't "too far" from the
3518 * closest MTU, then we'll return that rather than the closest MTU.
3520 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3521 unsigned short header_size,
3522 unsigned short data_size_max,
3523 unsigned short data_size_align,
3524 unsigned int *mtu_idxp)
3526 unsigned short max_mtu = header_size + data_size_max;
3527 unsigned short data_size_align_mask = data_size_align - 1;
3528 int mtu_idx, aligned_mtu_idx;
3530 /* Scan the MTU Table till we find an MTU which is larger than our
3531 * Maximum MTU or we reach the end of the table. Along the way,
3532 * record the last MTU found, if any, which will result in a Data
3533 * Segment Length matching the requested alignment.
3535 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3536 unsigned short data_size = mtus[mtu_idx] - header_size;
3538 /* If this MTU minus the Header Size would result in a
3539 * Data Segment Size of the desired alignment, remember it.
3541 if ((data_size & data_size_align_mask) == 0)
3542 aligned_mtu_idx = mtu_idx;
3544 /* If we're not at the end of the Hardware MTU Table and the
3545 * next element is larger than our Maximum MTU, drop out of
3548 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3552 /* If we fell out of the loop because we ran to the end of the table,
3553 * then we just have to use the last [largest] entry.
3555 if (mtu_idx == NMTUS)
3558 /* If we found an MTU which resulted in the requested Data Segment
3559 * Length alignment and that's "not far" from the largest MTU which is
3560 * less than or equal to the maximum MTU, then use that.
3562 if (aligned_mtu_idx >= 0 &&
3563 mtu_idx - aligned_mtu_idx <= 1)
3564 mtu_idx = aligned_mtu_idx;
3566 /* If the caller has passed in an MTU Index pointer, pass the
3567 * MTU Index back. Return the MTU value.
3570 *mtu_idxp = mtu_idx;
3571 return mtus[mtu_idx];
3573 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3576 * cxgb4_port_chan - get the HW channel of a port
3577 * @dev: the net device for the port
3579 * Return the HW Tx channel of the given port.
3581 unsigned int cxgb4_port_chan(const struct net_device *dev)
3583 return netdev2pinfo(dev)->tx_chan;
3585 EXPORT_SYMBOL(cxgb4_port_chan);
3587 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3589 struct adapter *adap = netdev2adap(dev);
3590 u32 v1, v2, lp_count, hp_count;
3592 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3593 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3594 if (is_t4(adap->params.chip)) {
3595 lp_count = G_LP_COUNT(v1);
3596 hp_count = G_HP_COUNT(v1);
3598 lp_count = G_LP_COUNT_T5(v1);
3599 hp_count = G_HP_COUNT_T5(v2);
3601 return lpfifo ? lp_count : hp_count;
3603 EXPORT_SYMBOL(cxgb4_dbfifo_count);
3606 * cxgb4_port_viid - get the VI id of a port
3607 * @dev: the net device for the port
3609 * Return the VI id of the given port.
3611 unsigned int cxgb4_port_viid(const struct net_device *dev)
3613 return netdev2pinfo(dev)->viid;
3615 EXPORT_SYMBOL(cxgb4_port_viid);
3618 * cxgb4_port_idx - get the index of a port
3619 * @dev: the net device for the port
3621 * Return the index of the given port.
3623 unsigned int cxgb4_port_idx(const struct net_device *dev)
3625 return netdev2pinfo(dev)->port_id;
3627 EXPORT_SYMBOL(cxgb4_port_idx);
3629 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3630 struct tp_tcp_stats *v6)
3632 struct adapter *adap = pci_get_drvdata(pdev);
3634 spin_lock(&adap->stats_lock);
3635 t4_tp_get_tcp_stats(adap, v4, v6);
3636 spin_unlock(&adap->stats_lock);
3638 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3640 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3641 const unsigned int *pgsz_order)
3643 struct adapter *adap = netdev2adap(dev);
3645 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3646 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3647 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3648 HPZ3(pgsz_order[3]));
3650 EXPORT_SYMBOL(cxgb4_iscsi_init);
3652 int cxgb4_flush_eq_cache(struct net_device *dev)
3654 struct adapter *adap = netdev2adap(dev);
3657 ret = t4_fwaddrspace_write(adap, adap->mbox,
3658 0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3661 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3663 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3665 u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3669 spin_lock(&adap->win0_lock);
3670 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3671 sizeof(indices), (__be32 *)&indices,
3673 spin_unlock(&adap->win0_lock);
3675 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3676 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3681 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3684 struct adapter *adap = netdev2adap(dev);
3685 u16 hw_pidx, hw_cidx;
3688 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3692 if (pidx != hw_pidx) {
3695 if (pidx >= hw_pidx)
3696 delta = pidx - hw_pidx;
3698 delta = size - hw_pidx + pidx;
3700 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3701 QID(qid) | PIDX(delta));
3706 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3708 void cxgb4_disable_db_coalescing(struct net_device *dev)
3710 struct adapter *adap;
3712 adap = netdev2adap(dev);
3713 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3716 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3718 void cxgb4_enable_db_coalescing(struct net_device *dev)
3720 struct adapter *adap;
3722 adap = netdev2adap(dev);
3723 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3725 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3727 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
3729 struct adapter *adap;
3730 u32 offset, memtype, memaddr;
3731 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
3732 u32 edc0_end, edc1_end, mc0_end, mc1_end;
3735 adap = netdev2adap(dev);
3737 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
3739 /* Figure out where the offset lands in the Memory Type/Address scheme.
3740 * This code assumes that the memory is laid out starting at offset 0
3741 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3742 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
3743 * MC0, and some have both MC0 and MC1.
3745 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
3746 edc0_size = EDRAM0_SIZE_G(size) << 20;
3747 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
3748 edc1_size = EDRAM1_SIZE_G(size) << 20;
3749 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
3750 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
3752 edc0_end = edc0_size;
3753 edc1_end = edc0_end + edc1_size;
3754 mc0_end = edc1_end + mc0_size;
3756 if (offset < edc0_end) {
3759 } else if (offset < edc1_end) {
3761 memaddr = offset - edc0_end;
3763 if (offset < mc0_end) {
3765 memaddr = offset - edc1_end;
3766 } else if (is_t4(adap->params.chip)) {
3767 /* T4 only has a single memory channel */
3770 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
3771 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
3772 mc1_end = mc0_end + mc1_size;
3773 if (offset < mc1_end) {
3775 memaddr = offset - mc0_end;
3777 /* offset beyond the end of any memory */
3783 spin_lock(&adap->win0_lock);
3784 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
3785 spin_unlock(&adap->win0_lock);
3789 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
3793 EXPORT_SYMBOL(cxgb4_read_tpte);
3795 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
3798 struct adapter *adap;
3800 adap = netdev2adap(dev);
3801 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
3802 hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
3804 return ((u64)hi << 32) | (u64)lo;
3806 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
3808 static struct pci_driver cxgb4_driver;
3810 static void check_neigh_update(struct neighbour *neigh)
3812 const struct device *parent;
3813 const struct net_device *netdev = neigh->dev;
3815 if (netdev->priv_flags & IFF_802_1Q_VLAN)
3816 netdev = vlan_dev_real_dev(netdev);
3817 parent = netdev->dev.parent;
3818 if (parent && parent->driver == &cxgb4_driver.driver)
3819 t4_l2t_update(dev_get_drvdata(parent), neigh);
3822 static int netevent_cb(struct notifier_block *nb, unsigned long event,
3826 case NETEVENT_NEIGH_UPDATE:
3827 check_neigh_update(data);
3829 case NETEVENT_REDIRECT:
3836 static bool netevent_registered;
3837 static struct notifier_block cxgb4_netevent_nb = {
3838 .notifier_call = netevent_cb
3841 static void drain_db_fifo(struct adapter *adap, int usecs)
3843 u32 v1, v2, lp_count, hp_count;
3846 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3847 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3848 if (is_t4(adap->params.chip)) {
3849 lp_count = G_LP_COUNT(v1);
3850 hp_count = G_HP_COUNT(v1);
3852 lp_count = G_LP_COUNT_T5(v1);
3853 hp_count = G_HP_COUNT_T5(v2);
3856 if (lp_count == 0 && hp_count == 0)
3858 set_current_state(TASK_UNINTERRUPTIBLE);
3859 schedule_timeout(usecs_to_jiffies(usecs));
3863 static void disable_txq_db(struct sge_txq *q)
3865 unsigned long flags;
3867 spin_lock_irqsave(&q->db_lock, flags);
3869 spin_unlock_irqrestore(&q->db_lock, flags);
3872 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3874 spin_lock_irq(&q->db_lock);
3875 if (q->db_pidx_inc) {
3876 /* Make sure that all writes to the TX descriptors
3877 * are committed before we tell HW about them.
3880 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3881 QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3885 spin_unlock_irq(&q->db_lock);
3888 static void disable_dbs(struct adapter *adap)
3892 for_each_ethrxq(&adap->sge, i)
3893 disable_txq_db(&adap->sge.ethtxq[i].q);
3894 for_each_ofldrxq(&adap->sge, i)
3895 disable_txq_db(&adap->sge.ofldtxq[i].q);
3896 for_each_port(adap, i)
3897 disable_txq_db(&adap->sge.ctrlq[i].q);
3900 static void enable_dbs(struct adapter *adap)
3904 for_each_ethrxq(&adap->sge, i)
3905 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3906 for_each_ofldrxq(&adap->sge, i)
3907 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3908 for_each_port(adap, i)
3909 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
3912 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3914 if (adap->uld_handle[CXGB4_ULD_RDMA])
3915 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3919 static void process_db_full(struct work_struct *work)
3921 struct adapter *adap;
3923 adap = container_of(work, struct adapter, db_full_task);
3925 drain_db_fifo(adap, dbfifo_drain_delay);
3927 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3928 t4_set_reg_field(adap, SGE_INT_ENABLE3,
3929 DBFIFO_HP_INT | DBFIFO_LP_INT,
3930 DBFIFO_HP_INT | DBFIFO_LP_INT);
3933 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
3935 u16 hw_pidx, hw_cidx;
3938 spin_lock_irq(&q->db_lock);
3939 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
3942 if (q->db_pidx != hw_pidx) {
3945 if (q->db_pidx >= hw_pidx)
3946 delta = q->db_pidx - hw_pidx;
3948 delta = q->size - hw_pidx + q->db_pidx;
3950 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3951 QID(q->cntxt_id) | PIDX(delta));
3956 spin_unlock_irq(&q->db_lock);
3958 CH_WARN(adap, "DB drop recovery failed.\n");
3960 static void recover_all_queues(struct adapter *adap)
3964 for_each_ethrxq(&adap->sge, i)
3965 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
3966 for_each_ofldrxq(&adap->sge, i)
3967 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
3968 for_each_port(adap, i)
3969 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
3972 static void process_db_drop(struct work_struct *work)
3974 struct adapter *adap;
3976 adap = container_of(work, struct adapter, db_drop_task);
3978 if (is_t4(adap->params.chip)) {
3979 drain_db_fifo(adap, dbfifo_drain_delay);
3980 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
3981 drain_db_fifo(adap, dbfifo_drain_delay);
3982 recover_all_queues(adap);
3983 drain_db_fifo(adap, dbfifo_drain_delay);
3985 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3987 u32 dropped_db = t4_read_reg(adap, 0x010ac);
3988 u16 qid = (dropped_db >> 15) & 0x1ffff;
3989 u16 pidx_inc = dropped_db & 0x1fff;
3991 unsigned short udb_density;
3992 unsigned long qpshift;
3996 dev_warn(adap->pdev_dev,
3997 "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
3999 (dropped_db >> 14) & 1,
4000 (dropped_db >> 13) & 1,
4003 drain_db_fifo(adap, 1);
4005 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4006 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4007 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4008 qpshift = PAGE_SHIFT - ilog2(udb_density);
4009 udb = qid << qpshift;
4011 page = udb / PAGE_SIZE;
4012 udb += (qid - (page * udb_density)) * 128;
4014 writel(PIDX(pidx_inc), adap->bar2 + udb + 8);
4016 /* Re-enable BAR2 WC */
4017 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4020 t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
4023 void t4_db_full(struct adapter *adap)
4025 if (is_t4(adap->params.chip)) {
4027 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4028 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4029 DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4030 queue_work(adap->workq, &adap->db_full_task);
4034 void t4_db_dropped(struct adapter *adap)
4036 if (is_t4(adap->params.chip)) {
4038 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4040 queue_work(adap->workq, &adap->db_drop_task);
4043 static void uld_attach(struct adapter *adap, unsigned int uld)
4046 struct cxgb4_lld_info lli;
4049 lli.pdev = adap->pdev;
4051 lli.l2t = adap->l2t;
4052 lli.tids = &adap->tids;
4053 lli.ports = adap->port;
4054 lli.vr = &adap->vres;
4055 lli.mtus = adap->params.mtus;
4056 if (uld == CXGB4_ULD_RDMA) {
4057 lli.rxq_ids = adap->sge.rdma_rxq;
4058 lli.ciq_ids = adap->sge.rdma_ciq;
4059 lli.nrxq = adap->sge.rdmaqs;
4060 lli.nciq = adap->sge.rdmaciqs;
4061 } else if (uld == CXGB4_ULD_ISCSI) {
4062 lli.rxq_ids = adap->sge.ofld_rxq;
4063 lli.nrxq = adap->sge.ofldqsets;
4065 lli.ntxq = adap->sge.ofldqsets;
4066 lli.nchan = adap->params.nports;
4067 lli.nports = adap->params.nports;
4068 lli.wr_cred = adap->params.ofldq_wr_cred;
4069 lli.adapter_type = adap->params.chip;
4070 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4071 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
4072 lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
4073 t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4075 lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
4076 t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4078 lli.filt_mode = adap->params.tp.vlan_pri_map;
4079 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4080 for (i = 0; i < NCHAN; i++)
4082 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4083 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4084 lli.fw_vers = adap->params.fw_vers;
4085 lli.dbfifo_int_thresh = dbfifo_int_thresh;
4086 lli.sge_ingpadboundary = adap->sge.fl_align;
4087 lli.sge_egrstatuspagesize = adap->sge.stat_len;
4088 lli.sge_pktshift = adap->sge.pktshift;
4089 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4090 lli.max_ordird_qp = adap->params.max_ordird_qp;
4091 lli.max_ird_adapter = adap->params.max_ird_adapter;
4092 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
4094 handle = ulds[uld].add(&lli);
4095 if (IS_ERR(handle)) {
4096 dev_warn(adap->pdev_dev,
4097 "could not attach to the %s driver, error %ld\n",
4098 uld_str[uld], PTR_ERR(handle));
4102 adap->uld_handle[uld] = handle;
4104 if (!netevent_registered) {
4105 register_netevent_notifier(&cxgb4_netevent_nb);
4106 netevent_registered = true;
4109 if (adap->flags & FULL_INIT_DONE)
4110 ulds[uld].state_change(handle, CXGB4_STATE_UP);
4113 static void attach_ulds(struct adapter *adap)
4117 spin_lock(&adap_rcu_lock);
4118 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4119 spin_unlock(&adap_rcu_lock);
4121 mutex_lock(&uld_mutex);
4122 list_add_tail(&adap->list_node, &adapter_list);
4123 for (i = 0; i < CXGB4_ULD_MAX; i++)
4125 uld_attach(adap, i);
4126 mutex_unlock(&uld_mutex);
4129 static void detach_ulds(struct adapter *adap)
4133 mutex_lock(&uld_mutex);
4134 list_del(&adap->list_node);
4135 for (i = 0; i < CXGB4_ULD_MAX; i++)
4136 if (adap->uld_handle[i]) {
4137 ulds[i].state_change(adap->uld_handle[i],
4138 CXGB4_STATE_DETACH);
4139 adap->uld_handle[i] = NULL;
4141 if (netevent_registered && list_empty(&adapter_list)) {
4142 unregister_netevent_notifier(&cxgb4_netevent_nb);
4143 netevent_registered = false;
4145 mutex_unlock(&uld_mutex);
4147 spin_lock(&adap_rcu_lock);
4148 list_del_rcu(&adap->rcu_node);
4149 spin_unlock(&adap_rcu_lock);
4152 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4156 mutex_lock(&uld_mutex);
4157 for (i = 0; i < CXGB4_ULD_MAX; i++)
4158 if (adap->uld_handle[i])
4159 ulds[i].state_change(adap->uld_handle[i], new_state);
4160 mutex_unlock(&uld_mutex);
4164 * cxgb4_register_uld - register an upper-layer driver
4165 * @type: the ULD type
4166 * @p: the ULD methods
4168 * Registers an upper-layer driver with this driver and notifies the ULD
4169 * about any presently available devices that support its type. Returns
4170 * %-EBUSY if a ULD of the same type is already registered.
4172 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4175 struct adapter *adap;
4177 if (type >= CXGB4_ULD_MAX)
4179 mutex_lock(&uld_mutex);
4180 if (ulds[type].add) {
4185 list_for_each_entry(adap, &adapter_list, list_node)
4186 uld_attach(adap, type);
4187 out: mutex_unlock(&uld_mutex);
4190 EXPORT_SYMBOL(cxgb4_register_uld);
4193 * cxgb4_unregister_uld - unregister an upper-layer driver
4194 * @type: the ULD type
4196 * Unregisters an existing upper-layer driver.
4198 int cxgb4_unregister_uld(enum cxgb4_uld type)
4200 struct adapter *adap;
4202 if (type >= CXGB4_ULD_MAX)
4204 mutex_lock(&uld_mutex);
4205 list_for_each_entry(adap, &adapter_list, list_node)
4206 adap->uld_handle[type] = NULL;
4207 ulds[type].add = NULL;
4208 mutex_unlock(&uld_mutex);
4211 EXPORT_SYMBOL(cxgb4_unregister_uld);
4213 /* Check if netdev on which event is occured belongs to us or not. Return
4214 * success (true) if it belongs otherwise failure (false).
4215 * Called with rcu_read_lock() held.
4217 #if IS_ENABLED(CONFIG_IPV6)
4218 static bool cxgb4_netdev(const struct net_device *netdev)
4220 struct adapter *adap;
4223 list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4224 for (i = 0; i < MAX_NPORTS; i++)
4225 if (adap->port[i] == netdev)
4230 static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4231 unsigned long event)
4233 int ret = NOTIFY_DONE;
4236 if (cxgb4_netdev(event_dev)) {
4239 ret = cxgb4_clip_get(event_dev, &ifa->addr);
4247 cxgb4_clip_release(event_dev, &ifa->addr);
4258 static int cxgb4_inet6addr_handler(struct notifier_block *this,
4259 unsigned long event, void *data)
4261 struct inet6_ifaddr *ifa = data;
4262 struct net_device *event_dev;
4263 int ret = NOTIFY_DONE;
4264 struct bonding *bond = netdev_priv(ifa->idev->dev);
4265 struct list_head *iter;
4266 struct slave *slave;
4267 struct pci_dev *first_pdev = NULL;
4269 if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4270 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4271 ret = clip_add(event_dev, ifa, event);
4272 } else if (ifa->idev->dev->flags & IFF_MASTER) {
4273 /* It is possible that two different adapters are bonded in one
4274 * bond. We need to find such different adapters and add clip
4275 * in all of them only once.
4277 bond_for_each_slave(bond, slave, iter) {
4279 ret = clip_add(slave->dev, ifa, event);
4280 /* If clip_add is success then only initialize
4281 * first_pdev since it means it is our device
4283 if (ret == NOTIFY_OK)
4284 first_pdev = to_pci_dev(
4285 slave->dev->dev.parent);
4286 } else if (first_pdev !=
4287 to_pci_dev(slave->dev->dev.parent))
4288 ret = clip_add(slave->dev, ifa, event);
4291 ret = clip_add(ifa->idev->dev, ifa, event);
4296 static struct notifier_block cxgb4_inet6addr_notifier = {
4297 .notifier_call = cxgb4_inet6addr_handler
4300 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4301 * a physical device.
4302 * The physical device reference is needed to send the actul CLIP command.
4304 static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4306 struct inet6_dev *idev = NULL;
4307 struct inet6_ifaddr *ifa;
4310 idev = __in6_dev_get(root_dev);
4314 read_lock_bh(&idev->lock);
4315 list_for_each_entry(ifa, &idev->addr_list, if_list) {
4316 ret = cxgb4_clip_get(dev, &ifa->addr);
4320 read_unlock_bh(&idev->lock);
4325 static int update_root_dev_clip(struct net_device *dev)
4327 struct net_device *root_dev = NULL;
4330 /* First populate the real net device's IPv6 addresses */
4331 ret = update_dev_clip(dev, dev);
4335 /* Parse all bond and vlan devices layered on top of the physical dev */
4336 root_dev = netdev_master_upper_dev_get_rcu(dev);
4338 ret = update_dev_clip(root_dev, dev);
4343 for (i = 0; i < VLAN_N_VID; i++) {
4344 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
4348 ret = update_dev_clip(root_dev, dev);
4355 static void update_clip(const struct adapter *adap)
4358 struct net_device *dev;
4363 for (i = 0; i < MAX_NPORTS; i++) {
4364 dev = adap->port[i];
4368 ret = update_root_dev_clip(dev);
4375 #endif /* IS_ENABLED(CONFIG_IPV6) */
4378 * cxgb_up - enable the adapter
4379 * @adap: adapter being enabled
4381 * Called when the first port is enabled, this function performs the
4382 * actions necessary to make an adapter operational, such as completing
4383 * the initialization of HW modules, and enabling interrupts.
4385 * Must be called with the rtnl lock held.
4387 static int cxgb_up(struct adapter *adap)
4391 err = setup_sge_queues(adap);
4394 err = setup_rss(adap);
4398 if (adap->flags & USING_MSIX) {
4399 name_msix_vecs(adap);
4400 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4401 adap->msix_info[0].desc, adap);
4405 err = request_msix_queue_irqs(adap);
4407 free_irq(adap->msix_info[0].vec, adap);
4411 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4412 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
4413 adap->port[0]->name, adap);
4419 t4_intr_enable(adap);
4420 adap->flags |= FULL_INIT_DONE;
4421 notify_ulds(adap, CXGB4_STATE_UP);
4422 #if IS_ENABLED(CONFIG_IPV6)
4428 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
4430 t4_free_sge_resources(adap);
4434 static void cxgb_down(struct adapter *adapter)
4436 t4_intr_disable(adapter);
4437 cancel_work_sync(&adapter->tid_release_task);
4438 cancel_work_sync(&adapter->db_full_task);
4439 cancel_work_sync(&adapter->db_drop_task);
4440 adapter->tid_release_task_busy = false;
4441 adapter->tid_release_head = NULL;
4443 if (adapter->flags & USING_MSIX) {
4444 free_msix_queue_irqs(adapter);
4445 free_irq(adapter->msix_info[0].vec, adapter);
4447 free_irq(adapter->pdev->irq, adapter);
4448 quiesce_rx(adapter);
4449 t4_sge_stop(adapter);
4450 t4_free_sge_resources(adapter);
4451 adapter->flags &= ~FULL_INIT_DONE;
4455 * net_device operations
4457 static int cxgb_open(struct net_device *dev)
4460 struct port_info *pi = netdev_priv(dev);
4461 struct adapter *adapter = pi->adapter;
4463 netif_carrier_off(dev);
4465 if (!(adapter->flags & FULL_INIT_DONE)) {
4466 err = cxgb_up(adapter);
4471 err = link_start(dev);
4473 netif_tx_start_all_queues(dev);
4477 static int cxgb_close(struct net_device *dev)
4479 struct port_info *pi = netdev_priv(dev);
4480 struct adapter *adapter = pi->adapter;
4482 netif_tx_stop_all_queues(dev);
4483 netif_carrier_off(dev);
4484 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
4487 /* Return an error number if the indicated filter isn't writable ...
4489 static int writable_filter(struct filter_entry *f)
4499 /* Delete the filter at the specified index (if valid). The checks for all
4500 * the common problems with doing this like the filter being locked, currently
4501 * pending in another operation, etc.
4503 static int delete_filter(struct adapter *adapter, unsigned int fidx)
4505 struct filter_entry *f;
4508 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
4511 f = &adapter->tids.ftid_tab[fidx];
4512 ret = writable_filter(f);
4516 return del_filter_wr(adapter, fidx);
4521 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
4522 __be32 sip, __be16 sport, __be16 vlan,
4523 unsigned int queue, unsigned char port, unsigned char mask)
4526 struct filter_entry *f;
4527 struct adapter *adap;
4531 adap = netdev2adap(dev);
4533 /* Adjust stid to correct filter index */
4534 stid -= adap->tids.sftid_base;
4535 stid += adap->tids.nftids;
4537 /* Check to make sure the filter requested is writable ...
4539 f = &adap->tids.ftid_tab[stid];
4540 ret = writable_filter(f);
4544 /* Clear out any old resources being used by the filter before
4545 * we start constructing the new filter.
4548 clear_filter(adap, f);
4550 /* Clear out filter specifications */
4551 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4552 f->fs.val.lport = cpu_to_be16(sport);
4553 f->fs.mask.lport = ~0;
4555 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
4556 for (i = 0; i < 4; i++) {
4557 f->fs.val.lip[i] = val[i];
4558 f->fs.mask.lip[i] = ~0;
4560 if (adap->params.tp.vlan_pri_map & F_PORT) {
4561 f->fs.val.iport = port;
4562 f->fs.mask.iport = mask;
4566 if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
4567 f->fs.val.proto = IPPROTO_TCP;
4568 f->fs.mask.proto = ~0;
4573 /* Mark filter as locked */
4577 ret = set_filter_wr(adap, stid);
4579 clear_filter(adap, f);
4585 EXPORT_SYMBOL(cxgb4_create_server_filter);
4587 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4588 unsigned int queue, bool ipv6)
4591 struct filter_entry *f;
4592 struct adapter *adap;
4594 adap = netdev2adap(dev);
4596 /* Adjust stid to correct filter index */
4597 stid -= adap->tids.sftid_base;
4598 stid += adap->tids.nftids;
4600 f = &adap->tids.ftid_tab[stid];
4601 /* Unlock the filter */
4604 ret = delete_filter(adap, stid);
4610 EXPORT_SYMBOL(cxgb4_remove_server_filter);
4612 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4613 struct rtnl_link_stats64 *ns)
4615 struct port_stats stats;
4616 struct port_info *p = netdev_priv(dev);
4617 struct adapter *adapter = p->adapter;
4619 /* Block retrieving statistics during EEH error
4620 * recovery. Otherwise, the recovery might fail
4621 * and the PCI device will be removed permanently
4623 spin_lock(&adapter->stats_lock);
4624 if (!netif_device_present(dev)) {
4625 spin_unlock(&adapter->stats_lock);
4628 t4_get_port_stats(adapter, p->tx_chan, &stats);
4629 spin_unlock(&adapter->stats_lock);
4631 ns->tx_bytes = stats.tx_octets;
4632 ns->tx_packets = stats.tx_frames;
4633 ns->rx_bytes = stats.rx_octets;
4634 ns->rx_packets = stats.rx_frames;
4635 ns->multicast = stats.rx_mcast_frames;
4637 /* detailed rx_errors */
4638 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4640 ns->rx_over_errors = 0;
4641 ns->rx_crc_errors = stats.rx_fcs_err;
4642 ns->rx_frame_errors = stats.rx_symbol_err;
4643 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
4644 stats.rx_ovflow2 + stats.rx_ovflow3 +
4645 stats.rx_trunc0 + stats.rx_trunc1 +
4646 stats.rx_trunc2 + stats.rx_trunc3;
4647 ns->rx_missed_errors = 0;
4649 /* detailed tx_errors */
4650 ns->tx_aborted_errors = 0;
4651 ns->tx_carrier_errors = 0;
4652 ns->tx_fifo_errors = 0;
4653 ns->tx_heartbeat_errors = 0;
4654 ns->tx_window_errors = 0;
4656 ns->tx_errors = stats.tx_error_frames;
4657 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4658 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4662 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4665 int ret = 0, prtad, devad;
4666 struct port_info *pi = netdev_priv(dev);
4667 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4671 if (pi->mdio_addr < 0)
4673 data->phy_id = pi->mdio_addr;
4677 if (mdio_phy_id_is_c45(data->phy_id)) {
4678 prtad = mdio_phy_id_prtad(data->phy_id);
4679 devad = mdio_phy_id_devad(data->phy_id);
4680 } else if (data->phy_id < 32) {
4681 prtad = data->phy_id;
4683 data->reg_num &= 0x1f;
4687 mbox = pi->adapter->fn;
4688 if (cmd == SIOCGMIIREG)
4689 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
4690 data->reg_num, &data->val_out);
4692 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
4693 data->reg_num, data->val_in);
4701 static void cxgb_set_rxmode(struct net_device *dev)
4703 /* unfortunately we can't return errors to the stack */
4704 set_rxmode(dev, -1, false);
4707 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4710 struct port_info *pi = netdev_priv(dev);
4712 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
4714 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4721 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4724 struct sockaddr *addr = p;
4725 struct port_info *pi = netdev_priv(dev);
4727 if (!is_valid_ether_addr(addr->sa_data))
4728 return -EADDRNOTAVAIL;
4730 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4731 pi->xact_addr_filt, addr->sa_data, true, true);
4735 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4736 pi->xact_addr_filt = ret;
4740 #ifdef CONFIG_NET_POLL_CONTROLLER
4741 static void cxgb_netpoll(struct net_device *dev)
4743 struct port_info *pi = netdev_priv(dev);
4744 struct adapter *adap = pi->adapter;
4746 if (adap->flags & USING_MSIX) {
4748 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4750 for (i = pi->nqsets; i; i--, rx++)
4751 t4_sge_intr_msix(0, &rx->rspq);
4753 t4_intr_handler(adap)(0, adap);
4757 static const struct net_device_ops cxgb4_netdev_ops = {
4758 .ndo_open = cxgb_open,
4759 .ndo_stop = cxgb_close,
4760 .ndo_start_xmit = t4_eth_xmit,
4761 .ndo_select_queue = cxgb_select_queue,
4762 .ndo_get_stats64 = cxgb_get_stats,
4763 .ndo_set_rx_mode = cxgb_set_rxmode,
4764 .ndo_set_mac_address = cxgb_set_mac_addr,
4765 .ndo_set_features = cxgb_set_features,
4766 .ndo_validate_addr = eth_validate_addr,
4767 .ndo_do_ioctl = cxgb_ioctl,
4768 .ndo_change_mtu = cxgb_change_mtu,
4769 #ifdef CONFIG_NET_POLL_CONTROLLER
4770 .ndo_poll_controller = cxgb_netpoll,
4774 void t4_fatal_err(struct adapter *adap)
4776 t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4777 t4_intr_disable(adap);
4778 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4781 /* Return the specified PCI-E Configuration Space register from our Physical
4782 * Function. We try first via a Firmware LDST Command since we prefer to let
4783 * the firmware own all of these registers, but if that fails we go for it
4784 * directly ourselves.
4786 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4788 struct fw_ldst_cmd ldst_cmd;
4792 /* Construct and send the Firmware LDST Command to retrieve the
4793 * specified PCI-E Configuration Space register.
4795 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4796 ldst_cmd.op_to_addrspace =
4797 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
4800 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
4801 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4802 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
4803 ldst_cmd.u.pcie.ctrl_to_fn =
4804 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
4805 ldst_cmd.u.pcie.r = reg;
4806 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4809 /* If the LDST Command suucceeded, exctract the returned register
4810 * value. Otherwise read it directly ourself.
4813 val = ntohl(ldst_cmd.u.pcie.data[0]);
4815 t4_hw_pci_read_cfg4(adap, reg, &val);
4820 static void setup_memwin(struct adapter *adap)
4822 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
4824 if (is_t4(adap->params.chip)) {
4827 /* Truncation intentional: we only read the bottom 32-bits of
4828 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
4829 * mechanism to read BAR0 instead of using
4830 * pci_resource_start() because we could be operating from
4831 * within a Virtual Machine which is trapping our accesses to
4832 * our Configuration Space and we need to set up the PCI-E
4833 * Memory Window decoders with the actual addresses which will
4834 * be coming across the PCI-E link.
4836 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4837 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4838 adap->t4_bar0 = bar0;
4840 mem_win0_base = bar0 + MEMWIN0_BASE;
4841 mem_win1_base = bar0 + MEMWIN1_BASE;
4842 mem_win2_base = bar0 + MEMWIN2_BASE;
4843 mem_win2_aperture = MEMWIN2_APERTURE;
4845 /* For T5, only relative offset inside the PCIe BAR is passed */
4846 mem_win0_base = MEMWIN0_BASE;
4847 mem_win1_base = MEMWIN1_BASE;
4848 mem_win2_base = MEMWIN2_BASE_T5;
4849 mem_win2_aperture = MEMWIN2_APERTURE_T5;
4851 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
4852 mem_win0_base | BIR(0) |
4853 WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4854 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
4855 mem_win1_base | BIR(0) |
4856 WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4857 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
4858 mem_win2_base | BIR(0) |
4859 WINDOW(ilog2(mem_win2_aperture) - 10));
4860 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
4863 static void setup_memwin_rdma(struct adapter *adap)
4865 if (adap->vres.ocq.size) {
4869 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4870 start &= PCI_BASE_ADDRESS_MEM_MASK;
4871 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4872 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4874 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4875 start | BIR(1) | WINDOW(ilog2(sz_kb)));
4877 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4878 adap->vres.ocq.start);
4880 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4884 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4889 /* get device capabilities */
4890 memset(c, 0, sizeof(*c));
4891 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4892 FW_CMD_REQUEST_F | FW_CMD_READ_F);
4893 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
4894 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
4898 /* select capabilities we'll be using */
4899 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4901 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4903 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4904 } else if (vf_acls) {
4905 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4908 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4909 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4910 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
4914 ret = t4_config_glbl_rss(adap, adap->fn,
4915 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4916 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
4917 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
4921 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4922 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
4928 /* tweak some settings */
4929 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
4930 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4931 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
4932 v = t4_read_reg(adap, TP_PIO_DATA);
4933 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
4935 /* first 4 Tx modulation queues point to consecutive Tx channels */
4936 adap->params.tp.tx_modq_map = 0xE4;
4937 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
4938 V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
4940 /* associate each Tx modulation queue with consecutive Tx channels */
4942 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4943 &v, 1, A_TP_TX_SCHED_HDR);
4944 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4945 &v, 1, A_TP_TX_SCHED_FIFO);
4946 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4947 &v, 1, A_TP_TX_SCHED_PCMD);
4949 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4950 if (is_offload(adap)) {
4951 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
4952 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4953 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4954 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4955 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4956 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
4957 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4958 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4959 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4960 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4963 /* get basic stuff going */
4964 return t4_early_init(adap, adap->fn);
4968 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
4970 #define MAX_ATIDS 8192U
4973 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4975 * If the firmware we're dealing with has Configuration File support, then
4976 * we use that to perform all configuration
4980 * Tweak configuration based on module parameters, etc. Most of these have
4981 * defaults assigned to them by Firmware Configuration Files (if we're using
4982 * them) but need to be explicitly set if we're using hard-coded
4983 * initialization. But even in the case of using Firmware Configuration
4984 * Files, we'd like to expose the ability to change these via module
4985 * parameters so these are essentially common tweaks/settings for
4986 * Configuration Files and hard-coded initialization ...
4988 static int adap_init0_tweaks(struct adapter *adapter)
4991 * Fix up various Host-Dependent Parameters like Page Size, Cache
4992 * Line Size, etc. The firmware default is for a 4KB Page Size and
4993 * 64B Cache Line Size ...
4995 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4998 * Process module parameters which affect early initialization.
5000 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
5001 dev_err(&adapter->pdev->dev,
5002 "Ignoring illegal rx_dma_offset=%d, using 2\n",
5006 t4_set_reg_field(adapter, SGE_CONTROL,
5008 PKTSHIFT(rx_dma_offset));
5011 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5012 * adds the pseudo header itself.
5014 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5015 CSUM_HAS_PSEUDO_HDR, 0);
5021 * Attempt to initialize the adapter via a Firmware Configuration File.
5023 static int adap_init0_config(struct adapter *adapter, int reset)
5025 struct fw_caps_config_cmd caps_cmd;
5026 const struct firmware *cf;
5027 unsigned long mtype = 0, maddr = 0;
5028 u32 finiver, finicsum, cfcsum;
5030 int config_issued = 0;
5031 char *fw_config_file, fw_config_file_path[256];
5032 char *config_name = NULL;
5035 * Reset device if necessary.
5038 ret = t4_fw_reset(adapter, adapter->mbox,
5039 PIORSTMODE | PIORST);
5045 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5046 * then use that. Otherwise, use the configuration file stored
5047 * in the adapter flash ...
5049 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
5051 fw_config_file = FW4_CFNAME;
5054 fw_config_file = FW5_CFNAME;
5057 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5058 adapter->pdev->device);
5063 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
5065 config_name = "On FLASH";
5066 mtype = FW_MEMTYPE_CF_FLASH;
5067 maddr = t4_flash_cfg_addr(adapter);
5069 u32 params[7], val[7];
5071 sprintf(fw_config_file_path,
5072 "/lib/firmware/%s", fw_config_file);
5073 config_name = fw_config_file_path;
5075 if (cf->size >= FLASH_CFG_MAX_SIZE)
5078 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5079 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
5080 ret = t4_query_params(adapter, adapter->mbox,
5081 adapter->fn, 0, 1, params, val);
5084 * For t4_memory_rw() below addresses and
5085 * sizes have to be in terms of multiples of 4
5086 * bytes. So, if the Configuration File isn't
5087 * a multiple of 4 bytes in length we'll have
5088 * to write that out separately since we can't
5089 * guarantee that the bytes following the
5090 * residual byte in the buffer returned by
5091 * request_firmware() are zeroed out ...
5093 size_t resid = cf->size & 0x3;
5094 size_t size = cf->size & ~0x3;
5095 __be32 *data = (__be32 *)cf->data;
5097 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
5098 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
5100 spin_lock(&adapter->win0_lock);
5101 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5102 size, data, T4_MEMORY_WRITE);
5103 if (ret == 0 && resid != 0) {
5110 last.word = data[size >> 2];
5111 for (i = resid; i < 4; i++)
5113 ret = t4_memory_rw(adapter, 0, mtype,
5118 spin_unlock(&adapter->win0_lock);
5122 release_firmware(cf);
5128 * Issue a Capability Configuration command to the firmware to get it
5129 * to parse the Configuration File. We don't use t4_fw_config_file()
5130 * because we want the ability to modify various features after we've
5131 * processed the configuration file ...
5133 memset(&caps_cmd, 0, sizeof(caps_cmd));
5134 caps_cmd.op_to_write =
5135 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5138 caps_cmd.cfvalid_to_len16 =
5139 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
5140 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
5141 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
5142 FW_LEN16(caps_cmd));
5143 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5146 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5147 * Configuration File in FLASH), our last gasp effort is to use the
5148 * Firmware Configuration File which is embedded in the firmware. A
5149 * very few early versions of the firmware didn't have one embedded
5150 * but we can ignore those.
5152 if (ret == -ENOENT) {
5153 memset(&caps_cmd, 0, sizeof(caps_cmd));
5154 caps_cmd.op_to_write =
5155 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5158 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5159 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5160 sizeof(caps_cmd), &caps_cmd);
5161 config_name = "Firmware Default";
5168 finiver = ntohl(caps_cmd.finiver);
5169 finicsum = ntohl(caps_cmd.finicsum);
5170 cfcsum = ntohl(caps_cmd.cfcsum);
5171 if (finicsum != cfcsum)
5172 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5173 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5177 * And now tell the firmware to use the configuration we just loaded.
5179 caps_cmd.op_to_write =
5180 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5183 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5184 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5190 * Tweak configuration based on system architecture, module
5193 ret = adap_init0_tweaks(adapter);
5198 * And finally tell the firmware to initialize itself using the
5199 * parameters from the Configuration File.
5201 ret = t4_fw_initialize(adapter, adapter->mbox);
5206 * Return successfully and note that we're operating with parameters
5207 * not supplied by the driver, rather than from hard-wired
5208 * initialization constants burried in the driver.
5210 adapter->flags |= USING_SOFT_PARAMS;
5211 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
5212 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5213 config_name, finiver, cfcsum);
5217 * Something bad happened. Return the error ... (If the "error"
5218 * is that there's no Configuration File on the adapter we don't
5219 * want to issue a warning since this is fairly common.)
5222 if (config_issued && ret != -ENOENT)
5223 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5229 * Attempt to initialize the adapter via hard-coded, driver supplied
5232 static int adap_init0_no_config(struct adapter *adapter, int reset)
5234 struct sge *s = &adapter->sge;
5235 struct fw_caps_config_cmd caps_cmd;
5240 * Reset device if necessary
5243 ret = t4_fw_reset(adapter, adapter->mbox,
5244 PIORSTMODE | PIORST);
5250 * Get device capabilities and select which we'll be using.
5252 memset(&caps_cmd, 0, sizeof(caps_cmd));
5253 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5254 FW_CMD_REQUEST_F | FW_CMD_READ_F);
5255 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5256 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5261 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5263 caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5265 caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5266 } else if (vf_acls) {
5267 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5270 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5271 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5272 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5278 * Tweak configuration based on system architecture, module
5281 ret = adap_init0_tweaks(adapter);
5286 * Select RSS Global Mode we want to use. We use "Basic Virtual"
5287 * mode which maps each Virtual Interface to its own section of
5288 * the RSS Table and we turn on all map and hash enables ...
5290 adapter->flags |= RSS_TNLALLLOOKUP;
5291 ret = t4_config_glbl_rss(adapter, adapter->mbox,
5292 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5293 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
5294 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F |
5295 ((adapter->flags & RSS_TNLALLLOOKUP) ?
5296 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F : 0));
5301 * Set up our own fundamental resource provisioning ...
5303 ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5304 PFRES_NEQ, PFRES_NETHCTRL,
5305 PFRES_NIQFLINT, PFRES_NIQ,
5306 PFRES_TC, PFRES_NVI,
5307 FW_PFVF_CMD_CMASK_M,
5308 pfvfres_pmask(adapter, adapter->fn, 0),
5310 PFRES_R_CAPS, PFRES_WX_CAPS);
5315 * Perform low level SGE initialization. We need to do this before we
5316 * send the firmware the INITIALIZE command because that will cause
5317 * any other PF Drivers which are waiting for the Master
5318 * Initialization to proceed forward.
5320 for (i = 0; i < SGE_NTIMERS - 1; i++)
5321 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5322 s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5323 s->counter_val[0] = 1;
5324 for (i = 1; i < SGE_NCOUNTERS; i++)
5325 s->counter_val[i] = min(intr_cnt[i - 1],
5326 THRESHOLD_0_GET(THRESHOLD_0_MASK));
5327 t4_sge_init(adapter);
5329 #ifdef CONFIG_PCI_IOV
5331 * Provision resource limits for Virtual Functions. We currently
5332 * grant them all the same static resource limits except for the Port
5333 * Access Rights Mask which we're assigning based on the PF. All of
5334 * the static provisioning stuff for both the PF and VF really needs
5335 * to be managed in a persistent manner for each device which the
5336 * firmware controls.
5341 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
5342 if (num_vf[pf] <= 0)
5345 /* VF numbering starts at 1! */
5346 for (vf = 1; vf <= num_vf[pf]; vf++) {
5347 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5349 VFRES_NEQ, VFRES_NETHCTRL,
5350 VFRES_NIQFLINT, VFRES_NIQ,
5351 VFRES_TC, VFRES_NVI,
5352 FW_PFVF_CMD_CMASK_M,
5356 VFRES_R_CAPS, VFRES_WX_CAPS);
5358 dev_warn(adapter->pdev_dev,
5360 "provision pf/vf=%d/%d; "
5361 "err=%d\n", pf, vf, ret);
5368 * Set up the default filter mode. Later we'll want to implement this
5369 * via a firmware command, etc. ... This needs to be done before the
5370 * firmare initialization command ... If the selected set of fields
5371 * isn't equal to the default value, we'll need to make sure that the
5372 * field selections will fit in the 36-bit budget.
5374 if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
5377 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5378 switch (tp_vlan_pri_map & (1 << j)) {
5380 /* compressed filter field not enabled */
5400 case ETHERTYPE_MASK:
5406 case MPSHITTYPE_MASK:
5409 case FRAGMENTATION_MASK:
5415 dev_err(adapter->pdev_dev,
5416 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5417 " using %#x\n", tp_vlan_pri_map, bits,
5418 TP_VLAN_PRI_MAP_DEFAULT);
5419 tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5422 v = tp_vlan_pri_map;
5423 t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5424 &v, 1, TP_VLAN_PRI_MAP);
5427 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5428 * to support any of the compressed filter fields above. Newer
5429 * versions of the firmware do this automatically but it doesn't hurt
5430 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
5431 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5432 * since the firmware automatically turns this on and off when we have
5433 * a non-zero number of filters active (since it does have a
5434 * performance impact).
5436 if (tp_vlan_pri_map)
5437 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5438 FIVETUPLELOOKUP_MASK,
5439 FIVETUPLELOOKUP_MASK);
5442 * Tweak some settings.
5444 t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5445 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5446 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5447 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5450 * Get basic stuff going by issuing the Firmware Initialize command.
5451 * Note that this _must_ be after all PFVF commands ...
5453 ret = t4_fw_initialize(adapter, adapter->mbox);
5458 * Return successfully!
5460 dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5461 "driver parameters\n");
5465 * Something bad happened. Return the error ...
5471 static struct fw_info fw_info_array[] = {
5474 .fs_name = FW4_CFNAME,
5475 .fw_mod_name = FW4_FNAME,
5477 .chip = FW_HDR_CHIP_T4,
5478 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5479 .intfver_nic = FW_INTFVER(T4, NIC),
5480 .intfver_vnic = FW_INTFVER(T4, VNIC),
5481 .intfver_ri = FW_INTFVER(T4, RI),
5482 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5483 .intfver_fcoe = FW_INTFVER(T4, FCOE),
5487 .fs_name = FW5_CFNAME,
5488 .fw_mod_name = FW5_FNAME,
5490 .chip = FW_HDR_CHIP_T5,
5491 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5492 .intfver_nic = FW_INTFVER(T5, NIC),
5493 .intfver_vnic = FW_INTFVER(T5, VNIC),
5494 .intfver_ri = FW_INTFVER(T5, RI),
5495 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5496 .intfver_fcoe = FW_INTFVER(T5, FCOE),
5501 static struct fw_info *find_fw_info(int chip)
5505 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5506 if (fw_info_array[i].chip == chip)
5507 return &fw_info_array[i];
5513 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5515 static int adap_init0(struct adapter *adap)
5519 enum dev_state state;
5520 u32 params[7], val[7];
5521 struct fw_caps_config_cmd caps_cmd;
5525 * Contact FW, advertising Master capability (and potentially forcing
5526 * ourselves as the Master PF if our module parameter force_init is
5529 ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5530 force_init ? MASTER_MUST : MASTER_MAY,
5533 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5537 if (ret == adap->mbox)
5538 adap->flags |= MASTER_PF;
5539 if (force_init && state == DEV_STATE_INIT)
5540 state = DEV_STATE_UNINIT;
5543 * If we're the Master PF Driver and the device is uninitialized,
5544 * then let's consider upgrading the firmware ... (We always want
5545 * to check the firmware version number in order to A. get it for
5546 * later reporting and B. to warn if the currently loaded firmware
5547 * is excessively mismatched relative to the driver.)
5549 t4_get_fw_version(adap, &adap->params.fw_vers);
5550 t4_get_tp_version(adap, &adap->params.tp_vers);
5551 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
5552 struct fw_info *fw_info;
5553 struct fw_hdr *card_fw;
5554 const struct firmware *fw;
5555 const u8 *fw_data = NULL;
5556 unsigned int fw_size = 0;
5558 /* This is the firmware whose headers the driver was compiled
5561 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5562 if (fw_info == NULL) {
5563 dev_err(adap->pdev_dev,
5564 "unable to get firmware info for chip %d.\n",
5565 CHELSIO_CHIP_VERSION(adap->params.chip));
5569 /* allocate memory to read the header of the firmware on the
5572 card_fw = t4_alloc_mem(sizeof(*card_fw));
5574 /* Get FW from from /lib/firmware/ */
5575 ret = request_firmware(&fw, fw_info->fw_mod_name,
5578 dev_err(adap->pdev_dev,
5579 "unable to load firmware image %s, error %d\n",
5580 fw_info->fw_mod_name, ret);
5586 /* upgrade FW logic */
5587 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5592 release_firmware(fw);
5593 t4_free_mem(card_fw);
5600 * Grab VPD parameters. This should be done after we establish a
5601 * connection to the firmware since some of the VPD parameters
5602 * (notably the Core Clock frequency) are retrieved via requests to
5603 * the firmware. On the other hand, we need these fairly early on
5604 * so we do this right after getting ahold of the firmware.
5606 ret = get_vpd_params(adap, &adap->params.vpd);
5611 * Find out what ports are available to us. Note that we need to do
5612 * this before calling adap_init0_no_config() since it needs nports
5616 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5617 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
5618 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
5622 adap->params.nports = hweight32(port_vec);
5623 adap->params.portvec = port_vec;
5626 * If the firmware is initialized already (and we're not forcing a
5627 * master initialization), note that we're living with existing
5628 * adapter parameters. Otherwise, it's time to try initializing the
5631 if (state == DEV_STATE_INIT) {
5632 dev_info(adap->pdev_dev, "Coming up as %s: "\
5633 "Adapter already initialized\n",
5634 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5635 adap->flags |= USING_SOFT_PARAMS;
5637 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5638 "Initializing adapter\n");
5640 * If the firmware doesn't support Configuration
5641 * Files warn user and exit,
5644 dev_warn(adap->pdev_dev, "Firmware doesn't support "
5645 "configuration file.\n");
5647 ret = adap_init0_no_config(adap, reset);
5650 * Find out whether we're dealing with a version of
5651 * the firmware which has configuration file support.
5653 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5654 FW_PARAMS_PARAM_X_V(
5655 FW_PARAMS_PARAM_DEV_CF));
5656 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5660 * If the firmware doesn't support Configuration
5661 * Files, use the old Driver-based, hard-wired
5662 * initialization. Otherwise, try using the
5663 * Configuration File support and fall back to the
5664 * Driver-based initialization if there's no
5665 * Configuration File found.
5668 ret = adap_init0_no_config(adap, reset);
5671 * The firmware provides us with a memory
5672 * buffer where we can load a Configuration
5673 * File from the host if we want to override
5674 * the Configuration File in flash.
5677 ret = adap_init0_config(adap, reset);
5678 if (ret == -ENOENT) {
5679 dev_info(adap->pdev_dev,
5680 "No Configuration File present "
5681 "on adapter. Using hard-wired "
5682 "configuration parameters.\n");
5683 ret = adap_init0_no_config(adap, reset);
5688 dev_err(adap->pdev_dev,
5689 "could not initialize adapter, error %d\n",
5696 * If we're living with non-hard-coded parameters (either from a
5697 * Firmware Configuration File or values programmed by a different PF
5698 * Driver), give the SGE code a chance to pull in anything that it
5699 * needs ... Note that this must be called after we retrieve our VPD
5700 * parameters in order to know how to convert core ticks to seconds.
5702 if (adap->flags & USING_SOFT_PARAMS) {
5703 ret = t4_sge_init(adap);
5708 if (is_bypass_device(adap->pdev->device))
5709 adap->params.bypass = 1;
5712 * Grab some of our basic fundamental operating parameters.
5714 #define FW_PARAM_DEV(param) \
5715 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
5716 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
5718 #define FW_PARAM_PFVF(param) \
5719 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
5720 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
5721 FW_PARAMS_PARAM_Y_V(0) | \
5722 FW_PARAMS_PARAM_Z_V(0)
5724 params[0] = FW_PARAM_PFVF(EQ_START);
5725 params[1] = FW_PARAM_PFVF(L2T_START);
5726 params[2] = FW_PARAM_PFVF(L2T_END);
5727 params[3] = FW_PARAM_PFVF(FILTER_START);
5728 params[4] = FW_PARAM_PFVF(FILTER_END);
5729 params[5] = FW_PARAM_PFVF(IQFLINT_START);
5730 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
5733 adap->sge.egr_start = val[0];
5734 adap->l2t_start = val[1];
5735 adap->l2t_end = val[2];
5736 adap->tids.ftid_base = val[3];
5737 adap->tids.nftids = val[4] - val[3] + 1;
5738 adap->sge.ingr_start = val[5];
5740 /* query params related to active filter region */
5741 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5742 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5743 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5744 /* If Active filter size is set we enable establishing
5745 * offload connection through firmware work request
5747 if ((val[0] != val[1]) && (ret >= 0)) {
5748 adap->flags |= FW_OFLD_CONN;
5749 adap->tids.aftid_base = val[0];
5750 adap->tids.aftid_end = val[1];
5753 /* If we're running on newer firmware, let it know that we're
5754 * prepared to deal with encapsulated CPL messages. Older
5755 * firmware won't understand this and we'll just get
5756 * unencapsulated messages ...
5758 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5760 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5763 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5764 * capability. Earlier versions of the firmware didn't have the
5765 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5766 * permission to use ULPTX MEMWRITE DSGL.
5768 if (is_t4(adap->params.chip)) {
5769 adap->params.ulptx_memwrite_dsgl = false;
5771 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5772 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5774 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5778 * Get device capabilities so we can determine what resources we need
5781 memset(&caps_cmd, 0, sizeof(caps_cmd));
5782 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5783 FW_CMD_REQUEST_F | FW_CMD_READ_F);
5784 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5785 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5790 if (caps_cmd.ofldcaps) {
5791 /* query offload-related parameters */
5792 params[0] = FW_PARAM_DEV(NTID);
5793 params[1] = FW_PARAM_PFVF(SERVER_START);
5794 params[2] = FW_PARAM_PFVF(SERVER_END);
5795 params[3] = FW_PARAM_PFVF(TDDP_START);
5796 params[4] = FW_PARAM_PFVF(TDDP_END);
5797 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5798 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5802 adap->tids.ntids = val[0];
5803 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5804 adap->tids.stid_base = val[1];
5805 adap->tids.nstids = val[2] - val[1] + 1;
5807 * Setup server filter region. Divide the availble filter
5808 * region into two parts. Regular filters get 1/3rd and server
5809 * filters get 2/3rd part. This is only enabled if workarond
5811 * 1. For regular filters.
5812 * 2. Server filter: This are special filters which are used
5813 * to redirect SYN packets to offload queue.
5815 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5816 adap->tids.sftid_base = adap->tids.ftid_base +
5817 DIV_ROUND_UP(adap->tids.nftids, 3);
5818 adap->tids.nsftids = adap->tids.nftids -
5819 DIV_ROUND_UP(adap->tids.nftids, 3);
5820 adap->tids.nftids = adap->tids.sftid_base -
5821 adap->tids.ftid_base;
5823 adap->vres.ddp.start = val[3];
5824 adap->vres.ddp.size = val[4] - val[3] + 1;
5825 adap->params.ofldq_wr_cred = val[5];
5827 adap->params.offload = 1;
5829 if (caps_cmd.rdmacaps) {
5830 params[0] = FW_PARAM_PFVF(STAG_START);
5831 params[1] = FW_PARAM_PFVF(STAG_END);
5832 params[2] = FW_PARAM_PFVF(RQ_START);
5833 params[3] = FW_PARAM_PFVF(RQ_END);
5834 params[4] = FW_PARAM_PFVF(PBL_START);
5835 params[5] = FW_PARAM_PFVF(PBL_END);
5836 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5840 adap->vres.stag.start = val[0];
5841 adap->vres.stag.size = val[1] - val[0] + 1;
5842 adap->vres.rq.start = val[2];
5843 adap->vres.rq.size = val[3] - val[2] + 1;
5844 adap->vres.pbl.start = val[4];
5845 adap->vres.pbl.size = val[5] - val[4] + 1;
5847 params[0] = FW_PARAM_PFVF(SQRQ_START);
5848 params[1] = FW_PARAM_PFVF(SQRQ_END);
5849 params[2] = FW_PARAM_PFVF(CQ_START);
5850 params[3] = FW_PARAM_PFVF(CQ_END);
5851 params[4] = FW_PARAM_PFVF(OCQ_START);
5852 params[5] = FW_PARAM_PFVF(OCQ_END);
5853 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
5857 adap->vres.qp.start = val[0];
5858 adap->vres.qp.size = val[1] - val[0] + 1;
5859 adap->vres.cq.start = val[2];
5860 adap->vres.cq.size = val[3] - val[2] + 1;
5861 adap->vres.ocq.start = val[4];
5862 adap->vres.ocq.size = val[5] - val[4] + 1;
5864 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5865 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5866 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
5869 adap->params.max_ordird_qp = 8;
5870 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5873 adap->params.max_ordird_qp = val[0];
5874 adap->params.max_ird_adapter = val[1];
5876 dev_info(adap->pdev_dev,
5877 "max_ordird_qp %d max_ird_adapter %d\n",
5878 adap->params.max_ordird_qp,
5879 adap->params.max_ird_adapter);
5881 if (caps_cmd.iscsicaps) {
5882 params[0] = FW_PARAM_PFVF(ISCSI_START);
5883 params[1] = FW_PARAM_PFVF(ISCSI_END);
5884 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5888 adap->vres.iscsi.start = val[0];
5889 adap->vres.iscsi.size = val[1] - val[0] + 1;
5891 #undef FW_PARAM_PFVF
5894 /* The MTU/MSS Table is initialized by now, so load their values. If
5895 * we're initializing the adapter, then we'll make any modifications
5896 * we want to the MTU/MSS Table and also initialize the congestion
5899 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5900 if (state != DEV_STATE_INIT) {
5903 /* The default MTU Table contains values 1492 and 1500.
5904 * However, for TCP, it's better to have two values which are
5905 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5906 * This allows us to have a TCP Data Payload which is a
5907 * multiple of 8 regardless of what combination of TCP Options
5908 * are in use (always a multiple of 4 bytes) which is
5909 * important for performance reasons. For instance, if no
5910 * options are in use, then we have a 20-byte IP header and a
5911 * 20-byte TCP header. In this case, a 1500-byte MSS would
5912 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5913 * which is not a multiple of 8. So using an MSS of 1488 in
5914 * this case results in a TCP Data Payload of 1448 bytes which
5915 * is a multiple of 8. On the other hand, if 12-byte TCP Time
5916 * Stamps have been negotiated, then an MTU of 1500 bytes
5917 * results in a TCP Data Payload of 1448 bytes which, as
5918 * above, is a multiple of 8 bytes ...
5920 for (i = 0; i < NMTUS; i++)
5921 if (adap->params.mtus[i] == 1492) {
5922 adap->params.mtus[i] = 1488;
5926 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5927 adap->params.b_wnd);
5929 t4_init_tp_params(adap);
5930 adap->flags |= FW_OK;
5934 * Something bad happened. If a command timed out or failed with EIO
5935 * FW does not operate within its spec or something catastrophic
5936 * happened to HW/FW, stop issuing commands.
5939 if (ret != -ETIMEDOUT && ret != -EIO)
5940 t4_fw_bye(adap, adap->mbox);
5946 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5947 pci_channel_state_t state)
5950 struct adapter *adap = pci_get_drvdata(pdev);
5956 adap->flags &= ~FW_OK;
5957 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5958 spin_lock(&adap->stats_lock);
5959 for_each_port(adap, i) {
5960 struct net_device *dev = adap->port[i];
5962 netif_device_detach(dev);
5963 netif_carrier_off(dev);
5965 spin_unlock(&adap->stats_lock);
5966 if (adap->flags & FULL_INIT_DONE)
5969 if ((adap->flags & DEV_ENABLED)) {
5970 pci_disable_device(pdev);
5971 adap->flags &= ~DEV_ENABLED;
5973 out: return state == pci_channel_io_perm_failure ?
5974 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5977 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5980 struct fw_caps_config_cmd c;
5981 struct adapter *adap = pci_get_drvdata(pdev);
5984 pci_restore_state(pdev);
5985 pci_save_state(pdev);
5986 return PCI_ERS_RESULT_RECOVERED;
5989 if (!(adap->flags & DEV_ENABLED)) {
5990 if (pci_enable_device(pdev)) {
5991 dev_err(&pdev->dev, "Cannot reenable PCI "
5992 "device after reset\n");
5993 return PCI_ERS_RESULT_DISCONNECT;
5995 adap->flags |= DEV_ENABLED;
5998 pci_set_master(pdev);
5999 pci_restore_state(pdev);
6000 pci_save_state(pdev);
6001 pci_cleanup_aer_uncorrect_error_status(pdev);
6003 if (t4_wait_dev_ready(adap->regs) < 0)
6004 return PCI_ERS_RESULT_DISCONNECT;
6005 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
6006 return PCI_ERS_RESULT_DISCONNECT;
6007 adap->flags |= FW_OK;
6008 if (adap_init1(adap, &c))
6009 return PCI_ERS_RESULT_DISCONNECT;
6011 for_each_port(adap, i) {
6012 struct port_info *p = adap2pinfo(adap, i);
6014 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6017 return PCI_ERS_RESULT_DISCONNECT;
6019 p->xact_addr_filt = -1;
6022 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6023 adap->params.b_wnd);
6026 return PCI_ERS_RESULT_DISCONNECT;
6027 return PCI_ERS_RESULT_RECOVERED;
6030 static void eeh_resume(struct pci_dev *pdev)
6033 struct adapter *adap = pci_get_drvdata(pdev);
6039 for_each_port(adap, i) {
6040 struct net_device *dev = adap->port[i];
6042 if (netif_running(dev)) {
6044 cxgb_set_rxmode(dev);
6046 netif_device_attach(dev);
6051 static const struct pci_error_handlers cxgb4_eeh = {
6052 .error_detected = eeh_err_detected,
6053 .slot_reset = eeh_slot_reset,
6054 .resume = eeh_resume,
6057 static inline bool is_x_10g_port(const struct link_config *lc)
6059 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6060 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
6063 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6064 unsigned int us, unsigned int cnt,
6065 unsigned int size, unsigned int iqe_size)
6068 set_rspq_intr_params(q, us, cnt);
6069 q->iqe_len = iqe_size;
6074 * Perform default configuration of DMA queues depending on the number and type
6075 * of ports we found and the number of available CPUs. Most settings can be
6076 * modified by the admin prior to actual use.
6078 static void cfg_queues(struct adapter *adap)
6080 struct sge *s = &adap->sge;
6081 int i, n10g = 0, qidx = 0;
6082 #ifndef CONFIG_CHELSIO_T4_DCB
6087 for_each_port(adap, i)
6088 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
6089 #ifdef CONFIG_CHELSIO_T4_DCB
6090 /* For Data Center Bridging support we need to be able to support up
6091 * to 8 Traffic Priorities; each of which will be assigned to its
6092 * own TX Queue in order to prevent Head-Of-Line Blocking.
6094 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6095 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6096 MAX_ETH_QSETS, adap->params.nports * 8);
6100 for_each_port(adap, i) {
6101 struct port_info *pi = adap2pinfo(adap, i);
6103 pi->first_qset = qidx;
6107 #else /* !CONFIG_CHELSIO_T4_DCB */
6109 * We default to 1 queue per non-10G port and up to # of cores queues
6113 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
6114 if (q10g > netif_get_num_default_rss_queues())
6115 q10g = netif_get_num_default_rss_queues();
6117 for_each_port(adap, i) {
6118 struct port_info *pi = adap2pinfo(adap, i);
6120 pi->first_qset = qidx;
6121 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
6124 #endif /* !CONFIG_CHELSIO_T4_DCB */
6127 s->max_ethqsets = qidx; /* MSI-X may lower it later */
6129 if (is_offload(adap)) {
6131 * For offload we use 1 queue/channel if all ports are up to 1G,
6132 * otherwise we divide all available queues amongst the channels
6133 * capped by the number of available cores.
6136 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6138 s->ofldqsets = roundup(i, adap->params.nports);
6140 s->ofldqsets = adap->params.nports;
6141 /* For RDMA one Rx queue per channel suffices */
6142 s->rdmaqs = adap->params.nports;
6143 s->rdmaciqs = adap->params.nports;
6146 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6147 struct sge_eth_rxq *r = &s->ethrxq[i];
6149 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
6153 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6154 s->ethtxq[i].q.size = 1024;
6156 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6157 s->ctrlq[i].q.size = 512;
6159 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6160 s->ofldtxq[i].q.size = 1024;
6162 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6163 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6165 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
6166 r->rspq.uld = CXGB4_ULD_ISCSI;
6170 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6171 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6173 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
6174 r->rspq.uld = CXGB4_ULD_RDMA;
6178 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6179 if (ciq_size > SGE_MAX_IQ_SIZE) {
6180 CH_WARN(adap, "CIQ size too small for available IQs\n");
6181 ciq_size = SGE_MAX_IQ_SIZE;
6184 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6185 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6187 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
6188 r->rspq.uld = CXGB4_ULD_RDMA;
6191 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6192 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
6196 * Reduce the number of Ethernet queues across all ports to at most n.
6197 * n provides at least one queue per port.
6199 static void reduce_ethqs(struct adapter *adap, int n)
6202 struct port_info *pi;
6204 while (n < adap->sge.ethqsets)
6205 for_each_port(adap, i) {
6206 pi = adap2pinfo(adap, i);
6207 if (pi->nqsets > 1) {
6209 adap->sge.ethqsets--;
6210 if (adap->sge.ethqsets <= n)
6216 for_each_port(adap, i) {
6217 pi = adap2pinfo(adap, i);
6223 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6224 #define EXTRA_VECS 2
6226 static int enable_msix(struct adapter *adap)
6230 struct sge *s = &adap->sge;
6231 unsigned int nchan = adap->params.nports;
6232 struct msix_entry entries[MAX_INGQ + 1];
6234 for (i = 0; i < ARRAY_SIZE(entries); ++i)
6235 entries[i].entry = i;
6237 want = s->max_ethqsets + EXTRA_VECS;
6238 if (is_offload(adap)) {
6239 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
6240 /* need nchan for each possible ULD */
6241 ofld_need = 3 * nchan;
6243 #ifdef CONFIG_CHELSIO_T4_DCB
6244 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6247 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6249 need = adap->params.nports + EXTRA_VECS + ofld_need;
6251 want = pci_enable_msix_range(adap->pdev, entries, need, want);
6256 * Distribute available vectors to the various queue groups.
6257 * Every group gets its minimum requirement and NIC gets top
6258 * priority for leftovers.
6260 i = want - EXTRA_VECS - ofld_need;
6261 if (i < s->max_ethqsets) {
6262 s->max_ethqsets = i;
6263 if (i < s->ethqsets)
6264 reduce_ethqs(adap, i);
6266 if (is_offload(adap)) {
6267 i = want - EXTRA_VECS - s->max_ethqsets;
6268 i -= ofld_need - nchan;
6269 s->ofldqsets = (i / nchan) * nchan; /* round down */
6271 for (i = 0; i < want; ++i)
6272 adap->msix_info[i].vec = entries[i].vector;
6279 static int init_rss(struct adapter *adap)
6283 for_each_port(adap, i) {
6284 struct port_info *pi = adap2pinfo(adap, i);
6286 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6289 for (j = 0; j < pi->rss_size; j++)
6290 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
6295 static void print_port_info(const struct net_device *dev)
6299 const char *spd = "";
6300 const struct port_info *pi = netdev_priv(dev);
6301 const struct adapter *adap = pi->adapter;
6303 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6305 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6307 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6310 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6311 bufp += sprintf(bufp, "100/");
6312 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6313 bufp += sprintf(bufp, "1000/");
6314 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6315 bufp += sprintf(bufp, "10G/");
6316 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6317 bufp += sprintf(bufp, "40G/");
6320 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
6322 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6323 adap->params.vpd.id,
6324 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
6325 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6326 (adap->flags & USING_MSIX) ? " MSI-X" :
6327 (adap->flags & USING_MSI) ? " MSI" : "");
6328 netdev_info(dev, "S/N: %s, P/N: %s\n",
6329 adap->params.vpd.sn, adap->params.vpd.pn);
6332 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
6334 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
6338 * Free the following resources:
6339 * - memory used for tables
6342 * - resources FW is holding for us
6344 static void free_some_resources(struct adapter *adapter)
6348 t4_free_mem(adapter->l2t);
6349 t4_free_mem(adapter->tids.tid_tab);
6350 disable_msi(adapter);
6352 for_each_port(adapter, i)
6353 if (adapter->port[i]) {
6354 kfree(adap2pinfo(adapter, i)->rss);
6355 free_netdev(adapter->port[i]);
6357 if (adapter->flags & FW_OK)
6358 t4_fw_bye(adapter, adapter->fn);
6361 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6362 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6363 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6364 #define SEGMENT_SIZE 128
6366 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6368 int func, i, err, s_qpp, qpp, num_seg;
6369 struct port_info *pi;
6370 bool highdma = false;
6371 struct adapter *adapter = NULL;
6374 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6376 err = pci_request_regions(pdev, KBUILD_MODNAME);
6378 /* Just info, some other driver may have claimed the device. */
6379 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6383 err = pci_enable_device(pdev);
6385 dev_err(&pdev->dev, "cannot enable PCI device\n");
6386 goto out_release_regions;
6389 regs = pci_ioremap_bar(pdev, 0);
6391 dev_err(&pdev->dev, "cannot map device registers\n");
6393 goto out_disable_device;
6396 err = t4_wait_dev_ready(regs);
6398 goto out_unmap_bar0;
6400 /* We control everything through one PF */
6401 func = SOURCEPF_GET(readl(regs + PL_WHOAMI));
6402 if (func != ent->driver_data) {
6404 pci_disable_device(pdev);
6405 pci_save_state(pdev); /* to restore SR-IOV later */
6409 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6411 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6413 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6414 "coherent allocations\n");
6415 goto out_unmap_bar0;
6418 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6420 dev_err(&pdev->dev, "no usable DMA configuration\n");
6421 goto out_unmap_bar0;
6425 pci_enable_pcie_error_reporting(pdev);
6426 enable_pcie_relaxed_ordering(pdev);
6427 pci_set_master(pdev);
6428 pci_save_state(pdev);
6430 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6433 goto out_unmap_bar0;
6436 adapter->workq = create_singlethread_workqueue("cxgb4");
6437 if (!adapter->workq) {
6439 goto out_free_adapter;
6442 /* PCI device has been enabled */
6443 adapter->flags |= DEV_ENABLED;
6445 adapter->regs = regs;
6446 adapter->pdev = pdev;
6447 adapter->pdev_dev = &pdev->dev;
6448 adapter->mbox = func;
6450 adapter->msg_enable = dflt_msg_enable;
6451 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6453 spin_lock_init(&adapter->stats_lock);
6454 spin_lock_init(&adapter->tid_release_lock);
6455 spin_lock_init(&adapter->win0_lock);
6457 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6458 INIT_WORK(&adapter->db_full_task, process_db_full);
6459 INIT_WORK(&adapter->db_drop_task, process_db_drop);
6461 err = t4_prep_adapter(adapter);
6463 goto out_free_adapter;
6466 if (!is_t4(adapter->params.chip)) {
6467 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6468 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6469 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6470 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6472 /* Each segment size is 128B. Write coalescing is enabled only
6473 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6474 * queue is less no of segments that can be accommodated in
6477 if (qpp > num_seg) {
6479 "Incorrect number of egress queues per page\n");
6481 goto out_free_adapter;
6483 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6484 pci_resource_len(pdev, 2));
6485 if (!adapter->bar2) {
6486 dev_err(&pdev->dev, "cannot map device bar2 region\n");
6488 goto out_free_adapter;
6492 setup_memwin(adapter);
6493 err = adap_init0(adapter);
6494 setup_memwin_rdma(adapter);
6498 for_each_port(adapter, i) {
6499 struct net_device *netdev;
6501 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6508 SET_NETDEV_DEV(netdev, &pdev->dev);
6510 adapter->port[i] = netdev;
6511 pi = netdev_priv(netdev);
6512 pi->adapter = adapter;
6513 pi->xact_addr_filt = -1;
6515 netdev->irq = pdev->irq;
6517 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6518 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6519 NETIF_F_RXCSUM | NETIF_F_RXHASH |
6520 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6522 netdev->hw_features |= NETIF_F_HIGHDMA;
6523 netdev->features |= netdev->hw_features;
6524 netdev->vlan_features = netdev->features & VLAN_FEAT;
6526 netdev->priv_flags |= IFF_UNICAST_FLT;
6528 netdev->netdev_ops = &cxgb4_netdev_ops;
6529 #ifdef CONFIG_CHELSIO_T4_DCB
6530 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6531 cxgb4_dcb_state_init(netdev);
6533 netdev->ethtool_ops = &cxgb_ethtool_ops;
6536 pci_set_drvdata(pdev, adapter);
6538 if (adapter->flags & FW_OK) {
6539 err = t4_port_init(adapter, func, func, 0);
6545 * Configure queues and allocate tables now, they can be needed as
6546 * soon as the first register_netdev completes.
6548 cfg_queues(adapter);
6550 adapter->l2t = t4_init_l2t();
6551 if (!adapter->l2t) {
6552 /* We tolerate a lack of L2T, giving up some functionality */
6553 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6554 adapter->params.offload = 0;
6557 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6558 dev_warn(&pdev->dev, "could not allocate TID table, "
6560 adapter->params.offload = 0;
6563 /* See what interrupts we'll be using */
6564 if (msi > 1 && enable_msix(adapter) == 0)
6565 adapter->flags |= USING_MSIX;
6566 else if (msi > 0 && pci_enable_msi(pdev) == 0)
6567 adapter->flags |= USING_MSI;
6569 err = init_rss(adapter);
6574 * The card is now ready to go. If any errors occur during device
6575 * registration we do not fail the whole card but rather proceed only
6576 * with the ports we manage to register successfully. However we must
6577 * register at least one net device.
6579 for_each_port(adapter, i) {
6580 pi = adap2pinfo(adapter, i);
6581 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6582 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6584 err = register_netdev(adapter->port[i]);
6587 adapter->chan_map[pi->tx_chan] = i;
6588 print_port_info(adapter->port[i]);
6591 dev_err(&pdev->dev, "could not register any net devices\n");
6595 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6599 if (cxgb4_debugfs_root) {
6600 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6601 cxgb4_debugfs_root);
6602 setup_debugfs(adapter);
6605 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6606 pdev->needs_freset = 1;
6608 if (is_offload(adapter))
6609 attach_ulds(adapter);
6612 #ifdef CONFIG_PCI_IOV
6613 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
6614 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6615 dev_info(&pdev->dev,
6616 "instantiated %u virtual functions\n",
6622 free_some_resources(adapter);
6624 if (!is_t4(adapter->params.chip))
6625 iounmap(adapter->bar2);
6628 destroy_workqueue(adapter->workq);
6634 pci_disable_pcie_error_reporting(pdev);
6635 pci_disable_device(pdev);
6636 out_release_regions:
6637 pci_release_regions(pdev);
6641 static void remove_one(struct pci_dev *pdev)
6643 struct adapter *adapter = pci_get_drvdata(pdev);
6645 #ifdef CONFIG_PCI_IOV
6646 pci_disable_sriov(pdev);
6653 /* Tear down per-adapter Work Queue first since it can contain
6654 * references to our adapter data structure.
6656 destroy_workqueue(adapter->workq);
6658 if (is_offload(adapter))
6659 detach_ulds(adapter);
6661 for_each_port(adapter, i)
6662 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6663 unregister_netdev(adapter->port[i]);
6665 debugfs_remove_recursive(adapter->debugfs_root);
6667 /* If we allocated filters, free up state associated with any
6670 if (adapter->tids.ftid_tab) {
6671 struct filter_entry *f = &adapter->tids.ftid_tab[0];
6672 for (i = 0; i < (adapter->tids.nftids +
6673 adapter->tids.nsftids); i++, f++)
6675 clear_filter(adapter, f);
6678 if (adapter->flags & FULL_INIT_DONE)
6681 free_some_resources(adapter);
6682 iounmap(adapter->regs);
6683 if (!is_t4(adapter->params.chip))
6684 iounmap(adapter->bar2);
6685 pci_disable_pcie_error_reporting(pdev);
6686 if ((adapter->flags & DEV_ENABLED)) {
6687 pci_disable_device(pdev);
6688 adapter->flags &= ~DEV_ENABLED;
6690 pci_release_regions(pdev);
6694 pci_release_regions(pdev);
6697 static struct pci_driver cxgb4_driver = {
6698 .name = KBUILD_MODNAME,
6699 .id_table = cxgb4_pci_tbl,
6701 .remove = remove_one,
6702 .shutdown = remove_one,
6703 .err_handler = &cxgb4_eeh,
6706 static int __init cxgb4_init_module(void)
6710 /* Debugfs support is optional, just warn if this fails */
6711 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6712 if (!cxgb4_debugfs_root)
6713 pr_warn("could not create debugfs entry, continuing\n");
6715 ret = pci_register_driver(&cxgb4_driver);
6717 debugfs_remove(cxgb4_debugfs_root);
6719 #if IS_ENABLED(CONFIG_IPV6)
6720 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6726 static void __exit cxgb4_cleanup_module(void)
6728 #if IS_ENABLED(CONFIG_IPV6)
6729 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6731 pci_unregister_driver(&cxgb4_driver);
6732 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
6735 module_init(cxgb4_init_module);
6736 module_exit(cxgb4_cleanup_module);