drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <asm/uaccess.h>
  66
  67 #include "cxgb4.h"
  68 #include "t4_regs.h"
  69 #include "t4_msg.h"
  70 #include "t4fw_api.h"
  71 #include "cxgb4_dcb.h"
  72 #include "cxgb4_debugfs.h"
  73 #include "l2t.h"
  74
  75 #ifdef DRV_VERSION
  76 #undef DRV_VERSION
  77 #endif
  78 #define DRV_VERSION "2.0.0-ko"
  79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
  80
  81 /*
  82  * Max interrupt hold-off timer value in us.  Queues fall back to this value
  83  * under extreme memory pressure so it's largish to give the system time to
  84  * recover.
  85  */
  86 #define MAX_SGE_TIMERVAL 200U
  87
  88 enum {
  89         /*
  90          * Physical Function provisioning constants.
  91          */
  92         PFRES_NVI = 4,                  /* # of Virtual Interfaces */
  93         PFRES_NETHCTRL = 128,           /* # of EQs used for ETH or CTRL Qs */
  94         PFRES_NIQFLINT = 128,           /* # of ingress Qs/w Free List(s)/intr
  95                                          */
  96         PFRES_NEQ = 256,                /* # of egress queues */
  97         PFRES_NIQ = 0,                  /* # of ingress queues */
  98         PFRES_TC = 0,                   /* PCI-E traffic class */
  99         PFRES_NEXACTF = 128,            /* # of exact MPS filters */
 100
 101         PFRES_R_CAPS = FW_CMD_CAP_PF,
 102         PFRES_WX_CAPS = FW_CMD_CAP_PF,
 103
 104 #ifdef CONFIG_PCI_IOV
 105         /*
 106          * Virtual Function provisioning constants.  We need two extra Ingress
 107          * Queues with Interrupt capability to serve as the VF's Firmware
 108          * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
 109          * neither will have Free Lists associated with them).  For each
 110          * Ethernet/Control Egress Queue and for each Free List, we need an
 111          * Egress Context.
 112          */
 113         VFRES_NPORTS = 1,               /* # of "ports" per VF */
 114         VFRES_NQSETS = 2,               /* # of "Queue Sets" per VF */
 115
 116         VFRES_NVI = VFRES_NPORTS,       /* # of Virtual Interfaces */
 117         VFRES_NETHCTRL = VFRES_NQSETS,  /* # of EQs used for ETH or CTRL Qs */
 118         VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
 119         VFRES_NEQ = VFRES_NQSETS*2,     /* # of egress queues */
 120         VFRES_NIQ = 0,                  /* # of non-fl/int ingress queues */
 121         VFRES_TC = 0,                   /* PCI-E traffic class */
 122         VFRES_NEXACTF = 16,             /* # of exact MPS filters */
 123
 124         VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
 125         VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
 126 #endif
 127 };
 128
 129 /*
 130  * Provide a Port Access Rights Mask for the specified PF/VF.  This is very
 131  * static and likely not to be useful in the long run.  We really need to
 132  * implement some form of persistent configuration which the firmware
 133  * controls.
 134  */
 135 static unsigned int pfvfres_pmask(struct adapter *adapter,
 136                                   unsigned int pf, unsigned int vf)
 137 {
 138         unsigned int portn, portvec;
 139
 140         /*
 141          * Give PF's access to all of the ports.
 142          */
 143         if (vf == 0)
 144                 return FW_PFVF_CMD_PMASK_MASK;
 145
 146         /*
 147          * For VFs, we'll assign them access to the ports based purely on the
 148          * PF.  We assign active ports in order, wrapping around if there are
 149          * fewer active ports than PFs: e.g. active port[pf % nports].
 150          * Unfortunately the adapter's port_info structs haven't been
 151          * initialized yet so we have to compute this.
 152          */
 153         if (adapter->params.nports == 0)
 154                 return 0;
 155
 156         portn = pf % adapter->params.nports;
 157         portvec = adapter->params.portvec;
 158         for (;;) {
 159                 /*
 160                  * Isolate the lowest set bit in the port vector.  If we're at
 161                  * the port number that we want, return that as the pmask.
 162                  * otherwise mask that bit out of the port vector and
 163                  * decrement our port number ...
 164                  */
 165                 unsigned int pmask = portvec ^ (portvec & (portvec-1));
 166                 if (portn == 0)
 167                         return pmask;
 168                 portn--;
 169                 portvec &= ~pmask;
 170         }
 171         /*NOTREACHED*/
 172 }
 173
 174 enum {
 175         MAX_TXQ_ENTRIES      = 16384,
 176         MAX_CTRL_TXQ_ENTRIES = 1024,
 177         MAX_RSPQ_ENTRIES     = 16384,
 178         MAX_RX_BUFFERS       = 16384,
 179         MIN_TXQ_ENTRIES      = 32,
 180         MIN_CTRL_TXQ_ENTRIES = 32,
 181         MIN_RSPQ_ENTRIES     = 128,
 182         MIN_FL_ENTRIES       = 16
 183 };
 184
 185 /* Host shadow copy of ingress filter entry.  This is in host native format
 186  * and doesn't match the ordering or bit order, etc. of the hardware of the
 187  * firmware command.  The use of bit-field structure elements is purely to
 188  * remind ourselves of the field size limitations and save memory in the case
 189  * where the filter table is large.
 190  */
 191 struct filter_entry {
 192         /* Administrative fields for filter.
 193          */
 194         u32 valid:1;            /* filter allocated and valid */
 195         u32 locked:1;           /* filter is administratively locked */
 196
 197         u32 pending:1;          /* filter action is pending firmware reply */
 198         u32 smtidx:8;           /* Source MAC Table index for smac */
 199         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 200
 201         /* The filter itself.  Most of this is a straight copy of information
 202          * provided by the extended ioctl().  Some fields are translated to
 203          * internal forms -- for instance the Ingress Queue ID passed in from
 204          * the ioctl() is translated into the Absolute Ingress Queue ID.
 205          */
 206         struct ch_filter_specification fs;
 207 };
 208
 209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
 210                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
 211                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 212
 213 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
 214
 215 static const struct pci_device_id cxgb4_pci_tbl[] = {
 216         CH_DEVICE(0xa000, 0),  /* PE10K */
 217         CH_DEVICE(0x4001, -1),
 218         CH_DEVICE(0x4002, -1),
 219         CH_DEVICE(0x4003, -1),
 220         CH_DEVICE(0x4004, -1),
 221         CH_DEVICE(0x4005, -1),
 222         CH_DEVICE(0x4006, -1),
 223         CH_DEVICE(0x4007, -1),
 224         CH_DEVICE(0x4008, -1),
 225         CH_DEVICE(0x4009, -1),
 226         CH_DEVICE(0x400a, -1),
 227         CH_DEVICE(0x400d, -1),
 228         CH_DEVICE(0x400e, -1),
 229         CH_DEVICE(0x4080, -1),
 230         CH_DEVICE(0x4081, -1),
 231         CH_DEVICE(0x4082, -1),
 232         CH_DEVICE(0x4083, -1),
 233         CH_DEVICE(0x4084, -1),
 234         CH_DEVICE(0x4085, -1),
 235         CH_DEVICE(0x4086, -1),
 236         CH_DEVICE(0x4087, -1),
 237         CH_DEVICE(0x4088, -1),
 238         CH_DEVICE(0x4401, 4),
 239         CH_DEVICE(0x4402, 4),
 240         CH_DEVICE(0x4403, 4),
 241         CH_DEVICE(0x4404, 4),
 242         CH_DEVICE(0x4405, 4),
 243         CH_DEVICE(0x4406, 4),
 244         CH_DEVICE(0x4407, 4),
 245         CH_DEVICE(0x4408, 4),
 246         CH_DEVICE(0x4409, 4),
 247         CH_DEVICE(0x440a, 4),
 248         CH_DEVICE(0x440d, 4),
 249         CH_DEVICE(0x440e, 4),
 250         CH_DEVICE(0x4480, 4),
 251         CH_DEVICE(0x4481, 4),
 252         CH_DEVICE(0x4482, 4),
 253         CH_DEVICE(0x4483, 4),
 254         CH_DEVICE(0x4484, 4),
 255         CH_DEVICE(0x4485, 4),
 256         CH_DEVICE(0x4486, 4),
 257         CH_DEVICE(0x4487, 4),
 258         CH_DEVICE(0x4488, 4),
 259         CH_DEVICE(0x5001, 4),
 260         CH_DEVICE(0x5002, 4),
 261         CH_DEVICE(0x5003, 4),
 262         CH_DEVICE(0x5004, 4),
 263         CH_DEVICE(0x5005, 4),
 264         CH_DEVICE(0x5006, 4),
 265         CH_DEVICE(0x5007, 4),
 266         CH_DEVICE(0x5008, 4),
 267         CH_DEVICE(0x5009, 4),
 268         CH_DEVICE(0x500A, 4),
 269         CH_DEVICE(0x500B, 4),
 270         CH_DEVICE(0x500C, 4),
 271         CH_DEVICE(0x500D, 4),
 272         CH_DEVICE(0x500E, 4),
 273         CH_DEVICE(0x500F, 4),
 274         CH_DEVICE(0x5010, 4),
 275         CH_DEVICE(0x5011, 4),
 276         CH_DEVICE(0x5012, 4),
 277         CH_DEVICE(0x5013, 4),
 278         CH_DEVICE(0x5014, 4),
 279         CH_DEVICE(0x5015, 4),
 280         CH_DEVICE(0x5080, 4),
 281         CH_DEVICE(0x5081, 4),
 282         CH_DEVICE(0x5082, 4),
 283         CH_DEVICE(0x5083, 4),
 284         CH_DEVICE(0x5084, 4),
 285         CH_DEVICE(0x5085, 4),
 286         CH_DEVICE(0x5086, 4),
 287         CH_DEVICE(0x5087, 4),
 288         CH_DEVICE(0x5088, 4),
 289         CH_DEVICE(0x5401, 4),
 290         CH_DEVICE(0x5402, 4),
 291         CH_DEVICE(0x5403, 4),
 292         CH_DEVICE(0x5404, 4),
 293         CH_DEVICE(0x5405, 4),
 294         CH_DEVICE(0x5406, 4),
 295         CH_DEVICE(0x5407, 4),
 296         CH_DEVICE(0x5408, 4),
 297         CH_DEVICE(0x5409, 4),
 298         CH_DEVICE(0x540A, 4),
 299         CH_DEVICE(0x540B, 4),
 300         CH_DEVICE(0x540C, 4),
 301         CH_DEVICE(0x540D, 4),
 302         CH_DEVICE(0x540E, 4),
 303         CH_DEVICE(0x540F, 4),
 304         CH_DEVICE(0x5410, 4),
 305         CH_DEVICE(0x5411, 4),
 306         CH_DEVICE(0x5412, 4),
 307         CH_DEVICE(0x5413, 4),
 308         CH_DEVICE(0x5414, 4),
 309         CH_DEVICE(0x5415, 4),
 310         CH_DEVICE(0x5480, 4),
 311         CH_DEVICE(0x5481, 4),
 312         CH_DEVICE(0x5482, 4),
 313         CH_DEVICE(0x5483, 4),
 314         CH_DEVICE(0x5484, 4),
 315         CH_DEVICE(0x5485, 4),
 316         CH_DEVICE(0x5486, 4),
 317         CH_DEVICE(0x5487, 4),
 318         CH_DEVICE(0x5488, 4),
 319         { 0, }
 320 };
 321
 322 #define FW4_FNAME "cxgb4/t4fw.bin"
 323 #define FW5_FNAME "cxgb4/t5fw.bin"
 324 #define FW4_CFNAME "cxgb4/t4-config.txt"
 325 #define FW5_CFNAME "cxgb4/t5-config.txt"
 326
 327 MODULE_DESCRIPTION(DRV_DESC);
 328 MODULE_AUTHOR("Chelsio Communications");
 329 MODULE_LICENSE("Dual BSD/GPL");
 330 MODULE_VERSION(DRV_VERSION);
 331 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 332 MODULE_FIRMWARE(FW4_FNAME);
 333 MODULE_FIRMWARE(FW5_FNAME);
 334
 335 /*
 336  * Normally we're willing to become the firmware's Master PF but will be happy
 337  * if another PF has already become the Master and initialized the adapter.
 338  * Setting "force_init" will cause this driver to forcibly establish itself as
 339  * the Master PF and initialize the adapter.
 340  */
 341 static uint force_init;
 342
 343 module_param(force_init, uint, 0644);
 344 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
 345
 346 /*
 347  * Normally if the firmware we connect to has Configuration File support, we
 348  * use that and only fall back to the old Driver-based initialization if the
 349  * Configuration File fails for some reason.  If force_old_init is set, then
 350  * we'll always use the old Driver-based initialization sequence.
 351  */
 352 static uint force_old_init;
 353
 354 module_param(force_old_init, uint, 0644);
 355 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
 356
 357 static int dflt_msg_enable = DFLT_MSG_ENABLE;
 358
 359 module_param(dflt_msg_enable, int, 0644);
 360 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
 361
 362 /*
 363  * The driver uses the best interrupt scheme available on a platform in the
 364  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 365  * of these schemes the driver may consider as follows:
 366  *
 367  * msi = 2: choose from among all three options
 368  * msi = 1: only consider MSI and INTx interrupts
 369  * msi = 0: force INTx interrupts
 370  */
 371 static int msi = 2;
 372
 373 module_param(msi, int, 0644);
 374 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 375
 376 /*
 377  * Queue interrupt hold-off timer values.  Queues default to the first of these
 378  * upon creation.
 379  */
 380 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
 381
 382 module_param_array(intr_holdoff, uint, NULL, 0644);
 383 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
 384                  "0..4 in microseconds");
 385
 386 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
 387
 388 module_param_array(intr_cnt, uint, NULL, 0644);
 389 MODULE_PARM_DESC(intr_cnt,
 390                  "thresholds 1..3 for queue interrupt packet counters");
 391
 392 /*
 393  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 394  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 395  * boundaries.  This is a requirement for many architectures which will throw
 396  * a machine check fault if an attempt is made to access one of the 4-byte IP
 397  * header fields on a non-4-byte boundary.  And it's a major performance issue
 398  * even on some architectures which allow it like some implementations of the
 399  * x86 ISA.  However, some architectures don't mind this and for some very
 400  * edge-case performance sensitive applications (like forwarding large volumes
 401  * of small packets), setting this DMA offset to 0 will decrease the number of
 402  * PCI-E Bus transfers enough to measurably affect performance.
 403  */
 404 static int rx_dma_offset = 2;
 405
 406 static bool vf_acls;
 407
 408 #ifdef CONFIG_PCI_IOV
 409 module_param(vf_acls, bool, 0644);
 410 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
 411
 412 /* Configure the number of PCI-E Virtual Function which are to be instantiated
 413  * on SR-IOV Capable Physical Functions.
 414  */
 415 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
 416
 417 module_param_array(num_vf, uint, NULL, 0644);
 418 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
 419 #endif
 420
 421 /* TX Queue select used to determine what algorithm to use for selecting TX
 422  * queue. Select between the kernel provided function (select_queue=0) or user
 423  * cxgb_select_queue function (select_queue=1)
 424  *
 425  * Default: select_queue=0
 426  */
 427 static int select_queue;
 428 module_param(select_queue, int, 0644);
 429 MODULE_PARM_DESC(select_queue,
 430                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 431
 432 /*
 433  * The filter TCAM has a fixed portion and a variable portion.  The fixed
 434  * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
 435  * ports.  The variable portion is 36 bits which can include things like Exact
 436  * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
 437  * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
 438  * far exceed the 36-bit budget for this "compressed" header portion of the
 439  * filter.  Thus, we have a scarce resource which must be carefully managed.
 440  *
 441  * By default we set this up to mostly match the set of filter matching
 442  * capabilities of T3 but with accommodations for some of T4's more
 443  * interesting features:
 444  *
 445  *   { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
 446  *     [Inner] VLAN (17), Port (3), FCoE (1) }
 447  */
 448 enum {
 449         TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
 450         TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
 451         TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
 452 };
 453
 454 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
 455
 456 module_param(tp_vlan_pri_map, uint, 0644);
 457 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
 458
 459 static struct dentry *cxgb4_debugfs_root;
 460
 461 static LIST_HEAD(adapter_list);
 462 static DEFINE_MUTEX(uld_mutex);
 463 /* Adapter list to be accessed from atomic context */
 464 static LIST_HEAD(adap_rcu_list);
 465 static DEFINE_SPINLOCK(adap_rcu_lock);
 466 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
 467 static const char *uld_str[] = { "RDMA", "iSCSI" };
 468
 469 static void link_report(struct net_device *dev)
 470 {
 471         if (!netif_carrier_ok(dev))
 472                 netdev_info(dev, "link down\n");
 473         else {
 474                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 475
 476                 const char *s = "10Mbps";
 477                 const struct port_info *p = netdev_priv(dev);
 478
 479                 switch (p->link_cfg.speed) {
 480                 case 10000:
 481                         s = "10Gbps";
 482                         break;
 483                 case 1000:
 484                         s = "1000Mbps";
 485                         break;
 486                 case 100:
 487                         s = "100Mbps";
 488                         break;
 489                 case 40000:
 490                         s = "40Gbps";
 491                         break;
 492                 }
 493
 494                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 495                             fc[p->link_cfg.fc]);
 496         }
 497 }
 498
 499 #ifdef CONFIG_CHELSIO_T4_DCB
 500 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 501 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 502 {
 503         struct port_info *pi = netdev_priv(dev);
 504         struct adapter *adap = pi->adapter;
 505         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 506         int i;
 507
 508         /* We use a simple mapping of Port TX Queue Index to DCB
 509          * Priority when we're enabling DCB.
 510          */
 511         for (i = 0; i < pi->nqsets; i++, txq++) {
 512                 u32 name, value;
 513                 int err;
 514
 515                 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 516                         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 517                         FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
 518                 value = enable ? i : 0xffffffff;
 519
 520                 /* Since we can be called while atomic (from "interrupt
 521                  * level") we need to issue the Set Parameters Commannd
 522                  * without sleeping (timeout < 0).
 523                  */
 524                 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
 525                                             &name, &value);
 526
 527                 if (err)
 528                         dev_err(adap->pdev_dev,
 529                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 530                                 enable ? "set" : "unset", pi->port_id, i, -err);
 531                 else
 532                         txq->dcb_prio = value;
 533         }
 534 }
 535 #endif /* CONFIG_CHELSIO_T4_DCB */
 536
 537 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 538 {
 539         struct net_device *dev = adapter->port[port_id];
 540
 541         /* Skip changes from disabled ports. */
 542         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 543                 if (link_stat)
 544                         netif_carrier_on(dev);
 545                 else {
 546 #ifdef CONFIG_CHELSIO_T4_DCB
 547                         cxgb4_dcb_state_init(dev);
 548                         dcb_tx_queue_prio_enable(dev, false);
 549 #endif /* CONFIG_CHELSIO_T4_DCB */
 550                         netif_carrier_off(dev);
 551                 }
 552
 553                 link_report(dev);
 554         }
 555 }
 556
 557 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 558 {
 559         static const char *mod_str[] = {
 560                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 561         };
 562
 563         const struct net_device *dev = adap->port[port_id];
 564         const struct port_info *pi = netdev_priv(dev);
 565
 566         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 567                 netdev_info(dev, "port module unplugged\n");
 568         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 569                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 570 }
 571
 572 /*
 573  * Configure the exact and hash address filters to handle a port's multicast
 574  * and secondary unicast MAC addresses.
 575  */
 576 static int set_addr_filters(const struct net_device *dev, bool sleep)
 577 {
 578         u64 mhash = 0;
 579         u64 uhash = 0;
 580         bool free = true;
 581         u16 filt_idx[7];
 582         const u8 *addr[7];
 583         int ret, naddr = 0;
 584         const struct netdev_hw_addr *ha;
 585         int uc_cnt = netdev_uc_count(dev);
 586         int mc_cnt = netdev_mc_count(dev);
 587         const struct port_info *pi = netdev_priv(dev);
 588         unsigned int mb = pi->adapter->fn;
 589
 590         /* first do the secondary unicast addresses */
 591         netdev_for_each_uc_addr(ha, dev) {
 592                 addr[naddr++] = ha->addr;
 593                 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 594                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 595                                         naddr, addr, filt_idx, &uhash, sleep);
 596                         if (ret < 0)
 597                                 return ret;
 598
 599                         free = false;
 600                         naddr = 0;
 601                 }
 602         }
 603
 604         /* next set up the multicast addresses */
 605         netdev_for_each_mc_addr(ha, dev) {
 606                 addr[naddr++] = ha->addr;
 607                 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 608                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 609                                         naddr, addr, filt_idx, &mhash, sleep);
 610                         if (ret < 0)
 611                                 return ret;
 612
 613                         free = false;
 614                         naddr = 0;
 615                 }
 616         }
 617
 618         return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
 619                                 uhash | mhash, sleep);
 620 }
 621
 622 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 623 module_param(dbfifo_int_thresh, int, 0644);
 624 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 625
 626 /*
 627  * usecs to sleep while draining the dbfifo
 628  */
 629 static int dbfifo_drain_delay = 1000;
 630 module_param(dbfifo_drain_delay, int, 0644);
 631 MODULE_PARM_DESC(dbfifo_drain_delay,
 632                  "usecs to sleep while draining the dbfifo");
 633
 634 /*
 635  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 636  * If @mtu is -1 it is left unchanged.
 637  */
 638 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 639 {
 640         int ret;
 641         struct port_info *pi = netdev_priv(dev);
 642
 643         ret = set_addr_filters(dev, sleep_ok);
 644         if (ret == 0)
 645                 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
 646                                     (dev->flags & IFF_PROMISC) ? 1 : 0,
 647                                     (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 648                                     sleep_ok);
 649         return ret;
 650 }
 651
 652 /**
 653  *      link_start - enable a port
 654  *      @dev: the port to enable
 655  *
 656  *      Performs the MAC and PHY actions needed to enable a port.
 657  */
 658 static int link_start(struct net_device *dev)
 659 {
 660         int ret;
 661         struct port_info *pi = netdev_priv(dev);
 662         unsigned int mb = pi->adapter->fn;
 663
 664         /*
 665          * We do not set address filters and promiscuity here, the stack does
 666          * that step explicitly.
 667          */
 668         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 669                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 670         if (ret == 0) {
 671                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 672                                     pi->xact_addr_filt, dev->dev_addr, true,
 673                                     true);
 674                 if (ret >= 0) {
 675                         pi->xact_addr_filt = ret;
 676                         ret = 0;
 677                 }
 678         }
 679         if (ret == 0)
 680                 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
 681                                     &pi->link_cfg);
 682         if (ret == 0) {
 683                 local_bh_disable();
 684                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 685                                           true, CXGB4_DCB_ENABLED);
 686                 local_bh_enable();
 687         }
 688
 689         return ret;
 690 }
 691
 692 int cxgb4_dcb_enabled(const struct net_device *dev)
 693 {
 694 #ifdef CONFIG_CHELSIO_T4_DCB
 695         struct port_info *pi = netdev_priv(dev);
 696
 697         if (!pi->dcb.enabled)
 698                 return 0;
 699
 700         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 701                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 702 #else
 703         return 0;
 704 #endif
 705 }
 706 EXPORT_SYMBOL(cxgb4_dcb_enabled);
 707
 708 #ifdef CONFIG_CHELSIO_T4_DCB
 709 /* Handle a Data Center Bridging update message from the firmware. */
 710 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 711 {
 712         int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
 713         struct net_device *dev = adap->port[port];
 714         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 715         int new_dcb_enabled;
 716
 717         cxgb4_dcb_handle_fw_update(adap, pcmd);
 718         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 719
 720         /* If the DCB has become enabled or disabled on the port then we're
 721          * going to need to set up/tear down DCB Priority parameters for the
 722          * TX Queues associated with the port.
 723          */
 724         if (new_dcb_enabled != old_dcb_enabled)
 725                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 726 }
 727 #endif /* CONFIG_CHELSIO_T4_DCB */
 728
 729 /* Clear a filter and release any of its resources that we own.  This also
 730  * clears the filter's "pending" status.
 731  */
 732 static void clear_filter(struct adapter *adap, struct filter_entry *f)
 733 {
 734         /* If the new or old filter have loopback rewriteing rules then we'll
 735          * need to free any existing Layer Two Table (L2T) entries of the old
 736          * filter rule.  The firmware will handle freeing up any Source MAC
 737          * Table (SMT) entries used for rewriting Source MAC Addresses in
 738          * loopback rules.
 739          */
 740         if (f->l2t)
 741                 cxgb4_l2t_release(f->l2t);
 742
 743         /* The zeroing of the filter rule below clears the filter valid,
 744          * pending, locked flags, l2t pointer, etc. so it's all we need for
 745          * this operation.
 746          */
 747         memset(f, 0, sizeof(*f));
 748 }
 749
 750 /* Handle a filter write/deletion reply.
 751  */
 752 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
 753 {
 754         unsigned int idx = GET_TID(rpl);
 755         unsigned int nidx = idx - adap->tids.ftid_base;
 756         unsigned int ret;
 757         struct filter_entry *f;
 758
 759         if (idx >= adap->tids.ftid_base && nidx <
 760            (adap->tids.nftids + adap->tids.nsftids)) {
 761                 idx = nidx;
 762                 ret = GET_TCB_COOKIE(rpl->cookie);
 763                 f = &adap->tids.ftid_tab[idx];
 764
 765                 if (ret == FW_FILTER_WR_FLT_DELETED) {
 766                         /* Clear the filter when we get confirmation from the
 767                          * hardware that the filter has been deleted.
 768                          */
 769                         clear_filter(adap, f);
 770                 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
 771                         dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
 772                                 idx);
 773                         clear_filter(adap, f);
 774                 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
 775                         f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
 776                         f->pending = 0;  /* asynchronous setup completed */
 777                         f->valid = 1;
 778                 } else {
 779                         /* Something went wrong.  Issue a warning about the
 780                          * problem and clear everything out.
 781                          */
 782                         dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
 783                                 idx, ret);
 784                         clear_filter(adap, f);
 785                 }
 786         }
 787 }
 788
 789 /* Response queue handler for the FW event queue.
 790  */
 791 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 792                           const struct pkt_gl *gl)
 793 {
 794         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 795
 796         rsp++;                                          /* skip RSS header */
 797
 798         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 799          */
 800         if (unlikely(opcode == CPL_FW4_MSG &&
 801            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 802                 rsp++;
 803                 opcode = ((const struct rss_header *)rsp)->opcode;
 804                 rsp++;
 805                 if (opcode != CPL_SGE_EGR_UPDATE) {
 806                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 807                                 , opcode);
 808                         goto out;
 809                 }
 810         }
 811
 812         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 813                 const struct cpl_sge_egr_update *p = (void *)rsp;
 814                 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
 815                 struct sge_txq *txq;
 816
 817                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 818                 txq->restarts++;
 819                 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
 820                         struct sge_eth_txq *eq;
 821
 822                         eq = container_of(txq, struct sge_eth_txq, q);
 823                         netif_tx_wake_queue(eq->txq);
 824                 } else {
 825                         struct sge_ofld_txq *oq;
 826
 827                         oq = container_of(txq, struct sge_ofld_txq, q);
 828                         tasklet_schedule(&oq->qresume_tsk);
 829                 }
 830         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 831                 const struct cpl_fw6_msg *p = (void *)rsp;
 832
 833 #ifdef CONFIG_CHELSIO_T4_DCB
 834                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 835                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 836                 unsigned int action =
 837                         FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
 838
 839                 if (cmd == FW_PORT_CMD &&
 840                     action == FW_PORT_ACTION_GET_PORT_INFO) {
 841                         int port = FW_PORT_CMD_PORTID_GET(
 842                                         be32_to_cpu(pcmd->op_to_portid));
 843                         struct net_device *dev = q->adap->port[port];
 844                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
 845                                             FW_PORT_CMD_DCBXDIS)
 846                                            ? CXGB4_DCB_INPUT_FW_DISABLED
 847                                            : CXGB4_DCB_INPUT_FW_ENABLED);
 848
 849                         cxgb4_dcb_state_fsm(dev, state_input);
 850                 }
 851
 852                 if (cmd == FW_PORT_CMD &&
 853                     action == FW_PORT_ACTION_L2_DCB_CFG)
 854                         dcb_rpl(q->adap, pcmd);
 855                 else
 856 #endif
 857                         if (p->type == 0)
 858                                 t4_handle_fw_rpl(q->adap, p->data);
 859         } else if (opcode == CPL_L2T_WRITE_RPL) {
 860                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 861
 862                 do_l2t_write_rpl(q->adap, p);
 863         } else if (opcode == CPL_SET_TCB_RPL) {
 864                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 865
 866                 filter_rpl(q->adap, p);
 867         } else
 868                 dev_err(q->adap->pdev_dev,
 869                         "unexpected CPL %#x on FW event queue\n", opcode);
 870 out:
 871         return 0;
 872 }
 873
 874 /**
 875  *      uldrx_handler - response queue handler for ULD queues
 876  *      @q: the response queue that received the packet
 877  *      @rsp: the response queue descriptor holding the offload message
 878  *      @gl: the gather list of packet fragments
 879  *
 880  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 881  *      the ULD, we just maintain statistics.
 882  */
 883 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 884                          const struct pkt_gl *gl)
 885 {
 886         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 887
 888         /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
 889          */
 890         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
 891             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
 892                 rsp += 2;
 893
 894         if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
 895                 rxq->stats.nomem++;
 896                 return -1;
 897         }
 898         if (gl == NULL)
 899                 rxq->stats.imm++;
 900         else if (gl == CXGB4_MSG_AN)
 901                 rxq->stats.an++;
 902         else
 903                 rxq->stats.pkts++;
 904         return 0;
 905 }
 906
 907 static void disable_msi(struct adapter *adapter)
 908 {
 909         if (adapter->flags & USING_MSIX) {
 910                 pci_disable_msix(adapter->pdev);
 911                 adapter->flags &= ~USING_MSIX;
 912         } else if (adapter->flags & USING_MSI) {
 913                 pci_disable_msi(adapter->pdev);
 914                 adapter->flags &= ~USING_MSI;
 915         }
 916 }
 917
 918 /*
 919  * Interrupt handler for non-data events used with MSI-X.
 920  */
 921 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 922 {
 923         struct adapter *adap = cookie;
 924
 925         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
 926         if (v & PFSW) {
 927                 adap->swintr = 1;
 928                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
 929         }
 930         t4_slow_intr_handler(adap);
 931         return IRQ_HANDLED;
 932 }
 933
 934 /*
 935  * Name the MSI-X interrupts.
 936  */
 937 static void name_msix_vecs(struct adapter *adap)
 938 {
 939         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 940
 941         /* non-data interrupts */
 942         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 943
 944         /* FW events */
 945         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 946                  adap->port[0]->name);
 947
 948         /* Ethernet queues */
 949         for_each_port(adap, j) {
 950                 struct net_device *d = adap->port[j];
 951                 const struct port_info *pi = netdev_priv(d);
 952
 953                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 954                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 955                                  d->name, i);
 956         }
 957
 958         /* offload queues */
 959         for_each_ofldrxq(&adap->sge, i)
 960                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
 961                          adap->port[0]->name, i);
 962
 963         for_each_rdmarxq(&adap->sge, i)
 964                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
 965                          adap->port[0]->name, i);
 966
 967         for_each_rdmaciq(&adap->sge, i)
 968                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
 969                          adap->port[0]->name, i);
 970 }
 971
 972 static int request_msix_queue_irqs(struct adapter *adap)
 973 {
 974         struct sge *s = &adap->sge;
 975         int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
 976         int msi_index = 2;
 977
 978         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 979                           adap->msix_info[1].desc, &s->fw_evtq);
 980         if (err)
 981                 return err;
 982
 983         for_each_ethrxq(s, ethqidx) {
 984                 err = request_irq(adap->msix_info[msi_index].vec,
 985                                   t4_sge_intr_msix, 0,
 986                                   adap->msix_info[msi_index].desc,
 987                                   &s->ethrxq[ethqidx].rspq);
 988                 if (err)
 989                         goto unwind;
 990                 msi_index++;
 991         }
 992         for_each_ofldrxq(s, ofldqidx) {
 993                 err = request_irq(adap->msix_info[msi_index].vec,
 994                                   t4_sge_intr_msix, 0,
 995                                   adap->msix_info[msi_index].desc,
 996                                   &s->ofldrxq[ofldqidx].rspq);
 997                 if (err)
 998                         goto unwind;
 999                 msi_index++;
1000         }
1001         for_each_rdmarxq(s, rdmaqidx) {
1002                 err = request_irq(adap->msix_info[msi_index].vec,
1003                                   t4_sge_intr_msix, 0,
1004                                   adap->msix_info[msi_index].desc,
1005                                   &s->rdmarxq[rdmaqidx].rspq);
1006                 if (err)
1007                         goto unwind;
1008                 msi_index++;
1009         }
1010         for_each_rdmaciq(s, rdmaciqqidx) {
1011                 err = request_irq(adap->msix_info[msi_index].vec,
1012                                   t4_sge_intr_msix, 0,
1013                                   adap->msix_info[msi_index].desc,
1014                                   &s->rdmaciq[rdmaciqqidx].rspq);
1015                 if (err)
1016                         goto unwind;
1017                 msi_index++;
1018         }
1019         return 0;
1020
1021 unwind:
1022         while (--rdmaciqqidx >= 0)
1023                 free_irq(adap->msix_info[--msi_index].vec,
1024                          &s->rdmaciq[rdmaciqqidx].rspq);
1025         while (--rdmaqidx >= 0)
1026                 free_irq(adap->msix_info[--msi_index].vec,
1027                          &s->rdmarxq[rdmaqidx].rspq);
1028         while (--ofldqidx >= 0)
1029                 free_irq(adap->msix_info[--msi_index].vec,
1030                          &s->ofldrxq[ofldqidx].rspq);
1031         while (--ethqidx >= 0)
1032                 free_irq(adap->msix_info[--msi_index].vec,
1033                          &s->ethrxq[ethqidx].rspq);
1034         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1035         return err;
1036 }
1037
1038 static void free_msix_queue_irqs(struct adapter *adap)
1039 {
1040         int i, msi_index = 2;
1041         struct sge *s = &adap->sge;
1042
1043         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1044         for_each_ethrxq(s, i)
1045                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
1046         for_each_ofldrxq(s, i)
1047                 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
1048         for_each_rdmarxq(s, i)
1049                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
1050         for_each_rdmaciq(s, i)
1051                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
1052 }
1053
1054 /**
1055  *      write_rss - write the RSS table for a given port
1056  *      @pi: the port
1057  *      @queues: array of queue indices for RSS
1058  *
1059  *      Sets up the portion of the HW RSS table for the port's VI to distribute
1060  *      packets to the Rx queues in @queues.
1061  */
1062 static int write_rss(const struct port_info *pi, const u16 *queues)
1063 {
1064         u16 *rss;
1065         int i, err;
1066         const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1067
1068         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1069         if (!rss)
1070                 return -ENOMEM;
1071
1072         /* map the queue indices to queue ids */
1073         for (i = 0; i < pi->rss_size; i++, queues++)
1074                 rss[i] = q[*queues].rspq.abs_id;
1075
1076         err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1077                                   pi->rss_size, rss, pi->rss_size);
1078         kfree(rss);
1079         return err;
1080 }
1081
1082 /**
1083  *      setup_rss - configure RSS
1084  *      @adap: the adapter
1085  *
1086  *      Sets up RSS for each port.
1087  */
1088 static int setup_rss(struct adapter *adap)
1089 {
1090         int i, err;
1091
1092         for_each_port(adap, i) {
1093                 const struct port_info *pi = adap2pinfo(adap, i);
1094
1095                 err = write_rss(pi, pi->rss);
1096                 if (err)
1097                         return err;
1098         }
1099         return 0;
1100 }
1101
1102 /*
1103  * Return the channel of the ingress queue with the given qid.
1104  */
1105 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1106 {
1107         qid -= p->ingr_start;
1108         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1109 }
1110
1111 /*
1112  * Wait until all NAPI handlers are descheduled.
1113  */
1114 static void quiesce_rx(struct adapter *adap)
1115 {
1116         int i;
1117
1118         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1119                 struct sge_rspq *q = adap->sge.ingr_map[i];
1120
1121                 if (q && q->handler)
1122                         napi_disable(&q->napi);
1123         }
1124 }
1125
1126 /*
1127  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1128  */
1129 static void enable_rx(struct adapter *adap)
1130 {
1131         int i;
1132
1133         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1134                 struct sge_rspq *q = adap->sge.ingr_map[i];
1135
1136                 if (!q)
1137                         continue;
1138                 if (q->handler)
1139                         napi_enable(&q->napi);
1140                 /* 0-increment GTS to start the timer and enable interrupts */
1141                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1142                              SEINTARM(q->intr_params) |
1143                              INGRESSQID(q->cntxt_id));
1144         }
1145 }
1146
1147 /**
1148  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1149  *      @adap: the adapter
1150  *
1151  *      Determines how many sets of SGE queues to use and initializes them.
1152  *      We support multiple queue sets per port if we have MSI-X, otherwise
1153  *      just one queue set per port.
1154  */
1155 static int setup_sge_queues(struct adapter *adap)
1156 {
1157         int err, msi_idx, i, j;
1158         struct sge *s = &adap->sge;
1159
1160         bitmap_zero(s->starving_fl, MAX_EGRQ);
1161         bitmap_zero(s->txq_maperr, MAX_EGRQ);
1162
1163         if (adap->flags & USING_MSIX)
1164                 msi_idx = 1;         /* vector 0 is for non-queue interrupts */
1165         else {
1166                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1167                                        NULL, NULL);
1168                 if (err)
1169                         return err;
1170                 msi_idx = -((int)s->intrq.abs_id + 1);
1171         }
1172
1173         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1174                                msi_idx, NULL, fwevtq_handler);
1175         if (err) {
1176 freeout:        t4_free_sge_resources(adap);
1177                 return err;
1178         }
1179
1180         for_each_port(adap, i) {
1181                 struct net_device *dev = adap->port[i];
1182                 struct port_info *pi = netdev_priv(dev);
1183                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1184                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1185
1186                 for (j = 0; j < pi->nqsets; j++, q++) {
1187                         if (msi_idx > 0)
1188                                 msi_idx++;
1189                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1190                                                msi_idx, &q->fl,
1191                                                t4_ethrx_handler);
1192                         if (err)
1193                                 goto freeout;
1194                         q->rspq.idx = j;
1195                         memset(&q->stats, 0, sizeof(q->stats));
1196                 }
1197                 for (j = 0; j < pi->nqsets; j++, t++) {
1198                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1199                                         netdev_get_tx_queue(dev, j),
1200                                         s->fw_evtq.cntxt_id);
1201                         if (err)
1202                                 goto freeout;
1203                 }
1204         }
1205
1206         j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1207         for_each_ofldrxq(s, i) {
1208                 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1209                 struct net_device *dev = adap->port[i / j];
1210
1211                 if (msi_idx > 0)
1212                         msi_idx++;
1213                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1214                                        q->fl.size ? &q->fl : NULL,
1215                                        uldrx_handler);
1216                 if (err)
1217                         goto freeout;
1218                 memset(&q->stats, 0, sizeof(q->stats));
1219                 s->ofld_rxq[i] = q->rspq.abs_id;
1220                 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1221                                             s->fw_evtq.cntxt_id);
1222                 if (err)
1223                         goto freeout;
1224         }
1225
1226         for_each_rdmarxq(s, i) {
1227                 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1228
1229                 if (msi_idx > 0)
1230                         msi_idx++;
1231                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1232                                        msi_idx, q->fl.size ? &q->fl : NULL,
1233                                        uldrx_handler);
1234                 if (err)
1235                         goto freeout;
1236                 memset(&q->stats, 0, sizeof(q->stats));
1237                 s->rdma_rxq[i] = q->rspq.abs_id;
1238         }
1239
1240         for_each_rdmaciq(s, i) {
1241                 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1242
1243                 if (msi_idx > 0)
1244                         msi_idx++;
1245                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1246                                        msi_idx, q->fl.size ? &q->fl : NULL,
1247                                        uldrx_handler);
1248                 if (err)
1249                         goto freeout;
1250                 memset(&q->stats, 0, sizeof(q->stats));
1251                 s->rdma_ciq[i] = q->rspq.abs_id;
1252         }
1253
1254         for_each_port(adap, i) {
1255                 /*
1256                  * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1257                  * have RDMA queues, and that's the right value.
1258                  */
1259                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1260                                             s->fw_evtq.cntxt_id,
1261                                             s->rdmarxq[i].rspq.cntxt_id);
1262                 if (err)
1263                         goto freeout;
1264         }
1265
1266         t4_write_reg(adap, is_t4(adap->params.chip) ?
1267                                 MPS_TRC_RSS_CONTROL :
1268                                 MPS_T5_TRC_RSS_CONTROL,
1269                      RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1270                      QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1271         return 0;
1272 }
1273
1274 /*
1275  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1276  * The allocated memory is cleared.
1277  */
1278 void *t4_alloc_mem(size_t size)
1279 {
1280         void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1281
1282         if (!p)
1283                 p = vzalloc(size);
1284         return p;
1285 }
1286
1287 /*
1288  * Free memory allocated through alloc_mem().
1289  */
1290 void t4_free_mem(void *addr)
1291 {
1292         if (is_vmalloc_addr(addr))
1293                 vfree(addr);
1294         else
1295                 kfree(addr);
1296 }
1297
1298 /* Send a Work Request to write the filter at a specified index.  We construct
1299  * a Firmware Filter Work Request to have the work done and put the indicated
1300  * filter into "pending" mode which will prevent any further actions against
1301  * it till we get a reply from the firmware on the completion status of the
1302  * request.
1303  */
1304 static int set_filter_wr(struct adapter *adapter, int fidx)
1305 {
1306         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1307         struct sk_buff *skb;
1308         struct fw_filter_wr *fwr;
1309         unsigned int ftid;
1310
1311         /* If the new filter requires loopback Destination MAC and/or VLAN
1312          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1313          * the filter.
1314          */
1315         if (f->fs.newdmac || f->fs.newvlan) {
1316                 /* allocate L2T entry for new filter */
1317                 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1318                 if (f->l2t == NULL)
1319                         return -EAGAIN;
1320                 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1321                                         f->fs.eport, f->fs.dmac)) {
1322                         cxgb4_l2t_release(f->l2t);
1323                         f->l2t = NULL;
1324                         return -ENOMEM;
1325                 }
1326         }
1327
1328         ftid = adapter->tids.ftid_base + fidx;
1329
1330         skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1331         fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1332         memset(fwr, 0, sizeof(*fwr));
1333
1334         /* It would be nice to put most of the following in t4_hw.c but most
1335          * of the work is translating the cxgbtool ch_filter_specification
1336          * into the Work Request and the definition of that structure is
1337          * currently in cxgbtool.h which isn't appropriate to pull into the
1338          * common code.  We may eventually try to come up with a more neutral
1339          * filter specification structure but for now it's easiest to simply
1340          * put this fairly direct code in line ...
1341          */
1342         fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1343         fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1344         fwr->tid_to_iq =
1345                 htonl(V_FW_FILTER_WR_TID(ftid) |
1346                       V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1347                       V_FW_FILTER_WR_NOREPLY(0) |
1348                       V_FW_FILTER_WR_IQ(f->fs.iq));
1349         fwr->del_filter_to_l2tix =
1350                 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1351                       V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1352                       V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1353                       V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1354                       V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1355                       V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1356                       V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1357                       V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1358                       V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1359                                              f->fs.newvlan == VLAN_REWRITE) |
1360                       V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1361                                             f->fs.newvlan == VLAN_REWRITE) |
1362                       V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1363                       V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1364                       V_FW_FILTER_WR_PRIO(f->fs.prio) |
1365                       V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1366         fwr->ethtype = htons(f->fs.val.ethtype);
1367         fwr->ethtypem = htons(f->fs.mask.ethtype);
1368         fwr->frag_to_ovlan_vldm =
1369                 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1370                  V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1371                  V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1372                  V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1373                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1374                  V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1375         fwr->smac_sel = 0;
1376         fwr->rx_chan_rx_rpl_iq =
1377                 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1378                       V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1379         fwr->maci_to_matchtypem =
1380                 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1381                       V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1382                       V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1383                       V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1384                       V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1385                       V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1386                       V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1387                       V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1388         fwr->ptcl = f->fs.val.proto;
1389         fwr->ptclm = f->fs.mask.proto;
1390         fwr->ttyp = f->fs.val.tos;
1391         fwr->ttypm = f->fs.mask.tos;
1392         fwr->ivlan = htons(f->fs.val.ivlan);
1393         fwr->ivlanm = htons(f->fs.mask.ivlan);
1394         fwr->ovlan = htons(f->fs.val.ovlan);
1395         fwr->ovlanm = htons(f->fs.mask.ovlan);
1396         memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1397         memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1398         memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1399         memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1400         fwr->lp = htons(f->fs.val.lport);
1401         fwr->lpm = htons(f->fs.mask.lport);
1402         fwr->fp = htons(f->fs.val.fport);
1403         fwr->fpm = htons(f->fs.mask.fport);
1404         if (f->fs.newsmac)
1405                 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1406
1407         /* Mark the filter as "pending" and ship off the Filter Work Request.
1408          * When we get the Work Request Reply we'll clear the pending status.
1409          */
1410         f->pending = 1;
1411         set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1412         t4_ofld_send(adapter, skb);
1413         return 0;
1414 }
1415
1416 /* Delete the filter at a specified index.
1417  */
1418 static int del_filter_wr(struct adapter *adapter, int fidx)
1419 {
1420         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1421         struct sk_buff *skb;
1422         struct fw_filter_wr *fwr;
1423         unsigned int len, ftid;
1424
1425         len = sizeof(*fwr);
1426         ftid = adapter->tids.ftid_base + fidx;
1427
1428         skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1429         fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1430         t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1431
1432         /* Mark the filter as "pending" and ship off the Filter Work Request.
1433          * When we get the Work Request Reply we'll clear the pending status.
1434          */
1435         f->pending = 1;
1436         t4_mgmt_tx(adapter, skb);
1437         return 0;
1438 }
1439
1440 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1441                              void *accel_priv, select_queue_fallback_t fallback)
1442 {
1443         int txq;
1444
1445 #ifdef CONFIG_CHELSIO_T4_DCB
1446         /* If a Data Center Bridging has been successfully negotiated on this
1447          * link then we'll use the skb's priority to map it to a TX Queue.
1448          * The skb's priority is determined via the VLAN Tag Priority Code
1449          * Point field.
1450          */
1451         if (cxgb4_dcb_enabled(dev)) {
1452                 u16 vlan_tci;
1453                 int err;
1454
1455                 err = vlan_get_tag(skb, &vlan_tci);
1456                 if (unlikely(err)) {
1457                         if (net_ratelimit())
1458                                 netdev_warn(dev,
1459                                             "TX Packet without VLAN Tag on DCB Link\n");
1460                         txq = 0;
1461                 } else {
1462                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1463                 }
1464                 return txq;
1465         }
1466 #endif /* CONFIG_CHELSIO_T4_DCB */
1467
1468         if (select_queue) {
1469                 txq = (skb_rx_queue_recorded(skb)
1470                         ? skb_get_rx_queue(skb)
1471                         : smp_processor_id());
1472
1473                 while (unlikely(txq >= dev->real_num_tx_queues))
1474                         txq -= dev->real_num_tx_queues;
1475
1476                 return txq;
1477         }
1478
1479         return fallback(dev, skb) % dev->real_num_tx_queues;
1480 }
1481
1482 static inline int is_offload(const struct adapter *adap)
1483 {
1484         return adap->params.offload;
1485 }
1486
1487 /*
1488  * Implementation of ethtool operations.
1489  */
1490
1491 static u32 get_msglevel(struct net_device *dev)
1492 {
1493         return netdev2adap(dev)->msg_enable;
1494 }
1495
1496 static void set_msglevel(struct net_device *dev, u32 val)
1497 {
1498         netdev2adap(dev)->msg_enable = val;
1499 }
1500
1501 static char stats_strings[][ETH_GSTRING_LEN] = {
1502         "TxOctetsOK         ",
1503         "TxFramesOK         ",
1504         "TxBroadcastFrames  ",
1505         "TxMulticastFrames  ",
1506         "TxUnicastFrames    ",
1507         "TxErrorFrames      ",
1508
1509         "TxFrames64         ",
1510         "TxFrames65To127    ",
1511         "TxFrames128To255   ",
1512         "TxFrames256To511   ",
1513         "TxFrames512To1023  ",
1514         "TxFrames1024To1518 ",
1515         "TxFrames1519ToMax  ",
1516
1517         "TxFramesDropped    ",
1518         "TxPauseFrames      ",
1519         "TxPPP0Frames       ",
1520         "TxPPP1Frames       ",
1521         "TxPPP2Frames       ",
1522         "TxPPP3Frames       ",
1523         "TxPPP4Frames       ",
1524         "TxPPP5Frames       ",
1525         "TxPPP6Frames       ",
1526         "TxPPP7Frames       ",
1527
1528         "RxOctetsOK         ",
1529         "RxFramesOK         ",
1530         "RxBroadcastFrames  ",
1531         "RxMulticastFrames  ",
1532         "RxUnicastFrames    ",
1533
1534         "RxFramesTooLong    ",
1535         "RxJabberErrors     ",
1536         "RxFCSErrors        ",
1537         "RxLengthErrors     ",
1538         "RxSymbolErrors     ",
1539         "RxRuntFrames       ",
1540
1541         "RxFrames64         ",
1542         "RxFrames65To127    ",
1543         "RxFrames128To255   ",
1544         "RxFrames256To511   ",
1545         "RxFrames512To1023  ",
1546         "RxFrames1024To1518 ",
1547         "RxFrames1519ToMax  ",
1548
1549         "RxPauseFrames      ",
1550         "RxPPP0Frames       ",
1551         "RxPPP1Frames       ",
1552         "RxPPP2Frames       ",
1553         "RxPPP3Frames       ",
1554         "RxPPP4Frames       ",
1555         "RxPPP5Frames       ",
1556         "RxPPP6Frames       ",
1557         "RxPPP7Frames       ",
1558
1559         "RxBG0FramesDropped ",
1560         "RxBG1FramesDropped ",
1561         "RxBG2FramesDropped ",
1562         "RxBG3FramesDropped ",
1563         "RxBG0FramesTrunc   ",
1564         "RxBG1FramesTrunc   ",
1565         "RxBG2FramesTrunc   ",
1566         "RxBG3FramesTrunc   ",
1567
1568         "TSO                ",
1569         "TxCsumOffload      ",
1570         "RxCsumGood         ",
1571         "VLANextractions    ",
1572         "VLANinsertions     ",
1573         "GROpackets         ",
1574         "GROmerged          ",
1575         "WriteCoalSuccess   ",
1576         "WriteCoalFail      ",
1577 };
1578
1579 static int get_sset_count(struct net_device *dev, int sset)
1580 {
1581         switch (sset) {
1582         case ETH_SS_STATS:
1583                 return ARRAY_SIZE(stats_strings);
1584         default:
1585                 return -EOPNOTSUPP;
1586         }
1587 }
1588
1589 #define T4_REGMAP_SIZE (160 * 1024)
1590 #define T5_REGMAP_SIZE (332 * 1024)
1591
1592 static int get_regs_len(struct net_device *dev)
1593 {
1594         struct adapter *adap = netdev2adap(dev);
1595         if (is_t4(adap->params.chip))
1596                 return T4_REGMAP_SIZE;
1597         else
1598                 return T5_REGMAP_SIZE;
1599 }
1600
1601 static int get_eeprom_len(struct net_device *dev)
1602 {
1603         return EEPROMSIZE;
1604 }
1605
1606 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1607 {
1608         struct adapter *adapter = netdev2adap(dev);
1609
1610         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1611         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1612         strlcpy(info->bus_info, pci_name(adapter->pdev),
1613                 sizeof(info->bus_info));
1614
1615         if (adapter->params.fw_vers)
1616                 snprintf(info->fw_version, sizeof(info->fw_version),
1617                         "%u.%u.%u.%u, TP %u.%u.%u.%u",
1618                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1619                         FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1620                         FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1621                         FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1622                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1623                         FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1624                         FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1625                         FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1626 }
1627
1628 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1629 {
1630         if (stringset == ETH_SS_STATS)
1631                 memcpy(data, stats_strings, sizeof(stats_strings));
1632 }
1633
1634 /*
1635  * port stats maintained per queue of the port.  They should be in the same
1636  * order as in stats_strings above.
1637  */
1638 struct queue_port_stats {
1639         u64 tso;
1640         u64 tx_csum;
1641         u64 rx_csum;
1642         u64 vlan_ex;
1643         u64 vlan_ins;
1644         u64 gro_pkts;
1645         u64 gro_merged;
1646 };
1647
1648 static void collect_sge_port_stats(const struct adapter *adap,
1649                 const struct port_info *p, struct queue_port_stats *s)
1650 {
1651         int i;
1652         const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1653         const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1654
1655         memset(s, 0, sizeof(*s));
1656         for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1657                 s->tso += tx->tso;
1658                 s->tx_csum += tx->tx_cso;
1659                 s->rx_csum += rx->stats.rx_cso;
1660                 s->vlan_ex += rx->stats.vlan_ex;
1661                 s->vlan_ins += tx->vlan_ins;
1662                 s->gro_pkts += rx->stats.lro_pkts;
1663                 s->gro_merged += rx->stats.lro_merged;
1664         }
1665 }
1666
1667 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1668                       u64 *data)
1669 {
1670         struct port_info *pi = netdev_priv(dev);
1671         struct adapter *adapter = pi->adapter;
1672         u32 val1, val2;
1673
1674         t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1675
1676         data += sizeof(struct port_stats) / sizeof(u64);
1677         collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1678         data += sizeof(struct queue_port_stats) / sizeof(u64);
1679         if (!is_t4(adapter->params.chip)) {
1680                 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1681                 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1682                 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1683                 *data = val1 - val2;
1684                 data++;
1685                 *data = val2;
1686                 data++;
1687         } else {
1688                 memset(data, 0, 2 * sizeof(u64));
1689                 *data += 2;
1690         }
1691 }
1692
1693 /*
1694  * Return a version number to identify the type of adapter.  The scheme is:
1695  * - bits 0..9: chip version
1696  * - bits 10..15: chip revision
1697  * - bits 16..23: register dump version
1698  */
1699 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1700 {
1701         return CHELSIO_CHIP_VERSION(ap->params.chip) |
1702                 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1703 }
1704
1705 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1706                            unsigned int end)
1707 {
1708         u32 *p = buf + start;
1709
1710         for ( ; start <= end; start += sizeof(u32))
1711                 *p++ = t4_read_reg(ap, start);
1712 }
1713
1714 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1715                      void *buf)
1716 {
1717         static const unsigned int t4_reg_ranges[] = {
1718                 0x1008, 0x1108,
1719                 0x1180, 0x11b4,
1720                 0x11fc, 0x123c,
1721                 0x1300, 0x173c,
1722                 0x1800, 0x18fc,
1723                 0x3000, 0x30d8,
1724                 0x30e0, 0x5924,
1725                 0x5960, 0x59d4,
1726                 0x5a00, 0x5af8,
1727                 0x6000, 0x6098,
1728                 0x6100, 0x6150,
1729                 0x6200, 0x6208,
1730                 0x6240, 0x6248,
1731                 0x6280, 0x6338,
1732                 0x6370, 0x638c,
1733                 0x6400, 0x643c,
1734                 0x6500, 0x6524,
1735                 0x6a00, 0x6a38,
1736                 0x6a60, 0x6a78,
1737                 0x6b00, 0x6b84,
1738                 0x6bf0, 0x6c84,
1739                 0x6cf0, 0x6d84,
1740                 0x6df0, 0x6e84,
1741                 0x6ef0, 0x6f84,
1742                 0x6ff0, 0x7084,
1743                 0x70f0, 0x7184,
1744                 0x71f0, 0x7284,
1745                 0x72f0, 0x7384,
1746                 0x73f0, 0x7450,
1747                 0x7500, 0x7530,
1748                 0x7600, 0x761c,
1749                 0x7680, 0x76cc,
1750                 0x7700, 0x7798,
1751                 0x77c0, 0x77fc,
1752                 0x7900, 0x79fc,
1753                 0x7b00, 0x7c38,
1754                 0x7d00, 0x7efc,
1755                 0x8dc0, 0x8e1c,
1756                 0x8e30, 0x8e78,
1757                 0x8ea0, 0x8f6c,
1758                 0x8fc0, 0x9074,
1759                 0x90fc, 0x90fc,
1760                 0x9400, 0x9458,
1761                 0x9600, 0x96bc,
1762                 0x9800, 0x9808,
1763                 0x9820, 0x983c,
1764                 0x9850, 0x9864,
1765                 0x9c00, 0x9c6c,
1766                 0x9c80, 0x9cec,
1767                 0x9d00, 0x9d6c,
1768                 0x9d80, 0x9dec,
1769                 0x9e00, 0x9e6c,
1770                 0x9e80, 0x9eec,
1771                 0x9f00, 0x9f6c,
1772                 0x9f80, 0x9fec,
1773                 0xd004, 0xd03c,
1774                 0xdfc0, 0xdfe0,
1775                 0xe000, 0xea7c,
1776                 0xf000, 0x11110,
1777                 0x11118, 0x11190,
1778                 0x19040, 0x1906c,
1779                 0x19078, 0x19080,
1780                 0x1908c, 0x19124,
1781                 0x19150, 0x191b0,
1782                 0x191d0, 0x191e8,
1783                 0x19238, 0x1924c,
1784                 0x193f8, 0x19474,
1785                 0x19490, 0x194f8,
1786                 0x19800, 0x19f30,
1787                 0x1a000, 0x1a06c,
1788                 0x1a0b0, 0x1a120,
1789                 0x1a128, 0x1a138,
1790                 0x1a190, 0x1a1c4,
1791                 0x1a1fc, 0x1a1fc,
1792                 0x1e040, 0x1e04c,
1793                 0x1e284, 0x1e28c,
1794                 0x1e2c0, 0x1e2c0,
1795                 0x1e2e0, 0x1e2e0,
1796                 0x1e300, 0x1e384,
1797                 0x1e3c0, 0x1e3c8,
1798                 0x1e440, 0x1e44c,
1799                 0x1e684, 0x1e68c,
1800                 0x1e6c0, 0x1e6c0,
1801                 0x1e6e0, 0x1e6e0,
1802                 0x1e700, 0x1e784,
1803                 0x1e7c0, 0x1e7c8,
1804                 0x1e840, 0x1e84c,
1805                 0x1ea84, 0x1ea8c,
1806                 0x1eac0, 0x1eac0,
1807                 0x1eae0, 0x1eae0,
1808                 0x1eb00, 0x1eb84,
1809                 0x1ebc0, 0x1ebc8,
1810                 0x1ec40, 0x1ec4c,
1811                 0x1ee84, 0x1ee8c,
1812                 0x1eec0, 0x1eec0,
1813                 0x1eee0, 0x1eee0,
1814                 0x1ef00, 0x1ef84,
1815                 0x1efc0, 0x1efc8,
1816                 0x1f040, 0x1f04c,
1817                 0x1f284, 0x1f28c,
1818                 0x1f2c0, 0x1f2c0,
1819                 0x1f2e0, 0x1f2e0,
1820                 0x1f300, 0x1f384,
1821                 0x1f3c0, 0x1f3c8,
1822                 0x1f440, 0x1f44c,
1823                 0x1f684, 0x1f68c,
1824                 0x1f6c0, 0x1f6c0,
1825                 0x1f6e0, 0x1f6e0,
1826                 0x1f700, 0x1f784,
1827                 0x1f7c0, 0x1f7c8,
1828                 0x1f840, 0x1f84c,
1829                 0x1fa84, 0x1fa8c,
1830                 0x1fac0, 0x1fac0,
1831                 0x1fae0, 0x1fae0,
1832                 0x1fb00, 0x1fb84,
1833                 0x1fbc0, 0x1fbc8,
1834                 0x1fc40, 0x1fc4c,
1835                 0x1fe84, 0x1fe8c,
1836                 0x1fec0, 0x1fec0,
1837                 0x1fee0, 0x1fee0,
1838                 0x1ff00, 0x1ff84,
1839                 0x1ffc0, 0x1ffc8,
1840                 0x20000, 0x2002c,
1841                 0x20100, 0x2013c,
1842                 0x20190, 0x201c8,
1843                 0x20200, 0x20318,
1844                 0x20400, 0x20528,
1845                 0x20540, 0x20614,
1846                 0x21000, 0x21040,
1847                 0x2104c, 0x21060,
1848                 0x210c0, 0x210ec,
1849                 0x21200, 0x21268,
1850                 0x21270, 0x21284,
1851                 0x212fc, 0x21388,
1852                 0x21400, 0x21404,
1853                 0x21500, 0x21518,
1854                 0x2152c, 0x2153c,
1855                 0x21550, 0x21554,
1856                 0x21600, 0x21600,
1857                 0x21608, 0x21628,
1858                 0x21630, 0x2163c,
1859                 0x21700, 0x2171c,
1860                 0x21780, 0x2178c,
1861                 0x21800, 0x21c38,
1862                 0x21c80, 0x21d7c,
1863                 0x21e00, 0x21e04,
1864                 0x22000, 0x2202c,
1865                 0x22100, 0x2213c,
1866                 0x22190, 0x221c8,
1867                 0x22200, 0x22318,
1868                 0x22400, 0x22528,
1869                 0x22540, 0x22614,
1870                 0x23000, 0x23040,
1871                 0x2304c, 0x23060,
1872                 0x230c0, 0x230ec,
1873                 0x23200, 0x23268,
1874                 0x23270, 0x23284,
1875                 0x232fc, 0x23388,
1876                 0x23400, 0x23404,
1877                 0x23500, 0x23518,
1878                 0x2352c, 0x2353c,
1879                 0x23550, 0x23554,
1880                 0x23600, 0x23600,
1881                 0x23608, 0x23628,
1882                 0x23630, 0x2363c,
1883                 0x23700, 0x2371c,
1884                 0x23780, 0x2378c,
1885                 0x23800, 0x23c38,
1886                 0x23c80, 0x23d7c,
1887                 0x23e00, 0x23e04,
1888                 0x24000, 0x2402c,
1889                 0x24100, 0x2413c,
1890                 0x24190, 0x241c8,
1891                 0x24200, 0x24318,
1892                 0x24400, 0x24528,
1893                 0x24540, 0x24614,
1894                 0x25000, 0x25040,
1895                 0x2504c, 0x25060,
1896                 0x250c0, 0x250ec,
1897                 0x25200, 0x25268,
1898                 0x25270, 0x25284,
1899                 0x252fc, 0x25388,
1900                 0x25400, 0x25404,
1901                 0x25500, 0x25518,
1902                 0x2552c, 0x2553c,
1903                 0x25550, 0x25554,
1904                 0x25600, 0x25600,
1905                 0x25608, 0x25628,
1906                 0x25630, 0x2563c,
1907                 0x25700, 0x2571c,
1908                 0x25780, 0x2578c,
1909                 0x25800, 0x25c38,
1910                 0x25c80, 0x25d7c,
1911                 0x25e00, 0x25e04,
1912                 0x26000, 0x2602c,
1913                 0x26100, 0x2613c,
1914                 0x26190, 0x261c8,
1915                 0x26200, 0x26318,
1916                 0x26400, 0x26528,
1917                 0x26540, 0x26614,
1918                 0x27000, 0x27040,
1919                 0x2704c, 0x27060,
1920                 0x270c0, 0x270ec,
1921                 0x27200, 0x27268,
1922                 0x27270, 0x27284,
1923                 0x272fc, 0x27388,
1924                 0x27400, 0x27404,
1925                 0x27500, 0x27518,
1926                 0x2752c, 0x2753c,
1927                 0x27550, 0x27554,
1928                 0x27600, 0x27600,
1929                 0x27608, 0x27628,
1930                 0x27630, 0x2763c,
1931                 0x27700, 0x2771c,
1932                 0x27780, 0x2778c,
1933                 0x27800, 0x27c38,
1934                 0x27c80, 0x27d7c,
1935                 0x27e00, 0x27e04
1936         };
1937
1938         static const unsigned int t5_reg_ranges[] = {
1939                 0x1008, 0x1148,
1940                 0x1180, 0x11b4,
1941                 0x11fc, 0x123c,
1942                 0x1280, 0x173c,
1943                 0x1800, 0x18fc,
1944                 0x3000, 0x3028,
1945                 0x3060, 0x30d8,
1946                 0x30e0, 0x30fc,
1947                 0x3140, 0x357c,
1948                 0x35a8, 0x35cc,
1949                 0x35ec, 0x35ec,
1950                 0x3600, 0x5624,
1951                 0x56cc, 0x575c,
1952                 0x580c, 0x5814,
1953                 0x5890, 0x58bc,
1954                 0x5940, 0x59dc,
1955                 0x59fc, 0x5a18,
1956                 0x5a60, 0x5a9c,
1957                 0x5b9c, 0x5bfc,
1958                 0x6000, 0x6040,
1959                 0x6058, 0x614c,
1960                 0x7700, 0x7798,
1961                 0x77c0, 0x78fc,
1962                 0x7b00, 0x7c54,
1963                 0x7d00, 0x7efc,
1964                 0x8dc0, 0x8de0,
1965                 0x8df8, 0x8e84,
1966                 0x8ea0, 0x8f84,
1967                 0x8fc0, 0x90f8,
1968                 0x9400, 0x9470,
1969                 0x9600, 0x96f4,
1970                 0x9800, 0x9808,
1971                 0x9820, 0x983c,
1972                 0x9850, 0x9864,
1973                 0x9c00, 0x9c6c,
1974                 0x9c80, 0x9cec,
1975                 0x9d00, 0x9d6c,
1976                 0x9d80, 0x9dec,
1977                 0x9e00, 0x9e6c,
1978                 0x9e80, 0x9eec,
1979                 0x9f00, 0x9f6c,
1980                 0x9f80, 0xa020,
1981                 0xd004, 0xd03c,
1982                 0xdfc0, 0xdfe0,
1983                 0xe000, 0x11088,
1984                 0x1109c, 0x11110,
1985                 0x11118, 0x1117c,
1986                 0x11190, 0x11204,
1987                 0x19040, 0x1906c,
1988                 0x19078, 0x19080,
1989                 0x1908c, 0x19124,
1990                 0x19150, 0x191b0,
1991                 0x191d0, 0x191e8,
1992                 0x19238, 0x19290,
1993                 0x193f8, 0x19474,
1994                 0x19490, 0x194cc,
1995                 0x194f0, 0x194f8,
1996                 0x19c00, 0x19c60,
1997                 0x19c94, 0x19e10,
1998                 0x19e50, 0x19f34,
1999                 0x19f40, 0x19f50,
2000                 0x19f90, 0x19fe4,
2001                 0x1a000, 0x1a06c,
2002                 0x1a0b0, 0x1a120,
2003                 0x1a128, 0x1a138,
2004                 0x1a190, 0x1a1c4,
2005                 0x1a1fc, 0x1a1fc,
2006                 0x1e008, 0x1e00c,
2007                 0x1e040, 0x1e04c,
2008                 0x1e284, 0x1e290,
2009                 0x1e2c0, 0x1e2c0,
2010                 0x1e2e0, 0x1e2e0,
2011                 0x1e300, 0x1e384,
2012                 0x1e3c0, 0x1e3c8,
2013                 0x1e408, 0x1e40c,
2014                 0x1e440, 0x1e44c,
2015                 0x1e684, 0x1e690,
2016                 0x1e6c0, 0x1e6c0,
2017                 0x1e6e0, 0x1e6e0,
2018                 0x1e700, 0x1e784,
2019                 0x1e7c0, 0x1e7c8,
2020                 0x1e808, 0x1e80c,
2021                 0x1e840, 0x1e84c,
2022                 0x1ea84, 0x1ea90,
2023                 0x1eac0, 0x1eac0,
2024                 0x1eae0, 0x1eae0,
2025                 0x1eb00, 0x1eb84,
2026                 0x1ebc0, 0x1ebc8,
2027                 0x1ec08, 0x1ec0c,
2028                 0x1ec40, 0x1ec4c,
2029                 0x1ee84, 0x1ee90,
2030                 0x1eec0, 0x1eec0,
2031                 0x1eee0, 0x1eee0,
2032                 0x1ef00, 0x1ef84,
2033                 0x1efc0, 0x1efc8,
2034                 0x1f008, 0x1f00c,
2035                 0x1f040, 0x1f04c,
2036                 0x1f284, 0x1f290,
2037                 0x1f2c0, 0x1f2c0,
2038                 0x1f2e0, 0x1f2e0,
2039                 0x1f300, 0x1f384,
2040                 0x1f3c0, 0x1f3c8,
2041                 0x1f408, 0x1f40c,
2042                 0x1f440, 0x1f44c,
2043                 0x1f684, 0x1f690,
2044                 0x1f6c0, 0x1f6c0,
2045                 0x1f6e0, 0x1f6e0,
2046                 0x1f700, 0x1f784,
2047                 0x1f7c0, 0x1f7c8,
2048                 0x1f808, 0x1f80c,
2049                 0x1f840, 0x1f84c,
2050                 0x1fa84, 0x1fa90,
2051                 0x1fac0, 0x1fac0,
2052                 0x1fae0, 0x1fae0,
2053                 0x1fb00, 0x1fb84,
2054                 0x1fbc0, 0x1fbc8,
2055                 0x1fc08, 0x1fc0c,
2056                 0x1fc40, 0x1fc4c,
2057                 0x1fe84, 0x1fe90,
2058                 0x1fec0, 0x1fec0,
2059                 0x1fee0, 0x1fee0,
2060                 0x1ff00, 0x1ff84,
2061                 0x1ffc0, 0x1ffc8,
2062                 0x30000, 0x30030,
2063                 0x30100, 0x30144,
2064                 0x30190, 0x301d0,
2065                 0x30200, 0x30318,
2066                 0x30400, 0x3052c,
2067                 0x30540, 0x3061c,
2068                 0x30800, 0x30834,
2069                 0x308c0, 0x30908,
2070                 0x30910, 0x309ac,
2071                 0x30a00, 0x30a04,
2072                 0x30a0c, 0x30a2c,
2073                 0x30a44, 0x30a50,
2074                 0x30a74, 0x30c24,
2075                 0x30d08, 0x30d14,
2076                 0x30d1c, 0x30d20,
2077                 0x30d3c, 0x30d50,
2078                 0x31200, 0x3120c,
2079                 0x31220, 0x31220,
2080                 0x31240, 0x31240,
2081                 0x31600, 0x31600,
2082                 0x31608, 0x3160c,
2083                 0x31a00, 0x31a1c,
2084                 0x31e04, 0x31e20,
2085                 0x31e38, 0x31e3c,
2086                 0x31e80, 0x31e80,
2087                 0x31e88, 0x31ea8,
2088                 0x31eb0, 0x31eb4,
2089                 0x31ec8, 0x31ed4,
2090                 0x31fb8, 0x32004,
2091                 0x32208, 0x3223c,
2092                 0x32600, 0x32630,
2093                 0x32a00, 0x32abc,
2094                 0x32b00, 0x32b70,
2095                 0x33000, 0x33048,
2096                 0x33060, 0x3309c,
2097                 0x330f0, 0x33148,
2098                 0x33160, 0x3319c,
2099                 0x331f0, 0x332e4,
2100                 0x332f8, 0x333e4,
2101                 0x333f8, 0x33448,
2102                 0x33460, 0x3349c,
2103                 0x334f0, 0x33548,
2104                 0x33560, 0x3359c,
2105                 0x335f0, 0x336e4,
2106                 0x336f8, 0x337e4,
2107                 0x337f8, 0x337fc,
2108                 0x33814, 0x33814,
2109                 0x3382c, 0x3382c,
2110                 0x33880, 0x3388c,
2111                 0x338e8, 0x338ec,
2112                 0x33900, 0x33948,
2113                 0x33960, 0x3399c,
2114                 0x339f0, 0x33ae4,
2115                 0x33af8, 0x33b10,
2116                 0x33b28, 0x33b28,
2117                 0x33b3c, 0x33b50,
2118                 0x33bf0, 0x33c10,
2119                 0x33c28, 0x33c28,
2120                 0x33c3c, 0x33c50,
2121                 0x33cf0, 0x33cfc,
2122                 0x34000, 0x34030,
2123                 0x34100, 0x34144,
2124                 0x34190, 0x341d0,
2125                 0x34200, 0x34318,
2126                 0x34400, 0x3452c,
2127                 0x34540, 0x3461c,
2128                 0x34800, 0x34834,
2129                 0x348c0, 0x34908,
2130                 0x34910, 0x349ac,
2131                 0x34a00, 0x34a04,
2132                 0x34a0c, 0x34a2c,
2133                 0x34a44, 0x34a50,
2134                 0x34a74, 0x34c24,
2135                 0x34d08, 0x34d14,
2136                 0x34d1c, 0x34d20,
2137                 0x34d3c, 0x34d50,
2138                 0x35200, 0x3520c,
2139                 0x35220, 0x35220,
2140                 0x35240, 0x35240,
2141                 0x35600, 0x35600,
2142                 0x35608, 0x3560c,
2143                 0x35a00, 0x35a1c,
2144                 0x35e04, 0x35e20,
2145                 0x35e38, 0x35e3c,
2146                 0x35e80, 0x35e80,
2147                 0x35e88, 0x35ea8,
2148                 0x35eb0, 0x35eb4,
2149                 0x35ec8, 0x35ed4,
2150                 0x35fb8, 0x36004,
2151                 0x36208, 0x3623c,
2152                 0x36600, 0x36630,
2153                 0x36a00, 0x36abc,
2154                 0x36b00, 0x36b70,
2155                 0x37000, 0x37048,
2156                 0x37060, 0x3709c,
2157                 0x370f0, 0x37148,
2158                 0x37160, 0x3719c,
2159                 0x371f0, 0x372e4,
2160                 0x372f8, 0x373e4,
2161                 0x373f8, 0x37448,
2162                 0x37460, 0x3749c,
2163                 0x374f0, 0x37548,
2164                 0x37560, 0x3759c,
2165                 0x375f0, 0x376e4,
2166                 0x376f8, 0x377e4,
2167                 0x377f8, 0x377fc,
2168                 0x37814, 0x37814,
2169                 0x3782c, 0x3782c,
2170                 0x37880, 0x3788c,
2171                 0x378e8, 0x378ec,
2172                 0x37900, 0x37948,
2173                 0x37960, 0x3799c,
2174                 0x379f0, 0x37ae4,
2175                 0x37af8, 0x37b10,
2176                 0x37b28, 0x37b28,
2177                 0x37b3c, 0x37b50,
2178                 0x37bf0, 0x37c10,
2179                 0x37c28, 0x37c28,
2180                 0x37c3c, 0x37c50,
2181                 0x37cf0, 0x37cfc,
2182                 0x38000, 0x38030,
2183                 0x38100, 0x38144,
2184                 0x38190, 0x381d0,
2185                 0x38200, 0x38318,
2186                 0x38400, 0x3852c,
2187                 0x38540, 0x3861c,
2188                 0x38800, 0x38834,
2189                 0x388c0, 0x38908,
2190                 0x38910, 0x389ac,
2191                 0x38a00, 0x38a04,
2192                 0x38a0c, 0x38a2c,
2193                 0x38a44, 0x38a50,
2194                 0x38a74, 0x38c24,
2195                 0x38d08, 0x38d14,
2196                 0x38d1c, 0x38d20,
2197                 0x38d3c, 0x38d50,
2198                 0x39200, 0x3920c,
2199                 0x39220, 0x39220,
2200                 0x39240, 0x39240,
2201                 0x39600, 0x39600,
2202                 0x39608, 0x3960c,
2203                 0x39a00, 0x39a1c,
2204                 0x39e04, 0x39e20,
2205                 0x39e38, 0x39e3c,
2206                 0x39e80, 0x39e80,
2207                 0x39e88, 0x39ea8,
2208                 0x39eb0, 0x39eb4,
2209                 0x39ec8, 0x39ed4,
2210                 0x39fb8, 0x3a004,
2211                 0x3a208, 0x3a23c,
2212                 0x3a600, 0x3a630,
2213                 0x3aa00, 0x3aabc,
2214                 0x3ab00, 0x3ab70,
2215                 0x3b000, 0x3b048,
2216                 0x3b060, 0x3b09c,
2217                 0x3b0f0, 0x3b148,
2218                 0x3b160, 0x3b19c,
2219                 0x3b1f0, 0x3b2e4,
2220                 0x3b2f8, 0x3b3e4,
2221                 0x3b3f8, 0x3b448,
2222                 0x3b460, 0x3b49c,
2223                 0x3b4f0, 0x3b548,
2224                 0x3b560, 0x3b59c,
2225                 0x3b5f0, 0x3b6e4,
2226                 0x3b6f8, 0x3b7e4,
2227                 0x3b7f8, 0x3b7fc,
2228                 0x3b814, 0x3b814,
2229                 0x3b82c, 0x3b82c,
2230                 0x3b880, 0x3b88c,
2231                 0x3b8e8, 0x3b8ec,
2232                 0x3b900, 0x3b948,
2233                 0x3b960, 0x3b99c,
2234                 0x3b9f0, 0x3bae4,
2235                 0x3baf8, 0x3bb10,
2236                 0x3bb28, 0x3bb28,
2237                 0x3bb3c, 0x3bb50,
2238                 0x3bbf0, 0x3bc10,
2239                 0x3bc28, 0x3bc28,
2240                 0x3bc3c, 0x3bc50,
2241                 0x3bcf0, 0x3bcfc,
2242                 0x3c000, 0x3c030,
2243                 0x3c100, 0x3c144,
2244                 0x3c190, 0x3c1d0,
2245                 0x3c200, 0x3c318,
2246                 0x3c400, 0x3c52c,
2247                 0x3c540, 0x3c61c,
2248                 0x3c800, 0x3c834,
2249                 0x3c8c0, 0x3c908,
2250                 0x3c910, 0x3c9ac,
2251                 0x3ca00, 0x3ca04,
2252                 0x3ca0c, 0x3ca2c,
2253                 0x3ca44, 0x3ca50,
2254                 0x3ca74, 0x3cc24,
2255                 0x3cd08, 0x3cd14,
2256                 0x3cd1c, 0x3cd20,
2257                 0x3cd3c, 0x3cd50,
2258                 0x3d200, 0x3d20c,
2259                 0x3d220, 0x3d220,
2260                 0x3d240, 0x3d240,
2261                 0x3d600, 0x3d600,
2262                 0x3d608, 0x3d60c,
2263                 0x3da00, 0x3da1c,
2264                 0x3de04, 0x3de20,
2265                 0x3de38, 0x3de3c,
2266                 0x3de80, 0x3de80,
2267                 0x3de88, 0x3dea8,
2268                 0x3deb0, 0x3deb4,
2269                 0x3dec8, 0x3ded4,
2270                 0x3dfb8, 0x3e004,
2271                 0x3e208, 0x3e23c,
2272                 0x3e600, 0x3e630,
2273                 0x3ea00, 0x3eabc,
2274                 0x3eb00, 0x3eb70,
2275                 0x3f000, 0x3f048,
2276                 0x3f060, 0x3f09c,
2277                 0x3f0f0, 0x3f148,
2278                 0x3f160, 0x3f19c,
2279                 0x3f1f0, 0x3f2e4,
2280                 0x3f2f8, 0x3f3e4,
2281                 0x3f3f8, 0x3f448,
2282                 0x3f460, 0x3f49c,
2283                 0x3f4f0, 0x3f548,
2284                 0x3f560, 0x3f59c,
2285                 0x3f5f0, 0x3f6e4,
2286                 0x3f6f8, 0x3f7e4,
2287                 0x3f7f8, 0x3f7fc,
2288                 0x3f814, 0x3f814,
2289                 0x3f82c, 0x3f82c,
2290                 0x3f880, 0x3f88c,
2291                 0x3f8e8, 0x3f8ec,
2292                 0x3f900, 0x3f948,
2293                 0x3f960, 0x3f99c,
2294                 0x3f9f0, 0x3fae4,
2295                 0x3faf8, 0x3fb10,
2296                 0x3fb28, 0x3fb28,
2297                 0x3fb3c, 0x3fb50,
2298                 0x3fbf0, 0x3fc10,
2299                 0x3fc28, 0x3fc28,
2300                 0x3fc3c, 0x3fc50,
2301                 0x3fcf0, 0x3fcfc,
2302                 0x40000, 0x4000c,
2303                 0x40040, 0x40068,
2304                 0x40080, 0x40144,
2305                 0x40180, 0x4018c,
2306                 0x40200, 0x40298,
2307                 0x402ac, 0x4033c,
2308                 0x403f8, 0x403fc,
2309                 0x41304, 0x413c4,
2310                 0x41400, 0x4141c,
2311                 0x41480, 0x414d0,
2312                 0x44000, 0x44078,
2313                 0x440c0, 0x44278,
2314                 0x442c0, 0x44478,
2315                 0x444c0, 0x44678,
2316                 0x446c0, 0x44878,
2317                 0x448c0, 0x449fc,
2318                 0x45000, 0x45068,
2319                 0x45080, 0x45084,
2320                 0x450a0, 0x450b0,
2321                 0x45200, 0x45268,
2322                 0x45280, 0x45284,
2323                 0x452a0, 0x452b0,
2324                 0x460c0, 0x460e4,
2325                 0x47000, 0x4708c,
2326                 0x47200, 0x47250,
2327                 0x47400, 0x47420,
2328                 0x47600, 0x47618,
2329                 0x47800, 0x47814,
2330                 0x48000, 0x4800c,
2331                 0x48040, 0x48068,
2332                 0x48080, 0x48144,
2333                 0x48180, 0x4818c,
2334                 0x48200, 0x48298,
2335                 0x482ac, 0x4833c,
2336                 0x483f8, 0x483fc,
2337                 0x49304, 0x493c4,
2338                 0x49400, 0x4941c,
2339                 0x49480, 0x494d0,
2340                 0x4c000, 0x4c078,
2341                 0x4c0c0, 0x4c278,
2342                 0x4c2c0, 0x4c478,
2343                 0x4c4c0, 0x4c678,
2344                 0x4c6c0, 0x4c878,
2345                 0x4c8c0, 0x4c9fc,
2346                 0x4d000, 0x4d068,
2347                 0x4d080, 0x4d084,
2348                 0x4d0a0, 0x4d0b0,
2349                 0x4d200, 0x4d268,
2350                 0x4d280, 0x4d284,
2351                 0x4d2a0, 0x4d2b0,
2352                 0x4e0c0, 0x4e0e4,
2353                 0x4f000, 0x4f08c,
2354                 0x4f200, 0x4f250,
2355                 0x4f400, 0x4f420,
2356                 0x4f600, 0x4f618,
2357                 0x4f800, 0x4f814,
2358                 0x50000, 0x500cc,
2359                 0x50400, 0x50400,
2360                 0x50800, 0x508cc,
2361                 0x50c00, 0x50c00,
2362                 0x51000, 0x5101c,
2363                 0x51300, 0x51308,
2364         };
2365
2366         int i;
2367         struct adapter *ap = netdev2adap(dev);
2368         static const unsigned int *reg_ranges;
2369         int arr_size = 0, buf_size = 0;
2370
2371         if (is_t4(ap->params.chip)) {
2372                 reg_ranges = &t4_reg_ranges[0];
2373                 arr_size = ARRAY_SIZE(t4_reg_ranges);
2374                 buf_size = T4_REGMAP_SIZE;
2375         } else {
2376                 reg_ranges = &t5_reg_ranges[0];
2377                 arr_size = ARRAY_SIZE(t5_reg_ranges);
2378                 buf_size = T5_REGMAP_SIZE;
2379         }
2380
2381         regs->version = mk_adap_vers(ap);
2382
2383         memset(buf, 0, buf_size);
2384         for (i = 0; i < arr_size; i += 2)
2385                 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2386 }
2387
2388 static int restart_autoneg(struct net_device *dev)
2389 {
2390         struct port_info *p = netdev_priv(dev);
2391
2392         if (!netif_running(dev))
2393                 return -EAGAIN;
2394         if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2395                 return -EINVAL;
2396         t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2397         return 0;
2398 }
2399
2400 static int identify_port(struct net_device *dev,
2401                          enum ethtool_phys_id_state state)
2402 {
2403         unsigned int val;
2404         struct adapter *adap = netdev2adap(dev);
2405
2406         if (state == ETHTOOL_ID_ACTIVE)
2407                 val = 0xffff;
2408         else if (state == ETHTOOL_ID_INACTIVE)
2409                 val = 0;
2410         else
2411                 return -EINVAL;
2412
2413         return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2414 }
2415
2416 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2417 {
2418         unsigned int v = 0;
2419
2420         if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2421             type == FW_PORT_TYPE_BT_XAUI) {
2422                 v |= SUPPORTED_TP;
2423                 if (caps & FW_PORT_CAP_SPEED_100M)
2424                         v |= SUPPORTED_100baseT_Full;
2425                 if (caps & FW_PORT_CAP_SPEED_1G)
2426                         v |= SUPPORTED_1000baseT_Full;
2427                 if (caps & FW_PORT_CAP_SPEED_10G)
2428                         v |= SUPPORTED_10000baseT_Full;
2429         } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2430                 v |= SUPPORTED_Backplane;
2431                 if (caps & FW_PORT_CAP_SPEED_1G)
2432                         v |= SUPPORTED_1000baseKX_Full;
2433                 if (caps & FW_PORT_CAP_SPEED_10G)
2434                         v |= SUPPORTED_10000baseKX4_Full;
2435         } else if (type == FW_PORT_TYPE_KR)
2436                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2437         else if (type == FW_PORT_TYPE_BP_AP)
2438                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2439                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2440         else if (type == FW_PORT_TYPE_BP4_AP)
2441                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2442                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2443                      SUPPORTED_10000baseKX4_Full;
2444         else if (type == FW_PORT_TYPE_FIBER_XFI ||
2445                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2446                 v |= SUPPORTED_FIBRE;
2447         else if (type == FW_PORT_TYPE_BP40_BA)
2448                 v |= SUPPORTED_40000baseSR4_Full;
2449
2450         if (caps & FW_PORT_CAP_ANEG)
2451                 v |= SUPPORTED_Autoneg;
2452         return v;
2453 }
2454
2455 static unsigned int to_fw_linkcaps(unsigned int caps)
2456 {
2457         unsigned int v = 0;
2458
2459         if (caps & ADVERTISED_100baseT_Full)
2460                 v |= FW_PORT_CAP_SPEED_100M;
2461         if (caps & ADVERTISED_1000baseT_Full)
2462                 v |= FW_PORT_CAP_SPEED_1G;
2463         if (caps & ADVERTISED_10000baseT_Full)
2464                 v |= FW_PORT_CAP_SPEED_10G;
2465         if (caps & ADVERTISED_40000baseSR4_Full)
2466                 v |= FW_PORT_CAP_SPEED_40G;
2467         return v;
2468 }
2469
2470 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2471 {
2472         const struct port_info *p = netdev_priv(dev);
2473
2474         if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2475             p->port_type == FW_PORT_TYPE_BT_XFI ||
2476             p->port_type == FW_PORT_TYPE_BT_XAUI)
2477                 cmd->port = PORT_TP;
2478         else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2479                  p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2480                 cmd->port = PORT_FIBRE;
2481         else if (p->port_type == FW_PORT_TYPE_SFP ||
2482                  p->port_type == FW_PORT_TYPE_QSFP_10G ||
2483                  p->port_type == FW_PORT_TYPE_QSFP) {
2484                 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2485                     p->mod_type == FW_PORT_MOD_TYPE_SR ||
2486                     p->mod_type == FW_PORT_MOD_TYPE_ER ||
2487                     p->mod_type == FW_PORT_MOD_TYPE_LRM)
2488                         cmd->port = PORT_FIBRE;
2489                 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2490                          p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2491                         cmd->port = PORT_DA;
2492                 else
2493                         cmd->port = PORT_OTHER;
2494         } else
2495                 cmd->port = PORT_OTHER;
2496
2497         if (p->mdio_addr >= 0) {
2498                 cmd->phy_address = p->mdio_addr;
2499                 cmd->transceiver = XCVR_EXTERNAL;
2500                 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2501                         MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2502         } else {
2503                 cmd->phy_address = 0;  /* not really, but no better option */
2504                 cmd->transceiver = XCVR_INTERNAL;
2505                 cmd->mdio_support = 0;
2506         }
2507
2508         cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2509         cmd->advertising = from_fw_linkcaps(p->port_type,
2510                                             p->link_cfg.advertising);
2511         ethtool_cmd_speed_set(cmd,
2512                               netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2513         cmd->duplex = DUPLEX_FULL;
2514         cmd->autoneg = p->link_cfg.autoneg;
2515         cmd->maxtxpkt = 0;
2516         cmd->maxrxpkt = 0;
2517         return 0;
2518 }
2519
2520 static unsigned int speed_to_caps(int speed)
2521 {
2522         if (speed == 100)
2523                 return FW_PORT_CAP_SPEED_100M;
2524         if (speed == 1000)
2525                 return FW_PORT_CAP_SPEED_1G;
2526         if (speed == 10000)
2527                 return FW_PORT_CAP_SPEED_10G;
2528         if (speed == 40000)
2529                 return FW_PORT_CAP_SPEED_40G;
2530         return 0;
2531 }
2532
2533 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2534 {
2535         unsigned int cap;
2536         struct port_info *p = netdev_priv(dev);
2537         struct link_config *lc = &p->link_cfg;
2538         u32 speed = ethtool_cmd_speed(cmd);
2539
2540         if (cmd->duplex != DUPLEX_FULL)     /* only full-duplex supported */
2541                 return -EINVAL;
2542
2543         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2544                 /*
2545                  * PHY offers a single speed.  See if that's what's
2546                  * being requested.
2547                  */
2548                 if (cmd->autoneg == AUTONEG_DISABLE &&
2549                     (lc->supported & speed_to_caps(speed)))
2550                         return 0;
2551                 return -EINVAL;
2552         }
2553
2554         if (cmd->autoneg == AUTONEG_DISABLE) {
2555                 cap = speed_to_caps(speed);
2556
2557                 if (!(lc->supported & cap) ||
2558                     (speed == 1000) ||
2559                     (speed == 10000) ||
2560                     (speed == 40000))
2561                         return -EINVAL;
2562                 lc->requested_speed = cap;
2563                 lc->advertising = 0;
2564         } else {
2565                 cap = to_fw_linkcaps(cmd->advertising);
2566                 if (!(lc->supported & cap))
2567                         return -EINVAL;
2568                 lc->requested_speed = 0;
2569                 lc->advertising = cap | FW_PORT_CAP_ANEG;
2570         }
2571         lc->autoneg = cmd->autoneg;
2572
2573         if (netif_running(dev))
2574                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2575                                      lc);
2576         return 0;
2577 }
2578
2579 static void get_pauseparam(struct net_device *dev,
2580                            struct ethtool_pauseparam *epause)
2581 {
2582         struct port_info *p = netdev_priv(dev);
2583
2584         epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2585         epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2586         epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2587 }
2588
2589 static int set_pauseparam(struct net_device *dev,
2590                           struct ethtool_pauseparam *epause)
2591 {
2592         struct port_info *p = netdev_priv(dev);
2593         struct link_config *lc = &p->link_cfg;
2594
2595         if (epause->autoneg == AUTONEG_DISABLE)
2596                 lc->requested_fc = 0;
2597         else if (lc->supported & FW_PORT_CAP_ANEG)
2598                 lc->requested_fc = PAUSE_AUTONEG;
2599         else
2600                 return -EINVAL;
2601
2602         if (epause->rx_pause)
2603                 lc->requested_fc |= PAUSE_RX;
2604         if (epause->tx_pause)
2605                 lc->requested_fc |= PAUSE_TX;
2606         if (netif_running(dev))
2607                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2608                                      lc);
2609         return 0;
2610 }
2611
2612 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2613 {
2614         const struct port_info *pi = netdev_priv(dev);
2615         const struct sge *s = &pi->adapter->sge;
2616
2617         e->rx_max_pending = MAX_RX_BUFFERS;
2618         e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2619         e->rx_jumbo_max_pending = 0;
2620         e->tx_max_pending = MAX_TXQ_ENTRIES;
2621
2622         e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2623         e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2624         e->rx_jumbo_pending = 0;
2625         e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2626 }
2627
2628 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2629 {
2630         int i;
2631         const struct port_info *pi = netdev_priv(dev);
2632         struct adapter *adapter = pi->adapter;
2633         struct sge *s = &adapter->sge;
2634
2635         if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2636             e->tx_pending > MAX_TXQ_ENTRIES ||
2637             e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2638             e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2639             e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2640                 return -EINVAL;
2641
2642         if (adapter->flags & FULL_INIT_DONE)
2643                 return -EBUSY;
2644
2645         for (i = 0; i < pi->nqsets; ++i) {
2646                 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2647                 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2648                 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2649         }
2650         return 0;
2651 }
2652
2653 static int closest_timer(const struct sge *s, int time)
2654 {
2655         int i, delta, match = 0, min_delta = INT_MAX;
2656
2657         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2658                 delta = time - s->timer_val[i];
2659                 if (delta < 0)
2660                         delta = -delta;
2661                 if (delta < min_delta) {
2662                         min_delta = delta;
2663                         match = i;
2664                 }
2665         }
2666         return match;
2667 }
2668
2669 static int closest_thres(const struct sge *s, int thres)
2670 {
2671         int i, delta, match = 0, min_delta = INT_MAX;
2672
2673         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2674                 delta = thres - s->counter_val[i];
2675                 if (delta < 0)
2676                         delta = -delta;
2677                 if (delta < min_delta) {
2678                         min_delta = delta;
2679                         match = i;
2680                 }
2681         }
2682         return match;
2683 }
2684
2685 /*
2686  * Return a queue's interrupt hold-off time in us.  0 means no timer.
2687  */
2688 static unsigned int qtimer_val(const struct adapter *adap,
2689                                const struct sge_rspq *q)
2690 {
2691         unsigned int idx = q->intr_params >> 1;
2692
2693         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2694 }
2695
2696 /**
2697  *      set_rspq_intr_params - set a queue's interrupt holdoff parameters
2698  *      @q: the Rx queue
2699  *      @us: the hold-off time in us, or 0 to disable timer
2700  *      @cnt: the hold-off packet count, or 0 to disable counter
2701  *
2702  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
2703  *      one of the two needs to be enabled for the queue to generate interrupts.
2704  */
2705 static int set_rspq_intr_params(struct sge_rspq *q,
2706                                 unsigned int us, unsigned int cnt)
2707 {
2708         struct adapter *adap = q->adap;
2709
2710         if ((us | cnt) == 0)
2711                 cnt = 1;
2712
2713         if (cnt) {
2714                 int err;
2715                 u32 v, new_idx;
2716
2717                 new_idx = closest_thres(&adap->sge, cnt);
2718                 if (q->desc && q->pktcnt_idx != new_idx) {
2719                         /* the queue has already been created, update it */
2720                         v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2721                             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2722                             FW_PARAMS_PARAM_YZ(q->cntxt_id);
2723                         err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2724                                             &new_idx);
2725                         if (err)
2726                                 return err;
2727                 }
2728                 q->pktcnt_idx = new_idx;
2729         }
2730
2731         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2732         q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2733         return 0;
2734 }
2735
2736 /**
2737  * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2738  * @dev: the network device
2739  * @us: the hold-off time in us, or 0 to disable timer
2740  * @cnt: the hold-off packet count, or 0 to disable counter
2741  *
2742  * Set the RX interrupt hold-off parameters for a network device.
2743  */
2744 static int set_rx_intr_params(struct net_device *dev,
2745                               unsigned int us, unsigned int cnt)
2746 {
2747         int i, err;
2748         struct port_info *pi = netdev_priv(dev);
2749         struct adapter *adap = pi->adapter;
2750         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2751
2752         for (i = 0; i < pi->nqsets; i++, q++) {
2753                 err = set_rspq_intr_params(&q->rspq, us, cnt);
2754                 if (err)
2755                         return err;
2756         }
2757         return 0;
2758 }
2759
2760 static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
2761 {
2762         int i;
2763         struct port_info *pi = netdev_priv(dev);
2764         struct adapter *adap = pi->adapter;
2765         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2766
2767         for (i = 0; i < pi->nqsets; i++, q++)
2768                 q->rspq.adaptive_rx = adaptive_rx;
2769
2770         return 0;
2771 }
2772
2773 static int get_adaptive_rx_setting(struct net_device *dev)
2774 {
2775         struct port_info *pi = netdev_priv(dev);
2776         struct adapter *adap = pi->adapter;
2777         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2778
2779         return q->rspq.adaptive_rx;
2780 }
2781
2782 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2783 {
2784         set_adaptive_rx_setting(dev, c->use_adaptive_rx_coalesce);
2785         return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2786                                   c->rx_max_coalesced_frames);
2787 }
2788
2789 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2790 {
2791         const struct port_info *pi = netdev_priv(dev);
2792         const struct adapter *adap = pi->adapter;
2793         const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2794
2795         c->rx_coalesce_usecs = qtimer_val(adap, rq);
2796         c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2797                 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2798         c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
2799         return 0;
2800 }
2801
2802 /**
2803  *      eeprom_ptov - translate a physical EEPROM address to virtual
2804  *      @phys_addr: the physical EEPROM address
2805  *      @fn: the PCI function number
2806  *      @sz: size of function-specific area
2807  *
2808  *      Translate a physical EEPROM address to virtual.  The first 1K is
2809  *      accessed through virtual addresses starting at 31K, the rest is
2810  *      accessed through virtual addresses starting at 0.
2811  *
2812  *      The mapping is as follows:
2813  *      [0..1K) -> [31K..32K)
2814  *      [1K..1K+A) -> [31K-A..31K)
2815  *      [1K+A..ES) -> [0..ES-A-1K)
2816  *
2817  *      where A = @fn * @sz, and ES = EEPROM size.
2818  */
2819 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2820 {
2821         fn *= sz;
2822         if (phys_addr < 1024)
2823                 return phys_addr + (31 << 10);
2824         if (phys_addr < 1024 + fn)
2825                 return 31744 - fn + phys_addr - 1024;
2826         if (phys_addr < EEPROMSIZE)
2827                 return phys_addr - 1024 - fn;
2828         return -EINVAL;
2829 }
2830
2831 /*
2832  * The next two routines implement eeprom read/write from physical addresses.
2833  */
2834 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2835 {
2836         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2837
2838         if (vaddr >= 0)
2839                 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2840         return vaddr < 0 ? vaddr : 0;
2841 }
2842
2843 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2844 {
2845         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2846
2847         if (vaddr >= 0)
2848                 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2849         return vaddr < 0 ? vaddr : 0;
2850 }
2851
2852 #define EEPROM_MAGIC 0x38E2F10C
2853
2854 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2855                       u8 *data)
2856 {
2857         int i, err = 0;
2858         struct adapter *adapter = netdev2adap(dev);
2859
2860         u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2861         if (!buf)
2862                 return -ENOMEM;
2863
2864         e->magic = EEPROM_MAGIC;
2865         for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2866                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2867
2868         if (!err)
2869                 memcpy(data, buf + e->offset, e->len);
2870         kfree(buf);
2871         return err;
2872 }
2873
2874 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2875                       u8 *data)
2876 {
2877         u8 *buf;
2878         int err = 0;
2879         u32 aligned_offset, aligned_len, *p;
2880         struct adapter *adapter = netdev2adap(dev);
2881
2882         if (eeprom->magic != EEPROM_MAGIC)
2883                 return -EINVAL;
2884
2885         aligned_offset = eeprom->offset & ~3;
2886         aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2887
2888         if (adapter->fn > 0) {
2889                 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2890
2891                 if (aligned_offset < start ||
2892                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
2893                         return -EPERM;
2894         }
2895
2896         if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2897                 /*
2898                  * RMW possibly needed for first or last words.
2899                  */
2900                 buf = kmalloc(aligned_len, GFP_KERNEL);
2901                 if (!buf)
2902                         return -ENOMEM;
2903                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2904                 if (!err && aligned_len > 4)
2905                         err = eeprom_rd_phys(adapter,
2906                                              aligned_offset + aligned_len - 4,
2907                                              (u32 *)&buf[aligned_len - 4]);
2908                 if (err)
2909                         goto out;
2910                 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2911         } else
2912                 buf = data;
2913
2914         err = t4_seeprom_wp(adapter, false);
2915         if (err)
2916                 goto out;
2917
2918         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2919                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2920                 aligned_offset += 4;
2921         }
2922
2923         if (!err)
2924                 err = t4_seeprom_wp(adapter, true);
2925 out:
2926         if (buf != data)
2927                 kfree(buf);
2928         return err;
2929 }
2930
2931 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2932 {
2933         int ret;
2934         const struct firmware *fw;
2935         struct adapter *adap = netdev2adap(netdev);
2936         unsigned int mbox = FW_PCIE_FW_MASTER_MASK + 1;
2937
2938         ef->data[sizeof(ef->data) - 1] = '\0';
2939         ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2940         if (ret < 0)
2941                 return ret;
2942
2943         /* If the adapter has been fully initialized then we'll go ahead and
2944          * try to get the firmware's cooperation in upgrading to the new
2945          * firmware image otherwise we'll try to do the entire job from the
2946          * host ... and we always "force" the operation in this path.
2947          */
2948         if (adap->flags & FULL_INIT_DONE)
2949                 mbox = adap->mbox;
2950
2951         ret = t4_fw_upgrade(adap, mbox, fw->data, fw->size, 1);
2952         release_firmware(fw);
2953         if (!ret)
2954                 dev_info(adap->pdev_dev, "loaded firmware %s,"
2955                          " reload cxgb4 driver\n", ef->data);
2956         return ret;
2957 }
2958
2959 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2960 #define BCAST_CRC 0xa0ccc1a6
2961
2962 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2963 {
2964         wol->supported = WAKE_BCAST | WAKE_MAGIC;
2965         wol->wolopts = netdev2adap(dev)->wol;
2966         memset(&wol->sopass, 0, sizeof(wol->sopass));
2967 }
2968
2969 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2970 {
2971         int err = 0;
2972         struct port_info *pi = netdev_priv(dev);
2973
2974         if (wol->wolopts & ~WOL_SUPPORTED)
2975                 return -EINVAL;
2976         t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2977                             (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2978         if (wol->wolopts & WAKE_BCAST) {
2979                 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2980                                         ~0ULL, 0, false);
2981                 if (!err)
2982                         err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2983                                                 ~6ULL, ~0ULL, BCAST_CRC, true);
2984         } else
2985                 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2986         return err;
2987 }
2988
2989 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2990 {
2991         const struct port_info *pi = netdev_priv(dev);
2992         netdev_features_t changed = dev->features ^ features;
2993         int err;
2994
2995         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2996                 return 0;
2997
2998         err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2999                             -1, -1, -1,
3000                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
3001         if (unlikely(err))
3002                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
3003         return err;
3004 }
3005
3006 static u32 get_rss_table_size(struct net_device *dev)
3007 {
3008         const struct port_info *pi = netdev_priv(dev);
3009
3010         return pi->rss_size;
3011 }
3012
3013 static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
3014 {
3015         const struct port_info *pi = netdev_priv(dev);
3016         unsigned int n = pi->rss_size;
3017
3018         while (n--)
3019                 p[n] = pi->rss[n];
3020         return 0;
3021 }
3022
3023 static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
3024 {
3025         unsigned int i;
3026         struct port_info *pi = netdev_priv(dev);
3027
3028         for (i = 0; i < pi->rss_size; i++)
3029                 pi->rss[i] = p[i];
3030         if (pi->adapter->flags & FULL_INIT_DONE)
3031                 return write_rss(pi, pi->rss);
3032         return 0;
3033 }
3034
3035 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3036                      u32 *rules)
3037 {
3038         const struct port_info *pi = netdev_priv(dev);
3039
3040         switch (info->cmd) {
3041         case ETHTOOL_GRXFH: {
3042                 unsigned int v = pi->rss_mode;
3043
3044                 info->data = 0;
3045                 switch (info->flow_type) {
3046                 case TCP_V4_FLOW:
3047                         if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3048                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3049                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3050                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3051                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3052                         break;
3053                 case UDP_V4_FLOW:
3054                         if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
3055                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3056                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3057                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3058                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3059                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3060                         break;
3061                 case SCTP_V4_FLOW:
3062                 case AH_ESP_V4_FLOW:
3063                 case IPV4_FLOW:
3064                         if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3065                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3066                         break;
3067                 case TCP_V6_FLOW:
3068                         if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3069                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3070                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3071                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3072                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3073                         break;
3074                 case UDP_V6_FLOW:
3075                         if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
3076                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3077                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3078                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3079                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3080                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3081                         break;
3082                 case SCTP_V6_FLOW:
3083                 case AH_ESP_V6_FLOW:
3084                 case IPV6_FLOW:
3085                         if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3086                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3087                         break;
3088                 }
3089                 return 0;
3090         }
3091         case ETHTOOL_GRXRINGS:
3092                 info->data = pi->nqsets;
3093                 return 0;
3094         }
3095         return -EOPNOTSUPP;
3096 }
3097
3098 static const struct ethtool_ops cxgb_ethtool_ops = {
3099         .get_settings      = get_settings,
3100         .set_settings      = set_settings,
3101         .get_drvinfo       = get_drvinfo,
3102         .get_msglevel      = get_msglevel,
3103         .set_msglevel      = set_msglevel,
3104         .get_ringparam     = get_sge_param,
3105         .set_ringparam     = set_sge_param,
3106         .get_coalesce      = get_coalesce,
3107         .set_coalesce      = set_coalesce,
3108         .get_eeprom_len    = get_eeprom_len,
3109         .get_eeprom        = get_eeprom,
3110         .set_eeprom        = set_eeprom,
3111         .get_pauseparam    = get_pauseparam,
3112         .set_pauseparam    = set_pauseparam,
3113         .get_link          = ethtool_op_get_link,
3114         .get_strings       = get_strings,
3115         .set_phys_id       = identify_port,
3116         .nway_reset        = restart_autoneg,
3117         .get_sset_count    = get_sset_count,
3118         .get_ethtool_stats = get_stats,
3119         .get_regs_len      = get_regs_len,
3120         .get_regs          = get_regs,
3121         .get_wol           = get_wol,
3122         .set_wol           = set_wol,
3123         .get_rxnfc         = get_rxnfc,
3124         .get_rxfh_indir_size = get_rss_table_size,
3125         .get_rxfh          = get_rss_table,
3126         .set_rxfh          = set_rss_table,
3127         .flash_device      = set_flash,
3128 };
3129
3130 static int setup_debugfs(struct adapter *adap)
3131 {
3132         if (IS_ERR_OR_NULL(adap->debugfs_root))
3133                 return -1;
3134
3135 #ifdef CONFIG_DEBUG_FS
3136         t4_setup_debugfs(adap);
3137 #endif
3138         return 0;
3139 }
3140
3141 /*
3142  * upper-layer driver support
3143  */
3144
3145 /*
3146  * Allocate an active-open TID and set it to the supplied value.
3147  */
3148 int cxgb4_alloc_atid(struct tid_info *t, void *data)
3149 {
3150         int atid = -1;
3151
3152         spin_lock_bh(&t->atid_lock);
3153         if (t->afree) {
3154                 union aopen_entry *p = t->afree;
3155
3156                 atid = (p - t->atid_tab) + t->atid_base;
3157                 t->afree = p->next;
3158                 p->data = data;
3159                 t->atids_in_use++;
3160         }
3161         spin_unlock_bh(&t->atid_lock);
3162         return atid;
3163 }
3164 EXPORT_SYMBOL(cxgb4_alloc_atid);
3165
3166 /*
3167  * Release an active-open TID.
3168  */
3169 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3170 {
3171         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
3172
3173         spin_lock_bh(&t->atid_lock);
3174         p->next = t->afree;
3175         t->afree = p;
3176         t->atids_in_use--;
3177         spin_unlock_bh(&t->atid_lock);
3178 }
3179 EXPORT_SYMBOL(cxgb4_free_atid);
3180
3181 /*
3182  * Allocate a server TID and set it to the supplied value.
3183  */
3184 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3185 {
3186         int stid;
3187
3188         spin_lock_bh(&t->stid_lock);
3189         if (family == PF_INET) {
3190                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3191                 if (stid < t->nstids)
3192                         __set_bit(stid, t->stid_bmap);
3193                 else
3194                         stid = -1;
3195         } else {
3196                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3197                 if (stid < 0)
3198                         stid = -1;
3199         }
3200         if (stid >= 0) {
3201                 t->stid_tab[stid].data = data;
3202                 stid += t->stid_base;
3203                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3204                  * This is equivalent to 4 TIDs. With CLIP enabled it
3205                  * needs 2 TIDs.
3206                  */
3207                 if (family == PF_INET)
3208                         t->stids_in_use++;
3209                 else
3210                         t->stids_in_use += 4;
3211         }
3212         spin_unlock_bh(&t->stid_lock);
3213         return stid;
3214 }
3215 EXPORT_SYMBOL(cxgb4_alloc_stid);
3216
3217 /* Allocate a server filter TID and set it to the supplied value.
3218  */
3219 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3220 {
3221         int stid;
3222
3223         spin_lock_bh(&t->stid_lock);
3224         if (family == PF_INET) {
3225                 stid = find_next_zero_bit(t->stid_bmap,
3226                                 t->nstids + t->nsftids, t->nstids);
3227                 if (stid < (t->nstids + t->nsftids))
3228                         __set_bit(stid, t->stid_bmap);
3229                 else
3230                         stid = -1;
3231         } else {
3232                 stid = -1;
3233         }
3234         if (stid >= 0) {
3235                 t->stid_tab[stid].data = data;
3236                 stid -= t->nstids;
3237                 stid += t->sftid_base;
3238                 t->stids_in_use++;
3239         }
3240         spin_unlock_bh(&t->stid_lock);
3241         return stid;
3242 }
3243 EXPORT_SYMBOL(cxgb4_alloc_sftid);
3244
3245 /* Release a server TID.
3246  */
3247 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3248 {
3249         /* Is it a server filter TID? */
3250         if (t->nsftids && (stid >= t->sftid_base)) {
3251                 stid -= t->sftid_base;
3252                 stid += t->nstids;
3253         } else {
3254                 stid -= t->stid_base;
3255         }
3256
3257         spin_lock_bh(&t->stid_lock);
3258         if (family == PF_INET)
3259                 __clear_bit(stid, t->stid_bmap);
3260         else
3261                 bitmap_release_region(t->stid_bmap, stid, 2);
3262         t->stid_tab[stid].data = NULL;
3263         if (family == PF_INET)
3264                 t->stids_in_use--;
3265         else
3266                 t->stids_in_use -= 4;
3267         spin_unlock_bh(&t->stid_lock);
3268 }
3269 EXPORT_SYMBOL(cxgb4_free_stid);
3270
3271 /*
3272  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
3273  */
3274 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3275                            unsigned int tid)
3276 {
3277         struct cpl_tid_release *req;
3278
3279         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3280         req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3281         INIT_TP_WR(req, tid);
3282         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3283 }
3284
3285 /*
3286  * Queue a TID release request and if necessary schedule a work queue to
3287  * process it.
3288  */
3289 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3290                                     unsigned int tid)
3291 {
3292         void **p = &t->tid_tab[tid];
3293         struct adapter *adap = container_of(t, struct adapter, tids);
3294
3295         spin_lock_bh(&adap->tid_release_lock);
3296         *p = adap->tid_release_head;
3297         /* Low 2 bits encode the Tx channel number */
3298         adap->tid_release_head = (void **)((uintptr_t)p | chan);
3299         if (!adap->tid_release_task_busy) {
3300                 adap->tid_release_task_busy = true;
3301                 queue_work(adap->workq, &adap->tid_release_task);
3302         }
3303         spin_unlock_bh(&adap->tid_release_lock);
3304 }
3305
3306 /*
3307  * Process the list of pending TID release requests.
3308  */
3309 static void process_tid_release_list(struct work_struct *work)
3310 {
3311         struct sk_buff *skb;
3312         struct adapter *adap;
3313
3314         adap = container_of(work, struct adapter, tid_release_task);
3315
3316         spin_lock_bh(&adap->tid_release_lock);
3317         while (adap->tid_release_head) {
3318                 void **p = adap->tid_release_head;
3319                 unsigned int chan = (uintptr_t)p & 3;
3320                 p = (void *)p - chan;
3321
3322                 adap->tid_release_head = *p;
3323                 *p = NULL;
3324                 spin_unlock_bh(&adap->tid_release_lock);
3325
3326                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3327                                          GFP_KERNEL)))
3328                         schedule_timeout_uninterruptible(1);
3329
3330                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3331                 t4_ofld_send(adap, skb);
3332                 spin_lock_bh(&adap->tid_release_lock);
3333         }
3334         adap->tid_release_task_busy = false;
3335         spin_unlock_bh(&adap->tid_release_lock);
3336 }
3337
3338 /*
3339  * Release a TID and inform HW.  If we are unable to allocate the release
3340  * message we defer to a work queue.
3341  */
3342 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3343 {
3344         void *old;
3345         struct sk_buff *skb;
3346         struct adapter *adap = container_of(t, struct adapter, tids);
3347
3348         old = t->tid_tab[tid];
3349         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3350         if (likely(skb)) {
3351                 t->tid_tab[tid] = NULL;
3352                 mk_tid_release(skb, chan, tid);
3353                 t4_ofld_send(adap, skb);
3354         } else
3355                 cxgb4_queue_tid_release(t, chan, tid);
3356         if (old)
3357                 atomic_dec(&t->tids_in_use);
3358 }
3359 EXPORT_SYMBOL(cxgb4_remove_tid);
3360
3361 /*
3362  * Allocate and initialize the TID tables.  Returns 0 on success.
3363  */
3364 static int tid_init(struct tid_info *t)
3365 {
3366         size_t size;
3367         unsigned int stid_bmap_size;
3368         unsigned int natids = t->natids;
3369         struct adapter *adap = container_of(t, struct adapter, tids);
3370
3371         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
3372         size = t->ntids * sizeof(*t->tid_tab) +
3373                natids * sizeof(*t->atid_tab) +
3374                t->nstids * sizeof(*t->stid_tab) +
3375                t->nsftids * sizeof(*t->stid_tab) +
3376                stid_bmap_size * sizeof(long) +
3377                t->nftids * sizeof(*t->ftid_tab) +
3378                t->nsftids * sizeof(*t->ftid_tab);
3379
3380         t->tid_tab = t4_alloc_mem(size);
3381         if (!t->tid_tab)
3382                 return -ENOMEM;
3383
3384         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3385         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
3386         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
3387         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
3388         spin_lock_init(&t->stid_lock);
3389         spin_lock_init(&t->atid_lock);
3390
3391         t->stids_in_use = 0;
3392         t->afree = NULL;
3393         t->atids_in_use = 0;
3394         atomic_set(&t->tids_in_use, 0);
3395
3396         /* Setup the free list for atid_tab and clear the stid bitmap. */
3397         if (natids) {
3398                 while (--natids)
3399                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3400                 t->afree = t->atid_tab;
3401         }
3402         bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
3403         /* Reserve stid 0 for T4/T5 adapters */
3404         if (!t->stid_base &&
3405             (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3406                 __set_bit(0, t->stid_bmap);
3407
3408         return 0;
3409 }
3410
3411 int cxgb4_clip_get(const struct net_device *dev,
3412                    const struct in6_addr *lip)
3413 {
3414         struct adapter *adap;
3415         struct fw_clip_cmd c;
3416
3417         adap = netdev2adap(dev);
3418         memset(&c, 0, sizeof(c));
3419         c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3420                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3421         c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
3422         c.ip_hi = *(__be64 *)(lip->s6_addr);
3423         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3424         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3425 }
3426 EXPORT_SYMBOL(cxgb4_clip_get);
3427
3428 int cxgb4_clip_release(const struct net_device *dev,
3429                        const struct in6_addr *lip)
3430 {
3431         struct adapter *adap;
3432         struct fw_clip_cmd c;
3433
3434         adap = netdev2adap(dev);
3435         memset(&c, 0, sizeof(c));
3436         c.op_to_write = htonl(FW_CMD_OP_V(FW_CLIP_CMD) |
3437                         FW_CMD_REQUEST_F | FW_CMD_READ_F);
3438         c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
3439         c.ip_hi = *(__be64 *)(lip->s6_addr);
3440         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3441         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3442 }
3443 EXPORT_SYMBOL(cxgb4_clip_release);
3444
3445 /**
3446  *      cxgb4_create_server - create an IP server
3447  *      @dev: the device
3448  *      @stid: the server TID
3449  *      @sip: local IP address to bind server to
3450  *      @sport: the server's TCP port
3451  *      @queue: queue to direct messages from this server to
3452  *
3453  *      Create an IP server for the given port and address.
3454  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3455  */
3456 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
3457                         __be32 sip, __be16 sport, __be16 vlan,
3458                         unsigned int queue)
3459 {
3460         unsigned int chan;
3461         struct sk_buff *skb;
3462         struct adapter *adap;
3463         struct cpl_pass_open_req *req;
3464         int ret;
3465
3466         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3467         if (!skb)
3468                 return -ENOMEM;
3469
3470         adap = netdev2adap(dev);
3471         req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3472         INIT_TP_WR(req, 0);
3473         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3474         req->local_port = sport;
3475         req->peer_port = htons(0);
3476         req->local_ip = sip;
3477         req->peer_ip = htonl(0);
3478         chan = rxq_to_chan(&adap->sge, queue);
3479         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3480         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3481                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3482         ret = t4_mgmt_tx(adap, skb);
3483         return net_xmit_eval(ret);
3484 }
3485 EXPORT_SYMBOL(cxgb4_create_server);
3486
3487 /*      cxgb4_create_server6 - create an IPv6 server
3488  *      @dev: the device
3489  *      @stid: the server TID
3490  *      @sip: local IPv6 address to bind server to
3491  *      @sport: the server's TCP port
3492  *      @queue: queue to direct messages from this server to
3493  *
3494  *      Create an IPv6 server for the given port and address.
3495  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3496  */
3497 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3498                          const struct in6_addr *sip, __be16 sport,
3499                          unsigned int queue)
3500 {
3501         unsigned int chan;
3502         struct sk_buff *skb;
3503         struct adapter *adap;
3504         struct cpl_pass_open_req6 *req;
3505         int ret;
3506
3507         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3508         if (!skb)
3509                 return -ENOMEM;
3510
3511         adap = netdev2adap(dev);
3512         req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3513         INIT_TP_WR(req, 0);
3514         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3515         req->local_port = sport;
3516         req->peer_port = htons(0);
3517         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3518         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3519         req->peer_ip_hi = cpu_to_be64(0);
3520         req->peer_ip_lo = cpu_to_be64(0);
3521         chan = rxq_to_chan(&adap->sge, queue);
3522         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
3523         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3524                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3525         ret = t4_mgmt_tx(adap, skb);
3526         return net_xmit_eval(ret);
3527 }
3528 EXPORT_SYMBOL(cxgb4_create_server6);
3529
3530 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3531                         unsigned int queue, bool ipv6)
3532 {
3533         struct sk_buff *skb;
3534         struct adapter *adap;
3535         struct cpl_close_listsvr_req *req;
3536         int ret;
3537
3538         adap = netdev2adap(dev);
3539
3540         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3541         if (!skb)
3542                 return -ENOMEM;
3543
3544         req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3545         INIT_TP_WR(req, 0);
3546         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3547         req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3548                                 LISTSVR_IPV6(0)) | QUEUENO(queue));
3549         ret = t4_mgmt_tx(adap, skb);
3550         return net_xmit_eval(ret);
3551 }
3552 EXPORT_SYMBOL(cxgb4_remove_server);
3553
3554 /**
3555  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3556  *      @mtus: the HW MTU table
3557  *      @mtu: the target MTU
3558  *      @idx: index of selected entry in the MTU table
3559  *
3560  *      Returns the index and the value in the HW MTU table that is closest to
3561  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
3562  *      table, in which case that smallest available value is selected.
3563  */
3564 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3565                             unsigned int *idx)
3566 {
3567         unsigned int i = 0;
3568
3569         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3570                 ++i;
3571         if (idx)
3572                 *idx = i;
3573         return mtus[i];
3574 }
3575 EXPORT_SYMBOL(cxgb4_best_mtu);
3576
3577 /**
3578  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3579  *     @mtus: the HW MTU table
3580  *     @header_size: Header Size
3581  *     @data_size_max: maximum Data Segment Size
3582  *     @data_size_align: desired Data Segment Size Alignment (2^N)
3583  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3584  *
3585  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
3586  *     MTU Table based solely on a Maximum MTU parameter, we break that
3587  *     parameter up into a Header Size and Maximum Data Segment Size, and
3588  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
3589  *     the Hardware MTU Table which will result in a Data Segment Size with
3590  *     the requested alignment _and_ that MTU isn't "too far" from the
3591  *     closest MTU, then we'll return that rather than the closest MTU.
3592  */
3593 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3594                                     unsigned short header_size,
3595                                     unsigned short data_size_max,
3596                                     unsigned short data_size_align,
3597                                     unsigned int *mtu_idxp)
3598 {
3599         unsigned short max_mtu = header_size + data_size_max;
3600         unsigned short data_size_align_mask = data_size_align - 1;
3601         int mtu_idx, aligned_mtu_idx;
3602
3603         /* Scan the MTU Table till we find an MTU which is larger than our
3604          * Maximum MTU or we reach the end of the table.  Along the way,
3605          * record the last MTU found, if any, which will result in a Data
3606          * Segment Length matching the requested alignment.
3607          */
3608         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3609                 unsigned short data_size = mtus[mtu_idx] - header_size;
3610
3611                 /* If this MTU minus the Header Size would result in a
3612                  * Data Segment Size of the desired alignment, remember it.
3613                  */
3614                 if ((data_size & data_size_align_mask) == 0)
3615                         aligned_mtu_idx = mtu_idx;
3616
3617                 /* If we're not at the end of the Hardware MTU Table and the
3618                  * next element is larger than our Maximum MTU, drop out of
3619                  * the loop.
3620                  */
3621                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3622                         break;
3623         }
3624
3625         /* If we fell out of the loop because we ran to the end of the table,
3626          * then we just have to use the last [largest] entry.
3627          */
3628         if (mtu_idx == NMTUS)
3629                 mtu_idx--;
3630
3631         /* If we found an MTU which resulted in the requested Data Segment
3632          * Length alignment and that's "not far" from the largest MTU which is
3633          * less than or equal to the maximum MTU, then use that.
3634          */
3635         if (aligned_mtu_idx >= 0 &&
3636             mtu_idx - aligned_mtu_idx <= 1)
3637                 mtu_idx = aligned_mtu_idx;
3638
3639         /* If the caller has passed in an MTU Index pointer, pass the
3640          * MTU Index back.  Return the MTU value.
3641          */
3642         if (mtu_idxp)
3643                 *mtu_idxp = mtu_idx;
3644         return mtus[mtu_idx];
3645 }
3646 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3647
3648 /**
3649  *      cxgb4_port_chan - get the HW channel of a port
3650  *      @dev: the net device for the port
3651  *
3652  *      Return the HW Tx channel of the given port.
3653  */
3654 unsigned int cxgb4_port_chan(const struct net_device *dev)
3655 {
3656         return netdev2pinfo(dev)->tx_chan;
3657 }
3658 EXPORT_SYMBOL(cxgb4_port_chan);
3659
3660 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3661 {
3662         struct adapter *adap = netdev2adap(dev);
3663         u32 v1, v2, lp_count, hp_count;
3664
3665         v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3666         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3667         if (is_t4(adap->params.chip)) {
3668                 lp_count = G_LP_COUNT(v1);
3669                 hp_count = G_HP_COUNT(v1);
3670         } else {
3671                 lp_count = G_LP_COUNT_T5(v1);
3672                 hp_count = G_HP_COUNT_T5(v2);
3673         }
3674         return lpfifo ? lp_count : hp_count;
3675 }
3676 EXPORT_SYMBOL(cxgb4_dbfifo_count);
3677
3678 /**
3679  *      cxgb4_port_viid - get the VI id of a port
3680  *      @dev: the net device for the port
3681  *
3682  *      Return the VI id of the given port.
3683  */
3684 unsigned int cxgb4_port_viid(const struct net_device *dev)
3685 {
3686         return netdev2pinfo(dev)->viid;
3687 }
3688 EXPORT_SYMBOL(cxgb4_port_viid);
3689
3690 /**
3691  *      cxgb4_port_idx - get the index of a port
3692  *      @dev: the net device for the port
3693  *
3694  *      Return the index of the given port.
3695  */
3696 unsigned int cxgb4_port_idx(const struct net_device *dev)
3697 {
3698         return netdev2pinfo(dev)->port_id;
3699 }
3700 EXPORT_SYMBOL(cxgb4_port_idx);
3701
3702 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3703                          struct tp_tcp_stats *v6)
3704 {
3705         struct adapter *adap = pci_get_drvdata(pdev);
3706
3707         spin_lock(&adap->stats_lock);
3708         t4_tp_get_tcp_stats(adap, v4, v6);
3709         spin_unlock(&adap->stats_lock);
3710 }
3711 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3712
3713 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3714                       const unsigned int *pgsz_order)
3715 {
3716         struct adapter *adap = netdev2adap(dev);
3717
3718         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3719         t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3720                      HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3721                      HPZ3(pgsz_order[3]));
3722 }
3723 EXPORT_SYMBOL(cxgb4_iscsi_init);
3724
3725 int cxgb4_flush_eq_cache(struct net_device *dev)
3726 {
3727         struct adapter *adap = netdev2adap(dev);
3728         int ret;
3729
3730         ret = t4_fwaddrspace_write(adap, adap->mbox,
3731                                    0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3732         return ret;
3733 }
3734 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3735
3736 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3737 {
3738         u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3739         __be64 indices;
3740         int ret;
3741
3742         spin_lock(&adap->win0_lock);
3743         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
3744                            sizeof(indices), (__be32 *)&indices,
3745                            T4_MEMORY_READ);
3746         spin_unlock(&adap->win0_lock);
3747         if (!ret) {
3748                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3749                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3750         }
3751         return ret;
3752 }
3753
3754 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3755                         u16 size)
3756 {
3757         struct adapter *adap = netdev2adap(dev);
3758         u16 hw_pidx, hw_cidx;
3759         int ret;
3760
3761         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3762         if (ret)
3763                 goto out;
3764
3765         if (pidx != hw_pidx) {
3766                 u16 delta;
3767
3768                 if (pidx >= hw_pidx)
3769                         delta = pidx - hw_pidx;
3770                 else
3771                         delta = size - hw_pidx + pidx;
3772                 wmb();
3773                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3774                              QID(qid) | PIDX(delta));
3775         }
3776 out:
3777         return ret;
3778 }
3779 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3780
3781 void cxgb4_disable_db_coalescing(struct net_device *dev)
3782 {
3783         struct adapter *adap;
3784
3785         adap = netdev2adap(dev);
3786         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3787                          F_NOCOALESCE);
3788 }
3789 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3790
3791 void cxgb4_enable_db_coalescing(struct net_device *dev)
3792 {
3793         struct adapter *adap;
3794
3795         adap = netdev2adap(dev);
3796         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3797 }
3798 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3799
3800 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
3801 {
3802         struct adapter *adap;
3803         u32 offset, memtype, memaddr;
3804         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
3805         u32 edc0_end, edc1_end, mc0_end, mc1_end;
3806         int ret;
3807
3808         adap = netdev2adap(dev);
3809
3810         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
3811
3812         /* Figure out where the offset lands in the Memory Type/Address scheme.
3813          * This code assumes that the memory is laid out starting at offset 0
3814          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3815          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
3816          * MC0, and some have both MC0 and MC1.
3817          */
3818         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
3819         edc0_size = EDRAM0_SIZE_G(size) << 20;
3820         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
3821         edc1_size = EDRAM1_SIZE_G(size) << 20;
3822         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
3823         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
3824
3825         edc0_end = edc0_size;
3826         edc1_end = edc0_end + edc1_size;
3827         mc0_end = edc1_end + mc0_size;
3828
3829         if (offset < edc0_end) {
3830                 memtype = MEM_EDC0;
3831                 memaddr = offset;
3832         } else if (offset < edc1_end) {
3833                 memtype = MEM_EDC1;
3834                 memaddr = offset - edc0_end;
3835         } else {
3836                 if (offset < mc0_end) {
3837                         memtype = MEM_MC0;
3838                         memaddr = offset - edc1_end;
3839                 } else if (is_t4(adap->params.chip)) {
3840                         /* T4 only has a single memory channel */
3841                         goto err;
3842                 } else {
3843                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
3844                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
3845                         mc1_end = mc0_end + mc1_size;
3846                         if (offset < mc1_end) {
3847                                 memtype = MEM_MC1;
3848                                 memaddr = offset - mc0_end;
3849                         } else {
3850                                 /* offset beyond the end of any memory */
3851                                 goto err;
3852                         }
3853                 }
3854         }
3855
3856         spin_lock(&adap->win0_lock);
3857         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
3858         spin_unlock(&adap->win0_lock);
3859         return ret;
3860
3861 err:
3862         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
3863                 stag, offset);
3864         return -EINVAL;
3865 }
3866 EXPORT_SYMBOL(cxgb4_read_tpte);
3867
3868 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
3869 {
3870         u32 hi, lo;
3871         struct adapter *adap;
3872
3873         adap = netdev2adap(dev);
3874         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
3875         hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
3876
3877         return ((u64)hi << 32) | (u64)lo;
3878 }
3879 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
3880
3881 static struct pci_driver cxgb4_driver;
3882
3883 static void check_neigh_update(struct neighbour *neigh)
3884 {
3885         const struct device *parent;
3886         const struct net_device *netdev = neigh->dev;
3887
3888         if (netdev->priv_flags & IFF_802_1Q_VLAN)
3889                 netdev = vlan_dev_real_dev(netdev);
3890         parent = netdev->dev.parent;
3891         if (parent && parent->driver == &cxgb4_driver.driver)
3892                 t4_l2t_update(dev_get_drvdata(parent), neigh);
3893 }
3894
3895 static int netevent_cb(struct notifier_block *nb, unsigned long event,
3896                        void *data)
3897 {
3898         switch (event) {
3899         case NETEVENT_NEIGH_UPDATE:
3900                 check_neigh_update(data);
3901                 break;
3902         case NETEVENT_REDIRECT:
3903         default:
3904                 break;
3905         }
3906         return 0;
3907 }
3908
3909 static bool netevent_registered;
3910 static struct notifier_block cxgb4_netevent_nb = {
3911         .notifier_call = netevent_cb
3912 };
3913
3914 static void drain_db_fifo(struct adapter *adap, int usecs)
3915 {
3916         u32 v1, v2, lp_count, hp_count;
3917
3918         do {
3919                 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3920                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3921                 if (is_t4(adap->params.chip)) {
3922                         lp_count = G_LP_COUNT(v1);
3923                         hp_count = G_HP_COUNT(v1);
3924                 } else {
3925                         lp_count = G_LP_COUNT_T5(v1);
3926                         hp_count = G_HP_COUNT_T5(v2);
3927                 }
3928
3929                 if (lp_count == 0 && hp_count == 0)
3930                         break;
3931                 set_current_state(TASK_UNINTERRUPTIBLE);
3932                 schedule_timeout(usecs_to_jiffies(usecs));
3933         } while (1);
3934 }
3935
3936 static void disable_txq_db(struct sge_txq *q)
3937 {
3938         unsigned long flags;
3939
3940         spin_lock_irqsave(&q->db_lock, flags);
3941         q->db_disabled = 1;
3942         spin_unlock_irqrestore(&q->db_lock, flags);
3943 }
3944
3945 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3946 {
3947         spin_lock_irq(&q->db_lock);
3948         if (q->db_pidx_inc) {
3949                 /* Make sure that all writes to the TX descriptors
3950                  * are committed before we tell HW about them.
3951                  */
3952                 wmb();
3953                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3954                              QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3955                 q->db_pidx_inc = 0;
3956         }
3957         q->db_disabled = 0;
3958         spin_unlock_irq(&q->db_lock);
3959 }
3960
3961 static void disable_dbs(struct adapter *adap)
3962 {
3963         int i;
3964
3965         for_each_ethrxq(&adap->sge, i)
3966                 disable_txq_db(&adap->sge.ethtxq[i].q);
3967         for_each_ofldrxq(&adap->sge, i)
3968                 disable_txq_db(&adap->sge.ofldtxq[i].q);
3969         for_each_port(adap, i)
3970                 disable_txq_db(&adap->sge.ctrlq[i].q);
3971 }
3972
3973 static void enable_dbs(struct adapter *adap)
3974 {
3975         int i;
3976
3977         for_each_ethrxq(&adap->sge, i)
3978                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3979         for_each_ofldrxq(&adap->sge, i)
3980                 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3981         for_each_port(adap, i)
3982                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
3983 }
3984
3985 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3986 {
3987         if (adap->uld_handle[CXGB4_ULD_RDMA])
3988                 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3989                                 cmd);
3990 }
3991
3992 static void process_db_full(struct work_struct *work)
3993 {
3994         struct adapter *adap;
3995
3996         adap = container_of(work, struct adapter, db_full_task);
3997
3998         drain_db_fifo(adap, dbfifo_drain_delay);
3999         enable_dbs(adap);
4000         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
4001         t4_set_reg_field(adap, SGE_INT_ENABLE3,
4002                          DBFIFO_HP_INT | DBFIFO_LP_INT,
4003                          DBFIFO_HP_INT | DBFIFO_LP_INT);
4004 }
4005
4006 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
4007 {
4008         u16 hw_pidx, hw_cidx;
4009         int ret;
4010
4011         spin_lock_irq(&q->db_lock);
4012         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
4013         if (ret)
4014                 goto out;
4015         if (q->db_pidx != hw_pidx) {
4016                 u16 delta;
4017
4018                 if (q->db_pidx >= hw_pidx)
4019                         delta = q->db_pidx - hw_pidx;
4020                 else
4021                         delta = q->size - hw_pidx + q->db_pidx;
4022                 wmb();
4023                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
4024                              QID(q->cntxt_id) | PIDX(delta));
4025         }
4026 out:
4027         q->db_disabled = 0;
4028         q->db_pidx_inc = 0;
4029         spin_unlock_irq(&q->db_lock);
4030         if (ret)
4031                 CH_WARN(adap, "DB drop recovery failed.\n");
4032 }
4033 static void recover_all_queues(struct adapter *adap)
4034 {
4035         int i;
4036
4037         for_each_ethrxq(&adap->sge, i)
4038                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
4039         for_each_ofldrxq(&adap->sge, i)
4040                 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
4041         for_each_port(adap, i)
4042                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
4043 }
4044
4045 static void process_db_drop(struct work_struct *work)
4046 {
4047         struct adapter *adap;
4048
4049         adap = container_of(work, struct adapter, db_drop_task);
4050
4051         if (is_t4(adap->params.chip)) {
4052                 drain_db_fifo(adap, dbfifo_drain_delay);
4053                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
4054                 drain_db_fifo(adap, dbfifo_drain_delay);
4055                 recover_all_queues(adap);
4056                 drain_db_fifo(adap, dbfifo_drain_delay);
4057                 enable_dbs(adap);
4058                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
4059         } else {
4060                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
4061                 u16 qid = (dropped_db >> 15) & 0x1ffff;
4062                 u16 pidx_inc = dropped_db & 0x1fff;
4063                 unsigned int s_qpp;
4064                 unsigned short udb_density;
4065                 unsigned long qpshift;
4066                 int page;
4067                 u32 udb;
4068
4069                 dev_warn(adap->pdev_dev,
4070                          "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4071                          dropped_db, qid,
4072                          (dropped_db >> 14) & 1,
4073                          (dropped_db >> 13) & 1,
4074                          pidx_inc);
4075
4076                 drain_db_fifo(adap, 1);
4077
4078                 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4079                 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4080                                 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4081                 qpshift = PAGE_SHIFT - ilog2(udb_density);
4082                 udb = qid << qpshift;
4083                 udb &= PAGE_MASK;
4084                 page = udb / PAGE_SIZE;
4085                 udb += (qid - (page * udb_density)) * 128;
4086
4087                 writel(PIDX(pidx_inc),  adap->bar2 + udb + 8);
4088
4089                 /* Re-enable BAR2 WC */
4090                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4091         }
4092
4093         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
4094 }
4095
4096 void t4_db_full(struct adapter *adap)
4097 {
4098         if (is_t4(adap->params.chip)) {
4099                 disable_dbs(adap);
4100                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4101                 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4102                                  DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4103                 queue_work(adap->workq, &adap->db_full_task);
4104         }
4105 }
4106
4107 void t4_db_dropped(struct adapter *adap)
4108 {
4109         if (is_t4(adap->params.chip)) {
4110                 disable_dbs(adap);
4111                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4112         }
4113         queue_work(adap->workq, &adap->db_drop_task);
4114 }
4115
4116 static void uld_attach(struct adapter *adap, unsigned int uld)
4117 {
4118         void *handle;
4119         struct cxgb4_lld_info lli;
4120         unsigned short i;
4121
4122         lli.pdev = adap->pdev;
4123         lli.pf = adap->fn;
4124         lli.l2t = adap->l2t;
4125         lli.tids = &adap->tids;
4126         lli.ports = adap->port;
4127         lli.vr = &adap->vres;
4128         lli.mtus = adap->params.mtus;
4129         if (uld == CXGB4_ULD_RDMA) {
4130                 lli.rxq_ids = adap->sge.rdma_rxq;
4131                 lli.ciq_ids = adap->sge.rdma_ciq;
4132                 lli.nrxq = adap->sge.rdmaqs;
4133                 lli.nciq = adap->sge.rdmaciqs;
4134         } else if (uld == CXGB4_ULD_ISCSI) {
4135                 lli.rxq_ids = adap->sge.ofld_rxq;
4136                 lli.nrxq = adap->sge.ofldqsets;
4137         }
4138         lli.ntxq = adap->sge.ofldqsets;
4139         lli.nchan = adap->params.nports;
4140         lli.nports = adap->params.nports;
4141         lli.wr_cred = adap->params.ofldq_wr_cred;
4142         lli.adapter_type = adap->params.chip;
4143         lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4144         lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
4145         lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
4146                         t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4147                         (adap->fn * 4));
4148         lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
4149                         t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4150                         (adap->fn * 4));
4151         lli.filt_mode = adap->params.tp.vlan_pri_map;
4152         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4153         for (i = 0; i < NCHAN; i++)
4154                 lli.tx_modq[i] = i;
4155         lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4156         lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4157         lli.fw_vers = adap->params.fw_vers;
4158         lli.dbfifo_int_thresh = dbfifo_int_thresh;
4159         lli.sge_ingpadboundary = adap->sge.fl_align;
4160         lli.sge_egrstatuspagesize = adap->sge.stat_len;
4161         lli.sge_pktshift = adap->sge.pktshift;
4162         lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4163         lli.max_ordird_qp = adap->params.max_ordird_qp;
4164         lli.max_ird_adapter = adap->params.max_ird_adapter;
4165         lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
4166
4167         handle = ulds[uld].add(&lli);
4168         if (IS_ERR(handle)) {
4169                 dev_warn(adap->pdev_dev,
4170                          "could not attach to the %s driver, error %ld\n",
4171                          uld_str[uld], PTR_ERR(handle));
4172                 return;
4173         }
4174
4175         adap->uld_handle[uld] = handle;
4176
4177         if (!netevent_registered) {
4178                 register_netevent_notifier(&cxgb4_netevent_nb);
4179                 netevent_registered = true;
4180         }
4181
4182         if (adap->flags & FULL_INIT_DONE)
4183                 ulds[uld].state_change(handle, CXGB4_STATE_UP);
4184 }
4185
4186 static void attach_ulds(struct adapter *adap)
4187 {
4188         unsigned int i;
4189
4190         spin_lock(&adap_rcu_lock);
4191         list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4192         spin_unlock(&adap_rcu_lock);
4193
4194         mutex_lock(&uld_mutex);
4195         list_add_tail(&adap->list_node, &adapter_list);
4196         for (i = 0; i < CXGB4_ULD_MAX; i++)
4197                 if (ulds[i].add)
4198                         uld_attach(adap, i);
4199         mutex_unlock(&uld_mutex);
4200 }
4201
4202 static void detach_ulds(struct adapter *adap)
4203 {
4204         unsigned int i;
4205
4206         mutex_lock(&uld_mutex);
4207         list_del(&adap->list_node);
4208         for (i = 0; i < CXGB4_ULD_MAX; i++)
4209                 if (adap->uld_handle[i]) {
4210                         ulds[i].state_change(adap->uld_handle[i],
4211                                              CXGB4_STATE_DETACH);
4212                         adap->uld_handle[i] = NULL;
4213                 }
4214         if (netevent_registered && list_empty(&adapter_list)) {
4215                 unregister_netevent_notifier(&cxgb4_netevent_nb);
4216                 netevent_registered = false;
4217         }
4218         mutex_unlock(&uld_mutex);
4219
4220         spin_lock(&adap_rcu_lock);
4221         list_del_rcu(&adap->rcu_node);
4222         spin_unlock(&adap_rcu_lock);
4223 }
4224
4225 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4226 {
4227         unsigned int i;
4228
4229         mutex_lock(&uld_mutex);
4230         for (i = 0; i < CXGB4_ULD_MAX; i++)
4231                 if (adap->uld_handle[i])
4232                         ulds[i].state_change(adap->uld_handle[i], new_state);
4233         mutex_unlock(&uld_mutex);
4234 }
4235
4236 /**
4237  *      cxgb4_register_uld - register an upper-layer driver
4238  *      @type: the ULD type
4239  *      @p: the ULD methods
4240  *
4241  *      Registers an upper-layer driver with this driver and notifies the ULD
4242  *      about any presently available devices that support its type.  Returns
4243  *      %-EBUSY if a ULD of the same type is already registered.
4244  */
4245 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4246 {
4247         int ret = 0;
4248         struct adapter *adap;
4249
4250         if (type >= CXGB4_ULD_MAX)
4251                 return -EINVAL;
4252         mutex_lock(&uld_mutex);
4253         if (ulds[type].add) {
4254                 ret = -EBUSY;
4255                 goto out;
4256         }
4257         ulds[type] = *p;
4258         list_for_each_entry(adap, &adapter_list, list_node)
4259                 uld_attach(adap, type);
4260 out:    mutex_unlock(&uld_mutex);
4261         return ret;
4262 }
4263 EXPORT_SYMBOL(cxgb4_register_uld);
4264
4265 /**
4266  *      cxgb4_unregister_uld - unregister an upper-layer driver
4267  *      @type: the ULD type
4268  *
4269  *      Unregisters an existing upper-layer driver.
4270  */
4271 int cxgb4_unregister_uld(enum cxgb4_uld type)
4272 {
4273         struct adapter *adap;
4274
4275         if (type >= CXGB4_ULD_MAX)
4276                 return -EINVAL;
4277         mutex_lock(&uld_mutex);
4278         list_for_each_entry(adap, &adapter_list, list_node)
4279                 adap->uld_handle[type] = NULL;
4280         ulds[type].add = NULL;
4281         mutex_unlock(&uld_mutex);
4282         return 0;
4283 }
4284 EXPORT_SYMBOL(cxgb4_unregister_uld);
4285
4286 /* Check if netdev on which event is occured belongs to us or not. Return
4287  * success (true) if it belongs otherwise failure (false).
4288  * Called with rcu_read_lock() held.
4289  */
4290 #if IS_ENABLED(CONFIG_IPV6)
4291 static bool cxgb4_netdev(const struct net_device *netdev)
4292 {
4293         struct adapter *adap;
4294         int i;
4295
4296         list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4297                 for (i = 0; i < MAX_NPORTS; i++)
4298                         if (adap->port[i] == netdev)
4299                                 return true;
4300         return false;
4301 }
4302
4303 static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4304                     unsigned long event)
4305 {
4306         int ret = NOTIFY_DONE;
4307
4308         rcu_read_lock();
4309         if (cxgb4_netdev(event_dev)) {
4310                 switch (event) {
4311                 case NETDEV_UP:
4312                         ret = cxgb4_clip_get(event_dev, &ifa->addr);
4313                         if (ret < 0) {
4314                                 rcu_read_unlock();
4315                                 return ret;
4316                         }
4317                         ret = NOTIFY_OK;
4318                         break;
4319                 case NETDEV_DOWN:
4320                         cxgb4_clip_release(event_dev, &ifa->addr);
4321                         ret = NOTIFY_OK;
4322                         break;
4323                 default:
4324                         break;
4325                 }
4326         }
4327         rcu_read_unlock();
4328         return ret;
4329 }
4330
4331 static int cxgb4_inet6addr_handler(struct notifier_block *this,
4332                 unsigned long event, void *data)
4333 {
4334         struct inet6_ifaddr *ifa = data;
4335         struct net_device *event_dev;
4336         int ret = NOTIFY_DONE;
4337         struct bonding *bond = netdev_priv(ifa->idev->dev);
4338         struct list_head *iter;
4339         struct slave *slave;
4340         struct pci_dev *first_pdev = NULL;
4341
4342         if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4343                 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4344                 ret = clip_add(event_dev, ifa, event);
4345         } else if (ifa->idev->dev->flags & IFF_MASTER) {
4346                 /* It is possible that two different adapters are bonded in one
4347                  * bond. We need to find such different adapters and add clip
4348                  * in all of them only once.
4349                  */
4350                 bond_for_each_slave(bond, slave, iter) {
4351                         if (!first_pdev) {
4352                                 ret = clip_add(slave->dev, ifa, event);
4353                                 /* If clip_add is success then only initialize
4354                                  * first_pdev since it means it is our device
4355                                  */
4356                                 if (ret == NOTIFY_OK)
4357                                         first_pdev = to_pci_dev(
4358                                                         slave->dev->dev.parent);
4359                         } else if (first_pdev !=
4360                                    to_pci_dev(slave->dev->dev.parent))
4361                                         ret = clip_add(slave->dev, ifa, event);
4362                 }
4363         } else
4364                 ret = clip_add(ifa->idev->dev, ifa, event);
4365
4366         return ret;
4367 }
4368
4369 static struct notifier_block cxgb4_inet6addr_notifier = {
4370         .notifier_call = cxgb4_inet6addr_handler
4371 };
4372
4373 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4374  * a physical device.
4375  * The physical device reference is needed to send the actul CLIP command.
4376  */
4377 static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4378 {
4379         struct inet6_dev *idev = NULL;
4380         struct inet6_ifaddr *ifa;
4381         int ret = 0;
4382
4383         idev = __in6_dev_get(root_dev);
4384         if (!idev)
4385                 return ret;
4386
4387         read_lock_bh(&idev->lock);
4388         list_for_each_entry(ifa, &idev->addr_list, if_list) {
4389                 ret = cxgb4_clip_get(dev, &ifa->addr);
4390                 if (ret < 0)
4391                         break;
4392         }
4393         read_unlock_bh(&idev->lock);
4394
4395         return ret;
4396 }
4397
4398 static int update_root_dev_clip(struct net_device *dev)
4399 {
4400         struct net_device *root_dev = NULL;
4401         int i, ret = 0;
4402
4403         /* First populate the real net device's IPv6 addresses */
4404         ret = update_dev_clip(dev, dev);
4405         if (ret)
4406                 return ret;
4407
4408         /* Parse all bond and vlan devices layered on top of the physical dev */
4409         root_dev = netdev_master_upper_dev_get_rcu(dev);
4410         if (root_dev) {
4411                 ret = update_dev_clip(root_dev, dev);
4412                 if (ret)
4413                         return ret;
4414         }
4415
4416         for (i = 0; i < VLAN_N_VID; i++) {
4417                 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
4418                 if (!root_dev)
4419                         continue;
4420
4421                 ret = update_dev_clip(root_dev, dev);
4422                 if (ret)
4423                         break;
4424         }
4425         return ret;
4426 }
4427
4428 static void update_clip(const struct adapter *adap)
4429 {
4430         int i;
4431         struct net_device *dev;
4432         int ret;
4433
4434         rcu_read_lock();
4435
4436         for (i = 0; i < MAX_NPORTS; i++) {
4437                 dev = adap->port[i];
4438                 ret = 0;
4439
4440                 if (dev)
4441                         ret = update_root_dev_clip(dev);
4442
4443                 if (ret < 0)
4444                         break;
4445         }
4446         rcu_read_unlock();
4447 }
4448 #endif /* IS_ENABLED(CONFIG_IPV6) */
4449
4450 /**
4451  *      cxgb_up - enable the adapter
4452  *      @adap: adapter being enabled
4453  *
4454  *      Called when the first port is enabled, this function performs the
4455  *      actions necessary to make an adapter operational, such as completing
4456  *      the initialization of HW modules, and enabling interrupts.
4457  *
4458  *      Must be called with the rtnl lock held.
4459  */
4460 static int cxgb_up(struct adapter *adap)
4461 {
4462         int err;
4463
4464         err = setup_sge_queues(adap);
4465         if (err)
4466                 goto out;
4467         err = setup_rss(adap);
4468         if (err)
4469                 goto freeq;
4470
4471         if (adap->flags & USING_MSIX) {
4472                 name_msix_vecs(adap);
4473                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4474                                   adap->msix_info[0].desc, adap);
4475                 if (err)
4476                         goto irq_err;
4477
4478                 err = request_msix_queue_irqs(adap);
4479                 if (err) {
4480                         free_irq(adap->msix_info[0].vec, adap);
4481                         goto irq_err;
4482                 }
4483         } else {
4484                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4485                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
4486                                   adap->port[0]->name, adap);
4487                 if (err)
4488                         goto irq_err;
4489         }
4490         enable_rx(adap);
4491         t4_sge_start(adap);
4492         t4_intr_enable(adap);
4493         adap->flags |= FULL_INIT_DONE;
4494         notify_ulds(adap, CXGB4_STATE_UP);
4495 #if IS_ENABLED(CONFIG_IPV6)
4496         update_clip(adap);
4497 #endif
4498  out:
4499         return err;
4500  irq_err:
4501         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
4502  freeq:
4503         t4_free_sge_resources(adap);
4504         goto out;
4505 }
4506
4507 static void cxgb_down(struct adapter *adapter)
4508 {
4509         t4_intr_disable(adapter);
4510         cancel_work_sync(&adapter->tid_release_task);
4511         cancel_work_sync(&adapter->db_full_task);
4512         cancel_work_sync(&adapter->db_drop_task);
4513         adapter->tid_release_task_busy = false;
4514         adapter->tid_release_head = NULL;
4515
4516         if (adapter->flags & USING_MSIX) {
4517                 free_msix_queue_irqs(adapter);
4518                 free_irq(adapter->msix_info[0].vec, adapter);
4519         } else
4520                 free_irq(adapter->pdev->irq, adapter);
4521         quiesce_rx(adapter);
4522         t4_sge_stop(adapter);
4523         t4_free_sge_resources(adapter);
4524         adapter->flags &= ~FULL_INIT_DONE;
4525 }
4526
4527 /*
4528  * net_device operations
4529  */
4530 static int cxgb_open(struct net_device *dev)
4531 {
4532         int err;
4533         struct port_info *pi = netdev_priv(dev);
4534         struct adapter *adapter = pi->adapter;
4535
4536         netif_carrier_off(dev);
4537
4538         if (!(adapter->flags & FULL_INIT_DONE)) {
4539                 err = cxgb_up(adapter);
4540                 if (err < 0)
4541                         return err;
4542         }
4543
4544         err = link_start(dev);
4545         if (!err)
4546                 netif_tx_start_all_queues(dev);
4547         return err;
4548 }
4549
4550 static int cxgb_close(struct net_device *dev)
4551 {
4552         struct port_info *pi = netdev_priv(dev);
4553         struct adapter *adapter = pi->adapter;
4554
4555         netif_tx_stop_all_queues(dev);
4556         netif_carrier_off(dev);
4557         return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
4558 }
4559
4560 /* Return an error number if the indicated filter isn't writable ...
4561  */
4562 static int writable_filter(struct filter_entry *f)
4563 {
4564         if (f->locked)
4565                 return -EPERM;
4566         if (f->pending)
4567                 return -EBUSY;
4568
4569         return 0;
4570 }
4571
4572 /* Delete the filter at the specified index (if valid).  The checks for all
4573  * the common problems with doing this like the filter being locked, currently
4574  * pending in another operation, etc.
4575  */
4576 static int delete_filter(struct adapter *adapter, unsigned int fidx)
4577 {
4578         struct filter_entry *f;
4579         int ret;
4580
4581         if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
4582                 return -EINVAL;
4583
4584         f = &adapter->tids.ftid_tab[fidx];
4585         ret = writable_filter(f);
4586         if (ret)
4587                 return ret;
4588         if (f->valid)
4589                 return del_filter_wr(adapter, fidx);
4590
4591         return 0;
4592 }
4593
4594 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
4595                 __be32 sip, __be16 sport, __be16 vlan,
4596                 unsigned int queue, unsigned char port, unsigned char mask)
4597 {
4598         int ret;
4599         struct filter_entry *f;
4600         struct adapter *adap;
4601         int i;
4602         u8 *val;
4603
4604         adap = netdev2adap(dev);
4605
4606         /* Adjust stid to correct filter index */
4607         stid -= adap->tids.sftid_base;
4608         stid += adap->tids.nftids;
4609
4610         /* Check to make sure the filter requested is writable ...
4611          */
4612         f = &adap->tids.ftid_tab[stid];
4613         ret = writable_filter(f);
4614         if (ret)
4615                 return ret;
4616
4617         /* Clear out any old resources being used by the filter before
4618          * we start constructing the new filter.
4619          */
4620         if (f->valid)
4621                 clear_filter(adap, f);
4622
4623         /* Clear out filter specifications */
4624         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4625         f->fs.val.lport = cpu_to_be16(sport);
4626         f->fs.mask.lport  = ~0;
4627         val = (u8 *)&sip;
4628         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
4629                 for (i = 0; i < 4; i++) {
4630                         f->fs.val.lip[i] = val[i];
4631                         f->fs.mask.lip[i] = ~0;
4632                 }
4633                 if (adap->params.tp.vlan_pri_map & F_PORT) {
4634                         f->fs.val.iport = port;
4635                         f->fs.mask.iport = mask;
4636                 }
4637         }
4638
4639         if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
4640                 f->fs.val.proto = IPPROTO_TCP;
4641                 f->fs.mask.proto = ~0;
4642         }
4643
4644         f->fs.dirsteer = 1;
4645         f->fs.iq = queue;
4646         /* Mark filter as locked */
4647         f->locked = 1;
4648         f->fs.rpttid = 1;
4649
4650         ret = set_filter_wr(adap, stid);
4651         if (ret) {
4652                 clear_filter(adap, f);
4653                 return ret;
4654         }
4655
4656         return 0;
4657 }
4658 EXPORT_SYMBOL(cxgb4_create_server_filter);
4659
4660 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4661                 unsigned int queue, bool ipv6)
4662 {
4663         int ret;
4664         struct filter_entry *f;
4665         struct adapter *adap;
4666
4667         adap = netdev2adap(dev);
4668
4669         /* Adjust stid to correct filter index */
4670         stid -= adap->tids.sftid_base;
4671         stid += adap->tids.nftids;
4672
4673         f = &adap->tids.ftid_tab[stid];
4674         /* Unlock the filter */
4675         f->locked = 0;
4676
4677         ret = delete_filter(adap, stid);
4678         if (ret)
4679                 return ret;
4680
4681         return 0;
4682 }
4683 EXPORT_SYMBOL(cxgb4_remove_server_filter);
4684
4685 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4686                                                 struct rtnl_link_stats64 *ns)
4687 {
4688         struct port_stats stats;
4689         struct port_info *p = netdev_priv(dev);
4690         struct adapter *adapter = p->adapter;
4691
4692         /* Block retrieving statistics during EEH error
4693          * recovery. Otherwise, the recovery might fail
4694          * and the PCI device will be removed permanently
4695          */
4696         spin_lock(&adapter->stats_lock);
4697         if (!netif_device_present(dev)) {
4698                 spin_unlock(&adapter->stats_lock);
4699                 return ns;
4700         }
4701         t4_get_port_stats(adapter, p->tx_chan, &stats);
4702         spin_unlock(&adapter->stats_lock);
4703
4704         ns->tx_bytes   = stats.tx_octets;
4705         ns->tx_packets = stats.tx_frames;
4706         ns->rx_bytes   = stats.rx_octets;
4707         ns->rx_packets = stats.rx_frames;
4708         ns->multicast  = stats.rx_mcast_frames;
4709
4710         /* detailed rx_errors */
4711         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4712                                stats.rx_runt;
4713         ns->rx_over_errors   = 0;
4714         ns->rx_crc_errors    = stats.rx_fcs_err;
4715         ns->rx_frame_errors  = stats.rx_symbol_err;
4716         ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
4717                                stats.rx_ovflow2 + stats.rx_ovflow3 +
4718                                stats.rx_trunc0 + stats.rx_trunc1 +
4719                                stats.rx_trunc2 + stats.rx_trunc3;
4720         ns->rx_missed_errors = 0;
4721
4722         /* detailed tx_errors */
4723         ns->tx_aborted_errors   = 0;
4724         ns->tx_carrier_errors   = 0;
4725         ns->tx_fifo_errors      = 0;
4726         ns->tx_heartbeat_errors = 0;
4727         ns->tx_window_errors    = 0;
4728
4729         ns->tx_errors = stats.tx_error_frames;
4730         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4731                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4732         return ns;
4733 }
4734
4735 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4736 {
4737         unsigned int mbox;
4738         int ret = 0, prtad, devad;
4739         struct port_info *pi = netdev_priv(dev);
4740         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4741
4742         switch (cmd) {
4743         case SIOCGMIIPHY:
4744                 if (pi->mdio_addr < 0)
4745                         return -EOPNOTSUPP;
4746                 data->phy_id = pi->mdio_addr;
4747                 break;
4748         case SIOCGMIIREG:
4749         case SIOCSMIIREG:
4750                 if (mdio_phy_id_is_c45(data->phy_id)) {
4751                         prtad = mdio_phy_id_prtad(data->phy_id);
4752                         devad = mdio_phy_id_devad(data->phy_id);
4753                 } else if (data->phy_id < 32) {
4754                         prtad = data->phy_id;
4755                         devad = 0;
4756                         data->reg_num &= 0x1f;
4757                 } else
4758                         return -EINVAL;
4759
4760                 mbox = pi->adapter->fn;
4761                 if (cmd == SIOCGMIIREG)
4762                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
4763                                          data->reg_num, &data->val_out);
4764                 else
4765                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
4766                                          data->reg_num, data->val_in);
4767                 break;
4768         default:
4769                 return -EOPNOTSUPP;
4770         }
4771         return ret;
4772 }
4773
4774 static void cxgb_set_rxmode(struct net_device *dev)
4775 {
4776         /* unfortunately we can't return errors to the stack */
4777         set_rxmode(dev, -1, false);
4778 }
4779
4780 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4781 {
4782         int ret;
4783         struct port_info *pi = netdev_priv(dev);
4784
4785         if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
4786                 return -EINVAL;
4787         ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4788                             -1, -1, -1, true);
4789         if (!ret)
4790                 dev->mtu = new_mtu;
4791         return ret;
4792 }
4793
4794 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4795 {
4796         int ret;
4797         struct sockaddr *addr = p;
4798         struct port_info *pi = netdev_priv(dev);
4799
4800         if (!is_valid_ether_addr(addr->sa_data))
4801                 return -EADDRNOTAVAIL;
4802
4803         ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4804                             pi->xact_addr_filt, addr->sa_data, true, true);
4805         if (ret < 0)
4806                 return ret;
4807
4808         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4809         pi->xact_addr_filt = ret;
4810         return 0;
4811 }
4812
4813 #ifdef CONFIG_NET_POLL_CONTROLLER
4814 static void cxgb_netpoll(struct net_device *dev)
4815 {
4816         struct port_info *pi = netdev_priv(dev);
4817         struct adapter *adap = pi->adapter;
4818
4819         if (adap->flags & USING_MSIX) {
4820                 int i;
4821                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4822
4823                 for (i = pi->nqsets; i; i--, rx++)
4824                         t4_sge_intr_msix(0, &rx->rspq);
4825         } else
4826                 t4_intr_handler(adap)(0, adap);
4827 }
4828 #endif
4829
4830 static const struct net_device_ops cxgb4_netdev_ops = {
4831         .ndo_open             = cxgb_open,
4832         .ndo_stop             = cxgb_close,
4833         .ndo_start_xmit       = t4_eth_xmit,
4834         .ndo_select_queue     = cxgb_select_queue,
4835         .ndo_get_stats64      = cxgb_get_stats,
4836         .ndo_set_rx_mode      = cxgb_set_rxmode,
4837         .ndo_set_mac_address  = cxgb_set_mac_addr,
4838         .ndo_set_features     = cxgb_set_features,
4839         .ndo_validate_addr    = eth_validate_addr,
4840         .ndo_do_ioctl         = cxgb_ioctl,
4841         .ndo_change_mtu       = cxgb_change_mtu,
4842 #ifdef CONFIG_NET_POLL_CONTROLLER
4843         .ndo_poll_controller  = cxgb_netpoll,
4844 #endif
4845 };
4846
4847 void t4_fatal_err(struct adapter *adap)
4848 {
4849         t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4850         t4_intr_disable(adap);
4851         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4852 }
4853
4854 /* Return the specified PCI-E Configuration Space register from our Physical
4855  * Function.  We try first via a Firmware LDST Command since we prefer to let
4856  * the firmware own all of these registers, but if that fails we go for it
4857  * directly ourselves.
4858  */
4859 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4860 {
4861         struct fw_ldst_cmd ldst_cmd;
4862         u32 val;
4863         int ret;
4864
4865         /* Construct and send the Firmware LDST Command to retrieve the
4866          * specified PCI-E Configuration Space register.
4867          */
4868         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4869         ldst_cmd.op_to_addrspace =
4870                 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
4871                       FW_CMD_REQUEST_F |
4872                       FW_CMD_READ_F |
4873                       FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
4874         ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4875         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
4876         ldst_cmd.u.pcie.ctrl_to_fn =
4877                 (FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
4878         ldst_cmd.u.pcie.r = reg;
4879         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4880                          &ldst_cmd);
4881
4882         /* If the LDST Command suucceeded, exctract the returned register
4883          * value.  Otherwise read it directly ourself.
4884          */
4885         if (ret == 0)
4886                 val = ntohl(ldst_cmd.u.pcie.data[0]);
4887         else
4888                 t4_hw_pci_read_cfg4(adap, reg, &val);
4889
4890         return val;
4891 }
4892
4893 static void setup_memwin(struct adapter *adap)
4894 {
4895         u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
4896
4897         if (is_t4(adap->params.chip)) {
4898                 u32 bar0;
4899
4900                 /* Truncation intentional: we only read the bottom 32-bits of
4901                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
4902                  * mechanism to read BAR0 instead of using
4903                  * pci_resource_start() because we could be operating from
4904                  * within a Virtual Machine which is trapping our accesses to
4905                  * our Configuration Space and we need to set up the PCI-E
4906                  * Memory Window decoders with the actual addresses which will
4907                  * be coming across the PCI-E link.
4908                  */
4909                 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4910                 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4911                 adap->t4_bar0 = bar0;
4912
4913                 mem_win0_base = bar0 + MEMWIN0_BASE;
4914                 mem_win1_base = bar0 + MEMWIN1_BASE;
4915                 mem_win2_base = bar0 + MEMWIN2_BASE;
4916                 mem_win2_aperture = MEMWIN2_APERTURE;
4917         } else {
4918                 /* For T5, only relative offset inside the PCIe BAR is passed */
4919                 mem_win0_base = MEMWIN0_BASE;
4920                 mem_win1_base = MEMWIN1_BASE;
4921                 mem_win2_base = MEMWIN2_BASE_T5;
4922                 mem_win2_aperture = MEMWIN2_APERTURE_T5;
4923         }
4924         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
4925                      mem_win0_base | BIR(0) |
4926                      WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4927         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
4928                      mem_win1_base | BIR(0) |
4929                      WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4930         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
4931                      mem_win2_base | BIR(0) |
4932                      WINDOW(ilog2(mem_win2_aperture) - 10));
4933         t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
4934 }
4935
4936 static void setup_memwin_rdma(struct adapter *adap)
4937 {
4938         if (adap->vres.ocq.size) {
4939                 u32 start;
4940                 unsigned int sz_kb;
4941
4942                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4943                 start &= PCI_BASE_ADDRESS_MEM_MASK;
4944                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4945                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4946                 t4_write_reg(adap,
4947                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4948                              start | BIR(1) | WINDOW(ilog2(sz_kb)));
4949                 t4_write_reg(adap,
4950                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4951                              adap->vres.ocq.start);
4952                 t4_read_reg(adap,
4953                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4954         }
4955 }
4956
4957 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4958 {
4959         u32 v;
4960         int ret;
4961
4962         /* get device capabilities */
4963         memset(c, 0, sizeof(*c));
4964         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4965                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
4966         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
4967         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
4968         if (ret < 0)
4969                 return ret;
4970
4971         /* select capabilities we'll be using */
4972         if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4973                 if (!vf_acls)
4974                         c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4975                 else
4976                         c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4977         } else if (vf_acls) {
4978                 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4979                 return ret;
4980         }
4981         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4982                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4983         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
4984         if (ret < 0)
4985                 return ret;
4986
4987         ret = t4_config_glbl_rss(adap, adap->fn,
4988                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4989                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
4990                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
4991         if (ret < 0)
4992                 return ret;
4993
4994         ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4995                           0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
4996         if (ret < 0)
4997                 return ret;
4998
4999         t4_sge_init(adap);
5000
5001         /* tweak some settings */
5002         t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
5003         t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
5004         t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
5005         v = t4_read_reg(adap, TP_PIO_DATA);
5006         t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
5007
5008         /* first 4 Tx modulation queues point to consecutive Tx channels */
5009         adap->params.tp.tx_modq_map = 0xE4;
5010         t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
5011                      V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
5012
5013         /* associate each Tx modulation queue with consecutive Tx channels */
5014         v = 0x84218421;
5015         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5016                           &v, 1, A_TP_TX_SCHED_HDR);
5017         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5018                           &v, 1, A_TP_TX_SCHED_FIFO);
5019         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
5020                           &v, 1, A_TP_TX_SCHED_PCMD);
5021
5022 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
5023         if (is_offload(adap)) {
5024                 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
5025                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5026                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5027                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5028                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5029                 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
5030                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5031                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5032                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
5033                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
5034         }
5035
5036         /* get basic stuff going */
5037         return t4_early_init(adap, adap->fn);
5038 }
5039
5040 /*
5041  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
5042  */
5043 #define MAX_ATIDS 8192U
5044
5045 /*
5046  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5047  *
5048  * If the firmware we're dealing with has Configuration File support, then
5049  * we use that to perform all configuration
5050  */
5051
5052 /*
5053  * Tweak configuration based on module parameters, etc.  Most of these have
5054  * defaults assigned to them by Firmware Configuration Files (if we're using
5055  * them) but need to be explicitly set if we're using hard-coded
5056  * initialization.  But even in the case of using Firmware Configuration
5057  * Files, we'd like to expose the ability to change these via module
5058  * parameters so these are essentially common tweaks/settings for
5059  * Configuration Files and hard-coded initialization ...
5060  */
5061 static int adap_init0_tweaks(struct adapter *adapter)
5062 {
5063         /*
5064          * Fix up various Host-Dependent Parameters like Page Size, Cache
5065          * Line Size, etc.  The firmware default is for a 4KB Page Size and
5066          * 64B Cache Line Size ...
5067          */
5068         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
5069
5070         /*
5071          * Process module parameters which affect early initialization.
5072          */
5073         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
5074                 dev_err(&adapter->pdev->dev,
5075                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
5076                         rx_dma_offset);
5077                 rx_dma_offset = 2;
5078         }
5079         t4_set_reg_field(adapter, SGE_CONTROL,
5080                          PKTSHIFT_MASK,
5081                          PKTSHIFT(rx_dma_offset));
5082
5083         /*
5084          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5085          * adds the pseudo header itself.
5086          */
5087         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5088                                CSUM_HAS_PSEUDO_HDR, 0);
5089
5090         return 0;
5091 }
5092
5093 /*
5094  * Attempt to initialize the adapter via a Firmware Configuration File.
5095  */
5096 static int adap_init0_config(struct adapter *adapter, int reset)
5097 {
5098         struct fw_caps_config_cmd caps_cmd;
5099         const struct firmware *cf;
5100         unsigned long mtype = 0, maddr = 0;
5101         u32 finiver, finicsum, cfcsum;
5102         int ret;
5103         int config_issued = 0;
5104         char *fw_config_file, fw_config_file_path[256];
5105         char *config_name = NULL;
5106
5107         /*
5108          * Reset device if necessary.
5109          */
5110         if (reset) {
5111                 ret = t4_fw_reset(adapter, adapter->mbox,
5112                                   PIORSTMODE | PIORST);
5113                 if (ret < 0)
5114                         goto bye;
5115         }
5116
5117         /*
5118          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5119          * then use that.  Otherwise, use the configuration file stored
5120          * in the adapter flash ...
5121          */
5122         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
5123         case CHELSIO_T4:
5124                 fw_config_file = FW4_CFNAME;
5125                 break;
5126         case CHELSIO_T5:
5127                 fw_config_file = FW5_CFNAME;
5128                 break;
5129         default:
5130                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5131                        adapter->pdev->device);
5132                 ret = -EINVAL;
5133                 goto bye;
5134         }
5135
5136         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
5137         if (ret < 0) {
5138                 config_name = "On FLASH";
5139                 mtype = FW_MEMTYPE_CF_FLASH;
5140                 maddr = t4_flash_cfg_addr(adapter);
5141         } else {
5142                 u32 params[7], val[7];
5143
5144                 sprintf(fw_config_file_path,
5145                         "/lib/firmware/%s", fw_config_file);
5146                 config_name = fw_config_file_path;
5147
5148                 if (cf->size >= FLASH_CFG_MAX_SIZE)
5149                         ret = -ENOMEM;
5150                 else {
5151                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5152                              FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5153                         ret = t4_query_params(adapter, adapter->mbox,
5154                                               adapter->fn, 0, 1, params, val);
5155                         if (ret == 0) {
5156                                 /*
5157                                  * For t4_memory_rw() below addresses and
5158                                  * sizes have to be in terms of multiples of 4
5159                                  * bytes.  So, if the Configuration File isn't
5160                                  * a multiple of 4 bytes in length we'll have
5161                                  * to write that out separately since we can't
5162                                  * guarantee that the bytes following the
5163                                  * residual byte in the buffer returned by
5164                                  * request_firmware() are zeroed out ...
5165                                  */
5166                                 size_t resid = cf->size & 0x3;
5167                                 size_t size = cf->size & ~0x3;
5168                                 __be32 *data = (__be32 *)cf->data;
5169
5170                                 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
5171                                 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
5172
5173                                 spin_lock(&adapter->win0_lock);
5174                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
5175                                                    size, data, T4_MEMORY_WRITE);
5176                                 if (ret == 0 && resid != 0) {
5177                                         union {
5178                                                 __be32 word;
5179                                                 char buf[4];
5180                                         } last;
5181                                         int i;
5182
5183                                         last.word = data[size >> 2];
5184                                         for (i = resid; i < 4; i++)
5185                                                 last.buf[i] = 0;
5186                                         ret = t4_memory_rw(adapter, 0, mtype,
5187                                                            maddr + size,
5188                                                            4, &last.word,
5189                                                            T4_MEMORY_WRITE);
5190                                 }
5191                                 spin_unlock(&adapter->win0_lock);
5192                         }
5193                 }
5194
5195                 release_firmware(cf);
5196                 if (ret)
5197                         goto bye;
5198         }
5199
5200         /*
5201          * Issue a Capability Configuration command to the firmware to get it
5202          * to parse the Configuration File.  We don't use t4_fw_config_file()
5203          * because we want the ability to modify various features after we've
5204          * processed the configuration file ...
5205          */
5206         memset(&caps_cmd, 0, sizeof(caps_cmd));
5207         caps_cmd.op_to_write =
5208                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5209                       FW_CMD_REQUEST_F |
5210                       FW_CMD_READ_F);
5211         caps_cmd.cfvalid_to_len16 =
5212                 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
5213                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5214                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
5215                       FW_LEN16(caps_cmd));
5216         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5217                          &caps_cmd);
5218
5219         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5220          * Configuration File in FLASH), our last gasp effort is to use the
5221          * Firmware Configuration File which is embedded in the firmware.  A
5222          * very few early versions of the firmware didn't have one embedded
5223          * but we can ignore those.
5224          */
5225         if (ret == -ENOENT) {
5226                 memset(&caps_cmd, 0, sizeof(caps_cmd));
5227                 caps_cmd.op_to_write =
5228                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5229                                         FW_CMD_REQUEST_F |
5230                                         FW_CMD_READ_F);
5231                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5232                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5233                                 sizeof(caps_cmd), &caps_cmd);
5234                 config_name = "Firmware Default";
5235         }
5236
5237         config_issued = 1;
5238         if (ret < 0)
5239                 goto bye;
5240
5241         finiver = ntohl(caps_cmd.finiver);
5242         finicsum = ntohl(caps_cmd.finicsum);
5243         cfcsum = ntohl(caps_cmd.cfcsum);
5244         if (finicsum != cfcsum)
5245                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5246                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5247                          finicsum, cfcsum);
5248
5249         /*
5250          * And now tell the firmware to use the configuration we just loaded.
5251          */
5252         caps_cmd.op_to_write =
5253                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5254                       FW_CMD_REQUEST_F |
5255                       FW_CMD_WRITE_F);
5256         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5257         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5258                          NULL);
5259         if (ret < 0)
5260                 goto bye;
5261
5262         /*
5263          * Tweak configuration based on system architecture, module
5264          * parameters, etc.
5265          */
5266         ret = adap_init0_tweaks(adapter);
5267         if (ret < 0)
5268                 goto bye;
5269
5270         /*
5271          * And finally tell the firmware to initialize itself using the
5272          * parameters from the Configuration File.
5273          */
5274         ret = t4_fw_initialize(adapter, adapter->mbox);
5275         if (ret < 0)
5276                 goto bye;
5277
5278         /*
5279          * Return successfully and note that we're operating with parameters
5280          * not supplied by the driver, rather than from hard-wired
5281          * initialization constants burried in the driver.
5282          */
5283         adapter->flags |= USING_SOFT_PARAMS;
5284         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
5285                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5286                  config_name, finiver, cfcsum);
5287         return 0;
5288
5289         /*
5290          * Something bad happened.  Return the error ...  (If the "error"
5291          * is that there's no Configuration File on the adapter we don't
5292          * want to issue a warning since this is fairly common.)
5293          */
5294 bye:
5295         if (config_issued && ret != -ENOENT)
5296                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5297                          config_name, -ret);
5298         return ret;
5299 }
5300
5301 /*
5302  * Attempt to initialize the adapter via hard-coded, driver supplied
5303  * parameters ...
5304  */
5305 static int adap_init0_no_config(struct adapter *adapter, int reset)
5306 {
5307         struct sge *s = &adapter->sge;
5308         struct fw_caps_config_cmd caps_cmd;
5309         u32 v;
5310         int i, ret;
5311
5312         /*
5313          * Reset device if necessary
5314          */
5315         if (reset) {
5316                 ret = t4_fw_reset(adapter, adapter->mbox,
5317                                   PIORSTMODE | PIORST);
5318                 if (ret < 0)
5319                         goto bye;
5320         }
5321
5322         /*
5323          * Get device capabilities and select which we'll be using.
5324          */
5325         memset(&caps_cmd, 0, sizeof(caps_cmd));
5326         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5327                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
5328         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5329         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5330                          &caps_cmd);
5331         if (ret < 0)
5332                 goto bye;
5333
5334         if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5335                 if (!vf_acls)
5336                         caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5337                 else
5338                         caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5339         } else if (vf_acls) {
5340                 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5341                 goto bye;
5342         }
5343         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5344                               FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5345         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5346                          NULL);
5347         if (ret < 0)
5348                 goto bye;
5349
5350         /*
5351          * Tweak configuration based on system architecture, module
5352          * parameters, etc.
5353          */
5354         ret = adap_init0_tweaks(adapter);
5355         if (ret < 0)
5356                 goto bye;
5357
5358         /*
5359          * Select RSS Global Mode we want to use.  We use "Basic Virtual"
5360          * mode which maps each Virtual Interface to its own section of
5361          * the RSS Table and we turn on all map and hash enables ...
5362          */
5363         adapter->flags |= RSS_TNLALLLOOKUP;
5364         ret = t4_config_glbl_rss(adapter, adapter->mbox,
5365                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5366                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5367                                  FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
5368                                  ((adapter->flags & RSS_TNLALLLOOKUP) ?
5369                                         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
5370         if (ret < 0)
5371                 goto bye;
5372
5373         /*
5374          * Set up our own fundamental resource provisioning ...
5375          */
5376         ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5377                           PFRES_NEQ, PFRES_NETHCTRL,
5378                           PFRES_NIQFLINT, PFRES_NIQ,
5379                           PFRES_TC, PFRES_NVI,
5380                           FW_PFVF_CMD_CMASK_MASK,
5381                           pfvfres_pmask(adapter, adapter->fn, 0),
5382                           PFRES_NEXACTF,
5383                           PFRES_R_CAPS, PFRES_WX_CAPS);
5384         if (ret < 0)
5385                 goto bye;
5386
5387         /*
5388          * Perform low level SGE initialization.  We need to do this before we
5389          * send the firmware the INITIALIZE command because that will cause
5390          * any other PF Drivers which are waiting for the Master
5391          * Initialization to proceed forward.
5392          */
5393         for (i = 0; i < SGE_NTIMERS - 1; i++)
5394                 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5395         s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5396         s->counter_val[0] = 1;
5397         for (i = 1; i < SGE_NCOUNTERS; i++)
5398                 s->counter_val[i] = min(intr_cnt[i - 1],
5399                                         THRESHOLD_0_GET(THRESHOLD_0_MASK));
5400         t4_sge_init(adapter);
5401
5402 #ifdef CONFIG_PCI_IOV
5403         /*
5404          * Provision resource limits for Virtual Functions.  We currently
5405          * grant them all the same static resource limits except for the Port
5406          * Access Rights Mask which we're assigning based on the PF.  All of
5407          * the static provisioning stuff for both the PF and VF really needs
5408          * to be managed in a persistent manner for each device which the
5409          * firmware controls.
5410          */
5411         {
5412                 int pf, vf;
5413
5414                 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
5415                         if (num_vf[pf] <= 0)
5416                                 continue;
5417
5418                         /* VF numbering starts at 1! */
5419                         for (vf = 1; vf <= num_vf[pf]; vf++) {
5420                                 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5421                                                   pf, vf,
5422                                                   VFRES_NEQ, VFRES_NETHCTRL,
5423                                                   VFRES_NIQFLINT, VFRES_NIQ,
5424                                                   VFRES_TC, VFRES_NVI,
5425                                                   FW_PFVF_CMD_CMASK_MASK,
5426                                                   pfvfres_pmask(
5427                                                   adapter, pf, vf),
5428                                                   VFRES_NEXACTF,
5429                                                   VFRES_R_CAPS, VFRES_WX_CAPS);
5430                                 if (ret < 0)
5431                                         dev_warn(adapter->pdev_dev,
5432                                                  "failed to "\
5433                                                  "provision pf/vf=%d/%d; "
5434                                                  "err=%d\n", pf, vf, ret);
5435                         }
5436                 }
5437         }
5438 #endif
5439
5440         /*
5441          * Set up the default filter mode.  Later we'll want to implement this
5442          * via a firmware command, etc. ...  This needs to be done before the
5443          * firmare initialization command ...  If the selected set of fields
5444          * isn't equal to the default value, we'll need to make sure that the
5445          * field selections will fit in the 36-bit budget.
5446          */
5447         if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
5448                 int j, bits = 0;
5449
5450                 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5451                         switch (tp_vlan_pri_map & (1 << j)) {
5452                         case 0:
5453                                 /* compressed filter field not enabled */
5454                                 break;
5455                         case FCOE_MASK:
5456                                 bits +=  1;
5457                                 break;
5458                         case PORT_MASK:
5459                                 bits +=  3;
5460                                 break;
5461                         case VNIC_ID_MASK:
5462                                 bits += 17;
5463                                 break;
5464                         case VLAN_MASK:
5465                                 bits += 17;
5466                                 break;
5467                         case TOS_MASK:
5468                                 bits +=  8;
5469                                 break;
5470                         case PROTOCOL_MASK:
5471                                 bits +=  8;
5472                                 break;
5473                         case ETHERTYPE_MASK:
5474                                 bits += 16;
5475                                 break;
5476                         case MACMATCH_MASK:
5477                                 bits +=  9;
5478                                 break;
5479                         case MPSHITTYPE_MASK:
5480                                 bits +=  3;
5481                                 break;
5482                         case FRAGMENTATION_MASK:
5483                                 bits +=  1;
5484                                 break;
5485                         }
5486
5487                 if (bits > 36) {
5488                         dev_err(adapter->pdev_dev,
5489                                 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5490                                 " using %#x\n", tp_vlan_pri_map, bits,
5491                                 TP_VLAN_PRI_MAP_DEFAULT);
5492                         tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5493                 }
5494         }
5495         v = tp_vlan_pri_map;
5496         t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5497                           &v, 1, TP_VLAN_PRI_MAP);
5498
5499         /*
5500          * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5501          * to support any of the compressed filter fields above.  Newer
5502          * versions of the firmware do this automatically but it doesn't hurt
5503          * to set it here.  Meanwhile, we do _not_ need to set Lookup Every
5504          * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5505          * since the firmware automatically turns this on and off when we have
5506          * a non-zero number of filters active (since it does have a
5507          * performance impact).
5508          */
5509         if (tp_vlan_pri_map)
5510                 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5511                                  FIVETUPLELOOKUP_MASK,
5512                                  FIVETUPLELOOKUP_MASK);
5513
5514         /*
5515          * Tweak some settings.
5516          */
5517         t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5518                      RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5519                      PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5520                      KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5521
5522         /*
5523          * Get basic stuff going by issuing the Firmware Initialize command.
5524          * Note that this _must_ be after all PFVF commands ...
5525          */
5526         ret = t4_fw_initialize(adapter, adapter->mbox);
5527         if (ret < 0)
5528                 goto bye;
5529
5530         /*
5531          * Return successfully!
5532          */
5533         dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5534                  "driver parameters\n");
5535         return 0;
5536
5537         /*
5538          * Something bad happened.  Return the error ...
5539          */
5540 bye:
5541         return ret;
5542 }
5543
5544 static struct fw_info fw_info_array[] = {
5545         {
5546                 .chip = CHELSIO_T4,
5547                 .fs_name = FW4_CFNAME,
5548                 .fw_mod_name = FW4_FNAME,
5549                 .fw_hdr = {
5550                         .chip = FW_HDR_CHIP_T4,
5551                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5552                         .intfver_nic = FW_INTFVER(T4, NIC),
5553                         .intfver_vnic = FW_INTFVER(T4, VNIC),
5554                         .intfver_ri = FW_INTFVER(T4, RI),
5555                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5556                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
5557                 },
5558         }, {
5559                 .chip = CHELSIO_T5,
5560                 .fs_name = FW5_CFNAME,
5561                 .fw_mod_name = FW5_FNAME,
5562                 .fw_hdr = {
5563                         .chip = FW_HDR_CHIP_T5,
5564                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5565                         .intfver_nic = FW_INTFVER(T5, NIC),
5566                         .intfver_vnic = FW_INTFVER(T5, VNIC),
5567                         .intfver_ri = FW_INTFVER(T5, RI),
5568                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5569                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
5570                 },
5571         }
5572 };
5573
5574 static struct fw_info *find_fw_info(int chip)
5575 {
5576         int i;
5577
5578         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5579                 if (fw_info_array[i].chip == chip)
5580                         return &fw_info_array[i];
5581         }
5582         return NULL;
5583 }
5584
5585 /*
5586  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5587  */
5588 static int adap_init0(struct adapter *adap)
5589 {
5590         int ret;
5591         u32 v, port_vec;
5592         enum dev_state state;
5593         u32 params[7], val[7];
5594         struct fw_caps_config_cmd caps_cmd;
5595         int reset = 1;
5596
5597         /*
5598          * Contact FW, advertising Master capability (and potentially forcing
5599          * ourselves as the Master PF if our module parameter force_init is
5600          * set).
5601          */
5602         ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5603                           force_init ? MASTER_MUST : MASTER_MAY,
5604                           &state);
5605         if (ret < 0) {
5606                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5607                         ret);
5608                 return ret;
5609         }
5610         if (ret == adap->mbox)
5611                 adap->flags |= MASTER_PF;
5612         if (force_init && state == DEV_STATE_INIT)
5613                 state = DEV_STATE_UNINIT;
5614
5615         /*
5616          * If we're the Master PF Driver and the device is uninitialized,
5617          * then let's consider upgrading the firmware ...  (We always want
5618          * to check the firmware version number in order to A. get it for
5619          * later reporting and B. to warn if the currently loaded firmware
5620          * is excessively mismatched relative to the driver.)
5621          */
5622         t4_get_fw_version(adap, &adap->params.fw_vers);
5623         t4_get_tp_version(adap, &adap->params.tp_vers);
5624         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
5625                 struct fw_info *fw_info;
5626                 struct fw_hdr *card_fw;
5627                 const struct firmware *fw;
5628                 const u8 *fw_data = NULL;
5629                 unsigned int fw_size = 0;
5630
5631                 /* This is the firmware whose headers the driver was compiled
5632                  * against
5633                  */
5634                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5635                 if (fw_info == NULL) {
5636                         dev_err(adap->pdev_dev,
5637                                 "unable to get firmware info for chip %d.\n",
5638                                 CHELSIO_CHIP_VERSION(adap->params.chip));
5639                         return -EINVAL;
5640                 }
5641
5642                 /* allocate memory to read the header of the firmware on the
5643                  * card
5644                  */
5645                 card_fw = t4_alloc_mem(sizeof(*card_fw));
5646
5647                 /* Get FW from from /lib/firmware/ */
5648                 ret = request_firmware(&fw, fw_info->fw_mod_name,
5649                                        adap->pdev_dev);
5650                 if (ret < 0) {
5651                         dev_err(adap->pdev_dev,
5652                                 "unable to load firmware image %s, error %d\n",
5653                                 fw_info->fw_mod_name, ret);
5654                 } else {
5655                         fw_data = fw->data;
5656                         fw_size = fw->size;
5657                 }
5658
5659                 /* upgrade FW logic */
5660                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5661                                  state, &reset);
5662
5663                 /* Cleaning up */
5664                 if (fw != NULL)
5665                         release_firmware(fw);
5666                 t4_free_mem(card_fw);
5667
5668                 if (ret < 0)
5669                         goto bye;
5670         }
5671
5672         /*
5673          * Grab VPD parameters.  This should be done after we establish a
5674          * connection to the firmware since some of the VPD parameters
5675          * (notably the Core Clock frequency) are retrieved via requests to
5676          * the firmware.  On the other hand, we need these fairly early on
5677          * so we do this right after getting ahold of the firmware.
5678          */
5679         ret = get_vpd_params(adap, &adap->params.vpd);
5680         if (ret < 0)
5681                 goto bye;
5682
5683         /*
5684          * Find out what ports are available to us.  Note that we need to do
5685          * this before calling adap_init0_no_config() since it needs nports
5686          * and portvec ...
5687          */
5688         v =
5689             FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5690             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
5691         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
5692         if (ret < 0)
5693                 goto bye;
5694
5695         adap->params.nports = hweight32(port_vec);
5696         adap->params.portvec = port_vec;
5697
5698         /*
5699          * If the firmware is initialized already (and we're not forcing a
5700          * master initialization), note that we're living with existing
5701          * adapter parameters.  Otherwise, it's time to try initializing the
5702          * adapter ...
5703          */
5704         if (state == DEV_STATE_INIT) {
5705                 dev_info(adap->pdev_dev, "Coming up as %s: "\
5706                          "Adapter already initialized\n",
5707                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5708                 adap->flags |= USING_SOFT_PARAMS;
5709         } else {
5710                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5711                          "Initializing adapter\n");
5712                 /*
5713                  * If the firmware doesn't support Configuration
5714                  * Files warn user and exit,
5715                  */
5716                 if (ret < 0)
5717                         dev_warn(adap->pdev_dev, "Firmware doesn't support "
5718                                  "configuration file.\n");
5719                 if (force_old_init)
5720                         ret = adap_init0_no_config(adap, reset);
5721                 else {
5722                         /*
5723                          * Find out whether we're dealing with a version of
5724                          * the firmware which has configuration file support.
5725                          */
5726                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5727                                      FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5728                         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5729                                               params, val);
5730
5731                         /*
5732                          * If the firmware doesn't support Configuration
5733                          * Files, use the old Driver-based, hard-wired
5734                          * initialization.  Otherwise, try using the
5735                          * Configuration File support and fall back to the
5736                          * Driver-based initialization if there's no
5737                          * Configuration File found.
5738                          */
5739                         if (ret < 0)
5740                                 ret = adap_init0_no_config(adap, reset);
5741                         else {
5742                                 /*
5743                                  * The firmware provides us with a memory
5744                                  * buffer where we can load a Configuration
5745                                  * File from the host if we want to override
5746                                  * the Configuration File in flash.
5747                                  */
5748
5749                                 ret = adap_init0_config(adap, reset);
5750                                 if (ret == -ENOENT) {
5751                                         dev_info(adap->pdev_dev,
5752                                             "No Configuration File present "
5753                                             "on adapter. Using hard-wired "
5754                                             "configuration parameters.\n");
5755                                         ret = adap_init0_no_config(adap, reset);
5756                                 }
5757                         }
5758                 }
5759                 if (ret < 0) {
5760                         dev_err(adap->pdev_dev,
5761                                 "could not initialize adapter, error %d\n",
5762                                 -ret);
5763                         goto bye;
5764                 }
5765         }
5766
5767         /*
5768          * If we're living with non-hard-coded parameters (either from a
5769          * Firmware Configuration File or values programmed by a different PF
5770          * Driver), give the SGE code a chance to pull in anything that it
5771          * needs ...  Note that this must be called after we retrieve our VPD
5772          * parameters in order to know how to convert core ticks to seconds.
5773          */
5774         if (adap->flags & USING_SOFT_PARAMS) {
5775                 ret = t4_sge_init(adap);
5776                 if (ret < 0)
5777                         goto bye;
5778         }
5779
5780         if (is_bypass_device(adap->pdev->device))
5781                 adap->params.bypass = 1;
5782
5783         /*
5784          * Grab some of our basic fundamental operating parameters.
5785          */
5786 #define FW_PARAM_DEV(param) \
5787         (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5788         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5789
5790 #define FW_PARAM_PFVF(param) \
5791         FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5792         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)|  \
5793         FW_PARAMS_PARAM_Y(0) | \
5794         FW_PARAMS_PARAM_Z(0)
5795
5796         params[0] = FW_PARAM_PFVF(EQ_START);
5797         params[1] = FW_PARAM_PFVF(L2T_START);
5798         params[2] = FW_PARAM_PFVF(L2T_END);
5799         params[3] = FW_PARAM_PFVF(FILTER_START);
5800         params[4] = FW_PARAM_PFVF(FILTER_END);
5801         params[5] = FW_PARAM_PFVF(IQFLINT_START);
5802         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
5803         if (ret < 0)
5804                 goto bye;
5805         adap->sge.egr_start = val[0];
5806         adap->l2t_start = val[1];
5807         adap->l2t_end = val[2];
5808         adap->tids.ftid_base = val[3];
5809         adap->tids.nftids = val[4] - val[3] + 1;
5810         adap->sge.ingr_start = val[5];
5811
5812         /* query params related to active filter region */
5813         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5814         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5815         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5816         /* If Active filter size is set we enable establishing
5817          * offload connection through firmware work request
5818          */
5819         if ((val[0] != val[1]) && (ret >= 0)) {
5820                 adap->flags |= FW_OFLD_CONN;
5821                 adap->tids.aftid_base = val[0];
5822                 adap->tids.aftid_end = val[1];
5823         }
5824
5825         /* If we're running on newer firmware, let it know that we're
5826          * prepared to deal with encapsulated CPL messages.  Older
5827          * firmware won't understand this and we'll just get
5828          * unencapsulated messages ...
5829          */
5830         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5831         val[0] = 1;
5832         (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5833
5834         /*
5835          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5836          * capability.  Earlier versions of the firmware didn't have the
5837          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5838          * permission to use ULPTX MEMWRITE DSGL.
5839          */
5840         if (is_t4(adap->params.chip)) {
5841                 adap->params.ulptx_memwrite_dsgl = false;
5842         } else {
5843                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5844                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5845                                       1, params, val);
5846                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5847         }
5848
5849         /*
5850          * Get device capabilities so we can determine what resources we need
5851          * to manage.
5852          */
5853         memset(&caps_cmd, 0, sizeof(caps_cmd));
5854         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
5855                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
5856         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5857         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5858                          &caps_cmd);
5859         if (ret < 0)
5860                 goto bye;
5861
5862         if (caps_cmd.ofldcaps) {
5863                 /* query offload-related parameters */
5864                 params[0] = FW_PARAM_DEV(NTID);
5865                 params[1] = FW_PARAM_PFVF(SERVER_START);
5866                 params[2] = FW_PARAM_PFVF(SERVER_END);
5867                 params[3] = FW_PARAM_PFVF(TDDP_START);
5868                 params[4] = FW_PARAM_PFVF(TDDP_END);
5869                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5870                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5871                                       params, val);
5872                 if (ret < 0)
5873                         goto bye;
5874                 adap->tids.ntids = val[0];
5875                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5876                 adap->tids.stid_base = val[1];
5877                 adap->tids.nstids = val[2] - val[1] + 1;
5878                 /*
5879                  * Setup server filter region. Divide the availble filter
5880                  * region into two parts. Regular filters get 1/3rd and server
5881                  * filters get 2/3rd part. This is only enabled if workarond
5882                  * path is enabled.
5883                  * 1. For regular filters.
5884                  * 2. Server filter: This are special filters which are used
5885                  * to redirect SYN packets to offload queue.
5886                  */
5887                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5888                         adap->tids.sftid_base = adap->tids.ftid_base +
5889                                         DIV_ROUND_UP(adap->tids.nftids, 3);
5890                         adap->tids.nsftids = adap->tids.nftids -
5891                                          DIV_ROUND_UP(adap->tids.nftids, 3);
5892                         adap->tids.nftids = adap->tids.sftid_base -
5893                                                 adap->tids.ftid_base;
5894                 }
5895                 adap->vres.ddp.start = val[3];
5896                 adap->vres.ddp.size = val[4] - val[3] + 1;
5897                 adap->params.ofldq_wr_cred = val[5];
5898
5899                 adap->params.offload = 1;
5900         }
5901         if (caps_cmd.rdmacaps) {
5902                 params[0] = FW_PARAM_PFVF(STAG_START);
5903                 params[1] = FW_PARAM_PFVF(STAG_END);
5904                 params[2] = FW_PARAM_PFVF(RQ_START);
5905                 params[3] = FW_PARAM_PFVF(RQ_END);
5906                 params[4] = FW_PARAM_PFVF(PBL_START);
5907                 params[5] = FW_PARAM_PFVF(PBL_END);
5908                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5909                                       params, val);
5910                 if (ret < 0)
5911                         goto bye;
5912                 adap->vres.stag.start = val[0];
5913                 adap->vres.stag.size = val[1] - val[0] + 1;
5914                 adap->vres.rq.start = val[2];
5915                 adap->vres.rq.size = val[3] - val[2] + 1;
5916                 adap->vres.pbl.start = val[4];
5917                 adap->vres.pbl.size = val[5] - val[4] + 1;
5918
5919                 params[0] = FW_PARAM_PFVF(SQRQ_START);
5920                 params[1] = FW_PARAM_PFVF(SQRQ_END);
5921                 params[2] = FW_PARAM_PFVF(CQ_START);
5922                 params[3] = FW_PARAM_PFVF(CQ_END);
5923                 params[4] = FW_PARAM_PFVF(OCQ_START);
5924                 params[5] = FW_PARAM_PFVF(OCQ_END);
5925                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
5926                                       val);
5927                 if (ret < 0)
5928                         goto bye;
5929                 adap->vres.qp.start = val[0];
5930                 adap->vres.qp.size = val[1] - val[0] + 1;
5931                 adap->vres.cq.start = val[2];
5932                 adap->vres.cq.size = val[3] - val[2] + 1;
5933                 adap->vres.ocq.start = val[4];
5934                 adap->vres.ocq.size = val[5] - val[4] + 1;
5935
5936                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
5937                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
5938                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
5939                                       val);
5940                 if (ret < 0) {
5941                         adap->params.max_ordird_qp = 8;
5942                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
5943                         ret = 0;
5944                 } else {
5945                         adap->params.max_ordird_qp = val[0];
5946                         adap->params.max_ird_adapter = val[1];
5947                 }
5948                 dev_info(adap->pdev_dev,
5949                          "max_ordird_qp %d max_ird_adapter %d\n",
5950                          adap->params.max_ordird_qp,
5951                          adap->params.max_ird_adapter);
5952         }
5953         if (caps_cmd.iscsicaps) {
5954                 params[0] = FW_PARAM_PFVF(ISCSI_START);
5955                 params[1] = FW_PARAM_PFVF(ISCSI_END);
5956                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5957                                       params, val);
5958                 if (ret < 0)
5959                         goto bye;
5960                 adap->vres.iscsi.start = val[0];
5961                 adap->vres.iscsi.size = val[1] - val[0] + 1;
5962         }
5963 #undef FW_PARAM_PFVF
5964 #undef FW_PARAM_DEV
5965
5966         /* The MTU/MSS Table is initialized by now, so load their values.  If
5967          * we're initializing the adapter, then we'll make any modifications
5968          * we want to the MTU/MSS Table and also initialize the congestion
5969          * parameters.
5970          */
5971         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5972         if (state != DEV_STATE_INIT) {
5973                 int i;
5974
5975                 /* The default MTU Table contains values 1492 and 1500.
5976                  * However, for TCP, it's better to have two values which are
5977                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5978                  * This allows us to have a TCP Data Payload which is a
5979                  * multiple of 8 regardless of what combination of TCP Options
5980                  * are in use (always a multiple of 4 bytes) which is
5981                  * important for performance reasons.  For instance, if no
5982                  * options are in use, then we have a 20-byte IP header and a
5983                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
5984                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5985                  * which is not a multiple of 8.  So using an MSS of 1488 in
5986                  * this case results in a TCP Data Payload of 1448 bytes which
5987                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
5988                  * Stamps have been negotiated, then an MTU of 1500 bytes
5989                  * results in a TCP Data Payload of 1448 bytes which, as
5990                  * above, is a multiple of 8 bytes ...
5991                  */
5992                 for (i = 0; i < NMTUS; i++)
5993                         if (adap->params.mtus[i] == 1492) {
5994                                 adap->params.mtus[i] = 1488;
5995                                 break;
5996                         }
5997
5998                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5999                              adap->params.b_wnd);
6000         }
6001         t4_init_tp_params(adap);
6002         adap->flags |= FW_OK;
6003         return 0;
6004
6005         /*
6006          * Something bad happened.  If a command timed out or failed with EIO
6007          * FW does not operate within its spec or something catastrophic
6008          * happened to HW/FW, stop issuing commands.
6009          */
6010 bye:
6011         if (ret != -ETIMEDOUT && ret != -EIO)
6012                 t4_fw_bye(adap, adap->mbox);
6013         return ret;
6014 }
6015
6016 /* EEH callbacks */
6017
6018 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
6019                                          pci_channel_state_t state)
6020 {
6021         int i;
6022         struct adapter *adap = pci_get_drvdata(pdev);
6023
6024         if (!adap)
6025                 goto out;
6026
6027         rtnl_lock();
6028         adap->flags &= ~FW_OK;
6029         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
6030         spin_lock(&adap->stats_lock);
6031         for_each_port(adap, i) {
6032                 struct net_device *dev = adap->port[i];
6033
6034                 netif_device_detach(dev);
6035                 netif_carrier_off(dev);
6036         }
6037         spin_unlock(&adap->stats_lock);
6038         if (adap->flags & FULL_INIT_DONE)
6039                 cxgb_down(adap);
6040         rtnl_unlock();
6041         if ((adap->flags & DEV_ENABLED)) {
6042                 pci_disable_device(pdev);
6043                 adap->flags &= ~DEV_ENABLED;
6044         }
6045 out:    return state == pci_channel_io_perm_failure ?
6046                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
6047 }
6048
6049 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
6050 {
6051         int i, ret;
6052         struct fw_caps_config_cmd c;
6053         struct adapter *adap = pci_get_drvdata(pdev);
6054
6055         if (!adap) {
6056                 pci_restore_state(pdev);
6057                 pci_save_state(pdev);
6058                 return PCI_ERS_RESULT_RECOVERED;
6059         }
6060
6061         if (!(adap->flags & DEV_ENABLED)) {
6062                 if (pci_enable_device(pdev)) {
6063                         dev_err(&pdev->dev, "Cannot reenable PCI "
6064                                             "device after reset\n");
6065                         return PCI_ERS_RESULT_DISCONNECT;
6066                 }
6067                 adap->flags |= DEV_ENABLED;
6068         }
6069
6070         pci_set_master(pdev);
6071         pci_restore_state(pdev);
6072         pci_save_state(pdev);
6073         pci_cleanup_aer_uncorrect_error_status(pdev);
6074
6075         if (t4_wait_dev_ready(adap->regs) < 0)
6076                 return PCI_ERS_RESULT_DISCONNECT;
6077         if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
6078                 return PCI_ERS_RESULT_DISCONNECT;
6079         adap->flags |= FW_OK;
6080         if (adap_init1(adap, &c))
6081                 return PCI_ERS_RESULT_DISCONNECT;
6082
6083         for_each_port(adap, i) {
6084                 struct port_info *p = adap2pinfo(adap, i);
6085
6086                 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
6087                                   NULL, NULL);
6088                 if (ret < 0)
6089                         return PCI_ERS_RESULT_DISCONNECT;
6090                 p->viid = ret;
6091                 p->xact_addr_filt = -1;
6092         }
6093
6094         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
6095                      adap->params.b_wnd);
6096         setup_memwin(adap);
6097         if (cxgb_up(adap))
6098                 return PCI_ERS_RESULT_DISCONNECT;
6099         return PCI_ERS_RESULT_RECOVERED;
6100 }
6101
6102 static void eeh_resume(struct pci_dev *pdev)
6103 {
6104         int i;
6105         struct adapter *adap = pci_get_drvdata(pdev);
6106
6107         if (!adap)
6108                 return;
6109
6110         rtnl_lock();
6111         for_each_port(adap, i) {
6112                 struct net_device *dev = adap->port[i];
6113
6114                 if (netif_running(dev)) {
6115                         link_start(dev);
6116                         cxgb_set_rxmode(dev);
6117                 }
6118                 netif_device_attach(dev);
6119         }
6120         rtnl_unlock();
6121 }
6122
6123 static const struct pci_error_handlers cxgb4_eeh = {
6124         .error_detected = eeh_err_detected,
6125         .slot_reset     = eeh_slot_reset,
6126         .resume         = eeh_resume,
6127 };
6128
6129 static inline bool is_x_10g_port(const struct link_config *lc)
6130 {
6131         return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6132                (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
6133 }
6134
6135 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6136                              unsigned int us, unsigned int cnt,
6137                              unsigned int size, unsigned int iqe_size)
6138 {
6139         q->adap = adap;
6140         set_rspq_intr_params(q, us, cnt);
6141         q->iqe_len = iqe_size;
6142         q->size = size;
6143 }
6144
6145 /*
6146  * Perform default configuration of DMA queues depending on the number and type
6147  * of ports we found and the number of available CPUs.  Most settings can be
6148  * modified by the admin prior to actual use.
6149  */
6150 static void cfg_queues(struct adapter *adap)
6151 {
6152         struct sge *s = &adap->sge;
6153         int i, n10g = 0, qidx = 0;
6154 #ifndef CONFIG_CHELSIO_T4_DCB
6155         int q10g = 0;
6156 #endif
6157         int ciq_size;
6158
6159         for_each_port(adap, i)
6160                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
6161 #ifdef CONFIG_CHELSIO_T4_DCB
6162         /* For Data Center Bridging support we need to be able to support up
6163          * to 8 Traffic Priorities; each of which will be assigned to its
6164          * own TX Queue in order to prevent Head-Of-Line Blocking.
6165          */
6166         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6167                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6168                         MAX_ETH_QSETS, adap->params.nports * 8);
6169                 BUG_ON(1);
6170         }
6171
6172         for_each_port(adap, i) {
6173                 struct port_info *pi = adap2pinfo(adap, i);
6174
6175                 pi->first_qset = qidx;
6176                 pi->nqsets = 8;
6177                 qidx += pi->nqsets;
6178         }
6179 #else /* !CONFIG_CHELSIO_T4_DCB */
6180         /*
6181          * We default to 1 queue per non-10G port and up to # of cores queues
6182          * per 10G port.
6183          */
6184         if (n10g)
6185                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
6186         if (q10g > netif_get_num_default_rss_queues())
6187                 q10g = netif_get_num_default_rss_queues();
6188
6189         for_each_port(adap, i) {
6190                 struct port_info *pi = adap2pinfo(adap, i);
6191
6192                 pi->first_qset = qidx;
6193                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
6194                 qidx += pi->nqsets;
6195         }
6196 #endif /* !CONFIG_CHELSIO_T4_DCB */
6197
6198         s->ethqsets = qidx;
6199         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
6200
6201         if (is_offload(adap)) {
6202                 /*
6203                  * For offload we use 1 queue/channel if all ports are up to 1G,
6204                  * otherwise we divide all available queues amongst the channels
6205                  * capped by the number of available cores.
6206                  */
6207                 if (n10g) {
6208                         i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6209                                   num_online_cpus());
6210                         s->ofldqsets = roundup(i, adap->params.nports);
6211                 } else
6212                         s->ofldqsets = adap->params.nports;
6213                 /* For RDMA one Rx queue per channel suffices */
6214                 s->rdmaqs = adap->params.nports;
6215                 s->rdmaciqs = adap->params.nports;
6216         }
6217
6218         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6219                 struct sge_eth_rxq *r = &s->ethrxq[i];
6220
6221                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
6222                 r->fl.size = 72;
6223         }
6224
6225         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6226                 s->ethtxq[i].q.size = 1024;
6227
6228         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6229                 s->ctrlq[i].q.size = 512;
6230
6231         for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6232                 s->ofldtxq[i].q.size = 1024;
6233
6234         for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6235                 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6236
6237                 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
6238                 r->rspq.uld = CXGB4_ULD_ISCSI;
6239                 r->fl.size = 72;
6240         }
6241
6242         for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6243                 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6244
6245                 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
6246                 r->rspq.uld = CXGB4_ULD_RDMA;
6247                 r->fl.size = 72;
6248         }
6249
6250         ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6251         if (ciq_size > SGE_MAX_IQ_SIZE) {
6252                 CH_WARN(adap, "CIQ size too small for available IQs\n");
6253                 ciq_size = SGE_MAX_IQ_SIZE;
6254         }
6255
6256         for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6257                 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6258
6259                 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
6260                 r->rspq.uld = CXGB4_ULD_RDMA;
6261         }
6262
6263         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6264         init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
6265 }
6266
6267 /*
6268  * Reduce the number of Ethernet queues across all ports to at most n.
6269  * n provides at least one queue per port.
6270  */
6271 static void reduce_ethqs(struct adapter *adap, int n)
6272 {
6273         int i;
6274         struct port_info *pi;
6275
6276         while (n < adap->sge.ethqsets)
6277                 for_each_port(adap, i) {
6278                         pi = adap2pinfo(adap, i);
6279                         if (pi->nqsets > 1) {
6280                                 pi->nqsets--;
6281                                 adap->sge.ethqsets--;
6282                                 if (adap->sge.ethqsets <= n)
6283                                         break;
6284                         }
6285                 }
6286
6287         n = 0;
6288         for_each_port(adap, i) {
6289                 pi = adap2pinfo(adap, i);
6290                 pi->first_qset = n;
6291                 n += pi->nqsets;
6292         }
6293 }
6294
6295 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6296 #define EXTRA_VECS 2
6297
6298 static int enable_msix(struct adapter *adap)
6299 {
6300         int ofld_need = 0;
6301         int i, want, need;
6302         struct sge *s = &adap->sge;
6303         unsigned int nchan = adap->params.nports;
6304         struct msix_entry entries[MAX_INGQ + 1];
6305
6306         for (i = 0; i < ARRAY_SIZE(entries); ++i)
6307                 entries[i].entry = i;
6308
6309         want = s->max_ethqsets + EXTRA_VECS;
6310         if (is_offload(adap)) {
6311                 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
6312                 /* need nchan for each possible ULD */
6313                 ofld_need = 3 * nchan;
6314         }
6315 #ifdef CONFIG_CHELSIO_T4_DCB
6316         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6317          * each port.
6318          */
6319         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6320 #else
6321         need = adap->params.nports + EXTRA_VECS + ofld_need;
6322 #endif
6323         want = pci_enable_msix_range(adap->pdev, entries, need, want);
6324         if (want < 0)
6325                 return want;
6326
6327         /*
6328          * Distribute available vectors to the various queue groups.
6329          * Every group gets its minimum requirement and NIC gets top
6330          * priority for leftovers.
6331          */
6332         i = want - EXTRA_VECS - ofld_need;
6333         if (i < s->max_ethqsets) {
6334                 s->max_ethqsets = i;
6335                 if (i < s->ethqsets)
6336                         reduce_ethqs(adap, i);
6337         }
6338         if (is_offload(adap)) {
6339                 i = want - EXTRA_VECS - s->max_ethqsets;
6340                 i -= ofld_need - nchan;
6341                 s->ofldqsets = (i / nchan) * nchan;  /* round down */
6342         }
6343         for (i = 0; i < want; ++i)
6344                 adap->msix_info[i].vec = entries[i].vector;
6345
6346         return 0;
6347 }
6348
6349 #undef EXTRA_VECS
6350
6351 static int init_rss(struct adapter *adap)
6352 {
6353         unsigned int i, j;
6354
6355         for_each_port(adap, i) {
6356                 struct port_info *pi = adap2pinfo(adap, i);
6357
6358                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6359                 if (!pi->rss)
6360                         return -ENOMEM;
6361                 for (j = 0; j < pi->rss_size; j++)
6362                         pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
6363         }
6364         return 0;
6365 }
6366
6367 static void print_port_info(const struct net_device *dev)
6368 {
6369         char buf[80];
6370         char *bufp = buf;
6371         const char *spd = "";
6372         const struct port_info *pi = netdev_priv(dev);
6373         const struct adapter *adap = pi->adapter;
6374
6375         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6376                 spd = " 2.5 GT/s";
6377         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6378                 spd = " 5 GT/s";
6379         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6380                 spd = " 8 GT/s";
6381
6382         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6383                 bufp += sprintf(bufp, "100/");
6384         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6385                 bufp += sprintf(bufp, "1000/");
6386         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6387                 bufp += sprintf(bufp, "10G/");
6388         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6389                 bufp += sprintf(bufp, "40G/");
6390         if (bufp != buf)
6391                 --bufp;
6392         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
6393
6394         netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6395                     adap->params.vpd.id,
6396                     CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
6397                     is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6398                     (adap->flags & USING_MSIX) ? " MSI-X" :
6399                     (adap->flags & USING_MSI) ? " MSI" : "");
6400         netdev_info(dev, "S/N: %s, P/N: %s\n",
6401                     adap->params.vpd.sn, adap->params.vpd.pn);
6402 }
6403
6404 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
6405 {
6406         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
6407 }
6408
6409 /*
6410  * Free the following resources:
6411  * - memory used for tables
6412  * - MSI/MSI-X
6413  * - net devices
6414  * - resources FW is holding for us
6415  */
6416 static void free_some_resources(struct adapter *adapter)
6417 {
6418         unsigned int i;
6419
6420         t4_free_mem(adapter->l2t);
6421         t4_free_mem(adapter->tids.tid_tab);
6422         disable_msi(adapter);
6423
6424         for_each_port(adapter, i)
6425                 if (adapter->port[i]) {
6426                         kfree(adap2pinfo(adapter, i)->rss);
6427                         free_netdev(adapter->port[i]);
6428                 }
6429         if (adapter->flags & FW_OK)
6430                 t4_fw_bye(adapter, adapter->fn);
6431 }
6432
6433 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6434 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6435                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6436 #define SEGMENT_SIZE 128
6437
6438 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6439 {
6440         int func, i, err, s_qpp, qpp, num_seg;
6441         struct port_info *pi;
6442         bool highdma = false;
6443         struct adapter *adapter = NULL;
6444         void __iomem *regs;
6445
6446         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6447
6448         err = pci_request_regions(pdev, KBUILD_MODNAME);
6449         if (err) {
6450                 /* Just info, some other driver may have claimed the device. */
6451                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6452                 return err;
6453         }
6454
6455         err = pci_enable_device(pdev);
6456         if (err) {
6457                 dev_err(&pdev->dev, "cannot enable PCI device\n");
6458                 goto out_release_regions;
6459         }
6460
6461         regs = pci_ioremap_bar(pdev, 0);
6462         if (!regs) {
6463                 dev_err(&pdev->dev, "cannot map device registers\n");
6464                 err = -ENOMEM;
6465                 goto out_disable_device;
6466         }
6467
6468         err = t4_wait_dev_ready(regs);
6469         if (err < 0)
6470                 goto out_unmap_bar0;
6471
6472         /* We control everything through one PF */
6473         func = SOURCEPF_GET(readl(regs + PL_WHOAMI));
6474         if (func != ent->driver_data) {
6475                 iounmap(regs);
6476                 pci_disable_device(pdev);
6477                 pci_save_state(pdev);        /* to restore SR-IOV later */
6478                 goto sriov;
6479         }
6480
6481         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6482                 highdma = true;
6483                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6484                 if (err) {
6485                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6486                                 "coherent allocations\n");
6487                         goto out_unmap_bar0;
6488                 }
6489         } else {
6490                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6491                 if (err) {
6492                         dev_err(&pdev->dev, "no usable DMA configuration\n");
6493                         goto out_unmap_bar0;
6494                 }
6495         }
6496
6497         pci_enable_pcie_error_reporting(pdev);
6498         enable_pcie_relaxed_ordering(pdev);
6499         pci_set_master(pdev);
6500         pci_save_state(pdev);
6501
6502         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6503         if (!adapter) {
6504                 err = -ENOMEM;
6505                 goto out_unmap_bar0;
6506         }
6507
6508         adapter->workq = create_singlethread_workqueue("cxgb4");
6509         if (!adapter->workq) {
6510                 err = -ENOMEM;
6511                 goto out_free_adapter;
6512         }
6513
6514         /* PCI device has been enabled */
6515         adapter->flags |= DEV_ENABLED;
6516
6517         adapter->regs = regs;
6518         adapter->pdev = pdev;
6519         adapter->pdev_dev = &pdev->dev;
6520         adapter->mbox = func;
6521         adapter->fn = func;
6522         adapter->msg_enable = dflt_msg_enable;
6523         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6524
6525         spin_lock_init(&adapter->stats_lock);
6526         spin_lock_init(&adapter->tid_release_lock);
6527         spin_lock_init(&adapter->win0_lock);
6528
6529         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6530         INIT_WORK(&adapter->db_full_task, process_db_full);
6531         INIT_WORK(&adapter->db_drop_task, process_db_drop);
6532
6533         err = t4_prep_adapter(adapter);
6534         if (err)
6535                 goto out_free_adapter;
6536
6537
6538         if (!is_t4(adapter->params.chip)) {
6539                 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6540                 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6541                       SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6542                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6543
6544                 /* Each segment size is 128B. Write coalescing is enabled only
6545                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6546                  * queue is less no of segments that can be accommodated in
6547                  * a page size.
6548                  */
6549                 if (qpp > num_seg) {
6550                         dev_err(&pdev->dev,
6551                                 "Incorrect number of egress queues per page\n");
6552                         err = -EINVAL;
6553                         goto out_free_adapter;
6554                 }
6555                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6556                 pci_resource_len(pdev, 2));
6557                 if (!adapter->bar2) {
6558                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
6559                         err = -ENOMEM;
6560                         goto out_free_adapter;
6561                 }
6562         }
6563
6564         setup_memwin(adapter);
6565         err = adap_init0(adapter);
6566         setup_memwin_rdma(adapter);
6567         if (err)
6568                 goto out_unmap_bar;
6569
6570         for_each_port(adapter, i) {
6571                 struct net_device *netdev;
6572
6573                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6574                                            MAX_ETH_QSETS);
6575                 if (!netdev) {
6576                         err = -ENOMEM;
6577                         goto out_free_dev;
6578                 }
6579
6580                 SET_NETDEV_DEV(netdev, &pdev->dev);
6581
6582                 adapter->port[i] = netdev;
6583                 pi = netdev_priv(netdev);
6584                 pi->adapter = adapter;
6585                 pi->xact_addr_filt = -1;
6586                 pi->port_id = i;
6587                 netdev->irq = pdev->irq;
6588
6589                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6590                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6591                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
6592                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6593                 if (highdma)
6594                         netdev->hw_features |= NETIF_F_HIGHDMA;
6595                 netdev->features |= netdev->hw_features;
6596                 netdev->vlan_features = netdev->features & VLAN_FEAT;
6597
6598                 netdev->priv_flags |= IFF_UNICAST_FLT;
6599
6600                 netdev->netdev_ops = &cxgb4_netdev_ops;
6601 #ifdef CONFIG_CHELSIO_T4_DCB
6602                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6603                 cxgb4_dcb_state_init(netdev);
6604 #endif
6605                 netdev->ethtool_ops = &cxgb_ethtool_ops;
6606         }
6607
6608         pci_set_drvdata(pdev, adapter);
6609
6610         if (adapter->flags & FW_OK) {
6611                 err = t4_port_init(adapter, func, func, 0);
6612                 if (err)
6613                         goto out_free_dev;
6614         }
6615
6616         /*
6617          * Configure queues and allocate tables now, they can be needed as
6618          * soon as the first register_netdev completes.
6619          */
6620         cfg_queues(adapter);
6621
6622         adapter->l2t = t4_init_l2t();
6623         if (!adapter->l2t) {
6624                 /* We tolerate a lack of L2T, giving up some functionality */
6625                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6626                 adapter->params.offload = 0;
6627         }
6628
6629         if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6630                 dev_warn(&pdev->dev, "could not allocate TID table, "
6631                          "continuing\n");
6632                 adapter->params.offload = 0;
6633         }
6634
6635         /* See what interrupts we'll be using */
6636         if (msi > 1 && enable_msix(adapter) == 0)
6637                 adapter->flags |= USING_MSIX;
6638         else if (msi > 0 && pci_enable_msi(pdev) == 0)
6639                 adapter->flags |= USING_MSI;
6640
6641         err = init_rss(adapter);
6642         if (err)
6643                 goto out_free_dev;
6644
6645         /*
6646          * The card is now ready to go.  If any errors occur during device
6647          * registration we do not fail the whole card but rather proceed only
6648          * with the ports we manage to register successfully.  However we must
6649          * register at least one net device.
6650          */
6651         for_each_port(adapter, i) {
6652                 pi = adap2pinfo(adapter, i);
6653                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6654                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6655
6656                 err = register_netdev(adapter->port[i]);
6657                 if (err)
6658                         break;
6659                 adapter->chan_map[pi->tx_chan] = i;
6660                 print_port_info(adapter->port[i]);
6661         }
6662         if (i == 0) {
6663                 dev_err(&pdev->dev, "could not register any net devices\n");
6664                 goto out_free_dev;
6665         }
6666         if (err) {
6667                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6668                 err = 0;
6669         }
6670
6671         if (cxgb4_debugfs_root) {
6672                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6673                                                            cxgb4_debugfs_root);
6674                 setup_debugfs(adapter);
6675         }
6676
6677         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6678         pdev->needs_freset = 1;
6679
6680         if (is_offload(adapter))
6681                 attach_ulds(adapter);
6682
6683 sriov:
6684 #ifdef CONFIG_PCI_IOV
6685         if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
6686                 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6687                         dev_info(&pdev->dev,
6688                                  "instantiated %u virtual functions\n",
6689                                  num_vf[func]);
6690 #endif
6691         return 0;
6692
6693  out_free_dev:
6694         free_some_resources(adapter);
6695  out_unmap_bar:
6696         if (!is_t4(adapter->params.chip))
6697                 iounmap(adapter->bar2);
6698  out_free_adapter:
6699         if (adapter->workq)
6700                 destroy_workqueue(adapter->workq);
6701
6702         kfree(adapter);
6703  out_unmap_bar0:
6704         iounmap(regs);
6705  out_disable_device:
6706         pci_disable_pcie_error_reporting(pdev);
6707         pci_disable_device(pdev);
6708  out_release_regions:
6709         pci_release_regions(pdev);
6710         return err;
6711 }
6712
6713 static void remove_one(struct pci_dev *pdev)
6714 {
6715         struct adapter *adapter = pci_get_drvdata(pdev);
6716
6717 #ifdef CONFIG_PCI_IOV
6718         pci_disable_sriov(pdev);
6719
6720 #endif
6721
6722         if (adapter) {
6723                 int i;
6724
6725                 /* Tear down per-adapter Work Queue first since it can contain
6726                  * references to our adapter data structure.
6727                  */
6728                 destroy_workqueue(adapter->workq);
6729
6730                 if (is_offload(adapter))
6731                         detach_ulds(adapter);
6732
6733                 for_each_port(adapter, i)
6734                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6735                                 unregister_netdev(adapter->port[i]);
6736
6737                 debugfs_remove_recursive(adapter->debugfs_root);
6738
6739                 /* If we allocated filters, free up state associated with any
6740                  * valid filters ...
6741                  */
6742                 if (adapter->tids.ftid_tab) {
6743                         struct filter_entry *f = &adapter->tids.ftid_tab[0];
6744                         for (i = 0; i < (adapter->tids.nftids +
6745                                         adapter->tids.nsftids); i++, f++)
6746                                 if (f->valid)
6747                                         clear_filter(adapter, f);
6748                 }
6749
6750                 if (adapter->flags & FULL_INIT_DONE)
6751                         cxgb_down(adapter);
6752
6753                 free_some_resources(adapter);
6754                 iounmap(adapter->regs);
6755                 if (!is_t4(adapter->params.chip))
6756                         iounmap(adapter->bar2);
6757                 pci_disable_pcie_error_reporting(pdev);
6758                 if ((adapter->flags & DEV_ENABLED)) {
6759                         pci_disable_device(pdev);
6760                         adapter->flags &= ~DEV_ENABLED;
6761                 }
6762                 pci_release_regions(pdev);
6763                 synchronize_rcu();
6764                 kfree(adapter);
6765         } else
6766                 pci_release_regions(pdev);
6767 }
6768
6769 static struct pci_driver cxgb4_driver = {
6770         .name     = KBUILD_MODNAME,
6771         .id_table = cxgb4_pci_tbl,
6772         .probe    = init_one,
6773         .remove   = remove_one,
6774         .shutdown = remove_one,
6775         .err_handler = &cxgb4_eeh,
6776 };
6777
6778 static int __init cxgb4_init_module(void)
6779 {
6780         int ret;
6781
6782         /* Debugfs support is optional, just warn if this fails */
6783         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6784         if (!cxgb4_debugfs_root)
6785                 pr_warn("could not create debugfs entry, continuing\n");
6786
6787         ret = pci_register_driver(&cxgb4_driver);
6788         if (ret < 0)
6789                 debugfs_remove(cxgb4_debugfs_root);
6790
6791 #if IS_ENABLED(CONFIG_IPV6)
6792         register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6793 #endif
6794
6795         return ret;
6796 }
6797
6798 static void __exit cxgb4_cleanup_module(void)
6799 {
6800 #if IS_ENABLED(CONFIG_IPV6)
6801         unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6802 #endif
6803         pci_unregister_driver(&cxgb4_driver);
6804         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6805 }
6806
6807 module_init(cxgb4_init_module);
6808 module_exit(cxgb4_cleanup_module);