drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed sucessfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_INV_LSTAG_WR             = 0x1a,
 104         FW_LASTC2E_WR                  = 0x40
 105 };
 106
 107 struct fw_wr_hdr {
 108         __be32 hi;
 109         __be32 lo;
 110 };
 111
 112 /* work request opcode (hi) */
 113 #define FW_WR_OP_S      24
 114 #define FW_WR_OP_M      0xff
 115 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 116 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 117
 118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 119 #define FW_WR_ATOMIC_S          23
 120 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 121
 122 /* flush flag (hi) - firmware flushes flushable work request buffered
 123  * in the flow context.
 124  */
 125 #define FW_WR_FLUSH_S     22
 126 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 127
 128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 129 #define FW_WR_COMPL_S     21
 130 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 131 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 132
 133 /* work request immediate data length (hi) */
 134 #define FW_WR_IMMDLEN_S 0
 135 #define FW_WR_IMMDLEN_M 0xff
 136 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 137
 138 /* egress queue status update to associated ingress queue entry (lo) */
 139 #define FW_WR_EQUIQ_S           31
 140 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 141 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 142
 143 /* egress queue status update to egress queue status entry (lo) */
 144 #define FW_WR_EQUEQ_S           30
 145 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 146 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 147
 148 /* flow context identifier (lo) */
 149 #define FW_WR_FLOWID_S          8
 150 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 151
 152 /* length in units of 16-bytes (lo) */
 153 #define FW_WR_LEN16_S           0
 154 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 155
 156 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 157 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 158
 159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 160 enum fw_filter_wr_cookie {
 161         FW_FILTER_WR_SUCCESS,
 162         FW_FILTER_WR_FLT_ADDED,
 163         FW_FILTER_WR_FLT_DELETED,
 164         FW_FILTER_WR_SMT_TBL_FULL,
 165         FW_FILTER_WR_EINVAL,
 166 };
 167
 168 struct fw_filter_wr {
 169         __be32 op_pkd;
 170         __be32 len16_pkd;
 171         __be64 r3;
 172         __be32 tid_to_iq;
 173         __be32 del_filter_to_l2tix;
 174         __be16 ethtype;
 175         __be16 ethtypem;
 176         __u8   frag_to_ovlan_vldm;
 177         __u8   smac_sel;
 178         __be16 rx_chan_rx_rpl_iq;
 179         __be32 maci_to_matchtypem;
 180         __u8   ptcl;
 181         __u8   ptclm;
 182         __u8   ttyp;
 183         __u8   ttypm;
 184         __be16 ivlan;
 185         __be16 ivlanm;
 186         __be16 ovlan;
 187         __be16 ovlanm;
 188         __u8   lip[16];
 189         __u8   lipm[16];
 190         __u8   fip[16];
 191         __u8   fipm[16];
 192         __be16 lp;
 193         __be16 lpm;
 194         __be16 fp;
 195         __be16 fpm;
 196         __be16 r7;
 197         __u8   sma[6];
 198 };
 199
 200 #define FW_FILTER_WR_TID_S      12
 201 #define FW_FILTER_WR_TID_M      0xfffff
 202 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 203 #define FW_FILTER_WR_TID_G(x)   \
 204         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 205
 206 #define FW_FILTER_WR_RQTYPE_S           11
 207 #define FW_FILTER_WR_RQTYPE_M           0x1
 208 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 209 #define FW_FILTER_WR_RQTYPE_G(x)        \
 210         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 211 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 212
 213 #define FW_FILTER_WR_NOREPLY_S          10
 214 #define FW_FILTER_WR_NOREPLY_M          0x1
 215 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 216 #define FW_FILTER_WR_NOREPLY_G(x)       \
 217         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 218 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 219
 220 #define FW_FILTER_WR_IQ_S       0
 221 #define FW_FILTER_WR_IQ_M       0x3ff
 222 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 223 #define FW_FILTER_WR_IQ_G(x)    \
 224         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 225
 226 #define FW_FILTER_WR_DEL_FILTER_S       31
 227 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 228 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 229 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 230         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 231 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 232
 233 #define FW_FILTER_WR_RPTTID_S           25
 234 #define FW_FILTER_WR_RPTTID_M           0x1
 235 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 236 #define FW_FILTER_WR_RPTTID_G(x)        \
 237         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 238 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 239
 240 #define FW_FILTER_WR_DROP_S     24
 241 #define FW_FILTER_WR_DROP_M     0x1
 242 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 243 #define FW_FILTER_WR_DROP_G(x)  \
 244         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 245 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 246
 247 #define FW_FILTER_WR_DIRSTEER_S         23
 248 #define FW_FILTER_WR_DIRSTEER_M         0x1
 249 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 250 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 251         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 253
 254 #define FW_FILTER_WR_MASKHASH_S         22
 255 #define FW_FILTER_WR_MASKHASH_M         0x1
 256 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 257 #define FW_FILTER_WR_MASKHASH_G(x)      \
 258         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 260
 261 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 262 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 263 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 264 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 265         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 266 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 267
 268 #define FW_FILTER_WR_LPBK_S     20
 269 #define FW_FILTER_WR_LPBK_M     0x1
 270 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 271 #define FW_FILTER_WR_LPBK_G(x)  \
 272         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 273 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 274
 275 #define FW_FILTER_WR_DMAC_S     19
 276 #define FW_FILTER_WR_DMAC_M     0x1
 277 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 278 #define FW_FILTER_WR_DMAC_G(x)  \
 279         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 280 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 281
 282 #define FW_FILTER_WR_SMAC_S     18
 283 #define FW_FILTER_WR_SMAC_M     0x1
 284 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 285 #define FW_FILTER_WR_SMAC_G(x)  \
 286         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 287 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 288
 289 #define FW_FILTER_WR_INSVLAN_S          17
 290 #define FW_FILTER_WR_INSVLAN_M          0x1
 291 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 292 #define FW_FILTER_WR_INSVLAN_G(x)       \
 293         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 294 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 295
 296 #define FW_FILTER_WR_RMVLAN_S           16
 297 #define FW_FILTER_WR_RMVLAN_M           0x1
 298 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 299 #define FW_FILTER_WR_RMVLAN_G(x)        \
 300         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 301 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 302
 303 #define FW_FILTER_WR_HITCNTS_S          15
 304 #define FW_FILTER_WR_HITCNTS_M          0x1
 305 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 306 #define FW_FILTER_WR_HITCNTS_G(x)       \
 307         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 308 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 309
 310 #define FW_FILTER_WR_TXCHAN_S           13
 311 #define FW_FILTER_WR_TXCHAN_M           0x3
 312 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 313 #define FW_FILTER_WR_TXCHAN_G(x)        \
 314         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 315
 316 #define FW_FILTER_WR_PRIO_S     12
 317 #define FW_FILTER_WR_PRIO_M     0x1
 318 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 319 #define FW_FILTER_WR_PRIO_G(x)  \
 320         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 321 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 322
 323 #define FW_FILTER_WR_L2TIX_S    0
 324 #define FW_FILTER_WR_L2TIX_M    0xfff
 325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 326 #define FW_FILTER_WR_L2TIX_G(x) \
 327         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 328
 329 #define FW_FILTER_WR_FRAG_S     7
 330 #define FW_FILTER_WR_FRAG_M     0x1
 331 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 332 #define FW_FILTER_WR_FRAG_G(x)  \
 333         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 334 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 335
 336 #define FW_FILTER_WR_FRAGM_S    6
 337 #define FW_FILTER_WR_FRAGM_M    0x1
 338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 339 #define FW_FILTER_WR_FRAGM_G(x) \
 340         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 341 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 342
 343 #define FW_FILTER_WR_IVLAN_VLD_S        5
 344 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 345 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 346 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 347         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 348 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 349
 350 #define FW_FILTER_WR_OVLAN_VLD_S        4
 351 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 352 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 353 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 354         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 355 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 356
 357 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 358 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 359 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 360 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 361         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 362 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 363
 364 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 365 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 366 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 367 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 368         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 369 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 370
 371 #define FW_FILTER_WR_RX_CHAN_S          15
 372 #define FW_FILTER_WR_RX_CHAN_M          0x1
 373 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 374 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 375         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 376 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 377
 378 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 379 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 380 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 381 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 382         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 383
 384 #define FW_FILTER_WR_MACI_S     23
 385 #define FW_FILTER_WR_MACI_M     0x1ff
 386 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 387 #define FW_FILTER_WR_MACI_G(x)  \
 388         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 389
 390 #define FW_FILTER_WR_MACIM_S    14
 391 #define FW_FILTER_WR_MACIM_M    0x1ff
 392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 393 #define FW_FILTER_WR_MACIM_G(x) \
 394         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 395
 396 #define FW_FILTER_WR_FCOE_S     13
 397 #define FW_FILTER_WR_FCOE_M     0x1
 398 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 399 #define FW_FILTER_WR_FCOE_G(x)  \
 400         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 401 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 402
 403 #define FW_FILTER_WR_FCOEM_S    12
 404 #define FW_FILTER_WR_FCOEM_M    0x1
 405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 406 #define FW_FILTER_WR_FCOEM_G(x) \
 407         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 408 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 409
 410 #define FW_FILTER_WR_PORT_S     9
 411 #define FW_FILTER_WR_PORT_M     0x7
 412 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 413 #define FW_FILTER_WR_PORT_G(x)  \
 414         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 415
 416 #define FW_FILTER_WR_PORTM_S    6
 417 #define FW_FILTER_WR_PORTM_M    0x7
 418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 419 #define FW_FILTER_WR_PORTM_G(x) \
 420         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 421
 422 #define FW_FILTER_WR_MATCHTYPE_S        3
 423 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 424 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 425 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 426         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 427
 428 #define FW_FILTER_WR_MATCHTYPEM_S       0
 429 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 430 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 431 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 432         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 433
 434 struct fw_ulptx_wr {
 435         __be32 op_to_compl;
 436         __be32 flowid_len16;
 437         u64 cookie;
 438 };
 439
 440 struct fw_tp_wr {
 441         __be32 op_to_immdlen;
 442         __be32 flowid_len16;
 443         u64 cookie;
 444 };
 445
 446 struct fw_eth_tx_pkt_wr {
 447         __be32 op_immdlen;
 448         __be32 equiq_to_len16;
 449         __be64 r3;
 450 };
 451
 452 struct fw_ofld_connection_wr {
 453         __be32 op_compl;
 454         __be32 len16_pkd;
 455         __u64  cookie;
 456         __be64 r2;
 457         __be64 r3;
 458         struct fw_ofld_connection_le {
 459                 __be32 version_cpl;
 460                 __be32 filter;
 461                 __be32 r1;
 462                 __be16 lport;
 463                 __be16 pport;
 464                 union fw_ofld_connection_leip {
 465                         struct fw_ofld_connection_le_ipv4 {
 466                                 __be32 pip;
 467                                 __be32 lip;
 468                                 __be64 r0;
 469                                 __be64 r1;
 470                                 __be64 r2;
 471                         } ipv4;
 472                         struct fw_ofld_connection_le_ipv6 {
 473                                 __be64 pip_hi;
 474                                 __be64 pip_lo;
 475                                 __be64 lip_hi;
 476                                 __be64 lip_lo;
 477                         } ipv6;
 478                 } u;
 479         } le;
 480         struct fw_ofld_connection_tcb {
 481                 __be32 t_state_to_astid;
 482                 __be16 cplrxdataack_cplpassacceptrpl;
 483                 __be16 rcv_adv;
 484                 __be32 rcv_nxt;
 485                 __be32 tx_max;
 486                 __be64 opt0;
 487                 __be32 opt2;
 488                 __be32 r1;
 489                 __be64 r2;
 490                 __be64 r3;
 491         } tcb;
 492 };
 493
 494 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 495 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 497         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 499         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 500         FW_OFLD_CONNECTION_WR_VERSION_M)
 501 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 502         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 503
 504 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 505 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 508         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 509 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 510
 511 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 512 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 514         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 516         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 517         FW_OFLD_CONNECTION_WR_T_STATE_M)
 518
 519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 522         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 524         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 525         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 526
 527 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 528 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 530         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 532         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 533
 534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 537         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 539         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 540         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 542         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 543
 544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 547         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 549         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 550         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 552         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 553
 554 enum fw_flowc_mnem {
 555         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 556         FW_FLOWC_MNEM_CH,
 557         FW_FLOWC_MNEM_PORT,
 558         FW_FLOWC_MNEM_IQID,
 559         FW_FLOWC_MNEM_SNDNXT,
 560         FW_FLOWC_MNEM_RCVNXT,
 561         FW_FLOWC_MNEM_SNDBUF,
 562         FW_FLOWC_MNEM_MSS,
 563 };
 564
 565 struct fw_flowc_mnemval {
 566         u8 mnemonic;
 567         u8 r4[3];
 568         __be32 val;
 569 };
 570
 571 struct fw_flowc_wr {
 572         __be32 op_to_nparams;
 573         __be32 flowid_len16;
 574         struct fw_flowc_mnemval mnemval[0];
 575 };
 576
 577 #define FW_FLOWC_WR_NPARAMS_S           0
 578 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 579
 580 struct fw_ofld_tx_data_wr {
 581         __be32 op_to_immdlen;
 582         __be32 flowid_len16;
 583         __be32 plen;
 584         __be32 tunnel_to_proxy;
 585 };
 586
 587 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 588 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 589
 590 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 591 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 592
 593 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 594 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 595 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 596
 597 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 598 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 599
 600 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 601 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 602
 603 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 604 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 605 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 606
 607 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 608 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 609
 610 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 612         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 613
 614 struct fw_cmd_wr {
 615         __be32 op_dma;
 616 #define FW_CMD_WR_DMA (1U << 17)
 617         __be32 len16_pkd;
 618         __be64 cookie_daddr;
 619 };
 620
 621 #define FW_CMD_WR_DMA_S         17
 622 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 623
 624 struct fw_eth_tx_pkt_vm_wr {
 625         __be32 op_immdlen;
 626         __be32 equiq_to_len16;
 627         __be32 r3[2];
 628         u8 ethmacdst[6];
 629         u8 ethmacsrc[6];
 630         __be16 ethtype;
 631         __be16 vlantci;
 632 };
 633
 634 #define FW_CMD_MAX_TIMEOUT 10000
 635
 636 /*
 637  * If a host driver does a HELLO and discovers that there's already a MASTER
 638  * selected, we may have to wait for that MASTER to finish issuing RESET,
 639  * configuration and INITIALIZE commands.  Also, there's a possibility that
 640  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 641  * RESET command, so we need to be willing to make a few retries of our HELLO.
 642  */
 643 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 644 #define FW_CMD_HELLO_RETRIES    3
 645
 646
 647 enum fw_cmd_opcodes {
 648         FW_LDST_CMD                    = 0x01,
 649         FW_RESET_CMD                   = 0x03,
 650         FW_HELLO_CMD                   = 0x04,
 651         FW_BYE_CMD                     = 0x05,
 652         FW_INITIALIZE_CMD              = 0x06,
 653         FW_CAPS_CONFIG_CMD             = 0x07,
 654         FW_PARAMS_CMD                  = 0x08,
 655         FW_PFVF_CMD                    = 0x09,
 656         FW_IQ_CMD                      = 0x10,
 657         FW_EQ_MNGT_CMD                 = 0x11,
 658         FW_EQ_ETH_CMD                  = 0x12,
 659         FW_EQ_CTRL_CMD                 = 0x13,
 660         FW_EQ_OFLD_CMD                 = 0x21,
 661         FW_VI_CMD                      = 0x14,
 662         FW_VI_MAC_CMD                  = 0x15,
 663         FW_VI_RXMODE_CMD               = 0x16,
 664         FW_VI_ENABLE_CMD               = 0x17,
 665         FW_ACL_MAC_CMD                 = 0x18,
 666         FW_ACL_VLAN_CMD                = 0x19,
 667         FW_VI_STATS_CMD                = 0x1a,
 668         FW_PORT_CMD                    = 0x1b,
 669         FW_PORT_STATS_CMD              = 0x1c,
 670         FW_PORT_LB_STATS_CMD           = 0x1d,
 671         FW_PORT_TRACE_CMD              = 0x1e,
 672         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 673         FW_RSS_IND_TBL_CMD             = 0x20,
 674         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 675         FW_RSS_VI_CONFIG_CMD           = 0x23,
 676         FW_CLIP_CMD                    = 0x28,
 677         FW_LASTC2E_CMD                 = 0x40,
 678         FW_ERROR_CMD                   = 0x80,
 679         FW_DEBUG_CMD                   = 0x81,
 680 };
 681
 682 enum fw_cmd_cap {
 683         FW_CMD_CAP_PF                  = 0x01,
 684         FW_CMD_CAP_DMAQ                = 0x02,
 685         FW_CMD_CAP_PORT                = 0x04,
 686         FW_CMD_CAP_PORTPROMISC         = 0x08,
 687         FW_CMD_CAP_PORTSTATS           = 0x10,
 688         FW_CMD_CAP_VF                  = 0x80,
 689 };
 690
 691 /*
 692  * Generic command header flit0
 693  */
 694 struct fw_cmd_hdr {
 695         __be32 hi;
 696         __be32 lo;
 697 };
 698
 699 #define FW_CMD_OP_S             24
 700 #define FW_CMD_OP_M             0xff
 701 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 702 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 703
 704 #define FW_CMD_REQUEST_S        23
 705 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 706 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 707
 708 #define FW_CMD_READ_S           22
 709 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 710 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 711
 712 #define FW_CMD_WRITE_S          21
 713 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 714 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 715
 716 #define FW_CMD_EXEC_S           20
 717 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 718 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 719
 720 #define FW_CMD_RAMASK_S         20
 721 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 722
 723 #define FW_CMD_RETVAL_S         8
 724 #define FW_CMD_RETVAL_M         0xff
 725 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 726 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 727
 728 #define FW_CMD_LEN16_S          0
 729 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 730
 731 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 732
 733 enum fw_ldst_addrspc {
 734         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 735         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 736         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 737         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 738         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 739         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 740         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 741         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 742         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 743         FW_LDST_ADDRSPC_MPS       = 0x0020,
 744         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 745         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 746 };
 747
 748 enum fw_ldst_mps_fid {
 749         FW_LDST_MPS_ATRB,
 750         FW_LDST_MPS_RPLC
 751 };
 752
 753 enum fw_ldst_func_access_ctl {
 754         FW_LDST_FUNC_ACC_CTL_VIID,
 755         FW_LDST_FUNC_ACC_CTL_FID
 756 };
 757
 758 enum fw_ldst_func_mod_index {
 759         FW_LDST_FUNC_MPS
 760 };
 761
 762 struct fw_ldst_cmd {
 763         __be32 op_to_addrspace;
 764 #define FW_LDST_CMD_ADDRSPACE_S         0
 765 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 766         __be32 cycles_to_len16;
 767         union fw_ldst {
 768                 struct fw_ldst_addrval {
 769                         __be32 addr;
 770                         __be32 val;
 771                 } addrval;
 772                 struct fw_ldst_idctxt {
 773                         __be32 physid;
 774                         __be32 msg_pkd;
 775                         __be32 ctxt_data7;
 776                         __be32 ctxt_data6;
 777                         __be32 ctxt_data5;
 778                         __be32 ctxt_data4;
 779                         __be32 ctxt_data3;
 780                         __be32 ctxt_data2;
 781                         __be32 ctxt_data1;
 782                         __be32 ctxt_data0;
 783                 } idctxt;
 784                 struct fw_ldst_mdio {
 785                         __be16 paddr_mmd;
 786                         __be16 raddr;
 787                         __be16 vctl;
 788                         __be16 rval;
 789                 } mdio;
 790                 struct fw_ldst_mps {
 791                         __be16 fid_ctl;
 792                         __be16 rplcpf_pkd;
 793                         __be32 rplc127_96;
 794                         __be32 rplc95_64;
 795                         __be32 rplc63_32;
 796                         __be32 rplc31_0;
 797                         __be32 atrb;
 798                         __be16 vlan[16];
 799                 } mps;
 800                 struct fw_ldst_func {
 801                         u8 access_ctl;
 802                         u8 mod_index;
 803                         __be16 ctl_id;
 804                         __be32 offset;
 805                         __be64 data0;
 806                         __be64 data1;
 807                 } func;
 808                 struct fw_ldst_pcie {
 809                         u8 ctrl_to_fn;
 810                         u8 bnum;
 811                         u8 r;
 812                         u8 ext_r;
 813                         u8 select_naccess;
 814                         u8 pcie_fn;
 815                         __be16 nset_pkd;
 816                         __be32 data[12];
 817                 } pcie;
 818         } u;
 819 };
 820
 821 #define FW_LDST_CMD_MSG_S       31
 822 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 823
 824 #define FW_LDST_CMD_PADDR_S     8
 825 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 826
 827 #define FW_LDST_CMD_MMD_S       0
 828 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 829
 830 #define FW_LDST_CMD_FID_S       15
 831 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 832
 833 #define FW_LDST_CMD_CTL_S       0
 834 #define FW_LDST_CMD_CTL_V(x)    ((x) << FW_LDST_CMD_CTL_S)
 835
 836 #define FW_LDST_CMD_RPLCPF_S    0
 837 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 838
 839 #define FW_LDST_CMD_LC_S        4
 840 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 841 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 842
 843 #define FW_LDST_CMD_FN_S        0
 844 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 845
 846 #define FW_LDST_CMD_NACCESS_S           0
 847 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 848
 849 struct fw_reset_cmd {
 850         __be32 op_to_write;
 851         __be32 retval_len16;
 852         __be32 val;
 853         __be32 halt_pkd;
 854 };
 855
 856 #define FW_RESET_CMD_HALT_S     31
 857 #define FW_RESET_CMD_HALT_M     0x1
 858 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 859 #define FW_RESET_CMD_HALT_G(x)  \
 860         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 861 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 862
 863 enum fw_hellow_cmd {
 864         fw_hello_cmd_stage_os           = 0x0
 865 };
 866
 867 struct fw_hello_cmd {
 868         __be32 op_to_write;
 869         __be32 retval_len16;
 870         __be32 err_to_clearinit;
 871         __be32 fwrev;
 872 };
 873
 874 #define FW_HELLO_CMD_ERR_S      31
 875 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 876 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 877
 878 #define FW_HELLO_CMD_INIT_S     30
 879 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 880 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 881
 882 #define FW_HELLO_CMD_MASTERDIS_S        29
 883 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 884
 885 #define FW_HELLO_CMD_MASTERFORCE_S      28
 886 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 887
 888 #define FW_HELLO_CMD_MBMASTER_S         24
 889 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 890 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 891 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 892         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 893
 894 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 895 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 896
 897 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 898 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 899
 900 #define FW_HELLO_CMD_STAGE_S            17
 901 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 902
 903 #define FW_HELLO_CMD_CLEARINIT_S        16
 904 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 905 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 906
 907 struct fw_bye_cmd {
 908         __be32 op_to_write;
 909         __be32 retval_len16;
 910         __be64 r3;
 911 };
 912
 913 struct fw_initialize_cmd {
 914         __be32 op_to_write;
 915         __be32 retval_len16;
 916         __be64 r3;
 917 };
 918
 919 enum fw_caps_config_hm {
 920         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 921         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 922         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 923         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 924         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 925         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 926         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 927         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 928         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 929         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 930         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 931         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 932         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 933         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 934         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 935         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 936         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 937         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 938         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 939         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 940         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 941         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 942         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 943         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 944 };
 945
 946 enum fw_caps_config_nbm {
 947         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
 948         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
 949 };
 950
 951 enum fw_caps_config_link {
 952         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
 953         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
 954         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
 955 };
 956
 957 enum fw_caps_config_switch {
 958         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
 959         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
 960 };
 961
 962 enum fw_caps_config_nic {
 963         FW_CAPS_CONFIG_NIC              = 0x00000001,
 964         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
 965 };
 966
 967 enum fw_caps_config_ofld {
 968         FW_CAPS_CONFIG_OFLD             = 0x00000001,
 969 };
 970
 971 enum fw_caps_config_rdma {
 972         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
 973         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
 974 };
 975
 976 enum fw_caps_config_iscsi {
 977         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
 978         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
 979         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
 980         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
 981 };
 982
 983 enum fw_caps_config_fcoe {
 984         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
 985         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
 986         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
 987 };
 988
 989 enum fw_memtype_cf {
 990         FW_MEMTYPE_CF_EDC0              = 0x0,
 991         FW_MEMTYPE_CF_EDC1              = 0x1,
 992         FW_MEMTYPE_CF_EXTMEM            = 0x2,
 993         FW_MEMTYPE_CF_FLASH             = 0x4,
 994         FW_MEMTYPE_CF_INTERNAL          = 0x5,
 995 };
 996
 997 struct fw_caps_config_cmd {
 998         __be32 op_to_write;
 999         __be32 cfvalid_to_len16;
1000         __be32 r2;
1001         __be32 hwmbitmap;
1002         __be16 nbmcaps;
1003         __be16 linkcaps;
1004         __be16 switchcaps;
1005         __be16 r3;
1006         __be16 niccaps;
1007         __be16 ofldcaps;
1008         __be16 rdmacaps;
1009         __be16 r4;
1010         __be16 iscsicaps;
1011         __be16 fcoecaps;
1012         __be32 cfcsum;
1013         __be32 finiver;
1014         __be32 finicsum;
1015 };
1016
1017 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1018 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1019 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1020
1021 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1022 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1023         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1024
1025 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1026 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1027         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1028
1029 /*
1030  * params command mnemonics
1031  */
1032 enum fw_params_mnem {
1033         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1034         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1035         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1036         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1037         FW_PARAMS_MNEM_LAST
1038 };
1039
1040 /*
1041  * device parameters
1042  */
1043 enum fw_params_param_dev {
1044         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1045         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1046         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1047                                                  * allocated by the device's
1048                                                  * Lookup Engine
1049                                                  */
1050         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1051         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1052         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1053         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1054         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1055         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1056         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1057         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1058         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1059         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1060         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1061         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1062         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1063         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1064 };
1065
1066 /*
1067  * physical and virtual function parameters
1068  */
1069 enum fw_params_param_pfvf {
1070         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1071         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1072         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1073         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1074         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1075         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1076         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1077         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1078         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1079         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1080         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1081         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1082         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1083         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1084         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1085         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1086         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1087         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1088         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1089         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1090         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1091         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1092         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1093         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1094         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1095         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1096         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1097         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1098         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1099         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1100         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1101         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1102         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1103         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1104         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1105         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1106         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1107         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1108         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1109 };
1110
1111 /*
1112  * dma queue parameters
1113  */
1114 enum fw_params_param_dmaq {
1115         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1116         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1117         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1118         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1119         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1120         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1121 };
1122
1123 #define FW_PARAMS_MNEM_S        24
1124 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1125
1126 #define FW_PARAMS_PARAM_X_S     16
1127 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1128
1129 #define FW_PARAMS_PARAM_Y_S     8
1130 #define FW_PARAMS_PARAM_Y_M     0xffU
1131 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1132 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1133                 FW_PARAMS_PARAM_Y_M)
1134
1135 #define FW_PARAMS_PARAM_Z_S     0
1136 #define FW_PARAMS_PARAM_Z_M     0xffu
1137 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1138 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1139                 FW_PARAMS_PARAM_Z_M)
1140
1141 #define FW_PARAMS_PARAM_XYZ_S           0
1142 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1143
1144 #define FW_PARAMS_PARAM_YZ_S            0
1145 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1146
1147 struct fw_params_cmd {
1148         __be32 op_to_vfn;
1149         __be32 retval_len16;
1150         struct fw_params_param {
1151                 __be32 mnem;
1152                 __be32 val;
1153         } param[7];
1154 };
1155
1156 #define FW_PARAMS_CMD_PFN_S     8
1157 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1158
1159 #define FW_PARAMS_CMD_VFN_S     0
1160 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1161
1162 struct fw_pfvf_cmd {
1163         __be32 op_to_vfn;
1164         __be32 retval_len16;
1165         __be32 niqflint_niq;
1166         __be32 type_to_neq;
1167         __be32 tc_to_nexactf;
1168         __be32 r_caps_to_nethctrl;
1169         __be16 nricq;
1170         __be16 nriqp;
1171         __be32 r4;
1172 };
1173
1174 #define FW_PFVF_CMD_PFN_S       8
1175 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1176
1177 #define FW_PFVF_CMD_VFN_S       0
1178 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1179
1180 #define FW_PFVF_CMD_NIQFLINT_S          20
1181 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1182 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1183 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1184         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1185
1186 #define FW_PFVF_CMD_NIQ_S       0
1187 #define FW_PFVF_CMD_NIQ_M       0xfffff
1188 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1189 #define FW_PFVF_CMD_NIQ_G(x)    \
1190         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1191
1192 #define FW_PFVF_CMD_TYPE_S      31
1193 #define FW_PFVF_CMD_TYPE_M      0x1
1194 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1195 #define FW_PFVF_CMD_TYPE_G(x)   \
1196         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1197 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1198
1199 #define FW_PFVF_CMD_CMASK_S     24
1200 #define FW_PFVF_CMD_CMASK_M     0xf
1201 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1202 #define FW_PFVF_CMD_CMASK_G(x)  \
1203         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1204
1205 #define FW_PFVF_CMD_PMASK_S     20
1206 #define FW_PFVF_CMD_PMASK_M     0xf
1207 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1208 #define FW_PFVF_CMD_PMASK_G(x) \
1209         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1210
1211 #define FW_PFVF_CMD_NEQ_S       0
1212 #define FW_PFVF_CMD_NEQ_M       0xfffff
1213 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1214 #define FW_PFVF_CMD_NEQ_G(x)    \
1215         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1216
1217 #define FW_PFVF_CMD_TC_S        24
1218 #define FW_PFVF_CMD_TC_M        0xff
1219 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1220 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1221
1222 #define FW_PFVF_CMD_NVI_S       16
1223 #define FW_PFVF_CMD_NVI_M       0xff
1224 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1225 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1226
1227 #define FW_PFVF_CMD_NEXACTF_S           0
1228 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1229 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1230 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1231         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1232
1233 #define FW_PFVF_CMD_R_CAPS_S    24
1234 #define FW_PFVF_CMD_R_CAPS_M    0xff
1235 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1236 #define FW_PFVF_CMD_R_CAPS_G(x) \
1237         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1238
1239 #define FW_PFVF_CMD_WX_CAPS_S           16
1240 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1241 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1242 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1243         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1244
1245 #define FW_PFVF_CMD_NETHCTRL_S          0
1246 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1247 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1248 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1249         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1250
1251 enum fw_iq_type {
1252         FW_IQ_TYPE_FL_INT_CAP,
1253         FW_IQ_TYPE_NO_FL_INT_CAP
1254 };
1255
1256 struct fw_iq_cmd {
1257         __be32 op_to_vfn;
1258         __be32 alloc_to_len16;
1259         __be16 physiqid;
1260         __be16 iqid;
1261         __be16 fl0id;
1262         __be16 fl1id;
1263         __be32 type_to_iqandstindex;
1264         __be16 iqdroprss_to_iqesize;
1265         __be16 iqsize;
1266         __be64 iqaddr;
1267         __be32 iqns_to_fl0congen;
1268         __be16 fl0dcaen_to_fl0cidxfthresh;
1269         __be16 fl0size;
1270         __be64 fl0addr;
1271         __be32 fl1cngchmap_to_fl1congen;
1272         __be16 fl1dcaen_to_fl1cidxfthresh;
1273         __be16 fl1size;
1274         __be64 fl1addr;
1275 };
1276
1277 #define FW_IQ_CMD_PFN(x) ((x) << 8)
1278 #define FW_IQ_CMD_VFN(x) ((x) << 0)
1279
1280 #define FW_IQ_CMD_ALLOC (1U << 31)
1281 #define FW_IQ_CMD_FREE (1U << 30)
1282 #define FW_IQ_CMD_MODIFY (1U << 29)
1283 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
1284 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
1285
1286 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
1287 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
1288 #define FW_IQ_CMD_VIID(x) ((x) << 16)
1289 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
1290 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
1291 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
1292 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
1293
1294 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
1295 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
1296 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
1297 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
1298 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
1299 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
1300 #define FW_IQ_CMD_IQO (1U << 3)
1301 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
1302 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
1303
1304 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
1305 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
1306 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
1307 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
1308 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
1309 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
1310 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
1311 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
1312 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
1313 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
1314 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
1315 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
1316 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
1317 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
1318 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
1319 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
1320 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
1321 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
1322 #define FW_IQ_CMD_FL0PADEN(x) ((x) << 2)
1323 #define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1)
1324 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
1325
1326 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
1327 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
1328 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
1329 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
1330 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
1331 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
1332
1333 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
1334 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
1335 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
1336 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
1337 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
1338 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
1339 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
1340 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
1341 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
1342 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
1343 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
1344 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
1345 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
1346 #define FW_IQ_CMD_FL1PADEN (1U << 2)
1347 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
1348 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
1349
1350 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
1351 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
1352 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
1353 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
1354 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
1355 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
1356
1357 struct fw_eq_eth_cmd {
1358         __be32 op_to_vfn;
1359         __be32 alloc_to_len16;
1360         __be32 eqid_pkd;
1361         __be32 physeqid_pkd;
1362         __be32 fetchszm_to_iqid;
1363         __be32 dcaen_to_eqsize;
1364         __be64 eqaddr;
1365         __be32 viid_pkd;
1366         __be32 r8_lo;
1367         __be64 r9;
1368 };
1369
1370 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
1371 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
1372 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
1373 #define FW_EQ_ETH_CMD_FREE (1U << 30)
1374 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
1375 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
1376 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
1377
1378 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
1379 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1380 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
1381 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1382
1383 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
1384 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
1385 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
1386 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
1387 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
1388 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
1389 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
1390 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
1391 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
1392 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
1393
1394 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
1395 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
1396 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
1397 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
1398 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
1399 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
1400 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
1401
1402 #define FW_EQ_ETH_CMD_AUTOEQUEQE (1U << 30)
1403 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
1404
1405 struct fw_eq_ctrl_cmd {
1406         __be32 op_to_vfn;
1407         __be32 alloc_to_len16;
1408         __be32 cmpliqid_eqid;
1409         __be32 physeqid_pkd;
1410         __be32 fetchszm_to_iqid;
1411         __be32 dcaen_to_eqsize;
1412         __be64 eqaddr;
1413 };
1414
1415 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
1416 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
1417
1418 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
1419 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
1420 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
1421 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
1422 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
1423
1424 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
1425 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
1426 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1427 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1428
1429 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
1430 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
1431 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
1432 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
1433 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
1434 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
1435 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
1436 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
1437 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
1438 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
1439
1440 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
1441 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
1442 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
1443 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
1444 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
1445 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
1446 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
1447
1448 struct fw_eq_ofld_cmd {
1449         __be32 op_to_vfn;
1450         __be32 alloc_to_len16;
1451         __be32 eqid_pkd;
1452         __be32 physeqid_pkd;
1453         __be32 fetchszm_to_iqid;
1454         __be32 dcaen_to_eqsize;
1455         __be64 eqaddr;
1456 };
1457
1458 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
1459 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
1460
1461 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
1462 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
1463 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
1464 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
1465 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
1466
1467 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
1468 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1469 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1470
1471 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
1472 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
1473 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
1474 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
1475 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
1476 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
1477 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
1478 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
1479 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
1480 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
1481
1482 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
1483 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
1484 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
1485 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
1486 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
1487 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
1488 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
1489
1490 /*
1491  * Macros for VIID parsing:
1492  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1493  */
1494
1495 #define FW_VIID_PFN_S           8
1496 #define FW_VIID_PFN_M           0x7
1497 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1498
1499 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
1500 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
1501
1502 struct fw_vi_cmd {
1503         __be32 op_to_vfn;
1504         __be32 alloc_to_len16;
1505         __be16 type_viid;
1506         u8 mac[6];
1507         u8 portid_pkd;
1508         u8 nmac;
1509         u8 nmac0[6];
1510         __be16 rsssize_pkd;
1511         u8 nmac1[6];
1512         __be16 idsiiq_pkd;
1513         u8 nmac2[6];
1514         __be16 idseiq_pkd;
1515         u8 nmac3[6];
1516         __be64 r9;
1517         __be64 r10;
1518 };
1519
1520 #define FW_VI_CMD_PFN(x) ((x) << 8)
1521 #define FW_VI_CMD_VFN(x) ((x) << 0)
1522 #define FW_VI_CMD_ALLOC (1U << 31)
1523 #define FW_VI_CMD_FREE (1U << 30)
1524 #define FW_VI_CMD_VIID(x) ((x) << 0)
1525 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
1526 #define FW_VI_CMD_PORTID(x) ((x) << 4)
1527 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
1528 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
1529
1530 /* Special VI_MAC command index ids */
1531 #define FW_VI_MAC_ADD_MAC               0x3FF
1532 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1533 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1534 #define FW_CLS_TCAM_NUM_ENTRIES         336
1535
1536 enum fw_vi_mac_smac {
1537         FW_VI_MAC_MPS_TCAM_ENTRY,
1538         FW_VI_MAC_MPS_TCAM_ONLY,
1539         FW_VI_MAC_SMT_ONLY,
1540         FW_VI_MAC_SMT_AND_MPSTCAM
1541 };
1542
1543 enum fw_vi_mac_result {
1544         FW_VI_MAC_R_SUCCESS,
1545         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1546         FW_VI_MAC_R_SMAC_FAIL,
1547         FW_VI_MAC_R_F_ACL_CHECK
1548 };
1549
1550 struct fw_vi_mac_cmd {
1551         __be32 op_to_viid;
1552         __be32 freemacs_to_len16;
1553         union fw_vi_mac {
1554                 struct fw_vi_mac_exact {
1555                         __be16 valid_to_idx;
1556                         u8 macaddr[6];
1557                 } exact[7];
1558                 struct fw_vi_mac_hash {
1559                         __be64 hashvec;
1560                 } hash;
1561         } u;
1562 };
1563
1564 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
1565 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
1566 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
1567 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
1568 #define FW_VI_MAC_CMD_VALID (1U << 15)
1569 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
1570 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
1571 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
1572 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
1573 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
1574
1575 #define FW_RXMODE_MTU_NO_CHG    65535
1576
1577 struct fw_vi_rxmode_cmd {
1578         __be32 op_to_viid;
1579         __be32 retval_len16;
1580         __be32 mtu_to_vlanexen;
1581         __be32 r4_lo;
1582 };
1583
1584 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
1585 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
1586 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
1587 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
1588 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
1589 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
1590 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
1591 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
1592 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
1593 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
1594 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
1595
1596 struct fw_vi_enable_cmd {
1597         __be32 op_to_viid;
1598         __be32 ien_to_len16;
1599         __be16 blinkdur;
1600         __be16 r3;
1601         __be32 r4;
1602 };
1603
1604 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
1605 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
1606 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
1607 #define FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << 28)
1608 #define FW_VI_ENABLE_CMD_LED (1U << 29)
1609
1610 /* VI VF stats offset definitions */
1611 #define VI_VF_NUM_STATS 16
1612 enum fw_vi_stats_vf_index {
1613         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
1614         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
1615         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
1616         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
1617         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
1618         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
1619         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
1620         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
1621         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
1622         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
1623         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
1624         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
1625         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
1626         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
1627         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
1628         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
1629 };
1630
1631 /* VI PF stats offset definitions */
1632 #define VI_PF_NUM_STATS 17
1633 enum fw_vi_stats_pf_index {
1634         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1635         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1636         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1637         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1638         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1639         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1640         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1641         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1642         FW_VI_PF_STAT_RX_BYTES_IX,
1643         FW_VI_PF_STAT_RX_FRAMES_IX,
1644         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1645         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1646         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1647         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1648         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1649         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1650         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1651 };
1652
1653 struct fw_vi_stats_cmd {
1654         __be32 op_to_viid;
1655         __be32 retval_len16;
1656         union fw_vi_stats {
1657                 struct fw_vi_stats_ctl {
1658                         __be16 nstats_ix;
1659                         __be16 r6;
1660                         __be32 r7;
1661                         __be64 stat0;
1662                         __be64 stat1;
1663                         __be64 stat2;
1664                         __be64 stat3;
1665                         __be64 stat4;
1666                         __be64 stat5;
1667                 } ctl;
1668                 struct fw_vi_stats_pf {
1669                         __be64 tx_bcast_bytes;
1670                         __be64 tx_bcast_frames;
1671                         __be64 tx_mcast_bytes;
1672                         __be64 tx_mcast_frames;
1673                         __be64 tx_ucast_bytes;
1674                         __be64 tx_ucast_frames;
1675                         __be64 tx_offload_bytes;
1676                         __be64 tx_offload_frames;
1677                         __be64 rx_pf_bytes;
1678                         __be64 rx_pf_frames;
1679                         __be64 rx_bcast_bytes;
1680                         __be64 rx_bcast_frames;
1681                         __be64 rx_mcast_bytes;
1682                         __be64 rx_mcast_frames;
1683                         __be64 rx_ucast_bytes;
1684                         __be64 rx_ucast_frames;
1685                         __be64 rx_err_frames;
1686                 } pf;
1687                 struct fw_vi_stats_vf {
1688                         __be64 tx_bcast_bytes;
1689                         __be64 tx_bcast_frames;
1690                         __be64 tx_mcast_bytes;
1691                         __be64 tx_mcast_frames;
1692                         __be64 tx_ucast_bytes;
1693                         __be64 tx_ucast_frames;
1694                         __be64 tx_drop_frames;
1695                         __be64 tx_offload_bytes;
1696                         __be64 tx_offload_frames;
1697                         __be64 rx_bcast_bytes;
1698                         __be64 rx_bcast_frames;
1699                         __be64 rx_mcast_bytes;
1700                         __be64 rx_mcast_frames;
1701                         __be64 rx_ucast_bytes;
1702                         __be64 rx_ucast_frames;
1703                         __be64 rx_err_frames;
1704                 } vf;
1705         } u;
1706 };
1707
1708 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1709 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1710 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1711
1712 struct fw_acl_mac_cmd {
1713         __be32 op_to_vfn;
1714         __be32 en_to_len16;
1715         u8 nmac;
1716         u8 r3[7];
1717         __be16 r4;
1718         u8 macaddr0[6];
1719         __be16 r5;
1720         u8 macaddr1[6];
1721         __be16 r6;
1722         u8 macaddr2[6];
1723         __be16 r7;
1724         u8 macaddr3[6];
1725 };
1726
1727 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1728 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1729 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1730
1731 struct fw_acl_vlan_cmd {
1732         __be32 op_to_vfn;
1733         __be32 en_to_len16;
1734         u8 nvlan;
1735         u8 dropnovlan_fm;
1736         u8 r3_lo[6];
1737         __be16 vlanid[16];
1738 };
1739
1740 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1741 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1742 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1743 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1744 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1745
1746 enum fw_port_cap {
1747         FW_PORT_CAP_SPEED_100M          = 0x0001,
1748         FW_PORT_CAP_SPEED_1G            = 0x0002,
1749         FW_PORT_CAP_SPEED_2_5G          = 0x0004,
1750         FW_PORT_CAP_SPEED_10G           = 0x0008,
1751         FW_PORT_CAP_SPEED_40G           = 0x0010,
1752         FW_PORT_CAP_SPEED_100G          = 0x0020,
1753         FW_PORT_CAP_FC_RX               = 0x0040,
1754         FW_PORT_CAP_FC_TX               = 0x0080,
1755         FW_PORT_CAP_ANEG                = 0x0100,
1756         FW_PORT_CAP_MDI_0               = 0x0200,
1757         FW_PORT_CAP_MDI_1               = 0x0400,
1758         FW_PORT_CAP_BEAN                = 0x0800,
1759         FW_PORT_CAP_PMA_LPBK            = 0x1000,
1760         FW_PORT_CAP_PCS_LPBK            = 0x2000,
1761         FW_PORT_CAP_PHYXS_LPBK          = 0x4000,
1762         FW_PORT_CAP_FAR_END_LPBK        = 0x8000,
1763 };
1764
1765 enum fw_port_mdi {
1766         FW_PORT_MDI_UNCHANGED,
1767         FW_PORT_MDI_AUTO,
1768         FW_PORT_MDI_F_STRAIGHT,
1769         FW_PORT_MDI_F_CROSSOVER
1770 };
1771
1772 #define FW_PORT_MDI(x) ((x) << 9)
1773
1774 enum fw_port_action {
1775         FW_PORT_ACTION_L1_CFG           = 0x0001,
1776         FW_PORT_ACTION_L2_CFG           = 0x0002,
1777         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
1778         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
1779         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
1780         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
1781         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
1782         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
1783         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1784         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
1785         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
1786         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
1787         FW_PORT_ACTION_L1_LPBK          = 0x0021,
1788         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
1789         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
1790         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1791         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1792         FW_PORT_ACTION_PHY_RESET        = 0x0040,
1793         FW_PORT_ACTION_PMA_RESET        = 0x0041,
1794         FW_PORT_ACTION_PCS_RESET        = 0x0042,
1795         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
1796         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
1797         FW_PORT_ACTION_AN_RESET         = 0x0045
1798 };
1799
1800 enum fw_port_l2cfg_ctlbf {
1801         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1802         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1803         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1804         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1805         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
1806         FW_PORT_L2_CTLBF_TXIPG  = 0x20
1807 };
1808
1809 enum fw_port_dcb_versions {
1810         FW_PORT_DCB_VER_UNKNOWN,
1811         FW_PORT_DCB_VER_CEE1D0,
1812         FW_PORT_DCB_VER_CEE1D01,
1813         FW_PORT_DCB_VER_IEEE,
1814         FW_PORT_DCB_VER_AUTO = 7
1815 };
1816
1817 enum fw_port_dcb_cfg {
1818         FW_PORT_DCB_CFG_PG      = 0x01,
1819         FW_PORT_DCB_CFG_PFC     = 0x02,
1820         FW_PORT_DCB_CFG_APPL    = 0x04
1821 };
1822
1823 enum fw_port_dcb_cfg_rc {
1824         FW_PORT_DCB_CFG_SUCCESS = 0x0,
1825         FW_PORT_DCB_CFG_ERROR   = 0x1
1826 };
1827
1828 enum fw_port_dcb_type {
1829         FW_PORT_DCB_TYPE_PGID           = 0x00,
1830         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
1831         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
1832         FW_PORT_DCB_TYPE_PFC            = 0x03,
1833         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
1834         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
1835 };
1836
1837 enum fw_port_dcb_feature_state {
1838         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
1839         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
1840         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
1841         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
1842 };
1843
1844 struct fw_port_cmd {
1845         __be32 op_to_portid;
1846         __be32 action_to_len16;
1847         union fw_port {
1848                 struct fw_port_l1cfg {
1849                         __be32 rcap;
1850                         __be32 r;
1851                 } l1cfg;
1852                 struct fw_port_l2cfg {
1853                         __u8   ctlbf;
1854                         __u8   ovlan3_to_ivlan0;
1855                         __be16 ivlantype;
1856                         __be16 txipg_force_pinfo;
1857                         __be16 mtu;
1858                         __be16 ovlan0mask;
1859                         __be16 ovlan0type;
1860                         __be16 ovlan1mask;
1861                         __be16 ovlan1type;
1862                         __be16 ovlan2mask;
1863                         __be16 ovlan2type;
1864                         __be16 ovlan3mask;
1865                         __be16 ovlan3type;
1866                 } l2cfg;
1867                 struct fw_port_info {
1868                         __be32 lstatus_to_modtype;
1869                         __be16 pcap;
1870                         __be16 acap;
1871                         __be16 mtu;
1872                         __u8   cbllen;
1873                         __u8   auxlinfo;
1874                         __u8   dcbxdis_pkd;
1875                         __u8   r8_lo[3];
1876                         __be64 r9;
1877                 } info;
1878                 struct fw_port_diags {
1879                         __u8   diagop;
1880                         __u8   r[3];
1881                         __be32 diagval;
1882                 } diags;
1883                 union fw_port_dcb {
1884                         struct fw_port_dcb_pgid {
1885                                 __u8   type;
1886                                 __u8   apply_pkd;
1887                                 __u8   r10_lo[2];
1888                                 __be32 pgid;
1889                                 __be64 r11;
1890                         } pgid;
1891                         struct fw_port_dcb_pgrate {
1892                                 __u8   type;
1893                                 __u8   apply_pkd;
1894                                 __u8   r10_lo[5];
1895                                 __u8   num_tcs_supported;
1896                                 __u8   pgrate[8];
1897                                 __u8   tsa[8];
1898                         } pgrate;
1899                         struct fw_port_dcb_priorate {
1900                                 __u8   type;
1901                                 __u8   apply_pkd;
1902                                 __u8   r10_lo[6];
1903                                 __u8   strict_priorate[8];
1904                         } priorate;
1905                         struct fw_port_dcb_pfc {
1906                                 __u8   type;
1907                                 __u8   pfcen;
1908                                 __u8   r10[5];
1909                                 __u8   max_pfc_tcs;
1910                                 __be64 r11;
1911                         } pfc;
1912                         struct fw_port_app_priority {
1913                                 __u8   type;
1914                                 __u8   r10[2];
1915                                 __u8   idx;
1916                                 __u8   user_prio_map;
1917                                 __u8   sel_field;
1918                                 __be16 protocolid;
1919                                 __be64 r12;
1920                         } app_priority;
1921                         struct fw_port_dcb_control {
1922                                 __u8   type;
1923                                 __u8   all_syncd_pkd;
1924                                 __be16 dcb_version_to_app_state;
1925                                 __be32 r11;
1926                                 __be64 r12;
1927                         } control;
1928                 } dcb;
1929         } u;
1930 };
1931
1932 #define FW_PORT_CMD_READ (1U << 22)
1933
1934 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1935 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1936
1937 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1938 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
1939
1940 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1941 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1942 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1943 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1944 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1945 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1946
1947 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1948
1949 #define FW_PORT_CMD_LSTATUS (1U << 31)
1950 #define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1)
1951 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1952 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1953 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1954 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1955 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1956 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1957 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1958 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1959 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1960 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1961 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1962 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1963
1964 #define FW_PORT_CMD_DCBXDIS (1U << 7)
1965 #define FW_PORT_CMD_APPLY (1U <<  7)
1966 #define FW_PORT_CMD_ALL_SYNCD (1U << 7)
1967 #define FW_PORT_CMD_DCB_VERSION_GET(x) (((x) >> 8) & 0xf)
1968
1969 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1970 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1971 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1972
1973 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1974 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1975 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1976 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1977 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1978
1979 enum fw_port_type {
1980         FW_PORT_TYPE_FIBER_XFI,
1981         FW_PORT_TYPE_FIBER_XAUI,
1982         FW_PORT_TYPE_BT_SGMII,
1983         FW_PORT_TYPE_BT_XFI,
1984         FW_PORT_TYPE_BT_XAUI,
1985         FW_PORT_TYPE_KX4,
1986         FW_PORT_TYPE_CX4,
1987         FW_PORT_TYPE_KX,
1988         FW_PORT_TYPE_KR,
1989         FW_PORT_TYPE_SFP,
1990         FW_PORT_TYPE_BP_AP,
1991         FW_PORT_TYPE_BP4_AP,
1992         FW_PORT_TYPE_QSFP_10G,
1993         FW_PORT_TYPE_QSFP,
1994         FW_PORT_TYPE_BP40_BA,
1995
1996         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1997 };
1998
1999 enum fw_port_module_type {
2000         FW_PORT_MOD_TYPE_NA,
2001         FW_PORT_MOD_TYPE_LR,
2002         FW_PORT_MOD_TYPE_SR,
2003         FW_PORT_MOD_TYPE_ER,
2004         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2005         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2006         FW_PORT_MOD_TYPE_LRM,
2007         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_MASK - 3,
2008         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_MASK - 2,
2009         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_MASK - 1,
2010
2011         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
2012 };
2013
2014 enum fw_port_mod_sub_type {
2015         FW_PORT_MOD_SUB_TYPE_NA,
2016         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2017         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2018         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2019         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2020         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2021         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2022
2023         /* The following will never been in the VPD.  They are TWINAX cable
2024          * lengths decoded from SFP+ module i2c PROMs.  These should
2025          * almost certainly go somewhere else ...
2026          */
2027         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2028         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2029         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2030         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2031 };
2032
2033 /* port stats */
2034 #define FW_NUM_PORT_STATS 50
2035 #define FW_NUM_PORT_TX_STATS 23
2036 #define FW_NUM_PORT_RX_STATS 27
2037
2038 enum fw_port_stats_tx_index {
2039         FW_STAT_TX_PORT_BYTES_IX,
2040         FW_STAT_TX_PORT_FRAMES_IX,
2041         FW_STAT_TX_PORT_BCAST_IX,
2042         FW_STAT_TX_PORT_MCAST_IX,
2043         FW_STAT_TX_PORT_UCAST_IX,
2044         FW_STAT_TX_PORT_ERROR_IX,
2045         FW_STAT_TX_PORT_64B_IX,
2046         FW_STAT_TX_PORT_65B_127B_IX,
2047         FW_STAT_TX_PORT_128B_255B_IX,
2048         FW_STAT_TX_PORT_256B_511B_IX,
2049         FW_STAT_TX_PORT_512B_1023B_IX,
2050         FW_STAT_TX_PORT_1024B_1518B_IX,
2051         FW_STAT_TX_PORT_1519B_MAX_IX,
2052         FW_STAT_TX_PORT_DROP_IX,
2053         FW_STAT_TX_PORT_PAUSE_IX,
2054         FW_STAT_TX_PORT_PPP0_IX,
2055         FW_STAT_TX_PORT_PPP1_IX,
2056         FW_STAT_TX_PORT_PPP2_IX,
2057         FW_STAT_TX_PORT_PPP3_IX,
2058         FW_STAT_TX_PORT_PPP4_IX,
2059         FW_STAT_TX_PORT_PPP5_IX,
2060         FW_STAT_TX_PORT_PPP6_IX,
2061         FW_STAT_TX_PORT_PPP7_IX
2062 };
2063
2064 enum fw_port_stat_rx_index {
2065         FW_STAT_RX_PORT_BYTES_IX,
2066         FW_STAT_RX_PORT_FRAMES_IX,
2067         FW_STAT_RX_PORT_BCAST_IX,
2068         FW_STAT_RX_PORT_MCAST_IX,
2069         FW_STAT_RX_PORT_UCAST_IX,
2070         FW_STAT_RX_PORT_MTU_ERROR_IX,
2071         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2072         FW_STAT_RX_PORT_CRC_ERROR_IX,
2073         FW_STAT_RX_PORT_LEN_ERROR_IX,
2074         FW_STAT_RX_PORT_SYM_ERROR_IX,
2075         FW_STAT_RX_PORT_64B_IX,
2076         FW_STAT_RX_PORT_65B_127B_IX,
2077         FW_STAT_RX_PORT_128B_255B_IX,
2078         FW_STAT_RX_PORT_256B_511B_IX,
2079         FW_STAT_RX_PORT_512B_1023B_IX,
2080         FW_STAT_RX_PORT_1024B_1518B_IX,
2081         FW_STAT_RX_PORT_1519B_MAX_IX,
2082         FW_STAT_RX_PORT_PAUSE_IX,
2083         FW_STAT_RX_PORT_PPP0_IX,
2084         FW_STAT_RX_PORT_PPP1_IX,
2085         FW_STAT_RX_PORT_PPP2_IX,
2086         FW_STAT_RX_PORT_PPP3_IX,
2087         FW_STAT_RX_PORT_PPP4_IX,
2088         FW_STAT_RX_PORT_PPP5_IX,
2089         FW_STAT_RX_PORT_PPP6_IX,
2090         FW_STAT_RX_PORT_PPP7_IX,
2091         FW_STAT_RX_PORT_LESS_64B_IX
2092 };
2093
2094 struct fw_port_stats_cmd {
2095         __be32 op_to_portid;
2096         __be32 retval_len16;
2097         union fw_port_stats {
2098                 struct fw_port_stats_ctl {
2099                         u8 nstats_bg_bm;
2100                         u8 tx_ix;
2101                         __be16 r6;
2102                         __be32 r7;
2103                         __be64 stat0;
2104                         __be64 stat1;
2105                         __be64 stat2;
2106                         __be64 stat3;
2107                         __be64 stat4;
2108                         __be64 stat5;
2109                 } ctl;
2110                 struct fw_port_stats_all {
2111                         __be64 tx_bytes;
2112                         __be64 tx_frames;
2113                         __be64 tx_bcast;
2114                         __be64 tx_mcast;
2115                         __be64 tx_ucast;
2116                         __be64 tx_error;
2117                         __be64 tx_64b;
2118                         __be64 tx_65b_127b;
2119                         __be64 tx_128b_255b;
2120                         __be64 tx_256b_511b;
2121                         __be64 tx_512b_1023b;
2122                         __be64 tx_1024b_1518b;
2123                         __be64 tx_1519b_max;
2124                         __be64 tx_drop;
2125                         __be64 tx_pause;
2126                         __be64 tx_ppp0;
2127                         __be64 tx_ppp1;
2128                         __be64 tx_ppp2;
2129                         __be64 tx_ppp3;
2130                         __be64 tx_ppp4;
2131                         __be64 tx_ppp5;
2132                         __be64 tx_ppp6;
2133                         __be64 tx_ppp7;
2134                         __be64 rx_bytes;
2135                         __be64 rx_frames;
2136                         __be64 rx_bcast;
2137                         __be64 rx_mcast;
2138                         __be64 rx_ucast;
2139                         __be64 rx_mtu_error;
2140                         __be64 rx_mtu_crc_error;
2141                         __be64 rx_crc_error;
2142                         __be64 rx_len_error;
2143                         __be64 rx_sym_error;
2144                         __be64 rx_64b;
2145                         __be64 rx_65b_127b;
2146                         __be64 rx_128b_255b;
2147                         __be64 rx_256b_511b;
2148                         __be64 rx_512b_1023b;
2149                         __be64 rx_1024b_1518b;
2150                         __be64 rx_1519b_max;
2151                         __be64 rx_pause;
2152                         __be64 rx_ppp0;
2153                         __be64 rx_ppp1;
2154                         __be64 rx_ppp2;
2155                         __be64 rx_ppp3;
2156                         __be64 rx_ppp4;
2157                         __be64 rx_ppp5;
2158                         __be64 rx_ppp6;
2159                         __be64 rx_ppp7;
2160                         __be64 rx_less_64b;
2161                         __be64 rx_bg_drop;
2162                         __be64 rx_bg_trunc;
2163                 } all;
2164         } u;
2165 };
2166
2167 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
2168 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
2169 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
2170 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
2171
2172 /* port loopback stats */
2173 #define FW_NUM_LB_STATS 16
2174 enum fw_port_lb_stats_index {
2175         FW_STAT_LB_PORT_BYTES_IX,
2176         FW_STAT_LB_PORT_FRAMES_IX,
2177         FW_STAT_LB_PORT_BCAST_IX,
2178         FW_STAT_LB_PORT_MCAST_IX,
2179         FW_STAT_LB_PORT_UCAST_IX,
2180         FW_STAT_LB_PORT_ERROR_IX,
2181         FW_STAT_LB_PORT_64B_IX,
2182         FW_STAT_LB_PORT_65B_127B_IX,
2183         FW_STAT_LB_PORT_128B_255B_IX,
2184         FW_STAT_LB_PORT_256B_511B_IX,
2185         FW_STAT_LB_PORT_512B_1023B_IX,
2186         FW_STAT_LB_PORT_1024B_1518B_IX,
2187         FW_STAT_LB_PORT_1519B_MAX_IX,
2188         FW_STAT_LB_PORT_DROP_FRAMES_IX
2189 };
2190
2191 struct fw_port_lb_stats_cmd {
2192         __be32 op_to_lbport;
2193         __be32 retval_len16;
2194         union fw_port_lb_stats {
2195                 struct fw_port_lb_stats_ctl {
2196                         u8 nstats_bg_bm;
2197                         u8 ix_pkd;
2198                         __be16 r6;
2199                         __be32 r7;
2200                         __be64 stat0;
2201                         __be64 stat1;
2202                         __be64 stat2;
2203                         __be64 stat3;
2204                         __be64 stat4;
2205                         __be64 stat5;
2206                 } ctl;
2207                 struct fw_port_lb_stats_all {
2208                         __be64 tx_bytes;
2209                         __be64 tx_frames;
2210                         __be64 tx_bcast;
2211                         __be64 tx_mcast;
2212                         __be64 tx_ucast;
2213                         __be64 tx_error;
2214                         __be64 tx_64b;
2215                         __be64 tx_65b_127b;
2216                         __be64 tx_128b_255b;
2217                         __be64 tx_256b_511b;
2218                         __be64 tx_512b_1023b;
2219                         __be64 tx_1024b_1518b;
2220                         __be64 tx_1519b_max;
2221                         __be64 rx_lb_drop;
2222                         __be64 rx_lb_trunc;
2223                 } all;
2224         } u;
2225 };
2226
2227 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
2228 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
2229 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
2230 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
2231
2232 struct fw_rss_ind_tbl_cmd {
2233         __be32 op_to_viid;
2234 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
2235         __be32 retval_len16;
2236         __be16 niqid;
2237         __be16 startidx;
2238         __be32 r3;
2239         __be32 iq0_to_iq2;
2240 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
2241 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
2242 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
2243         __be32 iq3_to_iq5;
2244         __be32 iq6_to_iq8;
2245         __be32 iq9_to_iq11;
2246         __be32 iq12_to_iq14;
2247         __be32 iq15_to_iq17;
2248         __be32 iq18_to_iq20;
2249         __be32 iq21_to_iq23;
2250         __be32 iq24_to_iq26;
2251         __be32 iq27_to_iq29;
2252         __be32 iq30_iq31;
2253         __be32 r15_lo;
2254 };
2255
2256 struct fw_rss_glb_config_cmd {
2257         __be32 op_to_write;
2258         __be32 retval_len16;
2259         union fw_rss_glb_config {
2260                 struct fw_rss_glb_config_manual {
2261                         __be32 mode_pkd;
2262                         __be32 r3;
2263                         __be64 r4;
2264                         __be64 r5;
2265                 } manual;
2266                 struct fw_rss_glb_config_basicvirtual {
2267                         __be32 mode_pkd;
2268                         __be32 synmapen_to_hashtoeplitz;
2269 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN      (1U << 8)
2270 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
2271 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
2272 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
2273 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
2274 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN      (1U << 3)
2275 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN      (1U << 2)
2276 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP     (1U << 1)
2277 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ  (1U << 0)
2278                         __be64 r8;
2279                         __be64 r9;
2280                 } basicvirtual;
2281         } u;
2282 };
2283
2284 #define FW_RSS_GLB_CONFIG_CMD_MODE(x)   ((x) << 28)
2285 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
2286
2287 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2288 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2289
2290 struct fw_rss_vi_config_cmd {
2291         __be32 op_to_viid;
2292 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2293         __be32 retval_len16;
2294         union fw_rss_vi_config {
2295                 struct fw_rss_vi_config_manual {
2296                         __be64 r3;
2297                         __be64 r4;
2298                         __be64 r5;
2299                 } manual;
2300                 struct fw_rss_vi_config_basicvirtual {
2301                         __be32 r6;
2302                         __be32 defaultq_to_udpen;
2303 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)  ((x) << 16)
2304 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
2305 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
2306 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN  (1U << 3)
2307 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
2308 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN  (1U << 1)
2309 #define FW_RSS_VI_CONFIG_CMD_UDPEN        (1U << 0)
2310                         __be64 r9;
2311                         __be64 r10;
2312                 } basicvirtual;
2313         } u;
2314 };
2315
2316 struct fw_clip_cmd {
2317         __be32 op_to_write;
2318         __be32 alloc_to_len16;
2319         __be64 ip_hi;
2320         __be64 ip_lo;
2321         __be32 r4[2];
2322 };
2323
2324 #define S_FW_CLIP_CMD_ALLOC     31
2325 #define M_FW_CLIP_CMD_ALLOC     0x1
2326 #define V_FW_CLIP_CMD_ALLOC(x)  ((x) << S_FW_CLIP_CMD_ALLOC)
2327 #define G_FW_CLIP_CMD_ALLOC(x)  \
2328         (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
2329 #define F_FW_CLIP_CMD_ALLOC     V_FW_CLIP_CMD_ALLOC(1U)
2330
2331 #define S_FW_CLIP_CMD_FREE      30
2332 #define M_FW_CLIP_CMD_FREE      0x1
2333 #define V_FW_CLIP_CMD_FREE(x)   ((x) << S_FW_CLIP_CMD_FREE)
2334 #define G_FW_CLIP_CMD_FREE(x)   \
2335         (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
2336 #define F_FW_CLIP_CMD_FREE      V_FW_CLIP_CMD_FREE(1U)
2337
2338 enum fw_error_type {
2339         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2340         FW_ERROR_TYPE_HWMODULE          = 0x1,
2341         FW_ERROR_TYPE_WR                = 0x2,
2342         FW_ERROR_TYPE_ACL               = 0x3,
2343 };
2344
2345 struct fw_error_cmd {
2346         __be32 op_to_type;
2347         __be32 len16_pkd;
2348         union fw_error {
2349                 struct fw_error_exception {
2350                         __be32 info[6];
2351                 } exception;
2352                 struct fw_error_hwmodule {
2353                         __be32 regaddr;
2354                         __be32 regval;
2355                 } hwmodule;
2356                 struct fw_error_wr {
2357                         __be16 cidx;
2358                         __be16 pfn_vfn;
2359                         __be32 eqid;
2360                         u8 wrhdr[16];
2361                 } wr;
2362                 struct fw_error_acl {
2363                         __be16 cidx;
2364                         __be16 pfn_vfn;
2365                         __be32 eqid;
2366                         __be16 mv_pkd;
2367                         u8 val[6];
2368                         __be64 r4;
2369                 } acl;
2370         } u;
2371 };
2372
2373 struct fw_debug_cmd {
2374         __be32 op_type;
2375 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
2376         __be32 len16_pkd;
2377         union fw_debug {
2378                 struct fw_debug_assert {
2379                         __be32 fcid;
2380                         __be32 line;
2381                         __be32 x;
2382                         __be32 y;
2383                         u8 filename_0_7[8];
2384                         u8 filename_8_15[8];
2385                         __be64 r3;
2386                 } assert;
2387                 struct fw_debug_prt {
2388                         __be16 dprtstridx;
2389                         __be16 r3[3];
2390                         __be32 dprtstrparam0;
2391                         __be32 dprtstrparam1;
2392                         __be32 dprtstrparam2;
2393                         __be32 dprtstrparam3;
2394                 } prt;
2395         } u;
2396 };
2397
2398 #define FW_PCIE_FW_ERR           (1U << 31)
2399 #define FW_PCIE_FW_INIT          (1U << 30)
2400 #define FW_PCIE_FW_HALT          (1U << 29)
2401 #define FW_PCIE_FW_MASTER_VLD    (1U << 15)
2402 #define FW_PCIE_FW_MASTER_MASK   0x7
2403 #define FW_PCIE_FW_MASTER_SHIFT  12
2404 #define FW_PCIE_FW_MASTER(x)     ((x) << FW_PCIE_FW_MASTER_SHIFT)
2405 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
2406                                  FW_PCIE_FW_MASTER_MASK)
2407 #define FW_PCIE_FW_EVAL_MASK   0x7
2408 #define FW_PCIE_FW_EVAL_SHIFT  24
2409 #define FW_PCIE_FW_EVAL_GET(x) (((x) >> FW_PCIE_FW_EVAL_SHIFT) & \
2410                                  FW_PCIE_FW_EVAL_MASK)
2411
2412 struct fw_hdr {
2413         u8 ver;
2414         u8 chip;                        /* terminator chip type */
2415         __be16  len512;                 /* bin length in units of 512-bytes */
2416         __be32  fw_ver;                 /* firmware version */
2417         __be32  tp_microcode_ver;
2418         u8 intfver_nic;
2419         u8 intfver_vnic;
2420         u8 intfver_ofld;
2421         u8 intfver_ri;
2422         u8 intfver_iscsipdu;
2423         u8 intfver_iscsi;
2424         u8 intfver_fcoepdu;
2425         u8 intfver_fcoe;
2426         __u32   reserved2;
2427         __u32   reserved3;
2428         __u32   reserved4;
2429         __be32  flags;
2430         __be32  reserved6[23];
2431 };
2432
2433 enum fw_hdr_chip {
2434         FW_HDR_CHIP_T4,
2435         FW_HDR_CHIP_T5
2436 };
2437
2438 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
2439 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
2440 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
2441 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
2442
2443 enum fw_hdr_intfver {
2444         FW_HDR_INTFVER_NIC      = 0x00,
2445         FW_HDR_INTFVER_VNIC     = 0x00,
2446         FW_HDR_INTFVER_OFLD     = 0x00,
2447         FW_HDR_INTFVER_RI       = 0x00,
2448         FW_HDR_INTFVER_ISCSIPDU = 0x00,
2449         FW_HDR_INTFVER_ISCSI    = 0x00,
2450         FW_HDR_INTFVER_FCOEPDU  = 0x00,
2451         FW_HDR_INTFVER_FCOE     = 0x00,
2452 };
2453
2454 enum fw_hdr_flags {
2455         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
2456 };
2457
2458 #endif /* _T4FW_INTERFACE_H_ */