1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
92 #include <asm/mpc85xx.h>
94 #include <asm/uaccess.h>
95 #include <linux/module.h>
96 #include <linux/dma-mapping.h>
97 #include <linux/crc32.h>
98 #include <linux/mii.h>
99 #include <linux/phy.h>
100 #include <linux/phy_fixed.h>
101 #include <linux/of.h>
102 #include <linux/of_net.h>
106 #define TX_TIMEOUT (1*HZ)
108 const char gfar_driver_version[] = "1.3";
110 static int gfar_enet_open(struct net_device *dev);
111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
112 static void gfar_reset_task(struct work_struct *work);
113 static void gfar_timeout(struct net_device *dev);
114 static int gfar_close(struct net_device *dev);
115 struct sk_buff *gfar_new_skb(struct net_device *dev);
116 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
117 struct sk_buff *skb);
118 static int gfar_set_mac_address(struct net_device *dev);
119 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
120 static irqreturn_t gfar_error(int irq, void *dev_id);
121 static irqreturn_t gfar_transmit(int irq, void *dev_id);
122 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
123 static void adjust_link(struct net_device *dev);
124 static int init_phy(struct net_device *dev);
125 static int gfar_probe(struct platform_device *ofdev);
126 static int gfar_remove(struct platform_device *ofdev);
127 static void free_skb_resources(struct gfar_private *priv);
128 static void gfar_set_multi(struct net_device *dev);
129 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
130 static void gfar_configure_serdes(struct net_device *dev);
131 static int gfar_poll_rx(struct napi_struct *napi, int budget);
132 static int gfar_poll_tx(struct napi_struct *napi, int budget);
133 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
134 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
135 #ifdef CONFIG_NET_POLL_CONTROLLER
136 static void gfar_netpoll(struct net_device *dev);
138 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
139 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
140 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
141 int amount_pull, struct napi_struct *napi);
142 static void gfar_halt_nodisable(struct gfar_private *priv);
143 static void gfar_clear_exact_match(struct net_device *dev);
144 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
161 lstatus |= BD_LFLAG(RXBD_WRAP);
165 bdp->lstatus = lstatus;
168 static int gfar_init_bds(struct net_device *ndev)
170 struct gfar_private *priv = netdev_priv(ndev);
171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
194 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp->status |= TXBD_WRAP;
199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
209 gfar_init_rxbdp(rx_queue, rxbdp,
212 skb = gfar_new_skb(ndev);
214 netdev_err(ndev, "Can't allocate RX buffers\n");
217 rx_queue->rx_skbuff[j] = skb;
219 gfar_new_rxbdp(rx_queue, rxbdp, skb);
230 static int gfar_alloc_skb_resources(struct net_device *ndev)
235 struct gfar_private *priv = netdev_priv(ndev);
236 struct device *dev = priv->dev;
237 struct gfar_priv_tx_q *tx_queue = NULL;
238 struct gfar_priv_rx_q *rx_queue = NULL;
240 priv->total_tx_ring_size = 0;
241 for (i = 0; i < priv->num_tx_queues; i++)
242 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
244 priv->total_rx_ring_size = 0;
245 for (i = 0; i < priv->num_rx_queues; i++)
246 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
248 /* Allocate memory for the buffer descriptors */
249 vaddr = dma_alloc_coherent(dev,
250 (priv->total_tx_ring_size *
251 sizeof(struct txbd8)) +
252 (priv->total_rx_ring_size *
253 sizeof(struct rxbd8)),
258 for (i = 0; i < priv->num_tx_queues; i++) {
259 tx_queue = priv->tx_queue[i];
260 tx_queue->tx_bd_base = vaddr;
261 tx_queue->tx_bd_dma_base = addr;
262 tx_queue->dev = ndev;
263 /* enet DMA only understands physical addresses */
264 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
265 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
268 /* Start the rx descriptor ring where the tx ring leaves off */
269 for (i = 0; i < priv->num_rx_queues; i++) {
270 rx_queue = priv->rx_queue[i];
271 rx_queue->rx_bd_base = vaddr;
272 rx_queue->rx_bd_dma_base = addr;
273 rx_queue->dev = ndev;
274 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
275 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
278 /* Setup the skbuff rings */
279 for (i = 0; i < priv->num_tx_queues; i++) {
280 tx_queue = priv->tx_queue[i];
281 tx_queue->tx_skbuff =
282 kmalloc_array(tx_queue->tx_ring_size,
283 sizeof(*tx_queue->tx_skbuff),
285 if (!tx_queue->tx_skbuff)
288 for (k = 0; k < tx_queue->tx_ring_size; k++)
289 tx_queue->tx_skbuff[k] = NULL;
292 for (i = 0; i < priv->num_rx_queues; i++) {
293 rx_queue = priv->rx_queue[i];
294 rx_queue->rx_skbuff =
295 kmalloc_array(rx_queue->rx_ring_size,
296 sizeof(*rx_queue->rx_skbuff),
298 if (!rx_queue->rx_skbuff)
301 for (j = 0; j < rx_queue->rx_ring_size; j++)
302 rx_queue->rx_skbuff[j] = NULL;
305 if (gfar_init_bds(ndev))
311 free_skb_resources(priv);
315 static void gfar_init_tx_rx_base(struct gfar_private *priv)
317 struct gfar __iomem *regs = priv->gfargrp[0].regs;
321 baddr = ®s->tbase0;
322 for (i = 0; i < priv->num_tx_queues; i++) {
323 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
327 baddr = ®s->rbase0;
328 for (i = 0; i < priv->num_rx_queues; i++) {
329 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
334 static void gfar_rx_buff_size_config(struct gfar_private *priv)
336 int frame_size = priv->ndev->mtu + ETH_HLEN;
338 /* set this when rx hw offload (TOE) functions are being used */
339 priv->uses_rxfcb = 0;
341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
342 priv->uses_rxfcb = 1;
344 if (priv->hwts_rx_en)
345 priv->uses_rxfcb = 1;
347 if (priv->uses_rxfcb)
348 frame_size += GMAC_FCB_LEN;
350 frame_size += priv->padding;
352 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
353 INCREMENTAL_BUFFER_SIZE;
355 priv->rx_buffer_size = frame_size;
358 static void gfar_mac_rx_config(struct gfar_private *priv)
360 struct gfar __iomem *regs = priv->gfargrp[0].regs;
363 if (priv->rx_filer_enable) {
364 rctrl |= RCTRL_FILREN;
365 /* Program the RIR0 reg with the required distribution */
366 if (priv->poll_mode == GFAR_SQ_POLLING)
367 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
368 else /* GFAR_MQ_POLLING */
369 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
372 /* Restore PROMISC mode */
373 if (priv->ndev->flags & IFF_PROMISC)
376 if (priv->ndev->features & NETIF_F_RXCSUM)
377 rctrl |= RCTRL_CHECKSUMMING;
379 if (priv->extended_hash)
380 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
383 rctrl &= ~RCTRL_PAL_MASK;
384 rctrl |= RCTRL_PADDING(priv->padding);
387 /* Enable HW time stamping if requested from user space */
388 if (priv->hwts_rx_en)
389 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
391 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
392 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
394 /* Init rctrl based on our settings */
395 gfar_write(®s->rctrl, rctrl);
398 static void gfar_mac_tx_config(struct gfar_private *priv)
400 struct gfar __iomem *regs = priv->gfargrp[0].regs;
403 if (priv->ndev->features & NETIF_F_IP_CSUM)
404 tctrl |= TCTRL_INIT_CSUM;
406 if (priv->prio_sched_en)
407 tctrl |= TCTRL_TXSCHED_PRIO;
409 tctrl |= TCTRL_TXSCHED_WRRS;
410 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
411 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
414 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
415 tctrl |= TCTRL_VLINS;
417 gfar_write(®s->tctrl, tctrl);
420 static void gfar_configure_coalescing(struct gfar_private *priv,
421 unsigned long tx_mask, unsigned long rx_mask)
423 struct gfar __iomem *regs = priv->gfargrp[0].regs;
426 if (priv->mode == MQ_MG_MODE) {
429 baddr = ®s->txic0;
430 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
431 gfar_write(baddr + i, 0);
432 if (likely(priv->tx_queue[i]->txcoalescing))
433 gfar_write(baddr + i, priv->tx_queue[i]->txic);
436 baddr = ®s->rxic0;
437 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
438 gfar_write(baddr + i, 0);
439 if (likely(priv->rx_queue[i]->rxcoalescing))
440 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
443 /* Backward compatible case -- even if we enable
444 * multiple queues, there's only single reg to program
446 gfar_write(®s->txic, 0);
447 if (likely(priv->tx_queue[0]->txcoalescing))
448 gfar_write(®s->txic, priv->tx_queue[0]->txic);
450 gfar_write(®s->rxic, 0);
451 if (unlikely(priv->rx_queue[0]->rxcoalescing))
452 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
456 void gfar_configure_coalescing_all(struct gfar_private *priv)
458 gfar_configure_coalescing(priv, 0xFF, 0xFF);
461 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
463 struct gfar_private *priv = netdev_priv(dev);
464 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
465 unsigned long tx_packets = 0, tx_bytes = 0;
468 for (i = 0; i < priv->num_rx_queues; i++) {
469 rx_packets += priv->rx_queue[i]->stats.rx_packets;
470 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
471 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
474 dev->stats.rx_packets = rx_packets;
475 dev->stats.rx_bytes = rx_bytes;
476 dev->stats.rx_dropped = rx_dropped;
478 for (i = 0; i < priv->num_tx_queues; i++) {
479 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
480 tx_packets += priv->tx_queue[i]->stats.tx_packets;
483 dev->stats.tx_bytes = tx_bytes;
484 dev->stats.tx_packets = tx_packets;
489 static const struct net_device_ops gfar_netdev_ops = {
490 .ndo_open = gfar_enet_open,
491 .ndo_start_xmit = gfar_start_xmit,
492 .ndo_stop = gfar_close,
493 .ndo_change_mtu = gfar_change_mtu,
494 .ndo_set_features = gfar_set_features,
495 .ndo_set_rx_mode = gfar_set_multi,
496 .ndo_tx_timeout = gfar_timeout,
497 .ndo_do_ioctl = gfar_ioctl,
498 .ndo_get_stats = gfar_get_stats,
499 .ndo_set_mac_address = eth_mac_addr,
500 .ndo_validate_addr = eth_validate_addr,
501 #ifdef CONFIG_NET_POLL_CONTROLLER
502 .ndo_poll_controller = gfar_netpoll,
506 static void gfar_ints_disable(struct gfar_private *priv)
509 for (i = 0; i < priv->num_grps; i++) {
510 struct gfar __iomem *regs = priv->gfargrp[i].regs;
512 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
514 /* Initialize IMASK */
515 gfar_write(®s->imask, IMASK_INIT_CLEAR);
519 static void gfar_ints_enable(struct gfar_private *priv)
522 for (i = 0; i < priv->num_grps; i++) {
523 struct gfar __iomem *regs = priv->gfargrp[i].regs;
524 /* Unmask the interrupts we look for */
525 gfar_write(®s->imask, IMASK_DEFAULT);
529 void lock_tx_qs(struct gfar_private *priv)
533 for (i = 0; i < priv->num_tx_queues; i++)
534 spin_lock(&priv->tx_queue[i]->txlock);
537 void unlock_tx_qs(struct gfar_private *priv)
541 for (i = 0; i < priv->num_tx_queues; i++)
542 spin_unlock(&priv->tx_queue[i]->txlock);
545 static int gfar_alloc_tx_queues(struct gfar_private *priv)
549 for (i = 0; i < priv->num_tx_queues; i++) {
550 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
552 if (!priv->tx_queue[i])
555 priv->tx_queue[i]->tx_skbuff = NULL;
556 priv->tx_queue[i]->qindex = i;
557 priv->tx_queue[i]->dev = priv->ndev;
558 spin_lock_init(&(priv->tx_queue[i]->txlock));
563 static int gfar_alloc_rx_queues(struct gfar_private *priv)
567 for (i = 0; i < priv->num_rx_queues; i++) {
568 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
570 if (!priv->rx_queue[i])
573 priv->rx_queue[i]->rx_skbuff = NULL;
574 priv->rx_queue[i]->qindex = i;
575 priv->rx_queue[i]->dev = priv->ndev;
580 static void gfar_free_tx_queues(struct gfar_private *priv)
584 for (i = 0; i < priv->num_tx_queues; i++)
585 kfree(priv->tx_queue[i]);
588 static void gfar_free_rx_queues(struct gfar_private *priv)
592 for (i = 0; i < priv->num_rx_queues; i++)
593 kfree(priv->rx_queue[i]);
596 static void unmap_group_regs(struct gfar_private *priv)
600 for (i = 0; i < MAXGROUPS; i++)
601 if (priv->gfargrp[i].regs)
602 iounmap(priv->gfargrp[i].regs);
605 static void free_gfar_dev(struct gfar_private *priv)
609 for (i = 0; i < priv->num_grps; i++)
610 for (j = 0; j < GFAR_NUM_IRQS; j++) {
611 kfree(priv->gfargrp[i].irqinfo[j]);
612 priv->gfargrp[i].irqinfo[j] = NULL;
615 free_netdev(priv->ndev);
618 static void disable_napi(struct gfar_private *priv)
622 for (i = 0; i < priv->num_grps; i++) {
623 napi_disable(&priv->gfargrp[i].napi_rx);
624 napi_disable(&priv->gfargrp[i].napi_tx);
628 static void enable_napi(struct gfar_private *priv)
632 for (i = 0; i < priv->num_grps; i++) {
633 napi_enable(&priv->gfargrp[i].napi_rx);
634 napi_enable(&priv->gfargrp[i].napi_tx);
638 static int gfar_parse_group(struct device_node *np,
639 struct gfar_private *priv, const char *model)
641 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
644 for (i = 0; i < GFAR_NUM_IRQS; i++) {
645 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
647 if (!grp->irqinfo[i])
651 grp->regs = of_iomap(np, 0);
655 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
657 /* If we aren't the FEC we have multiple interrupts */
658 if (model && strcasecmp(model, "FEC")) {
659 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
660 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
661 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
662 gfar_irq(grp, RX)->irq == NO_IRQ ||
663 gfar_irq(grp, ER)->irq == NO_IRQ)
668 spin_lock_init(&grp->grplock);
669 if (priv->mode == MQ_MG_MODE) {
670 u32 *rxq_mask, *txq_mask;
671 rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
672 txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
674 if (priv->poll_mode == GFAR_SQ_POLLING) {
675 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
676 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
677 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
678 } else { /* GFAR_MQ_POLLING */
679 grp->rx_bit_map = rxq_mask ?
680 *rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
681 grp->tx_bit_map = txq_mask ?
682 *txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
685 grp->rx_bit_map = 0xFF;
686 grp->tx_bit_map = 0xFF;
689 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
690 * right to left, so we need to revert the 8 bits to get the q index
692 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
693 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
695 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
696 * also assign queues to groups
698 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
700 grp->rx_queue = priv->rx_queue[i];
701 grp->num_rx_queues++;
702 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
703 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
704 priv->rx_queue[i]->grp = grp;
707 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
709 grp->tx_queue = priv->tx_queue[i];
710 grp->num_tx_queues++;
711 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
712 priv->tqueue |= (TQUEUE_EN0 >> i);
713 priv->tx_queue[i]->grp = grp;
721 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
725 const void *mac_addr;
727 struct net_device *dev = NULL;
728 struct gfar_private *priv = NULL;
729 struct device_node *np = ofdev->dev.of_node;
730 struct device_node *child = NULL;
732 const u32 *stash_len;
733 const u32 *stash_idx;
734 unsigned int num_tx_qs, num_rx_qs;
735 u32 *tx_queues, *rx_queues;
736 unsigned short mode, poll_mode;
738 if (!np || !of_device_is_available(np))
741 if (of_device_is_compatible(np, "fsl,etsec2")) {
743 poll_mode = GFAR_SQ_POLLING;
746 poll_mode = GFAR_SQ_POLLING;
749 /* parse the num of HW tx and rx queues */
750 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
751 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
753 if (mode == SQ_SG_MODE) {
756 } else { /* MQ_MG_MODE */
757 if (poll_mode == GFAR_SQ_POLLING) {
758 num_tx_qs = 2; /* one txq per int group */
759 num_rx_qs = 2; /* one rxq per int group */
760 } else { /* GFAR_MQ_POLLING */
761 num_tx_qs = tx_queues ? *tx_queues : 1;
762 num_rx_qs = rx_queues ? *rx_queues : 1;
766 if (num_tx_qs > MAX_TX_QS) {
767 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
768 num_tx_qs, MAX_TX_QS);
769 pr_err("Cannot do alloc_etherdev, aborting\n");
773 if (num_rx_qs > MAX_RX_QS) {
774 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
775 num_rx_qs, MAX_RX_QS);
776 pr_err("Cannot do alloc_etherdev, aborting\n");
780 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
785 priv = netdev_priv(dev);
789 priv->poll_mode = poll_mode;
791 priv->num_tx_queues = num_tx_qs;
792 netif_set_real_num_rx_queues(dev, num_rx_qs);
793 priv->num_rx_queues = num_rx_qs;
795 err = gfar_alloc_tx_queues(priv);
797 goto tx_alloc_failed;
799 err = gfar_alloc_rx_queues(priv);
801 goto rx_alloc_failed;
803 /* Init Rx queue filer rule set linked list */
804 INIT_LIST_HEAD(&priv->rx_list.list);
805 priv->rx_list.count = 0;
806 mutex_init(&priv->rx_queue_access);
808 model = of_get_property(np, "model", NULL);
810 for (i = 0; i < MAXGROUPS; i++)
811 priv->gfargrp[i].regs = NULL;
813 /* Parse and initialize group specific information */
814 if (priv->mode == MQ_MG_MODE) {
815 for_each_child_of_node(np, child) {
816 err = gfar_parse_group(child, priv, model);
820 } else { /* SQ_SG_MODE */
821 err = gfar_parse_group(np, priv, model);
826 stash = of_get_property(np, "bd-stash", NULL);
829 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
830 priv->bd_stash_en = 1;
833 stash_len = of_get_property(np, "rx-stash-len", NULL);
836 priv->rx_stash_size = *stash_len;
838 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
841 priv->rx_stash_index = *stash_idx;
843 if (stash_len || stash_idx)
844 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
846 mac_addr = of_get_mac_address(np);
849 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
851 if (model && !strcasecmp(model, "TSEC"))
852 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
853 FSL_GIANFAR_DEV_HAS_COALESCE |
854 FSL_GIANFAR_DEV_HAS_RMON |
855 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
857 if (model && !strcasecmp(model, "eTSEC"))
858 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
859 FSL_GIANFAR_DEV_HAS_COALESCE |
860 FSL_GIANFAR_DEV_HAS_RMON |
861 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
862 FSL_GIANFAR_DEV_HAS_CSUM |
863 FSL_GIANFAR_DEV_HAS_VLAN |
864 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
865 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
866 FSL_GIANFAR_DEV_HAS_TIMER;
868 ctype = of_get_property(np, "phy-connection-type", NULL);
870 /* We only care about rgmii-id. The rest are autodetected */
871 if (ctype && !strcmp(ctype, "rgmii-id"))
872 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
874 priv->interface = PHY_INTERFACE_MODE_MII;
876 if (of_get_property(np, "fsl,magic-packet", NULL))
877 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
879 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
881 /* Find the TBI PHY. If it's not there, we don't support SGMII */
882 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
887 unmap_group_regs(priv);
889 gfar_free_rx_queues(priv);
891 gfar_free_tx_queues(priv);
896 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
898 struct hwtstamp_config config;
899 struct gfar_private *priv = netdev_priv(netdev);
901 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
904 /* reserved for future extensions */
908 switch (config.tx_type) {
909 case HWTSTAMP_TX_OFF:
910 priv->hwts_tx_en = 0;
913 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
915 priv->hwts_tx_en = 1;
921 switch (config.rx_filter) {
922 case HWTSTAMP_FILTER_NONE:
923 if (priv->hwts_rx_en) {
924 priv->hwts_rx_en = 0;
929 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
931 if (!priv->hwts_rx_en) {
932 priv->hwts_rx_en = 1;
935 config.rx_filter = HWTSTAMP_FILTER_ALL;
939 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
943 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
945 struct hwtstamp_config config;
946 struct gfar_private *priv = netdev_priv(netdev);
949 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
950 config.rx_filter = (priv->hwts_rx_en ?
951 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
953 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
957 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
959 struct gfar_private *priv = netdev_priv(dev);
961 if (!netif_running(dev))
964 if (cmd == SIOCSHWTSTAMP)
965 return gfar_hwtstamp_set(dev, rq);
966 if (cmd == SIOCGHWTSTAMP)
967 return gfar_hwtstamp_get(dev, rq);
972 return phy_mii_ioctl(priv->phydev, rq, cmd);
975 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
978 u32 rqfpr = FPR_FILER_MASK;
982 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
983 priv->ftp_rqfpr[rqfar] = rqfpr;
984 priv->ftp_rqfcr[rqfar] = rqfcr;
985 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
988 rqfcr = RQFCR_CMP_NOMATCH;
989 priv->ftp_rqfpr[rqfar] = rqfpr;
990 priv->ftp_rqfcr[rqfar] = rqfcr;
991 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
994 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
996 priv->ftp_rqfcr[rqfar] = rqfcr;
997 priv->ftp_rqfpr[rqfar] = rqfpr;
998 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1001 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1003 priv->ftp_rqfcr[rqfar] = rqfcr;
1004 priv->ftp_rqfpr[rqfar] = rqfpr;
1005 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1010 static void gfar_init_filer_table(struct gfar_private *priv)
1013 u32 rqfar = MAX_FILER_IDX;
1015 u32 rqfpr = FPR_FILER_MASK;
1018 rqfcr = RQFCR_CMP_MATCH;
1019 priv->ftp_rqfcr[rqfar] = rqfcr;
1020 priv->ftp_rqfpr[rqfar] = rqfpr;
1021 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1023 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1024 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1025 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1026 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1027 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1028 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1030 /* cur_filer_idx indicated the first non-masked rule */
1031 priv->cur_filer_idx = rqfar;
1033 /* Rest are masked rules */
1034 rqfcr = RQFCR_CMP_NOMATCH;
1035 for (i = 0; i < rqfar; i++) {
1036 priv->ftp_rqfcr[i] = rqfcr;
1037 priv->ftp_rqfpr[i] = rqfpr;
1038 gfar_write_filer(priv, i, rqfcr, rqfpr);
1042 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1044 unsigned int pvr = mfspr(SPRN_PVR);
1045 unsigned int svr = mfspr(SPRN_SVR);
1046 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1047 unsigned int rev = svr & 0xffff;
1049 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1050 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1051 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1052 priv->errata |= GFAR_ERRATA_74;
1054 /* MPC8313 and MPC837x all rev */
1055 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1056 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1057 priv->errata |= GFAR_ERRATA_76;
1059 /* MPC8313 Rev < 2.0 */
1060 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1061 priv->errata |= GFAR_ERRATA_12;
1064 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1066 unsigned int svr = mfspr(SPRN_SVR);
1068 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1069 priv->errata |= GFAR_ERRATA_12;
1070 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1071 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1072 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1075 static void gfar_detect_errata(struct gfar_private *priv)
1077 struct device *dev = &priv->ofdev->dev;
1079 /* no plans to fix */
1080 priv->errata |= GFAR_ERRATA_A002;
1082 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1083 __gfar_detect_errata_85xx(priv);
1084 else /* non-mpc85xx parts, i.e. e300 core based */
1085 __gfar_detect_errata_83xx(priv);
1088 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1092 void gfar_mac_reset(struct gfar_private *priv)
1094 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1097 /* Reset MAC layer */
1098 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1100 /* We need to delay at least 3 TX clocks */
1103 /* the soft reset bit is not self-resetting, so we need to
1104 * clear it before resuming normal operation
1106 gfar_write(®s->maccfg1, 0);
1110 /* Compute rx_buff_size based on config flags */
1111 gfar_rx_buff_size_config(priv);
1113 /* Initialize the max receive frame/buffer lengths */
1114 gfar_write(®s->maxfrm, priv->rx_buffer_size);
1115 gfar_write(®s->mrblr, priv->rx_buffer_size);
1117 /* Initialize the Minimum Frame Length Register */
1118 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1120 /* Initialize MACCFG2. */
1121 tempval = MACCFG2_INIT_SETTINGS;
1123 /* If the mtu is larger than the max size for standard
1124 * ethernet frames (ie, a jumbo frame), then set maccfg2
1125 * to allow huge frames, and to check the length
1127 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1128 gfar_has_errata(priv, GFAR_ERRATA_74))
1129 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1131 gfar_write(®s->maccfg2, tempval);
1133 /* Clear mac addr hash registers */
1134 gfar_write(®s->igaddr0, 0);
1135 gfar_write(®s->igaddr1, 0);
1136 gfar_write(®s->igaddr2, 0);
1137 gfar_write(®s->igaddr3, 0);
1138 gfar_write(®s->igaddr4, 0);
1139 gfar_write(®s->igaddr5, 0);
1140 gfar_write(®s->igaddr6, 0);
1141 gfar_write(®s->igaddr7, 0);
1143 gfar_write(®s->gaddr0, 0);
1144 gfar_write(®s->gaddr1, 0);
1145 gfar_write(®s->gaddr2, 0);
1146 gfar_write(®s->gaddr3, 0);
1147 gfar_write(®s->gaddr4, 0);
1148 gfar_write(®s->gaddr5, 0);
1149 gfar_write(®s->gaddr6, 0);
1150 gfar_write(®s->gaddr7, 0);
1152 if (priv->extended_hash)
1153 gfar_clear_exact_match(priv->ndev);
1155 gfar_mac_rx_config(priv);
1157 gfar_mac_tx_config(priv);
1159 gfar_set_mac_address(priv->ndev);
1161 gfar_set_multi(priv->ndev);
1163 /* clear ievent and imask before configuring coalescing */
1164 gfar_ints_disable(priv);
1166 /* Configure the coalescing support */
1167 gfar_configure_coalescing_all(priv);
1170 static void gfar_hw_init(struct gfar_private *priv)
1172 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1175 /* Stop the DMA engine now, in case it was running before
1176 * (The firmware could have used it, and left it running).
1180 gfar_mac_reset(priv);
1182 /* Zero out the rmon mib registers if it has them */
1183 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1184 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1186 /* Mask off the CAM interrupts */
1187 gfar_write(®s->rmon.cam1, 0xffffffff);
1188 gfar_write(®s->rmon.cam2, 0xffffffff);
1191 /* Initialize ECNTRL */
1192 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1194 /* Set the extraction length and index */
1195 attrs = ATTRELI_EL(priv->rx_stash_size) |
1196 ATTRELI_EI(priv->rx_stash_index);
1198 gfar_write(®s->attreli, attrs);
1200 /* Start with defaults, and add stashing
1201 * depending on driver parameters
1203 attrs = ATTR_INIT_SETTINGS;
1205 if (priv->bd_stash_en)
1206 attrs |= ATTR_BDSTASH;
1208 if (priv->rx_stash_size != 0)
1209 attrs |= ATTR_BUFSTASH;
1211 gfar_write(®s->attr, attrs);
1214 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1215 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1216 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1218 /* Program the interrupt steering regs, only for MG devices */
1219 if (priv->num_grps > 1)
1220 gfar_write_isrg(priv);
1223 static void __init gfar_init_addr_hash_table(struct gfar_private *priv)
1225 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1227 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1228 priv->extended_hash = 1;
1229 priv->hash_width = 9;
1231 priv->hash_regs[0] = ®s->igaddr0;
1232 priv->hash_regs[1] = ®s->igaddr1;
1233 priv->hash_regs[2] = ®s->igaddr2;
1234 priv->hash_regs[3] = ®s->igaddr3;
1235 priv->hash_regs[4] = ®s->igaddr4;
1236 priv->hash_regs[5] = ®s->igaddr5;
1237 priv->hash_regs[6] = ®s->igaddr6;
1238 priv->hash_regs[7] = ®s->igaddr7;
1239 priv->hash_regs[8] = ®s->gaddr0;
1240 priv->hash_regs[9] = ®s->gaddr1;
1241 priv->hash_regs[10] = ®s->gaddr2;
1242 priv->hash_regs[11] = ®s->gaddr3;
1243 priv->hash_regs[12] = ®s->gaddr4;
1244 priv->hash_regs[13] = ®s->gaddr5;
1245 priv->hash_regs[14] = ®s->gaddr6;
1246 priv->hash_regs[15] = ®s->gaddr7;
1249 priv->extended_hash = 0;
1250 priv->hash_width = 8;
1252 priv->hash_regs[0] = ®s->gaddr0;
1253 priv->hash_regs[1] = ®s->gaddr1;
1254 priv->hash_regs[2] = ®s->gaddr2;
1255 priv->hash_regs[3] = ®s->gaddr3;
1256 priv->hash_regs[4] = ®s->gaddr4;
1257 priv->hash_regs[5] = ®s->gaddr5;
1258 priv->hash_regs[6] = ®s->gaddr6;
1259 priv->hash_regs[7] = ®s->gaddr7;
1263 /* Set up the ethernet device structure, private data,
1264 * and anything else we need before we start
1266 static int gfar_probe(struct platform_device *ofdev)
1268 struct net_device *dev = NULL;
1269 struct gfar_private *priv = NULL;
1272 err = gfar_of_init(ofdev, &dev);
1277 priv = netdev_priv(dev);
1279 priv->ofdev = ofdev;
1280 priv->dev = &ofdev->dev;
1281 SET_NETDEV_DEV(dev, &ofdev->dev);
1283 spin_lock_init(&priv->bflock);
1284 INIT_WORK(&priv->reset_task, gfar_reset_task);
1286 platform_set_drvdata(ofdev, priv);
1288 gfar_detect_errata(priv);
1290 /* Set the dev->base_addr to the gfar reg region */
1291 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1293 /* Fill in the dev structure */
1294 dev->watchdog_timeo = TX_TIMEOUT;
1296 dev->netdev_ops = &gfar_netdev_ops;
1297 dev->ethtool_ops = &gfar_ethtool_ops;
1299 /* Register for napi ...We are registering NAPI for each grp */
1300 for (i = 0; i < priv->num_grps; i++) {
1301 if (priv->poll_mode == GFAR_SQ_POLLING) {
1302 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1303 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1304 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1305 gfar_poll_tx_sq, 2);
1307 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1308 gfar_poll_rx, GFAR_DEV_WEIGHT);
1309 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1314 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1315 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1317 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1318 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1321 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1322 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1323 NETIF_F_HW_VLAN_CTAG_RX;
1324 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1327 gfar_init_addr_hash_table(priv);
1329 /* Insert receive time stamps into padding alignment bytes */
1330 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1333 if (dev->features & NETIF_F_IP_CSUM ||
1334 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1335 dev->needed_headroom = GMAC_FCB_LEN;
1337 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1339 /* Initializing some of the rx/tx queue level parameters */
1340 for (i = 0; i < priv->num_tx_queues; i++) {
1341 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1342 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1343 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1344 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1347 for (i = 0; i < priv->num_rx_queues; i++) {
1348 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1349 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1350 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1353 /* always enable rx filer */
1354 priv->rx_filer_enable = 1;
1355 /* Enable most messages by default */
1356 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1357 /* use pritority h/w tx queue scheduling for single queue devices */
1358 if (priv->num_tx_queues == 1)
1359 priv->prio_sched_en = 1;
1361 set_bit(GFAR_DOWN, &priv->state);
1365 err = register_netdev(dev);
1368 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1372 /* Carrier starts down, phylib will bring it up */
1373 netif_carrier_off(dev);
1375 device_init_wakeup(&dev->dev,
1376 priv->device_flags &
1377 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1379 /* fill out IRQ number and name fields */
1380 for (i = 0; i < priv->num_grps; i++) {
1381 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1382 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1383 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1384 dev->name, "_g", '0' + i, "_tx");
1385 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1386 dev->name, "_g", '0' + i, "_rx");
1387 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1388 dev->name, "_g", '0' + i, "_er");
1390 strcpy(gfar_irq(grp, TX)->name, dev->name);
1393 /* Initialize the filer table */
1394 gfar_init_filer_table(priv);
1396 /* Print out the device info */
1397 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1399 /* Even more device info helps when determining which kernel
1400 * provided which set of benchmarks.
1402 netdev_info(dev, "Running with NAPI enabled\n");
1403 for (i = 0; i < priv->num_rx_queues; i++)
1404 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1405 i, priv->rx_queue[i]->rx_ring_size);
1406 for (i = 0; i < priv->num_tx_queues; i++)
1407 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1408 i, priv->tx_queue[i]->tx_ring_size);
1413 unmap_group_regs(priv);
1414 gfar_free_rx_queues(priv);
1415 gfar_free_tx_queues(priv);
1417 of_node_put(priv->phy_node);
1419 of_node_put(priv->tbi_node);
1420 free_gfar_dev(priv);
1424 static int gfar_remove(struct platform_device *ofdev)
1426 struct gfar_private *priv = platform_get_drvdata(ofdev);
1429 of_node_put(priv->phy_node);
1431 of_node_put(priv->tbi_node);
1433 unregister_netdev(priv->ndev);
1434 unmap_group_regs(priv);
1435 gfar_free_rx_queues(priv);
1436 gfar_free_tx_queues(priv);
1437 free_gfar_dev(priv);
1444 static int gfar_suspend(struct device *dev)
1446 struct gfar_private *priv = dev_get_drvdata(dev);
1447 struct net_device *ndev = priv->ndev;
1448 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1449 unsigned long flags;
1452 int magic_packet = priv->wol_en &&
1453 (priv->device_flags &
1454 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1456 netif_device_detach(ndev);
1458 if (netif_running(ndev)) {
1460 local_irq_save(flags);
1463 gfar_halt_nodisable(priv);
1465 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1466 tempval = gfar_read(®s->maccfg1);
1468 tempval &= ~MACCFG1_TX_EN;
1471 tempval &= ~MACCFG1_RX_EN;
1473 gfar_write(®s->maccfg1, tempval);
1476 local_irq_restore(flags);
1481 /* Enable interrupt on Magic Packet */
1482 gfar_write(®s->imask, IMASK_MAG);
1484 /* Enable Magic Packet mode */
1485 tempval = gfar_read(®s->maccfg2);
1486 tempval |= MACCFG2_MPEN;
1487 gfar_write(®s->maccfg2, tempval);
1489 phy_stop(priv->phydev);
1496 static int gfar_resume(struct device *dev)
1498 struct gfar_private *priv = dev_get_drvdata(dev);
1499 struct net_device *ndev = priv->ndev;
1500 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1501 unsigned long flags;
1503 int magic_packet = priv->wol_en &&
1504 (priv->device_flags &
1505 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1507 if (!netif_running(ndev)) {
1508 netif_device_attach(ndev);
1512 if (!magic_packet && priv->phydev)
1513 phy_start(priv->phydev);
1515 /* Disable Magic Packet mode, in case something
1518 local_irq_save(flags);
1521 tempval = gfar_read(®s->maccfg2);
1522 tempval &= ~MACCFG2_MPEN;
1523 gfar_write(®s->maccfg2, tempval);
1528 local_irq_restore(flags);
1530 netif_device_attach(ndev);
1537 static int gfar_restore(struct device *dev)
1539 struct gfar_private *priv = dev_get_drvdata(dev);
1540 struct net_device *ndev = priv->ndev;
1542 if (!netif_running(ndev)) {
1543 netif_device_attach(ndev);
1548 if (gfar_init_bds(ndev)) {
1549 free_skb_resources(priv);
1553 gfar_mac_reset(priv);
1555 gfar_init_tx_rx_base(priv);
1561 priv->oldduplex = -1;
1564 phy_start(priv->phydev);
1566 netif_device_attach(ndev);
1572 static struct dev_pm_ops gfar_pm_ops = {
1573 .suspend = gfar_suspend,
1574 .resume = gfar_resume,
1575 .freeze = gfar_suspend,
1576 .thaw = gfar_resume,
1577 .restore = gfar_restore,
1580 #define GFAR_PM_OPS (&gfar_pm_ops)
1584 #define GFAR_PM_OPS NULL
1588 /* Reads the controller's registers to determine what interface
1589 * connects it to the PHY.
1591 static phy_interface_t gfar_get_interface(struct net_device *dev)
1593 struct gfar_private *priv = netdev_priv(dev);
1594 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1597 ecntrl = gfar_read(®s->ecntrl);
1599 if (ecntrl & ECNTRL_SGMII_MODE)
1600 return PHY_INTERFACE_MODE_SGMII;
1602 if (ecntrl & ECNTRL_TBI_MODE) {
1603 if (ecntrl & ECNTRL_REDUCED_MODE)
1604 return PHY_INTERFACE_MODE_RTBI;
1606 return PHY_INTERFACE_MODE_TBI;
1609 if (ecntrl & ECNTRL_REDUCED_MODE) {
1610 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1611 return PHY_INTERFACE_MODE_RMII;
1614 phy_interface_t interface = priv->interface;
1616 /* This isn't autodetected right now, so it must
1617 * be set by the device tree or platform code.
1619 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1620 return PHY_INTERFACE_MODE_RGMII_ID;
1622 return PHY_INTERFACE_MODE_RGMII;
1626 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1627 return PHY_INTERFACE_MODE_GMII;
1629 return PHY_INTERFACE_MODE_MII;
1633 /* Initializes driver's PHY state, and attaches to the PHY.
1634 * Returns 0 on success.
1636 static int init_phy(struct net_device *dev)
1638 struct gfar_private *priv = netdev_priv(dev);
1639 uint gigabit_support =
1640 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1641 GFAR_SUPPORTED_GBIT : 0;
1642 phy_interface_t interface;
1646 priv->oldduplex = -1;
1648 interface = gfar_get_interface(dev);
1650 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1653 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1655 if (!priv->phydev) {
1656 dev_err(&dev->dev, "could not attach to PHY\n");
1660 if (interface == PHY_INTERFACE_MODE_SGMII)
1661 gfar_configure_serdes(dev);
1663 /* Remove any features not supported by the controller */
1664 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1665 priv->phydev->advertising = priv->phydev->supported;
1670 /* Initialize TBI PHY interface for communicating with the
1671 * SERDES lynx PHY on the chip. We communicate with this PHY
1672 * through the MDIO bus on each controller, treating it as a
1673 * "normal" PHY at the address found in the TBIPA register. We assume
1674 * that the TBIPA register is valid. Either the MDIO bus code will set
1675 * it to a value that doesn't conflict with other PHYs on the bus, or the
1676 * value doesn't matter, as there are no other PHYs on the bus.
1678 static void gfar_configure_serdes(struct net_device *dev)
1680 struct gfar_private *priv = netdev_priv(dev);
1681 struct phy_device *tbiphy;
1683 if (!priv->tbi_node) {
1684 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1685 "device tree specify a tbi-handle\n");
1689 tbiphy = of_phy_find_device(priv->tbi_node);
1691 dev_err(&dev->dev, "error: Could not get TBI device\n");
1695 /* If the link is already up, we must already be ok, and don't need to
1696 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1697 * everything for us? Resetting it takes the link down and requires
1698 * several seconds for it to come back.
1700 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1703 /* Single clk mode, mii mode off(for serdes communication) */
1704 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1706 phy_write(tbiphy, MII_ADVERTISE,
1707 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1708 ADVERTISE_1000XPSE_ASYM);
1710 phy_write(tbiphy, MII_BMCR,
1711 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1715 static int __gfar_is_rx_idle(struct gfar_private *priv)
1719 /* Normaly TSEC should not hang on GRS commands, so we should
1720 * actually wait for IEVENT_GRSC flag.
1722 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1725 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1726 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1727 * and the Rx can be safely reset.
1729 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1731 if ((res & 0xffff) == (res >> 16))
1737 /* Halt the receive and transmit queues */
1738 static void gfar_halt_nodisable(struct gfar_private *priv)
1740 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1743 gfar_ints_disable(priv);
1745 /* Stop the DMA, and wait for it to stop */
1746 tempval = gfar_read(®s->dmactrl);
1747 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1748 (DMACTRL_GRS | DMACTRL_GTS)) {
1751 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1752 gfar_write(®s->dmactrl, tempval);
1755 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1756 (IEVENT_GRSC | IEVENT_GTSC)) ==
1757 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1758 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1759 ret = __gfar_is_rx_idle(priv);
1764 /* Halt the receive and transmit queues */
1765 void gfar_halt(struct gfar_private *priv)
1767 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1770 /* Dissable the Rx/Tx hw queues */
1771 gfar_write(®s->rqueue, 0);
1772 gfar_write(®s->tqueue, 0);
1776 gfar_halt_nodisable(priv);
1778 /* Disable Rx/Tx DMA */
1779 tempval = gfar_read(®s->maccfg1);
1780 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1781 gfar_write(®s->maccfg1, tempval);
1784 void stop_gfar(struct net_device *dev)
1786 struct gfar_private *priv = netdev_priv(dev);
1788 netif_tx_stop_all_queues(dev);
1790 smp_mb__before_clear_bit();
1791 set_bit(GFAR_DOWN, &priv->state);
1792 smp_mb__after_clear_bit();
1796 /* disable ints and gracefully shut down Rx/Tx DMA */
1799 phy_stop(priv->phydev);
1801 free_skb_resources(priv);
1804 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1806 struct txbd8 *txbdp;
1807 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1810 txbdp = tx_queue->tx_bd_base;
1812 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1813 if (!tx_queue->tx_skbuff[i])
1816 dma_unmap_single(priv->dev, txbdp->bufPtr,
1817 txbdp->length, DMA_TO_DEVICE);
1819 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1822 dma_unmap_page(priv->dev, txbdp->bufPtr,
1823 txbdp->length, DMA_TO_DEVICE);
1826 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1827 tx_queue->tx_skbuff[i] = NULL;
1829 kfree(tx_queue->tx_skbuff);
1830 tx_queue->tx_skbuff = NULL;
1833 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1835 struct rxbd8 *rxbdp;
1836 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1839 rxbdp = rx_queue->rx_bd_base;
1841 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1842 if (rx_queue->rx_skbuff[i]) {
1843 dma_unmap_single(priv->dev, rxbdp->bufPtr,
1844 priv->rx_buffer_size,
1846 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1847 rx_queue->rx_skbuff[i] = NULL;
1853 kfree(rx_queue->rx_skbuff);
1854 rx_queue->rx_skbuff = NULL;
1857 /* If there are any tx skbs or rx skbs still around, free them.
1858 * Then free tx_skbuff and rx_skbuff
1860 static void free_skb_resources(struct gfar_private *priv)
1862 struct gfar_priv_tx_q *tx_queue = NULL;
1863 struct gfar_priv_rx_q *rx_queue = NULL;
1866 /* Go through all the buffer descriptors and free their data buffers */
1867 for (i = 0; i < priv->num_tx_queues; i++) {
1868 struct netdev_queue *txq;
1870 tx_queue = priv->tx_queue[i];
1871 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1872 if (tx_queue->tx_skbuff)
1873 free_skb_tx_queue(tx_queue);
1874 netdev_tx_reset_queue(txq);
1877 for (i = 0; i < priv->num_rx_queues; i++) {
1878 rx_queue = priv->rx_queue[i];
1879 if (rx_queue->rx_skbuff)
1880 free_skb_rx_queue(rx_queue);
1883 dma_free_coherent(priv->dev,
1884 sizeof(struct txbd8) * priv->total_tx_ring_size +
1885 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1886 priv->tx_queue[0]->tx_bd_base,
1887 priv->tx_queue[0]->tx_bd_dma_base);
1890 void gfar_start(struct gfar_private *priv)
1892 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1896 /* Enable Rx/Tx hw queues */
1897 gfar_write(®s->rqueue, priv->rqueue);
1898 gfar_write(®s->tqueue, priv->tqueue);
1900 /* Initialize DMACTRL to have WWR and WOP */
1901 tempval = gfar_read(®s->dmactrl);
1902 tempval |= DMACTRL_INIT_SETTINGS;
1903 gfar_write(®s->dmactrl, tempval);
1905 /* Make sure we aren't stopped */
1906 tempval = gfar_read(®s->dmactrl);
1907 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1908 gfar_write(®s->dmactrl, tempval);
1910 for (i = 0; i < priv->num_grps; i++) {
1911 regs = priv->gfargrp[i].regs;
1912 /* Clear THLT/RHLT, so that the DMA starts polling now */
1913 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1914 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1917 /* Enable Rx/Tx DMA */
1918 tempval = gfar_read(®s->maccfg1);
1919 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1920 gfar_write(®s->maccfg1, tempval);
1922 gfar_ints_enable(priv);
1924 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
1927 static void free_grp_irqs(struct gfar_priv_grp *grp)
1929 free_irq(gfar_irq(grp, TX)->irq, grp);
1930 free_irq(gfar_irq(grp, RX)->irq, grp);
1931 free_irq(gfar_irq(grp, ER)->irq, grp);
1934 static int register_grp_irqs(struct gfar_priv_grp *grp)
1936 struct gfar_private *priv = grp->priv;
1937 struct net_device *dev = priv->ndev;
1940 /* If the device has multiple interrupts, register for
1941 * them. Otherwise, only register for the one
1943 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1944 /* Install our interrupt handlers for Error,
1945 * Transmit, and Receive
1947 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
1948 gfar_irq(grp, ER)->name, grp);
1950 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1951 gfar_irq(grp, ER)->irq);
1955 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
1956 gfar_irq(grp, TX)->name, grp);
1958 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1959 gfar_irq(grp, TX)->irq);
1962 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
1963 gfar_irq(grp, RX)->name, grp);
1965 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1966 gfar_irq(grp, RX)->irq);
1970 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
1971 gfar_irq(grp, TX)->name, grp);
1973 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1974 gfar_irq(grp, TX)->irq);
1982 free_irq(gfar_irq(grp, TX)->irq, grp);
1984 free_irq(gfar_irq(grp, ER)->irq, grp);
1990 static void gfar_free_irq(struct gfar_private *priv)
1995 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1996 for (i = 0; i < priv->num_grps; i++)
1997 free_grp_irqs(&priv->gfargrp[i]);
1999 for (i = 0; i < priv->num_grps; i++)
2000 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2005 static int gfar_request_irq(struct gfar_private *priv)
2009 for (i = 0; i < priv->num_grps; i++) {
2010 err = register_grp_irqs(&priv->gfargrp[i]);
2012 for (j = 0; j < i; j++)
2013 free_grp_irqs(&priv->gfargrp[j]);
2021 /* Bring the controller up and running */
2022 int startup_gfar(struct net_device *ndev)
2024 struct gfar_private *priv = netdev_priv(ndev);
2027 gfar_mac_reset(priv);
2029 err = gfar_alloc_skb_resources(ndev);
2033 gfar_init_tx_rx_base(priv);
2035 smp_mb__before_clear_bit();
2036 clear_bit(GFAR_DOWN, &priv->state);
2037 smp_mb__after_clear_bit();
2039 /* Start Rx/Tx DMA and enable the interrupts */
2042 phy_start(priv->phydev);
2046 netif_tx_wake_all_queues(ndev);
2051 /* Called when something needs to use the ethernet device
2052 * Returns 0 for success.
2054 static int gfar_enet_open(struct net_device *dev)
2056 struct gfar_private *priv = netdev_priv(dev);
2059 err = init_phy(dev);
2063 err = gfar_request_irq(priv);
2067 err = startup_gfar(dev);
2071 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2076 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2078 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2080 memset(fcb, 0, GMAC_FCB_LEN);
2085 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2088 /* If we're here, it's a IP packet with a TCP or UDP
2089 * payload. We set it to checksum, using a pseudo-header
2092 u8 flags = TXFCB_DEFAULT;
2094 /* Tell the controller what the protocol is
2095 * And provide the already calculated phcs
2097 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2099 fcb->phcs = udp_hdr(skb)->check;
2101 fcb->phcs = tcp_hdr(skb)->check;
2103 /* l3os is the distance between the start of the
2104 * frame (skb->data) and the start of the IP hdr.
2105 * l4os is the distance between the start of the
2106 * l3 hdr and the l4 hdr
2108 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2109 fcb->l4os = skb_network_header_len(skb);
2114 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2116 fcb->flags |= TXFCB_VLN;
2117 fcb->vlctl = vlan_tx_tag_get(skb);
2120 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2121 struct txbd8 *base, int ring_size)
2123 struct txbd8 *new_bd = bdp + stride;
2125 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2128 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2131 return skip_txbd(bdp, 1, base, ring_size);
2134 /* eTSEC12: csum generation not supported for some fcb offsets */
2135 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2136 unsigned long fcb_addr)
2138 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2139 (fcb_addr % 0x20) > 0x18);
2142 /* eTSEC76: csum generation for frames larger than 2500 may
2143 * cause excess delays before start of transmission
2145 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2148 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2152 /* This is called by the kernel when a frame is ready for transmission.
2153 * It is pointed to by the dev->hard_start_xmit function pointer
2155 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2157 struct gfar_private *priv = netdev_priv(dev);
2158 struct gfar_priv_tx_q *tx_queue = NULL;
2159 struct netdev_queue *txq;
2160 struct gfar __iomem *regs = NULL;
2161 struct txfcb *fcb = NULL;
2162 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2165 int do_tstamp, do_csum, do_vlan;
2167 unsigned long flags;
2168 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2170 rq = skb->queue_mapping;
2171 tx_queue = priv->tx_queue[rq];
2172 txq = netdev_get_tx_queue(dev, rq);
2173 base = tx_queue->tx_bd_base;
2174 regs = tx_queue->grp->regs;
2176 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2177 do_vlan = vlan_tx_tag_present(skb);
2178 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2181 if (do_csum || do_vlan)
2182 fcb_len = GMAC_FCB_LEN;
2184 /* check if time stamp should be generated */
2185 if (unlikely(do_tstamp))
2186 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2188 /* make space for additional header when fcb is needed */
2189 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2190 struct sk_buff *skb_new;
2192 skb_new = skb_realloc_headroom(skb, fcb_len);
2194 dev->stats.tx_errors++;
2195 dev_kfree_skb_any(skb);
2196 return NETDEV_TX_OK;
2200 skb_set_owner_w(skb_new, skb->sk);
2201 dev_consume_skb_any(skb);
2205 /* total number of fragments in the SKB */
2206 nr_frags = skb_shinfo(skb)->nr_frags;
2208 /* calculate the required number of TxBDs for this skb */
2209 if (unlikely(do_tstamp))
2210 nr_txbds = nr_frags + 2;
2212 nr_txbds = nr_frags + 1;
2214 /* check if there is space to queue this packet */
2215 if (nr_txbds > tx_queue->num_txbdfree) {
2216 /* no space, stop the queue */
2217 netif_tx_stop_queue(txq);
2218 dev->stats.tx_fifo_errors++;
2219 return NETDEV_TX_BUSY;
2222 /* Update transmit stats */
2223 bytes_sent = skb->len;
2224 tx_queue->stats.tx_bytes += bytes_sent;
2225 /* keep Tx bytes on wire for BQL accounting */
2226 GFAR_CB(skb)->bytes_sent = bytes_sent;
2227 tx_queue->stats.tx_packets++;
2229 txbdp = txbdp_start = tx_queue->cur_tx;
2230 lstatus = txbdp->lstatus;
2232 /* Time stamp insertion requires one additional TxBD */
2233 if (unlikely(do_tstamp))
2234 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2235 tx_queue->tx_ring_size);
2237 if (nr_frags == 0) {
2238 if (unlikely(do_tstamp))
2239 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2242 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2244 /* Place the fragment addresses and lengths into the TxBDs */
2245 for (i = 0; i < nr_frags; i++) {
2246 unsigned int frag_len;
2247 /* Point at the next BD, wrapping as needed */
2248 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2250 frag_len = skb_shinfo(skb)->frags[i].size;
2252 lstatus = txbdp->lstatus | frag_len |
2253 BD_LFLAG(TXBD_READY);
2255 /* Handle the last BD specially */
2256 if (i == nr_frags - 1)
2257 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2259 bufaddr = skb_frag_dma_map(priv->dev,
2260 &skb_shinfo(skb)->frags[i],
2265 /* set the TxBD length and buffer pointer */
2266 txbdp->bufPtr = bufaddr;
2267 txbdp->lstatus = lstatus;
2270 lstatus = txbdp_start->lstatus;
2273 /* Add TxPAL between FCB and frame if required */
2274 if (unlikely(do_tstamp)) {
2275 skb_push(skb, GMAC_TXPAL_LEN);
2276 memset(skb->data, 0, GMAC_TXPAL_LEN);
2279 /* Add TxFCB if required */
2281 fcb = gfar_add_fcb(skb);
2282 lstatus |= BD_LFLAG(TXBD_TOE);
2285 /* Set up checksumming */
2287 gfar_tx_checksum(skb, fcb, fcb_len);
2289 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2290 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2291 __skb_pull(skb, GMAC_FCB_LEN);
2292 skb_checksum_help(skb);
2293 if (do_vlan || do_tstamp) {
2294 /* put back a new fcb for vlan/tstamp TOE */
2295 fcb = gfar_add_fcb(skb);
2297 /* Tx TOE not used */
2298 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2305 gfar_tx_vlan(skb, fcb);
2307 /* Setup tx hardware time stamping if requested */
2308 if (unlikely(do_tstamp)) {
2309 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2313 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
2314 skb_headlen(skb), DMA_TO_DEVICE);
2316 /* If time stamping is requested one additional TxBD must be set up. The
2317 * first TxBD points to the FCB and must have a data length of
2318 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2319 * the full frame length.
2321 if (unlikely(do_tstamp)) {
2322 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
2323 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2324 (skb_headlen(skb) - fcb_len);
2325 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2327 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2330 netdev_tx_sent_queue(txq, bytes_sent);
2332 /* We can work in parallel with gfar_clean_tx_ring(), except
2333 * when modifying num_txbdfree. Note that we didn't grab the lock
2334 * when we were reading the num_txbdfree and checking for available
2335 * space, that's because outside of this function it can only grow,
2336 * and once we've got needed space, it cannot suddenly disappear.
2338 * The lock also protects us from gfar_error(), which can modify
2339 * regs->tstat and thus retrigger the transfers, which is why we
2340 * also must grab the lock before setting ready bit for the first
2341 * to be transmitted BD.
2343 spin_lock_irqsave(&tx_queue->txlock, flags);
2345 /* The powerpc-specific eieio() is used, as wmb() has too strong
2346 * semantics (it requires synchronization between cacheable and
2347 * uncacheable mappings, which eieio doesn't provide and which we
2348 * don't need), thus requiring a more expensive sync instruction. At
2349 * some point, the set of architecture-independent barrier functions
2350 * should be expanded to include weaker barriers.
2354 txbdp_start->lstatus = lstatus;
2356 eieio(); /* force lstatus write before tx_skbuff */
2358 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2360 /* Update the current skb pointer to the next entry we will use
2361 * (wrapping if necessary)
2363 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2364 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2366 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2368 /* reduce TxBD free count */
2369 tx_queue->num_txbdfree -= (nr_txbds);
2371 /* If the next BD still needs to be cleaned up, then the bds
2372 * are full. We need to tell the kernel to stop sending us stuff.
2374 if (!tx_queue->num_txbdfree) {
2375 netif_tx_stop_queue(txq);
2377 dev->stats.tx_fifo_errors++;
2380 /* Tell the DMA to go go go */
2381 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2384 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2386 return NETDEV_TX_OK;
2389 /* Stops the kernel queue, and halts the controller */
2390 static int gfar_close(struct net_device *dev)
2392 struct gfar_private *priv = netdev_priv(dev);
2394 cancel_work_sync(&priv->reset_task);
2397 /* Disconnect from the PHY */
2398 phy_disconnect(priv->phydev);
2399 priv->phydev = NULL;
2401 gfar_free_irq(priv);
2406 /* Changes the mac address if the controller is not running. */
2407 static int gfar_set_mac_address(struct net_device *dev)
2409 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2414 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2416 struct gfar_private *priv = netdev_priv(dev);
2417 int frame_size = new_mtu + ETH_HLEN;
2419 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2420 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2424 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2427 if (dev->flags & IFF_UP)
2432 if (dev->flags & IFF_UP)
2435 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2440 void reset_gfar(struct net_device *ndev)
2442 struct gfar_private *priv = netdev_priv(ndev);
2444 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2450 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2453 /* gfar_reset_task gets scheduled when a packet has not been
2454 * transmitted after a set amount of time.
2455 * For now, assume that clearing out all the structures, and
2456 * starting over will fix the problem.
2458 static void gfar_reset_task(struct work_struct *work)
2460 struct gfar_private *priv = container_of(work, struct gfar_private,
2462 reset_gfar(priv->ndev);
2465 static void gfar_timeout(struct net_device *dev)
2467 struct gfar_private *priv = netdev_priv(dev);
2469 dev->stats.tx_errors++;
2470 schedule_work(&priv->reset_task);
2473 static void gfar_align_skb(struct sk_buff *skb)
2475 /* We need the data buffer to be aligned properly. We will reserve
2476 * as many bytes as needed to align the data properly
2478 skb_reserve(skb, RXBUF_ALIGNMENT -
2479 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2482 /* Interrupt Handler for Transmit complete */
2483 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2485 struct net_device *dev = tx_queue->dev;
2486 struct netdev_queue *txq;
2487 struct gfar_private *priv = netdev_priv(dev);
2488 struct txbd8 *bdp, *next = NULL;
2489 struct txbd8 *lbdp = NULL;
2490 struct txbd8 *base = tx_queue->tx_bd_base;
2491 struct sk_buff *skb;
2493 int tx_ring_size = tx_queue->tx_ring_size;
2494 int frags = 0, nr_txbds = 0;
2497 int tqi = tx_queue->qindex;
2498 unsigned int bytes_sent = 0;
2502 txq = netdev_get_tx_queue(dev, tqi);
2503 bdp = tx_queue->dirty_tx;
2504 skb_dirtytx = tx_queue->skb_dirtytx;
2506 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2507 unsigned long flags;
2509 frags = skb_shinfo(skb)->nr_frags;
2511 /* When time stamping, one additional TxBD must be freed.
2512 * Also, we need to dma_unmap_single() the TxPAL.
2514 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2515 nr_txbds = frags + 2;
2517 nr_txbds = frags + 1;
2519 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2521 lstatus = lbdp->lstatus;
2523 /* Only clean completed frames */
2524 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2525 (lstatus & BD_LENGTH_MASK))
2528 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2529 next = next_txbd(bdp, base, tx_ring_size);
2530 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2532 buflen = bdp->length;
2534 dma_unmap_single(priv->dev, bdp->bufPtr,
2535 buflen, DMA_TO_DEVICE);
2537 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2538 struct skb_shared_hwtstamps shhwtstamps;
2539 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2541 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2542 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2543 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2544 skb_tstamp_tx(skb, &shhwtstamps);
2545 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2549 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2550 bdp = next_txbd(bdp, base, tx_ring_size);
2552 for (i = 0; i < frags; i++) {
2553 dma_unmap_page(priv->dev, bdp->bufPtr,
2554 bdp->length, DMA_TO_DEVICE);
2555 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2556 bdp = next_txbd(bdp, base, tx_ring_size);
2559 bytes_sent += GFAR_CB(skb)->bytes_sent;
2561 dev_kfree_skb_any(skb);
2563 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2565 skb_dirtytx = (skb_dirtytx + 1) &
2566 TX_RING_MOD_MASK(tx_ring_size);
2569 spin_lock_irqsave(&tx_queue->txlock, flags);
2570 tx_queue->num_txbdfree += nr_txbds;
2571 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2574 /* If we freed a buffer, we can restart transmission, if necessary */
2575 if (tx_queue->num_txbdfree &&
2576 netif_tx_queue_stopped(txq) &&
2577 !(test_bit(GFAR_DOWN, &priv->state)))
2578 netif_wake_subqueue(priv->ndev, tqi);
2580 /* Update dirty indicators */
2581 tx_queue->skb_dirtytx = skb_dirtytx;
2582 tx_queue->dirty_tx = bdp;
2584 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2587 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2588 struct sk_buff *skb)
2590 struct net_device *dev = rx_queue->dev;
2591 struct gfar_private *priv = netdev_priv(dev);
2594 buf = dma_map_single(priv->dev, skb->data,
2595 priv->rx_buffer_size, DMA_FROM_DEVICE);
2596 gfar_init_rxbdp(rx_queue, bdp, buf);
2599 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2601 struct gfar_private *priv = netdev_priv(dev);
2602 struct sk_buff *skb;
2604 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2608 gfar_align_skb(skb);
2613 struct sk_buff *gfar_new_skb(struct net_device *dev)
2615 return gfar_alloc_skb(dev);
2618 static inline void count_errors(unsigned short status, struct net_device *dev)
2620 struct gfar_private *priv = netdev_priv(dev);
2621 struct net_device_stats *stats = &dev->stats;
2622 struct gfar_extra_stats *estats = &priv->extra_stats;
2624 /* If the packet was truncated, none of the other errors matter */
2625 if (status & RXBD_TRUNCATED) {
2626 stats->rx_length_errors++;
2628 atomic64_inc(&estats->rx_trunc);
2632 /* Count the errors, if there were any */
2633 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2634 stats->rx_length_errors++;
2636 if (status & RXBD_LARGE)
2637 atomic64_inc(&estats->rx_large);
2639 atomic64_inc(&estats->rx_short);
2641 if (status & RXBD_NONOCTET) {
2642 stats->rx_frame_errors++;
2643 atomic64_inc(&estats->rx_nonoctet);
2645 if (status & RXBD_CRCERR) {
2646 atomic64_inc(&estats->rx_crcerr);
2647 stats->rx_crc_errors++;
2649 if (status & RXBD_OVERRUN) {
2650 atomic64_inc(&estats->rx_overrun);
2651 stats->rx_crc_errors++;
2655 irqreturn_t gfar_receive(int irq, void *grp_id)
2657 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2658 unsigned long flags;
2661 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2662 spin_lock_irqsave(&grp->grplock, flags);
2663 imask = gfar_read(&grp->regs->imask);
2664 imask &= IMASK_RX_DISABLED;
2665 gfar_write(&grp->regs->imask, imask);
2666 spin_unlock_irqrestore(&grp->grplock, flags);
2667 __napi_schedule(&grp->napi_rx);
2669 /* Clear IEVENT, so interrupts aren't called again
2670 * because of the packets that have already arrived.
2672 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2678 /* Interrupt Handler for Transmit complete */
2679 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2681 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2682 unsigned long flags;
2685 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2686 spin_lock_irqsave(&grp->grplock, flags);
2687 imask = gfar_read(&grp->regs->imask);
2688 imask &= IMASK_TX_DISABLED;
2689 gfar_write(&grp->regs->imask, imask);
2690 spin_unlock_irqrestore(&grp->grplock, flags);
2691 __napi_schedule(&grp->napi_tx);
2693 /* Clear IEVENT, so interrupts aren't called again
2694 * because of the packets that have already arrived.
2696 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2702 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2704 /* If valid headers were found, and valid sums
2705 * were verified, then we tell the kernel that no
2706 * checksumming is necessary. Otherwise, it is [FIXME]
2708 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2709 skb->ip_summed = CHECKSUM_UNNECESSARY;
2711 skb_checksum_none_assert(skb);
2715 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2716 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2717 int amount_pull, struct napi_struct *napi)
2719 struct gfar_private *priv = netdev_priv(dev);
2720 struct rxfcb *fcb = NULL;
2722 /* fcb is at the beginning if exists */
2723 fcb = (struct rxfcb *)skb->data;
2725 /* Remove the FCB from the skb
2726 * Remove the padded bytes, if there are any
2729 skb_record_rx_queue(skb, fcb->rq);
2730 skb_pull(skb, amount_pull);
2733 /* Get receive timestamp from the skb */
2734 if (priv->hwts_rx_en) {
2735 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2736 u64 *ns = (u64 *) skb->data;
2738 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2739 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2743 skb_pull(skb, priv->padding);
2745 if (dev->features & NETIF_F_RXCSUM)
2746 gfar_rx_checksum(skb, fcb);
2748 /* Tell the skb what kind of packet this is */
2749 skb->protocol = eth_type_trans(skb, dev);
2751 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2752 * Even if vlan rx accel is disabled, on some chips
2753 * RXFCB_VLN is pseudo randomly set.
2755 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2756 fcb->flags & RXFCB_VLN)
2757 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl);
2759 /* Send the packet up the stack */
2760 napi_gro_receive(napi, skb);
2764 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2765 * until the budget/quota has been reached. Returns the number
2768 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2770 struct net_device *dev = rx_queue->dev;
2771 struct rxbd8 *bdp, *base;
2772 struct sk_buff *skb;
2776 struct gfar_private *priv = netdev_priv(dev);
2778 /* Get the first full descriptor */
2779 bdp = rx_queue->cur_rx;
2780 base = rx_queue->rx_bd_base;
2782 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2784 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2785 struct sk_buff *newskb;
2789 /* Add another skb for the future */
2790 newskb = gfar_new_skb(dev);
2792 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2794 dma_unmap_single(priv->dev, bdp->bufPtr,
2795 priv->rx_buffer_size, DMA_FROM_DEVICE);
2797 if (unlikely(!(bdp->status & RXBD_ERR) &&
2798 bdp->length > priv->rx_buffer_size))
2799 bdp->status = RXBD_LARGE;
2801 /* We drop the frame if we failed to allocate a new buffer */
2802 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2803 bdp->status & RXBD_ERR)) {
2804 count_errors(bdp->status, dev);
2806 if (unlikely(!newskb))
2811 /* Increment the number of packets */
2812 rx_queue->stats.rx_packets++;
2816 pkt_len = bdp->length - ETH_FCS_LEN;
2817 /* Remove the FCS from the packet length */
2818 skb_put(skb, pkt_len);
2819 rx_queue->stats.rx_bytes += pkt_len;
2820 skb_record_rx_queue(skb, rx_queue->qindex);
2821 gfar_process_frame(dev, skb, amount_pull,
2822 &rx_queue->grp->napi_rx);
2825 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2826 rx_queue->stats.rx_dropped++;
2827 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2832 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2834 /* Setup the new bdp */
2835 gfar_new_rxbdp(rx_queue, bdp, newskb);
2837 /* Update to the next pointer */
2838 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2840 /* update to point at the next skb */
2841 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2842 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2845 /* Update the current rxbd pointer to be the next one */
2846 rx_queue->cur_rx = bdp;
2851 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2853 struct gfar_priv_grp *gfargrp =
2854 container_of(napi, struct gfar_priv_grp, napi_rx);
2855 struct gfar __iomem *regs = gfargrp->regs;
2856 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2859 /* Clear IEVENT, so interrupts aren't called again
2860 * because of the packets that have already arrived
2862 gfar_write(®s->ievent, IEVENT_RX_MASK);
2864 work_done = gfar_clean_rx_ring(rx_queue, budget);
2866 if (work_done < budget) {
2868 napi_complete(napi);
2869 /* Clear the halt bit in RSTAT */
2870 gfar_write(®s->rstat, gfargrp->rstat);
2872 spin_lock_irq(&gfargrp->grplock);
2873 imask = gfar_read(®s->imask);
2874 imask |= IMASK_RX_DEFAULT;
2875 gfar_write(®s->imask, imask);
2876 spin_unlock_irq(&gfargrp->grplock);
2882 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2884 struct gfar_priv_grp *gfargrp =
2885 container_of(napi, struct gfar_priv_grp, napi_tx);
2886 struct gfar __iomem *regs = gfargrp->regs;
2887 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2890 /* Clear IEVENT, so interrupts aren't called again
2891 * because of the packets that have already arrived
2893 gfar_write(®s->ievent, IEVENT_TX_MASK);
2895 /* run Tx cleanup to completion */
2896 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2897 gfar_clean_tx_ring(tx_queue);
2899 napi_complete(napi);
2901 spin_lock_irq(&gfargrp->grplock);
2902 imask = gfar_read(®s->imask);
2903 imask |= IMASK_TX_DEFAULT;
2904 gfar_write(®s->imask, imask);
2905 spin_unlock_irq(&gfargrp->grplock);
2910 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2912 struct gfar_priv_grp *gfargrp =
2913 container_of(napi, struct gfar_priv_grp, napi_rx);
2914 struct gfar_private *priv = gfargrp->priv;
2915 struct gfar __iomem *regs = gfargrp->regs;
2916 struct gfar_priv_rx_q *rx_queue = NULL;
2917 int work_done = 0, work_done_per_q = 0;
2918 int i, budget_per_q = 0;
2919 unsigned long rstat_rxf;
2922 /* Clear IEVENT, so interrupts aren't called again
2923 * because of the packets that have already arrived
2925 gfar_write(®s->ievent, IEVENT_RX_MASK);
2927 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
2929 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2931 budget_per_q = budget/num_act_queues;
2933 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2934 /* skip queue if not active */
2935 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2938 rx_queue = priv->rx_queue[i];
2940 gfar_clean_rx_ring(rx_queue, budget_per_q);
2941 work_done += work_done_per_q;
2943 /* finished processing this queue */
2944 if (work_done_per_q < budget_per_q) {
2945 /* clear active queue hw indication */
2946 gfar_write(®s->rstat,
2947 RSTAT_CLEAR_RXF0 >> i);
2950 if (!num_act_queues)
2955 if (!num_act_queues) {
2957 napi_complete(napi);
2959 /* Clear the halt bit in RSTAT */
2960 gfar_write(®s->rstat, gfargrp->rstat);
2962 spin_lock_irq(&gfargrp->grplock);
2963 imask = gfar_read(®s->imask);
2964 imask |= IMASK_RX_DEFAULT;
2965 gfar_write(®s->imask, imask);
2966 spin_unlock_irq(&gfargrp->grplock);
2972 static int gfar_poll_tx(struct napi_struct *napi, int budget)
2974 struct gfar_priv_grp *gfargrp =
2975 container_of(napi, struct gfar_priv_grp, napi_tx);
2976 struct gfar_private *priv = gfargrp->priv;
2977 struct gfar __iomem *regs = gfargrp->regs;
2978 struct gfar_priv_tx_q *tx_queue = NULL;
2979 int has_tx_work = 0;
2982 /* Clear IEVENT, so interrupts aren't called again
2983 * because of the packets that have already arrived
2985 gfar_write(®s->ievent, IEVENT_TX_MASK);
2987 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2988 tx_queue = priv->tx_queue[i];
2989 /* run Tx cleanup to completion */
2990 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2991 gfar_clean_tx_ring(tx_queue);
2998 napi_complete(napi);
3000 spin_lock_irq(&gfargrp->grplock);
3001 imask = gfar_read(®s->imask);
3002 imask |= IMASK_TX_DEFAULT;
3003 gfar_write(®s->imask, imask);
3004 spin_unlock_irq(&gfargrp->grplock);
3011 #ifdef CONFIG_NET_POLL_CONTROLLER
3012 /* Polling 'interrupt' - used by things like netconsole to send skbs
3013 * without having to re-enable interrupts. It's not called while
3014 * the interrupt routine is executing.
3016 static void gfar_netpoll(struct net_device *dev)
3018 struct gfar_private *priv = netdev_priv(dev);
3021 /* If the device has multiple interrupts, run tx/rx */
3022 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3023 for (i = 0; i < priv->num_grps; i++) {
3024 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3026 disable_irq(gfar_irq(grp, TX)->irq);
3027 disable_irq(gfar_irq(grp, RX)->irq);
3028 disable_irq(gfar_irq(grp, ER)->irq);
3029 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3030 enable_irq(gfar_irq(grp, ER)->irq);
3031 enable_irq(gfar_irq(grp, RX)->irq);
3032 enable_irq(gfar_irq(grp, TX)->irq);
3035 for (i = 0; i < priv->num_grps; i++) {
3036 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3038 disable_irq(gfar_irq(grp, TX)->irq);
3039 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3040 enable_irq(gfar_irq(grp, TX)->irq);
3046 /* The interrupt handler for devices with one interrupt */
3047 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3049 struct gfar_priv_grp *gfargrp = grp_id;
3051 /* Save ievent for future reference */
3052 u32 events = gfar_read(&gfargrp->regs->ievent);
3054 /* Check for reception */
3055 if (events & IEVENT_RX_MASK)
3056 gfar_receive(irq, grp_id);
3058 /* Check for transmit completion */
3059 if (events & IEVENT_TX_MASK)
3060 gfar_transmit(irq, grp_id);
3062 /* Check for errors */
3063 if (events & IEVENT_ERR_MASK)
3064 gfar_error(irq, grp_id);
3069 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3071 struct phy_device *phydev = priv->phydev;
3074 if (!phydev->duplex)
3077 if (!priv->pause_aneg_en) {
3078 if (priv->tx_pause_en)
3079 val |= MACCFG1_TX_FLOW;
3080 if (priv->rx_pause_en)
3081 val |= MACCFG1_RX_FLOW;
3083 u16 lcl_adv, rmt_adv;
3085 /* get link partner capabilities */
3088 rmt_adv = LPA_PAUSE_CAP;
3089 if (phydev->asym_pause)
3090 rmt_adv |= LPA_PAUSE_ASYM;
3092 lcl_adv = mii_advertise_flowctrl(phydev->advertising);
3094 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3095 if (flowctrl & FLOW_CTRL_TX)
3096 val |= MACCFG1_TX_FLOW;
3097 if (flowctrl & FLOW_CTRL_RX)
3098 val |= MACCFG1_RX_FLOW;
3104 /* Called every time the controller might need to be made
3105 * aware of new link state. The PHY code conveys this
3106 * information through variables in the phydev structure, and this
3107 * function converts those variables into the appropriate
3108 * register values, and can bring down the device if needed.
3110 static void adjust_link(struct net_device *dev)
3112 struct gfar_private *priv = netdev_priv(dev);
3113 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3114 struct phy_device *phydev = priv->phydev;
3117 if (test_bit(GFAR_RESETTING, &priv->state))
3121 u32 tempval1 = gfar_read(®s->maccfg1);
3122 u32 tempval = gfar_read(®s->maccfg2);
3123 u32 ecntrl = gfar_read(®s->ecntrl);
3125 /* Now we make sure that we can be in full duplex mode.
3126 * If not, we operate in half-duplex mode.
3128 if (phydev->duplex != priv->oldduplex) {
3130 if (!(phydev->duplex))
3131 tempval &= ~(MACCFG2_FULL_DUPLEX);
3133 tempval |= MACCFG2_FULL_DUPLEX;
3135 priv->oldduplex = phydev->duplex;
3138 if (phydev->speed != priv->oldspeed) {
3140 switch (phydev->speed) {
3143 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3145 ecntrl &= ~(ECNTRL_R100);
3150 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3152 /* Reduced mode distinguishes
3153 * between 10 and 100
3155 if (phydev->speed == SPEED_100)
3156 ecntrl |= ECNTRL_R100;
3158 ecntrl &= ~(ECNTRL_R100);
3161 netif_warn(priv, link, dev,
3162 "Ack! Speed (%d) is not 10/100/1000!\n",
3167 priv->oldspeed = phydev->speed;
3170 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3171 tempval1 |= gfar_get_flowctrl_cfg(priv);
3173 gfar_write(®s->maccfg1, tempval1);
3174 gfar_write(®s->maccfg2, tempval);
3175 gfar_write(®s->ecntrl, ecntrl);
3177 if (!priv->oldlink) {
3181 } else if (priv->oldlink) {
3185 priv->oldduplex = -1;
3188 if (new_state && netif_msg_link(priv))
3189 phy_print_status(phydev);
3192 /* Update the hash table based on the current list of multicast
3193 * addresses we subscribe to. Also, change the promiscuity of
3194 * the device based on the flags (this function is called
3195 * whenever dev->flags is changed
3197 static void gfar_set_multi(struct net_device *dev)
3199 struct netdev_hw_addr *ha;
3200 struct gfar_private *priv = netdev_priv(dev);
3201 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3204 if (dev->flags & IFF_PROMISC) {
3205 /* Set RCTRL to PROM */
3206 tempval = gfar_read(®s->rctrl);
3207 tempval |= RCTRL_PROM;
3208 gfar_write(®s->rctrl, tempval);
3210 /* Set RCTRL to not PROM */
3211 tempval = gfar_read(®s->rctrl);
3212 tempval &= ~(RCTRL_PROM);
3213 gfar_write(®s->rctrl, tempval);
3216 if (dev->flags & IFF_ALLMULTI) {
3217 /* Set the hash to rx all multicast frames */
3218 gfar_write(®s->igaddr0, 0xffffffff);
3219 gfar_write(®s->igaddr1, 0xffffffff);
3220 gfar_write(®s->igaddr2, 0xffffffff);
3221 gfar_write(®s->igaddr3, 0xffffffff);
3222 gfar_write(®s->igaddr4, 0xffffffff);
3223 gfar_write(®s->igaddr5, 0xffffffff);
3224 gfar_write(®s->igaddr6, 0xffffffff);
3225 gfar_write(®s->igaddr7, 0xffffffff);
3226 gfar_write(®s->gaddr0, 0xffffffff);
3227 gfar_write(®s->gaddr1, 0xffffffff);
3228 gfar_write(®s->gaddr2, 0xffffffff);
3229 gfar_write(®s->gaddr3, 0xffffffff);
3230 gfar_write(®s->gaddr4, 0xffffffff);
3231 gfar_write(®s->gaddr5, 0xffffffff);
3232 gfar_write(®s->gaddr6, 0xffffffff);
3233 gfar_write(®s->gaddr7, 0xffffffff);
3238 /* zero out the hash */
3239 gfar_write(®s->igaddr0, 0x0);
3240 gfar_write(®s->igaddr1, 0x0);
3241 gfar_write(®s->igaddr2, 0x0);
3242 gfar_write(®s->igaddr3, 0x0);
3243 gfar_write(®s->igaddr4, 0x0);
3244 gfar_write(®s->igaddr5, 0x0);
3245 gfar_write(®s->igaddr6, 0x0);
3246 gfar_write(®s->igaddr7, 0x0);
3247 gfar_write(®s->gaddr0, 0x0);
3248 gfar_write(®s->gaddr1, 0x0);
3249 gfar_write(®s->gaddr2, 0x0);
3250 gfar_write(®s->gaddr3, 0x0);
3251 gfar_write(®s->gaddr4, 0x0);
3252 gfar_write(®s->gaddr5, 0x0);
3253 gfar_write(®s->gaddr6, 0x0);
3254 gfar_write(®s->gaddr7, 0x0);
3256 /* If we have extended hash tables, we need to
3257 * clear the exact match registers to prepare for
3260 if (priv->extended_hash) {
3261 em_num = GFAR_EM_NUM + 1;
3262 gfar_clear_exact_match(dev);
3269 if (netdev_mc_empty(dev))
3272 /* Parse the list, and set the appropriate bits */
3273 netdev_for_each_mc_addr(ha, dev) {
3275 gfar_set_mac_for_addr(dev, idx, ha->addr);
3278 gfar_set_hash_for_addr(dev, ha->addr);
3284 /* Clears each of the exact match registers to zero, so they
3285 * don't interfere with normal reception
3287 static void gfar_clear_exact_match(struct net_device *dev)
3290 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3292 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3293 gfar_set_mac_for_addr(dev, idx, zero_arr);
3296 /* Set the appropriate hash bit for the given addr */
3297 /* The algorithm works like so:
3298 * 1) Take the Destination Address (ie the multicast address), and
3299 * do a CRC on it (little endian), and reverse the bits of the
3301 * 2) Use the 8 most significant bits as a hash into a 256-entry
3302 * table. The table is controlled through 8 32-bit registers:
3303 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3304 * gaddr7. This means that the 3 most significant bits in the
3305 * hash index which gaddr register to use, and the 5 other bits
3306 * indicate which bit (assuming an IBM numbering scheme, which
3307 * for PowerPC (tm) is usually the case) in the register holds
3310 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3313 struct gfar_private *priv = netdev_priv(dev);
3314 u32 result = ether_crc(ETH_ALEN, addr);
3315 int width = priv->hash_width;
3316 u8 whichbit = (result >> (32 - width)) & 0x1f;
3317 u8 whichreg = result >> (32 - width + 5);
3318 u32 value = (1 << (31-whichbit));
3320 tempval = gfar_read(priv->hash_regs[whichreg]);
3322 gfar_write(priv->hash_regs[whichreg], tempval);
3326 /* There are multiple MAC Address register pairs on some controllers
3327 * This function sets the numth pair to a given address
3329 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3332 struct gfar_private *priv = netdev_priv(dev);
3333 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3335 char tmpbuf[ETH_ALEN];
3337 u32 __iomem *macptr = ®s->macstnaddr1;
3341 /* Now copy it into the mac registers backwards, cuz
3342 * little endian is silly
3344 for (idx = 0; idx < ETH_ALEN; idx++)
3345 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3347 gfar_write(macptr, *((u32 *) (tmpbuf)));
3349 tempval = *((u32 *) (tmpbuf + 4));
3351 gfar_write(macptr+1, tempval);
3354 /* GFAR error interrupt handler */
3355 static irqreturn_t gfar_error(int irq, void *grp_id)
3357 struct gfar_priv_grp *gfargrp = grp_id;
3358 struct gfar __iomem *regs = gfargrp->regs;
3359 struct gfar_private *priv= gfargrp->priv;
3360 struct net_device *dev = priv->ndev;
3362 /* Save ievent for future reference */
3363 u32 events = gfar_read(®s->ievent);
3366 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3368 /* Magic Packet is not an error. */
3369 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3370 (events & IEVENT_MAG))
3371 events &= ~IEVENT_MAG;
3374 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3376 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3377 events, gfar_read(®s->imask));
3379 /* Update the error counters */
3380 if (events & IEVENT_TXE) {
3381 dev->stats.tx_errors++;
3383 if (events & IEVENT_LC)
3384 dev->stats.tx_window_errors++;
3385 if (events & IEVENT_CRL)
3386 dev->stats.tx_aborted_errors++;
3387 if (events & IEVENT_XFUN) {
3388 unsigned long flags;
3390 netif_dbg(priv, tx_err, dev,
3391 "TX FIFO underrun, packet dropped\n");
3392 dev->stats.tx_dropped++;
3393 atomic64_inc(&priv->extra_stats.tx_underrun);
3395 local_irq_save(flags);
3398 /* Reactivate the Tx Queues */
3399 gfar_write(®s->tstat, gfargrp->tstat);
3402 local_irq_restore(flags);
3404 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3406 if (events & IEVENT_BSY) {
3407 dev->stats.rx_errors++;
3408 atomic64_inc(&priv->extra_stats.rx_bsy);
3410 gfar_receive(irq, grp_id);
3412 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3413 gfar_read(®s->rstat));
3415 if (events & IEVENT_BABR) {
3416 dev->stats.rx_errors++;
3417 atomic64_inc(&priv->extra_stats.rx_babr);
3419 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3421 if (events & IEVENT_EBERR) {
3422 atomic64_inc(&priv->extra_stats.eberr);
3423 netif_dbg(priv, rx_err, dev, "bus error\n");
3425 if (events & IEVENT_RXC)
3426 netif_dbg(priv, rx_status, dev, "control frame\n");
3428 if (events & IEVENT_BABT) {
3429 atomic64_inc(&priv->extra_stats.tx_babt);
3430 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3435 static struct of_device_id gfar_match[] =
3439 .compatible = "gianfar",
3442 .compatible = "fsl,etsec2",
3446 MODULE_DEVICE_TABLE(of, gfar_match);
3448 /* Structure for a device driver */
3449 static struct platform_driver gfar_driver = {
3451 .name = "fsl-gianfar",
3452 .owner = THIS_MODULE,
3454 .of_match_table = gfar_match,
3456 .probe = gfar_probe,
3457 .remove = gfar_remove,
3460 module_platform_driver(gfar_driver);