drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32
  33 #include "ixgbe.h"
  34 #include "ixgbe_phy.h"
  35 #include "ixgbe_x540.h"
  36
  37 #define IXGBE_X540_MAX_TX_QUEUES        128
  38 #define IXGBE_X540_MAX_RX_QUEUES        128
  39 #define IXGBE_X540_RAR_ENTRIES          128
  40 #define IXGBE_X540_MC_TBL_SIZE          128
  41 #define IXGBE_X540_VFT_TBL_SIZE         128
  42 #define IXGBE_X540_RX_PB_SIZE           384
  43
  44 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  45 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  48
  49 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
  50 {
  51         return ixgbe_media_type_copper;
  52 }
  53
  54 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
  55 {
  56         struct ixgbe_mac_info *mac = &hw->mac;
  57         struct ixgbe_phy_info *phy = &hw->phy;
  58
  59         /* set_phy_power was set by default to NULL */
  60         if (!ixgbe_mng_present(hw))
  61                 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
  62
  63         mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
  64         mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
  65         mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
  66         mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
  67         mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
  68         mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
  69         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
  70
  71         return 0;
  72 }
  73
  74 /**
  75  *  ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
  76  *  @hw: pointer to hardware structure
  77  *  @speed: new link speed
  78  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  79  **/
  80 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
  81                               bool autoneg_wait_to_complete)
  82 {
  83         return hw->phy.ops.setup_link_speed(hw, speed,
  84                                             autoneg_wait_to_complete);
  85 }
  86
  87 /**
  88  *  ixgbe_reset_hw_X540 - Perform hardware reset
  89  *  @hw: pointer to hardware structure
  90  *
  91  *  Resets the hardware by resetting the transmit and receive units, masks
  92  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
  93  *  reset.
  94  **/
  95 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
  96 {
  97         s32 status;
  98         u32 ctrl, i;
  99
 100         /* Call adapter stop to disable tx/rx and clear interrupts */
 101         status = hw->mac.ops.stop_adapter(hw);
 102         if (status)
 103                 return status;
 104
 105         /* flush pending Tx transactions */
 106         ixgbe_clear_tx_pending(hw);
 107
 108 mac_reset_top:
 109         ctrl = IXGBE_CTRL_RST;
 110         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 111         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 112         IXGBE_WRITE_FLUSH(hw);
 113
 114         /* Poll for reset bit to self-clear indicating reset is complete */
 115         for (i = 0; i < 10; i++) {
 116                 udelay(1);
 117                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 118                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 119                         break;
 120         }
 121
 122         if (ctrl & IXGBE_CTRL_RST_MASK) {
 123                 status = IXGBE_ERR_RESET_FAILED;
 124                 hw_dbg(hw, "Reset polling failed to complete.\n");
 125         }
 126         msleep(100);
 127
 128         /*
 129          * Double resets are required for recovery from certain error
 130          * conditions.  Between resets, it is necessary to stall to allow time
 131          * for any pending HW events to complete.
 132          */
 133         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 134                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 135                 goto mac_reset_top;
 136         }
 137
 138         /* Set the Rx packet buffer size. */
 139         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 140
 141         /* Store the permanent mac address */
 142         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 143
 144         /*
 145          * Store MAC address from RAR0, clear receive address registers, and
 146          * clear the multicast table.  Also reset num_rar_entries to 128,
 147          * since we modify this value when programming the SAN MAC address.
 148          */
 149         hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
 150         hw->mac.ops.init_rx_addrs(hw);
 151
 152         /* Store the permanent SAN mac address */
 153         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 154
 155         /* Add the SAN MAC address to the RAR only if it's a valid address */
 156         if (is_valid_ether_addr(hw->mac.san_addr)) {
 157                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 158                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 159
 160                 /* Save the SAN MAC RAR index */
 161                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 162
 163                 /* Reserve the last RAR for the SAN MAC address */
 164                 hw->mac.num_rar_entries--;
 165         }
 166
 167         /* Store the alternative WWNN/WWPN prefix */
 168         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 169                                    &hw->mac.wwpn_prefix);
 170
 171         return status;
 172 }
 173
 174 /**
 175  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 176  *  @hw: pointer to hardware structure
 177  *
 178  *  Starts the hardware using the generic start_hw function
 179  *  and the generation start_hw function.
 180  *  Then performs revision-specific operations, if any.
 181  **/
 182 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 183 {
 184         s32 ret_val;
 185
 186         ret_val = ixgbe_start_hw_generic(hw);
 187         if (ret_val)
 188                 return ret_val;
 189
 190         return ixgbe_start_hw_gen2(hw);
 191 }
 192
 193 /**
 194  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 195  *  @hw: pointer to hardware structure
 196  *
 197  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 198  *  ixgbe_hw struct in order to set up EEPROM access.
 199  **/
 200 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 201 {
 202         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 203         u32 eec;
 204         u16 eeprom_size;
 205
 206         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 207                 eeprom->semaphore_delay = 10;
 208                 eeprom->type = ixgbe_flash;
 209
 210                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 211                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 212                                     IXGBE_EEC_SIZE_SHIFT);
 213                 eeprom->word_size = 1 << (eeprom_size +
 214                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 215
 216                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 217                        eeprom->type, eeprom->word_size);
 218         }
 219
 220         return 0;
 221 }
 222
 223 /**
 224  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 225  *  @hw: pointer to hardware structure
 226  *  @offset: offset of  word in the EEPROM to read
 227  *  @data: word read from the EEPROM
 228  *
 229  *  Reads a 16 bit word from the EEPROM using the EERD register.
 230  **/
 231 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 232 {
 233         s32 status;
 234
 235         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 236                 return IXGBE_ERR_SWFW_SYNC;
 237
 238         status = ixgbe_read_eerd_generic(hw, offset, data);
 239
 240         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 241         return status;
 242 }
 243
 244 /**
 245  *  ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
 246  *  @hw: pointer to hardware structure
 247  *  @offset: offset of  word in the EEPROM to read
 248  *  @words: number of words
 249  *  @data: word(s) read from the EEPROM
 250  *
 251  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 252  **/
 253 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 254                                        u16 offset, u16 words, u16 *data)
 255 {
 256         s32 status;
 257
 258         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 259                 return IXGBE_ERR_SWFW_SYNC;
 260
 261         status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
 262
 263         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 264         return status;
 265 }
 266
 267 /**
 268  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 269  *  @hw: pointer to hardware structure
 270  *  @offset: offset of  word in the EEPROM to write
 271  *  @data: word write to the EEPROM
 272  *
 273  *  Write a 16 bit word to the EEPROM using the EEWR register.
 274  **/
 275 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 276 {
 277         s32 status;
 278
 279         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 280                 return IXGBE_ERR_SWFW_SYNC;
 281
 282         status = ixgbe_write_eewr_generic(hw, offset, data);
 283
 284         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 285         return status;
 286 }
 287
 288 /**
 289  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 290  *  @hw: pointer to hardware structure
 291  *  @offset: offset of  word in the EEPROM to write
 292  *  @words: number of words
 293  *  @data: word(s) write to the EEPROM
 294  *
 295  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 296  **/
 297 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 298                                         u16 offset, u16 words, u16 *data)
 299 {
 300         s32 status;
 301
 302         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 303                 return IXGBE_ERR_SWFW_SYNC;
 304
 305         status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
 306
 307         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 308         return status;
 309 }
 310
 311 /**
 312  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 313  *
 314  *  This function does not use synchronization for EERD and EEWR. It can
 315  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 316  *
 317  *  @hw: pointer to hardware structure
 318  **/
 319 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 320 {
 321         u16 i;
 322         u16 j;
 323         u16 checksum = 0;
 324         u16 length = 0;
 325         u16 pointer = 0;
 326         u16 word = 0;
 327         u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
 328         u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
 329
 330         /*
 331          * Do not use hw->eeprom.ops.read because we do not want to take
 332          * the synchronization semaphores here. Instead use
 333          * ixgbe_read_eerd_generic
 334          */
 335
 336         /* Include 0x0-0x3F in the checksum */
 337         for (i = 0; i < checksum_last_word; i++) {
 338                 if (ixgbe_read_eerd_generic(hw, i, &word)) {
 339                         hw_dbg(hw, "EEPROM read failed\n");
 340                         return IXGBE_ERR_EEPROM;
 341                 }
 342                 checksum += word;
 343         }
 344
 345         /*
 346          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 347          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 348          */
 349         for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
 350                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 351                         continue;
 352
 353                 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
 354                         hw_dbg(hw, "EEPROM read failed\n");
 355                         break;
 356                 }
 357
 358                 /* Skip pointer section if the pointer is invalid. */
 359                 if (pointer == 0xFFFF || pointer == 0 ||
 360                     pointer >= hw->eeprom.word_size)
 361                         continue;
 362
 363                 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
 364                         hw_dbg(hw, "EEPROM read failed\n");
 365                         return IXGBE_ERR_EEPROM;
 366                         break;
 367                 }
 368
 369                 /* Skip pointer section if length is invalid. */
 370                 if (length == 0xFFFF || length == 0 ||
 371                     (pointer + length) >= hw->eeprom.word_size)
 372                         continue;
 373
 374                 for (j = pointer + 1; j <= pointer + length; j++) {
 375                         if (ixgbe_read_eerd_generic(hw, j, &word)) {
 376                                 hw_dbg(hw, "EEPROM read failed\n");
 377                                 return IXGBE_ERR_EEPROM;
 378                         }
 379                         checksum += word;
 380                 }
 381         }
 382
 383         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 384
 385         return (s32)checksum;
 386 }
 387
 388 /**
 389  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 390  *  @hw: pointer to hardware structure
 391  *  @checksum_val: calculated checksum
 392  *
 393  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 394  *  caller does not need checksum_val, the value can be NULL.
 395  **/
 396 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 397                                                u16 *checksum_val)
 398 {
 399         s32 status;
 400         u16 checksum;
 401         u16 read_checksum = 0;
 402
 403         /* Read the first word from the EEPROM. If this times out or fails, do
 404          * not continue or we could be in for a very long wait while every
 405          * EEPROM read fails
 406          */
 407         status = hw->eeprom.ops.read(hw, 0, &checksum);
 408         if (status) {
 409                 hw_dbg(hw, "EEPROM read failed\n");
 410                 return status;
 411         }
 412
 413         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 414                 return IXGBE_ERR_SWFW_SYNC;
 415
 416         status = hw->eeprom.ops.calc_checksum(hw);
 417         if (status < 0)
 418                 goto out;
 419
 420         checksum = (u16)(status & 0xffff);
 421
 422         /* Do not use hw->eeprom.ops.read because we do not want to take
 423          * the synchronization semaphores twice here.
 424          */
 425         status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 426                                          &read_checksum);
 427         if (status)
 428                 goto out;
 429
 430         /* Verify read checksum from EEPROM is the same as
 431          * calculated checksum
 432          */
 433         if (read_checksum != checksum) {
 434                 hw_dbg(hw, "Invalid EEPROM checksum");
 435                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 436         }
 437
 438         /* If the user cares, return the calculated checksum */
 439         if (checksum_val)
 440                 *checksum_val = checksum;
 441
 442 out:
 443         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 444
 445         return status;
 446 }
 447
 448 /**
 449  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 450  * @hw: pointer to hardware structure
 451  *
 452  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 453  * checksum and updates the EEPROM and instructs the hardware to update
 454  * the flash.
 455  **/
 456 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 457 {
 458         s32 status;
 459         u16 checksum;
 460
 461         /* Read the first word from the EEPROM. If this times out or fails, do
 462          * not continue or we could be in for a very long wait while every
 463          * EEPROM read fails
 464          */
 465         status = hw->eeprom.ops.read(hw, 0, &checksum);
 466         if (status) {
 467                 hw_dbg(hw, "EEPROM read failed\n");
 468                 return status;
 469         }
 470
 471         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
 472                 return  IXGBE_ERR_SWFW_SYNC;
 473
 474         status = hw->eeprom.ops.calc_checksum(hw);
 475         if (status < 0)
 476                 goto out;
 477
 478         checksum = (u16)(status & 0xffff);
 479
 480         /* Do not use hw->eeprom.ops.write because we do not want to
 481          * take the synchronization semaphores twice here.
 482          */
 483         status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
 484         if (status)
 485                 goto out;
 486
 487         status = ixgbe_update_flash_X540(hw);
 488
 489 out:
 490         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 491         return status;
 492 }
 493
 494 /**
 495  * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 496  * @hw: pointer to hardware structure
 497  *
 498  * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 499  * EEPROM from shadow RAM to the flash device.
 500  **/
 501 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 502 {
 503         u32 flup;
 504         s32 status;
 505
 506         status = ixgbe_poll_flash_update_done_X540(hw);
 507         if (status == IXGBE_ERR_EEPROM) {
 508                 hw_dbg(hw, "Flash update time out\n");
 509                 return status;
 510         }
 511
 512         flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
 513         IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
 514
 515         status = ixgbe_poll_flash_update_done_X540(hw);
 516         if (status == 0)
 517                 hw_dbg(hw, "Flash update complete\n");
 518         else
 519                 hw_dbg(hw, "Flash update time out\n");
 520
 521         if (hw->revision_id == 0) {
 522                 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 523
 524                 if (flup & IXGBE_EEC_SEC1VAL) {
 525                         flup |= IXGBE_EEC_FLUP;
 526                         IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
 527                 }
 528
 529                 status = ixgbe_poll_flash_update_done_X540(hw);
 530                 if (status == 0)
 531                         hw_dbg(hw, "Flash update complete\n");
 532                 else
 533                         hw_dbg(hw, "Flash update time out\n");
 534         }
 535
 536         return status;
 537 }
 538
 539 /**
 540  * ixgbe_poll_flash_update_done_X540 - Poll flash update status
 541  * @hw: pointer to hardware structure
 542  *
 543  * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 544  * flash update is done.
 545  **/
 546 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 547 {
 548         u32 i;
 549         u32 reg;
 550
 551         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 552                 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 553                 if (reg & IXGBE_EEC_FLUDONE)
 554                         return 0;
 555                 udelay(5);
 556         }
 557         return IXGBE_ERR_EEPROM;
 558 }
 559
 560 /**
 561  * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 562  * @hw: pointer to hardware structure
 563  * @mask: Mask to specify which semaphore to acquire
 564  *
 565  * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 566  * the specified function (CSR, PHY0, PHY1, NVM, Flash)
 567  **/
 568 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
 569 {
 570         u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
 571         u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
 572         u32 fwmask = swmask << 5;
 573         u32 timeout = 200;
 574         u32 hwmask = 0;
 575         u32 swfw_sync;
 576         u32 i;
 577
 578         if (swmask & IXGBE_GSSR_EEP_SM)
 579                 hwmask = IXGBE_GSSR_FLASH_SM;
 580
 581         /* SW only mask does not have FW bit pair */
 582         if (mask & IXGBE_GSSR_SW_MNG_SM)
 583                 swmask |= IXGBE_GSSR_SW_MNG_SM;
 584
 585         swmask |= swi2c_mask;
 586         fwmask |= swi2c_mask << 2;
 587         for (i = 0; i < timeout; i++) {
 588                 /* SW NVM semaphore bit is used for access to all
 589                  * SW_FW_SYNC bits (not just NVM)
 590                  */
 591                 if (ixgbe_get_swfw_sync_semaphore(hw))
 592                         return IXGBE_ERR_SWFW_SYNC;
 593
 594                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 595                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 596                         swfw_sync |= swmask;
 597                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
 598                         ixgbe_release_swfw_sync_semaphore(hw);
 599                         usleep_range(5000, 6000);
 600                         return 0;
 601                 }
 602                 /* Firmware currently using resource (fwmask), hardware
 603                  * currently using resource (hwmask), or other software
 604                  * thread currently using resource (swmask)
 605                  */
 606                 ixgbe_release_swfw_sync_semaphore(hw);
 607                 usleep_range(5000, 10000);
 608         }
 609
 610         /* Failed to get SW only semaphore */
 611         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 612                 hw_dbg(hw, "Failed to get SW only semaphore\n");
 613                 return IXGBE_ERR_SWFW_SYNC;
 614         }
 615
 616         /* If the resource is not released by the FW/HW the SW can assume that
 617          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 618          * of the requested resource(s) while ignoring the corresponding FW/HW
 619          * bits in the SW_FW_SYNC register.
 620          */
 621         if (ixgbe_get_swfw_sync_semaphore(hw))
 622                 return IXGBE_ERR_SWFW_SYNC;
 623         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 624         if (swfw_sync & (fwmask | hwmask)) {
 625                 swfw_sync |= swmask;
 626                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
 627                 ixgbe_release_swfw_sync_semaphore(hw);
 628                 usleep_range(5000, 6000);
 629                 return 0;
 630         }
 631         /* If the resource is not released by other SW the SW can assume that
 632          * the other SW malfunctions. In that case the SW should clear all SW
 633          * flags that it does not own and then repeat the whole process once
 634          * again.
 635          */
 636         if (swfw_sync & swmask) {
 637                 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
 638                             IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
 639
 640                 if (swi2c_mask)
 641                         rmask |= IXGBE_GSSR_I2C_MASK;
 642                 ixgbe_release_swfw_sync_X540(hw, rmask);
 643                 ixgbe_release_swfw_sync_semaphore(hw);
 644                 return IXGBE_ERR_SWFW_SYNC;
 645         }
 646         ixgbe_release_swfw_sync_semaphore(hw);
 647
 648         return IXGBE_ERR_SWFW_SYNC;
 649 }
 650
 651 /**
 652  * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 653  * @hw: pointer to hardware structure
 654  * @mask: Mask to specify which semaphore to release
 655  *
 656  * Releases the SWFW semaphore through the SW_FW_SYNC register
 657  * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 658  **/
 659 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
 660 {
 661         u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
 662         u32 swfw_sync;
 663
 664         if (mask & IXGBE_GSSR_I2C_MASK)
 665                 swmask |= mask & IXGBE_GSSR_I2C_MASK;
 666         ixgbe_get_swfw_sync_semaphore(hw);
 667
 668         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 669         swfw_sync &= ~swmask;
 670         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
 671
 672         ixgbe_release_swfw_sync_semaphore(hw);
 673         usleep_range(5000, 6000);
 674 }
 675
 676 /**
 677  * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
 678  * @hw: pointer to hardware structure
 679  *
 680  * Sets the hardware semaphores so SW/FW can gain control of shared resources
 681  */
 682 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 683 {
 684         u32 timeout = 2000;
 685         u32 i;
 686         u32 swsm;
 687
 688         /* Get SMBI software semaphore between device drivers first */
 689         for (i = 0; i < timeout; i++) {
 690                 /* If the SMBI bit is 0 when we read it, then the bit will be
 691                  * set and we have the semaphore
 692                  */
 693                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
 694                 if (!(swsm & IXGBE_SWSM_SMBI))
 695                         break;
 696                 usleep_range(50, 100);
 697         }
 698
 699         if (i == timeout) {
 700                 hw_dbg(hw,
 701                        "Software semaphore SMBI between device drivers not granted.\n");
 702                 return IXGBE_ERR_EEPROM;
 703         }
 704
 705         /* Now get the semaphore between SW/FW through the REGSMP bit */
 706         for (i = 0; i < timeout; i++) {
 707                 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 708                 if (!(swsm & IXGBE_SWFW_REGSMP))
 709                         return 0;
 710
 711                 usleep_range(50, 100);
 712         }
 713
 714         /* Release semaphores and return error if SW NVM semaphore
 715          * was not granted because we do not have access to the EEPROM
 716          */
 717         hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
 718         ixgbe_release_swfw_sync_semaphore(hw);
 719         return IXGBE_ERR_EEPROM;
 720 }
 721
 722 /**
 723  * ixgbe_release_nvm_semaphore - Release hardware semaphore
 724  * @hw: pointer to hardware structure
 725  *
 726  * This function clears hardware semaphore bits.
 727  **/
 728 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 729 {
 730          u32 swsm;
 731
 732         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 733
 734         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
 735         swsm &= ~IXGBE_SWFW_REGSMP;
 736         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
 737
 738         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
 739         swsm &= ~IXGBE_SWSM_SMBI;
 740         IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
 741
 742         IXGBE_WRITE_FLUSH(hw);
 743 }
 744
 745 /**
 746  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 747  * @hw: pointer to hardware structure
 748  * @index: led number to blink
 749  *
 750  * Devices that implement the version 2 interface:
 751  *   X540
 752  **/
 753 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 754 {
 755         u32 macc_reg;
 756         u32 ledctl_reg;
 757         ixgbe_link_speed speed;
 758         bool link_up;
 759
 760         /*
 761          * Link should be up in order for the blink bit in the LED control
 762          * register to work. Force link and speed in the MAC if link is down.
 763          * This will be reversed when we stop the blinking.
 764          */
 765         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 766         if (!link_up) {
 767                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 768                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 769                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 770         }
 771         /* Set the LED to LINK_UP + BLINK. */
 772         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 773         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 774         ledctl_reg |= IXGBE_LED_BLINK(index);
 775         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 776         IXGBE_WRITE_FLUSH(hw);
 777
 778         return 0;
 779 }
 780
 781 /**
 782  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 783  * @hw: pointer to hardware structure
 784  * @index: led number to stop blinking
 785  *
 786  * Devices that implement the version 2 interface:
 787  *   X540
 788  **/
 789 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 790 {
 791         u32 macc_reg;
 792         u32 ledctl_reg;
 793
 794         /* Restore the LED to its default value. */
 795         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 796         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 797         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 798         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 799         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 800
 801         /* Unforce link and speed in the MAC. */
 802         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 803         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 804         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 805         IXGBE_WRITE_FLUSH(hw);
 806
 807         return 0;
 808 }
 809 static struct ixgbe_mac_operations mac_ops_X540 = {
 810         .init_hw                = &ixgbe_init_hw_generic,
 811         .reset_hw               = &ixgbe_reset_hw_X540,
 812         .start_hw               = &ixgbe_start_hw_X540,
 813         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
 814         .get_media_type         = &ixgbe_get_media_type_X540,
 815         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
 816         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
 817         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
 818         .get_device_caps        = &ixgbe_get_device_caps_generic,
 819         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
 820         .stop_adapter           = &ixgbe_stop_adapter_generic,
 821         .get_bus_info           = &ixgbe_get_bus_info_generic,
 822         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
 823         .read_analog_reg8       = NULL,
 824         .write_analog_reg8      = NULL,
 825         .setup_link             = &ixgbe_setup_mac_link_X540,
 826         .set_rxpba              = &ixgbe_set_rxpba_generic,
 827         .check_link             = &ixgbe_check_mac_link_generic,
 828         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
 829         .led_on                 = &ixgbe_led_on_generic,
 830         .led_off                = &ixgbe_led_off_generic,
 831         .blink_led_start        = &ixgbe_blink_led_start_X540,
 832         .blink_led_stop         = &ixgbe_blink_led_stop_X540,
 833         .set_rar                = &ixgbe_set_rar_generic,
 834         .clear_rar              = &ixgbe_clear_rar_generic,
 835         .set_vmdq               = &ixgbe_set_vmdq_generic,
 836         .set_vmdq_san_mac       = &ixgbe_set_vmdq_san_mac_generic,
 837         .clear_vmdq             = &ixgbe_clear_vmdq_generic,
 838         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
 839         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
 840         .enable_mc              = &ixgbe_enable_mc_generic,
 841         .disable_mc             = &ixgbe_disable_mc_generic,
 842         .clear_vfta             = &ixgbe_clear_vfta_generic,
 843         .set_vfta               = &ixgbe_set_vfta_generic,
 844         .fc_enable              = &ixgbe_fc_enable_generic,
 845         .set_fw_drv_ver         = &ixgbe_set_fw_drv_ver_generic,
 846         .init_uta_tables        = &ixgbe_init_uta_tables_generic,
 847         .setup_sfp              = NULL,
 848         .set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
 849         .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
 850         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
 851         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
 852         .disable_rx_buff        = &ixgbe_disable_rx_buff_generic,
 853         .enable_rx_buff         = &ixgbe_enable_rx_buff_generic,
 854         .get_thermal_sensor_data = NULL,
 855         .init_thermal_sensor_thresh = NULL,
 856         .prot_autoc_read        = &prot_autoc_read_generic,
 857         .prot_autoc_write       = &prot_autoc_write_generic,
 858         .enable_rx              = &ixgbe_enable_rx_generic,
 859         .disable_rx             = &ixgbe_disable_rx_generic,
 860 };
 861
 862 static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
 863         .init_params            = &ixgbe_init_eeprom_params_X540,
 864         .read                   = &ixgbe_read_eerd_X540,
 865         .read_buffer            = &ixgbe_read_eerd_buffer_X540,
 866         .write                  = &ixgbe_write_eewr_X540,
 867         .write_buffer           = &ixgbe_write_eewr_buffer_X540,
 868         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X540,
 869         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X540,
 870         .update_checksum        = &ixgbe_update_eeprom_checksum_X540,
 871 };
 872
 873 static struct ixgbe_phy_operations phy_ops_X540 = {
 874         .identify               = &ixgbe_identify_phy_generic,
 875         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
 876         .init                   = NULL,
 877         .reset                  = NULL,
 878         .read_reg               = &ixgbe_read_phy_reg_generic,
 879         .write_reg              = &ixgbe_write_phy_reg_generic,
 880         .setup_link             = &ixgbe_setup_phy_link_generic,
 881         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
 882         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
 883         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
 884         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic,
 885         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
 886         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
 887         .check_overtemp         = &ixgbe_tn_check_overtemp,
 888         .set_phy_power          = &ixgbe_set_copper_phy_power,
 889         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
 890 };
 891
 892 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
 893         IXGBE_MVALS_INIT(X540)
 894 };
 895
 896 struct ixgbe_info ixgbe_X540_info = {
 897         .mac                    = ixgbe_mac_X540,
 898         .get_invariants         = &ixgbe_get_invariants_X540,
 899         .mac_ops                = &mac_ops_X540,
 900         .eeprom_ops             = &eeprom_ops_X540,
 901         .phy_ops                = &phy_ops_X540,
 902         .mbx_ops                = &mbx_ops_generic,
 903         .mvals                  = ixgbe_mvals_X540,
 904 };