drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50
  51 #ifdef RTL8169_DEBUG
  52 #define assert(expr) \
  53         if (!(expr)) {                                  \
  54                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  55                 #expr,__FILE__,__func__,__LINE__);              \
  56         }
  57 #define dprintk(fmt, args...) \
  58         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  59 #else
  60 #define assert(expr) do {} while (0)
  61 #define dprintk(fmt, args...)   do {} while (0)
  62 #endif /* RTL8169_DEBUG */
  63
  64 #define R8169_MSG_DEFAULT \
  65         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  66
  67 #define TX_SLOTS_AVAIL(tp) \
  68         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  69
  70 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  71 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  72         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  73
  74 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  75    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  76 static const int multicast_filter_limit = 32;
  77
  78 #define MAX_READ_REQUEST_SHIFT  12
  79 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  80 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  81 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  82
  83 #define R8169_REGS_SIZE         256
  84 #define R8169_NAPI_WEIGHT       64
  85 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  86 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  87 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  88 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  89 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  90
  91 #define RTL8169_TX_TIMEOUT      (6*HZ)
  92 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  93
  94 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  95 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  96 #define RTL_EEPROM_SIG_ADDR     0x0000
  97
  98 /* write/read MMIO register */
  99 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 100 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 101 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 102 #define RTL_R8(reg)             readb (ioaddr + (reg))
 103 #define RTL_R16(reg)            readw (ioaddr + (reg))
 104 #define RTL_R32(reg)            readl (ioaddr + (reg))
 105
 106 enum mac_version {
 107         RTL_GIGA_MAC_VER_01 = 0,
 108         RTL_GIGA_MAC_VER_02,
 109         RTL_GIGA_MAC_VER_03,
 110         RTL_GIGA_MAC_VER_04,
 111         RTL_GIGA_MAC_VER_05,
 112         RTL_GIGA_MAC_VER_06,
 113         RTL_GIGA_MAC_VER_07,
 114         RTL_GIGA_MAC_VER_08,
 115         RTL_GIGA_MAC_VER_09,
 116         RTL_GIGA_MAC_VER_10,
 117         RTL_GIGA_MAC_VER_11,
 118         RTL_GIGA_MAC_VER_12,
 119         RTL_GIGA_MAC_VER_13,
 120         RTL_GIGA_MAC_VER_14,
 121         RTL_GIGA_MAC_VER_15,
 122         RTL_GIGA_MAC_VER_16,
 123         RTL_GIGA_MAC_VER_17,
 124         RTL_GIGA_MAC_VER_18,
 125         RTL_GIGA_MAC_VER_19,
 126         RTL_GIGA_MAC_VER_20,
 127         RTL_GIGA_MAC_VER_21,
 128         RTL_GIGA_MAC_VER_22,
 129         RTL_GIGA_MAC_VER_23,
 130         RTL_GIGA_MAC_VER_24,
 131         RTL_GIGA_MAC_VER_25,
 132         RTL_GIGA_MAC_VER_26,
 133         RTL_GIGA_MAC_VER_27,
 134         RTL_GIGA_MAC_VER_28,
 135         RTL_GIGA_MAC_VER_29,
 136         RTL_GIGA_MAC_VER_30,
 137         RTL_GIGA_MAC_VER_31,
 138         RTL_GIGA_MAC_VER_32,
 139         RTL_GIGA_MAC_VER_33,
 140         RTL_GIGA_MAC_VER_34,
 141         RTL_GIGA_MAC_VER_35,
 142         RTL_GIGA_MAC_VER_36,
 143         RTL_GIGA_MAC_VER_37,
 144         RTL_GIGA_MAC_VER_38,
 145         RTL_GIGA_MAC_VER_39,
 146         RTL_GIGA_MAC_NONE   = 0xff,
 147 };
 148
 149 enum rtl_tx_desc_version {
 150         RTL_TD_0        = 0,
 151         RTL_TD_1        = 1,
 152 };
 153
 154 #define JUMBO_1K        ETH_DATA_LEN
 155 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 156 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 157 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 158 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 159
 160 #define _R(NAME,TD,FW,SZ,B) {   \
 161         .name = NAME,           \
 162         .txd_version = TD,      \
 163         .fw_name = FW,          \
 164         .jumbo_max = SZ,        \
 165         .jumbo_tx_csum = B      \
 166 }
 167
 168 static const struct {
 169         const char *name;
 170         enum rtl_tx_desc_version txd_version;
 171         const char *fw_name;
 172         u16 jumbo_max;
 173         bool jumbo_tx_csum;
 174 } rtl_chip_infos[] = {
 175         /* PCI devices. */
 176         [RTL_GIGA_MAC_VER_01] =
 177                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_02] =
 179                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_03] =
 181                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 182         [RTL_GIGA_MAC_VER_04] =
 183                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 184         [RTL_GIGA_MAC_VER_05] =
 185                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 186         [RTL_GIGA_MAC_VER_06] =
 187                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 188         /* PCI-E devices. */
 189         [RTL_GIGA_MAC_VER_07] =
 190                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_08] =
 192                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_09] =
 194                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_10] =
 196                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_11] =
 198                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 199         [RTL_GIGA_MAC_VER_12] =
 200                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 201         [RTL_GIGA_MAC_VER_13] =
 202                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_14] =
 204                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_15] =
 206                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_16] =
 208                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 209         [RTL_GIGA_MAC_VER_17] =
 210                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 211         [RTL_GIGA_MAC_VER_18] =
 212                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_19] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_20] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_21] =
 218                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_22] =
 220                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 221         [RTL_GIGA_MAC_VER_23] =
 222                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 223         [RTL_GIGA_MAC_VER_24] =
 224                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 225         [RTL_GIGA_MAC_VER_25] =
 226                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 227                                                         JUMBO_9K, false),
 228         [RTL_GIGA_MAC_VER_26] =
 229                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 230                                                         JUMBO_9K, false),
 231         [RTL_GIGA_MAC_VER_27] =
 232                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_28] =
 234                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 235         [RTL_GIGA_MAC_VER_29] =
 236                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 237                                                         JUMBO_1K, true),
 238         [RTL_GIGA_MAC_VER_30] =
 239                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 240                                                         JUMBO_1K, true),
 241         [RTL_GIGA_MAC_VER_31] =
 242                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_32] =
 244                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_33] =
 247                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_34] =
 250                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 251                                                         JUMBO_9K, false),
 252         [RTL_GIGA_MAC_VER_35] =
 253                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 254                                                         JUMBO_9K, false),
 255         [RTL_GIGA_MAC_VER_36] =
 256                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 257                                                         JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_37] =
 259                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 260                                                         JUMBO_1K, true),
 261         [RTL_GIGA_MAC_VER_38] =
 262                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_39] =
 265                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 266                                                         JUMBO_1K, true),
 267 };
 268 #undef _R
 269
 270 enum cfg_version {
 271         RTL_CFG_0 = 0x00,
 272         RTL_CFG_1,
 273         RTL_CFG_2
 274 };
 275
 276 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 277         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 278         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 279         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 280         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 281         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 282         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 283         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 284         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 285         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 286         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 287                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 288         { 0x0001,                               0x8168,
 289                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 290         {0,},
 291 };
 292
 293 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 294
 295 static int rx_buf_sz = 16383;
 296 static int use_dac;
 297 static struct {
 298         u32 msg_enable;
 299 } debug = { -1 };
 300
 301 enum rtl_registers {
 302         MAC0            = 0,    /* Ethernet hardware address. */
 303         MAC4            = 4,
 304         MAR0            = 8,    /* Multicast filter. */
 305         CounterAddrLow          = 0x10,
 306         CounterAddrHigh         = 0x14,
 307         TxDescStartAddrLow      = 0x20,
 308         TxDescStartAddrHigh     = 0x24,
 309         TxHDescStartAddrLow     = 0x28,
 310         TxHDescStartAddrHigh    = 0x2c,
 311         FLASH           = 0x30,
 312         ERSR            = 0x36,
 313         ChipCmd         = 0x37,
 314         TxPoll          = 0x38,
 315         IntrMask        = 0x3c,
 316         IntrStatus      = 0x3e,
 317
 318         TxConfig        = 0x40,
 319 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 320 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 321
 322         RxConfig        = 0x44,
 323 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 324 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 325 #define RXCFG_FIFO_SHIFT                13
 326                                         /* No threshold before first PCI xfer */
 327 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 328 #define RXCFG_DMA_SHIFT                 8
 329                                         /* Unlimited maximum PCI burst. */
 330 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 331
 332         RxMissed        = 0x4c,
 333         Cfg9346         = 0x50,
 334         Config0         = 0x51,
 335         Config1         = 0x52,
 336         Config2         = 0x53,
 337 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 338
 339         Config3         = 0x54,
 340         Config4         = 0x55,
 341         Config5         = 0x56,
 342         MultiIntr       = 0x5c,
 343         PHYAR           = 0x60,
 344         PHYstatus       = 0x6c,
 345         RxMaxSize       = 0xda,
 346         CPlusCmd        = 0xe0,
 347         IntrMitigate    = 0xe2,
 348         RxDescAddrLow   = 0xe4,
 349         RxDescAddrHigh  = 0xe8,
 350         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 351
 352 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 353
 354         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 355
 356 #define TxPacketMax     (8064 >> 7)
 357 #define EarlySize       0x27
 358
 359         FuncEvent       = 0xf0,
 360         FuncEventMask   = 0xf4,
 361         FuncPresetState = 0xf8,
 362         FuncForceEvent  = 0xfc,
 363 };
 364
 365 enum rtl8110_registers {
 366         TBICSR                  = 0x64,
 367         TBI_ANAR                = 0x68,
 368         TBI_LPAR                = 0x6a,
 369 };
 370
 371 enum rtl8168_8101_registers {
 372         CSIDR                   = 0x64,
 373         CSIAR                   = 0x68,
 374 #define CSIAR_FLAG                      0x80000000
 375 #define CSIAR_WRITE_CMD                 0x80000000
 376 #define CSIAR_BYTE_ENABLE               0x0f
 377 #define CSIAR_BYTE_ENABLE_SHIFT         12
 378 #define CSIAR_ADDR_MASK                 0x0fff
 379 #define CSIAR_FUNC_CARD                 0x00000000
 380 #define CSIAR_FUNC_SDIO                 0x00010000
 381 #define CSIAR_FUNC_NIC                  0x00020000
 382         PMCH                    = 0x6f,
 383         EPHYAR                  = 0x80,
 384 #define EPHYAR_FLAG                     0x80000000
 385 #define EPHYAR_WRITE_CMD                0x80000000
 386 #define EPHYAR_REG_MASK                 0x1f
 387 #define EPHYAR_REG_SHIFT                16
 388 #define EPHYAR_DATA_MASK                0xffff
 389         DLLPR                   = 0xd0,
 390 #define PFM_EN                          (1 << 6)
 391         DBG_REG                 = 0xd1,
 392 #define FIX_NAK_1                       (1 << 4)
 393 #define FIX_NAK_2                       (1 << 3)
 394         TWSI                    = 0xd2,
 395         MCU                     = 0xd3,
 396 #define NOW_IS_OOB                      (1 << 7)
 397 #define EN_NDP                          (1 << 3)
 398 #define EN_OOB_RESET                    (1 << 2)
 399         EFUSEAR                 = 0xdc,
 400 #define EFUSEAR_FLAG                    0x80000000
 401 #define EFUSEAR_WRITE_CMD               0x80000000
 402 #define EFUSEAR_READ_CMD                0x00000000
 403 #define EFUSEAR_REG_MASK                0x03ff
 404 #define EFUSEAR_REG_SHIFT               8
 405 #define EFUSEAR_DATA_MASK               0xff
 406 };
 407
 408 enum rtl8168_registers {
 409         LED_FREQ                = 0x1a,
 410         EEE_LED                 = 0x1b,
 411         ERIDR                   = 0x70,
 412         ERIAR                   = 0x74,
 413 #define ERIAR_FLAG                      0x80000000
 414 #define ERIAR_WRITE_CMD                 0x80000000
 415 #define ERIAR_READ_CMD                  0x00000000
 416 #define ERIAR_ADDR_BYTE_ALIGN           4
 417 #define ERIAR_TYPE_SHIFT                16
 418 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 419 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 420 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 421 #define ERIAR_MASK_SHIFT                12
 422 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 423 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 424 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 425         EPHY_RXER_NUM           = 0x7c,
 426         OCPDR                   = 0xb0, /* OCP GPHY access */
 427 #define OCPDR_WRITE_CMD                 0x80000000
 428 #define OCPDR_READ_CMD                  0x00000000
 429 #define OCPDR_REG_MASK                  0x7f
 430 #define OCPDR_GPHY_REG_SHIFT            16
 431 #define OCPDR_DATA_MASK                 0xffff
 432         OCPAR                   = 0xb4,
 433 #define OCPAR_FLAG                      0x80000000
 434 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 435 #define OCPAR_GPHY_READ_CMD             0x0000f060
 436         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 437         MISC                    = 0xf0, /* 8168e only. */
 438 #define TXPLA_RST                       (1 << 29)
 439 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 440 #define PWM_EN                          (1 << 22)
 441 #define EARLY_TALLY_EN                  (1 << 16)
 442 };
 443
 444 enum rtl_register_content {
 445         /* InterruptStatusBits */
 446         SYSErr          = 0x8000,
 447         PCSTimeout      = 0x4000,
 448         SWInt           = 0x0100,
 449         TxDescUnavail   = 0x0080,
 450         RxFIFOOver      = 0x0040,
 451         LinkChg         = 0x0020,
 452         RxOverflow      = 0x0010,
 453         TxErr           = 0x0008,
 454         TxOK            = 0x0004,
 455         RxErr           = 0x0002,
 456         RxOK            = 0x0001,
 457
 458         /* RxStatusDesc */
 459         RxBOVF  = (1 << 24),
 460         RxFOVF  = (1 << 23),
 461         RxRWT   = (1 << 22),
 462         RxRES   = (1 << 21),
 463         RxRUNT  = (1 << 20),
 464         RxCRC   = (1 << 19),
 465
 466         /* ChipCmdBits */
 467         StopReq         = 0x80,
 468         CmdReset        = 0x10,
 469         CmdRxEnb        = 0x08,
 470         CmdTxEnb        = 0x04,
 471         RxBufEmpty      = 0x01,
 472
 473         /* TXPoll register p.5 */
 474         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 475         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 476         FSWInt          = 0x01,         /* Forced software interrupt */
 477
 478         /* Cfg9346Bits */
 479         Cfg9346_Lock    = 0x00,
 480         Cfg9346_Unlock  = 0xc0,
 481
 482         /* rx_mode_bits */
 483         AcceptErr       = 0x20,
 484         AcceptRunt      = 0x10,
 485         AcceptBroadcast = 0x08,
 486         AcceptMulticast = 0x04,
 487         AcceptMyPhys    = 0x02,
 488         AcceptAllPhys   = 0x01,
 489 #define RX_CONFIG_ACCEPT_MASK           0x3f
 490
 491         /* TxConfigBits */
 492         TxInterFrameGapShift = 24,
 493         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 494
 495         /* Config1 register p.24 */
 496         LEDS1           = (1 << 7),
 497         LEDS0           = (1 << 6),
 498         Speed_down      = (1 << 4),
 499         MEMMAP          = (1 << 3),
 500         IOMAP           = (1 << 2),
 501         VPD             = (1 << 1),
 502         PMEnable        = (1 << 0),     /* Power Management Enable */
 503
 504         /* Config2 register p. 25 */
 505         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 506         PCI_Clock_66MHz = 0x01,
 507         PCI_Clock_33MHz = 0x00,
 508
 509         /* Config3 register p.25 */
 510         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 511         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 512         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 513         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 514
 515         /* Config4 register */
 516         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 517
 518         /* Config5 register p.27 */
 519         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 520         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 521         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 522         Spi_en          = (1 << 3),
 523         LanWake         = (1 << 1),     /* LanWake enable/disable */
 524         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 525
 526         /* TBICSR p.28 */
 527         TBIReset        = 0x80000000,
 528         TBILoopback     = 0x40000000,
 529         TBINwEnable     = 0x20000000,
 530         TBINwRestart    = 0x10000000,
 531         TBILinkOk       = 0x02000000,
 532         TBINwComplete   = 0x01000000,
 533
 534         /* CPlusCmd p.31 */
 535         EnableBist      = (1 << 15),    // 8168 8101
 536         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 537         Normal_mode     = (1 << 13),    // unused
 538         Force_half_dup  = (1 << 12),    // 8168 8101
 539         Force_rxflow_en = (1 << 11),    // 8168 8101
 540         Force_txflow_en = (1 << 10),    // 8168 8101
 541         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 542         ASF             = (1 << 8),     // 8168 8101
 543         PktCntrDisable  = (1 << 7),     // 8168 8101
 544         Mac_dbgo_sel    = 0x001c,       // 8168
 545         RxVlan          = (1 << 6),
 546         RxChkSum        = (1 << 5),
 547         PCIDAC          = (1 << 4),
 548         PCIMulRW        = (1 << 3),
 549         INTT_0          = 0x0000,       // 8168
 550         INTT_1          = 0x0001,       // 8168
 551         INTT_2          = 0x0002,       // 8168
 552         INTT_3          = 0x0003,       // 8168
 553
 554         /* rtl8169_PHYstatus */
 555         TBI_Enable      = 0x80,
 556         TxFlowCtrl      = 0x40,
 557         RxFlowCtrl      = 0x20,
 558         _1000bpsF       = 0x10,
 559         _100bps         = 0x08,
 560         _10bps          = 0x04,
 561         LinkStatus      = 0x02,
 562         FullDup         = 0x01,
 563
 564         /* _TBICSRBit */
 565         TBILinkOK       = 0x02000000,
 566
 567         /* DumpCounterCommand */
 568         CounterDump     = 0x8,
 569 };
 570
 571 enum rtl_desc_bit {
 572         /* First doubleword. */
 573         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 574         RingEnd         = (1 << 30), /* End of descriptor ring */
 575         FirstFrag       = (1 << 29), /* First segment of a packet */
 576         LastFrag        = (1 << 28), /* Final segment of a packet */
 577 };
 578
 579 /* Generic case. */
 580 enum rtl_tx_desc_bit {
 581         /* First doubleword. */
 582         TD_LSO          = (1 << 27),            /* Large Send Offload */
 583 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 584
 585         /* Second doubleword. */
 586         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 587 };
 588
 589 /* 8169, 8168b and 810x except 8102e. */
 590 enum rtl_tx_desc_bit_0 {
 591         /* First doubleword. */
 592 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 593         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 594         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 595         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 596 };
 597
 598 /* 8102e, 8168c and beyond. */
 599 enum rtl_tx_desc_bit_1 {
 600         /* Second doubleword. */
 601 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 602         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 603         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 604         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 605 };
 606
 607 static const struct rtl_tx_desc_info {
 608         struct {
 609                 u32 udp;
 610                 u32 tcp;
 611         } checksum;
 612         u16 mss_shift;
 613         u16 opts_offset;
 614 } tx_desc_info [] = {
 615         [RTL_TD_0] = {
 616                 .checksum = {
 617                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 618                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 619                 },
 620                 .mss_shift      = TD0_MSS_SHIFT,
 621                 .opts_offset    = 0
 622         },
 623         [RTL_TD_1] = {
 624                 .checksum = {
 625                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 626                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 627                 },
 628                 .mss_shift      = TD1_MSS_SHIFT,
 629                 .opts_offset    = 1
 630         }
 631 };
 632
 633 enum rtl_rx_desc_bit {
 634         /* Rx private */
 635         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 636         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 637
 638 #define RxProtoUDP      (PID1)
 639 #define RxProtoTCP      (PID0)
 640 #define RxProtoIP       (PID1 | PID0)
 641 #define RxProtoMask     RxProtoIP
 642
 643         IPFail          = (1 << 16), /* IP checksum failed */
 644         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 645         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 646         RxVlanTag       = (1 << 16), /* VLAN tag available */
 647 };
 648
 649 #define RsvdMask        0x3fffc000
 650
 651 struct TxDesc {
 652         __le32 opts1;
 653         __le32 opts2;
 654         __le64 addr;
 655 };
 656
 657 struct RxDesc {
 658         __le32 opts1;
 659         __le32 opts2;
 660         __le64 addr;
 661 };
 662
 663 struct ring_info {
 664         struct sk_buff  *skb;
 665         u32             len;
 666         u8              __pad[sizeof(void *) - sizeof(u32)];
 667 };
 668
 669 enum features {
 670         RTL_FEATURE_WOL         = (1 << 0),
 671         RTL_FEATURE_MSI         = (1 << 1),
 672         RTL_FEATURE_GMII        = (1 << 2),
 673 };
 674
 675 struct rtl8169_counters {
 676         __le64  tx_packets;
 677         __le64  rx_packets;
 678         __le64  tx_errors;
 679         __le32  rx_errors;
 680         __le16  rx_missed;
 681         __le16  align_errors;
 682         __le32  tx_one_collision;
 683         __le32  tx_multi_collision;
 684         __le64  rx_unicast;
 685         __le64  rx_broadcast;
 686         __le32  rx_multicast;
 687         __le16  tx_aborted;
 688         __le16  tx_underun;
 689 };
 690
 691 enum rtl_flag {
 692         RTL_FLAG_TASK_ENABLED,
 693         RTL_FLAG_TASK_SLOW_PENDING,
 694         RTL_FLAG_TASK_RESET_PENDING,
 695         RTL_FLAG_TASK_PHY_PENDING,
 696         RTL_FLAG_MAX
 697 };
 698
 699 struct rtl8169_stats {
 700         u64                     packets;
 701         u64                     bytes;
 702         struct u64_stats_sync   syncp;
 703 };
 704
 705 struct rtl8169_private {
 706         void __iomem *mmio_addr;        /* memory map physical address */
 707         struct pci_dev *pci_dev;
 708         struct net_device *dev;
 709         struct napi_struct napi;
 710         u32 msg_enable;
 711         u16 txd_version;
 712         u16 mac_version;
 713         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 714         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 715         u32 dirty_rx;
 716         u32 dirty_tx;
 717         struct rtl8169_stats rx_stats;
 718         struct rtl8169_stats tx_stats;
 719         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 720         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 721         dma_addr_t TxPhyAddr;
 722         dma_addr_t RxPhyAddr;
 723         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 724         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 725         struct timer_list timer;
 726         u16 cp_cmd;
 727
 728         u16 event_slow;
 729
 730         struct mdio_ops {
 731                 void (*write)(void __iomem *, int, int);
 732                 int (*read)(void __iomem *, int);
 733         } mdio_ops;
 734
 735         struct pll_power_ops {
 736                 void (*down)(struct rtl8169_private *);
 737                 void (*up)(struct rtl8169_private *);
 738         } pll_power_ops;
 739
 740         struct jumbo_ops {
 741                 void (*enable)(struct rtl8169_private *);
 742                 void (*disable)(struct rtl8169_private *);
 743         } jumbo_ops;
 744
 745         struct csi_ops {
 746                 void (*write)(void __iomem *, int, int);
 747                 u32 (*read)(void __iomem *, int);
 748         } csi_ops;
 749
 750         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 751         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 752         void (*phy_reset_enable)(struct rtl8169_private *tp);
 753         void (*hw_start)(struct net_device *);
 754         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 755         unsigned int (*link_ok)(void __iomem *);
 756         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 757
 758         struct {
 759                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 760                 struct mutex mutex;
 761                 struct work_struct work;
 762         } wk;
 763
 764         unsigned features;
 765
 766         struct mii_if_info mii;
 767         struct rtl8169_counters counters;
 768         u32 saved_wolopts;
 769         u32 opts1_mask;
 770
 771         struct rtl_fw {
 772                 const struct firmware *fw;
 773
 774 #define RTL_VER_SIZE            32
 775
 776                 char version[RTL_VER_SIZE];
 777
 778                 struct rtl_fw_phy_action {
 779                         __le32 *code;
 780                         size_t size;
 781                 } phy_action;
 782         } *rtl_fw;
 783 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 784 };
 785
 786 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 787 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 788 module_param(use_dac, int, 0);
 789 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 790 module_param_named(debug, debug.msg_enable, int, 0);
 791 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 792 MODULE_LICENSE("GPL");
 793 MODULE_VERSION(RTL8169_VERSION);
 794 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 795 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 796 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 797 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 798 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 799 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 800 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 801 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 802 MODULE_FIRMWARE(FIRMWARE_8402_1);
 803 MODULE_FIRMWARE(FIRMWARE_8411_1);
 804 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 805
 806 static void rtl_lock_work(struct rtl8169_private *tp)
 807 {
 808         mutex_lock(&tp->wk.mutex);
 809 }
 810
 811 static void rtl_unlock_work(struct rtl8169_private *tp)
 812 {
 813         mutex_unlock(&tp->wk.mutex);
 814 }
 815
 816 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 817 {
 818         int cap = pci_pcie_cap(pdev);
 819
 820         if (cap) {
 821                 u16 ctl;
 822
 823                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 824                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 825                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 826         }
 827 }
 828
 829 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 830 {
 831         void __iomem *ioaddr = tp->mmio_addr;
 832         int i;
 833
 834         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 835         for (i = 0; i < 20; i++) {
 836                 udelay(100);
 837                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 838                         break;
 839         }
 840         return RTL_R32(OCPDR);
 841 }
 842
 843 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 844 {
 845         void __iomem *ioaddr = tp->mmio_addr;
 846         int i;
 847
 848         RTL_W32(OCPDR, data);
 849         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 850         for (i = 0; i < 20; i++) {
 851                 udelay(100);
 852                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 853                         break;
 854         }
 855 }
 856
 857 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 858 {
 859         void __iomem *ioaddr = tp->mmio_addr;
 860         int i;
 861
 862         RTL_W8(ERIDR, cmd);
 863         RTL_W32(ERIAR, 0x800010e8);
 864         msleep(2);
 865         for (i = 0; i < 5; i++) {
 866                 udelay(100);
 867                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 868                         break;
 869         }
 870
 871         ocp_write(tp, 0x1, 0x30, 0x00000001);
 872 }
 873
 874 #define OOB_CMD_RESET           0x00
 875 #define OOB_CMD_DRIVER_START    0x05
 876 #define OOB_CMD_DRIVER_STOP     0x06
 877
 878 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 879 {
 880         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 881 }
 882
 883 static void rtl8168_driver_start(struct rtl8169_private *tp)
 884 {
 885         u16 reg;
 886         int i;
 887
 888         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 889
 890         reg = rtl8168_get_ocp_reg(tp);
 891
 892         for (i = 0; i < 10; i++) {
 893                 msleep(10);
 894                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 895                         break;
 896         }
 897 }
 898
 899 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 900 {
 901         u16 reg;
 902         int i;
 903
 904         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 905
 906         reg = rtl8168_get_ocp_reg(tp);
 907
 908         for (i = 0; i < 10; i++) {
 909                 msleep(10);
 910                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 911                         break;
 912         }
 913 }
 914
 915 static int r8168dp_check_dash(struct rtl8169_private *tp)
 916 {
 917         u16 reg = rtl8168_get_ocp_reg(tp);
 918
 919         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 920 }
 921
 922 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 923 {
 924         int i;
 925
 926         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 927
 928         for (i = 20; i > 0; i--) {
 929                 /*
 930                  * Check if the RTL8169 has completed writing to the specified
 931                  * MII register.
 932                  */
 933                 if (!(RTL_R32(PHYAR) & 0x80000000))
 934                         break;
 935                 udelay(25);
 936         }
 937         /*
 938          * According to hardware specs a 20us delay is required after write
 939          * complete indication, but before sending next command.
 940          */
 941         udelay(20);
 942 }
 943
 944 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 945 {
 946         int i, value = -1;
 947
 948         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 949
 950         for (i = 20; i > 0; i--) {
 951                 /*
 952                  * Check if the RTL8169 has completed retrieving data from
 953                  * the specified MII register.
 954                  */
 955                 if (RTL_R32(PHYAR) & 0x80000000) {
 956                         value = RTL_R32(PHYAR) & 0xffff;
 957                         break;
 958                 }
 959                 udelay(25);
 960         }
 961         /*
 962          * According to hardware specs a 20us delay is required after read
 963          * complete indication, but before sending next command.
 964          */
 965         udelay(20);
 966
 967         return value;
 968 }
 969
 970 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 971 {
 972         int i;
 973
 974         RTL_W32(OCPDR, data |
 975                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 976         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 977         RTL_W32(EPHY_RXER_NUM, 0);
 978
 979         for (i = 0; i < 100; i++) {
 980                 mdelay(1);
 981                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 982                         break;
 983         }
 984 }
 985
 986 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 987 {
 988         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 989                 (value & OCPDR_DATA_MASK));
 990 }
 991
 992 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 993 {
 994         int i;
 995
 996         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 997
 998         mdelay(1);
 999         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1000         RTL_W32(EPHY_RXER_NUM, 0);
1001
1002         for (i = 0; i < 100; i++) {
1003                 mdelay(1);
1004                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
1005                         break;
1006         }
1007
1008         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
1009 }
1010
1011 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1012
1013 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1014 {
1015         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1016 }
1017
1018 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1019 {
1020         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1021 }
1022
1023 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1024 {
1025         r8168dp_2_mdio_start(ioaddr);
1026
1027         r8169_mdio_write(ioaddr, reg_addr, value);
1028
1029         r8168dp_2_mdio_stop(ioaddr);
1030 }
1031
1032 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1033 {
1034         int value;
1035
1036         r8168dp_2_mdio_start(ioaddr);
1037
1038         value = r8169_mdio_read(ioaddr, reg_addr);
1039
1040         r8168dp_2_mdio_stop(ioaddr);
1041
1042         return value;
1043 }
1044
1045 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1046 {
1047         tp->mdio_ops.write(tp->mmio_addr, location, val);
1048 }
1049
1050 static int rtl_readphy(struct rtl8169_private *tp, int location)
1051 {
1052         return tp->mdio_ops.read(tp->mmio_addr, location);
1053 }
1054
1055 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1056 {
1057         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1058 }
1059
1060 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1061 {
1062         int val;
1063
1064         val = rtl_readphy(tp, reg_addr);
1065         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1066 }
1067
1068 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1069                            int val)
1070 {
1071         struct rtl8169_private *tp = netdev_priv(dev);
1072
1073         rtl_writephy(tp, location, val);
1074 }
1075
1076 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1077 {
1078         struct rtl8169_private *tp = netdev_priv(dev);
1079
1080         return rtl_readphy(tp, location);
1081 }
1082
1083 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1084 {
1085         unsigned int i;
1086
1087         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1088                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1089
1090         for (i = 0; i < 100; i++) {
1091                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1092                         break;
1093                 udelay(10);
1094         }
1095 }
1096
1097 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1098 {
1099         u16 value = 0xffff;
1100         unsigned int i;
1101
1102         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1103
1104         for (i = 0; i < 100; i++) {
1105                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1106                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1107                         break;
1108                 }
1109                 udelay(10);
1110         }
1111
1112         return value;
1113 }
1114
1115 static
1116 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1117 {
1118         unsigned int i;
1119
1120         BUG_ON((addr & 3) || (mask == 0));
1121         RTL_W32(ERIDR, val);
1122         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1123
1124         for (i = 0; i < 100; i++) {
1125                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1126                         break;
1127                 udelay(100);
1128         }
1129 }
1130
1131 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1132 {
1133         u32 value = ~0x00;
1134         unsigned int i;
1135
1136         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1137
1138         for (i = 0; i < 100; i++) {
1139                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1140                         value = RTL_R32(ERIDR);
1141                         break;
1142                 }
1143                 udelay(100);
1144         }
1145
1146         return value;
1147 }
1148
1149 static void
1150 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1151 {
1152         u32 val;
1153
1154         val = rtl_eri_read(ioaddr, addr, type);
1155         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1156 }
1157
1158 struct exgmac_reg {
1159         u16 addr;
1160         u16 mask;
1161         u32 val;
1162 };
1163
1164 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1165                                    const struct exgmac_reg *r, int len)
1166 {
1167         while (len-- > 0) {
1168                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1169                 r++;
1170         }
1171 }
1172
1173 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1174 {
1175         u8 value = 0xff;
1176         unsigned int i;
1177
1178         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1179
1180         for (i = 0; i < 300; i++) {
1181                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1182                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1183                         break;
1184                 }
1185                 udelay(100);
1186         }
1187
1188         return value;
1189 }
1190
1191 static u16 rtl_get_events(struct rtl8169_private *tp)
1192 {
1193         void __iomem *ioaddr = tp->mmio_addr;
1194
1195         return RTL_R16(IntrStatus);
1196 }
1197
1198 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1199 {
1200         void __iomem *ioaddr = tp->mmio_addr;
1201
1202         RTL_W16(IntrStatus, bits);
1203         mmiowb();
1204 }
1205
1206 static void rtl_irq_disable(struct rtl8169_private *tp)
1207 {
1208         void __iomem *ioaddr = tp->mmio_addr;
1209
1210         RTL_W16(IntrMask, 0);
1211         mmiowb();
1212 }
1213
1214 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1215 {
1216         void __iomem *ioaddr = tp->mmio_addr;
1217
1218         RTL_W16(IntrMask, bits);
1219 }
1220
1221 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1222 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1223 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1224
1225 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1226 {
1227         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1228 }
1229
1230 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233
1234         rtl_irq_disable(tp);
1235         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1236         RTL_R8(ChipCmd);
1237 }
1238
1239 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1240 {
1241         void __iomem *ioaddr = tp->mmio_addr;
1242
1243         return RTL_R32(TBICSR) & TBIReset;
1244 }
1245
1246 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1247 {
1248         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1249 }
1250
1251 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1252 {
1253         return RTL_R32(TBICSR) & TBILinkOk;
1254 }
1255
1256 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1257 {
1258         return RTL_R8(PHYstatus) & LinkStatus;
1259 }
1260
1261 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1262 {
1263         void __iomem *ioaddr = tp->mmio_addr;
1264
1265         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1266 }
1267
1268 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1269 {
1270         unsigned int val;
1271
1272         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1273         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1274 }
1275
1276 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1277 {
1278         void __iomem *ioaddr = tp->mmio_addr;
1279         struct net_device *dev = tp->dev;
1280
1281         if (!netif_running(dev))
1282                 return;
1283
1284         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1285             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1286                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1287                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1288                                       0x00000011, ERIAR_EXGMAC);
1289                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1290                                       0x00000005, ERIAR_EXGMAC);
1291                 } else if (RTL_R8(PHYstatus) & _100bps) {
1292                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1293                                       0x0000001f, ERIAR_EXGMAC);
1294                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1295                                       0x00000005, ERIAR_EXGMAC);
1296                 } else {
1297                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1298                                       0x0000001f, ERIAR_EXGMAC);
1299                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1300                                       0x0000003f, ERIAR_EXGMAC);
1301                 }
1302                 /* Reset packet filter */
1303                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1304                              ERIAR_EXGMAC);
1305                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1306                              ERIAR_EXGMAC);
1307         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1308                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1309                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1310                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1311                                       0x00000011, ERIAR_EXGMAC);
1312                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1313                                       0x00000005, ERIAR_EXGMAC);
1314                 } else {
1315                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1316                                       0x0000001f, ERIAR_EXGMAC);
1317                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1318                                       0x0000003f, ERIAR_EXGMAC);
1319                 }
1320         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1321                 if (RTL_R8(PHYstatus) & _10bps) {
1322                         rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1323                                       0x4d02, ERIAR_EXGMAC);
1324                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_0011,
1325                                       0x0060, ERIAR_EXGMAC);
1326                 } else {
1327                         rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011,
1328                                       0x0000, ERIAR_EXGMAC);
1329                 }
1330         }
1331 }
1332
1333 static void __rtl8169_check_link_status(struct net_device *dev,
1334                                         struct rtl8169_private *tp,
1335                                         void __iomem *ioaddr, bool pm)
1336 {
1337         if (tp->link_ok(ioaddr)) {
1338                 rtl_link_chg_patch(tp);
1339                 /* This is to cancel a scheduled suspend if there's one. */
1340                 if (pm)
1341                         pm_request_resume(&tp->pci_dev->dev);
1342                 netif_carrier_on(dev);
1343                 if (net_ratelimit())
1344                         netif_info(tp, ifup, dev, "link up\n");
1345         } else {
1346                 netif_carrier_off(dev);
1347                 netif_info(tp, ifdown, dev, "link down\n");
1348                 if (pm)
1349                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1350         }
1351 }
1352
1353 static void rtl8169_check_link_status(struct net_device *dev,
1354                                       struct rtl8169_private *tp,
1355                                       void __iomem *ioaddr)
1356 {
1357         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1358 }
1359
1360 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1361
1362 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365         u8 options;
1366         u32 wolopts = 0;
1367
1368         options = RTL_R8(Config1);
1369         if (!(options & PMEnable))
1370                 return 0;
1371
1372         options = RTL_R8(Config3);
1373         if (options & LinkUp)
1374                 wolopts |= WAKE_PHY;
1375         if (options & MagicPacket)
1376                 wolopts |= WAKE_MAGIC;
1377
1378         options = RTL_R8(Config5);
1379         if (options & UWF)
1380                 wolopts |= WAKE_UCAST;
1381         if (options & BWF)
1382                 wolopts |= WAKE_BCAST;
1383         if (options & MWF)
1384                 wolopts |= WAKE_MCAST;
1385
1386         return wolopts;
1387 }
1388
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1390 {
1391         struct rtl8169_private *tp = netdev_priv(dev);
1392
1393         rtl_lock_work(tp);
1394
1395         wol->supported = WAKE_ANY;
1396         wol->wolopts = __rtl8169_get_wol(tp);
1397
1398         rtl_unlock_work(tp);
1399 }
1400
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1402 {
1403         void __iomem *ioaddr = tp->mmio_addr;
1404         unsigned int i;
1405         static const struct {
1406                 u32 opt;
1407                 u16 reg;
1408                 u8  mask;
1409         } cfg[] = {
1410                 { WAKE_PHY,   Config3, LinkUp },
1411                 { WAKE_MAGIC, Config3, MagicPacket },
1412                 { WAKE_UCAST, Config5, UWF },
1413                 { WAKE_BCAST, Config5, BWF },
1414                 { WAKE_MCAST, Config5, MWF },
1415                 { WAKE_ANY,   Config5, LanWake }
1416         };
1417         u8 options;
1418
1419         RTL_W8(Cfg9346, Cfg9346_Unlock);
1420
1421         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1422                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1423                 if (wolopts & cfg[i].opt)
1424                         options |= cfg[i].mask;
1425                 RTL_W8(cfg[i].reg, options);
1426         }
1427
1428         switch (tp->mac_version) {
1429         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1430                 options = RTL_R8(Config1) & ~PMEnable;
1431                 if (wolopts)
1432                         options |= PMEnable;
1433                 RTL_W8(Config1, options);
1434                 break;
1435         default:
1436                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1437                 if (wolopts)
1438                         options |= PME_SIGNAL;
1439                 RTL_W8(Config2, options);
1440                 break;
1441         }
1442
1443         RTL_W8(Cfg9346, Cfg9346_Lock);
1444 }
1445
1446 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1447 {
1448         struct rtl8169_private *tp = netdev_priv(dev);
1449
1450         rtl_lock_work(tp);
1451
1452         if (wol->wolopts)
1453                 tp->features |= RTL_FEATURE_WOL;
1454         else
1455                 tp->features &= ~RTL_FEATURE_WOL;
1456         __rtl8169_set_wol(tp, wol->wolopts);
1457
1458         rtl_unlock_work(tp);
1459
1460         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1461
1462         return 0;
1463 }
1464
1465 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1466 {
1467         return rtl_chip_infos[tp->mac_version].fw_name;
1468 }
1469
1470 static void rtl8169_get_drvinfo(struct net_device *dev,
1471                                 struct ethtool_drvinfo *info)
1472 {
1473         struct rtl8169_private *tp = netdev_priv(dev);
1474         struct rtl_fw *rtl_fw = tp->rtl_fw;
1475
1476         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1477         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1478         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1479         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1480         if (!IS_ERR_OR_NULL(rtl_fw))
1481                 strlcpy(info->fw_version, rtl_fw->version,
1482                         sizeof(info->fw_version));
1483 }
1484
1485 static int rtl8169_get_regs_len(struct net_device *dev)
1486 {
1487         return R8169_REGS_SIZE;
1488 }
1489
1490 static int rtl8169_set_speed_tbi(struct net_device *dev,
1491                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1492 {
1493         struct rtl8169_private *tp = netdev_priv(dev);
1494         void __iomem *ioaddr = tp->mmio_addr;
1495         int ret = 0;
1496         u32 reg;
1497
1498         reg = RTL_R32(TBICSR);
1499         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1500             (duplex == DUPLEX_FULL)) {
1501                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1502         } else if (autoneg == AUTONEG_ENABLE)
1503                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1504         else {
1505                 netif_warn(tp, link, dev,
1506                            "incorrect speed setting refused in TBI mode\n");
1507                 ret = -EOPNOTSUPP;
1508         }
1509
1510         return ret;
1511 }
1512
1513 static int rtl8169_set_speed_xmii(struct net_device *dev,
1514                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1515 {
1516         struct rtl8169_private *tp = netdev_priv(dev);
1517         int giga_ctrl, bmcr;
1518         int rc = -EINVAL;
1519
1520         rtl_writephy(tp, 0x1f, 0x0000);
1521
1522         if (autoneg == AUTONEG_ENABLE) {
1523                 int auto_nego;
1524
1525                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1526                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1527                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1528
1529                 if (adv & ADVERTISED_10baseT_Half)
1530                         auto_nego |= ADVERTISE_10HALF;
1531                 if (adv & ADVERTISED_10baseT_Full)
1532                         auto_nego |= ADVERTISE_10FULL;
1533                 if (adv & ADVERTISED_100baseT_Half)
1534                         auto_nego |= ADVERTISE_100HALF;
1535                 if (adv & ADVERTISED_100baseT_Full)
1536                         auto_nego |= ADVERTISE_100FULL;
1537
1538                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1539
1540                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1541                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1542
1543                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1544                 if (tp->mii.supports_gmii) {
1545                         if (adv & ADVERTISED_1000baseT_Half)
1546                                 giga_ctrl |= ADVERTISE_1000HALF;
1547                         if (adv & ADVERTISED_1000baseT_Full)
1548                                 giga_ctrl |= ADVERTISE_1000FULL;
1549                 } else if (adv & (ADVERTISED_1000baseT_Half |
1550                                   ADVERTISED_1000baseT_Full)) {
1551                         netif_info(tp, link, dev,
1552                                    "PHY does not support 1000Mbps\n");
1553                         goto out;
1554                 }
1555
1556                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1557
1558                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1559                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1560         } else {
1561                 giga_ctrl = 0;
1562
1563                 if (speed == SPEED_10)
1564                         bmcr = 0;
1565                 else if (speed == SPEED_100)
1566                         bmcr = BMCR_SPEED100;
1567                 else
1568                         goto out;
1569
1570                 if (duplex == DUPLEX_FULL)
1571                         bmcr |= BMCR_FULLDPLX;
1572         }
1573
1574         rtl_writephy(tp, MII_BMCR, bmcr);
1575
1576         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1577             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1578                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1579                         rtl_writephy(tp, 0x17, 0x2138);
1580                         rtl_writephy(tp, 0x0e, 0x0260);
1581                 } else {
1582                         rtl_writephy(tp, 0x17, 0x2108);
1583                         rtl_writephy(tp, 0x0e, 0x0000);
1584                 }
1585         }
1586
1587         rc = 0;
1588 out:
1589         return rc;
1590 }
1591
1592 static int rtl8169_set_speed(struct net_device *dev,
1593                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596         int ret;
1597
1598         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1599         if (ret < 0)
1600                 goto out;
1601
1602         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1603             (advertising & ADVERTISED_1000baseT_Full)) {
1604                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1605         }
1606 out:
1607         return ret;
1608 }
1609
1610 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1611 {
1612         struct rtl8169_private *tp = netdev_priv(dev);
1613         int ret;
1614
1615         del_timer_sync(&tp->timer);
1616
1617         rtl_lock_work(tp);
1618         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1619                                 cmd->duplex, cmd->advertising);
1620         rtl_unlock_work(tp);
1621
1622         return ret;
1623 }
1624
1625 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1626         netdev_features_t features)
1627 {
1628         struct rtl8169_private *tp = netdev_priv(dev);
1629
1630         if (dev->mtu > TD_MSS_MAX)
1631                 features &= ~NETIF_F_ALL_TSO;
1632
1633         if (dev->mtu > JUMBO_1K &&
1634             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1635                 features &= ~NETIF_F_IP_CSUM;
1636
1637         return features;
1638 }
1639
1640 static void __rtl8169_set_features(struct net_device *dev,
1641                                    netdev_features_t features)
1642 {
1643         struct rtl8169_private *tp = netdev_priv(dev);
1644         netdev_features_t changed = features ^ dev->features;
1645         void __iomem *ioaddr = tp->mmio_addr;
1646
1647         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1648                 return;
1649
1650         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1651                 if (features & NETIF_F_RXCSUM)
1652                         tp->cp_cmd |= RxChkSum;
1653                 else
1654                         tp->cp_cmd &= ~RxChkSum;
1655
1656                 if (dev->features & NETIF_F_HW_VLAN_RX)
1657                         tp->cp_cmd |= RxVlan;
1658                 else
1659                         tp->cp_cmd &= ~RxVlan;
1660
1661                 RTL_W16(CPlusCmd, tp->cp_cmd);
1662                 RTL_R16(CPlusCmd);
1663         }
1664         if (changed & NETIF_F_RXALL) {
1665                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1666                 if (features & NETIF_F_RXALL)
1667                         tmp |= (AcceptErr | AcceptRunt);
1668                 RTL_W32(RxConfig, tmp);
1669         }
1670 }
1671
1672 static int rtl8169_set_features(struct net_device *dev,
1673                                 netdev_features_t features)
1674 {
1675         struct rtl8169_private *tp = netdev_priv(dev);
1676
1677         rtl_lock_work(tp);
1678         __rtl8169_set_features(dev, features);
1679         rtl_unlock_work(tp);
1680
1681         return 0;
1682 }
1683
1684
1685 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1686                                       struct sk_buff *skb)
1687 {
1688         return (vlan_tx_tag_present(skb)) ?
1689                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1690 }
1691
1692 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1693 {
1694         u32 opts2 = le32_to_cpu(desc->opts2);
1695
1696         if (opts2 & RxVlanTag)
1697                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1698
1699         desc->opts2 = 0;
1700 }
1701
1702 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1703 {
1704         struct rtl8169_private *tp = netdev_priv(dev);
1705         void __iomem *ioaddr = tp->mmio_addr;
1706         u32 status;
1707
1708         cmd->supported =
1709                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1710         cmd->port = PORT_FIBRE;
1711         cmd->transceiver = XCVR_INTERNAL;
1712
1713         status = RTL_R32(TBICSR);
1714         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1715         cmd->autoneg = !!(status & TBINwEnable);
1716
1717         ethtool_cmd_speed_set(cmd, SPEED_1000);
1718         cmd->duplex = DUPLEX_FULL; /* Always set */
1719
1720         return 0;
1721 }
1722
1723 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1724 {
1725         struct rtl8169_private *tp = netdev_priv(dev);
1726
1727         return mii_ethtool_gset(&tp->mii, cmd);
1728 }
1729
1730 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1731 {
1732         struct rtl8169_private *tp = netdev_priv(dev);
1733         int rc;
1734
1735         rtl_lock_work(tp);
1736         rc = tp->get_settings(dev, cmd);
1737         rtl_unlock_work(tp);
1738
1739         return rc;
1740 }
1741
1742 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1743                              void *p)
1744 {
1745         struct rtl8169_private *tp = netdev_priv(dev);
1746
1747         if (regs->len > R8169_REGS_SIZE)
1748                 regs->len = R8169_REGS_SIZE;
1749
1750         rtl_lock_work(tp);
1751         memcpy_fromio(p, tp->mmio_addr, regs->len);
1752         rtl_unlock_work(tp);
1753 }
1754
1755 static u32 rtl8169_get_msglevel(struct net_device *dev)
1756 {
1757         struct rtl8169_private *tp = netdev_priv(dev);
1758
1759         return tp->msg_enable;
1760 }
1761
1762 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1763 {
1764         struct rtl8169_private *tp = netdev_priv(dev);
1765
1766         tp->msg_enable = value;
1767 }
1768
1769 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1770         "tx_packets",
1771         "rx_packets",
1772         "tx_errors",
1773         "rx_errors",
1774         "rx_missed",
1775         "align_errors",
1776         "tx_single_collisions",
1777         "tx_multi_collisions",
1778         "unicast",
1779         "broadcast",
1780         "multicast",
1781         "tx_aborted",
1782         "tx_underrun",
1783 };
1784
1785 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1786 {
1787         switch (sset) {
1788         case ETH_SS_STATS:
1789                 return ARRAY_SIZE(rtl8169_gstrings);
1790         default:
1791                 return -EOPNOTSUPP;
1792         }
1793 }
1794
1795 static void rtl8169_update_counters(struct net_device *dev)
1796 {
1797         struct rtl8169_private *tp = netdev_priv(dev);
1798         void __iomem *ioaddr = tp->mmio_addr;
1799         struct device *d = &tp->pci_dev->dev;
1800         struct rtl8169_counters *counters;
1801         dma_addr_t paddr;
1802         u32 cmd;
1803         int wait = 1000;
1804
1805         /*
1806          * Some chips are unable to dump tally counters when the receiver
1807          * is disabled.
1808          */
1809         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1810                 return;
1811
1812         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1813         if (!counters)
1814                 return;
1815
1816         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1817         cmd = (u64)paddr & DMA_BIT_MASK(32);
1818         RTL_W32(CounterAddrLow, cmd);
1819         RTL_W32(CounterAddrLow, cmd | CounterDump);
1820
1821         while (wait--) {
1822                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1823                         memcpy(&tp->counters, counters, sizeof(*counters));
1824                         break;
1825                 }
1826                 udelay(10);
1827         }
1828
1829         RTL_W32(CounterAddrLow, 0);
1830         RTL_W32(CounterAddrHigh, 0);
1831
1832         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1833 }
1834
1835 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1836                                       struct ethtool_stats *stats, u64 *data)
1837 {
1838         struct rtl8169_private *tp = netdev_priv(dev);
1839
1840         ASSERT_RTNL();
1841
1842         rtl8169_update_counters(dev);
1843
1844         data[0] = le64_to_cpu(tp->counters.tx_packets);
1845         data[1] = le64_to_cpu(tp->counters.rx_packets);
1846         data[2] = le64_to_cpu(tp->counters.tx_errors);
1847         data[3] = le32_to_cpu(tp->counters.rx_errors);
1848         data[4] = le16_to_cpu(tp->counters.rx_missed);
1849         data[5] = le16_to_cpu(tp->counters.align_errors);
1850         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1851         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1852         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1853         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1854         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1855         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1856         data[12] = le16_to_cpu(tp->counters.tx_underun);
1857 }
1858
1859 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1860 {
1861         switch(stringset) {
1862         case ETH_SS_STATS:
1863                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1864                 break;
1865         }
1866 }
1867
1868 static const struct ethtool_ops rtl8169_ethtool_ops = {
1869         .get_drvinfo            = rtl8169_get_drvinfo,
1870         .get_regs_len           = rtl8169_get_regs_len,
1871         .get_link               = ethtool_op_get_link,
1872         .get_settings           = rtl8169_get_settings,
1873         .set_settings           = rtl8169_set_settings,
1874         .get_msglevel           = rtl8169_get_msglevel,
1875         .set_msglevel           = rtl8169_set_msglevel,
1876         .get_regs               = rtl8169_get_regs,
1877         .get_wol                = rtl8169_get_wol,
1878         .set_wol                = rtl8169_set_wol,
1879         .get_strings            = rtl8169_get_strings,
1880         .get_sset_count         = rtl8169_get_sset_count,
1881         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1882         .get_ts_info            = ethtool_op_get_ts_info,
1883 };
1884
1885 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1886                                     struct net_device *dev, u8 default_version)
1887 {
1888         void __iomem *ioaddr = tp->mmio_addr;
1889         /*
1890          * The driver currently handles the 8168Bf and the 8168Be identically
1891          * but they can be identified more specifically through the test below
1892          * if needed:
1893          *
1894          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1895          *
1896          * Same thing for the 8101Eb and the 8101Ec:
1897          *
1898          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1899          */
1900         static const struct rtl_mac_info {
1901                 u32 mask;
1902                 u32 val;
1903                 int mac_version;
1904         } mac_info[] = {
1905                 /* 8168F family. */
1906                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
1907                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1908                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1909
1910                 /* 8168E family. */
1911                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1912                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1913                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1914                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1915
1916                 /* 8168D family. */
1917                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1918                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1919                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1920
1921                 /* 8168DP family. */
1922                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1923                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1924                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1925
1926                 /* 8168C family. */
1927                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1928                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1929                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1930                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1931                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1932                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1933                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1934                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1935                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1936
1937                 /* 8168B family. */
1938                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1939                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1940                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1941                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1942
1943                 /* 8101 family. */
1944                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
1945                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
1946                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
1947                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1948                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1949                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1950                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1951                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1952                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1953                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1954                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1955                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1956                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1957                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1958                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1959                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1960                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1961                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1962                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1963                 /* FIXME: where did these entries come from ? -- FR */
1964                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1965                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1966
1967                 /* 8110 family. */
1968                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1969                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1970                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1971                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1972                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1973                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1974
1975                 /* Catch-all */
1976                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1977         };
1978         const struct rtl_mac_info *p = mac_info;
1979         u32 reg;
1980
1981         reg = RTL_R32(TxConfig);
1982         while ((reg & p->mask) != p->val)
1983                 p++;
1984         tp->mac_version = p->mac_version;
1985
1986         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1987                 netif_notice(tp, probe, dev,
1988                              "unknown MAC, using family default\n");
1989                 tp->mac_version = default_version;
1990         }
1991 }
1992
1993 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1994 {
1995         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1996 }
1997
1998 struct phy_reg {
1999         u16 reg;
2000         u16 val;
2001 };
2002
2003 static void rtl_writephy_batch(struct rtl8169_private *tp,
2004                                const struct phy_reg *regs, int len)
2005 {
2006         while (len-- > 0) {
2007                 rtl_writephy(tp, regs->reg, regs->val);
2008                 regs++;
2009         }
2010 }
2011
2012 #define PHY_READ                0x00000000
2013 #define PHY_DATA_OR             0x10000000
2014 #define PHY_DATA_AND            0x20000000
2015 #define PHY_BJMPN               0x30000000
2016 #define PHY_READ_EFUSE          0x40000000
2017 #define PHY_READ_MAC_BYTE       0x50000000
2018 #define PHY_WRITE_MAC_BYTE      0x60000000
2019 #define PHY_CLEAR_READCOUNT     0x70000000
2020 #define PHY_WRITE               0x80000000
2021 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2022 #define PHY_COMP_EQ_SKIPN       0xa0000000
2023 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2024 #define PHY_WRITE_PREVIOUS      0xc0000000
2025 #define PHY_SKIPN               0xd0000000
2026 #define PHY_DELAY_MS            0xe0000000
2027 #define PHY_WRITE_ERI_WORD      0xf0000000
2028
2029 struct fw_info {
2030         u32     magic;
2031         char    version[RTL_VER_SIZE];
2032         __le32  fw_start;
2033         __le32  fw_len;
2034         u8      chksum;
2035 } __packed;
2036
2037 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2038
2039 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2040 {
2041         const struct firmware *fw = rtl_fw->fw;
2042         struct fw_info *fw_info = (struct fw_info *)fw->data;
2043         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2044         char *version = rtl_fw->version;
2045         bool rc = false;
2046
2047         if (fw->size < FW_OPCODE_SIZE)
2048                 goto out;
2049
2050         if (!fw_info->magic) {
2051                 size_t i, size, start;
2052                 u8 checksum = 0;
2053
2054                 if (fw->size < sizeof(*fw_info))
2055                         goto out;
2056
2057                 for (i = 0; i < fw->size; i++)
2058                         checksum += fw->data[i];
2059                 if (checksum != 0)
2060                         goto out;
2061
2062                 start = le32_to_cpu(fw_info->fw_start);
2063                 if (start > fw->size)
2064                         goto out;
2065
2066                 size = le32_to_cpu(fw_info->fw_len);
2067                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2068                         goto out;
2069
2070                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2071
2072                 pa->code = (__le32 *)(fw->data + start);
2073                 pa->size = size;
2074         } else {
2075                 if (fw->size % FW_OPCODE_SIZE)
2076                         goto out;
2077
2078                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2079
2080                 pa->code = (__le32 *)fw->data;
2081                 pa->size = fw->size / FW_OPCODE_SIZE;
2082         }
2083         version[RTL_VER_SIZE - 1] = 0;
2084
2085         rc = true;
2086 out:
2087         return rc;
2088 }
2089
2090 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2091                            struct rtl_fw_phy_action *pa)
2092 {
2093         bool rc = false;
2094         size_t index;
2095
2096         for (index = 0; index < pa->size; index++) {
2097                 u32 action = le32_to_cpu(pa->code[index]);
2098                 u32 regno = (action & 0x0fff0000) >> 16;
2099
2100                 switch(action & 0xf0000000) {
2101                 case PHY_READ:
2102                 case PHY_DATA_OR:
2103                 case PHY_DATA_AND:
2104                 case PHY_READ_EFUSE:
2105                 case PHY_CLEAR_READCOUNT:
2106                 case PHY_WRITE:
2107                 case PHY_WRITE_PREVIOUS:
2108                 case PHY_DELAY_MS:
2109                         break;
2110
2111                 case PHY_BJMPN:
2112                         if (regno > index) {
2113                                 netif_err(tp, ifup, tp->dev,
2114                                           "Out of range of firmware\n");
2115                                 goto out;
2116                         }
2117                         break;
2118                 case PHY_READCOUNT_EQ_SKIP:
2119                         if (index + 2 >= pa->size) {
2120                                 netif_err(tp, ifup, tp->dev,
2121                                           "Out of range of firmware\n");
2122                                 goto out;
2123                         }
2124                         break;
2125                 case PHY_COMP_EQ_SKIPN:
2126                 case PHY_COMP_NEQ_SKIPN:
2127                 case PHY_SKIPN:
2128                         if (index + 1 + regno >= pa->size) {
2129                                 netif_err(tp, ifup, tp->dev,
2130                                           "Out of range of firmware\n");
2131                                 goto out;
2132                         }
2133                         break;
2134
2135                 case PHY_READ_MAC_BYTE:
2136                 case PHY_WRITE_MAC_BYTE:
2137                 case PHY_WRITE_ERI_WORD:
2138                 default:
2139                         netif_err(tp, ifup, tp->dev,
2140                                   "Invalid action 0x%08x\n", action);
2141                         goto out;
2142                 }
2143         }
2144         rc = true;
2145 out:
2146         return rc;
2147 }
2148
2149 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2150 {
2151         struct net_device *dev = tp->dev;
2152         int rc = -EINVAL;
2153
2154         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2155                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2156                 goto out;
2157         }
2158
2159         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2160                 rc = 0;
2161 out:
2162         return rc;
2163 }
2164
2165 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2166 {
2167         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2168         u32 predata, count;
2169         size_t index;
2170
2171         predata = count = 0;
2172
2173         for (index = 0; index < pa->size; ) {
2174                 u32 action = le32_to_cpu(pa->code[index]);
2175                 u32 data = action & 0x0000ffff;
2176                 u32 regno = (action & 0x0fff0000) >> 16;
2177
2178                 if (!action)
2179                         break;
2180
2181                 switch(action & 0xf0000000) {
2182                 case PHY_READ:
2183                         predata = rtl_readphy(tp, regno);
2184                         count++;
2185                         index++;
2186                         break;
2187                 case PHY_DATA_OR:
2188                         predata |= data;
2189                         index++;
2190                         break;
2191                 case PHY_DATA_AND:
2192                         predata &= data;
2193                         index++;
2194                         break;
2195                 case PHY_BJMPN:
2196                         index -= regno;
2197                         break;
2198                 case PHY_READ_EFUSE:
2199                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2200                         index++;
2201                         break;
2202                 case PHY_CLEAR_READCOUNT:
2203                         count = 0;
2204                         index++;
2205                         break;
2206                 case PHY_WRITE:
2207                         rtl_writephy(tp, regno, data);
2208                         index++;
2209                         break;
2210                 case PHY_READCOUNT_EQ_SKIP:
2211                         index += (count == data) ? 2 : 1;
2212                         break;
2213                 case PHY_COMP_EQ_SKIPN:
2214                         if (predata == data)
2215                                 index += regno;
2216                         index++;
2217                         break;
2218                 case PHY_COMP_NEQ_SKIPN:
2219                         if (predata != data)
2220                                 index += regno;
2221                         index++;
2222                         break;
2223                 case PHY_WRITE_PREVIOUS:
2224                         rtl_writephy(tp, regno, predata);
2225                         index++;
2226                         break;
2227                 case PHY_SKIPN:
2228                         index += regno + 1;
2229                         break;
2230                 case PHY_DELAY_MS:
2231                         mdelay(data);
2232                         index++;
2233                         break;
2234
2235                 case PHY_READ_MAC_BYTE:
2236                 case PHY_WRITE_MAC_BYTE:
2237                 case PHY_WRITE_ERI_WORD:
2238                 default:
2239                         BUG();
2240                 }
2241         }
2242 }
2243
2244 static void rtl_release_firmware(struct rtl8169_private *tp)
2245 {
2246         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2247                 release_firmware(tp->rtl_fw->fw);
2248                 kfree(tp->rtl_fw);
2249         }
2250         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2251 }
2252
2253 static void rtl_apply_firmware(struct rtl8169_private *tp)
2254 {
2255         struct rtl_fw *rtl_fw = tp->rtl_fw;
2256
2257         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2258         if (!IS_ERR_OR_NULL(rtl_fw))
2259                 rtl_phy_write_fw(tp, rtl_fw);
2260 }
2261
2262 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2263 {
2264         if (rtl_readphy(tp, reg) != val)
2265                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2266         else
2267                 rtl_apply_firmware(tp);
2268 }
2269
2270 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2271 {
2272         static const struct phy_reg phy_reg_init[] = {
2273                 { 0x1f, 0x0001 },
2274                 { 0x06, 0x006e },
2275                 { 0x08, 0x0708 },
2276                 { 0x15, 0x4000 },
2277                 { 0x18, 0x65c7 },
2278
2279                 { 0x1f, 0x0001 },
2280                 { 0x03, 0x00a1 },
2281                 { 0x02, 0x0008 },
2282                 { 0x01, 0x0120 },
2283                 { 0x00, 0x1000 },
2284                 { 0x04, 0x0800 },
2285                 { 0x04, 0x0000 },
2286
2287                 { 0x03, 0xff41 },
2288                 { 0x02, 0xdf60 },
2289                 { 0x01, 0x0140 },
2290                 { 0x00, 0x0077 },
2291                 { 0x04, 0x7800 },
2292                 { 0x04, 0x7000 },
2293
2294                 { 0x03, 0x802f },
2295                 { 0x02, 0x4f02 },
2296                 { 0x01, 0x0409 },
2297                 { 0x00, 0xf0f9 },
2298                 { 0x04, 0x9800 },
2299                 { 0x04, 0x9000 },
2300
2301                 { 0x03, 0xdf01 },
2302                 { 0x02, 0xdf20 },
2303                 { 0x01, 0xff95 },
2304                 { 0x00, 0xba00 },
2305                 { 0x04, 0xa800 },
2306                 { 0x04, 0xa000 },
2307
2308                 { 0x03, 0xff41 },
2309                 { 0x02, 0xdf20 },
2310                 { 0x01, 0x0140 },
2311                 { 0x00, 0x00bb },
2312                 { 0x04, 0xb800 },
2313                 { 0x04, 0xb000 },
2314
2315                 { 0x03, 0xdf41 },
2316                 { 0x02, 0xdc60 },
2317                 { 0x01, 0x6340 },
2318                 { 0x00, 0x007d },
2319                 { 0x04, 0xd800 },
2320                 { 0x04, 0xd000 },
2321
2322                 { 0x03, 0xdf01 },
2323                 { 0x02, 0xdf20 },
2324                 { 0x01, 0x100a },
2325                 { 0x00, 0xa0ff },
2326                 { 0x04, 0xf800 },
2327                 { 0x04, 0xf000 },
2328
2329                 { 0x1f, 0x0000 },
2330                 { 0x0b, 0x0000 },
2331                 { 0x00, 0x9200 }
2332         };
2333
2334         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2335 }
2336
2337 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2338 {
2339         static const struct phy_reg phy_reg_init[] = {
2340                 { 0x1f, 0x0002 },
2341                 { 0x01, 0x90d0 },
2342                 { 0x1f, 0x0000 }
2343         };
2344
2345         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2346 }
2347
2348 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2349 {
2350         struct pci_dev *pdev = tp->pci_dev;
2351
2352         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2353             (pdev->subsystem_device != 0xe000))
2354                 return;
2355
2356         rtl_writephy(tp, 0x1f, 0x0001);
2357         rtl_writephy(tp, 0x10, 0xf01b);
2358         rtl_writephy(tp, 0x1f, 0x0000);
2359 }
2360
2361 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2362 {
2363         static const struct phy_reg phy_reg_init[] = {
2364                 { 0x1f, 0x0001 },
2365                 { 0x04, 0x0000 },
2366                 { 0x03, 0x00a1 },
2367                 { 0x02, 0x0008 },
2368                 { 0x01, 0x0120 },
2369                 { 0x00, 0x1000 },
2370                 { 0x04, 0x0800 },
2371                 { 0x04, 0x9000 },
2372                 { 0x03, 0x802f },
2373                 { 0x02, 0x4f02 },
2374                 { 0x01, 0x0409 },
2375                 { 0x00, 0xf099 },
2376                 { 0x04, 0x9800 },
2377                 { 0x04, 0xa000 },
2378                 { 0x03, 0xdf01 },
2379                 { 0x02, 0xdf20 },
2380                 { 0x01, 0xff95 },
2381                 { 0x00, 0xba00 },
2382                 { 0x04, 0xa800 },
2383                 { 0x04, 0xf000 },
2384                 { 0x03, 0xdf01 },
2385                 { 0x02, 0xdf20 },
2386                 { 0x01, 0x101a },
2387                 { 0x00, 0xa0ff },
2388                 { 0x04, 0xf800 },
2389                 { 0x04, 0x0000 },
2390                 { 0x1f, 0x0000 },
2391
2392                 { 0x1f, 0x0001 },
2393                 { 0x10, 0xf41b },
2394                 { 0x14, 0xfb54 },
2395                 { 0x18, 0xf5c7 },
2396                 { 0x1f, 0x0000 },
2397
2398                 { 0x1f, 0x0001 },
2399                 { 0x17, 0x0cc0 },
2400                 { 0x1f, 0x0000 }
2401         };
2402
2403         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2404
2405         rtl8169scd_hw_phy_config_quirk(tp);
2406 }
2407
2408 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2409 {
2410         static const struct phy_reg phy_reg_init[] = {
2411                 { 0x1f, 0x0001 },
2412                 { 0x04, 0x0000 },
2413                 { 0x03, 0x00a1 },
2414                 { 0x02, 0x0008 },
2415                 { 0x01, 0x0120 },
2416                 { 0x00, 0x1000 },
2417                 { 0x04, 0x0800 },
2418                 { 0x04, 0x9000 },
2419                 { 0x03, 0x802f },
2420                 { 0x02, 0x4f02 },
2421                 { 0x01, 0x0409 },
2422                 { 0x00, 0xf099 },
2423                 { 0x04, 0x9800 },
2424                 { 0x04, 0xa000 },
2425                 { 0x03, 0xdf01 },
2426                 { 0x02, 0xdf20 },
2427                 { 0x01, 0xff95 },
2428                 { 0x00, 0xba00 },
2429                 { 0x04, 0xa800 },
2430                 { 0x04, 0xf000 },
2431                 { 0x03, 0xdf01 },
2432                 { 0x02, 0xdf20 },
2433                 { 0x01, 0x101a },
2434                 { 0x00, 0xa0ff },
2435                 { 0x04, 0xf800 },
2436                 { 0x04, 0x0000 },
2437                 { 0x1f, 0x0000 },
2438
2439                 { 0x1f, 0x0001 },
2440                 { 0x0b, 0x8480 },
2441                 { 0x1f, 0x0000 },
2442
2443                 { 0x1f, 0x0001 },
2444                 { 0x18, 0x67c7 },
2445                 { 0x04, 0x2000 },
2446                 { 0x03, 0x002f },
2447                 { 0x02, 0x4360 },
2448                 { 0x01, 0x0109 },
2449                 { 0x00, 0x3022 },
2450                 { 0x04, 0x2800 },
2451                 { 0x1f, 0x0000 },
2452
2453                 { 0x1f, 0x0001 },
2454                 { 0x17, 0x0cc0 },
2455                 { 0x1f, 0x0000 }
2456         };
2457
2458         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2459 }
2460
2461 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2462 {
2463         static const struct phy_reg phy_reg_init[] = {
2464                 { 0x10, 0xf41b },
2465                 { 0x1f, 0x0000 }
2466         };
2467
2468         rtl_writephy(tp, 0x1f, 0x0001);
2469         rtl_patchphy(tp, 0x16, 1 << 0);
2470
2471         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2472 }
2473
2474 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2475 {
2476         static const struct phy_reg phy_reg_init[] = {
2477                 { 0x1f, 0x0001 },
2478                 { 0x10, 0xf41b },
2479                 { 0x1f, 0x0000 }
2480         };
2481
2482         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2483 }
2484
2485 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2486 {
2487         static const struct phy_reg phy_reg_init[] = {
2488                 { 0x1f, 0x0000 },
2489                 { 0x1d, 0x0f00 },
2490                 { 0x1f, 0x0002 },
2491                 { 0x0c, 0x1ec8 },
2492                 { 0x1f, 0x0000 }
2493         };
2494
2495         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2496 }
2497
2498 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2499 {
2500         static const struct phy_reg phy_reg_init[] = {
2501                 { 0x1f, 0x0001 },
2502                 { 0x1d, 0x3d98 },
2503                 { 0x1f, 0x0000 }
2504         };
2505
2506         rtl_writephy(tp, 0x1f, 0x0000);
2507         rtl_patchphy(tp, 0x14, 1 << 5);
2508         rtl_patchphy(tp, 0x0d, 1 << 5);
2509
2510         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2511 }
2512
2513 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2514 {
2515         static const struct phy_reg phy_reg_init[] = {
2516                 { 0x1f, 0x0001 },
2517                 { 0x12, 0x2300 },
2518                 { 0x1f, 0x0002 },
2519                 { 0x00, 0x88d4 },
2520                 { 0x01, 0x82b1 },
2521                 { 0x03, 0x7002 },
2522                 { 0x08, 0x9e30 },
2523                 { 0x09, 0x01f0 },
2524                 { 0x0a, 0x5500 },
2525                 { 0x0c, 0x00c8 },
2526                 { 0x1f, 0x0003 },
2527                 { 0x12, 0xc096 },
2528                 { 0x16, 0x000a },
2529                 { 0x1f, 0x0000 },
2530                 { 0x1f, 0x0000 },
2531                 { 0x09, 0x2000 },
2532                 { 0x09, 0x0000 }
2533         };
2534
2535         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2536
2537         rtl_patchphy(tp, 0x14, 1 << 5);
2538         rtl_patchphy(tp, 0x0d, 1 << 5);
2539         rtl_writephy(tp, 0x1f, 0x0000);
2540 }
2541
2542 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2543 {
2544         static const struct phy_reg phy_reg_init[] = {
2545                 { 0x1f, 0x0001 },
2546                 { 0x12, 0x2300 },
2547                 { 0x03, 0x802f },
2548                 { 0x02, 0x4f02 },
2549                 { 0x01, 0x0409 },
2550                 { 0x00, 0xf099 },
2551                 { 0x04, 0x9800 },
2552                 { 0x04, 0x9000 },
2553                 { 0x1d, 0x3d98 },
2554                 { 0x1f, 0x0002 },
2555                 { 0x0c, 0x7eb8 },
2556                 { 0x06, 0x0761 },
2557                 { 0x1f, 0x0003 },
2558                 { 0x16, 0x0f0a },
2559                 { 0x1f, 0x0000 }
2560         };
2561
2562         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2563
2564         rtl_patchphy(tp, 0x16, 1 << 0);
2565         rtl_patchphy(tp, 0x14, 1 << 5);
2566         rtl_patchphy(tp, 0x0d, 1 << 5);
2567         rtl_writephy(tp, 0x1f, 0x0000);
2568 }
2569
2570 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2571 {
2572         static const struct phy_reg phy_reg_init[] = {
2573                 { 0x1f, 0x0001 },
2574                 { 0x12, 0x2300 },
2575                 { 0x1d, 0x3d98 },
2576                 { 0x1f, 0x0002 },
2577                 { 0x0c, 0x7eb8 },
2578                 { 0x06, 0x5461 },
2579                 { 0x1f, 0x0003 },
2580                 { 0x16, 0x0f0a },
2581                 { 0x1f, 0x0000 }
2582         };
2583
2584         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2585
2586         rtl_patchphy(tp, 0x16, 1 << 0);
2587         rtl_patchphy(tp, 0x14, 1 << 5);
2588         rtl_patchphy(tp, 0x0d, 1 << 5);
2589         rtl_writephy(tp, 0x1f, 0x0000);
2590 }
2591
2592 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2593 {
2594         rtl8168c_3_hw_phy_config(tp);
2595 }
2596
2597 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2598 {
2599         static const struct phy_reg phy_reg_init_0[] = {
2600                 /* Channel Estimation */
2601                 { 0x1f, 0x0001 },
2602                 { 0x06, 0x4064 },
2603                 { 0x07, 0x2863 },
2604                 { 0x08, 0x059c },
2605                 { 0x09, 0x26b4 },
2606                 { 0x0a, 0x6a19 },
2607                 { 0x0b, 0xdcc8 },
2608                 { 0x10, 0xf06d },
2609                 { 0x14, 0x7f68 },
2610                 { 0x18, 0x7fd9 },
2611                 { 0x1c, 0xf0ff },
2612                 { 0x1d, 0x3d9c },
2613                 { 0x1f, 0x0003 },
2614                 { 0x12, 0xf49f },
2615                 { 0x13, 0x070b },
2616                 { 0x1a, 0x05ad },
2617                 { 0x14, 0x94c0 },
2618
2619                 /*
2620                  * Tx Error Issue
2621                  * Enhance line driver power
2622                  */
2623                 { 0x1f, 0x0002 },
2624                 { 0x06, 0x5561 },
2625                 { 0x1f, 0x0005 },
2626                 { 0x05, 0x8332 },
2627                 { 0x06, 0x5561 },
2628
2629                 /*
2630                  * Can not link to 1Gbps with bad cable
2631                  * Decrease SNR threshold form 21.07dB to 19.04dB
2632                  */
2633                 { 0x1f, 0x0001 },
2634                 { 0x17, 0x0cc0 },
2635
2636                 { 0x1f, 0x0000 },
2637                 { 0x0d, 0xf880 }
2638         };
2639         void __iomem *ioaddr = tp->mmio_addr;
2640
2641         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2642
2643         /*
2644          * Rx Error Issue
2645          * Fine Tune Switching regulator parameter
2646          */
2647         rtl_writephy(tp, 0x1f, 0x0002);
2648         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2649         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2650
2651         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2652                 static const struct phy_reg phy_reg_init[] = {
2653                         { 0x1f, 0x0002 },
2654                         { 0x05, 0x669a },
2655                         { 0x1f, 0x0005 },
2656                         { 0x05, 0x8330 },
2657                         { 0x06, 0x669a },
2658                         { 0x1f, 0x0002 }
2659                 };
2660                 int val;
2661
2662                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2663
2664                 val = rtl_readphy(tp, 0x0d);
2665
2666                 if ((val & 0x00ff) != 0x006c) {
2667                         static const u32 set[] = {
2668                                 0x0065, 0x0066, 0x0067, 0x0068,
2669                                 0x0069, 0x006a, 0x006b, 0x006c
2670                         };
2671                         int i;
2672
2673                         rtl_writephy(tp, 0x1f, 0x0002);
2674
2675                         val &= 0xff00;
2676                         for (i = 0; i < ARRAY_SIZE(set); i++)
2677                                 rtl_writephy(tp, 0x0d, val | set[i]);
2678                 }
2679         } else {
2680                 static const struct phy_reg phy_reg_init[] = {
2681                         { 0x1f, 0x0002 },
2682                         { 0x05, 0x6662 },
2683                         { 0x1f, 0x0005 },
2684                         { 0x05, 0x8330 },
2685                         { 0x06, 0x6662 }
2686                 };
2687
2688                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2689         }
2690
2691         /* RSET couple improve */
2692         rtl_writephy(tp, 0x1f, 0x0002);
2693         rtl_patchphy(tp, 0x0d, 0x0300);
2694         rtl_patchphy(tp, 0x0f, 0x0010);
2695
2696         /* Fine tune PLL performance */
2697         rtl_writephy(tp, 0x1f, 0x0002);
2698         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2699         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2700
2701         rtl_writephy(tp, 0x1f, 0x0005);
2702         rtl_writephy(tp, 0x05, 0x001b);
2703
2704         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2705
2706         rtl_writephy(tp, 0x1f, 0x0000);
2707 }
2708
2709 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2710 {
2711         static const struct phy_reg phy_reg_init_0[] = {
2712                 /* Channel Estimation */
2713                 { 0x1f, 0x0001 },
2714                 { 0x06, 0x4064 },
2715                 { 0x07, 0x2863 },
2716                 { 0x08, 0x059c },
2717                 { 0x09, 0x26b4 },
2718                 { 0x0a, 0x6a19 },
2719                 { 0x0b, 0xdcc8 },
2720                 { 0x10, 0xf06d },
2721                 { 0x14, 0x7f68 },
2722                 { 0x18, 0x7fd9 },
2723                 { 0x1c, 0xf0ff },
2724                 { 0x1d, 0x3d9c },
2725                 { 0x1f, 0x0003 },
2726                 { 0x12, 0xf49f },
2727                 { 0x13, 0x070b },
2728                 { 0x1a, 0x05ad },
2729                 { 0x14, 0x94c0 },
2730
2731                 /*
2732                  * Tx Error Issue
2733                  * Enhance line driver power
2734                  */
2735                 { 0x1f, 0x0002 },
2736                 { 0x06, 0x5561 },
2737                 { 0x1f, 0x0005 },
2738                 { 0x05, 0x8332 },
2739                 { 0x06, 0x5561 },
2740
2741                 /*
2742                  * Can not link to 1Gbps with bad cable
2743                  * Decrease SNR threshold form 21.07dB to 19.04dB
2744                  */
2745                 { 0x1f, 0x0001 },
2746                 { 0x17, 0x0cc0 },
2747
2748                 { 0x1f, 0x0000 },
2749                 { 0x0d, 0xf880 }
2750         };
2751         void __iomem *ioaddr = tp->mmio_addr;
2752
2753         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2754
2755         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2756                 static const struct phy_reg phy_reg_init[] = {
2757                         { 0x1f, 0x0002 },
2758                         { 0x05, 0x669a },
2759                         { 0x1f, 0x0005 },
2760                         { 0x05, 0x8330 },
2761                         { 0x06, 0x669a },
2762
2763                         { 0x1f, 0x0002 }
2764                 };
2765                 int val;
2766
2767                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2768
2769                 val = rtl_readphy(tp, 0x0d);
2770                 if ((val & 0x00ff) != 0x006c) {
2771                         static const u32 set[] = {
2772                                 0x0065, 0x0066, 0x0067, 0x0068,
2773                                 0x0069, 0x006a, 0x006b, 0x006c
2774                         };
2775                         int i;
2776
2777                         rtl_writephy(tp, 0x1f, 0x0002);
2778
2779                         val &= 0xff00;
2780                         for (i = 0; i < ARRAY_SIZE(set); i++)
2781                                 rtl_writephy(tp, 0x0d, val | set[i]);
2782                 }
2783         } else {
2784                 static const struct phy_reg phy_reg_init[] = {
2785                         { 0x1f, 0x0002 },
2786                         { 0x05, 0x2642 },
2787                         { 0x1f, 0x0005 },
2788                         { 0x05, 0x8330 },
2789                         { 0x06, 0x2642 }
2790                 };
2791
2792                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2793         }
2794
2795         /* Fine tune PLL performance */
2796         rtl_writephy(tp, 0x1f, 0x0002);
2797         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2798         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2799
2800         /* Switching regulator Slew rate */
2801         rtl_writephy(tp, 0x1f, 0x0002);
2802         rtl_patchphy(tp, 0x0f, 0x0017);
2803
2804         rtl_writephy(tp, 0x1f, 0x0005);
2805         rtl_writephy(tp, 0x05, 0x001b);
2806
2807         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2808
2809         rtl_writephy(tp, 0x1f, 0x0000);
2810 }
2811
2812 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2813 {
2814         static const struct phy_reg phy_reg_init[] = {
2815                 { 0x1f, 0x0002 },
2816                 { 0x10, 0x0008 },
2817                 { 0x0d, 0x006c },
2818
2819                 { 0x1f, 0x0000 },
2820                 { 0x0d, 0xf880 },
2821
2822                 { 0x1f, 0x0001 },
2823                 { 0x17, 0x0cc0 },
2824
2825                 { 0x1f, 0x0001 },
2826                 { 0x0b, 0xa4d8 },
2827                 { 0x09, 0x281c },
2828                 { 0x07, 0x2883 },
2829                 { 0x0a, 0x6b35 },
2830                 { 0x1d, 0x3da4 },
2831                 { 0x1c, 0xeffd },
2832                 { 0x14, 0x7f52 },
2833                 { 0x18, 0x7fc6 },
2834                 { 0x08, 0x0601 },
2835                 { 0x06, 0x4063 },
2836                 { 0x10, 0xf074 },
2837                 { 0x1f, 0x0003 },
2838                 { 0x13, 0x0789 },
2839                 { 0x12, 0xf4bd },
2840                 { 0x1a, 0x04fd },
2841                 { 0x14, 0x84b0 },
2842                 { 0x1f, 0x0000 },
2843                 { 0x00, 0x9200 },
2844
2845                 { 0x1f, 0x0005 },
2846                 { 0x01, 0x0340 },
2847                 { 0x1f, 0x0001 },
2848                 { 0x04, 0x4000 },
2849                 { 0x03, 0x1d21 },
2850                 { 0x02, 0x0c32 },
2851                 { 0x01, 0x0200 },
2852                 { 0x00, 0x5554 },
2853                 { 0x04, 0x4800 },
2854                 { 0x04, 0x4000 },
2855                 { 0x04, 0xf000 },
2856                 { 0x03, 0xdf01 },
2857                 { 0x02, 0xdf20 },
2858                 { 0x01, 0x101a },
2859                 { 0x00, 0xa0ff },
2860                 { 0x04, 0xf800 },
2861                 { 0x04, 0xf000 },
2862                 { 0x1f, 0x0000 },
2863
2864                 { 0x1f, 0x0007 },
2865                 { 0x1e, 0x0023 },
2866                 { 0x16, 0x0000 },
2867                 { 0x1f, 0x0000 }
2868         };
2869
2870         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2871 }
2872
2873 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2874 {
2875         static const struct phy_reg phy_reg_init[] = {
2876                 { 0x1f, 0x0001 },
2877                 { 0x17, 0x0cc0 },
2878
2879                 { 0x1f, 0x0007 },
2880                 { 0x1e, 0x002d },
2881                 { 0x18, 0x0040 },
2882                 { 0x1f, 0x0000 }
2883         };
2884
2885         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2886         rtl_patchphy(tp, 0x0d, 1 << 5);
2887 }
2888
2889 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2890 {
2891         static const struct phy_reg phy_reg_init[] = {
2892                 /* Enable Delay cap */
2893                 { 0x1f, 0x0005 },
2894                 { 0x05, 0x8b80 },
2895                 { 0x06, 0xc896 },
2896                 { 0x1f, 0x0000 },
2897
2898                 /* Channel estimation fine tune */
2899                 { 0x1f, 0x0001 },
2900                 { 0x0b, 0x6c20 },
2901                 { 0x07, 0x2872 },
2902                 { 0x1c, 0xefff },
2903                 { 0x1f, 0x0003 },
2904                 { 0x14, 0x6420 },
2905                 { 0x1f, 0x0000 },
2906
2907                 /* Update PFM & 10M TX idle timer */
2908                 { 0x1f, 0x0007 },
2909                 { 0x1e, 0x002f },
2910                 { 0x15, 0x1919 },
2911                 { 0x1f, 0x0000 },
2912
2913                 { 0x1f, 0x0007 },
2914                 { 0x1e, 0x00ac },
2915                 { 0x18, 0x0006 },
2916                 { 0x1f, 0x0000 }
2917         };
2918
2919         rtl_apply_firmware(tp);
2920
2921         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2922
2923         /* DCO enable for 10M IDLE Power */
2924         rtl_writephy(tp, 0x1f, 0x0007);
2925         rtl_writephy(tp, 0x1e, 0x0023);
2926         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2927         rtl_writephy(tp, 0x1f, 0x0000);
2928
2929         /* For impedance matching */
2930         rtl_writephy(tp, 0x1f, 0x0002);
2931         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2932         rtl_writephy(tp, 0x1f, 0x0000);
2933
2934         /* PHY auto speed down */
2935         rtl_writephy(tp, 0x1f, 0x0007);
2936         rtl_writephy(tp, 0x1e, 0x002d);
2937         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2938         rtl_writephy(tp, 0x1f, 0x0000);
2939         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2940
2941         rtl_writephy(tp, 0x1f, 0x0005);
2942         rtl_writephy(tp, 0x05, 0x8b86);
2943         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2944         rtl_writephy(tp, 0x1f, 0x0000);
2945
2946         rtl_writephy(tp, 0x1f, 0x0005);
2947         rtl_writephy(tp, 0x05, 0x8b85);
2948         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2949         rtl_writephy(tp, 0x1f, 0x0007);
2950         rtl_writephy(tp, 0x1e, 0x0020);
2951         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2952         rtl_writephy(tp, 0x1f, 0x0006);
2953         rtl_writephy(tp, 0x00, 0x5a00);
2954         rtl_writephy(tp, 0x1f, 0x0000);
2955         rtl_writephy(tp, 0x0d, 0x0007);
2956         rtl_writephy(tp, 0x0e, 0x003c);
2957         rtl_writephy(tp, 0x0d, 0x4007);
2958         rtl_writephy(tp, 0x0e, 0x0000);
2959         rtl_writephy(tp, 0x0d, 0x0000);
2960 }
2961
2962 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2963 {
2964         static const struct phy_reg phy_reg_init[] = {
2965                 /* Enable Delay cap */
2966                 { 0x1f, 0x0004 },
2967                 { 0x1f, 0x0007 },
2968                 { 0x1e, 0x00ac },
2969                 { 0x18, 0x0006 },
2970                 { 0x1f, 0x0002 },
2971                 { 0x1f, 0x0000 },
2972                 { 0x1f, 0x0000 },
2973
2974                 /* Channel estimation fine tune */
2975                 { 0x1f, 0x0003 },
2976                 { 0x09, 0xa20f },
2977                 { 0x1f, 0x0000 },
2978                 { 0x1f, 0x0000 },
2979
2980                 /* Green Setting */
2981                 { 0x1f, 0x0005 },
2982                 { 0x05, 0x8b5b },
2983                 { 0x06, 0x9222 },
2984                 { 0x05, 0x8b6d },
2985                 { 0x06, 0x8000 },
2986                 { 0x05, 0x8b76 },
2987                 { 0x06, 0x8000 },
2988                 { 0x1f, 0x0000 }
2989         };
2990
2991         rtl_apply_firmware(tp);
2992
2993         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2994
2995         /* For 4-corner performance improve */
2996         rtl_writephy(tp, 0x1f, 0x0005);
2997         rtl_writephy(tp, 0x05, 0x8b80);
2998         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2999         rtl_writephy(tp, 0x1f, 0x0000);
3000
3001         /* PHY auto speed down */
3002         rtl_writephy(tp, 0x1f, 0x0004);
3003         rtl_writephy(tp, 0x1f, 0x0007);
3004         rtl_writephy(tp, 0x1e, 0x002d);
3005         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3006         rtl_writephy(tp, 0x1f, 0x0002);
3007         rtl_writephy(tp, 0x1f, 0x0000);
3008         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3009
3010         /* improve 10M EEE waveform */
3011         rtl_writephy(tp, 0x1f, 0x0005);
3012         rtl_writephy(tp, 0x05, 0x8b86);
3013         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3014         rtl_writephy(tp, 0x1f, 0x0000);
3015
3016         /* Improve 2-pair detection performance */
3017         rtl_writephy(tp, 0x1f, 0x0005);
3018         rtl_writephy(tp, 0x05, 0x8b85);
3019         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3020         rtl_writephy(tp, 0x1f, 0x0000);
3021
3022         /* EEE setting */
3023         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3024                      ERIAR_EXGMAC);
3025         rtl_writephy(tp, 0x1f, 0x0005);
3026         rtl_writephy(tp, 0x05, 0x8b85);
3027         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3028         rtl_writephy(tp, 0x1f, 0x0004);
3029         rtl_writephy(tp, 0x1f, 0x0007);
3030         rtl_writephy(tp, 0x1e, 0x0020);
3031         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3032         rtl_writephy(tp, 0x1f, 0x0002);
3033         rtl_writephy(tp, 0x1f, 0x0000);
3034         rtl_writephy(tp, 0x0d, 0x0007);
3035         rtl_writephy(tp, 0x0e, 0x003c);
3036         rtl_writephy(tp, 0x0d, 0x4007);
3037         rtl_writephy(tp, 0x0e, 0x0000);
3038         rtl_writephy(tp, 0x0d, 0x0000);
3039
3040         /* Green feature */
3041         rtl_writephy(tp, 0x1f, 0x0003);
3042         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3043         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3044         rtl_writephy(tp, 0x1f, 0x0000);
3045 }
3046
3047 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3048 {
3049         /* For 4-corner performance improve */
3050         rtl_writephy(tp, 0x1f, 0x0005);
3051         rtl_writephy(tp, 0x05, 0x8b80);
3052         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3053         rtl_writephy(tp, 0x1f, 0x0000);
3054
3055         /* PHY auto speed down */
3056         rtl_writephy(tp, 0x1f, 0x0007);
3057         rtl_writephy(tp, 0x1e, 0x002d);
3058         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3059         rtl_writephy(tp, 0x1f, 0x0000);
3060         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3061
3062         /* Improve 10M EEE waveform */
3063         rtl_writephy(tp, 0x1f, 0x0005);
3064         rtl_writephy(tp, 0x05, 0x8b86);
3065         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3066         rtl_writephy(tp, 0x1f, 0x0000);
3067 }
3068
3069 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3070 {
3071         static const struct phy_reg phy_reg_init[] = {
3072                 /* Channel estimation fine tune */
3073                 { 0x1f, 0x0003 },
3074                 { 0x09, 0xa20f },
3075                 { 0x1f, 0x0000 },
3076
3077                 /* Modify green table for giga & fnet */
3078                 { 0x1f, 0x0005 },
3079                 { 0x05, 0x8b55 },
3080                 { 0x06, 0x0000 },
3081                 { 0x05, 0x8b5e },
3082                 { 0x06, 0x0000 },
3083                 { 0x05, 0x8b67 },
3084                 { 0x06, 0x0000 },
3085                 { 0x05, 0x8b70 },
3086                 { 0x06, 0x0000 },
3087                 { 0x1f, 0x0000 },
3088                 { 0x1f, 0x0007 },
3089                 { 0x1e, 0x0078 },
3090                 { 0x17, 0x0000 },
3091                 { 0x19, 0x00fb },
3092                 { 0x1f, 0x0000 },
3093
3094                 /* Modify green table for 10M */
3095                 { 0x1f, 0x0005 },
3096                 { 0x05, 0x8b79 },
3097                 { 0x06, 0xaa00 },
3098                 { 0x1f, 0x0000 },
3099
3100                 /* Disable hiimpedance detection (RTCT) */
3101                 { 0x1f, 0x0003 },
3102                 { 0x01, 0x328a },
3103                 { 0x1f, 0x0000 }
3104         };
3105
3106         rtl_apply_firmware(tp);
3107
3108         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109
3110         rtl8168f_hw_phy_config(tp);
3111
3112         /* Improve 2-pair detection performance */
3113         rtl_writephy(tp, 0x1f, 0x0005);
3114         rtl_writephy(tp, 0x05, 0x8b85);
3115         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3116         rtl_writephy(tp, 0x1f, 0x0000);
3117 }
3118
3119 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3120 {
3121         rtl_apply_firmware(tp);
3122
3123         rtl8168f_hw_phy_config(tp);
3124 }
3125
3126 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3127 {
3128         void __iomem *ioaddr = tp->mmio_addr;
3129         static const struct phy_reg phy_reg_init[] = {
3130                 /* Channel estimation fine tune */
3131                 { 0x1f, 0x0003 },
3132                 { 0x09, 0xa20f },
3133                 { 0x1f, 0x0000 },
3134
3135                 /* Modify green table for giga & fnet */
3136                 { 0x1f, 0x0005 },
3137                 { 0x05, 0x8b55 },
3138                 { 0x06, 0x0000 },
3139                 { 0x05, 0x8b5e },
3140                 { 0x06, 0x0000 },
3141                 { 0x05, 0x8b67 },
3142                 { 0x06, 0x0000 },
3143                 { 0x05, 0x8b70 },
3144                 { 0x06, 0x0000 },
3145                 { 0x1f, 0x0000 },
3146                 { 0x1f, 0x0007 },
3147                 { 0x1e, 0x0078 },
3148                 { 0x17, 0x0000 },
3149                 { 0x19, 0x00aa },
3150                 { 0x1f, 0x0000 },
3151
3152                 /* Modify green table for 10M */
3153                 { 0x1f, 0x0005 },
3154                 { 0x05, 0x8b79 },
3155                 { 0x06, 0xaa00 },
3156                 { 0x1f, 0x0000 },
3157
3158                 /* Disable hiimpedance detection (RTCT) */
3159                 { 0x1f, 0x0003 },
3160                 { 0x01, 0x328a },
3161                 { 0x1f, 0x0000 }
3162         };
3163
3164
3165         rtl_apply_firmware(tp);
3166
3167         rtl8168f_hw_phy_config(tp);
3168
3169         /* Improve 2-pair detection performance */
3170         rtl_writephy(tp, 0x1f, 0x0005);
3171         rtl_writephy(tp, 0x05, 0x8b85);
3172         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3173         rtl_writephy(tp, 0x1f, 0x0000);
3174
3175         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3176
3177         /* Modify green table for giga */
3178         rtl_writephy(tp, 0x1f, 0x0005);
3179         rtl_writephy(tp, 0x05, 0x8b54);
3180         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3181         rtl_writephy(tp, 0x05, 0x8b5d);
3182         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3183         rtl_writephy(tp, 0x05, 0x8a7c);
3184         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3185         rtl_writephy(tp, 0x05, 0x8a7f);
3186         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3187         rtl_writephy(tp, 0x05, 0x8a82);
3188         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3189         rtl_writephy(tp, 0x05, 0x8a85);
3190         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3191         rtl_writephy(tp, 0x05, 0x8a88);
3192         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3193         rtl_writephy(tp, 0x1f, 0x0000);
3194
3195         /* uc same-seed solution */
3196         rtl_writephy(tp, 0x1f, 0x0005);
3197         rtl_writephy(tp, 0x05, 0x8b85);
3198         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3199         rtl_writephy(tp, 0x1f, 0x0000);
3200
3201         /* eee setting */
3202         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3203         rtl_writephy(tp, 0x1f, 0x0005);
3204         rtl_writephy(tp, 0x05, 0x8b85);
3205         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3206         rtl_writephy(tp, 0x1f, 0x0004);
3207         rtl_writephy(tp, 0x1f, 0x0007);
3208         rtl_writephy(tp, 0x1e, 0x0020);
3209         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3210         rtl_writephy(tp, 0x1f, 0x0000);
3211         rtl_writephy(tp, 0x0d, 0x0007);
3212         rtl_writephy(tp, 0x0e, 0x003c);
3213         rtl_writephy(tp, 0x0d, 0x4007);
3214         rtl_writephy(tp, 0x0e, 0x0000);
3215         rtl_writephy(tp, 0x0d, 0x0000);
3216
3217         /* Green feature */
3218         rtl_writephy(tp, 0x1f, 0x0003);
3219         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3220         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3221         rtl_writephy(tp, 0x1f, 0x0000);
3222 }
3223
3224 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3225 {
3226         static const struct phy_reg phy_reg_init[] = {
3227                 { 0x1f, 0x0003 },
3228                 { 0x08, 0x441d },
3229                 { 0x01, 0x9100 },
3230                 { 0x1f, 0x0000 }
3231         };
3232
3233         rtl_writephy(tp, 0x1f, 0x0000);
3234         rtl_patchphy(tp, 0x11, 1 << 12);
3235         rtl_patchphy(tp, 0x19, 1 << 13);
3236         rtl_patchphy(tp, 0x10, 1 << 15);
3237
3238         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3239 }
3240
3241 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3242 {
3243         static const struct phy_reg phy_reg_init[] = {
3244                 { 0x1f, 0x0005 },
3245                 { 0x1a, 0x0000 },
3246                 { 0x1f, 0x0000 },
3247
3248                 { 0x1f, 0x0004 },
3249                 { 0x1c, 0x0000 },
3250                 { 0x1f, 0x0000 },
3251
3252                 { 0x1f, 0x0001 },
3253                 { 0x15, 0x7701 },
3254                 { 0x1f, 0x0000 }
3255         };
3256
3257         /* Disable ALDPS before ram code */
3258         rtl_writephy(tp, 0x1f, 0x0000);
3259         rtl_writephy(tp, 0x18, 0x0310);
3260         msleep(100);
3261
3262         rtl_apply_firmware(tp);
3263
3264         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3265 }
3266
3267 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3268 {
3269         void __iomem *ioaddr = tp->mmio_addr;
3270
3271         /* Disable ALDPS before setting firmware */
3272         rtl_writephy(tp, 0x1f, 0x0000);
3273         rtl_writephy(tp, 0x18, 0x0310);
3274         msleep(20);
3275
3276         rtl_apply_firmware(tp);
3277
3278         /* EEE setting */
3279         rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3280         rtl_writephy(tp, 0x1f, 0x0004);
3281         rtl_writephy(tp, 0x10, 0x401f);
3282         rtl_writephy(tp, 0x19, 0x7030);
3283         rtl_writephy(tp, 0x1f, 0x0000);
3284 }
3285
3286 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3287 {
3288         void __iomem *ioaddr = tp->mmio_addr;
3289
3290         static const struct phy_reg phy_reg_init[] = {
3291                 { 0x1f, 0x0004 },
3292                 { 0x10, 0xc07f },
3293                 { 0x19, 0x7030 },
3294                 { 0x1f, 0x0000 }
3295         };
3296
3297         /* Disable ALDPS before ram code */
3298         rtl_writephy(tp, 0x1f, 0x0000);
3299         rtl_writephy(tp, 0x18, 0x0310);
3300         msleep(100);
3301
3302         rtl_apply_firmware(tp);
3303
3304         rtl_eri_write(ioaddr, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3305         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3306
3307         rtl_eri_write(ioaddr, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3308 }
3309
3310 static void rtl_hw_phy_config(struct net_device *dev)
3311 {
3312         struct rtl8169_private *tp = netdev_priv(dev);
3313
3314         rtl8169_print_mac_version(tp);
3315
3316         switch (tp->mac_version) {
3317         case RTL_GIGA_MAC_VER_01:
3318                 break;
3319         case RTL_GIGA_MAC_VER_02:
3320         case RTL_GIGA_MAC_VER_03:
3321                 rtl8169s_hw_phy_config(tp);
3322                 break;
3323         case RTL_GIGA_MAC_VER_04:
3324                 rtl8169sb_hw_phy_config(tp);
3325                 break;
3326         case RTL_GIGA_MAC_VER_05:
3327                 rtl8169scd_hw_phy_config(tp);
3328                 break;
3329         case RTL_GIGA_MAC_VER_06:
3330                 rtl8169sce_hw_phy_config(tp);
3331                 break;
3332         case RTL_GIGA_MAC_VER_07:
3333         case RTL_GIGA_MAC_VER_08:
3334         case RTL_GIGA_MAC_VER_09:
3335                 rtl8102e_hw_phy_config(tp);
3336                 break;
3337         case RTL_GIGA_MAC_VER_11:
3338                 rtl8168bb_hw_phy_config(tp);
3339                 break;
3340         case RTL_GIGA_MAC_VER_12:
3341                 rtl8168bef_hw_phy_config(tp);
3342                 break;
3343         case RTL_GIGA_MAC_VER_17:
3344                 rtl8168bef_hw_phy_config(tp);
3345                 break;
3346         case RTL_GIGA_MAC_VER_18:
3347                 rtl8168cp_1_hw_phy_config(tp);
3348                 break;
3349         case RTL_GIGA_MAC_VER_19:
3350                 rtl8168c_1_hw_phy_config(tp);
3351                 break;
3352         case RTL_GIGA_MAC_VER_20:
3353                 rtl8168c_2_hw_phy_config(tp);
3354                 break;
3355         case RTL_GIGA_MAC_VER_21:
3356                 rtl8168c_3_hw_phy_config(tp);
3357                 break;
3358         case RTL_GIGA_MAC_VER_22:
3359                 rtl8168c_4_hw_phy_config(tp);
3360                 break;
3361         case RTL_GIGA_MAC_VER_23:
3362         case RTL_GIGA_MAC_VER_24:
3363                 rtl8168cp_2_hw_phy_config(tp);
3364                 break;
3365         case RTL_GIGA_MAC_VER_25:
3366                 rtl8168d_1_hw_phy_config(tp);
3367                 break;
3368         case RTL_GIGA_MAC_VER_26:
3369                 rtl8168d_2_hw_phy_config(tp);
3370                 break;
3371         case RTL_GIGA_MAC_VER_27:
3372                 rtl8168d_3_hw_phy_config(tp);
3373                 break;
3374         case RTL_GIGA_MAC_VER_28:
3375                 rtl8168d_4_hw_phy_config(tp);
3376                 break;
3377         case RTL_GIGA_MAC_VER_29:
3378         case RTL_GIGA_MAC_VER_30:
3379                 rtl8105e_hw_phy_config(tp);
3380                 break;
3381         case RTL_GIGA_MAC_VER_31:
3382                 /* None. */
3383                 break;
3384         case RTL_GIGA_MAC_VER_32:
3385         case RTL_GIGA_MAC_VER_33:
3386                 rtl8168e_1_hw_phy_config(tp);
3387                 break;
3388         case RTL_GIGA_MAC_VER_34:
3389                 rtl8168e_2_hw_phy_config(tp);
3390                 break;
3391         case RTL_GIGA_MAC_VER_35:
3392                 rtl8168f_1_hw_phy_config(tp);
3393                 break;
3394         case RTL_GIGA_MAC_VER_36:
3395                 rtl8168f_2_hw_phy_config(tp);
3396                 break;
3397
3398         case RTL_GIGA_MAC_VER_37:
3399                 rtl8402_hw_phy_config(tp);
3400                 break;
3401
3402         case RTL_GIGA_MAC_VER_38:
3403                 rtl8411_hw_phy_config(tp);
3404                 break;
3405
3406         case RTL_GIGA_MAC_VER_39:
3407                 rtl8106e_hw_phy_config(tp);
3408                 break;
3409
3410         default:
3411                 break;
3412         }
3413 }
3414
3415 static void rtl_phy_work(struct rtl8169_private *tp)
3416 {
3417         struct timer_list *timer = &tp->timer;
3418         void __iomem *ioaddr = tp->mmio_addr;
3419         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3420
3421         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3422
3423         if (tp->phy_reset_pending(tp)) {
3424                 /*
3425                  * A busy loop could burn quite a few cycles on nowadays CPU.
3426                  * Let's delay the execution of the timer for a few ticks.
3427                  */
3428                 timeout = HZ/10;
3429                 goto out_mod_timer;
3430         }
3431
3432         if (tp->link_ok(ioaddr))
3433                 return;
3434
3435         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3436
3437         tp->phy_reset_enable(tp);
3438
3439 out_mod_timer:
3440         mod_timer(timer, jiffies + timeout);
3441 }
3442
3443 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3444 {
3445         if (!test_and_set_bit(flag, tp->wk.flags))
3446                 schedule_work(&tp->wk.work);
3447 }
3448
3449 static void rtl8169_phy_timer(unsigned long __opaque)
3450 {
3451         struct net_device *dev = (struct net_device *)__opaque;
3452         struct rtl8169_private *tp = netdev_priv(dev);
3453
3454         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3455 }
3456
3457 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3458                                   void __iomem *ioaddr)
3459 {
3460         iounmap(ioaddr);
3461         pci_release_regions(pdev);
3462         pci_clear_mwi(pdev);
3463         pci_disable_device(pdev);
3464         free_netdev(dev);
3465 }
3466
3467 static void rtl8169_phy_reset(struct net_device *dev,
3468                               struct rtl8169_private *tp)
3469 {
3470         unsigned int i;
3471
3472         tp->phy_reset_enable(tp);
3473         for (i = 0; i < 100; i++) {
3474                 if (!tp->phy_reset_pending(tp))
3475                         return;
3476                 msleep(1);
3477         }
3478         netif_err(tp, link, dev, "PHY reset failed\n");
3479 }
3480
3481 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3482 {
3483         void __iomem *ioaddr = tp->mmio_addr;
3484
3485         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3486             (RTL_R8(PHYstatus) & TBI_Enable);
3487 }
3488
3489 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3490 {
3491         void __iomem *ioaddr = tp->mmio_addr;
3492
3493         rtl_hw_phy_config(dev);
3494
3495         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3496                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3497                 RTL_W8(0x82, 0x01);
3498         }
3499
3500         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3501
3502         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3503                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3504
3505         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3506                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3507                 RTL_W8(0x82, 0x01);
3508                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3509                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3510         }
3511
3512         rtl8169_phy_reset(dev, tp);
3513
3514         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3515                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3516                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3517                           (tp->mii.supports_gmii ?
3518                            ADVERTISED_1000baseT_Half |
3519                            ADVERTISED_1000baseT_Full : 0));
3520
3521         if (rtl_tbi_enabled(tp))
3522                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3523 }
3524
3525 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3526 {
3527         void __iomem *ioaddr = tp->mmio_addr;
3528         u32 high;
3529         u32 low;
3530
3531         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3532         high = addr[4] | (addr[5] << 8);
3533
3534         rtl_lock_work(tp);
3535
3536         RTL_W8(Cfg9346, Cfg9346_Unlock);
3537
3538         RTL_W32(MAC4, high);
3539         RTL_R32(MAC4);
3540
3541         RTL_W32(MAC0, low);
3542         RTL_R32(MAC0);
3543
3544         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3545                 const struct exgmac_reg e[] = {
3546                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3547                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3548                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3549                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3550                                                                 low  >> 16 },
3551                 };
3552
3553                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3554         }
3555
3556         RTL_W8(Cfg9346, Cfg9346_Lock);
3557
3558         rtl_unlock_work(tp);
3559 }
3560
3561 static int rtl_set_mac_address(struct net_device *dev, void *p)
3562 {
3563         struct rtl8169_private *tp = netdev_priv(dev);
3564         struct sockaddr *addr = p;
3565
3566         if (!is_valid_ether_addr(addr->sa_data))
3567                 return -EADDRNOTAVAIL;
3568
3569         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3570
3571         rtl_rar_set(tp, dev->dev_addr);
3572
3573         return 0;
3574 }
3575
3576 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3577 {
3578         struct rtl8169_private *tp = netdev_priv(dev);
3579         struct mii_ioctl_data *data = if_mii(ifr);
3580
3581         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3582 }
3583
3584 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3585                           struct mii_ioctl_data *data, int cmd)
3586 {
3587         switch (cmd) {
3588         case SIOCGMIIPHY:
3589                 data->phy_id = 32; /* Internal PHY */
3590                 return 0;
3591
3592         case SIOCGMIIREG:
3593                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3594                 return 0;
3595
3596         case SIOCSMIIREG:
3597                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3598                 return 0;
3599         }
3600         return -EOPNOTSUPP;
3601 }
3602
3603 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3604 {
3605         return -EOPNOTSUPP;
3606 }
3607
3608 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3609 {
3610         if (tp->features & RTL_FEATURE_MSI) {
3611                 pci_disable_msi(pdev);
3612                 tp->features &= ~RTL_FEATURE_MSI;
3613         }
3614 }
3615
3616 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3617 {
3618         struct mdio_ops *ops = &tp->mdio_ops;
3619
3620         switch (tp->mac_version) {
3621         case RTL_GIGA_MAC_VER_27:
3622                 ops->write      = r8168dp_1_mdio_write;
3623                 ops->read       = r8168dp_1_mdio_read;
3624                 break;
3625         case RTL_GIGA_MAC_VER_28:
3626         case RTL_GIGA_MAC_VER_31:
3627                 ops->write      = r8168dp_2_mdio_write;
3628                 ops->read       = r8168dp_2_mdio_read;
3629                 break;
3630         default:
3631                 ops->write      = r8169_mdio_write;
3632                 ops->read       = r8169_mdio_read;
3633                 break;
3634         }
3635 }
3636
3637 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3638 {
3639         void __iomem *ioaddr = tp->mmio_addr;
3640
3641         switch (tp->mac_version) {
3642         case RTL_GIGA_MAC_VER_29:
3643         case RTL_GIGA_MAC_VER_30:
3644         case RTL_GIGA_MAC_VER_32:
3645         case RTL_GIGA_MAC_VER_33:
3646         case RTL_GIGA_MAC_VER_34:
3647         case RTL_GIGA_MAC_VER_37:
3648         case RTL_GIGA_MAC_VER_38:
3649         case RTL_GIGA_MAC_VER_39:
3650                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3651                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3652                 break;
3653         default:
3654                 break;
3655         }
3656 }
3657
3658 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3659 {
3660         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3661                 return false;
3662
3663         rtl_writephy(tp, 0x1f, 0x0000);
3664         rtl_writephy(tp, MII_BMCR, 0x0000);
3665
3666         rtl_wol_suspend_quirk(tp);
3667
3668         return true;
3669 }
3670
3671 static void r810x_phy_power_down(struct rtl8169_private *tp)
3672 {
3673         rtl_writephy(tp, 0x1f, 0x0000);
3674         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3675 }
3676
3677 static void r810x_phy_power_up(struct rtl8169_private *tp)
3678 {
3679         rtl_writephy(tp, 0x1f, 0x0000);
3680         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3681 }
3682
3683 static void r810x_pll_power_down(struct rtl8169_private *tp)
3684 {
3685         void __iomem *ioaddr = tp->mmio_addr;
3686
3687         if (rtl_wol_pll_power_down(tp))
3688                 return;
3689
3690         r810x_phy_power_down(tp);
3691
3692         switch (tp->mac_version) {
3693         case RTL_GIGA_MAC_VER_07:
3694         case RTL_GIGA_MAC_VER_08:
3695         case RTL_GIGA_MAC_VER_09:
3696         case RTL_GIGA_MAC_VER_10:
3697         case RTL_GIGA_MAC_VER_13:
3698         case RTL_GIGA_MAC_VER_16:
3699                 break;
3700         default:
3701                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3702                 break;
3703         }
3704 }
3705
3706 static void r810x_pll_power_up(struct rtl8169_private *tp)
3707 {
3708         void __iomem *ioaddr = tp->mmio_addr;
3709
3710         r810x_phy_power_up(tp);
3711
3712         switch (tp->mac_version) {
3713         case RTL_GIGA_MAC_VER_07:
3714         case RTL_GIGA_MAC_VER_08:
3715         case RTL_GIGA_MAC_VER_09:
3716         case RTL_GIGA_MAC_VER_10:
3717         case RTL_GIGA_MAC_VER_13:
3718         case RTL_GIGA_MAC_VER_16:
3719                 break;
3720         default:
3721                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3722                 break;
3723         }
3724 }
3725
3726 static void r8168_phy_power_up(struct rtl8169_private *tp)
3727 {
3728         rtl_writephy(tp, 0x1f, 0x0000);
3729         switch (tp->mac_version) {
3730         case RTL_GIGA_MAC_VER_11:
3731         case RTL_GIGA_MAC_VER_12:
3732         case RTL_GIGA_MAC_VER_17:
3733         case RTL_GIGA_MAC_VER_18:
3734         case RTL_GIGA_MAC_VER_19:
3735         case RTL_GIGA_MAC_VER_20:
3736         case RTL_GIGA_MAC_VER_21:
3737         case RTL_GIGA_MAC_VER_22:
3738         case RTL_GIGA_MAC_VER_23:
3739         case RTL_GIGA_MAC_VER_24:
3740         case RTL_GIGA_MAC_VER_25:
3741         case RTL_GIGA_MAC_VER_26:
3742         case RTL_GIGA_MAC_VER_27:
3743         case RTL_GIGA_MAC_VER_28:
3744         case RTL_GIGA_MAC_VER_31:
3745                 rtl_writephy(tp, 0x0e, 0x0000);
3746                 break;
3747         default:
3748                 break;
3749         }
3750         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3751 }
3752
3753 static void r8168_phy_power_down(struct rtl8169_private *tp)
3754 {
3755         rtl_writephy(tp, 0x1f, 0x0000);
3756         switch (tp->mac_version) {
3757         case RTL_GIGA_MAC_VER_32:
3758         case RTL_GIGA_MAC_VER_33:
3759                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3760                 break;
3761
3762         case RTL_GIGA_MAC_VER_11:
3763         case RTL_GIGA_MAC_VER_12:
3764         case RTL_GIGA_MAC_VER_17:
3765         case RTL_GIGA_MAC_VER_18:
3766         case RTL_GIGA_MAC_VER_19:
3767         case RTL_GIGA_MAC_VER_20:
3768         case RTL_GIGA_MAC_VER_21:
3769         case RTL_GIGA_MAC_VER_22:
3770         case RTL_GIGA_MAC_VER_23:
3771         case RTL_GIGA_MAC_VER_24:
3772         case RTL_GIGA_MAC_VER_25:
3773         case RTL_GIGA_MAC_VER_26:
3774         case RTL_GIGA_MAC_VER_27:
3775         case RTL_GIGA_MAC_VER_28:
3776         case RTL_GIGA_MAC_VER_31:
3777                 rtl_writephy(tp, 0x0e, 0x0200);
3778         default:
3779                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3780                 break;
3781         }
3782 }
3783
3784 static void r8168_pll_power_down(struct rtl8169_private *tp)
3785 {
3786         void __iomem *ioaddr = tp->mmio_addr;
3787
3788         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3789              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3790              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3791             r8168dp_check_dash(tp)) {
3792                 return;
3793         }
3794
3795         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3796              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3797             (RTL_R16(CPlusCmd) & ASF)) {
3798                 return;
3799         }
3800
3801         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3802             tp->mac_version == RTL_GIGA_MAC_VER_33)
3803                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3804
3805         if (rtl_wol_pll_power_down(tp))
3806                 return;
3807
3808         r8168_phy_power_down(tp);
3809
3810         switch (tp->mac_version) {
3811         case RTL_GIGA_MAC_VER_25:
3812         case RTL_GIGA_MAC_VER_26:
3813         case RTL_GIGA_MAC_VER_27:
3814         case RTL_GIGA_MAC_VER_28:
3815         case RTL_GIGA_MAC_VER_31:
3816         case RTL_GIGA_MAC_VER_32:
3817         case RTL_GIGA_MAC_VER_33:
3818                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3819                 break;
3820         }
3821 }
3822
3823 static void r8168_pll_power_up(struct rtl8169_private *tp)
3824 {
3825         void __iomem *ioaddr = tp->mmio_addr;
3826
3827         switch (tp->mac_version) {
3828         case RTL_GIGA_MAC_VER_25:
3829         case RTL_GIGA_MAC_VER_26:
3830         case RTL_GIGA_MAC_VER_27:
3831         case RTL_GIGA_MAC_VER_28:
3832         case RTL_GIGA_MAC_VER_31:
3833         case RTL_GIGA_MAC_VER_32:
3834         case RTL_GIGA_MAC_VER_33:
3835                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3836                 break;
3837         }
3838
3839         r8168_phy_power_up(tp);
3840 }
3841
3842 static void rtl_generic_op(struct rtl8169_private *tp,
3843                            void (*op)(struct rtl8169_private *))
3844 {
3845         if (op)
3846                 op(tp);
3847 }
3848
3849 static void rtl_pll_power_down(struct rtl8169_private *tp)
3850 {
3851         rtl_generic_op(tp, tp->pll_power_ops.down);
3852 }
3853
3854 static void rtl_pll_power_up(struct rtl8169_private *tp)
3855 {
3856         rtl_generic_op(tp, tp->pll_power_ops.up);
3857 }
3858
3859 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3860 {
3861         struct pll_power_ops *ops = &tp->pll_power_ops;
3862
3863         switch (tp->mac_version) {
3864         case RTL_GIGA_MAC_VER_07:
3865         case RTL_GIGA_MAC_VER_08:
3866         case RTL_GIGA_MAC_VER_09:
3867         case RTL_GIGA_MAC_VER_10:
3868         case RTL_GIGA_MAC_VER_16:
3869         case RTL_GIGA_MAC_VER_29:
3870         case RTL_GIGA_MAC_VER_30:
3871         case RTL_GIGA_MAC_VER_37:
3872         case RTL_GIGA_MAC_VER_39:
3873                 ops->down       = r810x_pll_power_down;
3874                 ops->up         = r810x_pll_power_up;
3875                 break;
3876
3877         case RTL_GIGA_MAC_VER_11:
3878         case RTL_GIGA_MAC_VER_12:
3879         case RTL_GIGA_MAC_VER_17:
3880         case RTL_GIGA_MAC_VER_18:
3881         case RTL_GIGA_MAC_VER_19:
3882         case RTL_GIGA_MAC_VER_20:
3883         case RTL_GIGA_MAC_VER_21:
3884         case RTL_GIGA_MAC_VER_22:
3885         case RTL_GIGA_MAC_VER_23:
3886         case RTL_GIGA_MAC_VER_24:
3887         case RTL_GIGA_MAC_VER_25:
3888         case RTL_GIGA_MAC_VER_26:
3889         case RTL_GIGA_MAC_VER_27:
3890         case RTL_GIGA_MAC_VER_28:
3891         case RTL_GIGA_MAC_VER_31:
3892         case RTL_GIGA_MAC_VER_32:
3893         case RTL_GIGA_MAC_VER_33:
3894         case RTL_GIGA_MAC_VER_34:
3895         case RTL_GIGA_MAC_VER_35:
3896         case RTL_GIGA_MAC_VER_36:
3897         case RTL_GIGA_MAC_VER_38:
3898                 ops->down       = r8168_pll_power_down;
3899                 ops->up         = r8168_pll_power_up;
3900                 break;
3901
3902         default:
3903                 ops->down       = NULL;
3904                 ops->up         = NULL;
3905                 break;
3906         }
3907 }
3908
3909 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3910 {
3911         void __iomem *ioaddr = tp->mmio_addr;
3912
3913         switch (tp->mac_version) {
3914         case RTL_GIGA_MAC_VER_01:
3915         case RTL_GIGA_MAC_VER_02:
3916         case RTL_GIGA_MAC_VER_03:
3917         case RTL_GIGA_MAC_VER_04:
3918         case RTL_GIGA_MAC_VER_05:
3919         case RTL_GIGA_MAC_VER_06:
3920         case RTL_GIGA_MAC_VER_10:
3921         case RTL_GIGA_MAC_VER_11:
3922         case RTL_GIGA_MAC_VER_12:
3923         case RTL_GIGA_MAC_VER_13:
3924         case RTL_GIGA_MAC_VER_14:
3925         case RTL_GIGA_MAC_VER_15:
3926         case RTL_GIGA_MAC_VER_16:
3927         case RTL_GIGA_MAC_VER_17:
3928                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3929                 break;
3930         case RTL_GIGA_MAC_VER_18:
3931         case RTL_GIGA_MAC_VER_19:
3932         case RTL_GIGA_MAC_VER_20:
3933         case RTL_GIGA_MAC_VER_21:
3934         case RTL_GIGA_MAC_VER_22:
3935         case RTL_GIGA_MAC_VER_23:
3936         case RTL_GIGA_MAC_VER_24:
3937         case RTL_GIGA_MAC_VER_34:
3938                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3939                 break;
3940         default:
3941                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3942                 break;
3943         }
3944 }
3945
3946 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3947 {
3948         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3949 }
3950
3951 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3952 {
3953         void __iomem *ioaddr = tp->mmio_addr;
3954
3955         RTL_W8(Cfg9346, Cfg9346_Unlock);
3956         rtl_generic_op(tp, tp->jumbo_ops.enable);
3957         RTL_W8(Cfg9346, Cfg9346_Lock);
3958 }
3959
3960 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3961 {
3962         void __iomem *ioaddr = tp->mmio_addr;
3963
3964         RTL_W8(Cfg9346, Cfg9346_Unlock);
3965         rtl_generic_op(tp, tp->jumbo_ops.disable);
3966         RTL_W8(Cfg9346, Cfg9346_Lock);
3967 }
3968
3969 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3970 {
3971         void __iomem *ioaddr = tp->mmio_addr;
3972
3973         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3974         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3975         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3976 }
3977
3978 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3979 {
3980         void __iomem *ioaddr = tp->mmio_addr;
3981
3982         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3983         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3984         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3985 }
3986
3987 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3988 {
3989         void __iomem *ioaddr = tp->mmio_addr;
3990
3991         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3992 }
3993
3994 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3995 {
3996         void __iomem *ioaddr = tp->mmio_addr;
3997
3998         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3999 }
4000
4001 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4002 {
4003         void __iomem *ioaddr = tp->mmio_addr;
4004
4005         RTL_W8(MaxTxPacketSize, 0x3f);
4006         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4007         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4008         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4009 }
4010
4011 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4012 {
4013         void __iomem *ioaddr = tp->mmio_addr;
4014
4015         RTL_W8(MaxTxPacketSize, 0x0c);
4016         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4017         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4018         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4019 }
4020
4021 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4022 {
4023         rtl_tx_performance_tweak(tp->pci_dev,
4024                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4025 }
4026
4027 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4028 {
4029         rtl_tx_performance_tweak(tp->pci_dev,
4030                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4031 }
4032
4033 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4034 {
4035         void __iomem *ioaddr = tp->mmio_addr;
4036
4037         r8168b_0_hw_jumbo_enable(tp);
4038
4039         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4040 }
4041
4042 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4043 {
4044         void __iomem *ioaddr = tp->mmio_addr;
4045
4046         r8168b_0_hw_jumbo_disable(tp);
4047
4048         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4049 }
4050
4051 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
4052 {
4053         struct jumbo_ops *ops = &tp->jumbo_ops;
4054
4055         switch (tp->mac_version) {
4056         case RTL_GIGA_MAC_VER_11:
4057                 ops->disable    = r8168b_0_hw_jumbo_disable;
4058                 ops->enable     = r8168b_0_hw_jumbo_enable;
4059                 break;
4060         case RTL_GIGA_MAC_VER_12:
4061         case RTL_GIGA_MAC_VER_17:
4062                 ops->disable    = r8168b_1_hw_jumbo_disable;
4063                 ops->enable     = r8168b_1_hw_jumbo_enable;
4064                 break;
4065         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4066         case RTL_GIGA_MAC_VER_19:
4067         case RTL_GIGA_MAC_VER_20:
4068         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4069         case RTL_GIGA_MAC_VER_22:
4070         case RTL_GIGA_MAC_VER_23:
4071         case RTL_GIGA_MAC_VER_24:
4072         case RTL_GIGA_MAC_VER_25:
4073         case RTL_GIGA_MAC_VER_26:
4074                 ops->disable    = r8168c_hw_jumbo_disable;
4075                 ops->enable     = r8168c_hw_jumbo_enable;
4076                 break;
4077         case RTL_GIGA_MAC_VER_27:
4078         case RTL_GIGA_MAC_VER_28:
4079                 ops->disable    = r8168dp_hw_jumbo_disable;
4080                 ops->enable     = r8168dp_hw_jumbo_enable;
4081                 break;
4082         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4083         case RTL_GIGA_MAC_VER_32:
4084         case RTL_GIGA_MAC_VER_33:
4085         case RTL_GIGA_MAC_VER_34:
4086                 ops->disable    = r8168e_hw_jumbo_disable;
4087                 ops->enable     = r8168e_hw_jumbo_enable;
4088                 break;
4089
4090         /*
4091          * No action needed for jumbo frames with 8169.
4092          * No jumbo for 810x at all.
4093          */
4094         default:
4095                 ops->disable    = NULL;
4096                 ops->enable     = NULL;
4097                 break;
4098         }
4099 }
4100
4101 static void rtl_hw_reset(struct rtl8169_private *tp)
4102 {
4103         void __iomem *ioaddr = tp->mmio_addr;
4104         int i;
4105
4106         /* Soft reset the chip. */
4107         RTL_W8(ChipCmd, CmdReset);
4108
4109         /* Check that the chip has finished the reset. */
4110         for (i = 0; i < 100; i++) {
4111                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
4112                         break;
4113                 udelay(100);
4114         }
4115 }
4116
4117 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4118 {
4119         struct rtl_fw *rtl_fw;
4120         const char *name;
4121         int rc = -ENOMEM;
4122
4123         name = rtl_lookup_firmware_name(tp);
4124         if (!name)
4125                 goto out_no_firmware;
4126
4127         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4128         if (!rtl_fw)
4129                 goto err_warn;
4130
4131         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4132         if (rc < 0)
4133                 goto err_free;
4134
4135         rc = rtl_check_firmware(tp, rtl_fw);
4136         if (rc < 0)
4137                 goto err_release_firmware;
4138
4139         tp->rtl_fw = rtl_fw;
4140 out:
4141         return;
4142
4143 err_release_firmware:
4144         release_firmware(rtl_fw->fw);
4145 err_free:
4146         kfree(rtl_fw);
4147 err_warn:
4148         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4149                    name, rc);
4150 out_no_firmware:
4151         tp->rtl_fw = NULL;
4152         goto out;
4153 }
4154
4155 static void rtl_request_firmware(struct rtl8169_private *tp)
4156 {
4157         if (IS_ERR(tp->rtl_fw))
4158                 rtl_request_uncached_firmware(tp);
4159 }
4160
4161 static void rtl_rx_close(struct rtl8169_private *tp)
4162 {
4163         void __iomem *ioaddr = tp->mmio_addr;
4164
4165         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4166 }
4167
4168 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4169 {
4170         void __iomem *ioaddr = tp->mmio_addr;
4171
4172         /* Disable interrupts */
4173         rtl8169_irq_mask_and_ack(tp);
4174
4175         rtl_rx_close(tp);
4176
4177         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4178             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4179             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4180                 while (RTL_R8(TxPoll) & NPQ)
4181                         udelay(20);
4182         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4183                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4184                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4185                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4186                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4187                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4188                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4189                         udelay(100);
4190         } else {
4191                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4192                 udelay(100);
4193         }
4194
4195         rtl_hw_reset(tp);
4196 }
4197
4198 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4199 {
4200         void __iomem *ioaddr = tp->mmio_addr;
4201
4202         /* Set DMA burst size and Interframe Gap Time */
4203         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4204                 (InterFrameGap << TxInterFrameGapShift));
4205 }
4206
4207 static void rtl_hw_start(struct net_device *dev)
4208 {
4209         struct rtl8169_private *tp = netdev_priv(dev);
4210
4211         tp->hw_start(dev);
4212
4213         rtl_irq_enable_all(tp);
4214 }
4215
4216 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4217                                          void __iomem *ioaddr)
4218 {
4219         /*
4220          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4221          * register to be written before TxDescAddrLow to work.
4222          * Switching from MMIO to I/O access fixes the issue as well.
4223          */
4224         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4225         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4226         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4227         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4228 }
4229
4230 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4231 {
4232         u16 cmd;
4233
4234         cmd = RTL_R16(CPlusCmd);
4235         RTL_W16(CPlusCmd, cmd);
4236         return cmd;
4237 }
4238
4239 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4240 {
4241         /* Low hurts. Let's disable the filtering. */
4242         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4243 }
4244
4245 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4246 {
4247         static const struct rtl_cfg2_info {
4248                 u32 mac_version;
4249                 u32 clk;
4250                 u32 val;
4251         } cfg2_info [] = {
4252                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4253                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4254                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4255                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4256         };
4257         const struct rtl_cfg2_info *p = cfg2_info;
4258         unsigned int i;
4259         u32 clk;
4260
4261         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4262         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4263                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4264                         RTL_W32(0x7c, p->val);
4265                         break;
4266                 }
4267         }
4268 }
4269
4270 static void rtl_set_rx_mode(struct net_device *dev)
4271 {
4272         struct rtl8169_private *tp = netdev_priv(dev);
4273         void __iomem *ioaddr = tp->mmio_addr;
4274         u32 mc_filter[2];       /* Multicast hash filter */
4275         int rx_mode;
4276         u32 tmp = 0;
4277
4278         if (dev->flags & IFF_PROMISC) {
4279                 /* Unconditionally log net taps. */
4280                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4281                 rx_mode =
4282                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4283                     AcceptAllPhys;
4284                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4285         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4286                    (dev->flags & IFF_ALLMULTI)) {
4287                 /* Too many to filter perfectly -- accept all multicasts. */
4288                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4289                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4290         } else {
4291                 struct netdev_hw_addr *ha;
4292
4293                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4294                 mc_filter[1] = mc_filter[0] = 0;
4295                 netdev_for_each_mc_addr(ha, dev) {
4296                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4297                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4298                         rx_mode |= AcceptMulticast;
4299                 }
4300         }
4301
4302         if (dev->features & NETIF_F_RXALL)
4303                 rx_mode |= (AcceptErr | AcceptRunt);
4304
4305         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4306
4307         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4308                 u32 data = mc_filter[0];
4309
4310                 mc_filter[0] = swab32(mc_filter[1]);
4311                 mc_filter[1] = swab32(data);
4312         }
4313
4314         RTL_W32(MAR0 + 4, mc_filter[1]);
4315         RTL_W32(MAR0 + 0, mc_filter[0]);
4316
4317         RTL_W32(RxConfig, tmp);
4318 }
4319
4320 static void rtl_hw_start_8169(struct net_device *dev)
4321 {
4322         struct rtl8169_private *tp = netdev_priv(dev);
4323         void __iomem *ioaddr = tp->mmio_addr;
4324         struct pci_dev *pdev = tp->pci_dev;
4325
4326         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4327                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4328                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4329         }
4330
4331         RTL_W8(Cfg9346, Cfg9346_Unlock);
4332         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4333             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4334             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4335             tp->mac_version == RTL_GIGA_MAC_VER_04)
4336                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4337
4338         rtl_init_rxcfg(tp);
4339
4340         RTL_W8(EarlyTxThres, NoEarlyTx);
4341
4342         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4343
4344         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4345             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4346             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4347             tp->mac_version == RTL_GIGA_MAC_VER_04)
4348                 rtl_set_rx_tx_config_registers(tp);
4349
4350         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4351
4352         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4353             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4354                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4355                         "Bit-3 and bit-14 MUST be 1\n");
4356                 tp->cp_cmd |= (1 << 14);
4357         }
4358
4359         RTL_W16(CPlusCmd, tp->cp_cmd);
4360
4361         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4362
4363         /*
4364          * Undocumented corner. Supposedly:
4365          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4366          */
4367         RTL_W16(IntrMitigate, 0x0000);
4368
4369         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4370
4371         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4372             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4373             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4374             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4375                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4376                 rtl_set_rx_tx_config_registers(tp);
4377         }
4378
4379         RTL_W8(Cfg9346, Cfg9346_Lock);
4380
4381         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4382         RTL_R8(IntrMask);
4383
4384         RTL_W32(RxMissed, 0);
4385
4386         rtl_set_rx_mode(dev);
4387
4388         /* no early-rx interrupts */
4389         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4390 }
4391
4392 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4393 {
4394         if (tp->csi_ops.write)
4395                 tp->csi_ops.write(tp->mmio_addr, addr, value);
4396 }
4397
4398 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4399 {
4400         if (tp->csi_ops.read)
4401                 return tp->csi_ops.read(tp->mmio_addr, addr);
4402         else
4403                 return ~0;
4404 }
4405
4406 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4407 {
4408         u32 csi;
4409
4410         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4411         rtl_csi_write(tp, 0x070c, csi | bits);
4412 }
4413
4414 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4415 {
4416         rtl_csi_access_enable(tp, 0x17000000);
4417 }
4418
4419 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4420 {
4421         rtl_csi_access_enable(tp, 0x27000000);
4422 }
4423
4424 static void r8169_csi_write(void __iomem *ioaddr, int addr, int value)
4425 {
4426         unsigned int i;
4427
4428         RTL_W32(CSIDR, value);
4429         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4430                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4431
4432         for (i = 0; i < 100; i++) {
4433                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4434                         break;
4435                 udelay(10);
4436         }
4437 }
4438
4439 static u32 r8169_csi_read(void __iomem *ioaddr, int addr)
4440 {
4441         u32 value = ~0x00;
4442         unsigned int i;
4443
4444         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4445                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4446
4447         for (i = 0; i < 100; i++) {
4448                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4449                         value = RTL_R32(CSIDR);
4450                         break;
4451                 }
4452                 udelay(10);
4453         }
4454
4455         return value;
4456 }
4457
4458 static void r8402_csi_write(void __iomem *ioaddr, int addr, int value)
4459 {
4460         unsigned int i;
4461
4462         RTL_W32(CSIDR, value);
4463         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4464                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4465                 CSIAR_FUNC_NIC);
4466
4467         for (i = 0; i < 100; i++) {
4468                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
4469                         break;
4470                 udelay(10);
4471         }
4472 }
4473
4474 static u32 r8402_csi_read(void __iomem *ioaddr, int addr)
4475 {
4476         u32 value = ~0x00;
4477         unsigned int i;
4478
4479         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4480                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4481
4482         for (i = 0; i < 100; i++) {
4483                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
4484                         value = RTL_R32(CSIDR);
4485                         break;
4486                 }
4487                 udelay(10);
4488         }
4489
4490         return value;
4491 }
4492
4493 static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4494 {
4495         struct csi_ops *ops = &tp->csi_ops;
4496
4497         switch (tp->mac_version) {
4498         case RTL_GIGA_MAC_VER_01:
4499         case RTL_GIGA_MAC_VER_02:
4500         case RTL_GIGA_MAC_VER_03:
4501         case RTL_GIGA_MAC_VER_04:
4502         case RTL_GIGA_MAC_VER_05:
4503         case RTL_GIGA_MAC_VER_06:
4504         case RTL_GIGA_MAC_VER_10:
4505         case RTL_GIGA_MAC_VER_11:
4506         case RTL_GIGA_MAC_VER_12:
4507         case RTL_GIGA_MAC_VER_13:
4508         case RTL_GIGA_MAC_VER_14:
4509         case RTL_GIGA_MAC_VER_15:
4510         case RTL_GIGA_MAC_VER_16:
4511         case RTL_GIGA_MAC_VER_17:
4512                 ops->write      = NULL;
4513                 ops->read       = NULL;
4514                 break;
4515
4516         case RTL_GIGA_MAC_VER_37:
4517         case RTL_GIGA_MAC_VER_38:
4518                 ops->write      = r8402_csi_write;
4519                 ops->read       = r8402_csi_read;
4520                 break;
4521
4522         default:
4523                 ops->write      = r8169_csi_write;
4524                 ops->read       = r8169_csi_read;
4525                 break;
4526         }
4527 }
4528
4529 struct ephy_info {
4530         unsigned int offset;
4531         u16 mask;
4532         u16 bits;
4533 };
4534
4535 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4536 {
4537         u16 w;
4538
4539         while (len-- > 0) {
4540                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4541                 rtl_ephy_write(ioaddr, e->offset, w);
4542                 e++;
4543         }
4544 }
4545
4546 static void rtl_disable_clock_request(struct pci_dev *pdev)
4547 {
4548         int cap = pci_pcie_cap(pdev);
4549
4550         if (cap) {
4551                 u16 ctl;
4552
4553                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4554                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4555                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4556         }
4557 }
4558
4559 static void rtl_enable_clock_request(struct pci_dev *pdev)
4560 {
4561         int cap = pci_pcie_cap(pdev);
4562
4563         if (cap) {
4564                 u16 ctl;
4565
4566                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4567                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4568                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4569         }
4570 }
4571
4572 #define R8168_CPCMD_QUIRK_MASK (\
4573         EnableBist | \
4574         Mac_dbgo_oe | \
4575         Force_half_dup | \
4576         Force_rxflow_en | \
4577         Force_txflow_en | \
4578         Cxpl_dbg_sel | \
4579         ASF | \
4580         PktCntrDisable | \
4581         Mac_dbgo_sel)
4582
4583 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4584 {
4585         void __iomem *ioaddr = tp->mmio_addr;
4586         struct pci_dev *pdev = tp->pci_dev;
4587
4588         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4589
4590         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4591
4592         rtl_tx_performance_tweak(pdev,
4593                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4594 }
4595
4596 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4597 {
4598         void __iomem *ioaddr = tp->mmio_addr;
4599
4600         rtl_hw_start_8168bb(tp);
4601
4602         RTL_W8(MaxTxPacketSize, TxPacketMax);
4603
4604         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4605 }
4606
4607 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4608 {
4609         void __iomem *ioaddr = tp->mmio_addr;
4610         struct pci_dev *pdev = tp->pci_dev;
4611
4612         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4613
4614         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4615
4616         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4617
4618         rtl_disable_clock_request(pdev);
4619
4620         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4621 }
4622
4623 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4624 {
4625         void __iomem *ioaddr = tp->mmio_addr;
4626         static const struct ephy_info e_info_8168cp[] = {
4627                 { 0x01, 0,      0x0001 },
4628                 { 0x02, 0x0800, 0x1000 },
4629                 { 0x03, 0,      0x0042 },
4630                 { 0x06, 0x0080, 0x0000 },
4631                 { 0x07, 0,      0x2000 }
4632         };
4633
4634         rtl_csi_access_enable_2(tp);
4635
4636         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4637
4638         __rtl_hw_start_8168cp(tp);
4639 }
4640
4641 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4642 {
4643         void __iomem *ioaddr = tp->mmio_addr;
4644         struct pci_dev *pdev = tp->pci_dev;
4645
4646         rtl_csi_access_enable_2(tp);
4647
4648         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4649
4650         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4651
4652         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4653 }
4654
4655 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4656 {
4657         void __iomem *ioaddr = tp->mmio_addr;
4658         struct pci_dev *pdev = tp->pci_dev;
4659
4660         rtl_csi_access_enable_2(tp);
4661
4662         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4663
4664         /* Magic. */
4665         RTL_W8(DBG_REG, 0x20);
4666
4667         RTL_W8(MaxTxPacketSize, TxPacketMax);
4668
4669         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4670
4671         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4672 }
4673
4674 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4675 {
4676         void __iomem *ioaddr = tp->mmio_addr;
4677         static const struct ephy_info e_info_8168c_1[] = {
4678                 { 0x02, 0x0800, 0x1000 },
4679                 { 0x03, 0,      0x0002 },
4680                 { 0x06, 0x0080, 0x0000 }
4681         };
4682
4683         rtl_csi_access_enable_2(tp);
4684
4685         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4686
4687         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4688
4689         __rtl_hw_start_8168cp(tp);
4690 }
4691
4692 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4693 {
4694         void __iomem *ioaddr = tp->mmio_addr;
4695         static const struct ephy_info e_info_8168c_2[] = {
4696                 { 0x01, 0,      0x0001 },
4697                 { 0x03, 0x0400, 0x0220 }
4698         };
4699
4700         rtl_csi_access_enable_2(tp);
4701
4702         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4703
4704         __rtl_hw_start_8168cp(tp);
4705 }
4706
4707 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4708 {
4709         rtl_hw_start_8168c_2(tp);
4710 }
4711
4712 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4713 {
4714         rtl_csi_access_enable_2(tp);
4715
4716         __rtl_hw_start_8168cp(tp);
4717 }
4718
4719 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4720 {
4721         void __iomem *ioaddr = tp->mmio_addr;
4722         struct pci_dev *pdev = tp->pci_dev;
4723
4724         rtl_csi_access_enable_2(tp);
4725
4726         rtl_disable_clock_request(pdev);
4727
4728         RTL_W8(MaxTxPacketSize, TxPacketMax);
4729
4730         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4731
4732         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4733 }
4734
4735 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4736 {
4737         void __iomem *ioaddr = tp->mmio_addr;
4738         struct pci_dev *pdev = tp->pci_dev;
4739
4740         rtl_csi_access_enable_1(tp);
4741
4742         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4743
4744         RTL_W8(MaxTxPacketSize, TxPacketMax);
4745
4746         rtl_disable_clock_request(pdev);
4747 }
4748
4749 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4750 {
4751         void __iomem *ioaddr = tp->mmio_addr;
4752         struct pci_dev *pdev = tp->pci_dev;
4753         static const struct ephy_info e_info_8168d_4[] = {
4754                 { 0x0b, ~0,     0x48 },
4755                 { 0x19, 0x20,   0x50 },
4756                 { 0x0c, ~0,     0x20 }
4757         };
4758         int i;
4759
4760         rtl_csi_access_enable_1(tp);
4761
4762         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4763
4764         RTL_W8(MaxTxPacketSize, TxPacketMax);
4765
4766         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4767                 const struct ephy_info *e = e_info_8168d_4 + i;
4768                 u16 w;
4769
4770                 w = rtl_ephy_read(ioaddr, e->offset);
4771                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4772         }
4773
4774         rtl_enable_clock_request(pdev);
4775 }
4776
4777 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4778 {
4779         void __iomem *ioaddr = tp->mmio_addr;
4780         struct pci_dev *pdev = tp->pci_dev;
4781         static const struct ephy_info e_info_8168e_1[] = {
4782                 { 0x00, 0x0200, 0x0100 },
4783                 { 0x00, 0x0000, 0x0004 },
4784                 { 0x06, 0x0002, 0x0001 },
4785                 { 0x06, 0x0000, 0x0030 },
4786                 { 0x07, 0x0000, 0x2000 },
4787                 { 0x00, 0x0000, 0x0020 },
4788                 { 0x03, 0x5800, 0x2000 },
4789                 { 0x03, 0x0000, 0x0001 },
4790                 { 0x01, 0x0800, 0x1000 },
4791                 { 0x07, 0x0000, 0x4000 },
4792                 { 0x1e, 0x0000, 0x2000 },
4793                 { 0x19, 0xffff, 0xfe6c },
4794                 { 0x0a, 0x0000, 0x0040 }
4795         };
4796
4797         rtl_csi_access_enable_2(tp);
4798
4799         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4800
4801         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4802
4803         RTL_W8(MaxTxPacketSize, TxPacketMax);
4804
4805         rtl_disable_clock_request(pdev);
4806
4807         /* Reset tx FIFO pointer */
4808         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4809         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4810
4811         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4812 }
4813
4814 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4815 {
4816         void __iomem *ioaddr = tp->mmio_addr;
4817         struct pci_dev *pdev = tp->pci_dev;
4818         static const struct ephy_info e_info_8168e_2[] = {
4819                 { 0x09, 0x0000, 0x0080 },
4820                 { 0x19, 0x0000, 0x0224 }
4821         };
4822
4823         rtl_csi_access_enable_1(tp);
4824
4825         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4826
4827         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4828
4829         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4830         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4831         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4832         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4833         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4834         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4835         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4836         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4837                      ERIAR_EXGMAC);
4838
4839         RTL_W8(MaxTxPacketSize, EarlySize);
4840
4841         rtl_disable_clock_request(pdev);
4842
4843         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4844         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4845
4846         /* Adjust EEE LED frequency */
4847         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4848
4849         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4850         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4851         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4852 }
4853
4854 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4855 {
4856         void __iomem *ioaddr = tp->mmio_addr;
4857         struct pci_dev *pdev = tp->pci_dev;
4858
4859         rtl_csi_access_enable_2(tp);
4860
4861         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4862
4863         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4864         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4865         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4866         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4867         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4868         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4869         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4870         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4871         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4872         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4873
4874         RTL_W8(MaxTxPacketSize, EarlySize);
4875
4876         rtl_disable_clock_request(pdev);
4877
4878         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4879         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4880         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4881         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4882         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4883 }
4884
4885 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4886 {
4887         void __iomem *ioaddr = tp->mmio_addr;
4888         static const struct ephy_info e_info_8168f_1[] = {
4889                 { 0x06, 0x00c0, 0x0020 },
4890                 { 0x08, 0x0001, 0x0002 },
4891                 { 0x09, 0x0000, 0x0080 },
4892                 { 0x19, 0x0000, 0x0224 }
4893         };
4894
4895         rtl_hw_start_8168f(tp);
4896
4897         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4898
4899         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4900                      ERIAR_EXGMAC);
4901
4902         /* Adjust EEE LED frequency */
4903         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4904 }
4905
4906 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4907 {
4908         void __iomem *ioaddr = tp->mmio_addr;
4909         static const struct ephy_info e_info_8168f_1[] = {
4910                 { 0x06, 0x00c0, 0x0020 },
4911                 { 0x0f, 0xffff, 0x5200 },
4912                 { 0x1e, 0x0000, 0x4000 },
4913                 { 0x19, 0x0000, 0x0224 }
4914         };
4915
4916         rtl_hw_start_8168f(tp);
4917
4918         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4919
4920         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000,
4921                      ERIAR_EXGMAC);
4922 }
4923
4924 static void rtl_hw_start_8168(struct net_device *dev)
4925 {
4926         struct rtl8169_private *tp = netdev_priv(dev);
4927         void __iomem *ioaddr = tp->mmio_addr;
4928
4929         RTL_W8(Cfg9346, Cfg9346_Unlock);
4930
4931         RTL_W8(MaxTxPacketSize, TxPacketMax);
4932
4933         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4934
4935         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4936
4937         RTL_W16(CPlusCmd, tp->cp_cmd);
4938
4939         RTL_W16(IntrMitigate, 0x5151);
4940
4941         /* Work around for RxFIFO overflow. */
4942         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4943                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4944                 tp->event_slow &= ~RxOverflow;
4945         }
4946
4947         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4948
4949         rtl_set_rx_mode(dev);
4950
4951         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4952                 (InterFrameGap << TxInterFrameGapShift));
4953
4954         RTL_R8(IntrMask);
4955
4956         switch (tp->mac_version) {
4957         case RTL_GIGA_MAC_VER_11:
4958                 rtl_hw_start_8168bb(tp);
4959                 break;
4960
4961         case RTL_GIGA_MAC_VER_12:
4962         case RTL_GIGA_MAC_VER_17:
4963                 rtl_hw_start_8168bef(tp);
4964                 break;
4965
4966         case RTL_GIGA_MAC_VER_18:
4967                 rtl_hw_start_8168cp_1(tp);
4968                 break;
4969
4970         case RTL_GIGA_MAC_VER_19:
4971                 rtl_hw_start_8168c_1(tp);
4972                 break;
4973
4974         case RTL_GIGA_MAC_VER_20:
4975                 rtl_hw_start_8168c_2(tp);
4976                 break;
4977
4978         case RTL_GIGA_MAC_VER_21:
4979                 rtl_hw_start_8168c_3(tp);
4980                 break;
4981
4982         case RTL_GIGA_MAC_VER_22:
4983                 rtl_hw_start_8168c_4(tp);
4984                 break;
4985
4986         case RTL_GIGA_MAC_VER_23:
4987                 rtl_hw_start_8168cp_2(tp);
4988                 break;
4989
4990         case RTL_GIGA_MAC_VER_24:
4991                 rtl_hw_start_8168cp_3(tp);
4992                 break;
4993
4994         case RTL_GIGA_MAC_VER_25:
4995         case RTL_GIGA_MAC_VER_26:
4996         case RTL_GIGA_MAC_VER_27:
4997                 rtl_hw_start_8168d(tp);
4998                 break;
4999
5000         case RTL_GIGA_MAC_VER_28:
5001                 rtl_hw_start_8168d_4(tp);
5002                 break;
5003
5004         case RTL_GIGA_MAC_VER_31:
5005                 rtl_hw_start_8168dp(tp);
5006                 break;
5007
5008         case RTL_GIGA_MAC_VER_32:
5009         case RTL_GIGA_MAC_VER_33:
5010                 rtl_hw_start_8168e_1(tp);
5011                 break;
5012         case RTL_GIGA_MAC_VER_34:
5013                 rtl_hw_start_8168e_2(tp);
5014                 break;
5015
5016         case RTL_GIGA_MAC_VER_35:
5017         case RTL_GIGA_MAC_VER_36:
5018                 rtl_hw_start_8168f_1(tp);
5019                 break;
5020
5021         case RTL_GIGA_MAC_VER_38:
5022                 rtl_hw_start_8411(tp);
5023                 break;
5024
5025         default:
5026                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5027                         dev->name, tp->mac_version);
5028                 break;
5029         }
5030
5031         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5032
5033         RTL_W8(Cfg9346, Cfg9346_Lock);
5034
5035         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5036 }
5037
5038 #define R810X_CPCMD_QUIRK_MASK (\
5039         EnableBist | \
5040         Mac_dbgo_oe | \
5041         Force_half_dup | \
5042         Force_rxflow_en | \
5043         Force_txflow_en | \
5044         Cxpl_dbg_sel | \
5045         ASF | \
5046         PktCntrDisable | \
5047         Mac_dbgo_sel)
5048
5049 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5050 {
5051         void __iomem *ioaddr = tp->mmio_addr;
5052         struct pci_dev *pdev = tp->pci_dev;
5053         static const struct ephy_info e_info_8102e_1[] = {
5054                 { 0x01, 0, 0x6e65 },
5055                 { 0x02, 0, 0x091f },
5056                 { 0x03, 0, 0xc2f9 },
5057                 { 0x06, 0, 0xafb5 },
5058                 { 0x07, 0, 0x0e00 },
5059                 { 0x19, 0, 0xec80 },
5060                 { 0x01, 0, 0x2e65 },
5061                 { 0x01, 0, 0x6e65 }
5062         };
5063         u8 cfg1;
5064
5065         rtl_csi_access_enable_2(tp);
5066
5067         RTL_W8(DBG_REG, FIX_NAK_1);
5068
5069         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5070
5071         RTL_W8(Config1,
5072                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5073         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5074
5075         cfg1 = RTL_R8(Config1);
5076         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5077                 RTL_W8(Config1, cfg1 & ~LEDS0);
5078
5079         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5080 }
5081
5082 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5083 {
5084         void __iomem *ioaddr = tp->mmio_addr;
5085         struct pci_dev *pdev = tp->pci_dev;
5086
5087         rtl_csi_access_enable_2(tp);
5088
5089         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5090
5091         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5092         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5093 }
5094
5095 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5096 {
5097         rtl_hw_start_8102e_2(tp);
5098
5099         rtl_ephy_write(tp->mmio_addr, 0x03, 0xc2f9);
5100 }
5101
5102 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5103 {
5104         void __iomem *ioaddr = tp->mmio_addr;
5105         static const struct ephy_info e_info_8105e_1[] = {
5106                 { 0x07, 0, 0x4000 },
5107                 { 0x19, 0, 0x0200 },
5108                 { 0x19, 0, 0x0020 },
5109                 { 0x1e, 0, 0x2000 },
5110                 { 0x03, 0, 0x0001 },
5111                 { 0x19, 0, 0x0100 },
5112                 { 0x19, 0, 0x0004 },
5113                 { 0x0a, 0, 0x0020 }
5114         };
5115
5116         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5117         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5118
5119         /* Disable Early Tally Counter */
5120         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5121
5122         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5123         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5124
5125         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5126 }
5127
5128 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5129 {
5130         void __iomem *ioaddr = tp->mmio_addr;
5131
5132         rtl_hw_start_8105e_1(tp);
5133         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5134 }
5135
5136 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5137 {
5138         void __iomem *ioaddr = tp->mmio_addr;
5139         static const struct ephy_info e_info_8402[] = {
5140                 { 0x19, 0xffff, 0xff64 },
5141                 { 0x1e, 0, 0x4000 }
5142         };
5143
5144         rtl_csi_access_enable_2(tp);
5145
5146         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5147         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5148
5149         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5150         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5151
5152         rtl_ephy_init(ioaddr, e_info_8402, ARRAY_SIZE(e_info_8402));
5153
5154         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5155
5156         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5157         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5158         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5159         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5160         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5161         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5162         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00,
5163                      ERIAR_EXGMAC);
5164 }
5165
5166 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5167 {
5168         void __iomem *ioaddr = tp->mmio_addr;
5169
5170         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5171         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5172
5173         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5174         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5175         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5176 }
5177
5178 static void rtl_hw_start_8101(struct net_device *dev)
5179 {
5180         struct rtl8169_private *tp = netdev_priv(dev);
5181         void __iomem *ioaddr = tp->mmio_addr;
5182         struct pci_dev *pdev = tp->pci_dev;
5183
5184         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5185                 tp->event_slow &= ~RxFIFOOver;
5186
5187         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5188             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5189                 int cap = pci_pcie_cap(pdev);
5190
5191                 if (cap) {
5192                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5193                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5194                 }
5195         }
5196
5197         RTL_W8(Cfg9346, Cfg9346_Unlock);
5198
5199         switch (tp->mac_version) {
5200         case RTL_GIGA_MAC_VER_07:
5201                 rtl_hw_start_8102e_1(tp);
5202                 break;
5203
5204         case RTL_GIGA_MAC_VER_08:
5205                 rtl_hw_start_8102e_3(tp);
5206                 break;
5207
5208         case RTL_GIGA_MAC_VER_09:
5209                 rtl_hw_start_8102e_2(tp);
5210                 break;
5211
5212         case RTL_GIGA_MAC_VER_29:
5213                 rtl_hw_start_8105e_1(tp);
5214                 break;
5215         case RTL_GIGA_MAC_VER_30:
5216                 rtl_hw_start_8105e_2(tp);
5217                 break;
5218
5219         case RTL_GIGA_MAC_VER_37:
5220                 rtl_hw_start_8402(tp);
5221                 break;
5222
5223         case RTL_GIGA_MAC_VER_39:
5224                 rtl_hw_start_8106(tp);
5225                 break;
5226         }
5227
5228         RTL_W8(Cfg9346, Cfg9346_Lock);
5229
5230         RTL_W8(MaxTxPacketSize, TxPacketMax);
5231
5232         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5233
5234         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5235         RTL_W16(CPlusCmd, tp->cp_cmd);
5236
5237         RTL_W16(IntrMitigate, 0x0000);
5238
5239         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5240
5241         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5242         rtl_set_rx_tx_config_registers(tp);
5243
5244         RTL_R8(IntrMask);
5245
5246         rtl_set_rx_mode(dev);
5247
5248         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5249 }
5250
5251 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5252 {
5253         struct rtl8169_private *tp = netdev_priv(dev);
5254
5255         if (new_mtu < ETH_ZLEN ||
5256             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5257                 return -EINVAL;
5258
5259         if (new_mtu > ETH_DATA_LEN)
5260                 rtl_hw_jumbo_enable(tp);
5261         else
5262                 rtl_hw_jumbo_disable(tp);
5263
5264         dev->mtu = new_mtu;
5265         netdev_update_features(dev);
5266
5267         return 0;
5268 }
5269
5270 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5271 {
5272         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5273         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5274 }
5275
5276 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5277                                      void **data_buff, struct RxDesc *desc)
5278 {
5279         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5280                          DMA_FROM_DEVICE);
5281
5282         kfree(*data_buff);
5283         *data_buff = NULL;
5284         rtl8169_make_unusable_by_asic(desc);
5285 }
5286
5287 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5288 {
5289         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5290
5291         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5292 }
5293
5294 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5295                                        u32 rx_buf_sz)
5296 {
5297         desc->addr = cpu_to_le64(mapping);
5298         wmb();
5299         rtl8169_mark_to_asic(desc, rx_buf_sz);
5300 }
5301
5302 static inline void *rtl8169_align(void *data)
5303 {
5304         return (void *)ALIGN((long)data, 16);
5305 }
5306
5307 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5308                                              struct RxDesc *desc)
5309 {
5310         void *data;
5311         dma_addr_t mapping;
5312         struct device *d = &tp->pci_dev->dev;
5313         struct net_device *dev = tp->dev;
5314         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5315
5316         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5317         if (!data)
5318                 return NULL;
5319
5320         if (rtl8169_align(data) != data) {
5321                 kfree(data);
5322                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5323                 if (!data)
5324                         return NULL;
5325         }
5326
5327         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5328                                  DMA_FROM_DEVICE);
5329         if (unlikely(dma_mapping_error(d, mapping))) {
5330                 if (net_ratelimit())
5331                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5332                 goto err_out;
5333         }
5334
5335         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5336         return data;
5337
5338 err_out:
5339         kfree(data);
5340         return NULL;
5341 }
5342
5343 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5344 {
5345         unsigned int i;
5346
5347         for (i = 0; i < NUM_RX_DESC; i++) {
5348                 if (tp->Rx_databuff[i]) {
5349                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5350                                             tp->RxDescArray + i);
5351                 }
5352         }
5353 }
5354
5355 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5356 {
5357         desc->opts1 |= cpu_to_le32(RingEnd);
5358 }
5359
5360 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5361 {
5362         unsigned int i;
5363
5364         for (i = 0; i < NUM_RX_DESC; i++) {
5365                 void *data;
5366
5367                 if (tp->Rx_databuff[i])
5368                         continue;
5369
5370                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5371                 if (!data) {
5372                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5373                         goto err_out;
5374                 }
5375                 tp->Rx_databuff[i] = data;
5376         }
5377
5378         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5379         return 0;
5380
5381 err_out:
5382         rtl8169_rx_clear(tp);
5383         return -ENOMEM;
5384 }
5385
5386 static int rtl8169_init_ring(struct net_device *dev)
5387 {
5388         struct rtl8169_private *tp = netdev_priv(dev);
5389
5390         rtl8169_init_ring_indexes(tp);
5391
5392         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5393         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5394
5395         return rtl8169_rx_fill(tp);
5396 }
5397
5398 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5399                                  struct TxDesc *desc)
5400 {
5401         unsigned int len = tx_skb->len;
5402
5403         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5404
5405         desc->opts1 = 0x00;
5406         desc->opts2 = 0x00;
5407         desc->addr = 0x00;
5408         tx_skb->len = 0;
5409 }
5410
5411 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5412                                    unsigned int n)
5413 {
5414         unsigned int i;
5415
5416         for (i = 0; i < n; i++) {
5417                 unsigned int entry = (start + i) % NUM_TX_DESC;
5418                 struct ring_info *tx_skb = tp->tx_skb + entry;
5419                 unsigned int len = tx_skb->len;
5420
5421                 if (len) {
5422                         struct sk_buff *skb = tx_skb->skb;
5423
5424                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5425                                              tp->TxDescArray + entry);
5426                         if (skb) {
5427                                 tp->dev->stats.tx_dropped++;
5428                                 dev_kfree_skb(skb);
5429                                 tx_skb->skb = NULL;
5430                         }
5431                 }
5432         }
5433 }
5434
5435 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5436 {
5437         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5438         tp->cur_tx = tp->dirty_tx = 0;
5439         netdev_reset_queue(tp->dev);
5440 }
5441
5442 static void rtl_reset_work(struct rtl8169_private *tp)
5443 {
5444         struct net_device *dev = tp->dev;
5445         int i;
5446
5447         napi_disable(&tp->napi);
5448         netif_stop_queue(dev);
5449         synchronize_sched();
5450
5451         rtl8169_hw_reset(tp);
5452
5453         for (i = 0; i < NUM_RX_DESC; i++)
5454                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5455
5456         rtl8169_tx_clear(tp);
5457         rtl8169_init_ring_indexes(tp);
5458
5459         napi_enable(&tp->napi);
5460         rtl_hw_start(dev);
5461         netif_wake_queue(dev);
5462         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5463 }
5464
5465 static void rtl8169_tx_timeout(struct net_device *dev)
5466 {
5467         struct rtl8169_private *tp = netdev_priv(dev);
5468
5469         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5470 }
5471
5472 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5473                               u32 *opts)
5474 {
5475         struct skb_shared_info *info = skb_shinfo(skb);
5476         unsigned int cur_frag, entry;
5477         struct TxDesc * uninitialized_var(txd);
5478         struct device *d = &tp->pci_dev->dev;
5479
5480         entry = tp->cur_tx;
5481         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5482                 const skb_frag_t *frag = info->frags + cur_frag;
5483                 dma_addr_t mapping;
5484                 u32 status, len;
5485                 void *addr;
5486
5487                 entry = (entry + 1) % NUM_TX_DESC;
5488
5489                 txd = tp->TxDescArray + entry;
5490                 len = skb_frag_size(frag);
5491                 addr = skb_frag_address(frag);
5492                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5493                 if (unlikely(dma_mapping_error(d, mapping))) {
5494                         if (net_ratelimit())
5495                                 netif_err(tp, drv, tp->dev,
5496                                           "Failed to map TX fragments DMA!\n");
5497                         goto err_out;
5498                 }
5499
5500                 /* Anti gcc 2.95.3 bugware (sic) */
5501                 status = opts[0] | len |
5502                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5503
5504                 txd->opts1 = cpu_to_le32(status);
5505                 txd->opts2 = cpu_to_le32(opts[1]);
5506                 txd->addr = cpu_to_le64(mapping);
5507
5508                 tp->tx_skb[entry].len = len;
5509         }
5510
5511         if (cur_frag) {
5512                 tp->tx_skb[entry].skb = skb;
5513                 txd->opts1 |= cpu_to_le32(LastFrag);
5514         }
5515
5516         return cur_frag;
5517
5518 err_out:
5519         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5520         return -EIO;
5521 }
5522
5523 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5524                                     struct sk_buff *skb, u32 *opts)
5525 {
5526         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5527         u32 mss = skb_shinfo(skb)->gso_size;
5528         int offset = info->opts_offset;
5529
5530         if (mss) {
5531                 opts[0] |= TD_LSO;
5532                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5533         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5534                 const struct iphdr *ip = ip_hdr(skb);
5535
5536                 if (ip->protocol == IPPROTO_TCP)
5537                         opts[offset] |= info->checksum.tcp;
5538                 else if (ip->protocol == IPPROTO_UDP)
5539                         opts[offset] |= info->checksum.udp;
5540                 else
5541                         WARN_ON_ONCE(1);
5542         }
5543 }
5544
5545 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5546                                       struct net_device *dev)
5547 {
5548         struct rtl8169_private *tp = netdev_priv(dev);
5549         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5550         struct TxDesc *txd = tp->TxDescArray + entry;
5551         void __iomem *ioaddr = tp->mmio_addr;
5552         struct device *d = &tp->pci_dev->dev;
5553         dma_addr_t mapping;
5554         u32 status, len;
5555         u32 opts[2];
5556         int frags;
5557
5558         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5559                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5560                 goto err_stop_0;
5561         }
5562
5563         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5564                 goto err_stop_0;
5565
5566         len = skb_headlen(skb);
5567         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5568         if (unlikely(dma_mapping_error(d, mapping))) {
5569                 if (net_ratelimit())
5570                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5571                 goto err_dma_0;
5572         }
5573
5574         tp->tx_skb[entry].len = len;
5575         txd->addr = cpu_to_le64(mapping);
5576
5577         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5578         opts[0] = DescOwn;
5579
5580         rtl8169_tso_csum(tp, skb, opts);
5581
5582         frags = rtl8169_xmit_frags(tp, skb, opts);
5583         if (frags < 0)
5584                 goto err_dma_1;
5585         else if (frags)
5586                 opts[0] |= FirstFrag;
5587         else {
5588                 opts[0] |= FirstFrag | LastFrag;
5589                 tp->tx_skb[entry].skb = skb;
5590         }
5591
5592         txd->opts2 = cpu_to_le32(opts[1]);
5593
5594         netdev_sent_queue(dev, skb->len);
5595
5596         skb_tx_timestamp(skb);
5597
5598         wmb();
5599
5600         /* Anti gcc 2.95.3 bugware (sic) */
5601         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5602         txd->opts1 = cpu_to_le32(status);
5603
5604         tp->cur_tx += frags + 1;
5605
5606         wmb();
5607
5608         RTL_W8(TxPoll, NPQ);
5609
5610         mmiowb();
5611
5612         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5613                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5614                  * not miss a ring update when it notices a stopped queue.
5615                  */
5616                 smp_wmb();
5617                 netif_stop_queue(dev);
5618                 /* Sync with rtl_tx:
5619                  * - publish queue status and cur_tx ring index (write barrier)
5620                  * - refresh dirty_tx ring index (read barrier).
5621                  * May the current thread have a pessimistic view of the ring
5622                  * status and forget to wake up queue, a racing rtl_tx thread
5623                  * can't.
5624                  */
5625                 smp_mb();
5626                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5627                         netif_wake_queue(dev);
5628         }
5629
5630         return NETDEV_TX_OK;
5631
5632 err_dma_1:
5633         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5634 err_dma_0:
5635         dev_kfree_skb(skb);
5636         dev->stats.tx_dropped++;
5637         return NETDEV_TX_OK;
5638
5639 err_stop_0:
5640         netif_stop_queue(dev);
5641         dev->stats.tx_dropped++;
5642         return NETDEV_TX_BUSY;
5643 }
5644
5645 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5646 {
5647         struct rtl8169_private *tp = netdev_priv(dev);
5648         struct pci_dev *pdev = tp->pci_dev;
5649         u16 pci_status, pci_cmd;
5650
5651         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5652         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5653
5654         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5655                   pci_cmd, pci_status);
5656
5657         /*
5658          * The recovery sequence below admits a very elaborated explanation:
5659          * - it seems to work;
5660          * - I did not see what else could be done;
5661          * - it makes iop3xx happy.
5662          *
5663          * Feel free to adjust to your needs.
5664          */
5665         if (pdev->broken_parity_status)
5666                 pci_cmd &= ~PCI_COMMAND_PARITY;
5667         else
5668                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5669
5670         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5671
5672         pci_write_config_word(pdev, PCI_STATUS,
5673                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5674                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5675                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5676
5677         /* The infamous DAC f*ckup only happens at boot time */
5678         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5679                 void __iomem *ioaddr = tp->mmio_addr;
5680
5681                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5682                 tp->cp_cmd &= ~PCIDAC;
5683                 RTL_W16(CPlusCmd, tp->cp_cmd);
5684                 dev->features &= ~NETIF_F_HIGHDMA;
5685         }
5686
5687         rtl8169_hw_reset(tp);
5688
5689         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5690 }
5691
5692 struct rtl_txc {
5693         int packets;
5694         int bytes;
5695 };
5696
5697 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5698 {
5699         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5700         unsigned int dirty_tx, tx_left;
5701         struct rtl_txc txc = { 0, 0 };
5702
5703         dirty_tx = tp->dirty_tx;
5704         smp_rmb();
5705         tx_left = tp->cur_tx - dirty_tx;
5706
5707         while (tx_left > 0) {
5708                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5709                 struct ring_info *tx_skb = tp->tx_skb + entry;
5710                 u32 status;
5711
5712                 rmb();
5713                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5714                 if (status & DescOwn)
5715                         break;
5716
5717                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5718                                      tp->TxDescArray + entry);
5719                 if (status & LastFrag) {
5720                         struct sk_buff *skb = tx_skb->skb;
5721
5722                         txc.packets++;
5723                         txc.bytes += skb->len;
5724                         dev_kfree_skb(skb);
5725                         tx_skb->skb = NULL;
5726                 }
5727                 dirty_tx++;
5728                 tx_left--;
5729         }
5730
5731         u64_stats_update_begin(&tx_stats->syncp);
5732         tx_stats->packets += txc.packets;
5733         tx_stats->bytes += txc.bytes;
5734         u64_stats_update_end(&tx_stats->syncp);
5735
5736         netdev_completed_queue(dev, txc.packets, txc.bytes);
5737
5738         if (tp->dirty_tx != dirty_tx) {
5739                 tp->dirty_tx = dirty_tx;
5740                 /* Sync with rtl8169_start_xmit:
5741                  * - publish dirty_tx ring index (write barrier)
5742                  * - refresh cur_tx ring index and queue status (read barrier)
5743                  * May the current thread miss the stopped queue condition,
5744                  * a racing xmit thread can only have a right view of the
5745                  * ring status.
5746                  */
5747                 smp_mb();
5748                 if (netif_queue_stopped(dev) &&
5749                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5750                         netif_wake_queue(dev);
5751                 }
5752                 /*
5753                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5754                  * too close. Let's kick an extra TxPoll request when a burst
5755                  * of start_xmit activity is detected (if it is not detected,
5756                  * it is slow enough). -- FR
5757                  */
5758                 if (tp->cur_tx != dirty_tx) {
5759                         void __iomem *ioaddr = tp->mmio_addr;
5760
5761                         RTL_W8(TxPoll, NPQ);
5762                 }
5763         }
5764 }
5765
5766 static inline int rtl8169_fragmented_frame(u32 status)
5767 {
5768         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5769 }
5770
5771 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5772 {
5773         u32 status = opts1 & RxProtoMask;
5774
5775         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5776             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5777                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5778         else
5779                 skb_checksum_none_assert(skb);
5780 }
5781
5782 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5783                                            struct rtl8169_private *tp,
5784                                            int pkt_size,
5785                                            dma_addr_t addr)
5786 {
5787         struct sk_buff *skb;
5788         struct device *d = &tp->pci_dev->dev;
5789
5790         data = rtl8169_align(data);
5791         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5792         prefetch(data);
5793         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5794         if (skb)
5795                 memcpy(skb->data, data, pkt_size);
5796         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5797
5798         return skb;
5799 }
5800
5801 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5802 {
5803         unsigned int cur_rx, rx_left;
5804         unsigned int count;
5805
5806         cur_rx = tp->cur_rx;
5807         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5808         rx_left = min(rx_left, budget);
5809
5810         for (; rx_left > 0; rx_left--, cur_rx++) {
5811                 unsigned int entry = cur_rx % NUM_RX_DESC;
5812                 struct RxDesc *desc = tp->RxDescArray + entry;
5813                 u32 status;
5814
5815                 rmb();
5816                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5817
5818                 if (status & DescOwn)
5819                         break;
5820                 if (unlikely(status & RxRES)) {
5821                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5822                                    status);
5823                         dev->stats.rx_errors++;
5824                         if (status & (RxRWT | RxRUNT))
5825                                 dev->stats.rx_length_errors++;
5826                         if (status & RxCRC)
5827                                 dev->stats.rx_crc_errors++;
5828                         if (status & RxFOVF) {
5829                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5830                                 dev->stats.rx_fifo_errors++;
5831                         }
5832                         if ((status & (RxRUNT | RxCRC)) &&
5833                             !(status & (RxRWT | RxFOVF)) &&
5834                             (dev->features & NETIF_F_RXALL))
5835                                 goto process_pkt;
5836
5837                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5838                 } else {
5839                         struct sk_buff *skb;
5840                         dma_addr_t addr;
5841                         int pkt_size;
5842
5843 process_pkt:
5844                         addr = le64_to_cpu(desc->addr);
5845                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5846                                 pkt_size = (status & 0x00003fff) - 4;
5847                         else
5848                                 pkt_size = status & 0x00003fff;
5849
5850                         /*
5851                          * The driver does not support incoming fragmented
5852                          * frames. They are seen as a symptom of over-mtu
5853                          * sized frames.
5854                          */
5855                         if (unlikely(rtl8169_fragmented_frame(status))) {
5856                                 dev->stats.rx_dropped++;
5857                                 dev->stats.rx_length_errors++;
5858                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5859                                 continue;
5860                         }
5861
5862                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5863                                                   tp, pkt_size, addr);
5864                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5865                         if (!skb) {
5866                                 dev->stats.rx_dropped++;
5867                                 continue;
5868                         }
5869
5870                         rtl8169_rx_csum(skb, status);
5871                         skb_put(skb, pkt_size);
5872                         skb->protocol = eth_type_trans(skb, dev);
5873
5874                         rtl8169_rx_vlan_tag(desc, skb);
5875
5876                         napi_gro_receive(&tp->napi, skb);
5877
5878                         u64_stats_update_begin(&tp->rx_stats.syncp);
5879                         tp->rx_stats.packets++;
5880                         tp->rx_stats.bytes += pkt_size;
5881                         u64_stats_update_end(&tp->rx_stats.syncp);
5882                 }
5883
5884                 /* Work around for AMD plateform. */
5885                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5886                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5887                         desc->opts2 = 0;
5888                         cur_rx++;
5889                 }
5890         }
5891
5892         count = cur_rx - tp->cur_rx;
5893         tp->cur_rx = cur_rx;
5894
5895         tp->dirty_rx += count;
5896
5897         return count;
5898 }
5899
5900 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5901 {
5902         struct net_device *dev = dev_instance;
5903         struct rtl8169_private *tp = netdev_priv(dev);
5904         int handled = 0;
5905         u16 status;
5906
5907         status = rtl_get_events(tp);
5908         if (status && status != 0xffff) {
5909                 status &= RTL_EVENT_NAPI | tp->event_slow;
5910                 if (status) {
5911                         handled = 1;
5912
5913                         rtl_irq_disable(tp);
5914                         napi_schedule(&tp->napi);
5915                 }
5916         }
5917         return IRQ_RETVAL(handled);
5918 }
5919
5920 /*
5921  * Workqueue context.
5922  */
5923 static void rtl_slow_event_work(struct rtl8169_private *tp)
5924 {
5925         struct net_device *dev = tp->dev;
5926         u16 status;
5927
5928         status = rtl_get_events(tp) & tp->event_slow;
5929         rtl_ack_events(tp, status);
5930
5931         if (unlikely(status & RxFIFOOver)) {
5932                 switch (tp->mac_version) {
5933                 /* Work around for rx fifo overflow */
5934                 case RTL_GIGA_MAC_VER_11:
5935                         netif_stop_queue(dev);
5936                         /* XXX - Hack alert. See rtl_task(). */
5937                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5938                 default:
5939                         break;
5940                 }
5941         }
5942
5943         if (unlikely(status & SYSErr))
5944                 rtl8169_pcierr_interrupt(dev);
5945
5946         if (status & LinkChg)
5947                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5948
5949         rtl_irq_enable_all(tp);
5950 }
5951
5952 static void rtl_task(struct work_struct *work)
5953 {
5954         static const struct {
5955                 int bitnr;
5956                 void (*action)(struct rtl8169_private *);
5957         } rtl_work[] = {
5958                 /* XXX - keep rtl_slow_event_work() as first element. */
5959                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5960                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5961                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5962         };
5963         struct rtl8169_private *tp =
5964                 container_of(work, struct rtl8169_private, wk.work);
5965         struct net_device *dev = tp->dev;
5966         int i;
5967
5968         rtl_lock_work(tp);
5969
5970         if (!netif_running(dev) ||
5971             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5972                 goto out_unlock;
5973
5974         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5975                 bool pending;
5976
5977                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5978                 if (pending)
5979                         rtl_work[i].action(tp);
5980         }
5981
5982 out_unlock:
5983         rtl_unlock_work(tp);
5984 }
5985
5986 static int rtl8169_poll(struct napi_struct *napi, int budget)
5987 {
5988         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5989         struct net_device *dev = tp->dev;
5990         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5991         int work_done= 0;
5992         u16 status;
5993
5994         status = rtl_get_events(tp);
5995         rtl_ack_events(tp, status & ~tp->event_slow);
5996
5997         if (status & RTL_EVENT_NAPI_RX)
5998                 work_done = rtl_rx(dev, tp, (u32) budget);
5999
6000         if (status & RTL_EVENT_NAPI_TX)
6001                 rtl_tx(dev, tp);
6002
6003         if (status & tp->event_slow) {
6004                 enable_mask &= ~tp->event_slow;
6005
6006                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6007         }
6008
6009         if (work_done < budget) {
6010                 napi_complete(napi);
6011
6012                 rtl_irq_enable(tp, enable_mask);
6013                 mmiowb();
6014         }
6015
6016         return work_done;
6017 }
6018
6019 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6020 {
6021         struct rtl8169_private *tp = netdev_priv(dev);
6022
6023         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6024                 return;
6025
6026         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6027         RTL_W32(RxMissed, 0);
6028 }
6029
6030 static void rtl8169_down(struct net_device *dev)
6031 {
6032         struct rtl8169_private *tp = netdev_priv(dev);
6033         void __iomem *ioaddr = tp->mmio_addr;
6034
6035         del_timer_sync(&tp->timer);
6036
6037         napi_disable(&tp->napi);
6038         netif_stop_queue(dev);
6039
6040         rtl8169_hw_reset(tp);
6041         /*
6042          * At this point device interrupts can not be enabled in any function,
6043          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6044          * and napi is disabled (rtl8169_poll).
6045          */
6046         rtl8169_rx_missed(dev, ioaddr);
6047
6048         /* Give a racing hard_start_xmit a few cycles to complete. */
6049         synchronize_sched();
6050
6051         rtl8169_tx_clear(tp);
6052
6053         rtl8169_rx_clear(tp);
6054
6055         rtl_pll_power_down(tp);
6056 }
6057
6058 static int rtl8169_close(struct net_device *dev)
6059 {
6060         struct rtl8169_private *tp = netdev_priv(dev);
6061         struct pci_dev *pdev = tp->pci_dev;
6062
6063         pm_runtime_get_sync(&pdev->dev);
6064
6065         /* Update counters before going down */
6066         rtl8169_update_counters(dev);
6067
6068         rtl_lock_work(tp);
6069         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6070
6071         rtl8169_down(dev);
6072         rtl_unlock_work(tp);
6073
6074         free_irq(pdev->irq, dev);
6075
6076         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6077                           tp->RxPhyAddr);
6078         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6079                           tp->TxPhyAddr);
6080         tp->TxDescArray = NULL;
6081         tp->RxDescArray = NULL;
6082
6083         pm_runtime_put_sync(&pdev->dev);
6084
6085         return 0;
6086 }
6087
6088 #ifdef CONFIG_NET_POLL_CONTROLLER
6089 static void rtl8169_netpoll(struct net_device *dev)
6090 {
6091         struct rtl8169_private *tp = netdev_priv(dev);
6092
6093         rtl8169_interrupt(tp->pci_dev->irq, dev);
6094 }
6095 #endif
6096
6097 static int rtl_open(struct net_device *dev)
6098 {
6099         struct rtl8169_private *tp = netdev_priv(dev);
6100         void __iomem *ioaddr = tp->mmio_addr;
6101         struct pci_dev *pdev = tp->pci_dev;
6102         int retval = -ENOMEM;
6103
6104         pm_runtime_get_sync(&pdev->dev);
6105
6106         /*
6107          * Rx and Tx descriptors needs 256 bytes alignment.
6108          * dma_alloc_coherent provides more.
6109          */
6110         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6111                                              &tp->TxPhyAddr, GFP_KERNEL);
6112         if (!tp->TxDescArray)
6113                 goto err_pm_runtime_put;
6114
6115         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6116                                              &tp->RxPhyAddr, GFP_KERNEL);
6117         if (!tp->RxDescArray)
6118                 goto err_free_tx_0;
6119
6120         retval = rtl8169_init_ring(dev);
6121         if (retval < 0)
6122                 goto err_free_rx_1;
6123
6124         INIT_WORK(&tp->wk.work, rtl_task);
6125
6126         smp_mb();
6127
6128         rtl_request_firmware(tp);
6129
6130         retval = request_irq(pdev->irq, rtl8169_interrupt,
6131                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6132                              dev->name, dev);
6133         if (retval < 0)
6134                 goto err_release_fw_2;
6135
6136         rtl_lock_work(tp);
6137
6138         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6139
6140         napi_enable(&tp->napi);
6141
6142         rtl8169_init_phy(dev, tp);
6143
6144         __rtl8169_set_features(dev, dev->features);
6145
6146         rtl_pll_power_up(tp);
6147
6148         rtl_hw_start(dev);
6149
6150         netif_start_queue(dev);
6151
6152         rtl_unlock_work(tp);
6153
6154         tp->saved_wolopts = 0;
6155         pm_runtime_put_noidle(&pdev->dev);
6156
6157         rtl8169_check_link_status(dev, tp, ioaddr);
6158 out:
6159         return retval;
6160
6161 err_release_fw_2:
6162         rtl_release_firmware(tp);
6163         rtl8169_rx_clear(tp);
6164 err_free_rx_1:
6165         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6166                           tp->RxPhyAddr);
6167         tp->RxDescArray = NULL;
6168 err_free_tx_0:
6169         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6170                           tp->TxPhyAddr);
6171         tp->TxDescArray = NULL;
6172 err_pm_runtime_put:
6173         pm_runtime_put_noidle(&pdev->dev);
6174         goto out;
6175 }
6176
6177 static struct rtnl_link_stats64 *
6178 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6179 {
6180         struct rtl8169_private *tp = netdev_priv(dev);
6181         void __iomem *ioaddr = tp->mmio_addr;
6182         unsigned int start;
6183
6184         if (netif_running(dev))
6185                 rtl8169_rx_missed(dev, ioaddr);
6186
6187         do {
6188                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6189                 stats->rx_packets = tp->rx_stats.packets;
6190                 stats->rx_bytes = tp->rx_stats.bytes;
6191         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6192
6193
6194         do {
6195                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6196                 stats->tx_packets = tp->tx_stats.packets;
6197                 stats->tx_bytes = tp->tx_stats.bytes;
6198         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6199
6200         stats->rx_dropped       = dev->stats.rx_dropped;
6201         stats->tx_dropped       = dev->stats.tx_dropped;
6202         stats->rx_length_errors = dev->stats.rx_length_errors;
6203         stats->rx_errors        = dev->stats.rx_errors;
6204         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6205         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6206         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6207
6208         return stats;
6209 }
6210
6211 static void rtl8169_net_suspend(struct net_device *dev)
6212 {
6213         struct rtl8169_private *tp = netdev_priv(dev);
6214
6215         if (!netif_running(dev))
6216                 return;
6217
6218         netif_device_detach(dev);
6219         netif_stop_queue(dev);
6220
6221         rtl_lock_work(tp);
6222         napi_disable(&tp->napi);
6223         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6224         rtl_unlock_work(tp);
6225
6226         rtl_pll_power_down(tp);
6227 }
6228
6229 #ifdef CONFIG_PM
6230
6231 static int rtl8169_suspend(struct device *device)
6232 {
6233         struct pci_dev *pdev = to_pci_dev(device);
6234         struct net_device *dev = pci_get_drvdata(pdev);
6235
6236         rtl8169_net_suspend(dev);
6237
6238         return 0;
6239 }
6240
6241 static void __rtl8169_resume(struct net_device *dev)
6242 {
6243         struct rtl8169_private *tp = netdev_priv(dev);
6244
6245         netif_device_attach(dev);
6246
6247         rtl_pll_power_up(tp);
6248
6249         rtl_lock_work(tp);
6250         napi_enable(&tp->napi);
6251         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6252         rtl_unlock_work(tp);
6253
6254         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6255 }
6256
6257 static int rtl8169_resume(struct device *device)
6258 {
6259         struct pci_dev *pdev = to_pci_dev(device);
6260         struct net_device *dev = pci_get_drvdata(pdev);
6261         struct rtl8169_private *tp = netdev_priv(dev);
6262
6263         rtl8169_init_phy(dev, tp);
6264
6265         if (netif_running(dev))
6266                 __rtl8169_resume(dev);
6267
6268         return 0;
6269 }
6270
6271 static int rtl8169_runtime_suspend(struct device *device)
6272 {
6273         struct pci_dev *pdev = to_pci_dev(device);
6274         struct net_device *dev = pci_get_drvdata(pdev);
6275         struct rtl8169_private *tp = netdev_priv(dev);
6276
6277         if (!tp->TxDescArray)
6278                 return 0;
6279
6280         rtl_lock_work(tp);
6281         tp->saved_wolopts = __rtl8169_get_wol(tp);
6282         __rtl8169_set_wol(tp, WAKE_ANY);
6283         rtl_unlock_work(tp);
6284
6285         rtl8169_net_suspend(dev);
6286
6287         return 0;
6288 }
6289
6290 static int rtl8169_runtime_resume(struct device *device)
6291 {
6292         struct pci_dev *pdev = to_pci_dev(device);
6293         struct net_device *dev = pci_get_drvdata(pdev);
6294         struct rtl8169_private *tp = netdev_priv(dev);
6295
6296         if (!tp->TxDescArray)
6297                 return 0;
6298
6299         rtl_lock_work(tp);
6300         __rtl8169_set_wol(tp, tp->saved_wolopts);
6301         tp->saved_wolopts = 0;
6302         rtl_unlock_work(tp);
6303
6304         rtl8169_init_phy(dev, tp);
6305
6306         __rtl8169_resume(dev);
6307
6308         return 0;
6309 }
6310
6311 static int rtl8169_runtime_idle(struct device *device)
6312 {
6313         struct pci_dev *pdev = to_pci_dev(device);
6314         struct net_device *dev = pci_get_drvdata(pdev);
6315         struct rtl8169_private *tp = netdev_priv(dev);
6316
6317         return tp->TxDescArray ? -EBUSY : 0;
6318 }
6319
6320 static const struct dev_pm_ops rtl8169_pm_ops = {
6321         .suspend                = rtl8169_suspend,
6322         .resume                 = rtl8169_resume,
6323         .freeze                 = rtl8169_suspend,
6324         .thaw                   = rtl8169_resume,
6325         .poweroff               = rtl8169_suspend,
6326         .restore                = rtl8169_resume,
6327         .runtime_suspend        = rtl8169_runtime_suspend,
6328         .runtime_resume         = rtl8169_runtime_resume,
6329         .runtime_idle           = rtl8169_runtime_idle,
6330 };
6331
6332 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6333
6334 #else /* !CONFIG_PM */
6335
6336 #define RTL8169_PM_OPS  NULL
6337
6338 #endif /* !CONFIG_PM */
6339
6340 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6341 {
6342         void __iomem *ioaddr = tp->mmio_addr;
6343
6344         /* WoL fails with 8168b when the receiver is disabled. */
6345         switch (tp->mac_version) {
6346         case RTL_GIGA_MAC_VER_11:
6347         case RTL_GIGA_MAC_VER_12:
6348         case RTL_GIGA_MAC_VER_17:
6349                 pci_clear_master(tp->pci_dev);
6350
6351                 RTL_W8(ChipCmd, CmdRxEnb);
6352                 /* PCI commit */
6353                 RTL_R8(ChipCmd);
6354                 break;
6355         default:
6356                 break;
6357         }
6358 }
6359
6360 static void rtl_shutdown(struct pci_dev *pdev)
6361 {
6362         struct net_device *dev = pci_get_drvdata(pdev);
6363         struct rtl8169_private *tp = netdev_priv(dev);
6364         struct device *d = &pdev->dev;
6365
6366         pm_runtime_get_sync(d);
6367
6368         rtl8169_net_suspend(dev);
6369
6370         /* Restore original MAC address */
6371         rtl_rar_set(tp, dev->perm_addr);
6372
6373         rtl8169_hw_reset(tp);
6374
6375         if (system_state == SYSTEM_POWER_OFF) {
6376                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6377                         rtl_wol_suspend_quirk(tp);
6378                         rtl_wol_shutdown_quirk(tp);
6379                 }
6380
6381                 pci_wake_from_d3(pdev, true);
6382                 pci_set_power_state(pdev, PCI_D3hot);
6383         }
6384
6385         pm_runtime_put_noidle(d);
6386 }
6387
6388 static void __devexit rtl_remove_one(struct pci_dev *pdev)
6389 {
6390         struct net_device *dev = pci_get_drvdata(pdev);
6391         struct rtl8169_private *tp = netdev_priv(dev);
6392
6393         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6394             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6395             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6396                 rtl8168_driver_stop(tp);
6397         }
6398
6399         cancel_work_sync(&tp->wk.work);
6400
6401         netif_napi_del(&tp->napi);
6402
6403         unregister_netdev(dev);
6404
6405         rtl_release_firmware(tp);
6406
6407         if (pci_dev_run_wake(pdev))
6408                 pm_runtime_get_noresume(&pdev->dev);
6409
6410         /* restore original MAC address */
6411         rtl_rar_set(tp, dev->perm_addr);
6412
6413         rtl_disable_msi(pdev, tp);
6414         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6415         pci_set_drvdata(pdev, NULL);
6416 }
6417
6418 static const struct net_device_ops rtl_netdev_ops = {
6419         .ndo_open               = rtl_open,
6420         .ndo_stop               = rtl8169_close,
6421         .ndo_get_stats64        = rtl8169_get_stats64,
6422         .ndo_start_xmit         = rtl8169_start_xmit,
6423         .ndo_tx_timeout         = rtl8169_tx_timeout,
6424         .ndo_validate_addr      = eth_validate_addr,
6425         .ndo_change_mtu         = rtl8169_change_mtu,
6426         .ndo_fix_features       = rtl8169_fix_features,
6427         .ndo_set_features       = rtl8169_set_features,
6428         .ndo_set_mac_address    = rtl_set_mac_address,
6429         .ndo_do_ioctl           = rtl8169_ioctl,
6430         .ndo_set_rx_mode        = rtl_set_rx_mode,
6431 #ifdef CONFIG_NET_POLL_CONTROLLER
6432         .ndo_poll_controller    = rtl8169_netpoll,
6433 #endif
6434
6435 };
6436
6437 static const struct rtl_cfg_info {
6438         void (*hw_start)(struct net_device *);
6439         unsigned int region;
6440         unsigned int align;
6441         u16 event_slow;
6442         unsigned features;
6443         u8 default_ver;
6444 } rtl_cfg_infos [] = {
6445         [RTL_CFG_0] = {
6446                 .hw_start       = rtl_hw_start_8169,
6447                 .region         = 1,
6448                 .align          = 0,
6449                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6450                 .features       = RTL_FEATURE_GMII,
6451                 .default_ver    = RTL_GIGA_MAC_VER_01,
6452         },
6453         [RTL_CFG_1] = {
6454                 .hw_start       = rtl_hw_start_8168,
6455                 .region         = 2,
6456                 .align          = 8,
6457                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6458                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6459                 .default_ver    = RTL_GIGA_MAC_VER_11,
6460         },
6461         [RTL_CFG_2] = {
6462                 .hw_start       = rtl_hw_start_8101,
6463                 .region         = 2,
6464                 .align          = 8,
6465                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6466                                   PCSTimeout,
6467                 .features       = RTL_FEATURE_MSI,
6468                 .default_ver    = RTL_GIGA_MAC_VER_13,
6469         }
6470 };
6471
6472 /* Cfg9346_Unlock assumed. */
6473 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6474                             const struct rtl_cfg_info *cfg)
6475 {
6476         void __iomem *ioaddr = tp->mmio_addr;
6477         unsigned msi = 0;
6478         u8 cfg2;
6479
6480         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6481         if (cfg->features & RTL_FEATURE_MSI) {
6482                 if (pci_enable_msi(tp->pci_dev)) {
6483                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6484                 } else {
6485                         cfg2 |= MSIEnable;
6486                         msi = RTL_FEATURE_MSI;
6487                 }
6488         }
6489         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6490                 RTL_W8(Config2, cfg2);
6491         return msi;
6492 }
6493
6494 static int __devinit
6495 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6496 {
6497         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6498         const unsigned int region = cfg->region;
6499         struct rtl8169_private *tp;
6500         struct mii_if_info *mii;
6501         struct net_device *dev;
6502         void __iomem *ioaddr;
6503         int chipset, i;
6504         int rc;
6505
6506         if (netif_msg_drv(&debug)) {
6507                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6508                        MODULENAME, RTL8169_VERSION);
6509         }
6510
6511         dev = alloc_etherdev(sizeof (*tp));
6512         if (!dev) {
6513                 rc = -ENOMEM;
6514                 goto out;
6515         }
6516
6517         SET_NETDEV_DEV(dev, &pdev->dev);
6518         dev->netdev_ops = &rtl_netdev_ops;
6519         tp = netdev_priv(dev);
6520         tp->dev = dev;
6521         tp->pci_dev = pdev;
6522         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6523
6524         mii = &tp->mii;
6525         mii->dev = dev;
6526         mii->mdio_read = rtl_mdio_read;
6527         mii->mdio_write = rtl_mdio_write;
6528         mii->phy_id_mask = 0x1f;
6529         mii->reg_num_mask = 0x1f;
6530         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6531
6532         /* disable ASPM completely as that cause random device stop working
6533          * problems as well as full system hangs for some PCIe devices users */
6534         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6535                                      PCIE_LINK_STATE_CLKPM);
6536
6537         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6538         rc = pci_enable_device(pdev);
6539         if (rc < 0) {
6540                 netif_err(tp, probe, dev, "enable failure\n");
6541                 goto err_out_free_dev_1;
6542         }
6543
6544         if (pci_set_mwi(pdev) < 0)
6545                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6546
6547         /* make sure PCI base addr 1 is MMIO */
6548         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6549                 netif_err(tp, probe, dev,
6550                           "region #%d not an MMIO resource, aborting\n",
6551                           region);
6552                 rc = -ENODEV;
6553                 goto err_out_mwi_2;
6554         }
6555
6556         /* check for weird/broken PCI region reporting */
6557         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6558                 netif_err(tp, probe, dev,
6559                           "Invalid PCI region size(s), aborting\n");
6560                 rc = -ENODEV;
6561                 goto err_out_mwi_2;
6562         }
6563
6564         rc = pci_request_regions(pdev, MODULENAME);
6565         if (rc < 0) {
6566                 netif_err(tp, probe, dev, "could not request regions\n");
6567                 goto err_out_mwi_2;
6568         }
6569
6570         tp->cp_cmd = RxChkSum;
6571
6572         if ((sizeof(dma_addr_t) > 4) &&
6573             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6574                 tp->cp_cmd |= PCIDAC;
6575                 dev->features |= NETIF_F_HIGHDMA;
6576         } else {
6577                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6578                 if (rc < 0) {
6579                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6580                         goto err_out_free_res_3;
6581                 }
6582         }
6583
6584         /* ioremap MMIO region */
6585         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6586         if (!ioaddr) {
6587                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6588                 rc = -EIO;
6589                 goto err_out_free_res_3;
6590         }
6591         tp->mmio_addr = ioaddr;
6592
6593         if (!pci_is_pcie(pdev))
6594                 netif_info(tp, probe, dev, "not PCI Express\n");
6595
6596         /* Identify chip attached to board */
6597         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6598
6599         rtl_init_rxcfg(tp);
6600
6601         rtl_irq_disable(tp);
6602
6603         rtl_hw_reset(tp);
6604
6605         rtl_ack_events(tp, 0xffff);
6606
6607         pci_set_master(pdev);
6608
6609         /*
6610          * Pretend we are using VLANs; This bypasses a nasty bug where
6611          * Interrupts stop flowing on high load on 8110SCd controllers.
6612          */
6613         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6614                 tp->cp_cmd |= RxVlan;
6615
6616         rtl_init_mdio_ops(tp);
6617         rtl_init_pll_power_ops(tp);
6618         rtl_init_jumbo_ops(tp);
6619         rtl_init_csi_ops(tp);
6620
6621         rtl8169_print_mac_version(tp);
6622
6623         chipset = tp->mac_version;
6624         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6625
6626         RTL_W8(Cfg9346, Cfg9346_Unlock);
6627         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6628         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6629         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6630                 tp->features |= RTL_FEATURE_WOL;
6631         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6632                 tp->features |= RTL_FEATURE_WOL;
6633         tp->features |= rtl_try_msi(tp, cfg);
6634         RTL_W8(Cfg9346, Cfg9346_Lock);
6635
6636         if (rtl_tbi_enabled(tp)) {
6637                 tp->set_speed = rtl8169_set_speed_tbi;
6638                 tp->get_settings = rtl8169_gset_tbi;
6639                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6640                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6641                 tp->link_ok = rtl8169_tbi_link_ok;
6642                 tp->do_ioctl = rtl_tbi_ioctl;
6643         } else {
6644                 tp->set_speed = rtl8169_set_speed_xmii;
6645                 tp->get_settings = rtl8169_gset_xmii;
6646                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6647                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6648                 tp->link_ok = rtl8169_xmii_link_ok;
6649                 tp->do_ioctl = rtl_xmii_ioctl;
6650         }
6651
6652         mutex_init(&tp->wk.mutex);
6653
6654         /* Get MAC address */
6655         for (i = 0; i < ETH_ALEN; i++)
6656                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6657         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6658
6659         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6660         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6661
6662         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6663
6664         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6665          * properly for all devices */
6666         dev->features |= NETIF_F_RXCSUM |
6667                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6668
6669         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6670                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6671         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6672                 NETIF_F_HIGHDMA;
6673
6674         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6675                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6676                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6677
6678         dev->hw_features |= NETIF_F_RXALL;
6679         dev->hw_features |= NETIF_F_RXFCS;
6680
6681         tp->hw_start = cfg->hw_start;
6682         tp->event_slow = cfg->event_slow;
6683
6684         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6685                 ~(RxBOVF | RxFOVF) : ~0;
6686
6687         init_timer(&tp->timer);
6688         tp->timer.data = (unsigned long) dev;
6689         tp->timer.function = rtl8169_phy_timer;
6690
6691         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6692
6693         rc = register_netdev(dev);
6694         if (rc < 0)
6695                 goto err_out_msi_4;
6696
6697         pci_set_drvdata(pdev, dev);
6698
6699         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6700                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6701                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6702         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6703                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6704                            "tx checksumming: %s]\n",
6705                            rtl_chip_infos[chipset].jumbo_max,
6706                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6707         }
6708
6709         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6710             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6711             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6712                 rtl8168_driver_start(tp);
6713         }
6714
6715         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6716
6717         if (pci_dev_run_wake(pdev))
6718                 pm_runtime_put_noidle(&pdev->dev);
6719
6720         netif_carrier_off(dev);
6721
6722 out:
6723         return rc;
6724
6725 err_out_msi_4:
6726         netif_napi_del(&tp->napi);
6727         rtl_disable_msi(pdev, tp);
6728         iounmap(ioaddr);
6729 err_out_free_res_3:
6730         pci_release_regions(pdev);
6731 err_out_mwi_2:
6732         pci_clear_mwi(pdev);
6733         pci_disable_device(pdev);
6734 err_out_free_dev_1:
6735         free_netdev(dev);
6736         goto out;
6737 }
6738
6739 static struct pci_driver rtl8169_pci_driver = {
6740         .name           = MODULENAME,
6741         .id_table       = rtl8169_pci_tbl,
6742         .probe          = rtl_init_one,
6743         .remove         = __devexit_p(rtl_remove_one),
6744         .shutdown       = rtl_shutdown,
6745         .driver.pm      = RTL8169_PM_OPS,
6746 };
6747
6748 static int __init rtl8169_init_module(void)
6749 {
6750         return pci_register_driver(&rtl8169_pci_driver);
6751 }
6752
6753 static void __exit rtl8169_cleanup_module(void)
6754 {
6755         pci_unregister_driver(&rtl8169_pci_driver);
6756 }
6757
6758 module_init(rtl8169_init_module);
6759 module_exit(rtl8169_cleanup_module);