drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  56         [EDSR]          = 0x0000,
  57         [EDMR]          = 0x0400,
  58         [EDTRR]         = 0x0408,
  59         [EDRRR]         = 0x0410,
  60         [EESR]          = 0x0428,
  61         [EESIPR]        = 0x0430,
  62         [TDLAR]         = 0x0010,
  63         [TDFAR]         = 0x0014,
  64         [TDFXR]         = 0x0018,
  65         [TDFFR]         = 0x001c,
  66         [RDLAR]         = 0x0030,
  67         [RDFAR]         = 0x0034,
  68         [RDFXR]         = 0x0038,
  69         [RDFFR]         = 0x003c,
  70         [TRSCER]        = 0x0438,
  71         [RMFCR]         = 0x0440,
  72         [TFTR]          = 0x0448,
  73         [FDR]           = 0x0450,
  74         [RMCR]          = 0x0458,
  75         [RPADIR]        = 0x0460,
  76         [FCFTR]         = 0x0468,
  77         [CSMR]          = 0x04E4,
  78
  79         [ECMR]          = 0x0500,
  80         [ECSR]          = 0x0510,
  81         [ECSIPR]        = 0x0518,
  82         [PIR]           = 0x0520,
  83         [PSR]           = 0x0528,
  84         [PIPR]          = 0x052c,
  85         [RFLR]          = 0x0508,
  86         [APR]           = 0x0554,
  87         [MPR]           = 0x0558,
  88         [PFTCR]         = 0x055c,
  89         [PFRCR]         = 0x0560,
  90         [TPAUSER]       = 0x0564,
  91         [GECMR]         = 0x05b0,
  92         [BCULR]         = 0x05b4,
  93         [MAHR]          = 0x05c0,
  94         [MALR]          = 0x05c8,
  95         [TROCR]         = 0x0700,
  96         [CDCR]          = 0x0708,
  97         [LCCR]          = 0x0710,
  98         [CEFCR]         = 0x0740,
  99         [FRECR]         = 0x0748,
 100         [TSFRCR]        = 0x0750,
 101         [TLFRCR]        = 0x0758,
 102         [RFCR]          = 0x0760,
 103         [CERCR]         = 0x0768,
 104         [CEECR]         = 0x0770,
 105         [MAFCR]         = 0x0778,
 106         [RMII_MII]      = 0x0790,
 107
 108         [ARSTR]         = 0x0000,
 109         [TSU_CTRST]     = 0x0004,
 110         [TSU_FWEN0]     = 0x0010,
 111         [TSU_FWEN1]     = 0x0014,
 112         [TSU_FCM]       = 0x0018,
 113         [TSU_BSYSL0]    = 0x0020,
 114         [TSU_BSYSL1]    = 0x0024,
 115         [TSU_PRISL0]    = 0x0028,
 116         [TSU_PRISL1]    = 0x002c,
 117         [TSU_FWSL0]     = 0x0030,
 118         [TSU_FWSL1]     = 0x0034,
 119         [TSU_FWSLC]     = 0x0038,
 120         [TSU_QTAG0]     = 0x0040,
 121         [TSU_QTAG1]     = 0x0044,
 122         [TSU_FWSR]      = 0x0050,
 123         [TSU_FWINMK]    = 0x0054,
 124         [TSU_ADQT0]     = 0x0048,
 125         [TSU_ADQT1]     = 0x004c,
 126         [TSU_VTAG0]     = 0x0058,
 127         [TSU_VTAG1]     = 0x005c,
 128         [TSU_ADSBSY]    = 0x0060,
 129         [TSU_TEN]       = 0x0064,
 130         [TSU_POST1]     = 0x0070,
 131         [TSU_POST2]     = 0x0074,
 132         [TSU_POST3]     = 0x0078,
 133         [TSU_POST4]     = 0x007c,
 134         [TSU_ADRH0]     = 0x0100,
 135         [TSU_ADRL0]     = 0x0104,
 136         [TSU_ADRH31]    = 0x01f8,
 137         [TSU_ADRL31]    = 0x01fc,
 138
 139         [TXNLCR0]       = 0x0080,
 140         [TXALCR0]       = 0x0084,
 141         [RXNLCR0]       = 0x0088,
 142         [RXALCR0]       = 0x008c,
 143         [FWNLCR0]       = 0x0090,
 144         [FWALCR0]       = 0x0094,
 145         [TXNLCR1]       = 0x00a0,
 146         [TXALCR1]       = 0x00a0,
 147         [RXNLCR1]       = 0x00a8,
 148         [RXALCR1]       = 0x00ac,
 149         [FWNLCR1]       = 0x00b0,
 150         [FWALCR1]       = 0x00b4,
 151 };
 152
 153 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 154         [EDSR]          = 0x0000,
 155         [EDMR]          = 0x0400,
 156         [EDTRR]         = 0x0408,
 157         [EDRRR]         = 0x0410,
 158         [EESR]          = 0x0428,
 159         [EESIPR]        = 0x0430,
 160         [TDLAR]         = 0x0010,
 161         [TDFAR]         = 0x0014,
 162         [TDFXR]         = 0x0018,
 163         [TDFFR]         = 0x001c,
 164         [RDLAR]         = 0x0030,
 165         [RDFAR]         = 0x0034,
 166         [RDFXR]         = 0x0038,
 167         [RDFFR]         = 0x003c,
 168         [TRSCER]        = 0x0438,
 169         [RMFCR]         = 0x0440,
 170         [TFTR]          = 0x0448,
 171         [FDR]           = 0x0450,
 172         [RMCR]          = 0x0458,
 173         [RPADIR]        = 0x0460,
 174         [FCFTR]         = 0x0468,
 175         [CSMR]          = 0x04E4,
 176
 177         [ECMR]          = 0x0500,
 178         [RFLR]          = 0x0508,
 179         [ECSR]          = 0x0510,
 180         [ECSIPR]        = 0x0518,
 181         [PIR]           = 0x0520,
 182         [APR]           = 0x0554,
 183         [MPR]           = 0x0558,
 184         [PFTCR]         = 0x055c,
 185         [PFRCR]         = 0x0560,
 186         [TPAUSER]       = 0x0564,
 187         [MAHR]          = 0x05c0,
 188         [MALR]          = 0x05c8,
 189         [CEFCR]         = 0x0740,
 190         [FRECR]         = 0x0748,
 191         [TSFRCR]        = 0x0750,
 192         [TLFRCR]        = 0x0758,
 193         [RFCR]          = 0x0760,
 194         [MAFCR]         = 0x0778,
 195
 196         [ARSTR]         = 0x0000,
 197         [TSU_CTRST]     = 0x0004,
 198         [TSU_VTAG0]     = 0x0058,
 199         [TSU_ADSBSY]    = 0x0060,
 200         [TSU_TEN]       = 0x0064,
 201         [TSU_ADRH0]     = 0x0100,
 202         [TSU_ADRL0]     = 0x0104,
 203         [TSU_ADRH31]    = 0x01f8,
 204         [TSU_ADRL31]    = 0x01fc,
 205
 206         [TXNLCR0]       = 0x0080,
 207         [TXALCR0]       = 0x0084,
 208         [RXNLCR0]       = 0x0088,
 209         [RXALCR0]       = 0x008C,
 210 };
 211
 212 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 213         [ECMR]          = 0x0300,
 214         [RFLR]          = 0x0308,
 215         [ECSR]          = 0x0310,
 216         [ECSIPR]        = 0x0318,
 217         [PIR]           = 0x0320,
 218         [PSR]           = 0x0328,
 219         [RDMLR]         = 0x0340,
 220         [IPGR]          = 0x0350,
 221         [APR]           = 0x0354,
 222         [MPR]           = 0x0358,
 223         [RFCF]          = 0x0360,
 224         [TPAUSER]       = 0x0364,
 225         [TPAUSECR]      = 0x0368,
 226         [MAHR]          = 0x03c0,
 227         [MALR]          = 0x03c8,
 228         [TROCR]         = 0x03d0,
 229         [CDCR]          = 0x03d4,
 230         [LCCR]          = 0x03d8,
 231         [CNDCR]         = 0x03dc,
 232         [CEFCR]         = 0x03e4,
 233         [FRECR]         = 0x03e8,
 234         [TSFRCR]        = 0x03ec,
 235         [TLFRCR]        = 0x03f0,
 236         [RFCR]          = 0x03f4,
 237         [MAFCR]         = 0x03f8,
 238
 239         [EDMR]          = 0x0200,
 240         [EDTRR]         = 0x0208,
 241         [EDRRR]         = 0x0210,
 242         [TDLAR]         = 0x0218,
 243         [RDLAR]         = 0x0220,
 244         [EESR]          = 0x0228,
 245         [EESIPR]        = 0x0230,
 246         [TRSCER]        = 0x0238,
 247         [RMFCR]         = 0x0240,
 248         [TFTR]          = 0x0248,
 249         [FDR]           = 0x0250,
 250         [RMCR]          = 0x0258,
 251         [TFUCR]         = 0x0264,
 252         [RFOCR]         = 0x0268,
 253         [RMIIMODE]      = 0x026c,
 254         [FCFTR]         = 0x0270,
 255         [TRIMD]         = 0x027c,
 256 };
 257
 258 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 259         [ECMR]          = 0x0100,
 260         [RFLR]          = 0x0108,
 261         [ECSR]          = 0x0110,
 262         [ECSIPR]        = 0x0118,
 263         [PIR]           = 0x0120,
 264         [PSR]           = 0x0128,
 265         [RDMLR]         = 0x0140,
 266         [IPGR]          = 0x0150,
 267         [APR]           = 0x0154,
 268         [MPR]           = 0x0158,
 269         [TPAUSER]       = 0x0164,
 270         [RFCF]          = 0x0160,
 271         [TPAUSECR]      = 0x0168,
 272         [BCFRR]         = 0x016c,
 273         [MAHR]          = 0x01c0,
 274         [MALR]          = 0x01c8,
 275         [TROCR]         = 0x01d0,
 276         [CDCR]          = 0x01d4,
 277         [LCCR]          = 0x01d8,
 278         [CNDCR]         = 0x01dc,
 279         [CEFCR]         = 0x01e4,
 280         [FRECR]         = 0x01e8,
 281         [TSFRCR]        = 0x01ec,
 282         [TLFRCR]        = 0x01f0,
 283         [RFCR]          = 0x01f4,
 284         [MAFCR]         = 0x01f8,
 285         [RTRATE]        = 0x01fc,
 286
 287         [EDMR]          = 0x0000,
 288         [EDTRR]         = 0x0008,
 289         [EDRRR]         = 0x0010,
 290         [TDLAR]         = 0x0018,
 291         [RDLAR]         = 0x0020,
 292         [EESR]          = 0x0028,
 293         [EESIPR]        = 0x0030,
 294         [TRSCER]        = 0x0038,
 295         [RMFCR]         = 0x0040,
 296         [TFTR]          = 0x0048,
 297         [FDR]           = 0x0050,
 298         [RMCR]          = 0x0058,
 299         [TFUCR]         = 0x0064,
 300         [RFOCR]         = 0x0068,
 301         [FCFTR]         = 0x0070,
 302         [RPADIR]        = 0x0078,
 303         [TRIMD]         = 0x007c,
 304         [RBWAR]         = 0x00c8,
 305         [RDFAR]         = 0x00cc,
 306         [TBRAR]         = 0x00d4,
 307         [TDFAR]         = 0x00d8,
 308 };
 309
 310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 311         [EDMR]          = 0x0000,
 312         [EDTRR]         = 0x0004,
 313         [EDRRR]         = 0x0008,
 314         [TDLAR]         = 0x000c,
 315         [RDLAR]         = 0x0010,
 316         [EESR]          = 0x0014,
 317         [EESIPR]        = 0x0018,
 318         [TRSCER]        = 0x001c,
 319         [RMFCR]         = 0x0020,
 320         [TFTR]          = 0x0024,
 321         [FDR]           = 0x0028,
 322         [RMCR]          = 0x002c,
 323         [EDOCR]         = 0x0030,
 324         [FCFTR]         = 0x0034,
 325         [RPADIR]        = 0x0038,
 326         [TRIMD]         = 0x003c,
 327         [RBWAR]         = 0x0040,
 328         [RDFAR]         = 0x0044,
 329         [TBRAR]         = 0x004c,
 330         [TDFAR]         = 0x0050,
 331
 332         [ECMR]          = 0x0160,
 333         [ECSR]          = 0x0164,
 334         [ECSIPR]        = 0x0168,
 335         [PIR]           = 0x016c,
 336         [MAHR]          = 0x0170,
 337         [MALR]          = 0x0174,
 338         [RFLR]          = 0x0178,
 339         [PSR]           = 0x017c,
 340         [TROCR]         = 0x0180,
 341         [CDCR]          = 0x0184,
 342         [LCCR]          = 0x0188,
 343         [CNDCR]         = 0x018c,
 344         [CEFCR]         = 0x0194,
 345         [FRECR]         = 0x0198,
 346         [TSFRCR]        = 0x019c,
 347         [TLFRCR]        = 0x01a0,
 348         [RFCR]          = 0x01a4,
 349         [MAFCR]         = 0x01a8,
 350         [IPGR]          = 0x01b4,
 351         [APR]           = 0x01b8,
 352         [MPR]           = 0x01bc,
 353         [TPAUSER]       = 0x01c4,
 354         [BCFR]          = 0x01cc,
 355
 356         [ARSTR]         = 0x0000,
 357         [TSU_CTRST]     = 0x0004,
 358         [TSU_FWEN0]     = 0x0010,
 359         [TSU_FWEN1]     = 0x0014,
 360         [TSU_FCM]       = 0x0018,
 361         [TSU_BSYSL0]    = 0x0020,
 362         [TSU_BSYSL1]    = 0x0024,
 363         [TSU_PRISL0]    = 0x0028,
 364         [TSU_PRISL1]    = 0x002c,
 365         [TSU_FWSL0]     = 0x0030,
 366         [TSU_FWSL1]     = 0x0034,
 367         [TSU_FWSLC]     = 0x0038,
 368         [TSU_QTAGM0]    = 0x0040,
 369         [TSU_QTAGM1]    = 0x0044,
 370         [TSU_ADQT0]     = 0x0048,
 371         [TSU_ADQT1]     = 0x004c,
 372         [TSU_FWSR]      = 0x0050,
 373         [TSU_FWINMK]    = 0x0054,
 374         [TSU_ADSBSY]    = 0x0060,
 375         [TSU_TEN]       = 0x0064,
 376         [TSU_POST1]     = 0x0070,
 377         [TSU_POST2]     = 0x0074,
 378         [TSU_POST3]     = 0x0078,
 379         [TSU_POST4]     = 0x007c,
 380
 381         [TXNLCR0]       = 0x0080,
 382         [TXALCR0]       = 0x0084,
 383         [RXNLCR0]       = 0x0088,
 384         [RXALCR0]       = 0x008c,
 385         [FWNLCR0]       = 0x0090,
 386         [FWALCR0]       = 0x0094,
 387         [TXNLCR1]       = 0x00a0,
 388         [TXALCR1]       = 0x00a0,
 389         [RXNLCR1]       = 0x00a8,
 390         [RXALCR1]       = 0x00ac,
 391         [FWNLCR1]       = 0x00b0,
 392         [FWALCR1]       = 0x00b4,
 393
 394         [TSU_ADRH0]     = 0x0100,
 395         [TSU_ADRL0]     = 0x0104,
 396         [TSU_ADRL31]    = 0x01fc,
 397 };
 398
 399 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 401
 402 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 403 {
 404         return mdp->reg_offset == sh_eth_offset_gigabit;
 405 }
 406
 407 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 408 {
 409         return mdp->reg_offset == sh_eth_offset_fast_rz;
 410 }
 411
 412 static void sh_eth_select_mii(struct net_device *ndev)
 413 {
 414         u32 value = 0x0;
 415         struct sh_eth_private *mdp = netdev_priv(ndev);
 416
 417         switch (mdp->phy_interface) {
 418         case PHY_INTERFACE_MODE_GMII:
 419                 value = 0x2;
 420                 break;
 421         case PHY_INTERFACE_MODE_MII:
 422                 value = 0x1;
 423                 break;
 424         case PHY_INTERFACE_MODE_RMII:
 425                 value = 0x0;
 426                 break;
 427         default:
 428                 netdev_warn(ndev,
 429                             "PHY interface mode was not setup. Set to MII.\n");
 430                 value = 0x1;
 431                 break;
 432         }
 433
 434         sh_eth_write(ndev, value, RMII_MII);
 435 }
 436
 437 static void sh_eth_set_duplex(struct net_device *ndev)
 438 {
 439         struct sh_eth_private *mdp = netdev_priv(ndev);
 440
 441         if (mdp->duplex) /* Full */
 442                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 443         else            /* Half */
 444                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 445 }
 446
 447 /* There is CPU dependent code */
 448 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 449 {
 450         struct sh_eth_private *mdp = netdev_priv(ndev);
 451
 452         switch (mdp->speed) {
 453         case 10: /* 10BASE */
 454                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 455                 break;
 456         case 100:/* 100BASE */
 457                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 458                 break;
 459         default:
 460                 break;
 461         }
 462 }
 463
 464 /* R8A7778/9 */
 465 static struct sh_eth_cpu_data r8a777x_data = {
 466         .set_duplex     = sh_eth_set_duplex,
 467         .set_rate       = sh_eth_set_rate_r8a777x,
 468
 469         .register_type  = SH_ETH_REG_FAST_RCAR,
 470
 471         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 472         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 473         .eesipr_value   = 0x01ff009f,
 474
 475         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 476         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 477                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 478                           EESR_ECI,
 479         .fdr_value      = 0x00000f0f,
 480
 481         .apr            = 1,
 482         .mpr            = 1,
 483         .tpauser        = 1,
 484         .hw_swap        = 1,
 485 };
 486
 487 /* R8A7790/1 */
 488 static struct sh_eth_cpu_data r8a779x_data = {
 489         .set_duplex     = sh_eth_set_duplex,
 490         .set_rate       = sh_eth_set_rate_r8a777x,
 491
 492         .register_type  = SH_ETH_REG_FAST_RCAR,
 493
 494         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 495         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 496         .eesipr_value   = 0x01ff009f,
 497
 498         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 499         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 500                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 501                           EESR_ECI,
 502         .fdr_value      = 0x00000f0f,
 503
 504         .trscer_err_mask = DESC_I_RINT8,
 505
 506         .apr            = 1,
 507         .mpr            = 1,
 508         .tpauser        = 1,
 509         .hw_swap        = 1,
 510         .rmiimode       = 1,
 511         .shift_rd0      = 1,
 512 };
 513
 514 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 515 {
 516         struct sh_eth_private *mdp = netdev_priv(ndev);
 517
 518         switch (mdp->speed) {
 519         case 10: /* 10BASE */
 520                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 521                 break;
 522         case 100:/* 100BASE */
 523                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 524                 break;
 525         default:
 526                 break;
 527         }
 528 }
 529
 530 /* SH7724 */
 531 static struct sh_eth_cpu_data sh7724_data = {
 532         .set_duplex     = sh_eth_set_duplex,
 533         .set_rate       = sh_eth_set_rate_sh7724,
 534
 535         .register_type  = SH_ETH_REG_FAST_SH4,
 536
 537         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 538         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 539         .eesipr_value   = 0x01ff009f,
 540
 541         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 542         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 543                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 544                           EESR_ECI,
 545
 546         .apr            = 1,
 547         .mpr            = 1,
 548         .tpauser        = 1,
 549         .hw_swap        = 1,
 550         .rpadir         = 1,
 551         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 552 };
 553
 554 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 555 {
 556         struct sh_eth_private *mdp = netdev_priv(ndev);
 557
 558         switch (mdp->speed) {
 559         case 10: /* 10BASE */
 560                 sh_eth_write(ndev, 0, RTRATE);
 561                 break;
 562         case 100:/* 100BASE */
 563                 sh_eth_write(ndev, 1, RTRATE);
 564                 break;
 565         default:
 566                 break;
 567         }
 568 }
 569
 570 /* SH7757 */
 571 static struct sh_eth_cpu_data sh7757_data = {
 572         .set_duplex     = sh_eth_set_duplex,
 573         .set_rate       = sh_eth_set_rate_sh7757,
 574
 575         .register_type  = SH_ETH_REG_FAST_SH4,
 576
 577         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 578
 579         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 580         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 581                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 582                           EESR_ECI,
 583
 584         .irq_flags      = IRQF_SHARED,
 585         .apr            = 1,
 586         .mpr            = 1,
 587         .tpauser        = 1,
 588         .hw_swap        = 1,
 589         .no_ade         = 1,
 590         .rpadir         = 1,
 591         .rpadir_value   = 2 << 16,
 592 };
 593
 594 #define SH_GIGA_ETH_BASE        0xfee00000UL
 595 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 596 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 597 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 598 {
 599         int i;
 600         u32 mahr[2], malr[2];
 601
 602         /* save MAHR and MALR */
 603         for (i = 0; i < 2; i++) {
 604                 malr[i] = ioread32((void *)GIGA_MALR(i));
 605                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 606         }
 607
 608         /* reset device */
 609         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 610         mdelay(1);
 611
 612         /* restore MAHR and MALR */
 613         for (i = 0; i < 2; i++) {
 614                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 615                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 616         }
 617 }
 618
 619 static void sh_eth_set_rate_giga(struct net_device *ndev)
 620 {
 621         struct sh_eth_private *mdp = netdev_priv(ndev);
 622
 623         switch (mdp->speed) {
 624         case 10: /* 10BASE */
 625                 sh_eth_write(ndev, 0x00000000, GECMR);
 626                 break;
 627         case 100:/* 100BASE */
 628                 sh_eth_write(ndev, 0x00000010, GECMR);
 629                 break;
 630         case 1000: /* 1000BASE */
 631                 sh_eth_write(ndev, 0x00000020, GECMR);
 632                 break;
 633         default:
 634                 break;
 635         }
 636 }
 637
 638 /* SH7757(GETHERC) */
 639 static struct sh_eth_cpu_data sh7757_data_giga = {
 640         .chip_reset     = sh_eth_chip_reset_giga,
 641         .set_duplex     = sh_eth_set_duplex,
 642         .set_rate       = sh_eth_set_rate_giga,
 643
 644         .register_type  = SH_ETH_REG_GIGABIT,
 645
 646         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 647         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 648         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 649
 650         .tx_check       = EESR_TC1 | EESR_FTC,
 651         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 652                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 653                           EESR_TDE | EESR_ECI,
 654         .fdr_value      = 0x0000072f,
 655
 656         .irq_flags      = IRQF_SHARED,
 657         .apr            = 1,
 658         .mpr            = 1,
 659         .tpauser        = 1,
 660         .bculr          = 1,
 661         .hw_swap        = 1,
 662         .rpadir         = 1,
 663         .rpadir_value   = 2 << 16,
 664         .no_trimd       = 1,
 665         .no_ade         = 1,
 666         .tsu            = 1,
 667 };
 668
 669 static void sh_eth_chip_reset(struct net_device *ndev)
 670 {
 671         struct sh_eth_private *mdp = netdev_priv(ndev);
 672
 673         /* reset device */
 674         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 675         mdelay(1);
 676 }
 677
 678 static void sh_eth_set_rate_gether(struct net_device *ndev)
 679 {
 680         struct sh_eth_private *mdp = netdev_priv(ndev);
 681
 682         switch (mdp->speed) {
 683         case 10: /* 10BASE */
 684                 sh_eth_write(ndev, GECMR_10, GECMR);
 685                 break;
 686         case 100:/* 100BASE */
 687                 sh_eth_write(ndev, GECMR_100, GECMR);
 688                 break;
 689         case 1000: /* 1000BASE */
 690                 sh_eth_write(ndev, GECMR_1000, GECMR);
 691                 break;
 692         default:
 693                 break;
 694         }
 695 }
 696
 697 /* SH7734 */
 698 static struct sh_eth_cpu_data sh7734_data = {
 699         .chip_reset     = sh_eth_chip_reset,
 700         .set_duplex     = sh_eth_set_duplex,
 701         .set_rate       = sh_eth_set_rate_gether,
 702
 703         .register_type  = SH_ETH_REG_GIGABIT,
 704
 705         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 706         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 707         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 708
 709         .tx_check       = EESR_TC1 | EESR_FTC,
 710         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 711                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 712                           EESR_TDE | EESR_ECI,
 713
 714         .apr            = 1,
 715         .mpr            = 1,
 716         .tpauser        = 1,
 717         .bculr          = 1,
 718         .hw_swap        = 1,
 719         .no_trimd       = 1,
 720         .no_ade         = 1,
 721         .tsu            = 1,
 722         .hw_crc         = 1,
 723         .select_mii     = 1,
 724 };
 725
 726 /* SH7763 */
 727 static struct sh_eth_cpu_data sh7763_data = {
 728         .chip_reset     = sh_eth_chip_reset,
 729         .set_duplex     = sh_eth_set_duplex,
 730         .set_rate       = sh_eth_set_rate_gether,
 731
 732         .register_type  = SH_ETH_REG_GIGABIT,
 733
 734         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 735         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 736         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 737
 738         .tx_check       = EESR_TC1 | EESR_FTC,
 739         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 740                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 741                           EESR_ECI,
 742
 743         .apr            = 1,
 744         .mpr            = 1,
 745         .tpauser        = 1,
 746         .bculr          = 1,
 747         .hw_swap        = 1,
 748         .no_trimd       = 1,
 749         .no_ade         = 1,
 750         .tsu            = 1,
 751         .irq_flags      = IRQF_SHARED,
 752 };
 753
 754 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 755 {
 756         struct sh_eth_private *mdp = netdev_priv(ndev);
 757
 758         /* reset device */
 759         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 760         mdelay(1);
 761
 762         sh_eth_select_mii(ndev);
 763 }
 764
 765 /* R8A7740 */
 766 static struct sh_eth_cpu_data r8a7740_data = {
 767         .chip_reset     = sh_eth_chip_reset_r8a7740,
 768         .set_duplex     = sh_eth_set_duplex,
 769         .set_rate       = sh_eth_set_rate_gether,
 770
 771         .register_type  = SH_ETH_REG_GIGABIT,
 772
 773         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 774         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 775         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 776
 777         .tx_check       = EESR_TC1 | EESR_FTC,
 778         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 779                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 780                           EESR_TDE | EESR_ECI,
 781         .fdr_value      = 0x0000070f,
 782
 783         .apr            = 1,
 784         .mpr            = 1,
 785         .tpauser        = 1,
 786         .bculr          = 1,
 787         .hw_swap        = 1,
 788         .rpadir         = 1,
 789         .rpadir_value   = 2 << 16,
 790         .no_trimd       = 1,
 791         .no_ade         = 1,
 792         .tsu            = 1,
 793         .select_mii     = 1,
 794         .shift_rd0      = 1,
 795 };
 796
 797 /* R7S72100 */
 798 static struct sh_eth_cpu_data r7s72100_data = {
 799         .chip_reset     = sh_eth_chip_reset,
 800         .set_duplex     = sh_eth_set_duplex,
 801
 802         .register_type  = SH_ETH_REG_FAST_RZ,
 803
 804         .ecsr_value     = ECSR_ICD,
 805         .ecsipr_value   = ECSIPR_ICDIP,
 806         .eesipr_value   = 0xff7f009f,
 807
 808         .tx_check       = EESR_TC1 | EESR_FTC,
 809         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 810                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 811                           EESR_TDE | EESR_ECI,
 812         .fdr_value      = 0x0000070f,
 813
 814         .no_psr         = 1,
 815         .apr            = 1,
 816         .mpr            = 1,
 817         .tpauser        = 1,
 818         .hw_swap        = 1,
 819         .rpadir         = 1,
 820         .rpadir_value   = 2 << 16,
 821         .no_trimd       = 1,
 822         .no_ade         = 1,
 823         .hw_crc         = 1,
 824         .tsu            = 1,
 825         .shift_rd0      = 1,
 826 };
 827
 828 static struct sh_eth_cpu_data sh7619_data = {
 829         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 830
 831         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 832
 833         .apr            = 1,
 834         .mpr            = 1,
 835         .tpauser        = 1,
 836         .hw_swap        = 1,
 837 };
 838
 839 static struct sh_eth_cpu_data sh771x_data = {
 840         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 841
 842         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 843         .tsu            = 1,
 844 };
 845
 846 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 847 {
 848         if (!cd->ecsr_value)
 849                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 850
 851         if (!cd->ecsipr_value)
 852                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 853
 854         if (!cd->fcftr_value)
 855                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 856                                   DEFAULT_FIFO_F_D_RFD;
 857
 858         if (!cd->fdr_value)
 859                 cd->fdr_value = DEFAULT_FDR_INIT;
 860
 861         if (!cd->tx_check)
 862                 cd->tx_check = DEFAULT_TX_CHECK;
 863
 864         if (!cd->eesr_err_check)
 865                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 866
 867         if (!cd->trscer_err_mask)
 868                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 869 }
 870
 871 static int sh_eth_check_reset(struct net_device *ndev)
 872 {
 873         int ret = 0;
 874         int cnt = 100;
 875
 876         while (cnt > 0) {
 877                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 878                         break;
 879                 mdelay(1);
 880                 cnt--;
 881         }
 882         if (cnt <= 0) {
 883                 netdev_err(ndev, "Device reset failed\n");
 884                 ret = -ETIMEDOUT;
 885         }
 886         return ret;
 887 }
 888
 889 static int sh_eth_reset(struct net_device *ndev)
 890 {
 891         struct sh_eth_private *mdp = netdev_priv(ndev);
 892         int ret = 0;
 893
 894         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 895                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 896                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 897                              EDMR);
 898
 899                 ret = sh_eth_check_reset(ndev);
 900                 if (ret)
 901                         return ret;
 902
 903                 /* Table Init */
 904                 sh_eth_write(ndev, 0x0, TDLAR);
 905                 sh_eth_write(ndev, 0x0, TDFAR);
 906                 sh_eth_write(ndev, 0x0, TDFXR);
 907                 sh_eth_write(ndev, 0x0, TDFFR);
 908                 sh_eth_write(ndev, 0x0, RDLAR);
 909                 sh_eth_write(ndev, 0x0, RDFAR);
 910                 sh_eth_write(ndev, 0x0, RDFXR);
 911                 sh_eth_write(ndev, 0x0, RDFFR);
 912
 913                 /* Reset HW CRC register */
 914                 if (mdp->cd->hw_crc)
 915                         sh_eth_write(ndev, 0x0, CSMR);
 916
 917                 /* Select MII mode */
 918                 if (mdp->cd->select_mii)
 919                         sh_eth_select_mii(ndev);
 920         } else {
 921                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 922                              EDMR);
 923                 mdelay(3);
 924                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 925                              EDMR);
 926         }
 927
 928         return ret;
 929 }
 930
 931 static void sh_eth_set_receive_align(struct sk_buff *skb)
 932 {
 933         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 934
 935         if (reserve)
 936                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 937 }
 938
 939
 940 /* CPU <-> EDMAC endian convert */
 941 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 942 {
 943         switch (mdp->edmac_endian) {
 944         case EDMAC_LITTLE_ENDIAN:
 945                 return cpu_to_le32(x);
 946         case EDMAC_BIG_ENDIAN:
 947                 return cpu_to_be32(x);
 948         }
 949         return x;
 950 }
 951
 952 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 953 {
 954         switch (mdp->edmac_endian) {
 955         case EDMAC_LITTLE_ENDIAN:
 956                 return le32_to_cpu(x);
 957         case EDMAC_BIG_ENDIAN:
 958                 return be32_to_cpu(x);
 959         }
 960         return x;
 961 }
 962
 963 /* Program the hardware MAC address from dev->dev_addr. */
 964 static void update_mac_address(struct net_device *ndev)
 965 {
 966         sh_eth_write(ndev,
 967                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 968                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 969         sh_eth_write(ndev,
 970                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 971 }
 972
 973 /* Get MAC address from SuperH MAC address register
 974  *
 975  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 976  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 977  * When you want use this device, you must set MAC address in bootloader.
 978  *
 979  */
 980 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 981 {
 982         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 983                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 984         } else {
 985                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 986                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 987                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 988                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 989                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 990                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 991         }
 992 }
 993
 994 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 995 {
 996         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 997                 return EDTRR_TRNS_GETHER;
 998         else
 999                 return EDTRR_TRNS_ETHER;
1000 }
1001
1002 struct bb_info {
1003         void (*set_gate)(void *addr);
1004         struct mdiobb_ctrl ctrl;
1005         void *addr;
1006         u32 mmd_msk;/* MMD */
1007         u32 mdo_msk;
1008         u32 mdi_msk;
1009         u32 mdc_msk;
1010 };
1011
1012 /* PHY bit set */
1013 static void bb_set(void *addr, u32 msk)
1014 {
1015         iowrite32(ioread32(addr) | msk, addr);
1016 }
1017
1018 /* PHY bit clear */
1019 static void bb_clr(void *addr, u32 msk)
1020 {
1021         iowrite32((ioread32(addr) & ~msk), addr);
1022 }
1023
1024 /* PHY bit read */
1025 static int bb_read(void *addr, u32 msk)
1026 {
1027         return (ioread32(addr) & msk) != 0;
1028 }
1029
1030 /* Data I/O pin control */
1031 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1032 {
1033         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1034
1035         if (bitbang->set_gate)
1036                 bitbang->set_gate(bitbang->addr);
1037
1038         if (bit)
1039                 bb_set(bitbang->addr, bitbang->mmd_msk);
1040         else
1041                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1042 }
1043
1044 /* Set bit data*/
1045 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1046 {
1047         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1048
1049         if (bitbang->set_gate)
1050                 bitbang->set_gate(bitbang->addr);
1051
1052         if (bit)
1053                 bb_set(bitbang->addr, bitbang->mdo_msk);
1054         else
1055                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1056 }
1057
1058 /* Get bit data*/
1059 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1060 {
1061         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1062
1063         if (bitbang->set_gate)
1064                 bitbang->set_gate(bitbang->addr);
1065
1066         return bb_read(bitbang->addr, bitbang->mdi_msk);
1067 }
1068
1069 /* MDC pin control */
1070 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1071 {
1072         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1073
1074         if (bitbang->set_gate)
1075                 bitbang->set_gate(bitbang->addr);
1076
1077         if (bit)
1078                 bb_set(bitbang->addr, bitbang->mdc_msk);
1079         else
1080                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1081 }
1082
1083 /* mdio bus control struct */
1084 static struct mdiobb_ops bb_ops = {
1085         .owner = THIS_MODULE,
1086         .set_mdc = sh_mdc_ctrl,
1087         .set_mdio_dir = sh_mmd_ctrl,
1088         .set_mdio_data = sh_set_mdio,
1089         .get_mdio_data = sh_get_mdio,
1090 };
1091
1092 /* free skb and descriptor buffer */
1093 static void sh_eth_ring_free(struct net_device *ndev)
1094 {
1095         struct sh_eth_private *mdp = netdev_priv(ndev);
1096         int i;
1097
1098         /* Free Rx skb ringbuffer */
1099         if (mdp->rx_skbuff) {
1100                 for (i = 0; i < mdp->num_rx_ring; i++)
1101                         dev_kfree_skb(mdp->rx_skbuff[i]);
1102         }
1103         kfree(mdp->rx_skbuff);
1104         mdp->rx_skbuff = NULL;
1105
1106         /* Free Tx skb ringbuffer */
1107         if (mdp->tx_skbuff) {
1108                 for (i = 0; i < mdp->num_tx_ring; i++)
1109                         dev_kfree_skb(mdp->tx_skbuff[i]);
1110         }
1111         kfree(mdp->tx_skbuff);
1112         mdp->tx_skbuff = NULL;
1113 }
1114
1115 /* format skb and descriptor buffer */
1116 static void sh_eth_ring_format(struct net_device *ndev)
1117 {
1118         struct sh_eth_private *mdp = netdev_priv(ndev);
1119         int i;
1120         struct sk_buff *skb;
1121         struct sh_eth_rxdesc *rxdesc = NULL;
1122         struct sh_eth_txdesc *txdesc = NULL;
1123         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1124         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1125         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1126         dma_addr_t dma_addr;
1127
1128         mdp->cur_rx = 0;
1129         mdp->cur_tx = 0;
1130         mdp->dirty_rx = 0;
1131         mdp->dirty_tx = 0;
1132
1133         memset(mdp->rx_ring, 0, rx_ringsize);
1134
1135         /* build Rx ring buffer */
1136         for (i = 0; i < mdp->num_rx_ring; i++) {
1137                 /* skb */
1138                 mdp->rx_skbuff[i] = NULL;
1139                 skb = netdev_alloc_skb(ndev, skbuff_size);
1140                 if (skb == NULL)
1141                         break;
1142                 sh_eth_set_receive_align(skb);
1143
1144                 /* RX descriptor */
1145                 rxdesc = &mdp->rx_ring[i];
1146                 /* The size of the buffer is a multiple of 16 bytes. */
1147                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1148                 dma_addr = dma_map_single(&ndev->dev, skb->data,
1149                                           rxdesc->buffer_length,
1150                                           DMA_FROM_DEVICE);
1151                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1152                         kfree_skb(skb);
1153                         break;
1154                 }
1155                 mdp->rx_skbuff[i] = skb;
1156                 rxdesc->addr = dma_addr;
1157                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1158
1159                 /* Rx descriptor address set */
1160                 if (i == 0) {
1161                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1162                         if (sh_eth_is_gether(mdp) ||
1163                             sh_eth_is_rz_fast_ether(mdp))
1164                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1165                 }
1166         }
1167
1168         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1169
1170         /* Mark the last entry as wrapping the ring. */
1171         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1172
1173         memset(mdp->tx_ring, 0, tx_ringsize);
1174
1175         /* build Tx ring buffer */
1176         for (i = 0; i < mdp->num_tx_ring; i++) {
1177                 mdp->tx_skbuff[i] = NULL;
1178                 txdesc = &mdp->tx_ring[i];
1179                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1180                 txdesc->buffer_length = 0;
1181                 if (i == 0) {
1182                         /* Tx descriptor address set */
1183                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1184                         if (sh_eth_is_gether(mdp) ||
1185                             sh_eth_is_rz_fast_ether(mdp))
1186                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1187                 }
1188         }
1189
1190         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1191 }
1192
1193 /* Get skb and descriptor buffer */
1194 static int sh_eth_ring_init(struct net_device *ndev)
1195 {
1196         struct sh_eth_private *mdp = netdev_priv(ndev);
1197         int rx_ringsize, tx_ringsize, ret = 0;
1198
1199         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1200          * card needs room to do 8 byte alignment, +2 so we can reserve
1201          * the first 2 bytes, and +16 gets room for the status word from the
1202          * card.
1203          */
1204         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1205                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1206         if (mdp->cd->rpadir)
1207                 mdp->rx_buf_sz += NET_IP_ALIGN;
1208
1209         /* Allocate RX and TX skb rings */
1210         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1211                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1212         if (!mdp->rx_skbuff) {
1213                 ret = -ENOMEM;
1214                 return ret;
1215         }
1216
1217         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1218                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1219         if (!mdp->tx_skbuff) {
1220                 ret = -ENOMEM;
1221                 goto skb_ring_free;
1222         }
1223
1224         /* Allocate all Rx descriptors. */
1225         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1226         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1227                                           GFP_KERNEL);
1228         if (!mdp->rx_ring) {
1229                 ret = -ENOMEM;
1230                 goto desc_ring_free;
1231         }
1232
1233         mdp->dirty_rx = 0;
1234
1235         /* Allocate all Tx descriptors. */
1236         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1237         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1238                                           GFP_KERNEL);
1239         if (!mdp->tx_ring) {
1240                 ret = -ENOMEM;
1241                 goto desc_ring_free;
1242         }
1243         return ret;
1244
1245 desc_ring_free:
1246         /* free DMA buffer */
1247         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1248
1249 skb_ring_free:
1250         /* Free Rx and Tx skb ring buffer */
1251         sh_eth_ring_free(ndev);
1252         mdp->tx_ring = NULL;
1253         mdp->rx_ring = NULL;
1254
1255         return ret;
1256 }
1257
1258 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1259 {
1260         int ringsize;
1261
1262         if (mdp->rx_ring) {
1263                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1264                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1265                                   mdp->rx_desc_dma);
1266                 mdp->rx_ring = NULL;
1267         }
1268
1269         if (mdp->tx_ring) {
1270                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1271                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1272                                   mdp->tx_desc_dma);
1273                 mdp->tx_ring = NULL;
1274         }
1275 }
1276
1277 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1278 {
1279         int ret = 0;
1280         struct sh_eth_private *mdp = netdev_priv(ndev);
1281         u32 val;
1282
1283         /* Soft Reset */
1284         ret = sh_eth_reset(ndev);
1285         if (ret)
1286                 return ret;
1287
1288         if (mdp->cd->rmiimode)
1289                 sh_eth_write(ndev, 0x1, RMIIMODE);
1290
1291         /* Descriptor format */
1292         sh_eth_ring_format(ndev);
1293         if (mdp->cd->rpadir)
1294                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1295
1296         /* all sh_eth int mask */
1297         sh_eth_write(ndev, 0, EESIPR);
1298
1299 #if defined(__LITTLE_ENDIAN)
1300         if (mdp->cd->hw_swap)
1301                 sh_eth_write(ndev, EDMR_EL, EDMR);
1302         else
1303 #endif
1304                 sh_eth_write(ndev, 0, EDMR);
1305
1306         /* FIFO size set */
1307         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1308         sh_eth_write(ndev, 0, TFTR);
1309
1310         /* Frame recv control (enable multiple-packets per rx irq) */
1311         sh_eth_write(ndev, RMCR_RNC, RMCR);
1312
1313         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1314
1315         if (mdp->cd->bculr)
1316                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1317
1318         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1319
1320         if (!mdp->cd->no_trimd)
1321                 sh_eth_write(ndev, 0, TRIMD);
1322
1323         /* Recv frame limit set register */
1324         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1325                      RFLR);
1326
1327         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1328         if (start) {
1329                 mdp->irq_enabled = true;
1330                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1331         }
1332
1333         /* PAUSE Prohibition */
1334         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1335                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1336
1337         sh_eth_write(ndev, val, ECMR);
1338
1339         if (mdp->cd->set_rate)
1340                 mdp->cd->set_rate(ndev);
1341
1342         /* E-MAC Status Register clear */
1343         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1344
1345         /* E-MAC Interrupt Enable register */
1346         if (start)
1347                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1348
1349         /* Set MAC address */
1350         update_mac_address(ndev);
1351
1352         /* mask reset */
1353         if (mdp->cd->apr)
1354                 sh_eth_write(ndev, APR_AP, APR);
1355         if (mdp->cd->mpr)
1356                 sh_eth_write(ndev, MPR_MP, MPR);
1357         if (mdp->cd->tpauser)
1358                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1359
1360         if (start) {
1361                 /* Setting the Rx mode will start the Rx process. */
1362                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1363
1364                 netif_start_queue(ndev);
1365         }
1366
1367         return ret;
1368 }
1369
1370 static void sh_eth_dev_exit(struct net_device *ndev)
1371 {
1372         struct sh_eth_private *mdp = netdev_priv(ndev);
1373         int i;
1374
1375         /* Deactivate all TX descriptors, so DMA should stop at next
1376          * packet boundary if it's currently running
1377          */
1378         for (i = 0; i < mdp->num_tx_ring; i++)
1379                 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1380
1381         /* Disable TX FIFO egress to MAC */
1382         sh_eth_rcv_snd_disable(ndev);
1383
1384         /* Stop RX DMA at next packet boundary */
1385         sh_eth_write(ndev, 0, EDRRR);
1386
1387         /* Aside from TX DMA, we can't tell when the hardware is
1388          * really stopped, so we need to reset to make sure.
1389          * Before doing that, wait for long enough to *probably*
1390          * finish transmitting the last packet and poll stats.
1391          */
1392         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1393         sh_eth_get_stats(ndev);
1394         sh_eth_reset(ndev);
1395
1396         /* Set MAC address again */
1397         update_mac_address(ndev);
1398 }
1399
1400 /* free Tx skb function */
1401 static int sh_eth_txfree(struct net_device *ndev)
1402 {
1403         struct sh_eth_private *mdp = netdev_priv(ndev);
1404         struct sh_eth_txdesc *txdesc;
1405         int free_num = 0;
1406         int entry = 0;
1407
1408         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1409                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1410                 txdesc = &mdp->tx_ring[entry];
1411                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1412                         break;
1413                 /* TACT bit must be checked before all the following reads */
1414                 rmb();
1415                 /* Free the original skb. */
1416                 if (mdp->tx_skbuff[entry]) {
1417                         dma_unmap_single(&ndev->dev, txdesc->addr,
1418                                          txdesc->buffer_length, DMA_TO_DEVICE);
1419                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1420                         mdp->tx_skbuff[entry] = NULL;
1421                         free_num++;
1422                 }
1423                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1424                 if (entry >= mdp->num_tx_ring - 1)
1425                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1426
1427                 ndev->stats.tx_packets++;
1428                 ndev->stats.tx_bytes += txdesc->buffer_length;
1429         }
1430         return free_num;
1431 }
1432
1433 /* Packet receive function */
1434 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1435 {
1436         struct sh_eth_private *mdp = netdev_priv(ndev);
1437         struct sh_eth_rxdesc *rxdesc;
1438
1439         int entry = mdp->cur_rx % mdp->num_rx_ring;
1440         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1441         int limit;
1442         struct sk_buff *skb;
1443         u16 pkt_len = 0;
1444         u32 desc_status;
1445         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1446         dma_addr_t dma_addr;
1447
1448         boguscnt = min(boguscnt, *quota);
1449         limit = boguscnt;
1450         rxdesc = &mdp->rx_ring[entry];
1451         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1452                 /* RACT bit must be checked before all the following reads */
1453                 rmb();
1454                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1455                 pkt_len = rxdesc->frame_length;
1456
1457                 if (--boguscnt < 0)
1458                         break;
1459
1460                 if (!(desc_status & RDFEND))
1461                         ndev->stats.rx_length_errors++;
1462
1463                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1464                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1465                  * bit 0. However, in case of the R8A7740, R8A779x, and
1466                  * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1467                  * driver needs right shifting by 16.
1468                  */
1469                 if (mdp->cd->shift_rd0)
1470                         desc_status >>= 16;
1471
1472                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1473                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1474                         ndev->stats.rx_errors++;
1475                         if (desc_status & RD_RFS1)
1476                                 ndev->stats.rx_crc_errors++;
1477                         if (desc_status & RD_RFS2)
1478                                 ndev->stats.rx_frame_errors++;
1479                         if (desc_status & RD_RFS3)
1480                                 ndev->stats.rx_length_errors++;
1481                         if (desc_status & RD_RFS4)
1482                                 ndev->stats.rx_length_errors++;
1483                         if (desc_status & RD_RFS6)
1484                                 ndev->stats.rx_missed_errors++;
1485                         if (desc_status & RD_RFS10)
1486                                 ndev->stats.rx_over_errors++;
1487                 } else {
1488                         if (!mdp->cd->hw_swap)
1489                                 sh_eth_soft_swap(
1490                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1491                                         pkt_len + 2);
1492                         skb = mdp->rx_skbuff[entry];
1493                         mdp->rx_skbuff[entry] = NULL;
1494                         if (mdp->cd->rpadir)
1495                                 skb_reserve(skb, NET_IP_ALIGN);
1496                         dma_unmap_single(&ndev->dev, rxdesc->addr,
1497                                          ALIGN(mdp->rx_buf_sz, 16),
1498                                          DMA_FROM_DEVICE);
1499                         skb_put(skb, pkt_len);
1500                         skb->protocol = eth_type_trans(skb, ndev);
1501                         netif_receive_skb(skb);
1502                         ndev->stats.rx_packets++;
1503                         ndev->stats.rx_bytes += pkt_len;
1504                 }
1505                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1506                 rxdesc = &mdp->rx_ring[entry];
1507         }
1508
1509         /* Refill the Rx ring buffers. */
1510         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1511                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1512                 rxdesc = &mdp->rx_ring[entry];
1513                 /* The size of the buffer is 16 byte boundary. */
1514                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1515
1516                 if (mdp->rx_skbuff[entry] == NULL) {
1517                         skb = netdev_alloc_skb(ndev, skbuff_size);
1518                         if (skb == NULL)
1519                                 break;  /* Better luck next round. */
1520                         sh_eth_set_receive_align(skb);
1521                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1522                                                   rxdesc->buffer_length,
1523                                                   DMA_FROM_DEVICE);
1524                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1525                                 kfree_skb(skb);
1526                                 break;
1527                         }
1528                         mdp->rx_skbuff[entry] = skb;
1529
1530                         skb_checksum_none_assert(skb);
1531                         rxdesc->addr = dma_addr;
1532                 }
1533                 wmb(); /* RACT bit must be set after all the above writes */
1534                 if (entry >= mdp->num_rx_ring - 1)
1535                         rxdesc->status |=
1536                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1537                 else
1538                         rxdesc->status |=
1539                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1540         }
1541
1542         /* Restart Rx engine if stopped. */
1543         /* If we don't need to check status, don't. -KDU */
1544         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1545                 /* fix the values for the next receiving if RDE is set */
1546                 if (intr_status & EESR_RDE) {
1547                         u32 count = (sh_eth_read(ndev, RDFAR) -
1548                                      sh_eth_read(ndev, RDLAR)) >> 4;
1549
1550                         mdp->cur_rx = count;
1551                         mdp->dirty_rx = count;
1552                 }
1553                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1554         }
1555
1556         *quota -= limit - boguscnt - 1;
1557
1558         return *quota <= 0;
1559 }
1560
1561 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1562 {
1563         /* disable tx and rx */
1564         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1565                 ~(ECMR_RE | ECMR_TE), ECMR);
1566 }
1567
1568 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1569 {
1570         /* enable tx and rx */
1571         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1572                 (ECMR_RE | ECMR_TE), ECMR);
1573 }
1574
1575 /* error control function */
1576 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1577 {
1578         struct sh_eth_private *mdp = netdev_priv(ndev);
1579         u32 felic_stat;
1580         u32 link_stat;
1581         u32 mask;
1582
1583         if (intr_status & EESR_ECI) {
1584                 felic_stat = sh_eth_read(ndev, ECSR);
1585                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1586                 if (felic_stat & ECSR_ICD)
1587                         ndev->stats.tx_carrier_errors++;
1588                 if (felic_stat & ECSR_LCHNG) {
1589                         /* Link Changed */
1590                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1591                                 goto ignore_link;
1592                         } else {
1593                                 link_stat = (sh_eth_read(ndev, PSR));
1594                                 if (mdp->ether_link_active_low)
1595                                         link_stat = ~link_stat;
1596                         }
1597                         if (!(link_stat & PHY_ST_LINK)) {
1598                                 sh_eth_rcv_snd_disable(ndev);
1599                         } else {
1600                                 /* Link Up */
1601                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1602                                                    ~DMAC_M_ECI, EESIPR);
1603                                 /* clear int */
1604                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1605                                              ECSR);
1606                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1607                                                    DMAC_M_ECI, EESIPR);
1608                                 /* enable tx and rx */
1609                                 sh_eth_rcv_snd_enable(ndev);
1610                         }
1611                 }
1612         }
1613
1614 ignore_link:
1615         if (intr_status & EESR_TWB) {
1616                 /* Unused write back interrupt */
1617                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1618                         ndev->stats.tx_aborted_errors++;
1619                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1620                 }
1621         }
1622
1623         if (intr_status & EESR_RABT) {
1624                 /* Receive Abort int */
1625                 if (intr_status & EESR_RFRMER) {
1626                         /* Receive Frame Overflow int */
1627                         ndev->stats.rx_frame_errors++;
1628                 }
1629         }
1630
1631         if (intr_status & EESR_TDE) {
1632                 /* Transmit Descriptor Empty int */
1633                 ndev->stats.tx_fifo_errors++;
1634                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1635         }
1636
1637         if (intr_status & EESR_TFE) {
1638                 /* FIFO under flow */
1639                 ndev->stats.tx_fifo_errors++;
1640                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1641         }
1642
1643         if (intr_status & EESR_RDE) {
1644                 /* Receive Descriptor Empty int */
1645                 ndev->stats.rx_over_errors++;
1646         }
1647
1648         if (intr_status & EESR_RFE) {
1649                 /* Receive FIFO Overflow int */
1650                 ndev->stats.rx_fifo_errors++;
1651         }
1652
1653         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1654                 /* Address Error */
1655                 ndev->stats.tx_fifo_errors++;
1656                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1657         }
1658
1659         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1660         if (mdp->cd->no_ade)
1661                 mask &= ~EESR_ADE;
1662         if (intr_status & mask) {
1663                 /* Tx error */
1664                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1665
1666                 /* dmesg */
1667                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1668                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1669                            (u32)ndev->state, edtrr);
1670                 /* dirty buffer free */
1671                 sh_eth_txfree(ndev);
1672
1673                 /* SH7712 BUG */
1674                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1675                         /* tx dma start */
1676                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1677                 }
1678                 /* wakeup */
1679                 netif_wake_queue(ndev);
1680         }
1681 }
1682
1683 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1684 {
1685         struct net_device *ndev = netdev;
1686         struct sh_eth_private *mdp = netdev_priv(ndev);
1687         struct sh_eth_cpu_data *cd = mdp->cd;
1688         irqreturn_t ret = IRQ_NONE;
1689         u32 intr_status, intr_enable;
1690
1691         spin_lock(&mdp->lock);
1692
1693         /* Get interrupt status */
1694         intr_status = sh_eth_read(ndev, EESR);
1695         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1696          * enabled since it's the one that  comes thru regardless of the mask,
1697          * and we need to fully handle it in sh_eth_error() in order to quench
1698          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1699          */
1700         intr_enable = sh_eth_read(ndev, EESIPR);
1701         intr_status &= intr_enable | DMAC_M_ECI;
1702         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1703                 ret = IRQ_HANDLED;
1704         else
1705                 goto out;
1706
1707         if (!likely(mdp->irq_enabled)) {
1708                 sh_eth_write(ndev, 0, EESIPR);
1709                 goto out;
1710         }
1711
1712         if (intr_status & EESR_RX_CHECK) {
1713                 if (napi_schedule_prep(&mdp->napi)) {
1714                         /* Mask Rx interrupts */
1715                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1716                                      EESIPR);
1717                         __napi_schedule(&mdp->napi);
1718                 } else {
1719                         netdev_warn(ndev,
1720                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1721                                     intr_status, intr_enable);
1722                 }
1723         }
1724
1725         /* Tx Check */
1726         if (intr_status & cd->tx_check) {
1727                 /* Clear Tx interrupts */
1728                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1729
1730                 sh_eth_txfree(ndev);
1731                 netif_wake_queue(ndev);
1732         }
1733
1734         if (intr_status & cd->eesr_err_check) {
1735                 /* Clear error interrupts */
1736                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1737
1738                 sh_eth_error(ndev, intr_status);
1739         }
1740
1741 out:
1742         spin_unlock(&mdp->lock);
1743
1744         return ret;
1745 }
1746
1747 static int sh_eth_poll(struct napi_struct *napi, int budget)
1748 {
1749         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1750                                                   napi);
1751         struct net_device *ndev = napi->dev;
1752         int quota = budget;
1753         u32 intr_status;
1754
1755         for (;;) {
1756                 intr_status = sh_eth_read(ndev, EESR);
1757                 if (!(intr_status & EESR_RX_CHECK))
1758                         break;
1759                 /* Clear Rx interrupts */
1760                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1761
1762                 if (sh_eth_rx(ndev, intr_status, &quota))
1763                         goto out;
1764         }
1765
1766         napi_complete(napi);
1767
1768         /* Reenable Rx interrupts */
1769         if (mdp->irq_enabled)
1770                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1771 out:
1772         return budget - quota;
1773 }
1774
1775 /* PHY state control function */
1776 static void sh_eth_adjust_link(struct net_device *ndev)
1777 {
1778         struct sh_eth_private *mdp = netdev_priv(ndev);
1779         struct phy_device *phydev = mdp->phydev;
1780         int new_state = 0;
1781
1782         if (phydev->link) {
1783                 if (phydev->duplex != mdp->duplex) {
1784                         new_state = 1;
1785                         mdp->duplex = phydev->duplex;
1786                         if (mdp->cd->set_duplex)
1787                                 mdp->cd->set_duplex(ndev);
1788                 }
1789
1790                 if (phydev->speed != mdp->speed) {
1791                         new_state = 1;
1792                         mdp->speed = phydev->speed;
1793                         if (mdp->cd->set_rate)
1794                                 mdp->cd->set_rate(ndev);
1795                 }
1796                 if (!mdp->link) {
1797                         sh_eth_write(ndev,
1798                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1799                                      ECMR);
1800                         new_state = 1;
1801                         mdp->link = phydev->link;
1802                         if (mdp->cd->no_psr || mdp->no_ether_link)
1803                                 sh_eth_rcv_snd_enable(ndev);
1804                 }
1805         } else if (mdp->link) {
1806                 new_state = 1;
1807                 mdp->link = 0;
1808                 mdp->speed = 0;
1809                 mdp->duplex = -1;
1810                 if (mdp->cd->no_psr || mdp->no_ether_link)
1811                         sh_eth_rcv_snd_disable(ndev);
1812         }
1813
1814         if (new_state && netif_msg_link(mdp))
1815                 phy_print_status(phydev);
1816 }
1817
1818 /* PHY init function */
1819 static int sh_eth_phy_init(struct net_device *ndev)
1820 {
1821         struct device_node *np = ndev->dev.parent->of_node;
1822         struct sh_eth_private *mdp = netdev_priv(ndev);
1823         struct phy_device *phydev = NULL;
1824
1825         mdp->link = 0;
1826         mdp->speed = 0;
1827         mdp->duplex = -1;
1828
1829         /* Try connect to PHY */
1830         if (np) {
1831                 struct device_node *pn;
1832
1833                 pn = of_parse_phandle(np, "phy-handle", 0);
1834                 phydev = of_phy_connect(ndev, pn,
1835                                         sh_eth_adjust_link, 0,
1836                                         mdp->phy_interface);
1837
1838                 if (!phydev)
1839                         phydev = ERR_PTR(-ENOENT);
1840         } else {
1841                 char phy_id[MII_BUS_ID_SIZE + 3];
1842
1843                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1844                          mdp->mii_bus->id, mdp->phy_id);
1845
1846                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1847                                      mdp->phy_interface);
1848         }
1849
1850         if (IS_ERR(phydev)) {
1851                 netdev_err(ndev, "failed to connect PHY\n");
1852                 return PTR_ERR(phydev);
1853         }
1854
1855         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1856                     phydev->addr, phydev->irq, phydev->drv->name);
1857
1858         mdp->phydev = phydev;
1859
1860         return 0;
1861 }
1862
1863 /* PHY control start function */
1864 static int sh_eth_phy_start(struct net_device *ndev)
1865 {
1866         struct sh_eth_private *mdp = netdev_priv(ndev);
1867         int ret;
1868
1869         ret = sh_eth_phy_init(ndev);
1870         if (ret)
1871                 return ret;
1872
1873         phy_start(mdp->phydev);
1874
1875         return 0;
1876 }
1877
1878 static int sh_eth_get_settings(struct net_device *ndev,
1879                                struct ethtool_cmd *ecmd)
1880 {
1881         struct sh_eth_private *mdp = netdev_priv(ndev);
1882         unsigned long flags;
1883         int ret;
1884
1885         if (!mdp->phydev)
1886                 return -ENODEV;
1887
1888         spin_lock_irqsave(&mdp->lock, flags);
1889         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1890         spin_unlock_irqrestore(&mdp->lock, flags);
1891
1892         return ret;
1893 }
1894
1895 static int sh_eth_set_settings(struct net_device *ndev,
1896                                struct ethtool_cmd *ecmd)
1897 {
1898         struct sh_eth_private *mdp = netdev_priv(ndev);
1899         unsigned long flags;
1900         int ret;
1901
1902         if (!mdp->phydev)
1903                 return -ENODEV;
1904
1905         spin_lock_irqsave(&mdp->lock, flags);
1906
1907         /* disable tx and rx */
1908         sh_eth_rcv_snd_disable(ndev);
1909
1910         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1911         if (ret)
1912                 goto error_exit;
1913
1914         if (ecmd->duplex == DUPLEX_FULL)
1915                 mdp->duplex = 1;
1916         else
1917                 mdp->duplex = 0;
1918
1919         if (mdp->cd->set_duplex)
1920                 mdp->cd->set_duplex(ndev);
1921
1922 error_exit:
1923         mdelay(1);
1924
1925         /* enable tx and rx */
1926         sh_eth_rcv_snd_enable(ndev);
1927
1928         spin_unlock_irqrestore(&mdp->lock, flags);
1929
1930         return ret;
1931 }
1932
1933 static int sh_eth_nway_reset(struct net_device *ndev)
1934 {
1935         struct sh_eth_private *mdp = netdev_priv(ndev);
1936         unsigned long flags;
1937         int ret;
1938
1939         if (!mdp->phydev)
1940                 return -ENODEV;
1941
1942         spin_lock_irqsave(&mdp->lock, flags);
1943         ret = phy_start_aneg(mdp->phydev);
1944         spin_unlock_irqrestore(&mdp->lock, flags);
1945
1946         return ret;
1947 }
1948
1949 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1950 {
1951         struct sh_eth_private *mdp = netdev_priv(ndev);
1952         return mdp->msg_enable;
1953 }
1954
1955 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1956 {
1957         struct sh_eth_private *mdp = netdev_priv(ndev);
1958         mdp->msg_enable = value;
1959 }
1960
1961 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1962         "rx_current", "tx_current",
1963         "rx_dirty", "tx_dirty",
1964 };
1965 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1966
1967 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1968 {
1969         switch (sset) {
1970         case ETH_SS_STATS:
1971                 return SH_ETH_STATS_LEN;
1972         default:
1973                 return -EOPNOTSUPP;
1974         }
1975 }
1976
1977 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1978                                      struct ethtool_stats *stats, u64 *data)
1979 {
1980         struct sh_eth_private *mdp = netdev_priv(ndev);
1981         int i = 0;
1982
1983         /* device-specific stats */
1984         data[i++] = mdp->cur_rx;
1985         data[i++] = mdp->cur_tx;
1986         data[i++] = mdp->dirty_rx;
1987         data[i++] = mdp->dirty_tx;
1988 }
1989
1990 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1991 {
1992         switch (stringset) {
1993         case ETH_SS_STATS:
1994                 memcpy(data, *sh_eth_gstrings_stats,
1995                        sizeof(sh_eth_gstrings_stats));
1996                 break;
1997         }
1998 }
1999
2000 static void sh_eth_get_ringparam(struct net_device *ndev,
2001                                  struct ethtool_ringparam *ring)
2002 {
2003         struct sh_eth_private *mdp = netdev_priv(ndev);
2004
2005         ring->rx_max_pending = RX_RING_MAX;
2006         ring->tx_max_pending = TX_RING_MAX;
2007         ring->rx_pending = mdp->num_rx_ring;
2008         ring->tx_pending = mdp->num_tx_ring;
2009 }
2010
2011 static int sh_eth_set_ringparam(struct net_device *ndev,
2012                                 struct ethtool_ringparam *ring)
2013 {
2014         struct sh_eth_private *mdp = netdev_priv(ndev);
2015         int ret;
2016
2017         if (ring->tx_pending > TX_RING_MAX ||
2018             ring->rx_pending > RX_RING_MAX ||
2019             ring->tx_pending < TX_RING_MIN ||
2020             ring->rx_pending < RX_RING_MIN)
2021                 return -EINVAL;
2022         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2023                 return -EINVAL;
2024
2025         if (netif_running(ndev)) {
2026                 netif_device_detach(ndev);
2027                 netif_tx_disable(ndev);
2028
2029                 /* Serialise with the interrupt handler and NAPI, then
2030                  * disable interrupts.  We have to clear the
2031                  * irq_enabled flag first to ensure that interrupts
2032                  * won't be re-enabled.
2033                  */
2034                 mdp->irq_enabled = false;
2035                 synchronize_irq(ndev->irq);
2036                 napi_synchronize(&mdp->napi);
2037                 sh_eth_write(ndev, 0x0000, EESIPR);
2038
2039                 sh_eth_dev_exit(ndev);
2040
2041                 /* Free all the skbuffs in the Rx queue. */
2042                 sh_eth_ring_free(ndev);
2043                 /* Free DMA buffer */
2044                 sh_eth_free_dma_buffer(mdp);
2045         }
2046
2047         /* Set new parameters */
2048         mdp->num_rx_ring = ring->rx_pending;
2049         mdp->num_tx_ring = ring->tx_pending;
2050
2051         if (netif_running(ndev)) {
2052                 ret = sh_eth_ring_init(ndev);
2053                 if (ret < 0) {
2054                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2055                                    __func__);
2056                         return ret;
2057                 }
2058                 ret = sh_eth_dev_init(ndev, false);
2059                 if (ret < 0) {
2060                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2061                                    __func__);
2062                         return ret;
2063                 }
2064
2065                 mdp->irq_enabled = true;
2066                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2067                 /* Setting the Rx mode will start the Rx process. */
2068                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2069                 netif_device_attach(ndev);
2070         }
2071
2072         return 0;
2073 }
2074
2075 static const struct ethtool_ops sh_eth_ethtool_ops = {
2076         .get_settings   = sh_eth_get_settings,
2077         .set_settings   = sh_eth_set_settings,
2078         .nway_reset     = sh_eth_nway_reset,
2079         .get_msglevel   = sh_eth_get_msglevel,
2080         .set_msglevel   = sh_eth_set_msglevel,
2081         .get_link       = ethtool_op_get_link,
2082         .get_strings    = sh_eth_get_strings,
2083         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2084         .get_sset_count     = sh_eth_get_sset_count,
2085         .get_ringparam  = sh_eth_get_ringparam,
2086         .set_ringparam  = sh_eth_set_ringparam,
2087 };
2088
2089 /* network device open function */
2090 static int sh_eth_open(struct net_device *ndev)
2091 {
2092         int ret = 0;
2093         struct sh_eth_private *mdp = netdev_priv(ndev);
2094
2095         pm_runtime_get_sync(&mdp->pdev->dev);
2096
2097         napi_enable(&mdp->napi);
2098
2099         ret = request_irq(ndev->irq, sh_eth_interrupt,
2100                           mdp->cd->irq_flags, ndev->name, ndev);
2101         if (ret) {
2102                 netdev_err(ndev, "Can not assign IRQ number\n");
2103                 goto out_napi_off;
2104         }
2105
2106         /* Descriptor set */
2107         ret = sh_eth_ring_init(ndev);
2108         if (ret)
2109                 goto out_free_irq;
2110
2111         /* device init */
2112         ret = sh_eth_dev_init(ndev, true);
2113         if (ret)
2114                 goto out_free_irq;
2115
2116         /* PHY control start*/
2117         ret = sh_eth_phy_start(ndev);
2118         if (ret)
2119                 goto out_free_irq;
2120
2121         mdp->is_opened = 1;
2122
2123         return ret;
2124
2125 out_free_irq:
2126         free_irq(ndev->irq, ndev);
2127 out_napi_off:
2128         napi_disable(&mdp->napi);
2129         pm_runtime_put_sync(&mdp->pdev->dev);
2130         return ret;
2131 }
2132
2133 /* Timeout function */
2134 static void sh_eth_tx_timeout(struct net_device *ndev)
2135 {
2136         struct sh_eth_private *mdp = netdev_priv(ndev);
2137         struct sh_eth_rxdesc *rxdesc;
2138         int i;
2139
2140         netif_stop_queue(ndev);
2141
2142         netif_err(mdp, timer, ndev,
2143                   "transmit timed out, status %8.8x, resetting...\n",
2144                   sh_eth_read(ndev, EESR));
2145
2146         /* tx_errors count up */
2147         ndev->stats.tx_errors++;
2148
2149         /* Free all the skbuffs in the Rx queue. */
2150         for (i = 0; i < mdp->num_rx_ring; i++) {
2151                 rxdesc = &mdp->rx_ring[i];
2152                 rxdesc->status = 0;
2153                 rxdesc->addr = 0xBADF00D0;
2154                 dev_kfree_skb(mdp->rx_skbuff[i]);
2155                 mdp->rx_skbuff[i] = NULL;
2156         }
2157         for (i = 0; i < mdp->num_tx_ring; i++) {
2158                 dev_kfree_skb(mdp->tx_skbuff[i]);
2159                 mdp->tx_skbuff[i] = NULL;
2160         }
2161
2162         /* device init */
2163         sh_eth_dev_init(ndev, true);
2164 }
2165
2166 /* Packet transmit function */
2167 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2168 {
2169         struct sh_eth_private *mdp = netdev_priv(ndev);
2170         struct sh_eth_txdesc *txdesc;
2171         u32 entry;
2172         unsigned long flags;
2173
2174         spin_lock_irqsave(&mdp->lock, flags);
2175         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2176                 if (!sh_eth_txfree(ndev)) {
2177                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2178                         netif_stop_queue(ndev);
2179                         spin_unlock_irqrestore(&mdp->lock, flags);
2180                         return NETDEV_TX_BUSY;
2181                 }
2182         }
2183         spin_unlock_irqrestore(&mdp->lock, flags);
2184
2185         if (skb_padto(skb, ETH_ZLEN))
2186                 return NETDEV_TX_OK;
2187
2188         entry = mdp->cur_tx % mdp->num_tx_ring;
2189         mdp->tx_skbuff[entry] = skb;
2190         txdesc = &mdp->tx_ring[entry];
2191         /* soft swap. */
2192         if (!mdp->cd->hw_swap)
2193                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2194                                  skb->len + 2);
2195         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2196                                       DMA_TO_DEVICE);
2197         if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2198                 kfree_skb(skb);
2199                 return NETDEV_TX_OK;
2200         }
2201         txdesc->buffer_length = skb->len;
2202
2203         wmb(); /* TACT bit must be set after all the above writes */
2204         if (entry >= mdp->num_tx_ring - 1)
2205                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2206         else
2207                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2208
2209         mdp->cur_tx++;
2210
2211         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2212                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2213
2214         return NETDEV_TX_OK;
2215 }
2216
2217 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2218 {
2219         struct sh_eth_private *mdp = netdev_priv(ndev);
2220
2221         if (sh_eth_is_rz_fast_ether(mdp))
2222                 return &ndev->stats;
2223
2224         if (!mdp->is_opened)
2225                 return &ndev->stats;
2226
2227         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2228         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2229         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2230         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2231         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2232         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2233
2234         if (sh_eth_is_gether(mdp)) {
2235                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2236                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2237                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2238                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2239         } else {
2240                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2241                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2242         }
2243
2244         return &ndev->stats;
2245 }
2246
2247 /* device close function */
2248 static int sh_eth_close(struct net_device *ndev)
2249 {
2250         struct sh_eth_private *mdp = netdev_priv(ndev);
2251
2252         netif_stop_queue(ndev);
2253
2254         /* Serialise with the interrupt handler and NAPI, then disable
2255          * interrupts.  We have to clear the irq_enabled flag first to
2256          * ensure that interrupts won't be re-enabled.
2257          */
2258         mdp->irq_enabled = false;
2259         synchronize_irq(ndev->irq);
2260         napi_disable(&mdp->napi);
2261         sh_eth_write(ndev, 0x0000, EESIPR);
2262
2263         sh_eth_dev_exit(ndev);
2264
2265         /* PHY Disconnect */
2266         if (mdp->phydev) {
2267                 phy_stop(mdp->phydev);
2268                 phy_disconnect(mdp->phydev);
2269                 mdp->phydev = NULL;
2270         }
2271
2272         free_irq(ndev->irq, ndev);
2273
2274         /* Free all the skbuffs in the Rx queue. */
2275         sh_eth_ring_free(ndev);
2276
2277         /* free DMA buffer */
2278         sh_eth_free_dma_buffer(mdp);
2279
2280         pm_runtime_put_sync(&mdp->pdev->dev);
2281
2282         mdp->is_opened = 0;
2283
2284         return 0;
2285 }
2286
2287 /* ioctl to device function */
2288 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2289 {
2290         struct sh_eth_private *mdp = netdev_priv(ndev);
2291         struct phy_device *phydev = mdp->phydev;
2292
2293         if (!netif_running(ndev))
2294                 return -EINVAL;
2295
2296         if (!phydev)
2297                 return -ENODEV;
2298
2299         return phy_mii_ioctl(phydev, rq, cmd);
2300 }
2301
2302 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2303 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2304                                             int entry)
2305 {
2306         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2307 }
2308
2309 static u32 sh_eth_tsu_get_post_mask(int entry)
2310 {
2311         return 0x0f << (28 - ((entry % 8) * 4));
2312 }
2313
2314 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2315 {
2316         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2317 }
2318
2319 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2320                                              int entry)
2321 {
2322         struct sh_eth_private *mdp = netdev_priv(ndev);
2323         u32 tmp;
2324         void *reg_offset;
2325
2326         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2327         tmp = ioread32(reg_offset);
2328         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2329 }
2330
2331 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2332                                               int entry)
2333 {
2334         struct sh_eth_private *mdp = netdev_priv(ndev);
2335         u32 post_mask, ref_mask, tmp;
2336         void *reg_offset;
2337
2338         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2339         post_mask = sh_eth_tsu_get_post_mask(entry);
2340         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2341
2342         tmp = ioread32(reg_offset);
2343         iowrite32(tmp & ~post_mask, reg_offset);
2344
2345         /* If other port enables, the function returns "true" */
2346         return tmp & ref_mask;
2347 }
2348
2349 static int sh_eth_tsu_busy(struct net_device *ndev)
2350 {
2351         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2352         struct sh_eth_private *mdp = netdev_priv(ndev);
2353
2354         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2355                 udelay(10);
2356                 timeout--;
2357                 if (timeout <= 0) {
2358                         netdev_err(ndev, "%s: timeout\n", __func__);
2359                         return -ETIMEDOUT;
2360                 }
2361         }
2362
2363         return 0;
2364 }
2365
2366 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2367                                   const u8 *addr)
2368 {
2369         u32 val;
2370
2371         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2372         iowrite32(val, reg);
2373         if (sh_eth_tsu_busy(ndev) < 0)
2374                 return -EBUSY;
2375
2376         val = addr[4] << 8 | addr[5];
2377         iowrite32(val, reg + 4);
2378         if (sh_eth_tsu_busy(ndev) < 0)
2379                 return -EBUSY;
2380
2381         return 0;
2382 }
2383
2384 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2385 {
2386         u32 val;
2387
2388         val = ioread32(reg);
2389         addr[0] = (val >> 24) & 0xff;
2390         addr[1] = (val >> 16) & 0xff;
2391         addr[2] = (val >> 8) & 0xff;
2392         addr[3] = val & 0xff;
2393         val = ioread32(reg + 4);
2394         addr[4] = (val >> 8) & 0xff;
2395         addr[5] = val & 0xff;
2396 }
2397
2398
2399 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2400 {
2401         struct sh_eth_private *mdp = netdev_priv(ndev);
2402         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2403         int i;
2404         u8 c_addr[ETH_ALEN];
2405
2406         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2407                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2408                 if (ether_addr_equal(addr, c_addr))
2409                         return i;
2410         }
2411
2412         return -ENOENT;
2413 }
2414
2415 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2416 {
2417         u8 blank[ETH_ALEN];
2418         int entry;
2419
2420         memset(blank, 0, sizeof(blank));
2421         entry = sh_eth_tsu_find_entry(ndev, blank);
2422         return (entry < 0) ? -ENOMEM : entry;
2423 }
2424
2425 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2426                                               int entry)
2427 {
2428         struct sh_eth_private *mdp = netdev_priv(ndev);
2429         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2430         int ret;
2431         u8 blank[ETH_ALEN];
2432
2433         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2434                          ~(1 << (31 - entry)), TSU_TEN);
2435
2436         memset(blank, 0, sizeof(blank));
2437         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2438         if (ret < 0)
2439                 return ret;
2440         return 0;
2441 }
2442
2443 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2444 {
2445         struct sh_eth_private *mdp = netdev_priv(ndev);
2446         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2447         int i, ret;
2448
2449         if (!mdp->cd->tsu)
2450                 return 0;
2451
2452         i = sh_eth_tsu_find_entry(ndev, addr);
2453         if (i < 0) {
2454                 /* No entry found, create one */
2455                 i = sh_eth_tsu_find_empty(ndev);
2456                 if (i < 0)
2457                         return -ENOMEM;
2458                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2459                 if (ret < 0)
2460                         return ret;
2461
2462                 /* Enable the entry */
2463                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2464                                  (1 << (31 - i)), TSU_TEN);
2465         }
2466
2467         /* Entry found or created, enable POST */
2468         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2469
2470         return 0;
2471 }
2472
2473 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2474 {
2475         struct sh_eth_private *mdp = netdev_priv(ndev);
2476         int i, ret;
2477
2478         if (!mdp->cd->tsu)
2479                 return 0;
2480
2481         i = sh_eth_tsu_find_entry(ndev, addr);
2482         if (i) {
2483                 /* Entry found */
2484                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2485                         goto done;
2486
2487                 /* Disable the entry if both ports was disabled */
2488                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2489                 if (ret < 0)
2490                         return ret;
2491         }
2492 done:
2493         return 0;
2494 }
2495
2496 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2497 {
2498         struct sh_eth_private *mdp = netdev_priv(ndev);
2499         int i, ret;
2500
2501         if (!mdp->cd->tsu)
2502                 return 0;
2503
2504         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2505                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2506                         continue;
2507
2508                 /* Disable the entry if both ports was disabled */
2509                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2510                 if (ret < 0)
2511                         return ret;
2512         }
2513
2514         return 0;
2515 }
2516
2517 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2518 {
2519         struct sh_eth_private *mdp = netdev_priv(ndev);
2520         u8 addr[ETH_ALEN];
2521         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2522         int i;
2523
2524         if (!mdp->cd->tsu)
2525                 return;
2526
2527         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2528                 sh_eth_tsu_read_entry(reg_offset, addr);
2529                 if (is_multicast_ether_addr(addr))
2530                         sh_eth_tsu_del_entry(ndev, addr);
2531         }
2532 }
2533
2534 /* Update promiscuous flag and multicast filter */
2535 static void sh_eth_set_rx_mode(struct net_device *ndev)
2536 {
2537         struct sh_eth_private *mdp = netdev_priv(ndev);
2538         u32 ecmr_bits;
2539         int mcast_all = 0;
2540         unsigned long flags;
2541
2542         spin_lock_irqsave(&mdp->lock, flags);
2543         /* Initial condition is MCT = 1, PRM = 0.
2544          * Depending on ndev->flags, set PRM or clear MCT
2545          */
2546         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2547         if (mdp->cd->tsu)
2548                 ecmr_bits |= ECMR_MCT;
2549
2550         if (!(ndev->flags & IFF_MULTICAST)) {
2551                 sh_eth_tsu_purge_mcast(ndev);
2552                 mcast_all = 1;
2553         }
2554         if (ndev->flags & IFF_ALLMULTI) {
2555                 sh_eth_tsu_purge_mcast(ndev);
2556                 ecmr_bits &= ~ECMR_MCT;
2557                 mcast_all = 1;
2558         }
2559
2560         if (ndev->flags & IFF_PROMISC) {
2561                 sh_eth_tsu_purge_all(ndev);
2562                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2563         } else if (mdp->cd->tsu) {
2564                 struct netdev_hw_addr *ha;
2565                 netdev_for_each_mc_addr(ha, ndev) {
2566                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2567                                 continue;
2568
2569                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2570                                 if (!mcast_all) {
2571                                         sh_eth_tsu_purge_mcast(ndev);
2572                                         ecmr_bits &= ~ECMR_MCT;
2573                                         mcast_all = 1;
2574                                 }
2575                         }
2576                 }
2577         }
2578
2579         /* update the ethernet mode */
2580         sh_eth_write(ndev, ecmr_bits, ECMR);
2581
2582         spin_unlock_irqrestore(&mdp->lock, flags);
2583 }
2584
2585 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2586 {
2587         if (!mdp->port)
2588                 return TSU_VTAG0;
2589         else
2590                 return TSU_VTAG1;
2591 }
2592
2593 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2594                                   __be16 proto, u16 vid)
2595 {
2596         struct sh_eth_private *mdp = netdev_priv(ndev);
2597         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2598
2599         if (unlikely(!mdp->cd->tsu))
2600                 return -EPERM;
2601
2602         /* No filtering if vid = 0 */
2603         if (!vid)
2604                 return 0;
2605
2606         mdp->vlan_num_ids++;
2607
2608         /* The controller has one VLAN tag HW filter. So, if the filter is
2609          * already enabled, the driver disables it and the filte
2610          */
2611         if (mdp->vlan_num_ids > 1) {
2612                 /* disable VLAN filter */
2613                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2614                 return 0;
2615         }
2616
2617         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2618                          vtag_reg_index);
2619
2620         return 0;
2621 }
2622
2623 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2624                                    __be16 proto, u16 vid)
2625 {
2626         struct sh_eth_private *mdp = netdev_priv(ndev);
2627         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2628
2629         if (unlikely(!mdp->cd->tsu))
2630                 return -EPERM;
2631
2632         /* No filtering if vid = 0 */
2633         if (!vid)
2634                 return 0;
2635
2636         mdp->vlan_num_ids--;
2637         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2638
2639         return 0;
2640 }
2641
2642 /* SuperH's TSU register init function */
2643 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2644 {
2645         if (sh_eth_is_rz_fast_ether(mdp)) {
2646                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2647                 return;
2648         }
2649
2650         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2651         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2652         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2653         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2654         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2655         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2656         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2657         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2658         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2659         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2660         if (sh_eth_is_gether(mdp)) {
2661                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2662                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2663         } else {
2664                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2665                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2666         }
2667         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2668         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2669         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2670         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2671         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2672         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2673         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2674 }
2675
2676 /* MDIO bus release function */
2677 static int sh_mdio_release(struct sh_eth_private *mdp)
2678 {
2679         /* unregister mdio bus */
2680         mdiobus_unregister(mdp->mii_bus);
2681
2682         /* free bitbang info */
2683         free_mdio_bitbang(mdp->mii_bus);
2684
2685         return 0;
2686 }
2687
2688 /* MDIO bus init function */
2689 static int sh_mdio_init(struct sh_eth_private *mdp,
2690                         struct sh_eth_plat_data *pd)
2691 {
2692         int ret, i;
2693         struct bb_info *bitbang;
2694         struct platform_device *pdev = mdp->pdev;
2695         struct device *dev = &mdp->pdev->dev;
2696
2697         /* create bit control struct for PHY */
2698         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2699         if (!bitbang)
2700                 return -ENOMEM;
2701
2702         /* bitbang init */
2703         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2704         bitbang->set_gate = pd->set_mdio_gate;
2705         bitbang->mdi_msk = PIR_MDI;
2706         bitbang->mdo_msk = PIR_MDO;
2707         bitbang->mmd_msk = PIR_MMD;
2708         bitbang->mdc_msk = PIR_MDC;
2709         bitbang->ctrl.ops = &bb_ops;
2710
2711         /* MII controller setting */
2712         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2713         if (!mdp->mii_bus)
2714                 return -ENOMEM;
2715
2716         /* Hook up MII support for ethtool */
2717         mdp->mii_bus->name = "sh_mii";
2718         mdp->mii_bus->parent = dev;
2719         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2720                  pdev->name, pdev->id);
2721
2722         /* PHY IRQ */
2723         mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2724                                                GFP_KERNEL);
2725         if (!mdp->mii_bus->irq) {
2726                 ret = -ENOMEM;
2727                 goto out_free_bus;
2728         }
2729
2730         /* register MDIO bus */
2731         if (dev->of_node) {
2732                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2733         } else {
2734                 for (i = 0; i < PHY_MAX_ADDR; i++)
2735                         mdp->mii_bus->irq[i] = PHY_POLL;
2736                 if (pd->phy_irq > 0)
2737                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2738
2739                 ret = mdiobus_register(mdp->mii_bus);
2740         }
2741
2742         if (ret)
2743                 goto out_free_bus;
2744
2745         return 0;
2746
2747 out_free_bus:
2748         free_mdio_bitbang(mdp->mii_bus);
2749         return ret;
2750 }
2751
2752 static const u16 *sh_eth_get_register_offset(int register_type)
2753 {
2754         const u16 *reg_offset = NULL;
2755
2756         switch (register_type) {
2757         case SH_ETH_REG_GIGABIT:
2758                 reg_offset = sh_eth_offset_gigabit;
2759                 break;
2760         case SH_ETH_REG_FAST_RZ:
2761                 reg_offset = sh_eth_offset_fast_rz;
2762                 break;
2763         case SH_ETH_REG_FAST_RCAR:
2764                 reg_offset = sh_eth_offset_fast_rcar;
2765                 break;
2766         case SH_ETH_REG_FAST_SH4:
2767                 reg_offset = sh_eth_offset_fast_sh4;
2768                 break;
2769         case SH_ETH_REG_FAST_SH3_SH2:
2770                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2771                 break;
2772         default:
2773                 break;
2774         }
2775
2776         return reg_offset;
2777 }
2778
2779 static const struct net_device_ops sh_eth_netdev_ops = {
2780         .ndo_open               = sh_eth_open,
2781         .ndo_stop               = sh_eth_close,
2782         .ndo_start_xmit         = sh_eth_start_xmit,
2783         .ndo_get_stats          = sh_eth_get_stats,
2784         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2785         .ndo_tx_timeout         = sh_eth_tx_timeout,
2786         .ndo_do_ioctl           = sh_eth_do_ioctl,
2787         .ndo_validate_addr      = eth_validate_addr,
2788         .ndo_set_mac_address    = eth_mac_addr,
2789         .ndo_change_mtu         = eth_change_mtu,
2790 };
2791
2792 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2793         .ndo_open               = sh_eth_open,
2794         .ndo_stop               = sh_eth_close,
2795         .ndo_start_xmit         = sh_eth_start_xmit,
2796         .ndo_get_stats          = sh_eth_get_stats,
2797         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2798         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2799         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2800         .ndo_tx_timeout         = sh_eth_tx_timeout,
2801         .ndo_do_ioctl           = sh_eth_do_ioctl,
2802         .ndo_validate_addr      = eth_validate_addr,
2803         .ndo_set_mac_address    = eth_mac_addr,
2804         .ndo_change_mtu         = eth_change_mtu,
2805 };
2806
2807 #ifdef CONFIG_OF
2808 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2809 {
2810         struct device_node *np = dev->of_node;
2811         struct sh_eth_plat_data *pdata;
2812         const char *mac_addr;
2813
2814         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2815         if (!pdata)
2816                 return NULL;
2817
2818         pdata->phy_interface = of_get_phy_mode(np);
2819
2820         mac_addr = of_get_mac_address(np);
2821         if (mac_addr)
2822                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2823
2824         pdata->no_ether_link =
2825                 of_property_read_bool(np, "renesas,no-ether-link");
2826         pdata->ether_link_active_low =
2827                 of_property_read_bool(np, "renesas,ether-link-active-low");
2828
2829         return pdata;
2830 }
2831
2832 static const struct of_device_id sh_eth_match_table[] = {
2833         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2834         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2835         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2836         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2837         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2838         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2839         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2840         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2841         { }
2842 };
2843 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2844 #else
2845 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2846 {
2847         return NULL;
2848 }
2849 #endif
2850
2851 static int sh_eth_drv_probe(struct platform_device *pdev)
2852 {
2853         int ret, devno = 0;
2854         struct resource *res;
2855         struct net_device *ndev = NULL;
2856         struct sh_eth_private *mdp = NULL;
2857         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2858         const struct platform_device_id *id = platform_get_device_id(pdev);
2859
2860         /* get base addr */
2861         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2862
2863         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2864         if (!ndev)
2865                 return -ENOMEM;
2866
2867         pm_runtime_enable(&pdev->dev);
2868         pm_runtime_get_sync(&pdev->dev);
2869
2870         devno = pdev->id;
2871         if (devno < 0)
2872                 devno = 0;
2873
2874         ndev->dma = -1;
2875         ret = platform_get_irq(pdev, 0);
2876         if (ret < 0) {
2877                 ret = -ENODEV;
2878                 goto out_release;
2879         }
2880         ndev->irq = ret;
2881
2882         SET_NETDEV_DEV(ndev, &pdev->dev);
2883
2884         mdp = netdev_priv(ndev);
2885         mdp->num_tx_ring = TX_RING_SIZE;
2886         mdp->num_rx_ring = RX_RING_SIZE;
2887         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2888         if (IS_ERR(mdp->addr)) {
2889                 ret = PTR_ERR(mdp->addr);
2890                 goto out_release;
2891         }
2892
2893         ndev->base_addr = res->start;
2894
2895         spin_lock_init(&mdp->lock);
2896         mdp->pdev = pdev;
2897
2898         if (pdev->dev.of_node)
2899                 pd = sh_eth_parse_dt(&pdev->dev);
2900         if (!pd) {
2901                 dev_err(&pdev->dev, "no platform data\n");
2902                 ret = -EINVAL;
2903                 goto out_release;
2904         }
2905
2906         /* get PHY ID */
2907         mdp->phy_id = pd->phy;
2908         mdp->phy_interface = pd->phy_interface;
2909         /* EDMAC endian */
2910         mdp->edmac_endian = pd->edmac_endian;
2911         mdp->no_ether_link = pd->no_ether_link;
2912         mdp->ether_link_active_low = pd->ether_link_active_low;
2913
2914         /* set cpu data */
2915         if (id) {
2916                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2917         } else  {
2918                 const struct of_device_id *match;
2919
2920                 match = of_match_device(of_match_ptr(sh_eth_match_table),
2921                                         &pdev->dev);
2922                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2923         }
2924         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2925         if (!mdp->reg_offset) {
2926                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2927                         mdp->cd->register_type);
2928                 ret = -EINVAL;
2929                 goto out_release;
2930         }
2931         sh_eth_set_default_cpu_data(mdp->cd);
2932
2933         /* set function */
2934         if (mdp->cd->tsu)
2935                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2936         else
2937                 ndev->netdev_ops = &sh_eth_netdev_ops;
2938         ndev->ethtool_ops = &sh_eth_ethtool_ops;
2939         ndev->watchdog_timeo = TX_TIMEOUT;
2940
2941         /* debug message level */
2942         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2943
2944         /* read and set MAC address */
2945         read_mac_address(ndev, pd->mac_addr);
2946         if (!is_valid_ether_addr(ndev->dev_addr)) {
2947                 dev_warn(&pdev->dev,
2948                          "no valid MAC address supplied, using a random one.\n");
2949                 eth_hw_addr_random(ndev);
2950         }
2951
2952         /* ioremap the TSU registers */
2953         if (mdp->cd->tsu) {
2954                 struct resource *rtsu;
2955                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2956                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2957                 if (IS_ERR(mdp->tsu_addr)) {
2958                         ret = PTR_ERR(mdp->tsu_addr);
2959                         goto out_release;
2960                 }
2961                 mdp->port = devno % 2;
2962                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2963         }
2964
2965         /* initialize first or needed device */
2966         if (!devno || pd->needs_init) {
2967                 if (mdp->cd->chip_reset)
2968                         mdp->cd->chip_reset(ndev);
2969
2970                 if (mdp->cd->tsu) {
2971                         /* TSU init (Init only)*/
2972                         sh_eth_tsu_init(mdp);
2973                 }
2974         }
2975
2976         if (mdp->cd->rmiimode)
2977                 sh_eth_write(ndev, 0x1, RMIIMODE);
2978
2979         /* MDIO bus init */
2980         ret = sh_mdio_init(mdp, pd);
2981         if (ret) {
2982                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2983                 goto out_release;
2984         }
2985
2986         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2987
2988         /* network device register */
2989         ret = register_netdev(ndev);
2990         if (ret)
2991                 goto out_napi_del;
2992
2993         /* print device information */
2994         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2995                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2996
2997         pm_runtime_put(&pdev->dev);
2998         platform_set_drvdata(pdev, ndev);
2999
3000         return ret;
3001
3002 out_napi_del:
3003         netif_napi_del(&mdp->napi);
3004         sh_mdio_release(mdp);
3005
3006 out_release:
3007         /* net_dev free */
3008         if (ndev)
3009                 free_netdev(ndev);
3010
3011         pm_runtime_put(&pdev->dev);
3012         pm_runtime_disable(&pdev->dev);
3013         return ret;
3014 }
3015
3016 static int sh_eth_drv_remove(struct platform_device *pdev)
3017 {
3018         struct net_device *ndev = platform_get_drvdata(pdev);
3019         struct sh_eth_private *mdp = netdev_priv(ndev);
3020
3021         unregister_netdev(ndev);
3022         netif_napi_del(&mdp->napi);
3023         sh_mdio_release(mdp);
3024         pm_runtime_disable(&pdev->dev);
3025         free_netdev(ndev);
3026
3027         return 0;
3028 }
3029
3030 #ifdef CONFIG_PM
3031 #ifdef CONFIG_PM_SLEEP
3032 static int sh_eth_suspend(struct device *dev)
3033 {
3034         struct net_device *ndev = dev_get_drvdata(dev);
3035         int ret = 0;
3036
3037         if (netif_running(ndev)) {
3038                 netif_device_detach(ndev);
3039                 ret = sh_eth_close(ndev);
3040         }
3041
3042         return ret;
3043 }
3044
3045 static int sh_eth_resume(struct device *dev)
3046 {
3047         struct net_device *ndev = dev_get_drvdata(dev);
3048         int ret = 0;
3049
3050         if (netif_running(ndev)) {
3051                 ret = sh_eth_open(ndev);
3052                 if (ret < 0)
3053                         return ret;
3054                 netif_device_attach(ndev);
3055         }
3056
3057         return ret;
3058 }
3059 #endif
3060
3061 static int sh_eth_runtime_nop(struct device *dev)
3062 {
3063         /* Runtime PM callback shared between ->runtime_suspend()
3064          * and ->runtime_resume(). Simply returns success.
3065          *
3066          * This driver re-initializes all registers after
3067          * pm_runtime_get_sync() anyway so there is no need
3068          * to save and restore registers here.
3069          */
3070         return 0;
3071 }
3072
3073 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3074         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3075         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3076 };
3077 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3078 #else
3079 #define SH_ETH_PM_OPS NULL
3080 #endif
3081
3082 static struct platform_device_id sh_eth_id_table[] = {
3083         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3084         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3085         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3086         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3087         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3088         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3089         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3090         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3091         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3092         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3093         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3094         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3095         { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3096         { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3097         { }
3098 };
3099 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3100
3101 static struct platform_driver sh_eth_driver = {
3102         .probe = sh_eth_drv_probe,
3103         .remove = sh_eth_drv_remove,
3104         .id_table = sh_eth_id_table,
3105         .driver = {
3106                    .name = CARDNAME,
3107                    .pm = SH_ETH_PM_OPS,
3108                    .of_match_table = of_match_ptr(sh_eth_match_table),
3109         },
3110 };
3111
3112 module_platform_driver(sh_eth_driver);
3113
3114 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3115 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3116 MODULE_LICENSE("GPL v2");