2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
42 enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
47 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
48 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
50 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
51 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
53 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
54 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
56 /* how long wait to wait for target to initialise, in ms */
57 #define ATH10K_PCI_TARGET_WAIT 3000
58 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
60 #define QCA988X_2_0_DEVICE_ID (0x003c)
61 #define QCA6164_2_1_DEVICE_ID (0x0041)
62 #define QCA6174_2_1_DEVICE_ID (0x003e)
63 #define QCA99X0_2_0_DEVICE_ID (0x0040)
64 #define QCA9377_1_0_DEVICE_ID (0x0042)
66 static const struct pci_device_id ath10k_pci_id_table[] = {
67 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
68 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
69 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
70 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
71 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
75 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
76 /* QCA988X pre 2.0 chips are not supported because they need some nasty
77 * hacks. ath10k doesn't have them and these devices crash horribly
80 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
82 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
83 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
84 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
85 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
86 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
88 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
89 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
90 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
91 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
92 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
94 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
95 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
98 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
99 static int ath10k_pci_cold_reset(struct ath10k *ar);
100 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
101 static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
102 static int ath10k_pci_init_irq(struct ath10k *ar);
103 static int ath10k_pci_deinit_irq(struct ath10k *ar);
104 static int ath10k_pci_request_irq(struct ath10k *ar);
105 static void ath10k_pci_free_irq(struct ath10k *ar);
106 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
107 struct ath10k_ce_pipe *rx_pipe,
108 struct bmi_xfer *xfer);
109 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
110 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
111 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
112 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
113 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
115 static const struct ce_attr host_ce_config_wlan[] = {
116 /* CE0: host->target HTC control and raw streams */
118 .flags = CE_ATTR_FLAGS,
122 .send_cb = ath10k_pci_htc_tx_cb,
125 /* CE1: target->host HTT + HTC control */
127 .flags = CE_ATTR_FLAGS,
130 .dest_nentries = 512,
131 .recv_cb = ath10k_pci_htc_rx_cb,
134 /* CE2: target->host WMI */
136 .flags = CE_ATTR_FLAGS,
139 .dest_nentries = 128,
140 .recv_cb = ath10k_pci_htc_rx_cb,
143 /* CE3: host->target WMI */
145 .flags = CE_ATTR_FLAGS,
149 .send_cb = ath10k_pci_htc_tx_cb,
152 /* CE4: host->target HTT */
154 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
155 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
158 .send_cb = ath10k_pci_htt_tx_cb,
161 /* CE5: target->host HTT (HIF->HTT) */
163 .flags = CE_ATTR_FLAGS,
166 .dest_nentries = 512,
167 .recv_cb = ath10k_pci_htt_rx_cb,
170 /* CE6: target autonomous hif_memcpy */
172 .flags = CE_ATTR_FLAGS,
178 /* CE7: ce_diag, the Diagnostic Window */
180 .flags = CE_ATTR_FLAGS,
182 .src_sz_max = DIAG_TRANSFER_LIMIT,
186 /* CE8: target->host pktlog */
188 .flags = CE_ATTR_FLAGS,
191 .dest_nentries = 128,
194 /* CE9 target autonomous qcache memcpy */
196 .flags = CE_ATTR_FLAGS,
202 /* CE10: target autonomous hif memcpy */
204 .flags = CE_ATTR_FLAGS,
210 /* CE11: target autonomous hif memcpy */
212 .flags = CE_ATTR_FLAGS,
219 /* Target firmware's Copy Engine configuration. */
220 static const struct ce_pipe_config target_ce_config_wlan[] = {
221 /* CE0: host->target HTC control and raw streams */
223 .pipenum = __cpu_to_le32(0),
224 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
225 .nentries = __cpu_to_le32(32),
226 .nbytes_max = __cpu_to_le32(256),
227 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
228 .reserved = __cpu_to_le32(0),
231 /* CE1: target->host HTT + HTC control */
233 .pipenum = __cpu_to_le32(1),
234 .pipedir = __cpu_to_le32(PIPEDIR_IN),
235 .nentries = __cpu_to_le32(32),
236 .nbytes_max = __cpu_to_le32(2048),
237 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
238 .reserved = __cpu_to_le32(0),
241 /* CE2: target->host WMI */
243 .pipenum = __cpu_to_le32(2),
244 .pipedir = __cpu_to_le32(PIPEDIR_IN),
245 .nentries = __cpu_to_le32(64),
246 .nbytes_max = __cpu_to_le32(2048),
247 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
248 .reserved = __cpu_to_le32(0),
251 /* CE3: host->target WMI */
253 .pipenum = __cpu_to_le32(3),
254 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
255 .nentries = __cpu_to_le32(32),
256 .nbytes_max = __cpu_to_le32(2048),
257 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
258 .reserved = __cpu_to_le32(0),
261 /* CE4: host->target HTT */
263 .pipenum = __cpu_to_le32(4),
264 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
265 .nentries = __cpu_to_le32(256),
266 .nbytes_max = __cpu_to_le32(256),
267 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
268 .reserved = __cpu_to_le32(0),
271 /* NB: 50% of src nentries, since tx has 2 frags */
273 /* CE5: target->host HTT (HIF->HTT) */
275 .pipenum = __cpu_to_le32(5),
276 .pipedir = __cpu_to_le32(PIPEDIR_IN),
277 .nentries = __cpu_to_le32(32),
278 .nbytes_max = __cpu_to_le32(512),
279 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
280 .reserved = __cpu_to_le32(0),
283 /* CE6: Reserved for target autonomous hif_memcpy */
285 .pipenum = __cpu_to_le32(6),
286 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
287 .nentries = __cpu_to_le32(32),
288 .nbytes_max = __cpu_to_le32(4096),
289 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
290 .reserved = __cpu_to_le32(0),
293 /* CE7 used only by Host */
295 .pipenum = __cpu_to_le32(7),
296 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
297 .nentries = __cpu_to_le32(0),
298 .nbytes_max = __cpu_to_le32(0),
299 .flags = __cpu_to_le32(0),
300 .reserved = __cpu_to_le32(0),
303 /* CE8 target->host packtlog */
305 .pipenum = __cpu_to_le32(8),
306 .pipedir = __cpu_to_le32(PIPEDIR_IN),
307 .nentries = __cpu_to_le32(64),
308 .nbytes_max = __cpu_to_le32(2048),
309 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
310 .reserved = __cpu_to_le32(0),
313 /* CE9 target autonomous qcache memcpy */
315 .pipenum = __cpu_to_le32(9),
316 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
317 .nentries = __cpu_to_le32(32),
318 .nbytes_max = __cpu_to_le32(2048),
319 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
320 .reserved = __cpu_to_le32(0),
323 /* It not necessary to send target wlan configuration for CE10 & CE11
324 * as these CEs are not actively used in target.
329 * Map from service/endpoint to Copy Engine.
330 * This table is derived from the CE_PCI TABLE, above.
331 * It is passed to the Target at startup for use by firmware.
333 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
335 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
336 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
340 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
341 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
345 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
346 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
350 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
351 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
355 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
356 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
360 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
361 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
365 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
366 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
370 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
371 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
375 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
376 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
380 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
381 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
385 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
386 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
390 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
391 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
395 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
396 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
400 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
401 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
405 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
406 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
410 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
411 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
415 /* (Additions here) */
424 static bool ath10k_pci_is_awake(struct ath10k *ar)
426 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
427 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
430 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
433 static void __ath10k_pci_wake(struct ath10k *ar)
435 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
437 lockdep_assert_held(&ar_pci->ps_lock);
439 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
440 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
442 iowrite32(PCIE_SOC_WAKE_V_MASK,
443 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
444 PCIE_SOC_WAKE_ADDRESS);
447 static void __ath10k_pci_sleep(struct ath10k *ar)
449 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
451 lockdep_assert_held(&ar_pci->ps_lock);
453 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
454 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
456 iowrite32(PCIE_SOC_WAKE_RESET,
457 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
458 PCIE_SOC_WAKE_ADDRESS);
459 ar_pci->ps_awake = false;
462 static int ath10k_pci_wake_wait(struct ath10k *ar)
467 while (tot_delay < PCIE_WAKE_TIMEOUT) {
468 if (ath10k_pci_is_awake(ar)) {
469 if (tot_delay > PCIE_WAKE_LATE_US)
470 ath10k_warn(ar, "device wakeup took %d ms which is unusally long, otherwise it works normally.\n",
476 tot_delay += curr_delay;
485 static int ath10k_pci_force_wake(struct ath10k *ar)
487 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
491 spin_lock_irqsave(&ar_pci->ps_lock, flags);
493 if (!ar_pci->ps_awake) {
494 iowrite32(PCIE_SOC_WAKE_V_MASK,
495 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
496 PCIE_SOC_WAKE_ADDRESS);
498 ret = ath10k_pci_wake_wait(ar);
500 ar_pci->ps_awake = true;
503 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
508 static void ath10k_pci_force_sleep(struct ath10k *ar)
510 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
513 spin_lock_irqsave(&ar_pci->ps_lock, flags);
515 iowrite32(PCIE_SOC_WAKE_RESET,
516 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
517 PCIE_SOC_WAKE_ADDRESS);
518 ar_pci->ps_awake = false;
520 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
523 static int ath10k_pci_wake(struct ath10k *ar)
525 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
529 if (ar_pci->pci_ps == 0)
532 spin_lock_irqsave(&ar_pci->ps_lock, flags);
534 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
535 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
537 /* This function can be called very frequently. To avoid excessive
538 * CPU stalls for MMIO reads use a cache var to hold the device state.
540 if (!ar_pci->ps_awake) {
541 __ath10k_pci_wake(ar);
543 ret = ath10k_pci_wake_wait(ar);
545 ar_pci->ps_awake = true;
549 ar_pci->ps_wake_refcount++;
550 WARN_ON(ar_pci->ps_wake_refcount == 0);
553 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
558 static void ath10k_pci_sleep(struct ath10k *ar)
560 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
563 if (ar_pci->pci_ps == 0)
566 spin_lock_irqsave(&ar_pci->ps_lock, flags);
568 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
569 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
571 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
574 ar_pci->ps_wake_refcount--;
576 mod_timer(&ar_pci->ps_timer, jiffies +
577 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
580 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
583 static void ath10k_pci_ps_timer(unsigned long ptr)
585 struct ath10k *ar = (void *)ptr;
586 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
589 spin_lock_irqsave(&ar_pci->ps_lock, flags);
591 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
592 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
594 if (ar_pci->ps_wake_refcount > 0)
597 __ath10k_pci_sleep(ar);
600 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
603 static void ath10k_pci_sleep_sync(struct ath10k *ar)
605 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
608 if (ar_pci->pci_ps == 0) {
609 ath10k_pci_force_sleep(ar);
613 del_timer_sync(&ar_pci->ps_timer);
615 spin_lock_irqsave(&ar_pci->ps_lock, flags);
616 WARN_ON(ar_pci->ps_wake_refcount > 0);
617 __ath10k_pci_sleep(ar);
618 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
621 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
623 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
626 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
627 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
628 offset, offset + sizeof(value), ar_pci->mem_len);
632 ret = ath10k_pci_wake(ar);
634 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
639 iowrite32(value, ar_pci->mem + offset);
640 ath10k_pci_sleep(ar);
643 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
645 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
649 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
650 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
651 offset, offset + sizeof(val), ar_pci->mem_len);
655 ret = ath10k_pci_wake(ar);
657 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
662 val = ioread32(ar_pci->mem + offset);
663 ath10k_pci_sleep(ar);
668 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
670 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
673 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
675 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
678 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
680 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
683 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
685 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
688 static bool ath10k_pci_irq_pending(struct ath10k *ar)
692 /* Check if the shared legacy irq is for us */
693 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
694 PCIE_INTR_CAUSE_ADDRESS);
695 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
701 static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
703 /* IMPORTANT: INTR_CLR register has to be set after
704 * INTR_ENABLE is set to 0, otherwise interrupt can not be
706 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
708 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
709 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
711 /* IMPORTANT: this extra read transaction is required to
712 * flush the posted write buffer. */
713 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
714 PCIE_INTR_ENABLE_ADDRESS);
717 static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
719 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
720 PCIE_INTR_ENABLE_ADDRESS,
721 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
723 /* IMPORTANT: this extra read transaction is required to
724 * flush the posted write buffer. */
725 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
726 PCIE_INTR_ENABLE_ADDRESS);
729 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
731 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
733 if (ar_pci->num_msi_intrs > 1)
736 if (ar_pci->num_msi_intrs == 1)
742 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
744 struct ath10k *ar = pipe->hif_ce_state;
745 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
746 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
751 skb = dev_alloc_skb(pipe->buf_sz);
755 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
757 paddr = dma_map_single(ar->dev, skb->data,
758 skb->len + skb_tailroom(skb),
760 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
761 ath10k_warn(ar, "failed to dma map pci rx buf\n");
762 dev_kfree_skb_any(skb);
766 ATH10K_SKB_RXCB(skb)->paddr = paddr;
768 spin_lock_bh(&ar_pci->ce_lock);
769 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
770 spin_unlock_bh(&ar_pci->ce_lock);
772 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
774 dev_kfree_skb_any(skb);
781 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
783 struct ath10k *ar = pipe->hif_ce_state;
784 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
785 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
788 if (pipe->buf_sz == 0)
791 if (!ce_pipe->dest_ring)
794 spin_lock_bh(&ar_pci->ce_lock);
795 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
796 spin_unlock_bh(&ar_pci->ce_lock);
798 ret = __ath10k_pci_rx_post_buf(pipe);
802 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
803 mod_timer(&ar_pci->rx_post_retry, jiffies +
804 ATH10K_PCI_RX_POST_RETRY_MS);
810 static void ath10k_pci_rx_post(struct ath10k *ar)
812 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
815 for (i = 0; i < CE_COUNT; i++)
816 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
819 static void ath10k_pci_rx_replenish_retry(unsigned long ptr)
821 struct ath10k *ar = (void *)ptr;
823 ath10k_pci_rx_post(ar);
826 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
830 switch (ar->hw_rev) {
831 case ATH10K_HW_QCA988X:
832 case ATH10K_HW_QCA6174:
833 case ATH10K_HW_QCA9377:
834 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
838 case ATH10K_HW_QCA99X0:
839 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
843 val |= 0x100000 | (addr & 0xfffff);
848 * Diagnostic read/write access is provided for startup/config/debug usage.
849 * Caller must guarantee proper alignment, when applicable, and single user
852 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
855 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
858 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
861 struct ath10k_ce_pipe *ce_diag;
862 /* Host buffer address in CE space */
864 dma_addr_t ce_data_base = 0;
865 void *data_buf = NULL;
868 spin_lock_bh(&ar_pci->ce_lock);
870 ce_diag = ar_pci->ce_diag;
873 * Allocate a temporary bounce buffer to hold caller's data
874 * to be DMA'ed from Target. This guarantees
875 * 1) 4-byte alignment
876 * 2) Buffer in DMA-able space
878 orig_nbytes = nbytes;
879 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
888 memset(data_buf, 0, orig_nbytes);
890 remaining_bytes = orig_nbytes;
891 ce_data = ce_data_base;
892 while (remaining_bytes) {
893 nbytes = min_t(unsigned int, remaining_bytes,
894 DIAG_TRANSFER_LIMIT);
896 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
900 /* Request CE to send from Target(!) address to Host buffer */
902 * The address supplied by the caller is in the
903 * Target CPU virtual address space.
905 * In order to use this address with the diagnostic CE,
906 * convert it from Target CPU virtual address space
907 * to CE address space
909 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
911 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
917 while (ath10k_ce_completed_send_next_nolock(ce_diag,
920 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
927 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
932 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
938 if (nbytes != completed_nbytes) {
943 if (buf != ce_data) {
948 remaining_bytes -= nbytes;
955 memcpy(data, data_buf, orig_nbytes);
957 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
961 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
964 spin_unlock_bh(&ar_pci->ce_lock);
969 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
974 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
975 *value = __le32_to_cpu(val);
980 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
986 host_addr = host_interest_item_address(src);
988 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
990 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
995 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
997 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1005 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1006 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1008 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1009 const void *data, int nbytes)
1011 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1014 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
1017 struct ath10k_ce_pipe *ce_diag;
1018 void *data_buf = NULL;
1019 u32 ce_data; /* Host buffer address in CE space */
1020 dma_addr_t ce_data_base = 0;
1023 spin_lock_bh(&ar_pci->ce_lock);
1025 ce_diag = ar_pci->ce_diag;
1028 * Allocate a temporary bounce buffer to hold caller's data
1029 * to be DMA'ed to Target. This guarantees
1030 * 1) 4-byte alignment
1031 * 2) Buffer in DMA-able space
1033 orig_nbytes = nbytes;
1034 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1043 /* Copy caller's data to allocated DMA buf */
1044 memcpy(data_buf, data, orig_nbytes);
1047 * The address supplied by the caller is in the
1048 * Target CPU virtual address space.
1050 * In order to use this address with the diagnostic CE,
1052 * Target CPU virtual address space
1056 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1058 remaining_bytes = orig_nbytes;
1059 ce_data = ce_data_base;
1060 while (remaining_bytes) {
1061 /* FIXME: check cast */
1062 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1064 /* Set up to receive directly into Target(!) address */
1065 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address);
1070 * Request CE to send caller-supplied data that
1071 * was copied to bounce buffer to Target(!) address.
1073 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
1079 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1083 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1090 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
1092 &id, &flags) != 0) {
1095 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1101 if (nbytes != completed_nbytes) {
1106 if (buf != address) {
1111 remaining_bytes -= nbytes;
1118 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
1123 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1126 spin_unlock_bh(&ar_pci->ce_lock);
1131 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1133 __le32 val = __cpu_to_le32(value);
1135 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1138 /* Called by lower (CE) layer when a send to Target completes. */
1139 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1141 struct ath10k *ar = ce_state->ar;
1142 struct sk_buff_head list;
1143 struct sk_buff *skb;
1145 __skb_queue_head_init(&list);
1146 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1147 /* no need to call tx completion for NULL pointers */
1151 __skb_queue_tail(&list, skb);
1154 while ((skb = __skb_dequeue(&list)))
1155 ath10k_htc_tx_completion_handler(ar, skb);
1158 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1159 void (*callback)(struct ath10k *ar,
1160 struct sk_buff *skb))
1162 struct ath10k *ar = ce_state->ar;
1163 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1164 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1165 struct sk_buff *skb;
1166 struct sk_buff_head list;
1167 void *transfer_context;
1169 unsigned int nbytes, max_nbytes;
1170 unsigned int transfer_id;
1173 __skb_queue_head_init(&list);
1174 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1175 &ce_data, &nbytes, &transfer_id,
1177 skb = transfer_context;
1178 max_nbytes = skb->len + skb_tailroom(skb);
1179 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1180 max_nbytes, DMA_FROM_DEVICE);
1182 if (unlikely(max_nbytes < nbytes)) {
1183 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1184 nbytes, max_nbytes);
1185 dev_kfree_skb_any(skb);
1189 skb_put(skb, nbytes);
1190 __skb_queue_tail(&list, skb);
1193 while ((skb = __skb_dequeue(&list))) {
1194 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1195 ce_state->id, skb->len);
1196 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1197 skb->data, skb->len);
1202 ath10k_pci_rx_post_pipe(pipe_info);
1205 /* Called by lower (CE) layer when data is received from the Target. */
1206 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1208 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1211 /* Called by lower (CE) layer when a send to HTT Target completes. */
1212 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1214 struct ath10k *ar = ce_state->ar;
1215 struct sk_buff *skb;
1217 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1218 /* no need to call tx completion for NULL pointers */
1222 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1223 skb->len, DMA_TO_DEVICE);
1224 ath10k_htt_hif_tx_complete(ar, skb);
1228 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1230 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1231 ath10k_htt_t2h_msg_handler(ar, skb);
1234 /* Called by lower (CE) layer when HTT data is received from the Target. */
1235 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1237 /* CE4 polling needs to be done whenever CE pipe which transports
1238 * HTT Rx (target->host) is processed.
1240 ath10k_ce_per_engine_service(ce_state->ar, 4);
1242 ath10k_pci_process_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1245 static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1246 struct ath10k_hif_sg_item *items, int n_items)
1248 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1249 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1250 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1251 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1252 unsigned int nentries_mask;
1253 unsigned int sw_index;
1254 unsigned int write_index;
1257 spin_lock_bh(&ar_pci->ce_lock);
1259 nentries_mask = src_ring->nentries_mask;
1260 sw_index = src_ring->sw_index;
1261 write_index = src_ring->write_index;
1263 if (unlikely(CE_RING_DELTA(nentries_mask,
1264 write_index, sw_index - 1) < n_items)) {
1269 for (i = 0; i < n_items - 1; i++) {
1270 ath10k_dbg(ar, ATH10K_DBG_PCI,
1271 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1272 i, items[i].paddr, items[i].len, n_items);
1273 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1274 items[i].vaddr, items[i].len);
1276 err = ath10k_ce_send_nolock(ce_pipe,
1277 items[i].transfer_context,
1280 items[i].transfer_id,
1281 CE_SEND_FLAG_GATHER);
1286 /* `i` is equal to `n_items -1` after for() */
1288 ath10k_dbg(ar, ATH10K_DBG_PCI,
1289 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1290 i, items[i].paddr, items[i].len, n_items);
1291 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1292 items[i].vaddr, items[i].len);
1294 err = ath10k_ce_send_nolock(ce_pipe,
1295 items[i].transfer_context,
1298 items[i].transfer_id,
1303 spin_unlock_bh(&ar_pci->ce_lock);
1308 __ath10k_ce_send_revert(ce_pipe);
1310 spin_unlock_bh(&ar_pci->ce_lock);
1314 static int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1317 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1320 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1322 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1324 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1326 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1329 static void ath10k_pci_dump_registers(struct ath10k *ar,
1330 struct ath10k_fw_crash_data *crash_data)
1332 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1335 lockdep_assert_held(&ar->data_lock);
1337 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1339 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1341 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1345 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1347 ath10k_err(ar, "firmware register dump:\n");
1348 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1349 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1351 __le32_to_cpu(reg_dump_values[i]),
1352 __le32_to_cpu(reg_dump_values[i + 1]),
1353 __le32_to_cpu(reg_dump_values[i + 2]),
1354 __le32_to_cpu(reg_dump_values[i + 3]));
1359 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1360 crash_data->registers[i] = reg_dump_values[i];
1363 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1365 struct ath10k_fw_crash_data *crash_data;
1368 spin_lock_bh(&ar->data_lock);
1370 ar->stats.fw_crash_counter++;
1372 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1375 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
1377 scnprintf(uuid, sizeof(uuid), "n/a");
1379 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
1380 ath10k_print_driver_info(ar);
1381 ath10k_pci_dump_registers(ar, crash_data);
1383 spin_unlock_bh(&ar->data_lock);
1385 queue_work(ar->workqueue, &ar->restart_work);
1388 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1391 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1396 * Decide whether to actually poll for completions, or just
1397 * wait for a later chance.
1398 * If there seem to be plenty of resources left, then just wait
1399 * since checking involves reading a CE register, which is a
1400 * relatively expensive operation.
1402 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1405 * If at least 50% of the total resources are still available,
1406 * don't bother checking again yet.
1408 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1411 ath10k_ce_per_engine_service(ar, pipe);
1414 static void ath10k_pci_kill_tasklet(struct ath10k *ar)
1416 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1419 tasklet_kill(&ar_pci->intr_tq);
1420 tasklet_kill(&ar_pci->msi_fw_err);
1422 for (i = 0; i < CE_COUNT; i++)
1423 tasklet_kill(&ar_pci->pipe_info[i].intr);
1425 del_timer_sync(&ar_pci->rx_post_retry);
1428 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1429 u8 *ul_pipe, u8 *dl_pipe)
1431 const struct service_to_pipe *entry;
1432 bool ul_set = false, dl_set = false;
1435 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1437 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1438 entry = &target_service_to_ce_map_wlan[i];
1440 if (__le32_to_cpu(entry->service_id) != service_id)
1443 switch (__le32_to_cpu(entry->pipedir)) {
1448 *dl_pipe = __le32_to_cpu(entry->pipenum);
1453 *ul_pipe = __le32_to_cpu(entry->pipenum);
1459 *dl_pipe = __le32_to_cpu(entry->pipenum);
1460 *ul_pipe = __le32_to_cpu(entry->pipenum);
1467 if (WARN_ON(!ul_set || !dl_set))
1473 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1474 u8 *ul_pipe, u8 *dl_pipe)
1476 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1478 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1479 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1483 static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1487 switch (ar->hw_rev) {
1488 case ATH10K_HW_QCA988X:
1489 case ATH10K_HW_QCA6174:
1490 case ATH10K_HW_QCA9377:
1491 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1493 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1494 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1495 CORE_CTRL_ADDRESS, val);
1497 case ATH10K_HW_QCA99X0:
1498 /* TODO: Find appropriate register configuration for QCA99X0
1505 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1509 switch (ar->hw_rev) {
1510 case ATH10K_HW_QCA988X:
1511 case ATH10K_HW_QCA6174:
1512 case ATH10K_HW_QCA9377:
1513 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1515 val |= CORE_CTRL_PCIE_REG_31_MASK;
1516 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1517 CORE_CTRL_ADDRESS, val);
1519 case ATH10K_HW_QCA99X0:
1520 /* TODO: Find appropriate register configuration for QCA99X0
1521 * to unmask irq/MSI.
1527 static void ath10k_pci_irq_disable(struct ath10k *ar)
1529 ath10k_ce_disable_interrupts(ar);
1530 ath10k_pci_disable_and_clear_legacy_irq(ar);
1531 ath10k_pci_irq_msi_fw_mask(ar);
1534 static void ath10k_pci_irq_sync(struct ath10k *ar)
1536 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1539 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1540 synchronize_irq(ar_pci->pdev->irq + i);
1543 static void ath10k_pci_irq_enable(struct ath10k *ar)
1545 ath10k_ce_enable_interrupts(ar);
1546 ath10k_pci_enable_legacy_irq(ar);
1547 ath10k_pci_irq_msi_fw_unmask(ar);
1550 static int ath10k_pci_hif_start(struct ath10k *ar)
1552 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1554 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1556 ath10k_pci_irq_enable(ar);
1557 ath10k_pci_rx_post(ar);
1559 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1565 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1568 struct ath10k_ce_pipe *ce_pipe;
1569 struct ath10k_ce_ring *ce_ring;
1570 struct sk_buff *skb;
1573 ar = pci_pipe->hif_ce_state;
1574 ce_pipe = pci_pipe->ce_hdl;
1575 ce_ring = ce_pipe->dest_ring;
1580 if (!pci_pipe->buf_sz)
1583 for (i = 0; i < ce_ring->nentries; i++) {
1584 skb = ce_ring->per_transfer_context[i];
1588 ce_ring->per_transfer_context[i] = NULL;
1590 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1591 skb->len + skb_tailroom(skb),
1593 dev_kfree_skb_any(skb);
1597 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1600 struct ath10k_pci *ar_pci;
1601 struct ath10k_ce_pipe *ce_pipe;
1602 struct ath10k_ce_ring *ce_ring;
1603 struct sk_buff *skb;
1606 ar = pci_pipe->hif_ce_state;
1607 ar_pci = ath10k_pci_priv(ar);
1608 ce_pipe = pci_pipe->ce_hdl;
1609 ce_ring = ce_pipe->src_ring;
1614 if (!pci_pipe->buf_sz)
1617 for (i = 0; i < ce_ring->nentries; i++) {
1618 skb = ce_ring->per_transfer_context[i];
1622 ce_ring->per_transfer_context[i] = NULL;
1624 ath10k_htc_tx_completion_handler(ar, skb);
1629 * Cleanup residual buffers for device shutdown:
1630 * buffers that were enqueued for receive
1631 * buffers that were to be sent
1632 * Note: Buffers that had completed but which were
1633 * not yet processed are on a completion queue. They
1634 * are handled when the completion thread shuts down.
1636 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1638 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1641 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1642 struct ath10k_pci_pipe *pipe_info;
1644 pipe_info = &ar_pci->pipe_info[pipe_num];
1645 ath10k_pci_rx_pipe_cleanup(pipe_info);
1646 ath10k_pci_tx_pipe_cleanup(pipe_info);
1650 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1654 for (i = 0; i < CE_COUNT; i++)
1655 ath10k_ce_deinit_pipe(ar, i);
1658 static void ath10k_pci_flush(struct ath10k *ar)
1660 ath10k_pci_kill_tasklet(ar);
1661 ath10k_pci_buffer_cleanup(ar);
1664 static void ath10k_pci_hif_stop(struct ath10k *ar)
1666 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1667 unsigned long flags;
1669 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1671 /* Most likely the device has HTT Rx ring configured. The only way to
1672 * prevent the device from accessing (and possible corrupting) host
1673 * memory is to reset the chip now.
1675 * There's also no known way of masking MSI interrupts on the device.
1676 * For ranged MSI the CE-related interrupts can be masked. However
1677 * regardless how many MSI interrupts are assigned the first one
1678 * is always used for firmware indications (crashes) and cannot be
1679 * masked. To prevent the device from asserting the interrupt reset it
1680 * before proceeding with cleanup.
1682 ath10k_pci_safe_chip_reset(ar);
1684 ath10k_pci_irq_disable(ar);
1685 ath10k_pci_irq_sync(ar);
1686 ath10k_pci_flush(ar);
1688 spin_lock_irqsave(&ar_pci->ps_lock, flags);
1689 WARN_ON(ar_pci->ps_wake_refcount > 0);
1690 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
1693 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1694 void *req, u32 req_len,
1695 void *resp, u32 *resp_len)
1697 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1698 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1699 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1700 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1701 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1702 dma_addr_t req_paddr = 0;
1703 dma_addr_t resp_paddr = 0;
1704 struct bmi_xfer xfer = {};
1705 void *treq, *tresp = NULL;
1710 if (resp && !resp_len)
1713 if (resp && resp_len && *resp_len == 0)
1716 treq = kmemdup(req, req_len, GFP_KERNEL);
1720 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1721 ret = dma_mapping_error(ar->dev, req_paddr);
1727 if (resp && resp_len) {
1728 tresp = kzalloc(*resp_len, GFP_KERNEL);
1734 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1736 ret = dma_mapping_error(ar->dev, resp_paddr);
1742 xfer.wait_for_resp = true;
1745 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1748 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1752 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1755 unsigned int unused_nbytes;
1756 unsigned int unused_id;
1758 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1759 &unused_nbytes, &unused_id);
1761 /* non-zero means we did not time out */
1769 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1770 dma_unmap_single(ar->dev, resp_paddr,
1771 *resp_len, DMA_FROM_DEVICE);
1774 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1776 if (ret == 0 && resp_len) {
1777 *resp_len = min(*resp_len, xfer.resp_len);
1778 memcpy(resp, tresp, xfer.resp_len);
1787 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1789 struct bmi_xfer *xfer;
1791 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
1794 xfer->tx_done = true;
1797 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1799 struct ath10k *ar = ce_state->ar;
1800 struct bmi_xfer *xfer;
1802 unsigned int nbytes;
1803 unsigned int transfer_id;
1806 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1807 &nbytes, &transfer_id, &flags))
1810 if (WARN_ON_ONCE(!xfer))
1813 if (!xfer->wait_for_resp) {
1814 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1818 xfer->resp_len = nbytes;
1819 xfer->rx_done = true;
1822 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1823 struct ath10k_ce_pipe *rx_pipe,
1824 struct bmi_xfer *xfer)
1826 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1828 while (time_before_eq(jiffies, timeout)) {
1829 ath10k_pci_bmi_send_done(tx_pipe);
1830 ath10k_pci_bmi_recv_data(rx_pipe);
1832 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
1842 * Send an interrupt to the device to wake up the Target CPU
1843 * so it has an opportunity to notice any changed state.
1845 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1849 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
1850 val = ath10k_pci_read32(ar, addr);
1851 val |= CORE_CTRL_CPU_INTR_MASK;
1852 ath10k_pci_write32(ar, addr, val);
1857 static int ath10k_pci_get_num_banks(struct ath10k *ar)
1859 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1861 switch (ar_pci->pdev->device) {
1862 case QCA988X_2_0_DEVICE_ID:
1863 case QCA99X0_2_0_DEVICE_ID:
1865 case QCA6164_2_1_DEVICE_ID:
1866 case QCA6174_2_1_DEVICE_ID:
1867 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
1868 case QCA6174_HW_1_0_CHIP_ID_REV:
1869 case QCA6174_HW_1_1_CHIP_ID_REV:
1870 case QCA6174_HW_2_1_CHIP_ID_REV:
1871 case QCA6174_HW_2_2_CHIP_ID_REV:
1873 case QCA6174_HW_1_3_CHIP_ID_REV:
1875 case QCA6174_HW_3_0_CHIP_ID_REV:
1876 case QCA6174_HW_3_1_CHIP_ID_REV:
1877 case QCA6174_HW_3_2_CHIP_ID_REV:
1881 case QCA9377_1_0_DEVICE_ID:
1885 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
1889 static int ath10k_pci_init_config(struct ath10k *ar)
1891 u32 interconnect_targ_addr;
1892 u32 pcie_state_targ_addr = 0;
1893 u32 pipe_cfg_targ_addr = 0;
1894 u32 svc_to_pipe_map = 0;
1895 u32 pcie_config_flags = 0;
1897 u32 ealloc_targ_addr;
1899 u32 flag2_targ_addr;
1902 /* Download to Target the CE Config and the service-to-CE map */
1903 interconnect_targ_addr =
1904 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1906 /* Supply Target-side CE configuration */
1907 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
1908 &pcie_state_targ_addr);
1910 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
1914 if (pcie_state_targ_addr == 0) {
1916 ath10k_err(ar, "Invalid pcie state addr\n");
1920 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1921 offsetof(struct pcie_state,
1923 &pipe_cfg_targ_addr);
1925 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
1929 if (pipe_cfg_targ_addr == 0) {
1931 ath10k_err(ar, "Invalid pipe cfg addr\n");
1935 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1936 target_ce_config_wlan,
1937 sizeof(struct ce_pipe_config) *
1938 NUM_TARGET_CE_CONFIG_WLAN);
1941 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
1945 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1946 offsetof(struct pcie_state,
1950 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
1954 if (svc_to_pipe_map == 0) {
1956 ath10k_err(ar, "Invalid svc_to_pipe map\n");
1960 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1961 target_service_to_ce_map_wlan,
1962 sizeof(target_service_to_ce_map_wlan));
1964 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
1968 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1969 offsetof(struct pcie_state,
1971 &pcie_config_flags);
1973 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
1977 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1979 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
1980 offsetof(struct pcie_state,
1984 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
1988 /* configure early allocation */
1989 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1991 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
1993 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
1997 /* first bank is switched to IRAM */
1998 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1999 HI_EARLY_ALLOC_MAGIC_MASK);
2000 ealloc_value |= ((ath10k_pci_get_num_banks(ar) <<
2001 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2002 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2004 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2006 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2010 /* Tell Target to proceed with initialization */
2011 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2013 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2015 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2019 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2021 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2023 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2030 static int ath10k_pci_alloc_pipes(struct ath10k *ar)
2032 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2033 struct ath10k_pci_pipe *pipe;
2036 for (i = 0; i < CE_COUNT; i++) {
2037 pipe = &ar_pci->pipe_info[i];
2038 pipe->ce_hdl = &ar_pci->ce_states[i];
2040 pipe->hif_ce_state = ar;
2042 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2044 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2049 /* Last CE is Diagnostic Window */
2050 if (i == CE_DIAG_PIPE) {
2051 ar_pci->ce_diag = pipe->ce_hdl;
2055 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2061 static void ath10k_pci_free_pipes(struct ath10k *ar)
2065 for (i = 0; i < CE_COUNT; i++)
2066 ath10k_ce_free_pipe(ar, i);
2069 static int ath10k_pci_init_pipes(struct ath10k *ar)
2073 for (i = 0; i < CE_COUNT; i++) {
2074 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2076 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2085 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2087 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2088 FW_IND_EVENT_PENDING;
2091 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2095 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2096 val &= ~FW_IND_EVENT_PENDING;
2097 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2100 /* this function effectively clears target memory controller assert line */
2101 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2105 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2106 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2107 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2108 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2112 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2113 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2114 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2115 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2120 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2124 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2126 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2127 SOC_RESET_CONTROL_ADDRESS);
2128 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2129 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2132 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2136 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2137 SOC_RESET_CONTROL_ADDRESS);
2139 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2140 val | SOC_RESET_CONTROL_CE_RST_MASK);
2142 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2143 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2146 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2150 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2151 SOC_LF_TIMER_CONTROL0_ADDRESS);
2152 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2153 SOC_LF_TIMER_CONTROL0_ADDRESS,
2154 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2157 static int ath10k_pci_warm_reset(struct ath10k *ar)
2161 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2163 spin_lock_bh(&ar->data_lock);
2164 ar->stats.fw_warm_reset_counter++;
2165 spin_unlock_bh(&ar->data_lock);
2167 ath10k_pci_irq_disable(ar);
2169 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2170 * were to access copy engine while host performs copy engine reset
2171 * then it is possible for the device to confuse pci-e controller to
2172 * the point of bringing host system to a complete stop (i.e. hang).
2174 ath10k_pci_warm_reset_si0(ar);
2175 ath10k_pci_warm_reset_cpu(ar);
2176 ath10k_pci_init_pipes(ar);
2177 ath10k_pci_wait_for_target_init(ar);
2179 ath10k_pci_warm_reset_clear_lf(ar);
2180 ath10k_pci_warm_reset_ce(ar);
2181 ath10k_pci_warm_reset_cpu(ar);
2182 ath10k_pci_init_pipes(ar);
2184 ret = ath10k_pci_wait_for_target_init(ar);
2186 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2190 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2195 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2197 if (QCA_REV_988X(ar) || QCA_REV_6174(ar)) {
2198 return ath10k_pci_warm_reset(ar);
2199 } else if (QCA_REV_99X0(ar)) {
2200 ath10k_pci_irq_disable(ar);
2201 return ath10k_pci_qca99x0_chip_reset(ar);
2207 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2212 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2214 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2215 * It is thus preferred to use warm reset which is safer but may not be
2216 * able to recover the device from all possible fail scenarios.
2218 * Warm reset doesn't always work on first try so attempt it a few
2219 * times before giving up.
2221 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2222 ret = ath10k_pci_warm_reset(ar);
2224 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2225 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2230 /* FIXME: Sometimes copy engine doesn't recover after warm
2231 * reset. In most cases this needs cold reset. In some of these
2232 * cases the device is in such a state that a cold reset may
2235 * Reading any host interest register via copy engine is
2236 * sufficient to verify if device is capable of booting
2239 ret = ath10k_pci_init_pipes(ar);
2241 ath10k_warn(ar, "failed to init copy engine: %d\n",
2246 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2249 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2254 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2258 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2259 ath10k_warn(ar, "refusing cold reset as requested\n");
2263 ret = ath10k_pci_cold_reset(ar);
2265 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2269 ret = ath10k_pci_wait_for_target_init(ar);
2271 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2276 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2281 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2285 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2287 /* FIXME: QCA6174 requires cold + warm reset to work. */
2289 ret = ath10k_pci_cold_reset(ar);
2291 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2295 ret = ath10k_pci_wait_for_target_init(ar);
2297 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2302 ret = ath10k_pci_warm_reset(ar);
2304 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2308 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2313 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2317 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2319 ret = ath10k_pci_cold_reset(ar);
2321 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2325 ret = ath10k_pci_wait_for_target_init(ar);
2327 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2332 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2337 static int ath10k_pci_chip_reset(struct ath10k *ar)
2339 if (QCA_REV_988X(ar))
2340 return ath10k_pci_qca988x_chip_reset(ar);
2341 else if (QCA_REV_6174(ar))
2342 return ath10k_pci_qca6174_chip_reset(ar);
2343 else if (QCA_REV_9377(ar))
2344 return ath10k_pci_qca6174_chip_reset(ar);
2345 else if (QCA_REV_99X0(ar))
2346 return ath10k_pci_qca99x0_chip_reset(ar);
2351 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2353 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2356 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2358 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2360 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2361 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2364 * Bring the target up cleanly.
2366 * The target may be in an undefined state with an AUX-powered Target
2367 * and a Host in WoW mode. If the Host crashes, loses power, or is
2368 * restarted (without unloading the driver) then the Target is left
2369 * (aux) powered and running. On a subsequent driver load, the Target
2370 * is in an unexpected state. We try to catch that here in order to
2371 * reset the Target and retry the probe.
2373 ret = ath10k_pci_chip_reset(ar);
2375 if (ath10k_pci_has_fw_crashed(ar)) {
2376 ath10k_warn(ar, "firmware crashed during chip reset\n");
2377 ath10k_pci_fw_crashed_clear(ar);
2378 ath10k_pci_fw_crashed_dump(ar);
2381 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2385 ret = ath10k_pci_init_pipes(ar);
2387 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2391 ret = ath10k_pci_init_config(ar);
2393 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2397 ret = ath10k_pci_wake_target_cpu(ar);
2399 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2406 ath10k_pci_ce_deinit(ar);
2412 static void ath10k_pci_hif_power_down(struct ath10k *ar)
2414 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2416 /* Currently hif_power_up performs effectively a reset and hif_stop
2417 * resets the chip as well so there's no point in resetting here.
2423 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2425 /* The grace timer can still be counting down and ar->ps_awake be true.
2426 * It is known that the device may be asleep after resuming regardless
2427 * of the SoC powersave state before suspending. Hence make sure the
2428 * device is asleep before proceeding.
2430 ath10k_pci_sleep_sync(ar);
2435 static int ath10k_pci_hif_resume(struct ath10k *ar)
2437 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2438 struct pci_dev *pdev = ar_pci->pdev;
2442 if (ar_pci->pci_ps == 0) {
2443 ret = ath10k_pci_force_wake(ar);
2445 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2450 /* Suspend/Resume resets the PCI configuration space, so we have to
2451 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2452 * from interfering with C3 CPU state. pci_restore_state won't help
2453 * here since it only restores the first 64 bytes pci config header.
2455 pci_read_config_dword(pdev, 0x40, &val);
2456 if ((val & 0x0000ff00) != 0)
2457 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2463 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2464 .tx_sg = ath10k_pci_hif_tx_sg,
2465 .diag_read = ath10k_pci_hif_diag_read,
2466 .diag_write = ath10k_pci_diag_write_mem,
2467 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2468 .start = ath10k_pci_hif_start,
2469 .stop = ath10k_pci_hif_stop,
2470 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2471 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2472 .send_complete_check = ath10k_pci_hif_send_complete_check,
2473 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2474 .power_up = ath10k_pci_hif_power_up,
2475 .power_down = ath10k_pci_hif_power_down,
2476 .read32 = ath10k_pci_read32,
2477 .write32 = ath10k_pci_write32,
2479 .suspend = ath10k_pci_hif_suspend,
2480 .resume = ath10k_pci_hif_resume,
2484 static void ath10k_pci_ce_tasklet(unsigned long ptr)
2486 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2487 struct ath10k_pci *ar_pci = pipe->ar_pci;
2489 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2492 static void ath10k_msi_err_tasklet(unsigned long data)
2494 struct ath10k *ar = (struct ath10k *)data;
2496 if (!ath10k_pci_has_fw_crashed(ar)) {
2497 ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
2501 ath10k_pci_irq_disable(ar);
2502 ath10k_pci_fw_crashed_clear(ar);
2503 ath10k_pci_fw_crashed_dump(ar);
2507 * Handler for a per-engine interrupt on a PARTICULAR CE.
2508 * This is used in cases where each CE has a private MSI interrupt.
2510 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2512 struct ath10k *ar = arg;
2513 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2514 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2516 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2517 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
2523 * NOTE: We are able to derive ce_id from irq because we
2524 * use a one-to-one mapping for CE's 0..5.
2525 * CE's 6 & 7 do not use interrupts at all.
2527 * This mapping must be kept in sync with the mapping
2530 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2534 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2536 struct ath10k *ar = arg;
2537 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2539 tasklet_schedule(&ar_pci->msi_fw_err);
2544 * Top-level interrupt handler for all PCI interrupts from a Target.
2545 * When a block of MSI interrupts is allocated, this top-level handler
2546 * is not used; instead, we directly call the correct sub-handler.
2548 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2550 struct ath10k *ar = arg;
2551 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2554 if (ar_pci->pci_ps == 0) {
2555 ret = ath10k_pci_force_wake(ar);
2557 ath10k_warn(ar, "failed to wake device up on irq: %d\n",
2563 if (ar_pci->num_msi_intrs == 0) {
2564 if (!ath10k_pci_irq_pending(ar))
2567 ath10k_pci_disable_and_clear_legacy_irq(ar);
2570 tasklet_schedule(&ar_pci->intr_tq);
2575 static void ath10k_pci_tasklet(unsigned long data)
2577 struct ath10k *ar = (struct ath10k *)data;
2578 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2580 if (ath10k_pci_has_fw_crashed(ar)) {
2581 ath10k_pci_irq_disable(ar);
2582 ath10k_pci_fw_crashed_clear(ar);
2583 ath10k_pci_fw_crashed_dump(ar);
2587 ath10k_ce_per_engine_service_any(ar);
2589 /* Re-enable legacy irq that was disabled in the irq handler */
2590 if (ar_pci->num_msi_intrs == 0)
2591 ath10k_pci_enable_legacy_irq(ar);
2594 static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2596 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2599 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2600 ath10k_pci_msi_fw_handler,
2601 IRQF_SHARED, "ath10k_pci", ar);
2603 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
2604 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2608 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2609 ret = request_irq(ar_pci->pdev->irq + i,
2610 ath10k_pci_per_engine_handler,
2611 IRQF_SHARED, "ath10k_pci", ar);
2613 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
2614 ar_pci->pdev->irq + i, ret);
2616 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2617 free_irq(ar_pci->pdev->irq + i, ar);
2619 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2627 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2629 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2632 ret = request_irq(ar_pci->pdev->irq,
2633 ath10k_pci_interrupt_handler,
2634 IRQF_SHARED, "ath10k_pci", ar);
2636 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2637 ar_pci->pdev->irq, ret);
2644 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2646 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2649 ret = request_irq(ar_pci->pdev->irq,
2650 ath10k_pci_interrupt_handler,
2651 IRQF_SHARED, "ath10k_pci", ar);
2653 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2654 ar_pci->pdev->irq, ret);
2661 static int ath10k_pci_request_irq(struct ath10k *ar)
2663 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2665 switch (ar_pci->num_msi_intrs) {
2667 return ath10k_pci_request_irq_legacy(ar);
2669 return ath10k_pci_request_irq_msi(ar);
2671 return ath10k_pci_request_irq_msix(ar);
2675 static void ath10k_pci_free_irq(struct ath10k *ar)
2677 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2680 /* There's at least one interrupt irregardless whether its legacy INTR
2681 * or MSI or MSI-X */
2682 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2683 free_irq(ar_pci->pdev->irq + i, ar);
2686 static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2688 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2691 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2692 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2695 for (i = 0; i < CE_COUNT; i++) {
2696 ar_pci->pipe_info[i].ar_pci = ar_pci;
2697 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2698 (unsigned long)&ar_pci->pipe_info[i]);
2702 static int ath10k_pci_init_irq(struct ath10k *ar)
2704 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2707 ath10k_pci_init_irq_tasklets(ar);
2709 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2710 ath10k_info(ar, "limiting irq mode to: %d\n",
2711 ath10k_pci_irq_mode);
2714 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
2715 ar_pci->num_msi_intrs = MSI_ASSIGN_CE_MAX + 1;
2716 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2717 ar_pci->num_msi_intrs);
2725 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2726 ar_pci->num_msi_intrs = 1;
2727 ret = pci_enable_msi(ar_pci->pdev);
2736 * A potential race occurs here: The CORE_BASE write
2737 * depends on target correctly decoding AXI address but
2738 * host won't know when target writes BAR to CORE_CTRL.
2739 * This write might get lost if target has NOT written BAR.
2740 * For now, fix the race by repeating the write in below
2741 * synchronization checking. */
2742 ar_pci->num_msi_intrs = 0;
2744 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2745 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2750 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2752 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2756 static int ath10k_pci_deinit_irq(struct ath10k *ar)
2758 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2760 switch (ar_pci->num_msi_intrs) {
2762 ath10k_pci_deinit_irq_legacy(ar);
2765 pci_disable_msi(ar_pci->pdev);
2772 static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2774 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2775 unsigned long timeout;
2778 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2780 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2783 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2785 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2788 /* target should never return this */
2789 if (val == 0xffffffff)
2792 /* the device has crashed so don't bother trying anymore */
2793 if (val & FW_IND_EVENT_PENDING)
2796 if (val & FW_IND_INITIALIZED)
2799 if (ar_pci->num_msi_intrs == 0)
2800 /* Fix potential race by repeating CORE_BASE writes */
2801 ath10k_pci_enable_legacy_irq(ar);
2804 } while (time_before(jiffies, timeout));
2806 ath10k_pci_disable_and_clear_legacy_irq(ar);
2807 ath10k_pci_irq_msi_fw_mask(ar);
2809 if (val == 0xffffffff) {
2810 ath10k_err(ar, "failed to read device register, device is gone\n");
2814 if (val & FW_IND_EVENT_PENDING) {
2815 ath10k_warn(ar, "device has crashed during init\n");
2819 if (!(val & FW_IND_INITIALIZED)) {
2820 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2825 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2829 static int ath10k_pci_cold_reset(struct ath10k *ar)
2833 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2835 spin_lock_bh(&ar->data_lock);
2837 ar->stats.fw_cold_reset_counter++;
2839 spin_unlock_bh(&ar->data_lock);
2841 /* Put Target, including PCIe, into RESET. */
2842 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2844 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2846 /* After writing into SOC_GLOBAL_RESET to put device into
2847 * reset and pulling out of reset pcie may not be stable
2848 * for any immediate pcie register access and cause bus error,
2849 * add delay before any pcie access request to fix this issue.
2853 /* Pull Target, including PCIe, out of RESET. */
2855 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2859 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
2864 static int ath10k_pci_claim(struct ath10k *ar)
2866 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2867 struct pci_dev *pdev = ar_pci->pdev;
2870 pci_set_drvdata(pdev, ar);
2872 ret = pci_enable_device(pdev);
2874 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
2878 ret = pci_request_region(pdev, BAR_NUM, "ath");
2880 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
2885 /* Target expects 32 bit DMA. Enforce it. */
2886 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2888 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
2892 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2894 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
2899 pci_set_master(pdev);
2901 /* Arrange for access to Target SoC registers. */
2902 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
2903 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
2905 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
2910 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2914 pci_clear_master(pdev);
2917 pci_release_region(pdev, BAR_NUM);
2920 pci_disable_device(pdev);
2925 static void ath10k_pci_release(struct ath10k *ar)
2927 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2928 struct pci_dev *pdev = ar_pci->pdev;
2930 pci_iounmap(pdev, ar_pci->mem);
2931 pci_release_region(pdev, BAR_NUM);
2932 pci_clear_master(pdev);
2933 pci_disable_device(pdev);
2936 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
2938 const struct ath10k_pci_supp_chip *supp_chip;
2940 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
2942 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
2943 supp_chip = &ath10k_pci_supp_chips[i];
2945 if (supp_chip->dev_id == dev_id &&
2946 supp_chip->rev_id == rev_id)
2953 static int ath10k_pci_probe(struct pci_dev *pdev,
2954 const struct pci_device_id *pci_dev)
2958 struct ath10k_pci *ar_pci;
2959 enum ath10k_hw_rev hw_rev;
2963 switch (pci_dev->device) {
2964 case QCA988X_2_0_DEVICE_ID:
2965 hw_rev = ATH10K_HW_QCA988X;
2968 case QCA6164_2_1_DEVICE_ID:
2969 case QCA6174_2_1_DEVICE_ID:
2970 hw_rev = ATH10K_HW_QCA6174;
2973 case QCA99X0_2_0_DEVICE_ID:
2974 hw_rev = ATH10K_HW_QCA99X0;
2977 case QCA9377_1_0_DEVICE_ID:
2978 hw_rev = ATH10K_HW_QCA9377;
2986 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
2987 hw_rev, &ath10k_pci_hif_ops);
2989 dev_err(&pdev->dev, "failed to allocate core\n");
2993 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
2994 pdev->vendor, pdev->device,
2995 pdev->subsystem_vendor, pdev->subsystem_device);
2997 ar_pci = ath10k_pci_priv(ar);
2998 ar_pci->pdev = pdev;
2999 ar_pci->dev = &pdev->dev;
3001 ar->dev_id = pci_dev->device;
3002 ar_pci->pci_ps = pci_ps;
3004 ar->id.vendor = pdev->vendor;
3005 ar->id.device = pdev->device;
3006 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3007 ar->id.subsystem_device = pdev->subsystem_device;
3009 spin_lock_init(&ar_pci->ce_lock);
3010 spin_lock_init(&ar_pci->ps_lock);
3012 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
3014 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
3017 ret = ath10k_pci_claim(ar);
3019 ath10k_err(ar, "failed to claim device: %d\n", ret);
3020 goto err_core_destroy;
3023 ret = ath10k_pci_alloc_pipes(ar);
3025 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3030 ath10k_pci_ce_deinit(ar);
3031 ath10k_pci_irq_disable(ar);
3033 if (ar_pci->pci_ps == 0) {
3034 ret = ath10k_pci_force_wake(ar);
3036 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3037 goto err_free_pipes;
3041 ret = ath10k_pci_init_irq(ar);
3043 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3044 goto err_free_pipes;
3047 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
3048 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
3049 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3051 ret = ath10k_pci_request_irq(ar);
3053 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3054 goto err_deinit_irq;
3057 ret = ath10k_pci_chip_reset(ar);
3059 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3063 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3064 if (chip_id == 0xffffffff) {
3065 ath10k_err(ar, "failed to get chip id\n");
3069 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3070 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3071 pdev->device, chip_id);
3075 ret = ath10k_core_register(ar, chip_id);
3077 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3084 ath10k_pci_free_irq(ar);
3085 ath10k_pci_kill_tasklet(ar);
3088 ath10k_pci_deinit_irq(ar);
3091 ath10k_pci_free_pipes(ar);
3094 ath10k_pci_sleep_sync(ar);
3095 ath10k_pci_release(ar);
3098 ath10k_core_destroy(ar);
3103 static void ath10k_pci_remove(struct pci_dev *pdev)
3105 struct ath10k *ar = pci_get_drvdata(pdev);
3106 struct ath10k_pci *ar_pci;
3108 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3113 ar_pci = ath10k_pci_priv(ar);
3118 ath10k_core_unregister(ar);
3119 ath10k_pci_free_irq(ar);
3120 ath10k_pci_kill_tasklet(ar);
3121 ath10k_pci_deinit_irq(ar);
3122 ath10k_pci_ce_deinit(ar);
3123 ath10k_pci_free_pipes(ar);
3124 ath10k_pci_sleep_sync(ar);
3125 ath10k_pci_release(ar);
3126 ath10k_core_destroy(ar);
3129 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3131 static struct pci_driver ath10k_pci_driver = {
3132 .name = "ath10k_pci",
3133 .id_table = ath10k_pci_id_table,
3134 .probe = ath10k_pci_probe,
3135 .remove = ath10k_pci_remove,
3138 static int __init ath10k_pci_init(void)
3142 ret = pci_register_driver(&ath10k_pci_driver);
3144 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3149 module_init(ath10k_pci_init);
3151 static void __exit ath10k_pci_exit(void)
3153 pci_unregister_driver(&ath10k_pci_driver);
3156 module_exit(ath10k_pci_exit);
3158 MODULE_AUTHOR("Qualcomm Atheros");
3159 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
3160 MODULE_LICENSE("Dual BSD/GPL");
3162 /* QCA988x 2.0 firmware files */
3163 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
3164 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3165 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3166 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3167 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3168 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3169 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3171 /* QCA6174 2.1 firmware files */
3172 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3173 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3174 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3175 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3177 /* QCA6174 3.1 firmware files */
3178 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3179 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3180 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3181 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3183 /* QCA9377 1.0 firmware files */
3184 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3185 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);