drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9003_buffalo_initvals.h"
  21 #include "ar9485_initvals.h"
  22 #include "ar9340_initvals.h"
  23 #include "ar9330_1p1_initvals.h"
  24 #include "ar9330_1p2_initvals.h"
  25 #include "ar955x_1p0_initvals.h"
  26 #include "ar9580_1p0_initvals.h"
  27 #include "ar9462_2p0_initvals.h"
  28 #include "ar9462_2p1_initvals.h"
  29 #include "ar9565_1p0_initvals.h"
  30 #include "ar9565_1p1_initvals.h"
  31 #include "ar953x_initvals.h"
  32 #include "ar956x_initvals.h"
  33
  34 /* General hardware code for the AR9003 hadware family */
  35
  36 /*
  37  * The AR9003 family uses a new INI format (pre, core, post
  38  * arrays per subsystem). This provides support for the
  39  * AR9003 2.2 chipsets.
  40  */
  41 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  42 {
  43         if (AR_SREV_9330_11(ah)) {
  44                 /* mac */
  45                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  46                                 ar9331_1p1_mac_core);
  47                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  48                                 ar9331_1p1_mac_postamble);
  49
  50                 /* bb */
  51                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  52                                 ar9331_1p1_baseband_core);
  53                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  54                                 ar9331_1p1_baseband_postamble);
  55
  56                 /* radio */
  57                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  58                                 ar9331_1p1_radio_core);
  59
  60                 /* soc */
  61                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  62                                 ar9331_1p1_soc_preamble);
  63                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  64                                 ar9331_1p1_soc_postamble);
  65
  66                 /* rx/tx gain */
  67                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  68                                 ar9331_common_rx_gain_1p1);
  69                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  70                                 ar9331_modes_lowest_ob_db_tx_gain_1p1);
  71
  72                 /* Japan 2484 Mhz CCK */
  73                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  74                                ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
  75
  76                 /* additional clock settings */
  77                 if (ah->is_clk_25mhz)
  78                         INIT_INI_ARRAY(&ah->iniAdditional,
  79                                         ar9331_1p1_xtal_25M);
  80                 else
  81                         INIT_INI_ARRAY(&ah->iniAdditional,
  82                                         ar9331_1p1_xtal_40M);
  83         } else if (AR_SREV_9330_12(ah)) {
  84                 /* mac */
  85                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  86                                 ar9331_1p2_mac_core);
  87                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  88                                 ar9331_1p2_mac_postamble);
  89
  90                 /* bb */
  91                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  92                                 ar9331_1p2_baseband_core);
  93                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  94                                 ar9331_1p2_baseband_postamble);
  95
  96                 /* radio */
  97                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  98                                 ar9331_1p2_radio_core);
  99
 100                 /* soc */
 101                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 102                                 ar9331_1p2_soc_preamble);
 103                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 104                                 ar9331_1p2_soc_postamble);
 105
 106                 /* rx/tx gain */
 107                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 108                                 ar9331_common_rx_gain_1p2);
 109                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 110                                 ar9331_modes_lowest_ob_db_tx_gain_1p2);
 111
 112                 /* Japan 2484 Mhz CCK */
 113                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 114                                ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
 115
 116                 /* additional clock settings */
 117                 if (ah->is_clk_25mhz)
 118                         INIT_INI_ARRAY(&ah->iniAdditional,
 119                                         ar9331_1p2_xtal_25M);
 120                 else
 121                         INIT_INI_ARRAY(&ah->iniAdditional,
 122                                         ar9331_1p2_xtal_40M);
 123         } else if (AR_SREV_9340(ah)) {
 124                 /* mac */
 125                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 126                                 ar9340_1p0_mac_core);
 127                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 128                                 ar9340_1p0_mac_postamble);
 129
 130                 /* bb */
 131                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 132                                 ar9340_1p0_baseband_core);
 133                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 134                                 ar9340_1p0_baseband_postamble);
 135
 136                 /* radio */
 137                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 138                                 ar9340_1p0_radio_core);
 139                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 140                                 ar9340_1p0_radio_postamble);
 141
 142                 /* soc */
 143                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 144                                 ar9340_1p0_soc_preamble);
 145                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 146                                 ar9340_1p0_soc_postamble);
 147
 148                 /* rx/tx gain */
 149                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 150                                 ar9340Common_wo_xlna_rx_gain_table_1p0);
 151                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 152                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
 153
 154                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 155                                ar9340Modes_fast_clock_1p0);
 156                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 157                                ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
 158                 INIT_INI_ARRAY(&ah->ini_dfs,
 159                                ar9340_1p0_baseband_postamble_dfs_channel);
 160
 161                 if (!ah->is_clk_25mhz)
 162                         INIT_INI_ARRAY(&ah->iniAdditional,
 163                                        ar9340_1p0_radio_core_40M);
 164         } else if (AR_SREV_9485_11_OR_LATER(ah)) {
 165                 /* mac */
 166                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 167                                 ar9485_1_1_mac_core);
 168                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 169                                 ar9485_1_1_mac_postamble);
 170
 171                 /* bb */
 172                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
 173                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 174                                 ar9485_1_1_baseband_core);
 175                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 176                                 ar9485_1_1_baseband_postamble);
 177
 178                 /* radio */
 179                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 180                                 ar9485_1_1_radio_core);
 181                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 182                                 ar9485_1_1_radio_postamble);
 183
 184                 /* soc */
 185                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 186                                 ar9485_1_1_soc_preamble);
 187
 188                 /* rx/tx gain */
 189                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 190                                 ar9485Common_wo_xlna_rx_gain_1_1);
 191                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 192                                 ar9485_modes_lowest_ob_db_tx_gain_1_1);
 193
 194                 /* Japan 2484 Mhz CCK */
 195                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 196                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 197
 198                 if (ah->config.no_pll_pwrsave) {
 199                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 200                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 201                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 202                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 203                 } else {
 204                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 205                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 206                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 207                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 208                 }
 209         } else if (AR_SREV_9462_21(ah)) {
 210                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 211                                ar9462_2p1_mac_core);
 212                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 213                                ar9462_2p1_mac_postamble);
 214                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 215                                ar9462_2p1_baseband_core);
 216                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 217                                ar9462_2p1_baseband_postamble);
 218                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 219                                ar9462_2p1_radio_core);
 220                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 221                                ar9462_2p1_radio_postamble);
 222                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 223                                ar9462_2p1_radio_postamble_sys2ant);
 224                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 225                                ar9462_2p1_soc_preamble);
 226                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 227                                ar9462_2p1_soc_postamble);
 228                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 229                                ar9462_2p1_common_rx_gain);
 230                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 231                                ar9462_2p1_modes_fast_clock);
 232                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 233                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 234                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 235                                ar9462_2p1_pciephy_clkreq_disable_L1);
 236                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 237                                ar9462_2p1_pciephy_clkreq_disable_L1);
 238         } else if (AR_SREV_9462_20(ah)) {
 239
 240                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 241                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 242                                 ar9462_2p0_mac_postamble);
 243
 244                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 245                                 ar9462_2p0_baseband_core);
 246                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 247                                 ar9462_2p0_baseband_postamble);
 248
 249                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 250                                 ar9462_2p0_radio_core);
 251                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 252                                 ar9462_2p0_radio_postamble);
 253                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 254                                 ar9462_2p0_radio_postamble_sys2ant);
 255
 256                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 257                                 ar9462_2p0_soc_preamble);
 258                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 259                                 ar9462_2p0_soc_postamble);
 260
 261                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 262                                 ar9462_2p0_common_rx_gain);
 263
 264                 /* Awake -> Sleep Setting */
 265                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 266                                ar9462_2p0_pciephy_clkreq_disable_L1);
 267                 /* Sleep -> Awake Setting */
 268                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 269                                ar9462_2p0_pciephy_clkreq_disable_L1);
 270
 271                 /* Fast clock modal settings */
 272                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 273                                 ar9462_2p0_modes_fast_clock);
 274
 275                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 276                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 277         } else if (AR_SREV_9550(ah)) {
 278                 /* mac */
 279                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 280                                 ar955x_1p0_mac_core);
 281                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 282                                 ar955x_1p0_mac_postamble);
 283
 284                 /* bb */
 285                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 286                                 ar955x_1p0_baseband_core);
 287                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 288                                 ar955x_1p0_baseband_postamble);
 289
 290                 /* radio */
 291                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 292                                 ar955x_1p0_radio_core);
 293                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 294                                 ar955x_1p0_radio_postamble);
 295
 296                 /* soc */
 297                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 298                                 ar955x_1p0_soc_preamble);
 299                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 300                                 ar955x_1p0_soc_postamble);
 301
 302                 /* rx/tx gain */
 303                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 304                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 305                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 306                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 307                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 308                                 ar955x_1p0_modes_xpa_tx_gain_table);
 309
 310                 /* Fast clock modal settings */
 311                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 312                                 ar955x_1p0_modes_fast_clock);
 313         } else if (AR_SREV_9531(ah)) {
 314                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 315                                qca953x_1p0_mac_core);
 316                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 317                                qca953x_1p0_mac_postamble);
 318                 if (AR_SREV_9531_20(ah)) {
 319                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 320                                        qca953x_2p0_baseband_core);
 321                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 322                                        qca953x_2p0_baseband_postamble);
 323                 } else {
 324                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 325                                        qca953x_1p0_baseband_core);
 326                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 327                                        qca953x_1p0_baseband_postamble);
 328                 }
 329                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 330                                qca953x_1p0_radio_core);
 331                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 332                                qca953x_1p0_radio_postamble);
 333                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 334                                qca953x_1p0_soc_preamble);
 335                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 336                                qca953x_1p0_soc_postamble);
 337
 338                 if (AR_SREV_9531_20(ah)) {
 339                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 340                                        qca953x_2p0_common_wo_xlna_rx_gain_table);
 341                         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 342                                        qca953x_2p0_common_wo_xlna_rx_gain_bounds);
 343                 } else {
 344                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 345                                        qca953x_1p0_common_wo_xlna_rx_gain_table);
 346                         INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 347                                        qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 348                 }
 349
 350                 if (AR_SREV_9531_20(ah))
 351                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 352                                        qca953x_2p0_modes_no_xpa_tx_gain_table);
 353                 else if (AR_SREV_9531_11(ah))
 354                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 355                                        qca953x_1p1_modes_no_xpa_tx_gain_table);
 356                 else
 357                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 358                                        qca953x_1p0_modes_no_xpa_tx_gain_table);
 359
 360                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 361                                qca953x_1p0_modes_fast_clock);
 362         } else if (AR_SREV_9561(ah)) {
 363                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 364                                qca956x_1p0_mac_core);
 365                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 366                                qca956x_1p0_mac_postamble);
 367
 368                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 369                                qca956x_1p0_baseband_core);
 370                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 371                                qca956x_1p0_baseband_postamble);
 372
 373                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 374                                qca956x_1p0_radio_core);
 375                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 376                                qca956x_1p0_radio_postamble);
 377
 378                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 379                                qca956x_1p0_soc_preamble);
 380                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 381                                qca956x_1p0_soc_postamble);
 382
 383                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 384                                qca956x_1p0_common_wo_xlna_rx_gain_table);
 385                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 386                                qca956x_1p0_common_wo_xlna_rx_gain_bounds);
 387                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 388                                qca956x_1p0_modes_no_xpa_tx_gain_table);
 389
 390                 INIT_INI_ARRAY(&ah->ini_dfs,
 391                                qca956x_1p0_baseband_postamble_dfs_channel);
 392                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 393                                qca956x_1p0_baseband_core_txfir_coeff_japan_2484);
 394                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 395                                qca956x_1p0_modes_fast_clock);
 396         } else if (AR_SREV_9580(ah)) {
 397                 /* mac */
 398                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 399                                 ar9580_1p0_mac_core);
 400                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 401                                 ar9580_1p0_mac_postamble);
 402
 403                 /* bb */
 404                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 405                                 ar9580_1p0_baseband_core);
 406                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 407                                 ar9580_1p0_baseband_postamble);
 408
 409                 /* radio */
 410                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 411                                 ar9580_1p0_radio_core);
 412                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 413                                 ar9580_1p0_radio_postamble);
 414
 415                 /* soc */
 416                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 417                                 ar9580_1p0_soc_preamble);
 418                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 419                                 ar9580_1p0_soc_postamble);
 420
 421                 /* rx/tx gain */
 422                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 423                                 ar9580_1p0_rx_gain_table);
 424                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 425                                 ar9580_1p0_low_ob_db_tx_gain_table);
 426
 427                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 428                                ar9580_1p0_modes_fast_clock);
 429                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 430                                ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 431                 INIT_INI_ARRAY(&ah->ini_dfs,
 432                                ar9580_1p0_baseband_postamble_dfs_channel);
 433         } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 434                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 435                                ar9565_1p1_mac_core);
 436                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 437                                ar9565_1p1_mac_postamble);
 438
 439                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 440                                ar9565_1p1_baseband_core);
 441                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 442                                ar9565_1p1_baseband_postamble);
 443
 444                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 445                                ar9565_1p1_radio_core);
 446                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 447                                ar9565_1p1_radio_postamble);
 448
 449                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 450                                ar9565_1p1_soc_preamble);
 451                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 452                                ar9565_1p1_soc_postamble);
 453
 454                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 455                                ar9565_1p1_Common_rx_gain_table);
 456                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 457                                ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 458
 459                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 460                                ar9565_1p1_pciephy_clkreq_disable_L1);
 461                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 462                                ar9565_1p1_pciephy_clkreq_disable_L1);
 463
 464                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 465                                 ar9565_1p1_modes_fast_clock);
 466                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 467                                ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 468         } else if (AR_SREV_9565(ah)) {
 469                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 470                                ar9565_1p0_mac_core);
 471                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 472                                ar9565_1p0_mac_postamble);
 473
 474                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 475                                ar9565_1p0_baseband_core);
 476                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 477                                ar9565_1p0_baseband_postamble);
 478
 479                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 480                                ar9565_1p0_radio_core);
 481                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 482                                ar9565_1p0_radio_postamble);
 483
 484                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 485                                ar9565_1p0_soc_preamble);
 486                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 487                                ar9565_1p0_soc_postamble);
 488
 489                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 490                                ar9565_1p0_Common_rx_gain_table);
 491                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 492                                ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
 493
 494                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 495                                ar9565_1p0_pciephy_clkreq_disable_L1);
 496                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 497                                ar9565_1p0_pciephy_clkreq_disable_L1);
 498
 499                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 500                                 ar9565_1p0_modes_fast_clock);
 501                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 502                                ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
 503         } else {
 504                 /* mac */
 505                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 506                                 ar9300_2p2_mac_core);
 507                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 508                                 ar9300_2p2_mac_postamble);
 509
 510                 /* bb */
 511                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 512                                 ar9300_2p2_baseband_core);
 513                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 514                                 ar9300_2p2_baseband_postamble);
 515
 516                 /* radio */
 517                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 518                                 ar9300_2p2_radio_core);
 519                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 520                                 ar9300_2p2_radio_postamble);
 521
 522                 /* soc */
 523                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 524                                 ar9300_2p2_soc_preamble);
 525                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 526                                 ar9300_2p2_soc_postamble);
 527
 528                 /* rx/tx gain */
 529                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 530                                 ar9300Common_rx_gain_table_2p2);
 531                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 532                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 533
 534                 /* Load PCIE SERDES settings from INI */
 535
 536                 /* Awake Setting */
 537
 538                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 539                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 540
 541                 /* Sleep Setting */
 542
 543                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 544                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 545
 546                 /* Fast clock modal settings */
 547                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 548                                ar9300Modes_fast_clock_2p2);
 549                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 550                                ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 551                 INIT_INI_ARRAY(&ah->ini_dfs,
 552                                ar9300_2p2_baseband_postamble_dfs_channel);
 553         }
 554 }
 555
 556 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 557 {
 558         if (AR_SREV_9330_12(ah))
 559                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 560                         ar9331_modes_lowest_ob_db_tx_gain_1p2);
 561         else if (AR_SREV_9330_11(ah))
 562                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 563                         ar9331_modes_lowest_ob_db_tx_gain_1p1);
 564         else if (AR_SREV_9340(ah))
 565                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 566                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
 567         else if (AR_SREV_9485_11_OR_LATER(ah))
 568                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 569                         ar9485_modes_lowest_ob_db_tx_gain_1_1);
 570         else if (AR_SREV_9550(ah))
 571                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 572                         ar955x_1p0_modes_xpa_tx_gain_table);
 573         else if (AR_SREV_9531_10(ah))
 574                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 575                                qca953x_1p0_modes_xpa_tx_gain_table);
 576         else if (AR_SREV_9531_11(ah))
 577                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 578                                qca953x_1p1_modes_xpa_tx_gain_table);
 579         else if (AR_SREV_9531_20(ah))
 580                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 581                                qca953x_2p0_modes_xpa_tx_gain_table);
 582         else if (AR_SREV_9561(ah))
 583                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 584                                qca956x_1p0_modes_xpa_tx_gain_table);
 585         else if (AR_SREV_9580(ah))
 586                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 587                         ar9580_1p0_lowest_ob_db_tx_gain_table);
 588         else if (AR_SREV_9462_21(ah))
 589                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 590                         ar9462_2p1_modes_low_ob_db_tx_gain);
 591         else if (AR_SREV_9462_20(ah))
 592                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 593                         ar9462_2p0_modes_low_ob_db_tx_gain);
 594         else if (AR_SREV_9565_11(ah))
 595                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 596                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 597         else if (AR_SREV_9565(ah))
 598                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 599                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 600         else
 601                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 602                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 603 }
 604
 605 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 606 {
 607         if (AR_SREV_9330_12(ah))
 608                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 609                         ar9331_modes_high_ob_db_tx_gain_1p2);
 610         else if (AR_SREV_9330_11(ah))
 611                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 612                         ar9331_modes_high_ob_db_tx_gain_1p1);
 613         else if (AR_SREV_9340(ah))
 614                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 615                         ar9340Modes_high_ob_db_tx_gain_table_1p0);
 616         else if (AR_SREV_9485_11_OR_LATER(ah))
 617                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 618                         ar9485Modes_high_ob_db_tx_gain_1_1);
 619         else if (AR_SREV_9580(ah))
 620                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 621                         ar9580_1p0_high_ob_db_tx_gain_table);
 622         else if (AR_SREV_9550(ah))
 623                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 624                         ar955x_1p0_modes_no_xpa_tx_gain_table);
 625         else if (AR_SREV_9531(ah)) {
 626                 if (AR_SREV_9531_20(ah))
 627                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 628                                        qca953x_2p0_modes_no_xpa_tx_gain_table);
 629                 else if (AR_SREV_9531_11(ah))
 630                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 631                                        qca953x_1p1_modes_no_xpa_tx_gain_table);
 632                 else
 633                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 634                                        qca953x_1p0_modes_no_xpa_tx_gain_table);
 635         } else if (AR_SREV_9561(ah))
 636                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 637                                qca956x_1p0_modes_no_xpa_tx_gain_table);
 638         else if (AR_SREV_9462_21(ah))
 639                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 640                         ar9462_2p1_modes_high_ob_db_tx_gain);
 641         else if (AR_SREV_9462_20(ah))
 642                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 643                         ar9462_2p0_modes_high_ob_db_tx_gain);
 644         else if (AR_SREV_9565_11(ah))
 645                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 646                                ar9565_1p1_modes_high_ob_db_tx_gain_table);
 647         else if (AR_SREV_9565(ah))
 648                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 649                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 650         else
 651                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 652                         ar9300Modes_high_ob_db_tx_gain_table_2p2);
 653 }
 654
 655 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 656 {
 657         if (AR_SREV_9330_12(ah))
 658                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 659                         ar9331_modes_low_ob_db_tx_gain_1p2);
 660         else if (AR_SREV_9330_11(ah))
 661                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 662                         ar9331_modes_low_ob_db_tx_gain_1p1);
 663         else if (AR_SREV_9340(ah))
 664                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 665                         ar9340Modes_low_ob_db_tx_gain_table_1p0);
 666         else if (AR_SREV_9485_11_OR_LATER(ah))
 667                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 668                         ar9485Modes_low_ob_db_tx_gain_1_1);
 669         else if (AR_SREV_9580(ah))
 670                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 671                         ar9580_1p0_low_ob_db_tx_gain_table);
 672         else if (AR_SREV_9561(ah))
 673                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 674                                qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table);
 675         else if (AR_SREV_9565_11(ah))
 676                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 677                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 678         else if (AR_SREV_9565(ah))
 679                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 680                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 681         else
 682                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 683                         ar9300Modes_low_ob_db_tx_gain_table_2p2);
 684 }
 685
 686 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 687 {
 688         if (AR_SREV_9330_12(ah))
 689                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 690                         ar9331_modes_high_power_tx_gain_1p2);
 691         else if (AR_SREV_9330_11(ah))
 692                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 693                         ar9331_modes_high_power_tx_gain_1p1);
 694         else if (AR_SREV_9340(ah))
 695                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 696                         ar9340Modes_high_power_tx_gain_table_1p0);
 697         else if (AR_SREV_9485_11_OR_LATER(ah))
 698                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 699                         ar9485Modes_high_power_tx_gain_1_1);
 700         else if (AR_SREV_9580(ah))
 701                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 702                         ar9580_1p0_high_power_tx_gain_table);
 703         else if (AR_SREV_9565_11(ah))
 704                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 705                                ar9565_1p1_modes_high_power_tx_gain_table);
 706         else if (AR_SREV_9565(ah))
 707                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 708                                ar9565_1p0_modes_high_power_tx_gain_table);
 709         else {
 710                 if (ah->config.tx_gain_buffalo)
 711                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 712                                        ar9300Modes_high_power_tx_gain_table_buffalo);
 713                 else
 714                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 715                                        ar9300Modes_high_power_tx_gain_table_2p2);
 716         }
 717 }
 718
 719 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 720 {
 721         if (AR_SREV_9340(ah))
 722                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 723                         ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
 724         else if (AR_SREV_9580(ah))
 725                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 726                         ar9580_1p0_mixed_ob_db_tx_gain_table);
 727         else if (AR_SREV_9462_21(ah))
 728                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 729                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 730         else if (AR_SREV_9462_20(ah))
 731                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 732                        ar9462_2p0_modes_mix_ob_db_tx_gain);
 733         else
 734                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 735                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 736 }
 737
 738 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
 739 {
 740         if (AR_SREV_9485_11_OR_LATER(ah))
 741                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 742                         ar9485Modes_green_ob_db_tx_gain_1_1);
 743         else if (AR_SREV_9580(ah))
 744                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 745                         ar9580_1p0_type5_tx_gain_table);
 746         else if (AR_SREV_9561(ah))
 747                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 748                                qca956x_1p0_modes_no_xpa_green_tx_gain_table);
 749         else if (AR_SREV_9300_22(ah))
 750                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 751                         ar9300Modes_type5_tx_gain_table_2p2);
 752 }
 753
 754 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
 755 {
 756         if (AR_SREV_9340(ah))
 757                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 758                         ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
 759         else if (AR_SREV_9485_11_OR_LATER(ah))
 760                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 761                         ar9485Modes_green_spur_ob_db_tx_gain_1_1);
 762         else if (AR_SREV_9580(ah))
 763                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 764                         ar9580_1p0_type6_tx_gain_table);
 765 }
 766
 767 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 768 {
 769         if (AR_SREV_9340(ah))
 770                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 771                                ar9340_cus227_tx_gain_table_1p0);
 772 }
 773
 774 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 775
 776 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 777 {
 778         static const ath_txgain_tab modes[] = {
 779                 ar9003_tx_gain_table_mode0,
 780                 ar9003_tx_gain_table_mode1,
 781                 ar9003_tx_gain_table_mode2,
 782                 ar9003_tx_gain_table_mode3,
 783                 ar9003_tx_gain_table_mode4,
 784                 ar9003_tx_gain_table_mode5,
 785                 ar9003_tx_gain_table_mode6,
 786                 ar9003_tx_gain_table_mode7,
 787         };
 788         int idx = ar9003_hw_get_tx_gain_idx(ah);
 789
 790         if (idx >= ARRAY_SIZE(modes))
 791                 idx = 0;
 792
 793         modes[idx](ah);
 794 }
 795
 796 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 797 {
 798         if (AR_SREV_9330_12(ah))
 799                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 800                                 ar9331_common_rx_gain_1p2);
 801         else if (AR_SREV_9330_11(ah))
 802                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 803                                 ar9331_common_rx_gain_1p1);
 804         else if (AR_SREV_9340(ah))
 805                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 806                                 ar9340Common_rx_gain_table_1p0);
 807         else if (AR_SREV_9485_11_OR_LATER(ah))
 808                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 809                                ar9485_common_rx_gain_1_1);
 810         else if (AR_SREV_9550(ah)) {
 811                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 812                                 ar955x_1p0_common_rx_gain_table);
 813                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 814                                 ar955x_1p0_common_rx_gain_bounds);
 815         } else if (AR_SREV_9531(ah)) {
 816                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 817                                qca953x_1p0_common_rx_gain_table);
 818                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 819                                qca953x_1p0_common_rx_gain_bounds);
 820         } else if (AR_SREV_9561(ah)) {
 821                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 822                                qca956x_1p0_common_rx_gain_table);
 823                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 824                                qca956x_1p0_common_rx_gain_bounds);
 825                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 826                                qca956x_1p0_xlna_only);
 827         } else if (AR_SREV_9580(ah))
 828                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 829                                 ar9580_1p0_rx_gain_table);
 830         else if (AR_SREV_9462_21(ah))
 831                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 832                                 ar9462_2p1_common_rx_gain);
 833         else if (AR_SREV_9462_20(ah))
 834                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 835                                 ar9462_2p0_common_rx_gain);
 836         else if (AR_SREV_9565_11(ah))
 837                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 838                                ar9565_1p1_Common_rx_gain_table);
 839         else if (AR_SREV_9565(ah))
 840                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 841                                ar9565_1p0_Common_rx_gain_table);
 842         else
 843                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 844                                 ar9300Common_rx_gain_table_2p2);
 845 }
 846
 847 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 848 {
 849         if (AR_SREV_9330_12(ah))
 850                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 851                         ar9331_common_wo_xlna_rx_gain_1p2);
 852         else if (AR_SREV_9330_11(ah))
 853                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 854                         ar9331_common_wo_xlna_rx_gain_1p1);
 855         else if (AR_SREV_9340(ah))
 856                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 857                         ar9340Common_wo_xlna_rx_gain_table_1p0);
 858         else if (AR_SREV_9485_11_OR_LATER(ah))
 859                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 860                         ar9485Common_wo_xlna_rx_gain_1_1);
 861         else if (AR_SREV_9462_21(ah))
 862                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 863                         ar9462_2p1_common_wo_xlna_rx_gain);
 864         else if (AR_SREV_9462_20(ah))
 865                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 866                         ar9462_2p0_common_wo_xlna_rx_gain);
 867         else if (AR_SREV_9550(ah)) {
 868                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 869                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 870                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 871                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 872         } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {
 873                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 874                                qca953x_1p0_common_wo_xlna_rx_gain_table);
 875                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 876                                qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 877         } else if (AR_SREV_9531_20(ah)) {
 878                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 879                                qca953x_2p0_common_wo_xlna_rx_gain_table);
 880                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 881                                qca953x_2p0_common_wo_xlna_rx_gain_bounds);
 882         } else if (AR_SREV_9561(ah)) {
 883                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 884                                qca956x_1p0_common_wo_xlna_rx_gain_table);
 885                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 886                                qca956x_1p0_common_wo_xlna_rx_gain_bounds);
 887         } else if (AR_SREV_9580(ah))
 888                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 889                         ar9580_1p0_wo_xlna_rx_gain_table);
 890         else if (AR_SREV_9565_11(ah))
 891                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 892                                ar9565_1p1_common_wo_xlna_rx_gain_table);
 893         else if (AR_SREV_9565(ah))
 894                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 895                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 896         else
 897                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 898                         ar9300Common_wo_xlna_rx_gain_table_2p2);
 899 }
 900
 901 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 902 {
 903         if (AR_SREV_9462_21(ah)) {
 904                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 905                                ar9462_2p1_common_mixed_rx_gain);
 906                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 907                                ar9462_2p1_baseband_core_mix_rxgain);
 908                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 909                                ar9462_2p1_baseband_postamble_mix_rxgain);
 910                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 911                                ar9462_2p1_baseband_postamble_5g_xlna);
 912         } else if (AR_SREV_9462_20(ah)) {
 913                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 914                                ar9462_2p0_common_mixed_rx_gain);
 915                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 916                                ar9462_2p0_baseband_core_mix_rxgain);
 917                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 918                                ar9462_2p0_baseband_postamble_mix_rxgain);
 919                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 920                                ar9462_2p0_baseband_postamble_5g_xlna);
 921         }
 922 }
 923
 924 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
 925 {
 926         if (AR_SREV_9462_21(ah)) {
 927                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 928                                ar9462_2p1_common_5g_xlna_only_rxgain);
 929                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 930                                ar9462_2p1_baseband_postamble_5g_xlna);
 931         } else if (AR_SREV_9462_20(ah)) {
 932                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 933                                ar9462_2p0_common_5g_xlna_only_rxgain);
 934                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 935                                ar9462_2p0_baseband_postamble_5g_xlna);
 936         }
 937 }
 938
 939 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 940 {
 941         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 942         case 0:
 943         default:
 944                 ar9003_rx_gain_table_mode0(ah);
 945                 break;
 946         case 1:
 947                 ar9003_rx_gain_table_mode1(ah);
 948                 break;
 949         case 2:
 950                 ar9003_rx_gain_table_mode2(ah);
 951                 break;
 952         case 3:
 953                 ar9003_rx_gain_table_mode3(ah);
 954                 break;
 955         }
 956 }
 957
 958 /* set gain table pointers according to values read from the eeprom */
 959 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 960 {
 961         ar9003_tx_gain_table_apply(ah);
 962         ar9003_rx_gain_table_apply(ah);
 963 }
 964
 965 /*
 966  * Helper for ASPM support.
 967  *
 968  * Disable PLL when in L0s as well as receiver clock when in L1.
 969  * This power saving option must be enabled through the SerDes.
 970  *
 971  * Programming the SerDes must go through the same 288 bit serial shift
 972  * register as the other analog registers.  Hence the 9 writes.
 973  */
 974 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 975                                          bool power_off)
 976 {
 977         unsigned int i;
 978         struct ar5416IniArray *array;
 979
 980         /*
 981          * Increase L1 Entry Latency. Some WB222 boards don't have
 982          * this change in eeprom/OTP.
 983          *
 984          */
 985         if (AR_SREV_9462(ah)) {
 986                 u32 val = ah->config.aspm_l1_fix;
 987                 if ((val & 0xff000000) == 0x17000000) {
 988                         val &= 0x00ffffff;
 989                         val |= 0x27000000;
 990                         REG_WRITE(ah, 0x570c, val);
 991                 }
 992         }
 993
 994         /* Nothing to do on restore for 11N */
 995         if (!power_off /* !restore */) {
 996                 /* set bit 19 to allow forcing of pcie core into L1 state */
 997                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 998                 REG_WRITE(ah, AR_WA, ah->WARegVal);
 999         }
1000
1001         /*
1002          * Configire PCIE after Ini init. SERDES values now come from ini file
1003          * This enables PCIe low power mode.
1004          */
1005         array = power_off ? &ah->iniPcieSerdes :
1006                 &ah->iniPcieSerdesLowPower;
1007
1008         for (i = 0; i < array->ia_rows; i++) {
1009                 REG_WRITE(ah,
1010                           INI_RA(array, i, 0),
1011                           INI_RA(array, i, 1));
1012         }
1013 }
1014
1015 static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
1016 {
1017         /*
1018          * All chips support detection of BB/MAC hangs.
1019          */
1020         ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
1021         ah->config.hw_hang_checks |= HW_MAC_HANG;
1022
1023         /*
1024          * This is not required for AR9580 1.0
1025          */
1026         if (AR_SREV_9300_22(ah))
1027                 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
1028
1029         if (AR_SREV_9330(ah))
1030                 ah->bb_watchdog_timeout_ms = 85;
1031         else
1032                 ah->bb_watchdog_timeout_ms = 25;
1033 }
1034
1035 /*
1036  * MAC HW hang check
1037  * =================
1038  *
1039  * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
1040  *
1041  * The state of each DCU chain (mapped to TX queues) is available from these
1042  * DMA debug registers:
1043  *
1044  * Chain 0 state : Bits 4:0   of AR_DMADBG_4
1045  * Chain 1 state : Bits 9:5   of AR_DMADBG_4
1046  * Chain 2 state : Bits 14:10 of AR_DMADBG_4
1047  * Chain 3 state : Bits 19:15 of AR_DMADBG_4
1048  * Chain 4 state : Bits 24:20 of AR_DMADBG_4
1049  * Chain 5 state : Bits 29:25 of AR_DMADBG_4
1050  * Chain 6 state : Bits 4:0   of AR_DMADBG_5
1051  * Chain 7 state : Bits 9:5   of AR_DMADBG_5
1052  * Chain 8 state : Bits 14:10 of AR_DMADBG_5
1053  * Chain 9 state : Bits 19:15 of AR_DMADBG_5
1054  *
1055  * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
1056  */
1057
1058 #define NUM_STATUS_READS 50
1059
1060 static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
1061 {
1062         u32 dma_dbg_chain, dma_dbg_complete;
1063         u8 dcu_chain_state, dcu_complete_state;
1064         int i;
1065
1066         for (i = 0; i < NUM_STATUS_READS; i++) {
1067                 if (queue < 6)
1068                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
1069                 else
1070                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
1071
1072                 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
1073
1074                 dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
1075                 dcu_complete_state = dma_dbg_complete & 0x3;
1076
1077                 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
1078                         return false;
1079         }
1080
1081         ath_dbg(ath9k_hw_common(ah), RESET,
1082                 "MAC Hang signature found for queue: %d\n", queue);
1083
1084         return true;
1085 }
1086
1087 static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
1088 {
1089         u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
1090         u8 dcu_chain_state, dcu_complete_state;
1091         bool dcu_wait_frdone = false;
1092         unsigned long chk_dcu = 0;
1093         unsigned int i = 0;
1094
1095         dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1096         dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1097         dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1098
1099         dcu_complete_state = dma_dbg_6 & 0x3;
1100         if (dcu_complete_state != 0x1)
1101                 goto exit;
1102
1103         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1104                 if (i < 6)
1105                         chk_dbg = dma_dbg_4;
1106                 else
1107                         chk_dbg = dma_dbg_5;
1108
1109                 dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
1110                 if (dcu_chain_state == 0x6) {
1111                         dcu_wait_frdone = true;
1112                         chk_dcu |= BIT(i);
1113                 }
1114         }
1115
1116         if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
1117                 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
1118                         if (ath9k_hw_verify_hang(ah, i))
1119                                 return true;
1120                 }
1121         }
1122 exit:
1123         return false;
1124 }
1125
1126 /* Sets up the AR9003 hardware familiy callbacks */
1127 void ar9003_hw_attach_ops(struct ath_hw *ah)
1128 {
1129         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1130         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1131
1132         ar9003_hw_init_mode_regs(ah);
1133         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
1134         priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
1135         priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
1136
1137         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
1138
1139         ar9003_hw_attach_phy_ops(ah);
1140         ar9003_hw_attach_calib_ops(ah);
1141         ar9003_hw_attach_mac_ops(ah);
1142 }