2 * PCIe host controller driver for Freescale Layerscape SoCs
4 * Copyright (C) 2014 Freescale Semiconductor.
6 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of_pci.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include "pcie-designware.h"
28 /* PEX1/2 Misc Ports Status Register */
29 #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
30 #define LTSSM_STATE_SHIFT 20
31 #define LTSSM_STATE_MASK 0x3f
32 #define LTSSM_PCIE_L0 0x11 /* L0 state */
34 /* Symbol Timer Register and Filter Mask Register 1 */
35 #define PCIE_STRFMR1 0x71c
37 struct ls_pcie_drvdata {
38 struct pcie_host_ops *ops;
45 const struct ls_pcie_drvdata *drvdata;
50 #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
52 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
56 header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE);
59 return header_type == PCI_HEADER_TYPE_BRIDGE;
62 static int ls1021_pcie_link_up(struct pcie_port *pp)
65 struct ls_pcie *pcie = to_ls_pcie(pp);
70 regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
71 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
73 if (state < LTSSM_PCIE_L0)
79 static void ls1021_pcie_host_init(struct pcie_port *pp)
81 struct ls_pcie *pcie = to_ls_pcie(pp);
84 pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
86 if (IS_ERR(pcie->scfg)) {
87 dev_err(pp->dev, "No syscfg phandle specified\n");
92 if (of_property_read_u32_array(pp->dev->of_node,
93 "fsl,pcie-scfg", index, 2)) {
97 pcie->index = index[1];
102 * LS1021A Workaround for internal TKT228622
103 * to fix the INTx hang issue
105 val = ioread32(pcie->dbi + PCIE_STRFMR1);
107 iowrite32(val, pcie->dbi + PCIE_STRFMR1);
110 static struct pcie_host_ops ls1021_pcie_host_ops = {
111 .link_up = ls1021_pcie_link_up,
112 .host_init = ls1021_pcie_host_init,
115 static struct ls_pcie_drvdata ls1021_drvdata = {
116 .ops = &ls1021_pcie_host_ops,
119 static const struct of_device_id ls_pcie_of_match[] = {
120 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
123 MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
125 static int __init ls_add_pcie_port(struct pcie_port *pp,
126 struct platform_device *pdev)
129 struct ls_pcie *pcie = to_ls_pcie(pp);
131 pp->dev = &pdev->dev;
132 pp->dbi_base = pcie->dbi;
133 pp->ops = pcie->drvdata->ops;
135 ret = dw_pcie_host_init(pp);
137 dev_err(pp->dev, "failed to initialize host\n");
144 static int __init ls_pcie_probe(struct platform_device *pdev)
146 const struct of_device_id *match;
147 struct ls_pcie *pcie;
148 struct resource *dbi_base;
151 match = of_match_device(ls_pcie_of_match, &pdev->dev);
155 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
159 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
160 pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
161 if (IS_ERR(pcie->dbi)) {
162 dev_err(&pdev->dev, "missing *regs* space\n");
163 return PTR_ERR(pcie->dbi);
166 pcie->drvdata = match->data;
168 if (!ls_pcie_is_bridge(pcie))
171 ret = ls_add_pcie_port(&pcie->pp, pdev);
175 platform_set_drvdata(pdev, pcie);
180 static struct platform_driver ls_pcie_driver = {
182 .name = "layerscape-pcie",
183 .of_match_table = ls_pcie_of_match,
187 module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
189 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
190 MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
191 MODULE_LICENSE("GPL v2");