2 * PCIe host controller driver for Freescale Layerscape SoCs
4 * Copyright (C) 2014 Freescale Semiconductor.
6 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of_pci.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include "pcie-designware.h"
28 /* PEX1/2 Misc Ports Status Register */
29 #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
30 #define LTSSM_STATE_SHIFT 20
31 #define LTSSM_STATE_MASK 0x3f
32 #define LTSSM_PCIE_L0 0x11 /* L0 state */
34 /* Symbol Timer Register and Filter Mask Register 1 */
35 #define PCIE_STRFMR1 0x71c
38 struct list_head node;
48 #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
50 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
54 header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE);
57 return header_type == PCI_HEADER_TYPE_BRIDGE;
60 static int ls_pcie_link_up(struct pcie_port *pp)
63 struct ls_pcie *pcie = to_ls_pcie(pp);
65 regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
66 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
68 if (state < LTSSM_PCIE_L0)
74 static void ls_pcie_host_init(struct pcie_port *pp)
76 struct ls_pcie *pcie = to_ls_pcie(pp);
82 * LS1021A Workaround for internal TKT228622
83 * to fix the INTx hang issue
85 val = ioread32(pcie->dbi + PCIE_STRFMR1);
87 iowrite32(val, pcie->dbi + PCIE_STRFMR1);
90 static struct pcie_host_ops ls_pcie_host_ops = {
91 .link_up = ls_pcie_link_up,
92 .host_init = ls_pcie_host_init,
95 static int ls_add_pcie_port(struct ls_pcie *pcie)
102 pp->dbi_base = pcie->dbi;
103 pp->root_bus_nr = -1;
104 pp->ops = &ls_pcie_host_ops;
106 ret = dw_pcie_host_init(pp);
108 dev_err(pp->dev, "failed to initialize host\n");
115 static int __init ls_pcie_probe(struct platform_device *pdev)
117 struct ls_pcie *pcie;
118 struct resource *dbi_base;
122 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
126 pcie->dev = &pdev->dev;
128 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
129 pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
130 if (IS_ERR(pcie->dbi)) {
131 dev_err(&pdev->dev, "missing *regs* space\n");
132 return PTR_ERR(pcie->dbi);
135 pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
137 if (IS_ERR(pcie->scfg)) {
138 dev_err(&pdev->dev, "No syscfg phandle specified\n");
139 return PTR_ERR(pcie->scfg);
142 ret = of_property_read_u32_array(pdev->dev.of_node,
143 "fsl,pcie-scfg", index, 2);
146 pcie->index = index[1];
148 if (!ls_pcie_is_bridge(pcie))
151 ret = ls_add_pcie_port(pcie);
155 platform_set_drvdata(pdev, pcie);
160 static const struct of_device_id ls_pcie_of_match[] = {
161 { .compatible = "fsl,ls1021a-pcie" },
164 MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
166 static struct platform_driver ls_pcie_driver = {
168 .name = "layerscape-pcie",
169 .of_match_table = ls_pcie_of_match,
173 module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
175 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
176 MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
177 MODULE_LICENSE("GPL v2");