drivers/pinctrl/sh-pfc/pfc-r8a7794.c

   1 /*
   2  * r8a7794 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Renesas Solutions Corp.
   6  * Copyright (C) 2015 Cogent  Embedded, Inc., <source@cogentembedded.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2
  10  * as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/platform_data/gpio-rcar.h>
  15
  16 #include "core.h"
  17 #include "sh_pfc.h"
  18
  19 #define PORT_GP_26(bank, fn, sfx)                                       \
  20         PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
  21         PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
  22         PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
  23         PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
  24         PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
  25         PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
  26         PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
  27         PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
  28         PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
  29         PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
  30         PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
  31         PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
  32         PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
  33
  34 #define PORT_GP_28(bank, fn, sfx)                                       \
  35         PORT_GP_26(bank, fn, sfx),                                      \
  36         PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx)
  37
  38 #define CPU_ALL_PORT(fn, sfx)                                           \
  39         PORT_GP_32(0, fn, sfx),                                         \
  40         PORT_GP_26(1, fn, sfx),                                         \
  41         PORT_GP_32(2, fn, sfx),                                         \
  42         PORT_GP_32(3, fn, sfx),                                         \
  43         PORT_GP_32(4, fn, sfx),                                         \
  44         PORT_GP_28(5, fn, sfx),                                         \
  45         PORT_GP_26(6, fn, sfx)
  46
  47 enum {
  48         PINMUX_RESERVED = 0,
  49
  50         PINMUX_DATA_BEGIN,
  51         GP_ALL(DATA),
  52         PINMUX_DATA_END,
  53
  54         PINMUX_FUNCTION_BEGIN,
  55         GP_ALL(FN),
  56
  57         /* GPSR0 */
  58         FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  59         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  60         FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  61         FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  62         FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  63         FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  64         FN_IP2_17_16,
  65
  66         /* GPSR1 */
  67         FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  68         FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  69         FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  70         FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  71         FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  72
  73         /* GPSR2 */
  74         FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  75         FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  76         FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  77         FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  78         FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  79         FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  80         FN_IP6_5_4, FN_IP6_7_6,
  81
  82         /* GPSR3 */
  83         FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  84         FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  85         FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  86         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  87         FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  88         FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  89         FN_IP8_22_20,
  90
  91         /* GPSR4 */
  92         FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  93         FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  94         FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  95         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  96         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  97         FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  98         FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  99
 100         /* GPSR5 */
 101         FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
 102         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
 103         FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
 104         FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
 105         FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
 106         FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
 107
 108         /* GPSR6 */
 109         FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
 110         FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
 111         FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
 112         FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
 113         FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
 114
 115         /* IPSR0 */
 116         FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
 117         FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
 118         FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
 119         FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
 120         FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
 121         FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
 122         FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
 123         FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 124
 125         /* IPSR1 */
 126         FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1,
 127         FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX,
 128         FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
 129         FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 130         FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
 131         FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
 132         FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
 133         FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
 134         FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 135         FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 136
 137         /* IPSR2 */
 138         FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
 139         FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
 140         FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B,
 141         FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
 142         FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 143         FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
 144         FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
 145         FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
 146         FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
 147         FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
 148         FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
 149
 150         /* IPSR3 */
 151         FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
 152         FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
 153         FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
 154         FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
 155         FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
 156         FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
 157         FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
 158         FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
 159         FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
 160         FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
 161         FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
 162         FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
 163         FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
 164
 165         /* IPSR4 */
 166         FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
 167         FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
 168         FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
 169         FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
 170         FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
 171         FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
 172         FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
 173         FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
 174         FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
 175         FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
 176         FN_LCDOUT12, FN_CC50_STATE12,
 177
 178         /* IPSR5 */
 179         FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
 180         FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
 181         FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
 182         FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
 183         FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
 184         FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
 185         FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
 186         FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
 187         FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
 188         FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
 189         FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
 190
 191         /* IPSR6 */
 192         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
 193         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
 194         FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
 195         FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
 196         FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
 197         FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
 198         FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
 199         FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
 200         FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
 201         FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
 202         FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
 203         FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
 204         FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
 205         FN_ADIDATA, FN_AD_DI,
 206
 207         /* IPSR7 */
 208         FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
 209         FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
 210         FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
 211         FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
 212         FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
 213         FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
 214         FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
 215         FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
 216         FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
 217         FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
 218         FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
 219         FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
 220         FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
 221
 222         /* IPSR8 */
 223         FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
 224         FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
 225         FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
 226         FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
 227         FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
 228         FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
 229         FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
 230         FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
 231         FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 232         FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
 233         FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
 234         FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
 235         FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
 236         FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
 237         FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
 238
 239         /* IPSR9 */
 240         FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
 241         FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
 242         FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
 243         FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
 244         FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
 245         FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
 246         FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
 247         FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
 248         FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
 249         FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
 250         FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
 251         FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
 252         FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
 253         FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
 254
 255         /* IPSR10 */
 256         FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
 257         FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
 258         FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
 259         FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
 260         FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
 261         FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
 262         FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
 263         FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
 264         FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
 265         FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
 266         FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
 267         FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
 268         FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
 269         FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
 270         FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
 271         FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
 272
 273         /* IPSR11 */
 274         FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
 275         FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
 276         FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
 277         FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
 278         FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
 279         FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
 280         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
 281         FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
 282         FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
 283         FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
 284         FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
 285         FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
 286         FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
 287         FN_ADICLK_B, FN_AD_CLK_B,
 288
 289         /* IPSR12 */
 290         FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
 291         FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
 292         FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
 293         FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
 294         FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
 295         FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
 296         FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
 297         FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
 298         FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
 299         FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
 300         FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
 301         FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
 302         FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
 303         FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
 304
 305         /* IPSR13 */
 306         FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
 307         FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
 308         FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
 309         FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
 310         FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
 311         FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
 312         FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
 313         FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
 314         FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
 315         FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
 316         FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
 317         FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
 318         FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
 319         FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
 320         FN_FMIN_E, FN_RDS_DATA_D,
 321
 322         /* MOD_SEL */
 323         FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
 324         FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
 325         FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
 326         FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
 327         FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
 328         FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
 329         FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
 330         FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
 331         FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
 332         FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
 333         FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 334         FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
 335         FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
 336         FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
 337
 338         /* MOD_SEL2 */
 339         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
 340         FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
 341         FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
 342         FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
 343         FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
 344         FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
 345         FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 346         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
 347         FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
 348         FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
 349         FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
 350         FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 351         FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 352         FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 353         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
 354         FN_SEL_RDS_2, FN_SEL_RDS_3,
 355
 356         /* MOD_SEL3 */
 357         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 358         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
 359         FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
 360         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 361         FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
 362         FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
 363         FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
 364         FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
 365         FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
 366         FN_SEL_SSI9_1,
 367         PINMUX_FUNCTION_END,
 368
 369         PINMUX_MARK_BEGIN,
 370         A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
 371
 372         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 373
 374         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
 375         SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 376
 377         SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
 378         SD1_DATA2_MARK, SD1_DATA3_MARK,
 379
 380         /* IPSR0 */
 381         SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
 382         MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
 383         SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
 384         SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
 385         MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
 386         CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
 387         CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
 388         SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
 389         SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
 390         SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 391
 392         /* IPSR1 */
 393         D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK,
 394         TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
 395         D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK,
 396         HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 397         D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 398         D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
 399         D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
 400         D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
 401         IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
 402         SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
 403         A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
 404         SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 405
 406         /* IPSR2 */
 407         A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
 408         SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
 409         A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
 410         IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
 411         A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
 412         HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
 413         HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
 414         HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
 415         TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
 416         CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
 417         SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
 418         MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
 419         SPCLK_MARK, MOUT1_MARK,
 420
 421         /* IPSR3 */
 422         A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
 423         MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
 424         ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
 425         ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
 426         VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
 427         TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
 428         PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
 429         TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
 430         SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
 431         BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
 432         SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
 433         FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
 434         SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
 435         FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
 436         PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
 437         ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
 438
 439         /* IPSR4 */
 440         EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
 441         DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
 442         CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
 443         I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
 444         CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
 445         DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
 446         LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
 447         CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
 448         DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
 449         CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
 450         I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
 451         CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
 452         DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
 453
 454         /* IPSR5 */
 455         DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
 456         LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
 457         CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
 458         I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
 459         LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
 460         CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
 461         DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
 462         LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
 463         CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
 464         DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
 465         QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
 466         QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
 467         CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 468         CC50_STATE27_MARK,
 469
 470         /* IPSR6 */
 471         DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
 472         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
 473         DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
 474         CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
 475         AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 476         VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
 477         AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 478         VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
 479         AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
 480         I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
 481         VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
 482         AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
 483         IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
 484         I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
 485         VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
 486         ADIDATA_MARK, AD_DI_MARK,
 487
 488         /* IPSR7 */
 489         ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
 490         AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
 491         MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
 492         AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
 493         CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
 494         ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
 495         AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
 496         MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
 497         ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 498         SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
 499         IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
 500         VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
 501         SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
 502         AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
 503         SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
 504         DREQ0_N_MARK, SCIFB1_RXD_MARK,
 505
 506         /* IPSR8 */
 507         ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
 508         AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
 509         I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
 510         HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
 511         AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
 512         SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
 513         HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
 514         AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
 515         HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
 516         I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
 517         AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 518         SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 519         CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
 520         DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
 521         I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
 522         TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
 523         I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
 524         FMCLK_C_MARK, RDS_CLK_MARK,
 525
 526         /* IPSR9 */
 527         MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
 528         RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
 529         MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
 530         TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
 531         RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
 532         TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
 533         MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
 534         RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
 535         I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
 536         I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
 537         PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
 538         VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
 539         DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
 540         CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
 541         DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
 542         SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
 543         CAN_TXCLK_MARK, CC50_STATE34_MARK,
 544
 545         /* IPSR10 */
 546         SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
 547         CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
 548         DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
 549         SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
 550         USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
 551         IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
 552         CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
 553         DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
 554         CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
 555         DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
 556         CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
 557         DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
 558         RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
 559         DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
 560         RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
 561         AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
 562         SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
 563         SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
 564
 565         /* IPSR11 */
 566         SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
 567         CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
 568         DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
 569         SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
 570         SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
 571         DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
 572         SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 573         CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
 574         DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
 575         DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
 576         AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
 577         MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
 578         PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
 579         ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
 580         PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
 581
 582         /* IPSR12 */
 583         SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
 584         AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
 585         SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
 586         SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
 587         CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
 588         IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
 589         SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
 590         SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
 591         DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
 592         IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
 593         ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
 594         VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
 595         SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
 596         ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
 597         VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
 598
 599         /* IPSR13 */
 600         SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
 601         SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
 602         HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
 603         ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
 604         PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
 605         ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
 606         VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
 607         SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
 608         ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
 609         VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
 610         AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
 611         TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
 612         AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
 613         TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
 614         AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
 615         TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
 616         PINMUX_MARK_END,
 617 };
 618
 619 static const u16 pinmux_data[] = {
 620         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 621
 622         PINMUX_DATA(A2_MARK, FN_A2),
 623         PINMUX_DATA(WE0_N_MARK, FN_WE0_N),
 624         PINMUX_DATA(WE1_N_MARK, FN_WE1_N),
 625         PINMUX_DATA(DACK0_MARK, FN_DACK0),
 626         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 627         PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
 628         PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
 629         PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
 630         PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
 631         PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
 632         PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0),
 633         PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1),
 634         PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2),
 635         PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3),
 636         PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
 637         PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
 638         PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
 639         PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD),
 640         PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0),
 641         PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1),
 642         PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
 643         PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
 644
 645         /* IPSR0 */
 646         PINMUX_IPSR_DATA(IP0_0, SD1_CD),
 647         PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
 648         PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
 649         PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
 650         PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
 651         PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
 652         PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
 653         PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
 654         PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
 655         PINMUX_IPSR_DATA(IP0_12, MMC_D0),
 656         PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
 657         PINMUX_IPSR_DATA(IP0_13, MMC_D1),
 658         PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
 659         PINMUX_IPSR_DATA(IP0_14, MMC_D2),
 660         PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
 661         PINMUX_IPSR_DATA(IP0_15, MMC_D3),
 662         PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
 663         PINMUX_IPSR_DATA(IP0_16, MMC_D4),
 664         PINMUX_IPSR_DATA(IP0_16, SD2_CD),
 665         PINMUX_IPSR_DATA(IP0_17, MMC_D5),
 666         PINMUX_IPSR_DATA(IP0_17, SD2_WP),
 667         PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
 668         PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
 669         PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
 670         PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
 671         PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
 672         PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
 673         PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
 674         PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
 675         PINMUX_IPSR_DATA(IP0_23_22, D0),
 676         PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
 677         PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
 678         PINMUX_IPSR_DATA(IP0_24, D1),
 679         PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
 680         PINMUX_IPSR_DATA(IP0_25, D2),
 681         PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
 682         PINMUX_IPSR_DATA(IP0_27_26, D3),
 683         PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
 684         PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
 685         PINMUX_IPSR_DATA(IP0_29_28, D4),
 686         PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
 687         PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
 688         PINMUX_IPSR_DATA(IP0_31_30, D5),
 689         PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
 690         PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 691
 692         /* IPSR1 */
 693         PINMUX_IPSR_DATA(IP1_1_0, D6),
 694         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
 695         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
 696         PINMUX_IPSR_DATA(IP1_3_2, D7),
 697         PINMUX_IPSR_DATA(IP1_3_2, IRQ3),
 698         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0),
 699         PINMUX_IPSR_DATA(IP1_3_2, PWM6_B),
 700         PINMUX_IPSR_DATA(IP1_5_4, D8),
 701         PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX),
 702         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
 703         PINMUX_IPSR_DATA(IP1_7_6, D9),
 704         PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX),
 705         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
 706         PINMUX_IPSR_DATA(IP1_10_8, D10),
 707         PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK),
 708         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
 709         PINMUX_IPSR_DATA(IP1_10_8, IRQ6),
 710         PINMUX_IPSR_DATA(IP1_10_8, PWM5_C),
 711         PINMUX_IPSR_DATA(IP1_12_11, D11),
 712         PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N),
 713         PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
 714         PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
 715         PINMUX_IPSR_DATA(IP1_14_13, D12),
 716         PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N),
 717         PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
 718         PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 719         PINMUX_IPSR_DATA(IP1_17_15, D13),
 720         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
 721         PINMUX_IPSR_DATA(IP1_17_15, TANS1),
 722         PINMUX_IPSR_DATA(IP1_17_15, PWM2_C),
 723         PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1),
 724         PINMUX_IPSR_DATA(IP1_19_18, D14),
 725         PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
 726         PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
 727         PINMUX_IPSR_DATA(IP1_21_20, D15),
 728         PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
 729         PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
 730         PINMUX_IPSR_DATA(IP1_23_22, A0),
 731         PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK),
 732         PINMUX_IPSR_DATA(IP1_23_22, PWM3_B),
 733         PINMUX_IPSR_DATA(IP1_24, A1),
 734         PINMUX_IPSR_DATA(IP1_24, SCIFB1_TXD),
 735         PINMUX_IPSR_DATA(IP1_26, A3),
 736         PINMUX_IPSR_DATA(IP1_26, SCIFB0_SCK),
 737         PINMUX_IPSR_DATA(IP1_27, A4),
 738         PINMUX_IPSR_DATA(IP1_27, SCIFB0_TXD),
 739         PINMUX_IPSR_DATA(IP1_29_28, A5),
 740         PINMUX_IPSR_DATA(IP1_29_28, SCIFB0_RXD),
 741         PINMUX_IPSR_DATA(IP1_29_28, PWM4_B),
 742         PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C),
 743         PINMUX_IPSR_DATA(IP1_31_30, A6),
 744         PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N),
 745         PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
 746         PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C),
 747
 748         /* IPSR2 */
 749         PINMUX_IPSR_DATA(IP2_1_0, A7),
 750         PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N),
 751         PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
 752         PINMUX_IPSR_DATA(IP2_3_2, A8),
 753         PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
 754         PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
 755         PINMUX_IPSR_DATA(IP2_5_4, A9),
 756         PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
 757         PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
 758         PINMUX_IPSR_DATA(IP2_7_6, A10),
 759         PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
 760         PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
 761         PINMUX_IPSR_DATA(IP2_9_8, A11),
 762         PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
 763         PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
 764         PINMUX_IPSR_DATA(IP2_11_10, A12),
 765         PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
 766         PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
 767         PINMUX_IPSR_DATA(IP2_13_12, A13),
 768         PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
 769         PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
 770         PINMUX_IPSR_DATA(IP2_15_14, A14),
 771         PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
 772         PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
 773         PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0),
 774         PINMUX_IPSR_DATA(IP2_17_16, A15),
 775         PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
 776         PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
 777         PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0),
 778         PINMUX_IPSR_DATA(IP2_20_18, A16),
 779         PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 780         PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
 781         PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0),
 782         PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0),
 783         PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 784         PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B),
 785         PINMUX_IPSR_DATA(IP2_23_21, A17),
 786         PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 787         PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 788         PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
 789         PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
 790         PINMUX_IPSR_DATA(IP2_26_24, A18),
 791         PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 792         PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 793         PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
 794         PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
 795         PINMUX_IPSR_DATA(IP2_29_27, A19),
 796         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 797         PINMUX_IPSR_DATA(IP2_29_27, PWM4),
 798         PINMUX_IPSR_DATA(IP2_29_27, TPUTO2),
 799         PINMUX_IPSR_DATA(IP2_29_27, MOUT0),
 800         PINMUX_IPSR_DATA(IP2_31_30, A20),
 801         PINMUX_IPSR_DATA(IP2_31_30, SPCLK),
 802         PINMUX_IPSR_DATA(IP2_29_27, MOUT1),
 803
 804         /* IPSR3 */
 805         PINMUX_IPSR_DATA(IP3_1_0, A21),
 806         PINMUX_IPSR_DATA(IP3_1_0, MOSI_IO0),
 807         PINMUX_IPSR_DATA(IP3_1_0, MOUT2),
 808         PINMUX_IPSR_DATA(IP3_3_2, A22),
 809         PINMUX_IPSR_DATA(IP3_3_2, MISO_IO1),
 810         PINMUX_IPSR_DATA(IP3_3_2, MOUT5),
 811         PINMUX_IPSR_DATA(IP3_3_2, ATADIR1_N),
 812         PINMUX_IPSR_DATA(IP3_5_4, A23),
 813         PINMUX_IPSR_DATA(IP3_5_4, IO2),
 814         PINMUX_IPSR_DATA(IP3_5_4, MOUT6),
 815         PINMUX_IPSR_DATA(IP3_5_4, ATAWR1_N),
 816         PINMUX_IPSR_DATA(IP3_7_6, A24),
 817         PINMUX_IPSR_DATA(IP3_7_6, IO3),
 818         PINMUX_IPSR_DATA(IP3_7_6, EX_WAIT2),
 819         PINMUX_IPSR_DATA(IP3_9_8, A25),
 820         PINMUX_IPSR_DATA(IP3_9_8, SSL),
 821         PINMUX_IPSR_DATA(IP3_9_8, ATARD1_N),
 822         PINMUX_IPSR_DATA(IP3_10, CS0_N),
 823         PINMUX_IPSR_DATA(IP3_10, VI1_DATA8),
 824         PINMUX_IPSR_DATA(IP3_11, CS1_N_A26),
 825         PINMUX_IPSR_DATA(IP3_11, VI1_DATA9),
 826         PINMUX_IPSR_DATA(IP3_12, EX_CS0_N),
 827         PINMUX_IPSR_DATA(IP3_12, VI1_DATA10),
 828         PINMUX_IPSR_DATA(IP3_14_13, EX_CS1_N),
 829         PINMUX_IPSR_DATA(IP3_14_13, TPUTO3_B),
 830         PINMUX_IPSR_DATA(IP3_14_13, SCIFB2_RXD),
 831         PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11),
 832         PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N),
 833         PINMUX_IPSR_DATA(IP3_17_15, PWM0),
 834         PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
 835         PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
 836         PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
 837         PINMUX_IPSR_DATA(IP3_17_15, TPUTO3),
 838         PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD),
 839         PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1),
 840         PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N),
 841         PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 842         PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
 843         PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
 844         PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0),
 845         PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0),
 846         PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK),
 847         PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1),
 848         PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N),
 849         PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 850         PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
 851         PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
 852         PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0),
 853         PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0),
 854         PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N),
 855         PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1),
 856         PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N),
 857         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 858         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
 859         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
 860         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0),
 861         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0),
 862         PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N),
 863         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1),
 864         PINMUX_IPSR_DATA(IP3_29_27, BS_N),
 865         PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
 866         PINMUX_IPSR_DATA(IP3_29_27, PWM1_C),
 867         PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C),
 868         PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N),
 869         PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1),
 870         PINMUX_IPSR_DATA(IP3_30, RD_N),
 871         PINMUX_IPSR_DATA(IP3_30, ATACS11_N),
 872         PINMUX_IPSR_DATA(IP3_31, RD_WR_N),
 873         PINMUX_IPSR_DATA(IP3_31, ATAG1_N),
 874
 875         /* IPSR4 */
 876         PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0),
 877         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 878         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
 879         PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0),
 880         PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0),
 881         PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16),
 882         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 883         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
 884         PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0),
 885         PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1),
 886         PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17),
 887         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 888         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
 889         PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1),
 890         PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2),
 891         PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18),
 892         PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE2),
 893         PINMUX_IPSR_DATA(IP4_11_10, DU0_DR3),
 894         PINMUX_IPSR_DATA(IP4_11_10, LCDOUT19),
 895         PINMUX_IPSR_DATA(IP4_11_10, CC50_STATE3),
 896         PINMUX_IPSR_DATA(IP4_13_12, DU0_DR4),
 897         PINMUX_IPSR_DATA(IP4_13_12, LCDOUT20),
 898         PINMUX_IPSR_DATA(IP4_13_12, CC50_STATE4),
 899         PINMUX_IPSR_DATA(IP4_15_14, DU0_DR5),
 900         PINMUX_IPSR_DATA(IP4_15_14, LCDOUT21),
 901         PINMUX_IPSR_DATA(IP4_15_14, CC50_STATE5),
 902         PINMUX_IPSR_DATA(IP4_17_16, DU0_DR6),
 903         PINMUX_IPSR_DATA(IP4_17_16, LCDOUT22),
 904         PINMUX_IPSR_DATA(IP4_17_16, CC50_STATE6),
 905         PINMUX_IPSR_DATA(IP4_19_18, DU0_DR7),
 906         PINMUX_IPSR_DATA(IP4_19_18, LCDOUT23),
 907         PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7),
 908         PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0),
 909         PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8),
 910         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 911         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
 912         PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8),
 913         PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1),
 914         PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9),
 915         PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 916         PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
 917         PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9),
 918         PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2),
 919         PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10),
 920         PINMUX_IPSR_DATA(IP4_27_26, CC50_STATE10),
 921         PINMUX_IPSR_DATA(IP4_29_28, DU0_DG3),
 922         PINMUX_IPSR_DATA(IP4_29_28, LCDOUT11),
 923         PINMUX_IPSR_DATA(IP4_29_28, CC50_STATE11),
 924         PINMUX_IPSR_DATA(IP4_31_30, DU0_DG4),
 925         PINMUX_IPSR_DATA(IP4_31_30, LCDOUT12),
 926         PINMUX_IPSR_DATA(IP4_31_30, CC50_STATE12),
 927
 928         /* IPSR5 */
 929         PINMUX_IPSR_DATA(IP5_1_0, DU0_DG5),
 930         PINMUX_IPSR_DATA(IP5_1_0, LCDOUT13),
 931         PINMUX_IPSR_DATA(IP5_1_0, CC50_STATE13),
 932         PINMUX_IPSR_DATA(IP5_3_2, DU0_DG6),
 933         PINMUX_IPSR_DATA(IP5_3_2, LCDOUT14),
 934         PINMUX_IPSR_DATA(IP5_3_2, CC50_STATE14),
 935         PINMUX_IPSR_DATA(IP5_5_4, DU0_DG7),
 936         PINMUX_IPSR_DATA(IP5_5_4, LCDOUT15),
 937         PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15),
 938         PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0),
 939         PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0),
 940         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 941         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 942         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
 943         PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16),
 944         PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1),
 945         PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1),
 946         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 947         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 948         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
 949         PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17),
 950         PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2),
 951         PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2),
 952         PINMUX_IPSR_DATA(IP5_13_12, CC50_STATE18),
 953         PINMUX_IPSR_DATA(IP5_15_14, DU0_DB3),
 954         PINMUX_IPSR_DATA(IP5_15_14, LCDOUT3),
 955         PINMUX_IPSR_DATA(IP5_15_14, CC50_STATE19),
 956         PINMUX_IPSR_DATA(IP5_17_16, DU0_DB4),
 957         PINMUX_IPSR_DATA(IP5_17_16, LCDOUT4),
 958         PINMUX_IPSR_DATA(IP5_17_16, CC50_STATE20),
 959         PINMUX_IPSR_DATA(IP5_19_18, DU0_DB5),
 960         PINMUX_IPSR_DATA(IP5_19_18, LCDOUT5),
 961         PINMUX_IPSR_DATA(IP5_19_18, CC50_STATE21),
 962         PINMUX_IPSR_DATA(IP5_21_20, DU0_DB6),
 963         PINMUX_IPSR_DATA(IP5_21_20, LCDOUT6),
 964         PINMUX_IPSR_DATA(IP5_21_20, CC50_STATE22),
 965         PINMUX_IPSR_DATA(IP5_23_22, DU0_DB7),
 966         PINMUX_IPSR_DATA(IP5_23_22, LCDOUT7),
 967         PINMUX_IPSR_DATA(IP5_23_22, CC50_STATE23),
 968         PINMUX_IPSR_DATA(IP5_25_24, DU0_DOTCLKIN),
 969         PINMUX_IPSR_DATA(IP5_25_24, QSTVA_QVS),
 970         PINMUX_IPSR_DATA(IP5_25_24, CC50_STATE24),
 971         PINMUX_IPSR_DATA(IP5_27_26, DU0_DOTCLKOUT0),
 972         PINMUX_IPSR_DATA(IP5_27_26, QCLK),
 973         PINMUX_IPSR_DATA(IP5_27_26, CC50_STATE25),
 974         PINMUX_IPSR_DATA(IP5_29_28, DU0_DOTCLKOUT1),
 975         PINMUX_IPSR_DATA(IP5_29_28, QSTVB_QVE),
 976         PINMUX_IPSR_DATA(IP5_29_28, CC50_STATE26),
 977         PINMUX_IPSR_DATA(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
 978         PINMUX_IPSR_DATA(IP5_31_30, QSTH_QHS),
 979         PINMUX_IPSR_DATA(IP5_31_30, CC50_STATE27),
 980
 981         /* IPSR6 */
 982         PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
 983         PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE),
 984         PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28),
 985         PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 986         PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE),
 987         PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29),
 988         PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP),
 989         PINMUX_IPSR_DATA(IP6_5_4, QPOLA),
 990         PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30),
 991         PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE),
 992         PINMUX_IPSR_DATA(IP6_7_6, QPOLB),
 993         PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31),
 994         PINMUX_IPSR_DATA(IP6_8, VI0_CLK),
 995         PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK),
 996         PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0),
 997         PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV),
 998         PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1),
 999         PINMUX_IPSR_DATA(IP6_10, AVB_RXD0),
1000         PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2),
1001         PINMUX_IPSR_DATA(IP6_11, AVB_RXD1),
1002         PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3),
1003         PINMUX_IPSR_DATA(IP6_12, AVB_RXD2),
1004         PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4),
1005         PINMUX_IPSR_DATA(IP6_13, AVB_RXD3),
1006         PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5),
1007         PINMUX_IPSR_DATA(IP6_14, AVB_RXD4),
1008         PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6),
1009         PINMUX_IPSR_DATA(IP6_15, AVB_RXD5),
1010         PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
1011         PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
1012         PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
1013         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1014         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1015         PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2),
1016         PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
1017         PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
1018         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1019         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1020         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2),
1021         PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
1022         PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
1023         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1024         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1025         PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2),
1026         PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
1027         PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
1028         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1029         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1030         PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1031         PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
1032         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1033         PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
1034         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1035         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
1036         PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
1037         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0),
1038         PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0),
1039
1040         /* IPSR7 */
1041         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1042         PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
1043         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1044         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
1045         PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
1046         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1047         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0),
1048         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1049         PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
1050         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1051         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1052         PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
1053         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0),
1054         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0),
1055         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1056         PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
1057         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1058         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1059         PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
1060         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0),
1061         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1062         PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1063         PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
1064         PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1065         PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1066         PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
1067         PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0),
1068         PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0),
1069         PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
1070         PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1071         PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1072         PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
1073         PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0),
1074         PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1075         PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
1076         PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1077         PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
1078         PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1079         PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1080         PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
1081         PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1082         PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
1083         PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
1084         PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1085         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1086         PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
1087         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1088         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
1089         PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
1090         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1091         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1092         PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
1093         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1094         PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
1095         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1096         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1097         PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
1098         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1099         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1100         PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
1101         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1102         PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
1103         PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
1104
1105         /* IPSR8 */
1106         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0),
1107         PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
1108         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1109         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1110         PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
1111         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1112         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1113         PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
1114         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1115         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1116         PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
1117         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1118         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1119         PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
1120         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1121         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1122         PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
1123         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1124         PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
1125         PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
1126         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1127         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1128         PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
1129         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1130         PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
1131         PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
1132         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1133         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1134         PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
1135         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1136         PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1137         PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1138         PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
1139         PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1140         PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1141         PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1142         PINMUX_IPSR_DATA(IP8_19_17, PWM5),
1143         PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1),
1144         PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
1145         PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1146         PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
1147         PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1148         PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1149         PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
1150         PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0),
1151         PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
1152         PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1153         PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1154         PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1155         PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
1156         PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
1157         PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1158         PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1159         PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
1160         PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1161         PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1162         PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
1163         PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
1164         PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1165         PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1166         PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1167         PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
1168         PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1169         PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1170         PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
1171         PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1172         PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1173         PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2),
1174         PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0),
1175
1176         /* IPSR9 */
1177         PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD),
1178         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1179         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1180         PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3),
1181         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1182         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1183         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2),
1184         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0),
1185         PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK),
1186         PINMUX_IPSR_DATA(IP9_5_3, IRQ0),
1187         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1188         PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4),
1189         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1190         PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C),
1191         PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC),
1192         PINMUX_IPSR_DATA(IP9_8_6, PWM1),
1193         PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1194         PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5),
1195         PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1196         PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1197         PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1),
1198         PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1199         PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1200         PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6),
1201         PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0),
1202         PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1),
1203         PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1204         PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2),
1205         PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1206         PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1207         PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7),
1208         PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0),
1209         PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1),
1210         PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1211         PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1212         PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1213         PINMUX_IPSR_DATA(IP9_16_15, PWM6),
1214         PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0),
1215         PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1216         PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1217         PINMUX_IPSR_DATA(IP9_18_17, TPUTO1),
1218         PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1),
1219         PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK),
1220         PINMUX_IPSR_DATA(IP9_21_19, PWM2),
1221         PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0),
1222         PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2),
1223         PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1),
1224         PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1225         PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1),
1226         PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1227         PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1228         PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0),
1229         PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3),
1230         PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1231         PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1232         PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32),
1233         PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1234         PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1235         PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0),
1236         PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4),
1237         PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1238         PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0),
1239         PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33),
1240         PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1241         PINMUX_IPSR_DATA(IP9_30_28, PWM3),
1242         PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0),
1243         PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5),
1244         PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1245         PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK),
1246         PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34),
1247
1248         /* IPSR10 */
1249         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1250         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
1251         PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6),
1252         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1253         PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0),
1254         PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35),
1255         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1256         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
1257         PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7),
1258         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1259         PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1),
1260         PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36),
1261         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1262         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
1263         PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0),
1264         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1265         PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP),
1266         PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2),
1267         PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37),
1268         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1269         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
1270         PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1),
1271         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1272         PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1),
1273         PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3),
1274         PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38),
1275         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1276         PINMUX_IPSR_DATA(IP10_14_12, IRQ1),
1277         PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2),
1278         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1279         PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN),
1280         PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4),
1281         PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39),
1282         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1283         PINMUX_IPSR_DATA(IP10_17_15, IRQ2),
1284         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1285         PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3),
1286         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1287         PINMUX_IPSR_DATA(IP10_17_15, TANS2),
1288         PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5),
1289         PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT),
1290         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1291         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1292         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3),
1293         PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4),
1294         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1295         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1296         PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6),
1297         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1298         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1299         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1300         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3),
1301         PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5),
1302         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1303         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1304         PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7),
1305         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1306         PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1307         PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1308         PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6),
1309         PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1310         PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1311         PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8),
1312         PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1313         PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1314         PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7),
1315         PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1316         PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9),
1317         PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1318         PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1319         PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN),
1320         PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10),
1321
1322         /* IPSR11 */
1323         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1324         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1325         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1326         PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
1327         PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
1328         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1329         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1330         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1331         PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
1332         PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
1333         PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1334         PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1335         PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1336         PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
1337         PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1338         PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1339         PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1340         PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1341         PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
1342         PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1343         PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1344         PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1345         PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1346         PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
1347         PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1348         PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1349         PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
1350         PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
1351         PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1352         PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1353         PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
1354         PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
1355         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1356         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1357         PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
1358         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1359         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1360         PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
1361         PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
1362         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1363         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1364         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1365         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1),
1366         PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
1367         PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
1368         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1369         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1370         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1371         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1),
1372         PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
1373         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1374         PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
1375         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1),
1376         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1377
1378         /* IPSR12 */
1379         PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34),
1380         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1381         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1382         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1383         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1384         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1385         PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34),
1386         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1387         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1388         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1389         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1390         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1),
1391         PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3),
1392         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1393         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1394         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1395         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1396         PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N),
1397         PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1398         PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK),
1399         PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1),
1400         PINMUX_IPSR_DATA(IP12_10_9, IRD_TX),
1401         PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1402         PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG),
1403         PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1),
1404         PINMUX_IPSR_DATA(IP12_12_11, IRD_RX),
1405         PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1406         PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT),
1407         PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1),
1408         PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK),
1409         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1410         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1411         PINMUX_IPSR_DATA(IP12_17_15, PWM1_B),
1412         PINMUX_IPSR_DATA(IP12_17_15, IRQ9),
1413         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0),
1414         PINMUX_IPSR_DATA(IP12_17_15, DACK2),
1415         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1416         PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1417         PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1418         PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
1419         PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK),
1420         PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1421         PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1422         PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1423         PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1424         PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1425         PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
1426         PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0),
1427         PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1428         PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1429         PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1430         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1431         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1432         PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1),
1433         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0),
1434         PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N),
1435         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1436         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1437         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1438         PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2),
1439         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0),
1440         PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N),
1441         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1442
1443         /* IPSR13 */
1444         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1445         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1446         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1447         PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3),
1448         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0),
1449         PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N),
1450         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1451         PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1452         PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1453         PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1454         PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4),
1455         PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0),
1456         PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N),
1457         PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1458         PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1459         PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1460         PINMUX_IPSR_DATA(IP13_8_6, PWM2_B),
1461         PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5),
1462         PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0),
1463         PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1),
1464         PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1465         PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1466         PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1467         PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1468         PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6),
1469         PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N),
1470         PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1471         PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1472         PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1473         PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1474         PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7),
1475         PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N),
1476         PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1477         PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1478         PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1479         PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1480         PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB),
1481         PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1482         PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1483         PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1484         PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1485         PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1486         PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1487         PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD),
1488         PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1489         PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1490         PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1491         PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1492         PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1493         PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1494         PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1495         PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N),
1496         PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1497         PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1498         PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4),
1499         PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1500         PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1501         PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1502         PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1503         PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N),
1504         PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1505         PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1506         PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4),
1507         PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1508 };
1509
1510 static const struct sh_pfc_pin pinmux_pins[] = {
1511         PINMUX_GPIO_GP_ALL(),
1512 };
1513
1514 /* - ETH -------------------------------------------------------------------- */
1515 static const unsigned int eth_link_pins[] = {
1516         /* LINK */
1517         RCAR_GP_PIN(3, 18),
1518 };
1519 static const unsigned int eth_link_mux[] = {
1520         ETH_LINK_MARK,
1521 };
1522 static const unsigned int eth_magic_pins[] = {
1523         /* MAGIC */
1524         RCAR_GP_PIN(3, 22),
1525 };
1526 static const unsigned int eth_magic_mux[] = {
1527         ETH_MAGIC_MARK,
1528 };
1529 static const unsigned int eth_mdio_pins[] = {
1530         /* MDC, MDIO */
1531         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1532 };
1533 static const unsigned int eth_mdio_mux[] = {
1534         ETH_MDC_MARK, ETH_MDIO_MARK,
1535 };
1536 static const unsigned int eth_rmii_pins[] = {
1537         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1538         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1539         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1540         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1541 };
1542 static const unsigned int eth_rmii_mux[] = {
1543         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1544         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1545 };
1546 static const unsigned int eth_link_b_pins[] = {
1547         /* LINK */
1548         RCAR_GP_PIN(5, 15),
1549 };
1550 static const unsigned int eth_link_b_mux[] = {
1551         ETH_LINK_B_MARK,
1552 };
1553 static const unsigned int eth_magic_b_pins[] = {
1554         /* MAGIC */
1555         RCAR_GP_PIN(5, 19),
1556 };
1557 static const unsigned int eth_magic_b_mux[] = {
1558         ETH_MAGIC_B_MARK,
1559 };
1560 static const unsigned int eth_mdio_b_pins[] = {
1561         /* MDC, MDIO */
1562         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1563 };
1564 static const unsigned int eth_mdio_b_mux[] = {
1565         ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1566 };
1567 static const unsigned int eth_rmii_b_pins[] = {
1568         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1569         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1570         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1571         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1572 };
1573 static const unsigned int eth_rmii_b_mux[] = {
1574         ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1575         ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1576 };
1577 /* - HSCIF0 ----------------------------------------------------------------- */
1578 static const unsigned int hscif0_data_pins[] = {
1579         /* RX, TX */
1580         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1581 };
1582 static const unsigned int hscif0_data_mux[] = {
1583         HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1584 };
1585 static const unsigned int hscif0_clk_pins[] = {
1586         /* SCK */
1587         RCAR_GP_PIN(3, 29),
1588 };
1589 static const unsigned int hscif0_clk_mux[] = {
1590         HSCIF0_HSCK_MARK,
1591 };
1592 static const unsigned int hscif0_ctrl_pins[] = {
1593         /* RTS, CTS */
1594         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1595 };
1596 static const unsigned int hscif0_ctrl_mux[] = {
1597         HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1598 };
1599 static const unsigned int hscif0_data_b_pins[] = {
1600         /* RX, TX */
1601         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1602 };
1603 static const unsigned int hscif0_data_b_mux[] = {
1604         HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1605 };
1606 static const unsigned int hscif0_clk_b_pins[] = {
1607         /* SCK */
1608         RCAR_GP_PIN(1, 0),
1609 };
1610 static const unsigned int hscif0_clk_b_mux[] = {
1611         HSCIF0_HSCK_B_MARK,
1612 };
1613 /* - HSCIF1 ----------------------------------------------------------------- */
1614 static const unsigned int hscif1_data_pins[] = {
1615         /* RX, TX */
1616         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1617 };
1618 static const unsigned int hscif1_data_mux[] = {
1619         HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1620 };
1621 static const unsigned int hscif1_clk_pins[] = {
1622         /* SCK */
1623         RCAR_GP_PIN(4, 10),
1624 };
1625 static const unsigned int hscif1_clk_mux[] = {
1626         HSCIF1_HSCK_MARK,
1627 };
1628 static const unsigned int hscif1_ctrl_pins[] = {
1629         /* RTS, CTS */
1630         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
1631 };
1632 static const unsigned int hscif1_ctrl_mux[] = {
1633         HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
1634 };
1635 static const unsigned int hscif1_data_b_pins[] = {
1636         /* RX, TX */
1637         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1638 };
1639 static const unsigned int hscif1_data_b_mux[] = {
1640         HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
1641 };
1642 static const unsigned int hscif1_ctrl_b_pins[] = {
1643         /* RTS, CTS */
1644         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1645 };
1646 static const unsigned int hscif1_ctrl_b_mux[] = {
1647         HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
1648 };
1649 /* - HSCIF2 ----------------------------------------------------------------- */
1650 static const unsigned int hscif2_data_pins[] = {
1651         /* RX, TX */
1652         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1653 };
1654 static const unsigned int hscif2_data_mux[] = {
1655         HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
1656 };
1657 static const unsigned int hscif2_clk_pins[] = {
1658         /* SCK */
1659         RCAR_GP_PIN(0, 10),
1660 };
1661 static const unsigned int hscif2_clk_mux[] = {
1662         HSCIF2_HSCK_MARK,
1663 };
1664 static const unsigned int hscif2_ctrl_pins[] = {
1665         /* RTS, CTS */
1666         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
1667 };
1668 static const unsigned int hscif2_ctrl_mux[] = {
1669         HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
1670 };
1671 /* - I2C0 ------------------------------------------------------------------- */
1672 static const unsigned int i2c0_pins[] = {
1673         /* SCL, SDA */
1674         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
1675 };
1676 static const unsigned int i2c0_mux[] = {
1677         I2C0_SCL_MARK, I2C0_SDA_MARK,
1678 };
1679 static const unsigned int i2c0_b_pins[] = {
1680         /* SCL, SDA */
1681         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1682 };
1683 static const unsigned int i2c0_b_mux[] = {
1684         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
1685 };
1686 static const unsigned int i2c0_c_pins[] = {
1687         /* SCL, SDA */
1688         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1689 };
1690 static const unsigned int i2c0_c_mux[] = {
1691         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
1692 };
1693 static const unsigned int i2c0_d_pins[] = {
1694         /* SCL, SDA */
1695         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1696 };
1697 static const unsigned int i2c0_d_mux[] = {
1698         I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
1699 };
1700 static const unsigned int i2c0_e_pins[] = {
1701         /* SCL, SDA */
1702         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1703 };
1704 static const unsigned int i2c0_e_mux[] = {
1705         I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
1706 };
1707 /* - I2C1 ------------------------------------------------------------------- */
1708 static const unsigned int i2c1_pins[] = {
1709         /* SCL, SDA */
1710         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1711 };
1712 static const unsigned int i2c1_mux[] = {
1713         I2C1_SCL_MARK, I2C1_SDA_MARK,
1714 };
1715 static const unsigned int i2c1_b_pins[] = {
1716         /* SCL, SDA */
1717         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1718 };
1719 static const unsigned int i2c1_b_mux[] = {
1720         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
1721 };
1722 static const unsigned int i2c1_c_pins[] = {
1723         /* SCL, SDA */
1724         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1725 };
1726 static const unsigned int i2c1_c_mux[] = {
1727         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
1728 };
1729 static const unsigned int i2c1_d_pins[] = {
1730         /* SCL, SDA */
1731         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
1732 };
1733 static const unsigned int i2c1_d_mux[] = {
1734         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
1735 };
1736 static const unsigned int i2c1_e_pins[] = {
1737         /* SCL, SDA */
1738         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1739 };
1740 static const unsigned int i2c1_e_mux[] = {
1741         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
1742 };
1743 /* - I2C2 ------------------------------------------------------------------- */
1744 static const unsigned int i2c2_pins[] = {
1745         /* SCL, SDA */
1746         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1747 };
1748 static const unsigned int i2c2_mux[] = {
1749         I2C2_SCL_MARK, I2C2_SDA_MARK,
1750 };
1751 static const unsigned int i2c2_b_pins[] = {
1752         /* SCL, SDA */
1753         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1754 };
1755 static const unsigned int i2c2_b_mux[] = {
1756         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
1757 };
1758 static const unsigned int i2c2_c_pins[] = {
1759         /* SCL, SDA */
1760         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1761 };
1762 static const unsigned int i2c2_c_mux[] = {
1763         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
1764 };
1765 static const unsigned int i2c2_d_pins[] = {
1766         /* SCL, SDA */
1767         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1768 };
1769 static const unsigned int i2c2_d_mux[] = {
1770         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
1771 };
1772 static const unsigned int i2c2_e_pins[] = {
1773         /* SCL, SDA */
1774         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1775 };
1776 static const unsigned int i2c2_e_mux[] = {
1777         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
1778 };
1779 /* - I2C3 ------------------------------------------------------------------- */
1780 static const unsigned int i2c3_pins[] = {
1781         /* SCL, SDA */
1782         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1783 };
1784 static const unsigned int i2c3_mux[] = {
1785         I2C3_SCL_MARK, I2C3_SDA_MARK,
1786 };
1787 static const unsigned int i2c3_b_pins[] = {
1788         /* SCL, SDA */
1789         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
1790 };
1791 static const unsigned int i2c3_b_mux[] = {
1792         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
1793 };
1794 static const unsigned int i2c3_c_pins[] = {
1795         /* SCL, SDA */
1796         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1797 };
1798 static const unsigned int i2c3_c_mux[] = {
1799         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
1800 };
1801 static const unsigned int i2c3_d_pins[] = {
1802         /* SCL, SDA */
1803         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1804 };
1805 static const unsigned int i2c3_d_mux[] = {
1806         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
1807 };
1808 static const unsigned int i2c3_e_pins[] = {
1809         /* SCL, SDA */
1810         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
1811 };
1812 static const unsigned int i2c3_e_mux[] = {
1813         I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
1814 };
1815 /* - I2C4 ------------------------------------------------------------------- */
1816 static const unsigned int i2c4_pins[] = {
1817         /* SCL, SDA */
1818         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1819 };
1820 static const unsigned int i2c4_mux[] = {
1821         I2C4_SCL_MARK, I2C4_SDA_MARK,
1822 };
1823 static const unsigned int i2c4_b_pins[] = {
1824         /* SCL, SDA */
1825         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1826 };
1827 static const unsigned int i2c4_b_mux[] = {
1828         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
1829 };
1830 static const unsigned int i2c4_c_pins[] = {
1831         /* SCL, SDA */
1832         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1833 };
1834 static const unsigned int i2c4_c_mux[] = {
1835         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
1836 };
1837 static const unsigned int i2c4_d_pins[] = {
1838         /* SCL, SDA */
1839         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1840 };
1841 static const unsigned int i2c4_d_mux[] = {
1842         I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
1843 };
1844 static const unsigned int i2c4_e_pins[] = {
1845         /* SCL, SDA */
1846         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
1847 };
1848 static const unsigned int i2c4_e_mux[] = {
1849         I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
1850 };
1851 /* - INTC ------------------------------------------------------------------- */
1852 static const unsigned int intc_irq0_pins[] = {
1853         /* IRQ0 */
1854         RCAR_GP_PIN(4, 4),
1855 };
1856 static const unsigned int intc_irq0_mux[] = {
1857         IRQ0_MARK,
1858 };
1859 static const unsigned int intc_irq1_pins[] = {
1860         /* IRQ1 */
1861         RCAR_GP_PIN(4, 18),
1862 };
1863 static const unsigned int intc_irq1_mux[] = {
1864         IRQ1_MARK,
1865 };
1866 static const unsigned int intc_irq2_pins[] = {
1867         /* IRQ2 */
1868         RCAR_GP_PIN(4, 19),
1869 };
1870 static const unsigned int intc_irq2_mux[] = {
1871         IRQ2_MARK,
1872 };
1873 static const unsigned int intc_irq3_pins[] = {
1874         /* IRQ3 */
1875         RCAR_GP_PIN(0, 7),
1876 };
1877 static const unsigned int intc_irq3_mux[] = {
1878         IRQ3_MARK,
1879 };
1880 static const unsigned int intc_irq4_pins[] = {
1881         /* IRQ4 */
1882         RCAR_GP_PIN(0, 0),
1883 };
1884 static const unsigned int intc_irq4_mux[] = {
1885         IRQ4_MARK,
1886 };
1887 static const unsigned int intc_irq5_pins[] = {
1888         /* IRQ5 */
1889         RCAR_GP_PIN(4, 1),
1890 };
1891 static const unsigned int intc_irq5_mux[] = {
1892         IRQ5_MARK,
1893 };
1894 static const unsigned int intc_irq6_pins[] = {
1895         /* IRQ6 */
1896         RCAR_GP_PIN(0, 10),
1897 };
1898 static const unsigned int intc_irq6_mux[] = {
1899         IRQ6_MARK,
1900 };
1901 static const unsigned int intc_irq7_pins[] = {
1902         /* IRQ7 */
1903         RCAR_GP_PIN(6, 15),
1904 };
1905 static const unsigned int intc_irq7_mux[] = {
1906         IRQ7_MARK,
1907 };
1908 static const unsigned int intc_irq8_pins[] = {
1909         /* IRQ8 */
1910         RCAR_GP_PIN(5, 0),
1911 };
1912 static const unsigned int intc_irq8_mux[] = {
1913         IRQ8_MARK,
1914 };
1915 static const unsigned int intc_irq9_pins[] = {
1916         /* IRQ9 */
1917         RCAR_GP_PIN(5, 10),
1918 };
1919 static const unsigned int intc_irq9_mux[] = {
1920         IRQ9_MARK,
1921 };
1922 /* - MMCIF ------------------------------------------------------------------ */
1923 static const unsigned int mmc_data1_pins[] = {
1924         /* D[0] */
1925         RCAR_GP_PIN(6, 18),
1926 };
1927 static const unsigned int mmc_data1_mux[] = {
1928         MMC_D0_MARK,
1929 };
1930 static const unsigned int mmc_data4_pins[] = {
1931         /* D[0:3] */
1932         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1933         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1934 };
1935 static const unsigned int mmc_data4_mux[] = {
1936         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1937 };
1938 static const unsigned int mmc_data8_pins[] = {
1939         /* D[0:7] */
1940         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1941         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1942         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1943         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1944 };
1945 static const unsigned int mmc_data8_mux[] = {
1946         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1947         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
1948 };
1949 static const unsigned int mmc_ctrl_pins[] = {
1950         /* CLK, CMD */
1951         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
1952 };
1953 static const unsigned int mmc_ctrl_mux[] = {
1954         MMC_CLK_MARK, MMC_CMD_MARK,
1955 };
1956 /* - MSIOF0 ----------------------------------------------------------------- */
1957 static const unsigned int msiof0_clk_pins[] = {
1958         /* SCK */
1959         RCAR_GP_PIN(4, 4),
1960 };
1961 static const unsigned int msiof0_clk_mux[] = {
1962         MSIOF0_SCK_MARK,
1963 };
1964 static const unsigned int msiof0_sync_pins[] = {
1965         /* SYNC */
1966         RCAR_GP_PIN(4, 5),
1967 };
1968 static const unsigned int msiof0_sync_mux[] = {
1969         MSIOF0_SYNC_MARK,
1970 };
1971 static const unsigned int msiof0_ss1_pins[] = {
1972         /* SS1 */
1973         RCAR_GP_PIN(4, 6),
1974 };
1975 static const unsigned int msiof0_ss1_mux[] = {
1976         MSIOF0_SS1_MARK,
1977 };
1978 static const unsigned int msiof0_ss2_pins[] = {
1979         /* SS2 */
1980         RCAR_GP_PIN(4, 7),
1981 };
1982 static const unsigned int msiof0_ss2_mux[] = {
1983         MSIOF0_SS2_MARK,
1984 };
1985 static const unsigned int msiof0_rx_pins[] = {
1986         /* RXD */
1987         RCAR_GP_PIN(4, 2),
1988 };
1989 static const unsigned int msiof0_rx_mux[] = {
1990         MSIOF0_RXD_MARK,
1991 };
1992 static const unsigned int msiof0_tx_pins[] = {
1993         /* TXD */
1994         RCAR_GP_PIN(4, 3),
1995 };
1996 static const unsigned int msiof0_tx_mux[] = {
1997         MSIOF0_TXD_MARK,
1998 };
1999 /* - MSIOF1 ----------------------------------------------------------------- */
2000 static const unsigned int msiof1_clk_pins[] = {
2001         /* SCK */
2002         RCAR_GP_PIN(0, 26),
2003 };
2004 static const unsigned int msiof1_clk_mux[] = {
2005         MSIOF1_SCK_MARK,
2006 };
2007 static const unsigned int msiof1_sync_pins[] = {
2008         /* SYNC */
2009         RCAR_GP_PIN(0, 27),
2010 };
2011 static const unsigned int msiof1_sync_mux[] = {
2012         MSIOF1_SYNC_MARK,
2013 };
2014 static const unsigned int msiof1_ss1_pins[] = {
2015         /* SS1 */
2016         RCAR_GP_PIN(0, 28),
2017 };
2018 static const unsigned int msiof1_ss1_mux[] = {
2019         MSIOF1_SS1_MARK,
2020 };
2021 static const unsigned int msiof1_ss2_pins[] = {
2022         /* SS2 */
2023         RCAR_GP_PIN(0, 29),
2024 };
2025 static const unsigned int msiof1_ss2_mux[] = {
2026         MSIOF1_SS2_MARK,
2027 };
2028 static const unsigned int msiof1_rx_pins[] = {
2029         /* RXD */
2030         RCAR_GP_PIN(0, 24),
2031 };
2032 static const unsigned int msiof1_rx_mux[] = {
2033         MSIOF1_RXD_MARK,
2034 };
2035 static const unsigned int msiof1_tx_pins[] = {
2036         /* TXD */
2037         RCAR_GP_PIN(0, 25),
2038 };
2039 static const unsigned int msiof1_tx_mux[] = {
2040         MSIOF1_TXD_MARK,
2041 };
2042 static const unsigned int msiof1_clk_b_pins[] = {
2043         /* SCK */
2044         RCAR_GP_PIN(5, 3),
2045 };
2046 static const unsigned int msiof1_clk_b_mux[] = {
2047         MSIOF1_SCK_B_MARK,
2048 };
2049 static const unsigned int msiof1_sync_b_pins[] = {
2050         /* SYNC */
2051         RCAR_GP_PIN(5, 4),
2052 };
2053 static const unsigned int msiof1_sync_b_mux[] = {
2054         MSIOF1_SYNC_B_MARK,
2055 };
2056 static const unsigned int msiof1_ss1_b_pins[] = {
2057         /* SS1 */
2058         RCAR_GP_PIN(5, 5),
2059 };
2060 static const unsigned int msiof1_ss1_b_mux[] = {
2061         MSIOF1_SS1_B_MARK,
2062 };
2063 static const unsigned int msiof1_ss2_b_pins[] = {
2064         /* SS2 */
2065         RCAR_GP_PIN(5, 6),
2066 };
2067 static const unsigned int msiof1_ss2_b_mux[] = {
2068         MSIOF1_SS2_B_MARK,
2069 };
2070 static const unsigned int msiof1_rx_b_pins[] = {
2071         /* RXD */
2072         RCAR_GP_PIN(5, 1),
2073 };
2074 static const unsigned int msiof1_rx_b_mux[] = {
2075         MSIOF1_RXD_B_MARK,
2076 };
2077 static const unsigned int msiof1_tx_b_pins[] = {
2078         /* TXD */
2079         RCAR_GP_PIN(5, 2),
2080 };
2081 static const unsigned int msiof1_tx_b_mux[] = {
2082         MSIOF1_TXD_B_MARK,
2083 };
2084 /* - MSIOF2 ----------------------------------------------------------------- */
2085 static const unsigned int msiof2_clk_pins[] = {
2086         /* SCK */
2087         RCAR_GP_PIN(1, 0),
2088 };
2089 static const unsigned int msiof2_clk_mux[] = {
2090         MSIOF2_SCK_MARK,
2091 };
2092 static const unsigned int msiof2_sync_pins[] = {
2093         /* SYNC */
2094         RCAR_GP_PIN(1, 1),
2095 };
2096 static const unsigned int msiof2_sync_mux[] = {
2097         MSIOF2_SYNC_MARK,
2098 };
2099 static const unsigned int msiof2_ss1_pins[] = {
2100         /* SS1 */
2101         RCAR_GP_PIN(1, 2),
2102 };
2103 static const unsigned int msiof2_ss1_mux[] = {
2104         MSIOF2_SS1_MARK,
2105 };
2106 static const unsigned int msiof2_ss2_pins[] = {
2107         /* SS2 */
2108         RCAR_GP_PIN(1, 3),
2109 };
2110 static const unsigned int msiof2_ss2_mux[] = {
2111         MSIOF2_SS2_MARK,
2112 };
2113 static const unsigned int msiof2_rx_pins[] = {
2114         /* RXD */
2115         RCAR_GP_PIN(0, 30),
2116 };
2117 static const unsigned int msiof2_rx_mux[] = {
2118         MSIOF2_RXD_MARK,
2119 };
2120 static const unsigned int msiof2_tx_pins[] = {
2121         /* TXD */
2122         RCAR_GP_PIN(0, 31),
2123 };
2124 static const unsigned int msiof2_tx_mux[] = {
2125         MSIOF2_TXD_MARK,
2126 };
2127 static const unsigned int msiof2_clk_b_pins[] = {
2128         /* SCK */
2129         RCAR_GP_PIN(3, 15),
2130 };
2131 static const unsigned int msiof2_clk_b_mux[] = {
2132         MSIOF2_SCK_B_MARK,
2133 };
2134 static const unsigned int msiof2_sync_b_pins[] = {
2135         /* SYNC */
2136         RCAR_GP_PIN(3, 16),
2137 };
2138 static const unsigned int msiof2_sync_b_mux[] = {
2139         MSIOF2_SYNC_B_MARK,
2140 };
2141 static const unsigned int msiof2_ss1_b_pins[] = {
2142         /* SS1 */
2143         RCAR_GP_PIN(3, 17),
2144 };
2145 static const unsigned int msiof2_ss1_b_mux[] = {
2146         MSIOF2_SS1_B_MARK,
2147 };
2148 static const unsigned int msiof2_ss2_b_pins[] = {
2149         /* SS2 */
2150         RCAR_GP_PIN(3, 18),
2151 };
2152 static const unsigned int msiof2_ss2_b_mux[] = {
2153         MSIOF2_SS2_B_MARK,
2154 };
2155 static const unsigned int msiof2_rx_b_pins[] = {
2156         /* RXD */
2157         RCAR_GP_PIN(3, 13),
2158 };
2159 static const unsigned int msiof2_rx_b_mux[] = {
2160         MSIOF2_RXD_B_MARK,
2161 };
2162 static const unsigned int msiof2_tx_b_pins[] = {
2163         /* TXD */
2164         RCAR_GP_PIN(3, 14),
2165 };
2166 static const unsigned int msiof2_tx_b_mux[] = {
2167         MSIOF2_TXD_B_MARK,
2168 };
2169 /* - QSPI ------------------------------------------------------------------- */
2170 static const unsigned int qspi_ctrl_pins[] = {
2171         /* SPCLK, SSL */
2172         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2173 };
2174 static const unsigned int qspi_ctrl_mux[] = {
2175         SPCLK_MARK, SSL_MARK,
2176 };
2177 static const unsigned int qspi_data2_pins[] = {
2178         /* MOSI_IO0, MISO_IO1 */
2179         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2180 };
2181 static const unsigned int qspi_data2_mux[] = {
2182         MOSI_IO0_MARK, MISO_IO1_MARK,
2183 };
2184 static const unsigned int qspi_data4_pins[] = {
2185         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2186         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2187         RCAR_GP_PIN(1, 8),
2188 };
2189 static const unsigned int qspi_data4_mux[] = {
2190         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2191 };
2192 /* - SCIF0 ------------------------------------------------------------------ */
2193 static const unsigned int scif0_data_pins[] = {
2194         /* RX, TX */
2195         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2196 };
2197 static const unsigned int scif0_data_mux[] = {
2198         SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2199 };
2200 static const unsigned int scif0_clk_pins[] = {
2201         /* SCK */
2202         RCAR_GP_PIN(1, 23),
2203 };
2204 static const unsigned int scif0_clk_mux[] = {
2205         SCIF_CLK_MARK,
2206 };
2207 static const unsigned int scif0_data_b_pins[] = {
2208         /* RX, TX */
2209         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2210 };
2211 static const unsigned int scif0_data_b_mux[] = {
2212         SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2213 };
2214 static const unsigned int scif0_clk_b_pins[] = {
2215         /* SCK */
2216         RCAR_GP_PIN(3, 29),
2217 };
2218 static const unsigned int scif0_clk_b_mux[] = {
2219         SCIF_CLK_B_MARK,
2220 };
2221 static const unsigned int scif0_data_c_pins[] = {
2222         /* RX, TX */
2223         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2224 };
2225 static const unsigned int scif0_data_c_mux[] = {
2226         SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2227 };
2228 static const unsigned int scif0_data_d_pins[] = {
2229         /* RX, TX */
2230         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2231 };
2232 static const unsigned int scif0_data_d_mux[] = {
2233         SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2234 };
2235 /* - SCIF1 ------------------------------------------------------------------ */
2236 static const unsigned int scif1_data_pins[] = {
2237         /* RX, TX */
2238         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2239 };
2240 static const unsigned int scif1_data_mux[] = {
2241         SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2242 };
2243 static const unsigned int scif1_clk_pins[] = {
2244         /* SCK */
2245         RCAR_GP_PIN(4, 13),
2246 };
2247 static const unsigned int scif1_clk_mux[] = {
2248         SCIF1_SCK_MARK,
2249 };
2250 static const unsigned int scif1_data_b_pins[] = {
2251         /* RX, TX */
2252         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2253 };
2254 static const unsigned int scif1_data_b_mux[] = {
2255         SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2256 };
2257 static const unsigned int scif1_clk_b_pins[] = {
2258         /* SCK */
2259         RCAR_GP_PIN(5, 10),
2260 };
2261 static const unsigned int scif1_clk_b_mux[] = {
2262         SCIF1_SCK_B_MARK,
2263 };
2264 static const unsigned int scif1_data_c_pins[] = {
2265         /* RX, TX */
2266         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2267 };
2268 static const unsigned int scif1_data_c_mux[] = {
2269         SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2270 };
2271 static const unsigned int scif1_clk_c_pins[] = {
2272         /* SCK */
2273         RCAR_GP_PIN(0, 10),
2274 };
2275 static const unsigned int scif1_clk_c_mux[] = {
2276         SCIF1_SCK_C_MARK,
2277 };
2278 /* - SCIF2 ------------------------------------------------------------------ */
2279 static const unsigned int scif2_data_pins[] = {
2280         /* RX, TX */
2281         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2282 };
2283 static const unsigned int scif2_data_mux[] = {
2284         SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2285 };
2286 static const unsigned int scif2_clk_pins[] = {
2287         /* SCK */
2288         RCAR_GP_PIN(4, 18),
2289 };
2290 static const unsigned int scif2_clk_mux[] = {
2291         SCIF2_SCK_MARK,
2292 };
2293 static const unsigned int scif2_data_b_pins[] = {
2294         /* RX, TX */
2295         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2296 };
2297 static const unsigned int scif2_data_b_mux[] = {
2298         SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2299 };
2300 static const unsigned int scif2_clk_b_pins[] = {
2301         /* SCK */
2302         RCAR_GP_PIN(5, 17),
2303 };
2304 static const unsigned int scif2_clk_b_mux[] = {
2305         SCIF2_SCK_B_MARK,
2306 };
2307 static const unsigned int scif2_data_c_pins[] = {
2308         /* RX, TX */
2309         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2310 };
2311 static const unsigned int scif2_data_c_mux[] = {
2312         SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2313 };
2314 static const unsigned int scif2_clk_c_pins[] = {
2315         /* SCK */
2316         RCAR_GP_PIN(3, 19),
2317 };
2318 static const unsigned int scif2_clk_c_mux[] = {
2319         SCIF2_SCK_C_MARK,
2320 };
2321 /* - SCIF3 ------------------------------------------------------------------ */
2322 static const unsigned int scif3_data_pins[] = {
2323         /* RX, TX */
2324         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2325 };
2326 static const unsigned int scif3_data_mux[] = {
2327         SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2328 };
2329 static const unsigned int scif3_clk_pins[] = {
2330         /* SCK */
2331         RCAR_GP_PIN(4, 19),
2332 };
2333 static const unsigned int scif3_clk_mux[] = {
2334         SCIF3_SCK_MARK,
2335 };
2336 static const unsigned int scif3_data_b_pins[] = {
2337         /* RX, TX */
2338         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2339 };
2340 static const unsigned int scif3_data_b_mux[] = {
2341         SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2342 };
2343 static const unsigned int scif3_clk_b_pins[] = {
2344         /* SCK */
2345         RCAR_GP_PIN(3, 22),
2346 };
2347 static const unsigned int scif3_clk_b_mux[] = {
2348         SCIF3_SCK_B_MARK,
2349 };
2350 /* - SCIF4 ------------------------------------------------------------------ */
2351 static const unsigned int scif4_data_pins[] = {
2352         /* RX, TX */
2353         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2354 };
2355 static const unsigned int scif4_data_mux[] = {
2356         SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2357 };
2358 static const unsigned int scif4_data_b_pins[] = {
2359         /* RX, TX */
2360         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2361 };
2362 static const unsigned int scif4_data_b_mux[] = {
2363         SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2364 };
2365 static const unsigned int scif4_data_c_pins[] = {
2366         /* RX, TX */
2367         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2368 };
2369 static const unsigned int scif4_data_c_mux[] = {
2370         SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2371 };
2372 static const unsigned int scif4_data_d_pins[] = {
2373         /* RX, TX */
2374         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2375 };
2376 static const unsigned int scif4_data_d_mux[] = {
2377         SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2378 };
2379 static const unsigned int scif4_data_e_pins[] = {
2380         /* RX, TX */
2381         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2382 };
2383 static const unsigned int scif4_data_e_mux[] = {
2384         SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2385 };
2386 /* - SCIF5 ------------------------------------------------------------------ */
2387 static const unsigned int scif5_data_pins[] = {
2388         /* RX, TX */
2389         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2390 };
2391 static const unsigned int scif5_data_mux[] = {
2392         SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2393 };
2394 static const unsigned int scif5_data_b_pins[] = {
2395         /* RX, TX */
2396         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2397 };
2398 static const unsigned int scif5_data_b_mux[] = {
2399         SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2400 };
2401 static const unsigned int scif5_data_c_pins[] = {
2402         /* RX, TX */
2403         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2404 };
2405 static const unsigned int scif5_data_c_mux[] = {
2406         SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2407 };
2408 static const unsigned int scif5_data_d_pins[] = {
2409         /* RX, TX */
2410         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2411 };
2412 static const unsigned int scif5_data_d_mux[] = {
2413         SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2414 };
2415 /* - SCIFA0 ----------------------------------------------------------------- */
2416 static const unsigned int scifa0_data_pins[] = {
2417         /* RXD, TXD */
2418         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2419 };
2420 static const unsigned int scifa0_data_mux[] = {
2421         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2422 };
2423 static const unsigned int scifa0_data_b_pins[] = {
2424         /* RXD, TXD */
2425         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2426 };
2427 static const unsigned int scifa0_data_b_mux[] = {
2428         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2429 };
2430 static const unsigned int scifa0_data_c_pins[] = {
2431         /* RXD, TXD */
2432         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2433 };
2434 static const unsigned int scifa0_data_c_mux[] = {
2435         SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2436 };
2437 static const unsigned int scifa0_data_d_pins[] = {
2438         /* RXD, TXD */
2439         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2440 };
2441 static const unsigned int scifa0_data_d_mux[] = {
2442         SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2443 };
2444 /* - SCIFA1 ----------------------------------------------------------------- */
2445 static const unsigned int scifa1_data_pins[] = {
2446         /* RXD, TXD */
2447         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2448 };
2449 static const unsigned int scifa1_data_mux[] = {
2450         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2451 };
2452 static const unsigned int scifa1_clk_pins[] = {
2453         /* SCK */
2454         RCAR_GP_PIN(0, 13),
2455 };
2456 static const unsigned int scifa1_clk_mux[] = {
2457         SCIFA1_SCK_MARK,
2458 };
2459 static const unsigned int scifa1_data_b_pins[] = {
2460         /* RXD, TXD */
2461         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2462 };
2463 static const unsigned int scifa1_data_b_mux[] = {
2464         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2465 };
2466 static const unsigned int scifa1_clk_b_pins[] = {
2467         /* SCK */
2468         RCAR_GP_PIN(4, 27),
2469 };
2470 static const unsigned int scifa1_clk_b_mux[] = {
2471         SCIFA1_SCK_B_MARK,
2472 };
2473 static const unsigned int scifa1_data_c_pins[] = {
2474         /* RXD, TXD */
2475         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2476 };
2477 static const unsigned int scifa1_data_c_mux[] = {
2478         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2479 };
2480 static const unsigned int scifa1_clk_c_pins[] = {
2481         /* SCK */
2482         RCAR_GP_PIN(5, 4),
2483 };
2484 static const unsigned int scifa1_clk_c_mux[] = {
2485         SCIFA1_SCK_C_MARK,
2486 };
2487 /* - SCIFA2 ----------------------------------------------------------------- */
2488 static const unsigned int scifa2_data_pins[] = {
2489         /* RXD, TXD */
2490         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2491 };
2492 static const unsigned int scifa2_data_mux[] = {
2493         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2494 };
2495 static const unsigned int scifa2_clk_pins[] = {
2496         /* SCK */
2497         RCAR_GP_PIN(1, 15),
2498 };
2499 static const unsigned int scifa2_clk_mux[] = {
2500         SCIFA2_SCK_MARK,
2501 };
2502 static const unsigned int scifa2_data_b_pins[] = {
2503         /* RXD, TXD */
2504         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
2505 };
2506 static const unsigned int scifa2_data_b_mux[] = {
2507         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2508 };
2509 static const unsigned int scifa2_clk_b_pins[] = {
2510         /* SCK */
2511         RCAR_GP_PIN(4, 30),
2512 };
2513 static const unsigned int scifa2_clk_b_mux[] = {
2514         SCIFA2_SCK_B_MARK,
2515 };
2516 /* - SCIFA3 ----------------------------------------------------------------- */
2517 static const unsigned int scifa3_data_pins[] = {
2518         /* RXD, TXD */
2519         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2520 };
2521 static const unsigned int scifa3_data_mux[] = {
2522         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2523 };
2524 static const unsigned int scifa3_clk_pins[] = {
2525         /* SCK */
2526         RCAR_GP_PIN(4, 24),
2527 };
2528 static const unsigned int scifa3_clk_mux[] = {
2529         SCIFA3_SCK_MARK,
2530 };
2531 static const unsigned int scifa3_data_b_pins[] = {
2532         /* RXD, TXD */
2533         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2534 };
2535 static const unsigned int scifa3_data_b_mux[] = {
2536         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2537 };
2538 static const unsigned int scifa3_clk_b_pins[] = {
2539         /* SCK */
2540         RCAR_GP_PIN(0, 0),
2541 };
2542 static const unsigned int scifa3_clk_b_mux[] = {
2543         SCIFA3_SCK_B_MARK,
2544 };
2545 /* - SCIFA4 ----------------------------------------------------------------- */
2546 static const unsigned int scifa4_data_pins[] = {
2547         /* RXD, TXD */
2548         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
2549 };
2550 static const unsigned int scifa4_data_mux[] = {
2551         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2552 };
2553 static const unsigned int scifa4_data_b_pins[] = {
2554         /* RXD, TXD */
2555         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
2556 };
2557 static const unsigned int scifa4_data_b_mux[] = {
2558         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2559 };
2560 static const unsigned int scifa4_data_c_pins[] = {
2561         /* RXD, TXD */
2562         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2563 };
2564 static const unsigned int scifa4_data_c_mux[] = {
2565         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2566 };
2567 static const unsigned int scifa4_data_d_pins[] = {
2568         /* RXD, TXD */
2569         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2570 };
2571 static const unsigned int scifa4_data_d_mux[] = {
2572         SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
2573 };
2574 /* - SCIFA5 ----------------------------------------------------------------- */
2575 static const unsigned int scifa5_data_pins[] = {
2576         /* RXD, TXD */
2577         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2578 };
2579 static const unsigned int scifa5_data_mux[] = {
2580         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2581 };
2582 static const unsigned int scifa5_data_b_pins[] = {
2583         /* RXD, TXD */
2584         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
2585 };
2586 static const unsigned int scifa5_data_b_mux[] = {
2587         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2588 };
2589 static const unsigned int scifa5_data_c_pins[] = {
2590         /* RXD, TXD */
2591         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2592 };
2593 static const unsigned int scifa5_data_c_mux[] = {
2594         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2595 };
2596 static const unsigned int scifa5_data_d_pins[] = {
2597         /* RXD, TXD */
2598         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2599 };
2600 static const unsigned int scifa5_data_d_mux[] = {
2601         SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
2602 };
2603 /* - SCIFB0 ----------------------------------------------------------------- */
2604 static const unsigned int scifb0_data_pins[] = {
2605         /* RXD, TXD */
2606         RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
2607 };
2608 static const unsigned int scifb0_data_mux[] = {
2609         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2610 };
2611 static const unsigned int scifb0_clk_pins[] = {
2612         /* SCK */
2613         RCAR_GP_PIN(0, 19),
2614 };
2615 static const unsigned int scifb0_clk_mux[] = {
2616         SCIFB0_SCK_MARK,
2617 };
2618 static const unsigned int scifb0_ctrl_pins[] = {
2619         /* RTS, CTS */
2620         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
2621 };
2622 static const unsigned int scifb0_ctrl_mux[] = {
2623         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2624 };
2625 /* - SCIFB1 ----------------------------------------------------------------- */
2626 static const unsigned int scifb1_data_pins[] = {
2627         /* RXD, TXD */
2628         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
2629 };
2630 static const unsigned int scifb1_data_mux[] = {
2631         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2632 };
2633 static const unsigned int scifb1_clk_pins[] = {
2634         /* SCK */
2635         RCAR_GP_PIN(0, 16),
2636 };
2637 static const unsigned int scifb1_clk_mux[] = {
2638         SCIFB1_SCK_MARK,
2639 };
2640 /* - SCIFB2 ----------------------------------------------------------------- */
2641 static const unsigned int scifb2_data_pins[] = {
2642         /* RXD, TXD */
2643         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2644 };
2645 static const unsigned int scifb2_data_mux[] = {
2646         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2647 };
2648 static const unsigned int scifb2_clk_pins[] = {
2649         /* SCK */
2650         RCAR_GP_PIN(1, 15),
2651 };
2652 static const unsigned int scifb2_clk_mux[] = {
2653         SCIFB2_SCK_MARK,
2654 };
2655 static const unsigned int scifb2_ctrl_pins[] = {
2656         /* RTS, CTS */
2657         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2658 };
2659 static const unsigned int scifb2_ctrl_mux[] = {
2660         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2661 };
2662 /* - SDHI0 ------------------------------------------------------------------ */
2663 static const unsigned int sdhi0_data1_pins[] = {
2664         /* D0 */
2665         RCAR_GP_PIN(6, 2),
2666 };
2667 static const unsigned int sdhi0_data1_mux[] = {
2668         SD0_DATA0_MARK,
2669 };
2670 static const unsigned int sdhi0_data4_pins[] = {
2671         /* D[0:3] */
2672         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2673         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2674 };
2675 static const unsigned int sdhi0_data4_mux[] = {
2676         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2677 };
2678 static const unsigned int sdhi0_ctrl_pins[] = {
2679         /* CLK, CMD */
2680         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2681 };
2682 static const unsigned int sdhi0_ctrl_mux[] = {
2683         SD0_CLK_MARK, SD0_CMD_MARK,
2684 };
2685 static const unsigned int sdhi0_cd_pins[] = {
2686         /* CD */
2687         RCAR_GP_PIN(6, 6),
2688 };
2689 static const unsigned int sdhi0_cd_mux[] = {
2690         SD0_CD_MARK,
2691 };
2692 static const unsigned int sdhi0_wp_pins[] = {
2693         /* WP */
2694         RCAR_GP_PIN(6, 7),
2695 };
2696 static const unsigned int sdhi0_wp_mux[] = {
2697         SD0_WP_MARK,
2698 };
2699 /* - SDHI1 ------------------------------------------------------------------ */
2700 static const unsigned int sdhi1_data1_pins[] = {
2701         /* D0 */
2702         RCAR_GP_PIN(6, 10),
2703 };
2704 static const unsigned int sdhi1_data1_mux[] = {
2705         SD1_DATA0_MARK,
2706 };
2707 static const unsigned int sdhi1_data4_pins[] = {
2708         /* D[0:3] */
2709         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2710         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2711 };
2712 static const unsigned int sdhi1_data4_mux[] = {
2713         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2714 };
2715 static const unsigned int sdhi1_ctrl_pins[] = {
2716         /* CLK, CMD */
2717         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2718 };
2719 static const unsigned int sdhi1_ctrl_mux[] = {
2720         SD1_CLK_MARK, SD1_CMD_MARK,
2721 };
2722 static const unsigned int sdhi1_cd_pins[] = {
2723         /* CD */
2724         RCAR_GP_PIN(6, 14),
2725 };
2726 static const unsigned int sdhi1_cd_mux[] = {
2727         SD1_CD_MARK,
2728 };
2729 static const unsigned int sdhi1_wp_pins[] = {
2730         /* WP */
2731         RCAR_GP_PIN(6, 15),
2732 };
2733 static const unsigned int sdhi1_wp_mux[] = {
2734         SD1_WP_MARK,
2735 };
2736 /* - SDHI2 ------------------------------------------------------------------ */
2737 static const unsigned int sdhi2_data1_pins[] = {
2738         /* D0 */
2739         RCAR_GP_PIN(6, 18),
2740 };
2741 static const unsigned int sdhi2_data1_mux[] = {
2742         SD2_DATA0_MARK,
2743 };
2744 static const unsigned int sdhi2_data4_pins[] = {
2745         /* D[0:3] */
2746         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2747         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2748 };
2749 static const unsigned int sdhi2_data4_mux[] = {
2750         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
2751 };
2752 static const unsigned int sdhi2_ctrl_pins[] = {
2753         /* CLK, CMD */
2754         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2755 };
2756 static const unsigned int sdhi2_ctrl_mux[] = {
2757         SD2_CLK_MARK, SD2_CMD_MARK,
2758 };
2759 static const unsigned int sdhi2_cd_pins[] = {
2760         /* CD */
2761         RCAR_GP_PIN(6, 22),
2762 };
2763 static const unsigned int sdhi2_cd_mux[] = {
2764         SD2_CD_MARK,
2765 };
2766 static const unsigned int sdhi2_wp_pins[] = {
2767         /* WP */
2768         RCAR_GP_PIN(6, 23),
2769 };
2770 static const unsigned int sdhi2_wp_mux[] = {
2771         SD2_WP_MARK,
2772 };
2773 /* - USB0 ------------------------------------------------------------------- */
2774 static const unsigned int usb0_pins[] = {
2775         RCAR_GP_PIN(5, 24), /* PWEN */
2776         RCAR_GP_PIN(5, 25), /* OVC */
2777 };
2778 static const unsigned int usb0_mux[] = {
2779         USB0_PWEN_MARK,
2780         USB0_OVC_MARK,
2781 };
2782 /* - USB1 ------------------------------------------------------------------- */
2783 static const unsigned int usb1_pins[] = {
2784         RCAR_GP_PIN(5, 26), /* PWEN */
2785         RCAR_GP_PIN(5, 27), /* OVC */
2786 };
2787 static const unsigned int usb1_mux[] = {
2788         USB1_PWEN_MARK,
2789         USB1_OVC_MARK,
2790 };
2791
2792 static const struct sh_pfc_pin_group pinmux_groups[] = {
2793         SH_PFC_PIN_GROUP(eth_link),
2794         SH_PFC_PIN_GROUP(eth_magic),
2795         SH_PFC_PIN_GROUP(eth_mdio),
2796         SH_PFC_PIN_GROUP(eth_rmii),
2797         SH_PFC_PIN_GROUP(eth_link_b),
2798         SH_PFC_PIN_GROUP(eth_magic_b),
2799         SH_PFC_PIN_GROUP(eth_mdio_b),
2800         SH_PFC_PIN_GROUP(eth_rmii_b),
2801         SH_PFC_PIN_GROUP(hscif0_data),
2802         SH_PFC_PIN_GROUP(hscif0_clk),
2803         SH_PFC_PIN_GROUP(hscif0_ctrl),
2804         SH_PFC_PIN_GROUP(hscif0_data_b),
2805         SH_PFC_PIN_GROUP(hscif0_clk_b),
2806         SH_PFC_PIN_GROUP(hscif1_data),
2807         SH_PFC_PIN_GROUP(hscif1_clk),
2808         SH_PFC_PIN_GROUP(hscif1_ctrl),
2809         SH_PFC_PIN_GROUP(hscif1_data_b),
2810         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2811         SH_PFC_PIN_GROUP(hscif2_data),
2812         SH_PFC_PIN_GROUP(hscif2_clk),
2813         SH_PFC_PIN_GROUP(hscif2_ctrl),
2814         SH_PFC_PIN_GROUP(i2c0),
2815         SH_PFC_PIN_GROUP(i2c0_b),
2816         SH_PFC_PIN_GROUP(i2c0_c),
2817         SH_PFC_PIN_GROUP(i2c0_d),
2818         SH_PFC_PIN_GROUP(i2c0_e),
2819         SH_PFC_PIN_GROUP(i2c1),
2820         SH_PFC_PIN_GROUP(i2c1_b),
2821         SH_PFC_PIN_GROUP(i2c1_c),
2822         SH_PFC_PIN_GROUP(i2c1_d),
2823         SH_PFC_PIN_GROUP(i2c1_e),
2824         SH_PFC_PIN_GROUP(i2c2),
2825         SH_PFC_PIN_GROUP(i2c2_b),
2826         SH_PFC_PIN_GROUP(i2c2_c),
2827         SH_PFC_PIN_GROUP(i2c2_d),
2828         SH_PFC_PIN_GROUP(i2c2_e),
2829         SH_PFC_PIN_GROUP(i2c3),
2830         SH_PFC_PIN_GROUP(i2c3_b),
2831         SH_PFC_PIN_GROUP(i2c3_c),
2832         SH_PFC_PIN_GROUP(i2c3_d),
2833         SH_PFC_PIN_GROUP(i2c3_e),
2834         SH_PFC_PIN_GROUP(i2c4),
2835         SH_PFC_PIN_GROUP(i2c4_b),
2836         SH_PFC_PIN_GROUP(i2c4_c),
2837         SH_PFC_PIN_GROUP(i2c4_d),
2838         SH_PFC_PIN_GROUP(i2c4_e),
2839         SH_PFC_PIN_GROUP(intc_irq0),
2840         SH_PFC_PIN_GROUP(intc_irq1),
2841         SH_PFC_PIN_GROUP(intc_irq2),
2842         SH_PFC_PIN_GROUP(intc_irq3),
2843         SH_PFC_PIN_GROUP(intc_irq4),
2844         SH_PFC_PIN_GROUP(intc_irq5),
2845         SH_PFC_PIN_GROUP(intc_irq6),
2846         SH_PFC_PIN_GROUP(intc_irq7),
2847         SH_PFC_PIN_GROUP(intc_irq8),
2848         SH_PFC_PIN_GROUP(intc_irq9),
2849         SH_PFC_PIN_GROUP(mmc_data1),
2850         SH_PFC_PIN_GROUP(mmc_data4),
2851         SH_PFC_PIN_GROUP(mmc_data8),
2852         SH_PFC_PIN_GROUP(mmc_ctrl),
2853         SH_PFC_PIN_GROUP(msiof0_clk),
2854         SH_PFC_PIN_GROUP(msiof0_sync),
2855         SH_PFC_PIN_GROUP(msiof0_ss1),
2856         SH_PFC_PIN_GROUP(msiof0_ss2),
2857         SH_PFC_PIN_GROUP(msiof0_rx),
2858         SH_PFC_PIN_GROUP(msiof0_tx),
2859         SH_PFC_PIN_GROUP(msiof1_clk),
2860         SH_PFC_PIN_GROUP(msiof1_sync),
2861         SH_PFC_PIN_GROUP(msiof1_ss1),
2862         SH_PFC_PIN_GROUP(msiof1_ss2),
2863         SH_PFC_PIN_GROUP(msiof1_rx),
2864         SH_PFC_PIN_GROUP(msiof1_tx),
2865         SH_PFC_PIN_GROUP(msiof1_clk_b),
2866         SH_PFC_PIN_GROUP(msiof1_sync_b),
2867         SH_PFC_PIN_GROUP(msiof1_ss1_b),
2868         SH_PFC_PIN_GROUP(msiof1_ss2_b),
2869         SH_PFC_PIN_GROUP(msiof1_rx_b),
2870         SH_PFC_PIN_GROUP(msiof1_tx_b),
2871         SH_PFC_PIN_GROUP(msiof2_clk),
2872         SH_PFC_PIN_GROUP(msiof2_sync),
2873         SH_PFC_PIN_GROUP(msiof2_ss1),
2874         SH_PFC_PIN_GROUP(msiof2_ss2),
2875         SH_PFC_PIN_GROUP(msiof2_rx),
2876         SH_PFC_PIN_GROUP(msiof2_tx),
2877         SH_PFC_PIN_GROUP(msiof2_clk_b),
2878         SH_PFC_PIN_GROUP(msiof2_sync_b),
2879         SH_PFC_PIN_GROUP(msiof2_ss1_b),
2880         SH_PFC_PIN_GROUP(msiof2_ss2_b),
2881         SH_PFC_PIN_GROUP(msiof2_rx_b),
2882         SH_PFC_PIN_GROUP(msiof2_tx_b),
2883         SH_PFC_PIN_GROUP(qspi_ctrl),
2884         SH_PFC_PIN_GROUP(qspi_data2),
2885         SH_PFC_PIN_GROUP(qspi_data4),
2886         SH_PFC_PIN_GROUP(scif0_data),
2887         SH_PFC_PIN_GROUP(scif0_clk),
2888         SH_PFC_PIN_GROUP(scif0_data_b),
2889         SH_PFC_PIN_GROUP(scif0_clk_b),
2890         SH_PFC_PIN_GROUP(scif0_data_c),
2891         SH_PFC_PIN_GROUP(scif0_data_d),
2892         SH_PFC_PIN_GROUP(scif1_data),
2893         SH_PFC_PIN_GROUP(scif1_clk),
2894         SH_PFC_PIN_GROUP(scif1_data_b),
2895         SH_PFC_PIN_GROUP(scif1_clk_b),
2896         SH_PFC_PIN_GROUP(scif1_data_c),
2897         SH_PFC_PIN_GROUP(scif1_clk_c),
2898         SH_PFC_PIN_GROUP(scif2_data),
2899         SH_PFC_PIN_GROUP(scif2_clk),
2900         SH_PFC_PIN_GROUP(scif2_data_b),
2901         SH_PFC_PIN_GROUP(scif2_clk_b),
2902         SH_PFC_PIN_GROUP(scif2_data_c),
2903         SH_PFC_PIN_GROUP(scif2_clk_c),
2904         SH_PFC_PIN_GROUP(scif3_data),
2905         SH_PFC_PIN_GROUP(scif3_clk),
2906         SH_PFC_PIN_GROUP(scif3_data_b),
2907         SH_PFC_PIN_GROUP(scif3_clk_b),
2908         SH_PFC_PIN_GROUP(scif4_data),
2909         SH_PFC_PIN_GROUP(scif4_data_b),
2910         SH_PFC_PIN_GROUP(scif4_data_c),
2911         SH_PFC_PIN_GROUP(scif4_data_d),
2912         SH_PFC_PIN_GROUP(scif4_data_e),
2913         SH_PFC_PIN_GROUP(scif5_data),
2914         SH_PFC_PIN_GROUP(scif5_data_b),
2915         SH_PFC_PIN_GROUP(scif5_data_c),
2916         SH_PFC_PIN_GROUP(scif5_data_d),
2917         SH_PFC_PIN_GROUP(scifa0_data),
2918         SH_PFC_PIN_GROUP(scifa0_data_b),
2919         SH_PFC_PIN_GROUP(scifa0_data_c),
2920         SH_PFC_PIN_GROUP(scifa0_data_d),
2921         SH_PFC_PIN_GROUP(scifa1_data),
2922         SH_PFC_PIN_GROUP(scifa1_clk),
2923         SH_PFC_PIN_GROUP(scifa1_data_b),
2924         SH_PFC_PIN_GROUP(scifa1_clk_b),
2925         SH_PFC_PIN_GROUP(scifa1_data_c),
2926         SH_PFC_PIN_GROUP(scifa1_clk_c),
2927         SH_PFC_PIN_GROUP(scifa2_data),
2928         SH_PFC_PIN_GROUP(scifa2_clk),
2929         SH_PFC_PIN_GROUP(scifa2_data_b),
2930         SH_PFC_PIN_GROUP(scifa2_clk_b),
2931         SH_PFC_PIN_GROUP(scifa3_data),
2932         SH_PFC_PIN_GROUP(scifa3_clk),
2933         SH_PFC_PIN_GROUP(scifa3_data_b),
2934         SH_PFC_PIN_GROUP(scifa3_clk_b),
2935         SH_PFC_PIN_GROUP(scifa4_data),
2936         SH_PFC_PIN_GROUP(scifa4_data_b),
2937         SH_PFC_PIN_GROUP(scifa4_data_c),
2938         SH_PFC_PIN_GROUP(scifa4_data_d),
2939         SH_PFC_PIN_GROUP(scifa5_data),
2940         SH_PFC_PIN_GROUP(scifa5_data_b),
2941         SH_PFC_PIN_GROUP(scifa5_data_c),
2942         SH_PFC_PIN_GROUP(scifa5_data_d),
2943         SH_PFC_PIN_GROUP(scifb0_data),
2944         SH_PFC_PIN_GROUP(scifb0_clk),
2945         SH_PFC_PIN_GROUP(scifb0_ctrl),
2946         SH_PFC_PIN_GROUP(scifb1_data),
2947         SH_PFC_PIN_GROUP(scifb1_clk),
2948         SH_PFC_PIN_GROUP(scifb2_data),
2949         SH_PFC_PIN_GROUP(scifb2_clk),
2950         SH_PFC_PIN_GROUP(scifb2_ctrl),
2951         SH_PFC_PIN_GROUP(sdhi0_data1),
2952         SH_PFC_PIN_GROUP(sdhi0_data4),
2953         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2954         SH_PFC_PIN_GROUP(sdhi0_cd),
2955         SH_PFC_PIN_GROUP(sdhi0_wp),
2956         SH_PFC_PIN_GROUP(sdhi1_data1),
2957         SH_PFC_PIN_GROUP(sdhi1_data4),
2958         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2959         SH_PFC_PIN_GROUP(sdhi1_cd),
2960         SH_PFC_PIN_GROUP(sdhi1_wp),
2961         SH_PFC_PIN_GROUP(sdhi2_data1),
2962         SH_PFC_PIN_GROUP(sdhi2_data4),
2963         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2964         SH_PFC_PIN_GROUP(sdhi2_cd),
2965         SH_PFC_PIN_GROUP(sdhi2_wp),
2966         SH_PFC_PIN_GROUP(usb0),
2967         SH_PFC_PIN_GROUP(usb1),
2968 };
2969
2970 static const char * const eth_groups[] = {
2971         "eth_link",
2972         "eth_magic",
2973         "eth_mdio",
2974         "eth_rmii",
2975         "eth_link_b",
2976         "eth_magic_b",
2977         "eth_mdio_b",
2978         "eth_rmii_b",
2979 };
2980
2981 static const char * const hscif0_groups[] = {
2982         "hscif0_data",
2983         "hscif0_clk",
2984         "hscif0_ctrl",
2985         "hscif0_data_b",
2986         "hscif0_clk_b",
2987 };
2988
2989 static const char * const hscif1_groups[] = {
2990         "hscif1_data",
2991         "hscif1_clk",
2992         "hscif1_ctrl",
2993         "hscif1_data_b",
2994         "hscif1_ctrl_b",
2995 };
2996
2997 static const char * const hscif2_groups[] = {
2998         "hscif2_data",
2999         "hscif2_clk",
3000         "hscif2_ctrl",
3001 };
3002
3003 static const char * const i2c0_groups[] = {
3004         "i2c0",
3005         "i2c0_b",
3006         "i2c0_c",
3007         "i2c0_d",
3008         "i2c0_e",
3009 };
3010
3011 static const char * const i2c1_groups[] = {
3012         "i2c1",
3013         "i2c1_b",
3014         "i2c1_c",
3015         "i2c1_d",
3016         "i2c1_e",
3017 };
3018
3019 static const char * const i2c2_groups[] = {
3020         "i2c2",
3021         "i2c2_b",
3022         "i2c2_c",
3023         "i2c2_d",
3024         "i2c2_e",
3025 };
3026
3027 static const char * const i2c3_groups[] = {
3028         "i2c3",
3029         "i2c3_b",
3030         "i2c3_c",
3031         "i2c3_d",
3032         "i2c3_e",
3033 };
3034
3035 static const char * const i2c4_groups[] = {
3036         "i2c4",
3037         "i2c4_b",
3038         "i2c4_c",
3039         "i2c4_d",
3040         "i2c4_e",
3041 };
3042
3043 static const char * const intc_groups[] = {
3044         "intc_irq0",
3045         "intc_irq1",
3046         "intc_irq2",
3047         "intc_irq3",
3048         "intc_irq4",
3049         "intc_irq5",
3050         "intc_irq6",
3051         "intc_irq7",
3052         "intc_irq8",
3053         "intc_irq9",
3054 };
3055
3056 static const char * const mmc_groups[] = {
3057         "mmc_data1",
3058         "mmc_data4",
3059         "mmc_data8",
3060         "mmc_ctrl",
3061 };
3062
3063 static const char * const msiof0_groups[] = {
3064         "msiof0_clk",
3065         "msiof0_sync",
3066         "msiof0_ss1",
3067         "msiof0_ss2",
3068         "msiof0_rx",
3069         "msiof0_tx",
3070 };
3071
3072 static const char * const msiof1_groups[] = {
3073         "msiof1_clk",
3074         "msiof1_sync",
3075         "msiof1_ss1",
3076         "msiof1_ss2",
3077         "msiof1_rx",
3078         "msiof1_tx",
3079         "msiof1_clk_b",
3080         "msiof1_sync_b",
3081         "msiof1_ss1_b",
3082         "msiof1_ss2_b",
3083         "msiof1_rx_b",
3084         "msiof1_tx_b",
3085 };
3086
3087 static const char * const msiof2_groups[] = {
3088         "msiof2_clk",
3089         "msiof2_sync",
3090         "msiof2_ss1",
3091         "msiof2_ss2",
3092         "msiof2_rx",
3093         "msiof2_tx",
3094         "msiof2_clk_b",
3095         "msiof2_sync_b",
3096         "msiof2_ss1_b",
3097         "msiof2_ss2_b",
3098         "msiof2_rx_b",
3099         "msiof2_tx_b",
3100 };
3101
3102 static const char * const qspi_groups[] = {
3103         "qspi_ctrl",
3104         "qspi_data2",
3105         "qspi_data4",
3106 };
3107
3108 static const char * const scif0_groups[] = {
3109         "scif0_data",
3110         "scif0_clk",
3111         "scif0_data_b",
3112         "scif0_clk_b",
3113         "scif0_data_c",
3114         "scif0_data_d",
3115 };
3116
3117 static const char * const scif1_groups[] = {
3118         "scif1_data",
3119         "scif1_clk",
3120         "scif1_data_b",
3121         "scif1_clk_b",
3122         "scif1_data_c",
3123         "scif1_clk_c",
3124 };
3125
3126 static const char * const scif2_groups[] = {
3127         "scif2_data",
3128         "scif2_clk",
3129         "scif2_data_b",
3130         "scif2_clk_b",
3131         "scif2_data_c",
3132         "scif2_clk_c",
3133 };
3134
3135 static const char * const scif3_groups[] = {
3136         "scif3_data",
3137         "scif3_clk",
3138         "scif3_data_b",
3139         "scif3_clk_b",
3140 };
3141
3142 static const char * const scif4_groups[] = {
3143         "scif4_data",
3144         "scif4_data_b",
3145         "scif4_data_c",
3146         "scif4_data_d",
3147         "scif4_data_e",
3148 };
3149
3150 static const char * const scif5_groups[] = {
3151         "scif5_data",
3152         "scif5_data_b",
3153         "scif5_data_c",
3154         "scif5_data_d",
3155 };
3156
3157 static const char * const scifa0_groups[] = {
3158         "scifa0_data",
3159         "scifa0_data_b",
3160         "scifa0_data_c",
3161         "scifa0_data_d",
3162 };
3163
3164 static const char * const scifa1_groups[] = {
3165         "scifa1_data",
3166         "scifa1_clk",
3167         "scifa1_data_b",
3168         "scifa1_clk_b",
3169         "scifa1_data_c",
3170         "scifa1_clk_c",
3171 };
3172
3173 static const char * const scifa2_groups[] = {
3174         "scifa2_data",
3175         "scifa2_clk",
3176         "scifa2_data_b",
3177         "scifa2_clk_b",
3178 };
3179
3180 static const char * const scifa3_groups[] = {
3181         "scifa3_data",
3182         "scifa3_clk",
3183         "scifa3_data_b",
3184         "scifa3_clk_b",
3185 };
3186
3187 static const char * const scifa4_groups[] = {
3188         "scifa4_data",
3189         "scifa4_data_b",
3190         "scifa4_data_c",
3191         "scifa4_data_d",
3192 };
3193
3194 static const char * const scifa5_groups[] = {
3195         "scifa5_data",
3196         "scifa5_data_b",
3197         "scifa5_data_c",
3198         "scifa5_data_d",
3199 };
3200
3201 static const char * const scifb0_groups[] = {
3202         "scifb0_data",
3203         "scifb0_clk",
3204         "scifb0_ctrl",
3205 };
3206
3207 static const char * const scifb1_groups[] = {
3208         "scifb1_data",
3209         "scifb1_clk",
3210 };
3211
3212 static const char * const scifb2_groups[] = {
3213         "scifb2_data",
3214         "scifb2_clk",
3215         "scifb2_ctrl",
3216 };
3217
3218 static const char * const sdhi0_groups[] = {
3219         "sdhi0_data1",
3220         "sdhi0_data4",
3221         "sdhi0_ctrl",
3222         "sdhi0_cd",
3223         "sdhi0_wp",
3224 };
3225
3226 static const char * const sdhi1_groups[] = {
3227         "sdhi1_data1",
3228         "sdhi1_data4",
3229         "sdhi1_ctrl",
3230         "sdhi1_cd",
3231         "sdhi1_wp",
3232 };
3233
3234 static const char * const sdhi2_groups[] = {
3235         "sdhi2_data1",
3236         "sdhi2_data4",
3237         "sdhi2_ctrl",
3238         "sdhi2_cd",
3239         "sdhi2_wp",
3240 };
3241
3242 static const char * const usb0_groups[] = {
3243         "usb0",
3244 };
3245
3246 static const char * const usb1_groups[] = {
3247         "usb1",
3248 };
3249
3250 static const struct sh_pfc_function pinmux_functions[] = {
3251         SH_PFC_FUNCTION(eth),
3252         SH_PFC_FUNCTION(hscif0),
3253         SH_PFC_FUNCTION(hscif1),
3254         SH_PFC_FUNCTION(hscif2),
3255         SH_PFC_FUNCTION(i2c0),
3256         SH_PFC_FUNCTION(i2c1),
3257         SH_PFC_FUNCTION(i2c2),
3258         SH_PFC_FUNCTION(i2c3),
3259         SH_PFC_FUNCTION(i2c4),
3260         SH_PFC_FUNCTION(intc),
3261         SH_PFC_FUNCTION(mmc),
3262         SH_PFC_FUNCTION(msiof0),
3263         SH_PFC_FUNCTION(msiof1),
3264         SH_PFC_FUNCTION(msiof2),
3265         SH_PFC_FUNCTION(qspi),
3266         SH_PFC_FUNCTION(scif0),
3267         SH_PFC_FUNCTION(scif1),
3268         SH_PFC_FUNCTION(scif2),
3269         SH_PFC_FUNCTION(scif3),
3270         SH_PFC_FUNCTION(scif4),
3271         SH_PFC_FUNCTION(scif5),
3272         SH_PFC_FUNCTION(scifa0),
3273         SH_PFC_FUNCTION(scifa1),
3274         SH_PFC_FUNCTION(scifa2),
3275         SH_PFC_FUNCTION(scifa3),
3276         SH_PFC_FUNCTION(scifa4),
3277         SH_PFC_FUNCTION(scifa5),
3278         SH_PFC_FUNCTION(scifb0),
3279         SH_PFC_FUNCTION(scifb1),
3280         SH_PFC_FUNCTION(scifb2),
3281         SH_PFC_FUNCTION(sdhi0),
3282         SH_PFC_FUNCTION(sdhi1),
3283         SH_PFC_FUNCTION(sdhi2),
3284         SH_PFC_FUNCTION(usb0),
3285         SH_PFC_FUNCTION(usb1),
3286 };
3287
3288 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3289         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3290                 GP_0_31_FN, FN_IP2_17_16,
3291                 GP_0_30_FN, FN_IP2_15_14,
3292                 GP_0_29_FN, FN_IP2_13_12,
3293                 GP_0_28_FN, FN_IP2_11_10,
3294                 GP_0_27_FN, FN_IP2_9_8,
3295                 GP_0_26_FN, FN_IP2_7_6,
3296                 GP_0_25_FN, FN_IP2_5_4,
3297                 GP_0_24_FN, FN_IP2_3_2,
3298                 GP_0_23_FN, FN_IP2_1_0,
3299                 GP_0_22_FN, FN_IP1_31_30,
3300                 GP_0_21_FN, FN_IP1_29_28,
3301                 GP_0_20_FN, FN_IP1_27,
3302                 GP_0_19_FN, FN_IP1_26,
3303                 GP_0_18_FN, FN_A2,
3304                 GP_0_17_FN, FN_IP1_24,
3305                 GP_0_16_FN, FN_IP1_23_22,
3306                 GP_0_15_FN, FN_IP1_21_20,
3307                 GP_0_14_FN, FN_IP1_19_18,
3308                 GP_0_13_FN, FN_IP1_17_15,
3309                 GP_0_12_FN, FN_IP1_14_13,
3310                 GP_0_11_FN, FN_IP1_12_11,
3311                 GP_0_10_FN, FN_IP1_10_8,
3312                 GP_0_9_FN, FN_IP1_7_6,
3313                 GP_0_8_FN, FN_IP1_5_4,
3314                 GP_0_7_FN, FN_IP1_3_2,
3315                 GP_0_6_FN, FN_IP1_1_0,
3316                 GP_0_5_FN, FN_IP0_31_30,
3317                 GP_0_4_FN, FN_IP0_29_28,
3318                 GP_0_3_FN, FN_IP0_27_26,
3319                 GP_0_2_FN, FN_IP0_25,
3320                 GP_0_1_FN, FN_IP0_24,
3321                 GP_0_0_FN, FN_IP0_23_22, }
3322         },
3323         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3324                 0, 0,
3325                 0, 0,
3326                 0, 0,
3327                 0, 0,
3328                 0, 0,
3329                 0, 0,
3330                 GP_1_25_FN, FN_DACK0,
3331                 GP_1_24_FN, FN_IP7_31,
3332                 GP_1_23_FN, FN_IP4_1_0,
3333                 GP_1_22_FN, FN_WE1_N,
3334                 GP_1_21_FN, FN_WE0_N,
3335                 GP_1_20_FN, FN_IP3_31,
3336                 GP_1_19_FN, FN_IP3_30,
3337                 GP_1_18_FN, FN_IP3_29_27,
3338                 GP_1_17_FN, FN_IP3_26_24,
3339                 GP_1_16_FN, FN_IP3_23_21,
3340                 GP_1_15_FN, FN_IP3_20_18,
3341                 GP_1_14_FN, FN_IP3_17_15,
3342                 GP_1_13_FN, FN_IP3_14_13,
3343                 GP_1_12_FN, FN_IP3_12,
3344                 GP_1_11_FN, FN_IP3_11,
3345                 GP_1_10_FN, FN_IP3_10,
3346                 GP_1_9_FN, FN_IP3_9_8,
3347                 GP_1_8_FN, FN_IP3_7_6,
3348                 GP_1_7_FN, FN_IP3_5_4,
3349                 GP_1_6_FN, FN_IP3_3_2,
3350                 GP_1_5_FN, FN_IP3_1_0,
3351                 GP_1_4_FN, FN_IP2_31_30,
3352                 GP_1_3_FN, FN_IP2_29_27,
3353                 GP_1_2_FN, FN_IP2_26_24,
3354                 GP_1_1_FN, FN_IP2_23_21,
3355                 GP_1_0_FN, FN_IP2_20_18, }
3356         },
3357         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3358                 GP_2_31_FN, FN_IP6_7_6,
3359                 GP_2_30_FN, FN_IP6_5_4,
3360                 GP_2_29_FN, FN_IP6_3_2,
3361                 GP_2_28_FN, FN_IP6_1_0,
3362                 GP_2_27_FN, FN_IP5_31_30,
3363                 GP_2_26_FN, FN_IP5_29_28,
3364                 GP_2_25_FN, FN_IP5_27_26,
3365                 GP_2_24_FN, FN_IP5_25_24,
3366                 GP_2_23_FN, FN_IP5_23_22,
3367                 GP_2_22_FN, FN_IP5_21_20,
3368                 GP_2_21_FN, FN_IP5_19_18,
3369                 GP_2_20_FN, FN_IP5_17_16,
3370                 GP_2_19_FN, FN_IP5_15_14,
3371                 GP_2_18_FN, FN_IP5_13_12,
3372                 GP_2_17_FN, FN_IP5_11_9,
3373                 GP_2_16_FN, FN_IP5_8_6,
3374                 GP_2_15_FN, FN_IP5_5_4,
3375                 GP_2_14_FN, FN_IP5_3_2,
3376                 GP_2_13_FN, FN_IP5_1_0,
3377                 GP_2_12_FN, FN_IP4_31_30,
3378                 GP_2_11_FN, FN_IP4_29_28,
3379                 GP_2_10_FN, FN_IP4_27_26,
3380                 GP_2_9_FN, FN_IP4_25_23,
3381                 GP_2_8_FN, FN_IP4_22_20,
3382                 GP_2_7_FN, FN_IP4_19_18,
3383                 GP_2_6_FN, FN_IP4_17_16,
3384                 GP_2_5_FN, FN_IP4_15_14,
3385                 GP_2_4_FN, FN_IP4_13_12,
3386                 GP_2_3_FN, FN_IP4_11_10,
3387                 GP_2_2_FN, FN_IP4_9_8,
3388                 GP_2_1_FN, FN_IP4_7_5,
3389                 GP_2_0_FN, FN_IP4_4_2 }
3390         },
3391         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3392                 GP_3_31_FN, FN_IP8_22_20,
3393                 GP_3_30_FN, FN_IP8_19_17,
3394                 GP_3_29_FN, FN_IP8_16_15,
3395                 GP_3_28_FN, FN_IP8_14_12,
3396                 GP_3_27_FN, FN_IP8_11_9,
3397                 GP_3_26_FN, FN_IP8_8_6,
3398                 GP_3_25_FN, FN_IP8_5_3,
3399                 GP_3_24_FN, FN_IP8_2_0,
3400                 GP_3_23_FN, FN_IP7_29_27,
3401                 GP_3_22_FN, FN_IP7_26_24,
3402                 GP_3_21_FN, FN_IP7_23_21,
3403                 GP_3_20_FN, FN_IP7_20_18,
3404                 GP_3_19_FN, FN_IP7_17_15,
3405                 GP_3_18_FN, FN_IP7_14_12,
3406                 GP_3_17_FN, FN_IP7_11_9,
3407                 GP_3_16_FN, FN_IP7_8_6,
3408                 GP_3_15_FN, FN_IP7_5_3,
3409                 GP_3_14_FN, FN_IP7_2_0,
3410                 GP_3_13_FN, FN_IP6_31_29,
3411                 GP_3_12_FN, FN_IP6_28_26,
3412                 GP_3_11_FN, FN_IP6_25_23,
3413                 GP_3_10_FN, FN_IP6_22_20,
3414                 GP_3_9_FN, FN_IP6_19_17,
3415                 GP_3_8_FN, FN_IP6_16,
3416                 GP_3_7_FN, FN_IP6_15,
3417                 GP_3_6_FN, FN_IP6_14,
3418                 GP_3_5_FN, FN_IP6_13,
3419                 GP_3_4_FN, FN_IP6_12,
3420                 GP_3_3_FN, FN_IP6_11,
3421                 GP_3_2_FN, FN_IP6_10,
3422                 GP_3_1_FN, FN_IP6_9,
3423                 GP_3_0_FN, FN_IP6_8 }
3424         },
3425         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3426                 GP_4_31_FN, FN_IP11_17_16,
3427                 GP_4_30_FN, FN_IP11_15_14,
3428                 GP_4_29_FN, FN_IP11_13_11,
3429                 GP_4_28_FN, FN_IP11_10_8,
3430                 GP_4_27_FN, FN_IP11_7_6,
3431                 GP_4_26_FN, FN_IP11_5_3,
3432                 GP_4_25_FN, FN_IP11_2_0,
3433                 GP_4_24_FN, FN_IP10_31_30,
3434                 GP_4_23_FN, FN_IP10_29_27,
3435                 GP_4_22_FN, FN_IP10_26_24,
3436                 GP_4_21_FN, FN_IP10_23_21,
3437                 GP_4_20_FN, FN_IP10_20_18,
3438                 GP_4_19_FN, FN_IP10_17_15,
3439                 GP_4_18_FN, FN_IP10_14_12,
3440                 GP_4_17_FN, FN_IP10_11_9,
3441                 GP_4_16_FN, FN_IP10_8_6,
3442                 GP_4_15_FN, FN_IP10_5_3,
3443                 GP_4_14_FN, FN_IP10_2_0,
3444                 GP_4_13_FN, FN_IP9_30_28,
3445                 GP_4_12_FN, FN_IP9_27_25,
3446                 GP_4_11_FN, FN_IP9_24_22,
3447                 GP_4_10_FN, FN_IP9_21_19,
3448                 GP_4_9_FN, FN_IP9_18_17,
3449                 GP_4_8_FN, FN_IP9_16_15,
3450                 GP_4_7_FN, FN_IP9_14_12,
3451                 GP_4_6_FN, FN_IP9_11_9,
3452                 GP_4_5_FN, FN_IP9_8_6,
3453                 GP_4_4_FN, FN_IP9_5_3,
3454                 GP_4_3_FN, FN_IP9_2_0,
3455                 GP_4_2_FN, FN_IP8_31_29,
3456                 GP_4_1_FN, FN_IP8_28_26,
3457                 GP_4_0_FN, FN_IP8_25_23 }
3458         },
3459         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3460                 0, 0,
3461                 0, 0,
3462                 0, 0,
3463                 0, 0,
3464                 GP_5_27_FN, FN_USB1_OVC,
3465                 GP_5_26_FN, FN_USB1_PWEN,
3466                 GP_5_25_FN, FN_USB0_OVC,
3467                 GP_5_24_FN, FN_USB0_PWEN,
3468                 GP_5_23_FN, FN_IP13_26_24,
3469                 GP_5_22_FN, FN_IP13_23_21,
3470                 GP_5_21_FN, FN_IP13_20_18,
3471                 GP_5_20_FN, FN_IP13_17_15,
3472                 GP_5_19_FN, FN_IP13_14_12,
3473                 GP_5_18_FN, FN_IP13_11_9,
3474                 GP_5_17_FN, FN_IP13_8_6,
3475                 GP_5_16_FN, FN_IP13_5_3,
3476                 GP_5_15_FN, FN_IP13_2_0,
3477                 GP_5_14_FN, FN_IP12_29_27,
3478                 GP_5_13_FN, FN_IP12_26_24,
3479                 GP_5_12_FN, FN_IP12_23_21,
3480                 GP_5_11_FN, FN_IP12_20_18,
3481                 GP_5_10_FN, FN_IP12_17_15,
3482                 GP_5_9_FN, FN_IP12_14_13,
3483                 GP_5_8_FN, FN_IP12_12_11,
3484                 GP_5_7_FN, FN_IP12_10_9,
3485                 GP_5_6_FN, FN_IP12_8_6,
3486                 GP_5_5_FN, FN_IP12_5_3,
3487                 GP_5_4_FN, FN_IP12_2_0,
3488                 GP_5_3_FN, FN_IP11_29_27,
3489                 GP_5_2_FN, FN_IP11_26_24,
3490                 GP_5_1_FN, FN_IP11_23_21,
3491                 GP_5_0_FN, FN_IP11_20_18 }
3492         },
3493         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
3494                 0, 0,
3495                 0, 0,
3496                 0, 0,
3497                 0, 0,
3498                 0, 0,
3499                 0, 0,
3500                 GP_6_25_FN, FN_IP0_21_20,
3501                 GP_6_24_FN, FN_IP0_19_18,
3502                 GP_6_23_FN, FN_IP0_17,
3503                 GP_6_22_FN, FN_IP0_16,
3504                 GP_6_21_FN, FN_IP0_15,
3505                 GP_6_20_FN, FN_IP0_14,
3506                 GP_6_19_FN, FN_IP0_13,
3507                 GP_6_18_FN, FN_IP0_12,
3508                 GP_6_17_FN, FN_IP0_11,
3509                 GP_6_16_FN, FN_IP0_10,
3510                 GP_6_15_FN, FN_IP0_9_8,
3511                 GP_6_14_FN, FN_IP0_0,
3512                 GP_6_13_FN, FN_SD1_DATA3,
3513                 GP_6_12_FN, FN_SD1_DATA2,
3514                 GP_6_11_FN, FN_SD1_DATA1,
3515                 GP_6_10_FN, FN_SD1_DATA0,
3516                 GP_6_9_FN, FN_SD1_CMD,
3517                 GP_6_8_FN, FN_SD1_CLK,
3518                 GP_6_7_FN, FN_SD0_WP,
3519                 GP_6_6_FN, FN_SD0_CD,
3520                 GP_6_5_FN, FN_SD0_DATA3,
3521                 GP_6_4_FN, FN_SD0_DATA2,
3522                 GP_6_3_FN, FN_SD0_DATA1,
3523                 GP_6_2_FN, FN_SD0_DATA0,
3524                 GP_6_1_FN, FN_SD0_CMD,
3525                 GP_6_0_FN, FN_SD0_CLK }
3526         },
3527         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3528                              2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
3529                              2, 1, 1, 1, 1, 1, 1, 1, 1) {
3530                 /* IP0_31_30 [2] */
3531                 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
3532                 /* IP0_29_28 [2] */
3533                 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
3534                 /* IP0_27_26 [2] */
3535                 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
3536                 /* IP0_25 [1] */
3537                 FN_D2, FN_SCIFA3_TXD_B,
3538                 /* IP0_24 [1] */
3539                 FN_D1, FN_SCIFA3_RXD_B,
3540                 /* IP0_23_22 [2] */
3541                 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
3542                 /* IP0_21_20 [2] */
3543                 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
3544                 /* IP0_19_18 [2] */
3545                 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
3546                 /* IP0_17 [1] */
3547                 FN_MMC_D5, FN_SD2_WP,
3548                 /* IP0_16 [1] */
3549                 FN_MMC_D4, FN_SD2_CD,
3550                 /* IP0_15 [1] */
3551                 FN_MMC_D3, FN_SD2_DATA3,
3552                 /* IP0_14 [1] */
3553                 FN_MMC_D2, FN_SD2_DATA2,
3554                 /* IP0_13 [1] */
3555                 FN_MMC_D1, FN_SD2_DATA1,
3556                 /* IP0_12 [1] */
3557                 FN_MMC_D0, FN_SD2_DATA0,
3558                 /* IP0_11 [1] */
3559                 FN_MMC_CMD, FN_SD2_CMD,
3560                 /* IP0_10 [1] */
3561                 FN_MMC_CLK, FN_SD2_CLK,
3562                 /* IP0_9_8 [2] */
3563                 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
3564                 /* IP0_7 [1] */
3565                 0, 0,
3566                 /* IP0_6 [1] */
3567                 0, 0,
3568                 /* IP0_5 [1] */
3569                 0, 0,
3570                 /* IP0_4 [1] */
3571                 0, 0,
3572                 /* IP0_3 [1] */
3573                 0, 0,
3574                 /* IP0_2 [1] */
3575                 0, 0,
3576                 /* IP0_1 [1] */
3577                 0, 0,
3578                 /* IP0_0 [1] */
3579                 FN_SD1_CD, FN_CAN0_RX, }
3580         },
3581         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3582                              2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
3583                              2, 2) {
3584                 /* IP1_31_30 [2] */
3585                 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
3586                 /* IP1_29_28 [2] */
3587                 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
3588                 /* IP1_27 [1] */
3589                 FN_A4, FN_SCIFB0_TXD,
3590                 /* IP1_26 [1] */
3591                 FN_A3, FN_SCIFB0_SCK,
3592                 /* IP1_25 [1] */
3593                 0, 0,
3594                 /* IP1_24 [1] */
3595                 FN_A1, FN_SCIFB1_TXD,
3596                 /* IP1_23_22 [2] */
3597                 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
3598                 /* IP1_21_20 [2] */
3599                 FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0,
3600                 /* IP1_19_18 [2] */
3601                 FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0,
3602                 /* IP1_17_15 [3] */
3603                 FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
3604                 0, 0, 0,
3605                 /* IP1_14_13 [2] */
3606                 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
3607                 /* IP1_12_11 [2] */
3608                 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
3609                 /* IP1_10_8 [3] */
3610                 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
3611                 0, 0, 0,
3612                 /* IP1_7_6 [2] */
3613                 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
3614                 /* IP1_5_4 [2] */
3615                 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
3616                 /* IP1_3_2 [2] */
3617                 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
3618                 /* IP1_1_0 [2] */
3619                 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
3620         },
3621         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3622                              2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
3623                 /* IP2_31_30 [2] */
3624                 FN_A20, FN_SPCLK, FN_MOUT1, 0,
3625                 /* IP2_29_27 [3] */
3626                 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
3627                 FN_MOUT0, 0, 0, 0,
3628                 /* IP2_26_24 [3] */
3629                 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
3630                 FN_AVB_AVTP_MATCH_B, 0, 0, 0,
3631                 /* IP2_23_21 [3] */
3632                 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
3633                 FN_AVB_AVTP_CAPTURE_B, 0, 0, 0,
3634                 /* IP2_20_18 [3] */
3635                 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
3636                 FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
3637                 /* IP2_17_16 [2] */
3638                 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
3639                 /* IP2_15_14 [2] */
3640                 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
3641                 /* IP2_13_12 [2] */
3642                 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
3643                 /* IP2_11_10 [2] */
3644                 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
3645                 /* IP2_9_8 [2] */
3646                 FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0,
3647                 /* IP2_7_6 [2] */
3648                 FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0,
3649                 /* IP2_5_4 [2] */
3650                 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
3651                 /* IP2_3_2 [2] */
3652                 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
3653                 /* IP2_1_0 [2] */
3654                 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
3655         },
3656         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3657                              1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
3658                 /* IP3_31 [1] */
3659                 FN_RD_WR_N, FN_ATAG1_N,
3660                 /* IP3_30 [1] */
3661                 FN_RD_N, FN_ATACS11_N,
3662                 /* IP3_29_27 [3] */
3663                 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
3664                 FN_MTS_N_B, 0, 0,
3665                 /* IP3_26_24 [3] */
3666                 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
3667                 FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
3668                 /* IP3_23_21 [3] */
3669                 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
3670                 FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B,
3671                 /* IP3_20_18 [3] */
3672                 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
3673                 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B,
3674                 /* IP3_17_15 [3] */
3675                 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
3676                 FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B,
3677                 /* IP3_14_13 [2] */
3678                 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
3679                 /* IP3_12 [1] */
3680                 FN_EX_CS0_N, FN_VI1_DATA10,
3681                 /* IP3_11 [1] */
3682                 FN_CS1_N_A26, FN_VI1_DATA9,
3683                 /* IP3_10 [1] */
3684                 FN_CS0_N, FN_VI1_DATA8,
3685                 /* IP3_9_8 [2] */
3686                 FN_A25, FN_SSL, FN_ATARD1_N, 0,
3687                 /* IP3_7_6 [2] */
3688                 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
3689                 /* IP3_5_4 [2] */
3690                 FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N,
3691                 /* IP3_3_2 [2] */
3692                 FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N,
3693                 /* IP3_1_0 [2] */
3694                 FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, }
3695         },
3696         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3697                              2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
3698                 /* IP4_31_30 [2] */
3699                 FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0,
3700                 /* IP4_29_28 [2] */
3701                 FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0,
3702                 /* IP4_27_26 [2] */
3703                 FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0,
3704                 /* IP4_25_23 [3] */
3705                 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
3706                 FN_CC50_STATE9, 0, 0, 0,
3707                 /* IP4_22_20 [3] */
3708                 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
3709                 FN_CC50_STATE8, 0, 0, 0,
3710                 /* IP4_19_18 [2] */
3711                 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0,
3712                 /* IP4_17_16 [2] */
3713                 FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0,
3714                 /* IP4_15_14 [2] */
3715                 FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0,
3716                 /* IP4_13_12 [2] */
3717                 FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0,
3718                 /* IP4_11_10 [2] */
3719                 FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0,
3720                 /* IP4_9_8 [2] */
3721                 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0,
3722                 /* IP4_7_5 [3] */
3723                 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
3724                 FN_CC50_STATE1, 0, 0, 0,
3725                 /* IP4_4_2 [3] */
3726                 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
3727                 FN_CC50_STATE0, 0, 0, 0,
3728                 /* IP4_1_0 [2] */
3729                 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, }
3730         },
3731         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3732                              2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
3733                 /* IP5_31_30 [2] */
3734                 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0,
3735                 /* IP5_29_28 [2] */
3736                 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0,
3737                 /* IP5_27_26 [2] */
3738                 FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0,
3739                 /* IP5_25_24 [2] */
3740                 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0,
3741                 /* IP5_23_22 [2] */
3742                 FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0,
3743                 /* IP5_21_20 [2] */
3744                 FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0,
3745                 /* IP5_19_18 [2] */
3746                 FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0,
3747                 /* IP5_17_16 [2] */
3748                 FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0,
3749                 /* IP5_15_14 [2] */
3750                 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0,
3751                 /* IP5_13_12 [2] */
3752                 FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0,
3753                 /* IP5_11_9 [3] */
3754                 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
3755                 FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0,
3756                 /* IP5_8_6 [3] */
3757                 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
3758                 FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0,
3759                 /* IP5_5_4 [2] */
3760                 FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0,
3761                 /* IP5_3_2 [2] */
3762                 FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0,
3763                 /* IP5_1_0 [2] */
3764                 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, }
3765         },
3766         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3767                              3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3768                              2, 2) {
3769                 /* IP6_31_29 [3] */
3770                 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
3771                 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
3772                 /* IP6_28_26 [3] */
3773                 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
3774                 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
3775                 /* IP6_25_23 [3] */
3776                 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
3777                 FN_AVB_COL, 0, 0, 0,
3778                 /* IP6_22_20 [3] */
3779                 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
3780                 FN_AVB_RX_ER, 0, 0, 0,
3781                 /* IP6_19_17 [3] */
3782                 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
3783                 FN_AVB_RXD7, 0, 0, 0,
3784                 /* IP6_16 [1] */
3785                 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
3786                 /* IP6_15 [1] */
3787                 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
3788                 /* IP6_14 [1] */
3789                 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
3790                 /* IP6_13 [1] */
3791                 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
3792                 /* IP6_12 [1] */
3793                 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
3794                 /* IP6_11 [1] */
3795                 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
3796                 /* IP6_10 [1] */
3797                 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
3798                 /* IP6_9 [1] */
3799                 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
3800                 /* IP6_8 [1] */
3801                 FN_VI0_CLK, FN_AVB_RX_CLK,
3802                 /* IP6_7_6 [2] */
3803                 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
3804                 /* IP6_5_4 [2] */
3805                 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
3806                 /* IP6_3_2 [2] */
3807                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
3808                 /* IP6_1_0 [2] */
3809                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
3810         },
3811         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3812                              1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3813                 /* IP7_31 [1] */
3814                 FN_DREQ0_N, FN_SCIFB1_RXD,
3815                 /* IP7_30 [1] */
3816                 0, 0,
3817                 /* IP7_29_27 [3] */
3818                 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
3819                 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
3820                 /* IP7_26_24 [3] */
3821                 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
3822                 FN_SSI_SCK6_B, 0, 0, 0,
3823                 /* IP7_23_21 [3] */
3824                 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
3825                 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
3826                 /* IP7_20_18 [3] */
3827                 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
3828                 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
3829                 /* IP7_17_15 [3] */
3830                 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
3831                 FN_SSI_SCK5_B, 0, 0, 0,
3832                 /* IP7_14_12 [3] */
3833                 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
3834                 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
3835                 /* IP7_11_9 [3] */
3836                 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
3837                 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
3838                 /* IP7_8_6 [3] */
3839                 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
3840                 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
3841                 /* IP7_5_3 [3] */
3842                 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
3843                 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
3844                 /* IP7_2_0 [3] */
3845                 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
3846                 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
3847         },
3848         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3849                              3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
3850                 /* IP8_31_29 [3] */
3851                 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
3852                 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
3853                 /* IP8_28_26 [3] */
3854                 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
3855                 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
3856                 /* IP8_25_23 [3] */
3857                 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
3858                 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
3859                 /* IP8_22_20 [3] */
3860                 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
3861                 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
3862                 /* IP8_19_17 [3] */
3863                 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
3864                 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
3865                 /* IP8_16_15 [2] */
3866                 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
3867                 /* IP8_14_12 [3] */
3868                 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
3869                 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
3870                 /* IP8_11_9 [3] */
3871                 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
3872                 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
3873                 /* IP8_8_6 [3] */
3874                 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
3875                 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
3876                 /* IP8_5_3 [3] */
3877                 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
3878                 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
3879                 /* IP8_2_0 [3] */
3880                 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
3881                 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
3882         },
3883         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3884                              1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
3885                 /* IP9_31 [1] */
3886                 0, 0,
3887                 /* IP9_30_28 [3] */
3888                 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
3889                 FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0,
3890                 /* IP9_27_25 [3] */
3891                 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
3892                 FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0,
3893                 /* IP9_24_22 [3] */
3894                 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
3895                 FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0,
3896                 /* IP9_21_19 [3] */
3897                 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
3898                 FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0,
3899                 /* IP9_18_17 [2] */
3900                 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
3901                 /* IP9_16_15 [2] */
3902                 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
3903                 /* IP9_14_12 [3] */
3904                 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
3905                 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0,
3906                 /* IP9_11_9 [3] */
3907                 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
3908                 FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0,
3909                 /* IP9_8_6 [3] */
3910                 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
3911                 FN_RIF1_CLK, FN_BPFCLK_B, 0, 0,
3912                 /* IP9_5_3 [3] */
3913                 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
3914                 FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0,
3915                 /* IP9_2_0 [3] */
3916                 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
3917                 FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, }
3918         },
3919         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3920                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3921                 /* IP10_31_30 [2] */
3922                 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
3923                 /* IP10_29_27 [3] */
3924                 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
3925                 FN_CAN_DEBUGOUT9, 0, 0, 0,
3926                 /* IP10_26_24 [3] */
3927                 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
3928                 FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0,
3929                 /* IP10_23_21 [3] */
3930                 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
3931                 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C,
3932                 /* IP10_20_18 [3] */
3933                 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
3934                 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C,
3935                 /* IP10_17_15 [3] */
3936                 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
3937                 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
3938                 /* IP10_14_12 [3] */
3939                 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
3940                 FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
3941                 /* IP10_11_9 [3] */
3942                 FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
3943                 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
3944                 /* IP10_8_6 [3] */
3945                 FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
3946                 FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
3947                 /* IP10_5_3 [3] */
3948                 FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
3949                 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
3950                 /* IP10_2_0 [3] */
3951                 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
3952                 FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
3953         },
3954         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3955                              2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
3956                 /* IP11_31_30 [2] */
3957                 0, 0, 0, 0,
3958                 /* IP11_29_27 [3] */
3959                 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
3960                 FN_AD_CLK_B, 0, 0, 0,
3961                 /* IP11_26_24 [3] */
3962                 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
3963                 FN_AD_DO_B, 0, 0, 0,
3964                 /* IP11_23_21 [3] */
3965                 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
3966                 FN_AD_DI_B, FN_PCMWE_N, 0, 0,
3967                 /* IP11_20_18 [3] */
3968                 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
3969                 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
3970                 /* IP11_17_16 [2] */
3971                 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
3972                 /* IP11_15_14 [2] */
3973                 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
3974                 /* IP11_13_11 [3] */
3975                 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
3976                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
3977                 /* IP11_10_8 [3] */
3978                 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
3979                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
3980                 /* IP11_7_6 [2] */
3981                 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
3982                 FN_CAN_DEBUGOUT13,
3983                 /* IP11_5_3 [3] */
3984                 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
3985                 FN_CAN_DEBUGOUT12, 0, 0, 0,
3986                 /* IP11_2_0 [3] */
3987                 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
3988                 FN_CAN_DEBUGOUT11, 0, 0, 0, }
3989         },
3990         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3991                              2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
3992                 /* IP12_31_30 [2] */
3993                 0, 0, 0, 0,
3994                 /* IP12_29_27 [3] */
3995                 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
3996                 FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
3997                 /* IP12_26_24 [3] */
3998                 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
3999                 FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
4000                 /* IP12_23_21 [3] */
4001                 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
4002                 FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
4003                 /* IP12_20_18 [3] */
4004                 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK,
4005                 FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
4006                 /* IP12_17_15 [3] */
4007                 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
4008                 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
4009                 /* IP12_14_13 [2] */
4010                 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK,
4011                 /* IP12_12_11 [2] */
4012                 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX,
4013                 /* IP12_10_9 [2] */
4014                 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX,
4015                 /* IP12_8_6 [3] */
4016                 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
4017                 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
4018                 /* IP12_5_3 [3] */
4019                 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
4020                 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
4021                 /* IP12_2_0 [3] */
4022                 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
4023                 FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, }
4024         },
4025         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4026                              1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4027                 /* IP13_31 [1] */
4028                 0, 0,
4029                 /* IP13_30 [1] */
4030                 0, 0,
4031                 /* IP13_29 [1] */
4032                 0, 0,
4033                 /* IP13_28 [1] */
4034                 0, 0,
4035                 /* IP13_27 [1] */
4036                 0, 0,
4037                 /* IP13_26_24 [3] */
4038                 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
4039                 FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D,
4040                 /* IP13_23_21 [3] */
4041                 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
4042                 FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D,
4043                 /* IP13_20_18 [3] */
4044                 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
4045                 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B,
4046                 /* IP13_17_15 [3] */
4047                 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
4048                 FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0,
4049                 /* IP13_14_12 [3] */
4050                 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
4051                 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
4052                 /* IP13_11_9 [3] */
4053                 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
4054                 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
4055                 /* IP13_8_6 [3] */
4056                 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
4057                 FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
4058                 /* IP13_5_3 [2] */
4059                 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
4060                 FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
4061                 /* IP13_2_0 [3] */
4062                 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
4063                 FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
4064         },
4065         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4066                              2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
4067                              2, 1) {
4068                 /* SEL_ADG [2] */
4069                 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
4070                 /* SEL_ADI [1] */
4071                 FN_SEL_ADI_0, FN_SEL_ADI_1,
4072                 /* SEL_CAN [2] */
4073                 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
4074                 /* SEL_DARC [3] */
4075                 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
4076                 FN_SEL_DARC_4, 0, 0, 0,
4077                 /* SEL_DR0 [1] */
4078                 FN_SEL_DR0_0, FN_SEL_DR0_1,
4079                 /* SEL_DR1 [1] */
4080                 FN_SEL_DR1_0, FN_SEL_DR1_1,
4081                 /* SEL_DR2 [1] */
4082                 FN_SEL_DR2_0, FN_SEL_DR2_1,
4083                 /* SEL_DR3 [1] */
4084                 FN_SEL_DR3_0, FN_SEL_DR3_1,
4085                 /* SEL_ETH [1] */
4086                 FN_SEL_ETH_0, FN_SEL_ETH_1,
4087                 /* SLE_FSN [1] */
4088                 FN_SEL_FSN_0, FN_SEL_FSN_1,
4089                 /* SEL_IC200 [3] */
4090                 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
4091                 FN_SEL_I2C00_4, 0, 0, 0,
4092                 /* SEL_I2C01 [3] */
4093                 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
4094                 FN_SEL_I2C01_4, 0, 0, 0,
4095                 /* SEL_I2C02 [3] */
4096                 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
4097                 FN_SEL_I2C02_4, 0, 0, 0,
4098                 /* SEL_I2C03 [3] */
4099                 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
4100                 FN_SEL_I2C03_4, 0, 0, 0,
4101                 /* SEL_I2C04 [3] */
4102                 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
4103                 FN_SEL_I2C04_4, 0, 0, 0,
4104                 /* SEL_IIC00 [2] */
4105                 FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
4106                 /* SEL_AVB [1] */
4107                 FN_SEL_AVB_0, FN_SEL_AVB_1, }
4108         },
4109         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4110                              2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
4111                              2, 2, 2, 1, 1, 2) {
4112                 /* SEL_IEB [2] */
4113                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
4114                 /* SEL_IIC0 [2] */
4115                 FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
4116                 /* SEL_LBS [1] */
4117                 FN_SEL_LBS_0, FN_SEL_LBS_1,
4118                 /* SEL_MSI1 [1] */
4119                 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
4120                 /* SEL_MSI2 [1] */
4121                 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
4122                 /* SEL_RAD [1] */
4123                 FN_SEL_RAD_0, FN_SEL_RAD_1,
4124                 /* SEL_RCN [1] */
4125                 FN_SEL_RCN_0, FN_SEL_RCN_1,
4126                 /* SEL_RSP [1] */
4127                 FN_SEL_RSP_0, FN_SEL_RSP_1,
4128                 /* SEL_SCIFA0 [2] */
4129                 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
4130                 FN_SEL_SCIFA0_3,
4131                 /* SEL_SCIFA1 [2] */
4132                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4133                 /* SEL_SCIFA2 [1] */
4134                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4135                 /* SEL_SCIFA3 [1] */
4136                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
4137                 /* SEL_SCIFA4 [2] */
4138                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
4139                 FN_SEL_SCIFA4_3,
4140                 /* SEL_SCIFA5 [2] */
4141                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
4142                 FN_SEL_SCIFA5_3,
4143                 /* SEL_SPDM [1] */
4144                 FN_SEL_SPDM_0, FN_SEL_SPDM_1,
4145                 /* SEL_TMU [1] */
4146                 FN_SEL_TMU_0, FN_SEL_TMU_1,
4147                 /* SEL_TSIF0 [2] */
4148                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4149                 /* SEL_CAN0 [2] */
4150                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4151                 /* SEL_CAN1 [2] */
4152                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
4153                 /* SEL_HSCIF0 [1] */
4154                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
4155                 /* SEL_HSCIF1 [1] */
4156                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
4157                 /* SEL_RDS [2] */
4158                 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
4159         },
4160         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4161                              2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4162                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
4163                 /* SEL_SCIF0 [2] */
4164                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
4165                 /* SEL_SCIF1 [2] */
4166                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
4167                 /* SEL_SCIF2 [2] */
4168                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
4169                 /* SEL_SCIF3 [1] */
4170                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
4171                 /* SEL_SCIF4 [3] */
4172                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
4173                 FN_SEL_SCIF4_4, 0, 0, 0,
4174                 /* SEL_SCIF5 [2] */
4175                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
4176                 /* SEL_SSI1 [1] */
4177                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
4178                 /* SEL_SSI2 [1] */
4179                 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
4180                 /* SEL_SSI4 [1] */
4181                 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
4182                 /* SEL_SSI5 [1] */
4183                 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
4184                 /* SEL_SSI6 [1] */
4185                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
4186                 /* SEL_SSI7 [1] */
4187                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
4188                 /* SEL_SSI8 [1] */
4189                 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
4190                 /* SEL_SSI9 [1] */
4191                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
4192                 /* RESERVED [1] */
4193                 0, 0,
4194                 /* RESERVED [1] */
4195                 0, 0,
4196                 /* RESERVED [1] */
4197                 0, 0,
4198                 /* RESERVED [1] */
4199                 0, 0,
4200                 /* RESERVED [1] */
4201                 0, 0,
4202                 /* RESERVED [1] */
4203                 0, 0,
4204                 /* RESERVED [1] */
4205                 0, 0,
4206                 /* RESERVED [1] */
4207                 0, 0,
4208                 /* RESERVED [1] */
4209                 0, 0,
4210                 /* RESERVED [1] */
4211                 0, 0,
4212                 /* RESERVED [1] */
4213                 0, 0,
4214                 /* RESERVED [1] */
4215                 0, 0, }
4216         },
4217         { },
4218 };
4219
4220 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
4221         .name = "r8a77940_pfc",
4222         .unlock_reg = 0xe6060000, /* PMMR */
4223
4224         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4225
4226         .pins = pinmux_pins,
4227         .nr_pins = ARRAY_SIZE(pinmux_pins),
4228         .groups = pinmux_groups,
4229         .nr_groups = ARRAY_SIZE(pinmux_groups),
4230         .functions = pinmux_functions,
4231         .nr_functions = ARRAY_SIZE(pinmux_functions),
4232
4233         .cfg_regs = pinmux_config_regs,
4234
4235         .gpio_data = pinmux_data,
4236         .gpio_data_size = ARRAY_SIZE(pinmux_data),
4237 };