2 * R-Car Gen3 processor support - PFC hardware block.
4 * Copyright (C) 2015 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
11 #include <linux/kernel.h>
16 #define PORT_GP_3(bank, fn, sfx) \
17 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
18 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx)
20 #define PORT_GP_14(bank, fn, sfx) \
21 PORT_GP_3(bank, fn, sfx), \
22 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
23 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
24 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
25 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
26 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
27 PORT_GP_1(bank, 14, fn, sfx)
29 #define PORT_GP_15(bank, fn, sfx) \
30 PORT_GP_14(bank, fn, sfx), PORT_GP_1(bank, 15, fn, sfx)
32 #define PORT_GP_17(bank, fn, sfx) \
33 PORT_GP_15(bank, fn, sfx), \
34 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx)
36 #define PORT_GP_25(bank, fn, sfx) \
37 PORT_GP_17(bank, fn, sfx), \
38 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
39 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
40 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
41 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
43 #define PORT_GP_27(bank, fn, sfx) \
44 PORT_GP_25(bank, fn, sfx), \
45 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx)
47 #define CPU_ALL_PORT(fn, sfx) \
48 PORT_GP_15(0, fn, sfx), \
49 PORT_GP_27(1, fn, sfx), \
50 PORT_GP_14(2, fn, sfx), \
51 PORT_GP_15(3, fn, sfx), \
52 PORT_GP_17(4, fn, sfx), \
53 PORT_GP_25(5, fn, sfx), \
54 PORT_GP_32(6, fn, sfx), \
57 * F_() : just information
58 * FM() : macro for FN_xxx / xxx_MARK
62 #define GPSR0_15 F_(D15, IP7_11_8)
63 #define GPSR0_14 F_(D14, IP7_7_4)
64 #define GPSR0_13 F_(D13, IP7_3_0)
65 #define GPSR0_12 F_(D12, IP6_31_28)
66 #define GPSR0_11 F_(D11, IP6_27_24)
67 #define GPSR0_10 F_(D10, IP6_23_20)
68 #define GPSR0_9 F_(D9, IP6_19_16)
69 #define GPSR0_8 F_(D8, IP6_15_12)
70 #define GPSR0_7 F_(D7, IP6_11_8)
71 #define GPSR0_6 F_(D6, IP6_7_4)
72 #define GPSR0_5 F_(D5, IP6_3_0)
73 #define GPSR0_4 F_(D4, IP5_31_28)
74 #define GPSR0_3 F_(D3, IP5_27_24)
75 #define GPSR0_2 F_(D2, IP5_23_20)
76 #define GPSR0_1 F_(D1, IP5_19_16)
77 #define GPSR0_0 F_(D0, IP5_15_12)
80 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
81 #define GPSR1_26 F_(WE1_N, IP5_7_4)
82 #define GPSR1_25 F_(WE0_N, IP5_3_0)
83 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
84 #define GPSR1_23 F_(RD_N, IP4_27_24)
85 #define GPSR1_22 F_(BS_N, IP4_23_20)
86 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
87 #define GPSR1_20 F_(CS0_N, IP4_15_12)
88 #define GPSR1_19 F_(A19, IP4_11_8)
89 #define GPSR1_18 F_(A18, IP4_7_4)
90 #define GPSR1_17 F_(A17, IP4_3_0)
91 #define GPSR1_16 F_(A16, IP3_31_28)
92 #define GPSR1_15 F_(A15, IP3_27_24)
93 #define GPSR1_14 F_(A14, IP3_23_20)
94 #define GPSR1_13 F_(A13, IP3_19_16)
95 #define GPSR1_12 F_(A12, IP3_15_12)
96 #define GPSR1_11 F_(A11, IP3_11_8)
97 #define GPSR1_10 F_(A10, IP3_7_4)
98 #define GPSR1_9 F_(A9, IP3_3_0)
99 #define GPSR1_8 F_(A8, IP2_31_28)
100 #define GPSR1_7 F_(A7, IP2_27_24)
101 #define GPSR1_6 F_(A6, IP2_23_20)
102 #define GPSR1_5 F_(A5, IP2_19_16)
103 #define GPSR1_4 F_(A4, IP2_15_12)
104 #define GPSR1_3 F_(A3, IP2_11_8)
105 #define GPSR1_2 F_(A2, IP2_7_4)
106 #define GPSR1_1 F_(A1, IP2_3_0)
107 #define GPSR1_0 F_(A0, IP1_31_28)
110 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
111 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
112 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
113 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
114 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
115 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
116 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
117 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
118 #define GPSR2_6 F_(PWM0, IP1_19_16)
119 #define GPSR2_5 F_(IRQ5, IP1_15_12)
120 #define GPSR2_4 F_(IRQ4, IP1_11_8)
121 #define GPSR2_3 F_(IRQ3, IP1_7_4)
122 #define GPSR2_2 F_(IRQ2, IP1_3_0)
123 #define GPSR2_1 F_(IRQ1, IP0_31_28)
124 #define GPSR2_0 F_(IRQ0, IP0_27_24)
127 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
128 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
129 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
130 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
131 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
132 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
133 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
134 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
135 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
136 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
137 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
138 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
139 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
140 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
141 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
142 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
145 #define GPSR4_17 FM(SD3_DS)
146 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
147 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
148 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
149 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
150 #define GPSR4_12 FM(SD3_DAT3)
151 #define GPSR4_11 FM(SD3_DAT2)
152 #define GPSR4_10 FM(SD3_DAT1)
153 #define GPSR4_9 FM(SD3_DAT0)
154 #define GPSR4_8 FM(SD3_CMD)
155 #define GPSR4_7 FM(SD3_CLK)
156 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
157 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
158 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
159 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
160 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
161 #define GPSR4_1 FM(SD2_CMD)
162 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
165 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
166 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
167 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
168 #define GPSR5_22 FM(MSIOF0_RXD)
169 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
170 #define GPSR5_20 FM(MSIOF0_TXD)
171 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
172 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
173 #define GPSR5_17 FM(MSIOF0_SCK)
174 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
175 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
176 #define GPSR5_14 F_(HTX0, IP12_19_16)
177 #define GPSR5_13 F_(HRX0, IP12_15_12)
178 #define GPSR5_12 F_(HSCK0, IP12_11_8)
179 #define GPSR5_11 F_(RX2_A, IP12_7_4)
180 #define GPSR5_10 F_(TX2_A, IP12_3_0)
181 #define GPSR5_9 F_(SCK2, IP11_31_28)
182 #define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
183 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
184 #define GPSR5_6 F_(TX1_A, IP11_19_16)
185 #define GPSR5_5 F_(RX1_A, IP11_15_12)
186 #define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
187 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
188 #define GPSR5_2 F_(TX0, IP11_3_0)
189 #define GPSR5_1 F_(RX0, IP10_31_28)
190 #define GPSR5_0 F_(SCK0, IP10_27_24)
193 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
194 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
195 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
196 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
197 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
198 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
199 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
200 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
201 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
202 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
203 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
204 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
205 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
206 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
207 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
208 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
209 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
210 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
211 #define GPSR6_13 FM(SSI_SDATA5)
212 #define GPSR6_12 FM(SSI_WS5)
213 #define GPSR6_11 FM(SSI_SCK5)
214 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
215 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
216 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
217 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
218 #define GPSR6_6 F_(SSI_WS34, IP14_15_12)
219 #define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
220 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
221 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
222 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
223 #define GPSR6_1 F_(SSI_WS0129, IP13_27_24)
224 #define GPSR6_0 F_(SSI_SCK0129, IP13_23_20)
227 #define GPSR7_3 FM(HDMI1_CEC)
228 #define GPSR7_2 FM(HDMI0_CEC)
229 #define GPSR7_1 FM(AVS2)
230 #define GPSR7_0 FM(AVS1)
233 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
234 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
255 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
299 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
343 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP13_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP13_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define PINMUX_GPSR \
387 GPSR1_25 GPSR5_25 GPSR6_25 \
388 GPSR1_24 GPSR5_24 GPSR6_24 \
389 GPSR1_23 GPSR5_23 GPSR6_23 \
390 GPSR1_22 GPSR5_22 GPSR6_22 \
391 GPSR1_21 GPSR5_21 GPSR6_21 \
392 GPSR1_20 GPSR5_20 GPSR6_20 \
393 GPSR1_19 GPSR5_19 GPSR6_19 \
394 GPSR1_18 GPSR5_18 GPSR6_18 \
395 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
396 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
397 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
398 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
399 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
400 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
401 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
402 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
403 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
404 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
405 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
406 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
407 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
408 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
409 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
410 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
411 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
412 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
414 #define PINMUX_IPSR \
416 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
417 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
418 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
419 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
420 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
421 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
422 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
423 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
425 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
426 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
427 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
428 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
429 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
430 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
431 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
432 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
434 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
435 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
436 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
437 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
438 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
439 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
440 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
441 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
443 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
444 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
445 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
446 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
447 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
448 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
449 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
450 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
452 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
453 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
454 FM(IP16_11_8) IP16_11_8 \
455 FM(IP16_15_12) IP16_15_12 \
456 FM(IP16_19_16) IP16_19_16 \
457 FM(IP16_23_20) IP16_23_20 \
458 FM(IP16_27_24) IP16_27_24 \
459 FM(IP16_31_28) IP16_31_28
461 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
462 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
463 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
464 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
465 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
466 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
467 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
468 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
469 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
470 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
471 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
472 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
473 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
474 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
475 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
476 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
477 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
478 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
479 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
480 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
481 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
482 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
484 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
485 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
486 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
487 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
488 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
489 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
490 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
491 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
492 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
493 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
494 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
495 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
496 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
497 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
498 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
499 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
500 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
501 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
502 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
503 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
504 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
505 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
506 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
508 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
509 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
510 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
511 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
512 #define MOD_SEL2_2_1 FM(SEL_VSP_0) FM(SEL_VSP_1) FM(SEL_VSP_2) FM(SEL_VSP_3)
513 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
515 #define PINMUX_MOD_SELS\
517 MOD_SEL1_31_30 MOD_SEL2_31 \
518 MOD_SEL0_30_29 MOD_SEL2_30 \
519 MOD_SEL1_29_28_27 MOD_SEL2_29 \
522 MOD_SEL0_26_25_24 MOD_SEL1_26 \
525 MOD_SEL0_23 MOD_SEL1_23_22_21 \
529 MOD_SEL0_19 MOD_SEL1_19 \
530 MOD_SEL0_18 MOD_SEL1_18_17 \
532 MOD_SEL0_16_15 MOD_SEL1_16 \
535 MOD_SEL0_13 MOD_SEL1_13 \
536 MOD_SEL0_12 MOD_SEL1_12 \
537 MOD_SEL0_11 MOD_SEL1_11 \
538 MOD_SEL0_10 MOD_SEL1_10 \
539 MOD_SEL0_9 MOD_SEL1_9 \
543 MOD_SEL0_5_4 MOD_SEL1_5 \
545 MOD_SEL0_3 MOD_SEL1_3 \
546 MOD_SEL0_2_1 MOD_SEL1_2 MOD_SEL2_2_1 \
548 MOD_SEL1_0 MOD_SEL2_0
559 #define FM(x) FN_##x,
560 PINMUX_FUNCTION_BEGIN,
570 #define FM(x) x##_MARK,
580 static const u16 pinmux_data[] = {
581 PINMUX_DATA_GP_ALL(),
584 PINMUX_IPSR_DATA(IP0_3_0, AVB_MDC),
585 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
587 PINMUX_IPSR_DATA(IP0_7_4, AVB_MAGIC),
588 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
589 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
591 PINMUX_IPSR_DATA(IP0_11_8, AVB_PHY_INT),
592 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
593 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
595 PINMUX_IPSR_DATA(IP0_15_12, AVB_LINK),
596 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
597 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
599 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
600 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
601 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
603 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
604 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
605 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
607 PINMUX_IPSR_DATA(IP0_27_24, IRQ0),
608 PINMUX_IPSR_DATA(IP0_27_24, QPOLB),
609 PINMUX_IPSR_DATA(IP0_27_24, DU_CDE),
610 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
611 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
612 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
614 PINMUX_IPSR_DATA(IP0_31_28, IRQ1),
615 PINMUX_IPSR_DATA(IP0_31_28, QPOLA),
616 PINMUX_IPSR_DATA(IP0_31_28, DU_DISP),
617 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
618 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
619 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
622 PINMUX_IPSR_DATA(IP1_3_0, IRQ2),
623 PINMUX_IPSR_DATA(IP1_3_0, QCPV_QDE),
624 PINMUX_IPSR_DATA(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
625 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
626 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
628 PINMUX_IPSR_DATA(IP1_7_4, IRQ3),
629 PINMUX_IPSR_DATA(IP1_7_4, QSTVB_QVE),
630 PINMUX_IPSR_DATA(IP1_7_4, A25),
631 PINMUX_IPSR_DATA(IP1_7_4, DU_DOTCLKOUT1),
632 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
635 PINMUX_IPSR_DATA(IP1_11_8, IRQ4),
636 PINMUX_IPSR_DATA(IP1_11_8, QSTH_QHS),
637 PINMUX_IPSR_DATA(IP1_11_8, A24),
638 PINMUX_IPSR_DATA(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
639 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
640 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
642 PINMUX_IPSR_DATA(IP1_15_12, IRQ5),
643 PINMUX_IPSR_DATA(IP1_15_12, QSTB_QHE),
644 PINMUX_IPSR_DATA(IP1_15_12, A23),
645 PINMUX_IPSR_DATA(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
646 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
647 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
649 PINMUX_IPSR_DATA(IP1_19_16, PWM0),
650 PINMUX_IPSR_DATA(IP1_19_16, AVB_AVTP_PPS),
651 PINMUX_IPSR_DATA(IP1_19_16, A22),
652 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
653 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
655 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
656 PINMUX_IPSR_DATA(IP1_23_20, A21),
657 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
658 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
659 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
661 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
662 PINMUX_IPSR_DATA(IP1_27_24, A20),
663 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
664 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
666 PINMUX_IPSR_DATA(IP1_31_28, A0),
667 PINMUX_IPSR_DATA(IP1_31_28, LCDOUT16),
668 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
669 PINMUX_IPSR_DATA(IP1_31_28, VI4_DATA8),
670 PINMUX_IPSR_DATA(IP1_31_28, DU_DB0),
671 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
674 PINMUX_IPSR_DATA(IP2_3_0, A1),
675 PINMUX_IPSR_DATA(IP2_3_0, LCDOUT17),
676 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
677 PINMUX_IPSR_DATA(IP2_3_0, VI4_DATA9),
678 PINMUX_IPSR_DATA(IP2_3_0, DU_DB1),
679 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
681 PINMUX_IPSR_DATA(IP2_7_4, A2),
682 PINMUX_IPSR_DATA(IP2_7_4, LCDOUT18),
683 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
684 PINMUX_IPSR_DATA(IP2_7_4, VI4_DATA10),
685 PINMUX_IPSR_DATA(IP2_7_4, DU_DB2),
686 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
688 PINMUX_IPSR_DATA(IP2_11_8, A3),
689 PINMUX_IPSR_DATA(IP2_11_8, LCDOUT19),
690 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
691 PINMUX_IPSR_DATA(IP2_11_8, VI4_DATA11),
692 PINMUX_IPSR_DATA(IP2_11_8, DU_DB3),
693 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
695 PINMUX_IPSR_DATA(IP2_15_12, A4),
696 PINMUX_IPSR_DATA(IP2_15_12, LCDOUT20),
697 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
698 PINMUX_IPSR_DATA(IP2_15_12, VI4_DATA12),
699 PINMUX_IPSR_DATA(IP2_15_12, VI5_DATA12),
700 PINMUX_IPSR_DATA(IP2_15_12, DU_DB4),
702 PINMUX_IPSR_DATA(IP2_19_16, A5),
703 PINMUX_IPSR_DATA(IP2_19_16, LCDOUT21),
704 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
705 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
706 PINMUX_IPSR_DATA(IP2_19_16, VI4_DATA13),
707 PINMUX_IPSR_DATA(IP2_19_16, VI5_DATA13),
708 PINMUX_IPSR_DATA(IP2_19_16, DU_DB5),
710 PINMUX_IPSR_DATA(IP2_23_20, A6),
711 PINMUX_IPSR_DATA(IP2_23_20, LCDOUT22),
712 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
713 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
714 PINMUX_IPSR_DATA(IP2_23_20, VI4_DATA14),
715 PINMUX_IPSR_DATA(IP2_23_20, VI5_DATA14),
716 PINMUX_IPSR_DATA(IP2_23_20, DU_DB6),
718 PINMUX_IPSR_DATA(IP2_27_24, A7),
719 PINMUX_IPSR_DATA(IP2_27_24, LCDOUT23),
720 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
721 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
722 PINMUX_IPSR_DATA(IP2_27_24, VI4_DATA15),
723 PINMUX_IPSR_DATA(IP2_27_24, VI5_DATA15),
724 PINMUX_IPSR_DATA(IP2_27_24, DU_DB7),
726 PINMUX_IPSR_DATA(IP2_31_28, A8),
727 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
728 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
729 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
730 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
731 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
732 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
735 PINMUX_IPSR_DATA(IP3_3_0, A9),
736 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
738 PINMUX_IPSR_DATA(IP3_3_0, VI5_VSYNC_N),
740 PINMUX_IPSR_DATA(IP3_7_4, A10),
741 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
743 PINMUX_IPSR_DATA(IP3_7_4, VI5_HSYNC_N),
745 PINMUX_IPSR_DATA(IP3_11_8, A11),
746 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
747 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
749 PINMUX_IPSR_DATA(IP3_11_8, HSCK4),
750 PINMUX_IPSR_DATA(IP3_11_8, VI5_FIELD),
751 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
752 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
753 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
755 PINMUX_IPSR_DATA(IP3_15_12, A12),
756 PINMUX_IPSR_DATA(IP3_15_12, LCDOUT12),
757 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
758 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
759 PINMUX_IPSR_DATA(IP3_15_12, VI5_DATA8),
760 PINMUX_IPSR_DATA(IP3_15_12, DU_DG4),
762 PINMUX_IPSR_DATA(IP3_19_16, A13),
763 PINMUX_IPSR_DATA(IP3_19_16, LCDOUT13),
764 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
765 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
766 PINMUX_IPSR_DATA(IP3_19_16, VI5_DATA9),
767 PINMUX_IPSR_DATA(IP3_19_16, DU_DG5),
769 PINMUX_IPSR_DATA(IP3_23_20, A14),
770 PINMUX_IPSR_DATA(IP3_23_20, LCDOUT14),
771 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
772 PINMUX_IPSR_DATA(IP3_23_20, HCTS4_N),
773 PINMUX_IPSR_DATA(IP3_23_20, VI5_DATA10),
774 PINMUX_IPSR_DATA(IP3_23_20, DU_DG6),
776 PINMUX_IPSR_DATA(IP3_27_24, A15),
777 PINMUX_IPSR_DATA(IP3_27_24, LCDOUT15),
778 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
779 PINMUX_IPSR_DATA(IP3_27_24, HRTS4_N),
780 PINMUX_IPSR_DATA(IP3_27_24, VI5_DATA11),
781 PINMUX_IPSR_DATA(IP3_27_24, DU_DG7),
783 PINMUX_IPSR_DATA(IP3_31_28, A16),
784 PINMUX_IPSR_DATA(IP3_31_28, LCDOUT8),
785 PINMUX_IPSR_DATA(IP3_31_28, VI4_FIELD),
786 PINMUX_IPSR_DATA(IP3_31_28, DU_DG0),
789 PINMUX_IPSR_DATA(IP4_3_0, A17),
790 PINMUX_IPSR_DATA(IP4_3_0, LCDOUT9),
791 PINMUX_IPSR_DATA(IP4_3_0, VI4_VSYNC_N),
792 PINMUX_IPSR_DATA(IP4_3_0, DU_DG1),
794 PINMUX_IPSR_DATA(IP4_7_4, A18),
795 PINMUX_IPSR_DATA(IP4_7_4, LCDOUT10),
796 PINMUX_IPSR_DATA(IP4_7_4, VI4_HSYNC_N),
797 PINMUX_IPSR_DATA(IP4_7_4, DU_DG2),
799 PINMUX_IPSR_DATA(IP4_11_8, A19),
800 PINMUX_IPSR_DATA(IP4_11_8, LCDOUT11),
801 PINMUX_IPSR_DATA(IP4_11_8, VI4_CLKENB),
802 PINMUX_IPSR_DATA(IP4_11_8, DU_DG3),
804 PINMUX_IPSR_DATA(IP4_15_12, CS0_N),
805 PINMUX_IPSR_DATA(IP4_15_12, VI5_CLKENB),
807 PINMUX_IPSR_DATA(IP4_19_16, CS1_N_A26),
808 PINMUX_IPSR_DATA(IP4_19_16, VI5_CLK),
809 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
811 PINMUX_IPSR_DATA(IP4_23_20, BS_N),
812 PINMUX_IPSR_DATA(IP4_23_20, QSTVA_QVS),
813 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
814 PINMUX_IPSR_DATA(IP4_23_20, SCK3),
815 PINMUX_IPSR_DATA(IP4_23_20, HSCK3),
816 PINMUX_IPSR_DATA(IP4_23_20, CAN1_TX),
817 PINMUX_IPSR_DATA(IP4_23_20, CANFD1_TX),
818 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
820 PINMUX_IPSR_DATA(IP4_27_24, RD_N),
821 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
822 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
823 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
824 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
825 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
827 PINMUX_IPSR_DATA(IP4_31_28, RD_WR_N),
828 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
829 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
830 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
831 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
832 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
835 PINMUX_IPSR_DATA(IP5_3_0, WE0_N),
836 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
837 PINMUX_IPSR_DATA(IP5_3_0, CTS3_N),
838 PINMUX_IPSR_DATA(IP5_3_0, HCTS3_N),
839 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
840 PINMUX_IPSR_DATA(IP5_3_0, CAN_CLK),
841 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
843 PINMUX_IPSR_DATA(IP5_7_4, WE1_N),
844 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
845 PINMUX_IPSR_DATA(IP5_7_4, RTS3_N_TANS),
846 PINMUX_IPSR_DATA(IP5_7_4, HRTS3_N),
847 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
848 PINMUX_IPSR_DATA(IP5_7_4, CAN1_RX),
849 PINMUX_IPSR_DATA(IP5_7_4, CANFD1_RX),
850 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
852 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
853 PINMUX_IPSR_DATA(IP5_11_8, QCLK),
854 PINMUX_IPSR_DATA(IP5_11_8, VI4_CLK),
855 PINMUX_IPSR_DATA(IP5_11_8, DU_DOTCLKOUT0),
857 PINMUX_IPSR_DATA(IP5_15_12, D0),
858 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
859 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
860 PINMUX_IPSR_DATA(IP5_15_12, VI4_DATA16),
861 PINMUX_IPSR_DATA(IP5_15_12, VI5_DATA0),
863 PINMUX_IPSR_DATA(IP5_19_16, D1),
864 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
865 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
866 PINMUX_IPSR_DATA(IP5_19_16, VI4_DATA17),
867 PINMUX_IPSR_DATA(IP5_19_16, VI5_DATA1),
869 PINMUX_IPSR_DATA(IP5_23_20, D2),
870 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
871 PINMUX_IPSR_DATA(IP5_23_20, VI4_DATA18),
872 PINMUX_IPSR_DATA(IP5_23_20, VI5_DATA2),
874 PINMUX_IPSR_DATA(IP5_27_24, D3),
875 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
876 PINMUX_IPSR_DATA(IP5_27_24, VI4_DATA19),
877 PINMUX_IPSR_DATA(IP5_27_24, VI5_DATA3),
879 PINMUX_IPSR_DATA(IP5_31_28, D4),
880 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
881 PINMUX_IPSR_DATA(IP5_31_28, VI4_DATA20),
882 PINMUX_IPSR_DATA(IP5_31_28, VI5_DATA4),
885 PINMUX_IPSR_DATA(IP6_3_0, D5),
886 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
887 PINMUX_IPSR_DATA(IP6_3_0, VI4_DATA21),
888 PINMUX_IPSR_DATA(IP6_3_0, VI5_DATA5),
890 PINMUX_IPSR_DATA(IP6_7_4, D6),
891 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_DATA(IP6_7_4, VI4_DATA22),
893 PINMUX_IPSR_DATA(IP6_7_4, VI5_DATA6),
895 PINMUX_IPSR_DATA(IP6_11_8, D7),
896 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
897 PINMUX_IPSR_DATA(IP6_11_8, VI4_DATA23),
898 PINMUX_IPSR_DATA(IP6_11_8, VI5_DATA7),
900 PINMUX_IPSR_DATA(IP6_15_12, D8),
901 PINMUX_IPSR_DATA(IP6_15_12, LCDOUT0),
902 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
903 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
904 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
905 PINMUX_IPSR_DATA(IP6_15_12, DU_DR0),
907 PINMUX_IPSR_DATA(IP6_19_16, D9),
908 PINMUX_IPSR_DATA(IP6_19_16, LCDOUT1),
909 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
910 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
911 PINMUX_IPSR_DATA(IP6_19_16, DU_DR1),
913 PINMUX_IPSR_DATA(IP6_23_20, D10),
914 PINMUX_IPSR_DATA(IP6_23_20, LCDOUT2),
915 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
916 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
917 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
918 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
919 PINMUX_IPSR_DATA(IP6_23_20, DU_DR2),
921 PINMUX_IPSR_DATA(IP6_27_24, D11),
922 PINMUX_IPSR_DATA(IP6_27_24, LCDOUT3),
923 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
924 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
925 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
926 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
927 PINMUX_IPSR_DATA(IP6_27_24, DU_DR3),
929 PINMUX_IPSR_DATA(IP6_31_28, D12),
930 PINMUX_IPSR_DATA(IP6_31_28, LCDOUT4),
931 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
933 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
934 PINMUX_IPSR_DATA(IP6_31_28, DU_DR4),
937 PINMUX_IPSR_DATA(IP7_3_0, D13),
938 PINMUX_IPSR_DATA(IP7_3_0, LCDOUT5),
939 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
941 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
942 PINMUX_IPSR_DATA(IP7_3_0, DU_DR5),
944 PINMUX_IPSR_DATA(IP7_7_4, D14),
945 PINMUX_IPSR_DATA(IP7_7_4, LCDOUT6),
946 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
947 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
948 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
949 PINMUX_IPSR_DATA(IP7_7_4, DU_DR6),
950 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
952 PINMUX_IPSR_DATA(IP7_11_8, D15),
953 PINMUX_IPSR_DATA(IP7_11_8, LCDOUT7),
954 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
955 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
956 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
957 PINMUX_IPSR_DATA(IP7_11_8, DU_DR7),
958 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
960 PINMUX_IPSR_DATA(IP7_15_12, FSCLKST),
962 PINMUX_IPSR_DATA(IP7_19_16, SD0_CLK),
963 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
964 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
966 PINMUX_IPSR_DATA(IP7_23_20, SD0_CMD),
967 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
968 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
970 PINMUX_IPSR_DATA(IP7_27_24, SD0_DAT0),
971 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
972 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
973 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
975 PINMUX_IPSR_DATA(IP7_31_28, SD0_DAT1),
976 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
977 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
978 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
981 PINMUX_IPSR_DATA(IP8_3_0, SD0_DAT2),
982 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
983 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
984 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
986 PINMUX_IPSR_DATA(IP8_7_4, SD0_DAT3),
987 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
988 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
989 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
991 PINMUX_IPSR_DATA(IP8_11_8, SD1_CLK),
992 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
993 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
995 PINMUX_IPSR_DATA(IP8_15_12, SD1_CMD),
996 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
997 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
998 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1000 PINMUX_IPSR_DATA(IP8_19_16, SD1_DAT0),
1001 PINMUX_IPSR_DATA(IP8_19_16, SD2_DAT4),
1002 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1003 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1004 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1006 PINMUX_IPSR_DATA(IP8_23_20, SD1_DAT1),
1007 PINMUX_IPSR_DATA(IP8_23_20, SD2_DAT5),
1008 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1009 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1010 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1012 PINMUX_IPSR_DATA(IP8_27_24, SD1_DAT2),
1013 PINMUX_IPSR_DATA(IP8_27_24, SD2_DAT6),
1014 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1016 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1018 PINMUX_IPSR_DATA(IP8_31_28, SD1_DAT3),
1019 PINMUX_IPSR_DATA(IP8_31_28, SD2_DAT7),
1020 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1021 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1022 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1025 PINMUX_IPSR_DATA(IP9_3_0, SD2_CLK),
1027 PINMUX_IPSR_DATA(IP9_7_4, SD2_DAT0),
1029 PINMUX_IPSR_DATA(IP9_11_8, SD2_DAT1),
1031 PINMUX_IPSR_DATA(IP9_15_12, SD2_DAT2),
1033 PINMUX_IPSR_DATA(IP9_19_16, SD2_DAT3),
1035 PINMUX_IPSR_DATA(IP9_23_20, SD2_DS),
1036 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SCIF_1),
1038 PINMUX_IPSR_DATA(IP9_27_24, SD3_DAT4),
1039 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1041 PINMUX_IPSR_DATA(IP9_31_28, SD3_DAT5),
1042 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1045 PINMUX_IPSR_DATA(IP10_3_0, SD3_DAT6),
1046 PINMUX_IPSR_DATA(IP10_3_0, SD3_CD),
1048 PINMUX_IPSR_DATA(IP10_7_4, SD3_DAT7),
1049 PINMUX_IPSR_DATA(IP10_7_4, SD3_WP),
1051 PINMUX_IPSR_DATA(IP10_11_8, SD0_CD),
1052 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1053 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1055 PINMUX_IPSR_DATA(IP10_15_12, SD0_WP),
1056 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1058 PINMUX_IPSR_DATA(IP10_19_16, SD1_CD),
1059 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1061 PINMUX_IPSR_DATA(IP10_23_20, SD1_WP),
1062 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1064 PINMUX_IPSR_DATA(IP10_27_24, SCK0),
1065 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1066 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1067 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1068 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1069 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1070 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1071 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1072 PINMUX_IPSR_DATA(IP10_27_24, ADICHS2),
1074 PINMUX_IPSR_DATA(IP10_31_28, RX0),
1075 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1076 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1077 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1078 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1081 PINMUX_IPSR_DATA(IP11_3_0, TX0),
1082 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1083 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1084 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1085 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1087 PINMUX_IPSR_DATA(IP11_7_4, CTS0_N),
1088 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1089 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1090 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1091 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1092 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1093 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1094 PINMUX_IPSR_DATA(IP11_7_4, ADICS_SAMP),
1096 PINMUX_IPSR_DATA(IP11_11_8, RTS0_N_TANS),
1097 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1098 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1099 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1100 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1101 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1102 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1103 PINMUX_IPSR_DATA(IP11_11_8, ADICHS1),
1105 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1106 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1107 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1108 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1109 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1111 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1112 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1113 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1114 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1115 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1117 PINMUX_IPSR_DATA(IP11_23_20, CTS1_N),
1118 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1119 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1120 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1121 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1122 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1123 PINMUX_IPSR_DATA(IP11_23_20, ADIDATA),
1125 PINMUX_IPSR_DATA(IP11_27_24, RTS1_N_TANS),
1126 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1127 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1128 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1129 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1130 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1131 PINMUX_IPSR_DATA(IP11_27_24, ADICHS0),
1133 PINMUX_IPSR_DATA(IP11_31_28, SCK2),
1134 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1135 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1136 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1137 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1138 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1139 PINMUX_IPSR_DATA(IP11_31_28, ADICLK),
1142 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1143 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1144 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1145 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1146 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1147 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1149 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1150 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1151 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1152 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1153 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1154 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1156 PINMUX_IPSR_DATA(IP12_11_8, HSCK0),
1157 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1158 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1159 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1160 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1161 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1162 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1164 PINMUX_IPSR_DATA(IP12_15_12, HRX0),
1165 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1166 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1167 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1168 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1169 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1171 PINMUX_IPSR_DATA(IP12_19_16, HTX0),
1172 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1173 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1174 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1175 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1176 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1178 PINMUX_IPSR_DATA(IP12_23_20, HCTS0_N),
1179 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1180 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1181 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1182 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1183 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1185 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1187 PINMUX_IPSR_DATA(IP12_27_24, HRTS0_N),
1188 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1190 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1191 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1192 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1195 PINMUX_IPSR_DATA(IP12_31_28, MSIOF0_SYNC),
1196 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1199 PINMUX_IPSR_DATA(IP13_3_0, MSIOF0_SS1),
1200 PINMUX_IPSR_DATA(IP13_3_0, RX5),
1201 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1202 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1203 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1204 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1205 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1207 PINMUX_IPSR_DATA(IP13_7_4, MSIOF0_SS2),
1208 PINMUX_IPSR_DATA(IP13_7_4, TX5),
1209 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1210 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1211 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1212 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1213 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1214 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1216 PINMUX_IPSR_DATA(IP13_11_8, MLB_CLK),
1217 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1218 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1220 PINMUX_IPSR_DATA(IP13_15_12, MLB_SIG),
1221 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1222 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1223 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1225 PINMUX_IPSR_DATA(IP13_19_16, MLB_DAT),
1226 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1227 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1229 PINMUX_IPSR_DATA(IP13_23_20, SSI_SCK0129),
1230 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1232 PINMUX_IPSR_DATA(IP13_27_24, SSI_WS0129),
1233 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1235 PINMUX_IPSR_DATA(IP13_31_28, SSI_SDATA0),
1236 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1239 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1241 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1242 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1244 PINMUX_IPSR_DATA(IP14_11_8, SSI_SCK34),
1245 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1246 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1248 PINMUX_IPSR_DATA(IP14_15_12, SSI_WS34),
1249 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1250 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1251 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1253 PINMUX_IPSR_DATA(IP14_19_16, SSI_SDATA3),
1254 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1255 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1256 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1257 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1258 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1259 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1261 PINMUX_IPSR_DATA(IP14_23_20, SSI_SCK4),
1262 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1263 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1264 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1265 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1266 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1267 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1269 PINMUX_IPSR_DATA(IP14_27_24, SSI_WS4),
1270 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1271 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1272 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1273 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1274 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1275 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1277 PINMUX_IPSR_DATA(IP14_31_28, SSI_SDATA4),
1278 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1279 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1280 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1281 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1282 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1283 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1286 PINMUX_IPSR_DATA(IP15_3_0, SSI_SCK6),
1287 PINMUX_IPSR_DATA(IP15_3_0, USB2_PWEN),
1288 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1290 PINMUX_IPSR_DATA(IP15_7_4, SSI_WS6),
1291 PINMUX_IPSR_DATA(IP15_7_4, USB2_OVC),
1292 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1294 PINMUX_IPSR_DATA(IP15_11_8, SSI_SDATA6),
1295 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1296 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SCIF_0),
1298 PINMUX_IPSR_DATA(IP15_15_12, SSI_SCK78),
1299 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1300 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1301 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1302 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1303 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1304 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1306 PINMUX_IPSR_DATA(IP15_19_16, SSI_WS78),
1307 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1308 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1309 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1310 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1311 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1312 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1314 PINMUX_IPSR_DATA(IP15_23_20, SSI_SDATA7),
1315 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1316 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1317 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1318 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1319 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1320 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1321 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1323 PINMUX_IPSR_DATA(IP15_27_24, SSI_SDATA8),
1324 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1325 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1326 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1327 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1328 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1329 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1331 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1332 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1333 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1334 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1335 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1336 PINMUX_IPSR_DATA(IP15_31_28, SCK1),
1337 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1338 PINMUX_IPSR_DATA(IP15_31_28, SCK5),
1341 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1342 PINMUX_IPSR_DATA(IP16_3_0, CC5_OSCOUT),
1344 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1345 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1346 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1347 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1348 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1350 PINMUX_IPSR_DATA(IP16_11_8, USB0_PWEN),
1351 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1352 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1353 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1354 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1355 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1357 PINMUX_IPSR_DATA(IP16_15_12, USB0_OVC),
1358 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1359 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1360 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1361 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1363 PINMUX_IPSR_DATA(IP16_19_16, USB1_PWEN),
1364 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1365 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1366 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1367 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1368 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1369 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1372 PINMUX_IPSR_DATA(IP16_23_20, USB1_OVC),
1373 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1374 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1375 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1376 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1377 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1378 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1379 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1381 PINMUX_IPSR_DATA(IP16_27_24, USB30_PWEN),
1382 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1383 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1384 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1385 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1386 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1387 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1388 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1389 PINMUX_IPSR_DATA(IP16_27_24, TPU0TO0),
1391 PINMUX_IPSR_DATA(IP16_31_28, USB30_OVC),
1392 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1393 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1394 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1395 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1396 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1397 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1398 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1399 PINMUX_IPSR_DATA(IP16_31_28, TPU0TO1),
1402 PINMUX_IPSR_DATA(IP17_3_0, USB31_PWEN),
1403 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1404 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1405 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1406 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1407 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1408 PINMUX_IPSR_DATA(IP17_3_0, TPU0TO2),
1410 PINMUX_IPSR_DATA(IP17_7_4, USB31_OVC),
1411 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1412 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1413 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1414 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1415 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1416 PINMUX_IPSR_DATA(IP17_7_4, TPU0TO3),
1419 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1420 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1421 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1424 static const struct sh_pfc_pin pinmux_pins[] = {
1425 PINMUX_GPIO_GP_ALL(),
1428 /* - AUDIO CLOCK ------------------------------------------------------------ */
1429 static const unsigned int audio_clk_a_a_pins[] = {
1433 static const unsigned int audio_clk_a_a_mux[] = {
1436 static const unsigned int audio_clk_a_b_pins[] = {
1440 static const unsigned int audio_clk_a_b_mux[] = {
1443 static const unsigned int audio_clk_a_c_pins[] = {
1447 static const unsigned int audio_clk_a_c_mux[] = {
1450 static const unsigned int audio_clk_b_a_pins[] = {
1454 static const unsigned int audio_clk_b_a_mux[] = {
1457 static const unsigned int audio_clk_b_b_pins[] = {
1461 static const unsigned int audio_clk_b_b_mux[] = {
1464 static const unsigned int audio_clk_c_a_pins[] = {
1468 static const unsigned int audio_clk_c_a_mux[] = {
1471 static const unsigned int audio_clk_c_b_pins[] = {
1475 static const unsigned int audio_clk_c_b_mux[] = {
1478 static const unsigned int audio_clkout_a_pins[] = {
1482 static const unsigned int audio_clkout_a_mux[] = {
1483 AUDIO_CLKOUT_A_MARK,
1485 static const unsigned int audio_clkout_b_pins[] = {
1489 static const unsigned int audio_clkout_b_mux[] = {
1490 AUDIO_CLKOUT_B_MARK,
1492 static const unsigned int audio_clkout_c_pins[] = {
1496 static const unsigned int audio_clkout_c_mux[] = {
1497 AUDIO_CLKOUT_C_MARK,
1499 static const unsigned int audio_clkout_d_pins[] = {
1503 static const unsigned int audio_clkout_d_mux[] = {
1504 AUDIO_CLKOUT_D_MARK,
1506 static const unsigned int audio_clkout1_a_pins[] = {
1510 static const unsigned int audio_clkout1_a_mux[] = {
1511 AUDIO_CLKOUT1_A_MARK,
1513 static const unsigned int audio_clkout1_b_pins[] = {
1517 static const unsigned int audio_clkout1_b_mux[] = {
1518 AUDIO_CLKOUT1_B_MARK,
1520 static const unsigned int audio_clkout2_a_pins[] = {
1524 static const unsigned int audio_clkout2_a_mux[] = {
1525 AUDIO_CLKOUT2_A_MARK,
1527 static const unsigned int audio_clkout2_b_pins[] = {
1531 static const unsigned int audio_clkout2_b_mux[] = {
1532 AUDIO_CLKOUT2_B_MARK,
1535 static const unsigned int audio_clkout3_a_pins[] = {
1539 static const unsigned int audio_clkout3_a_mux[] = {
1540 AUDIO_CLKOUT3_A_MARK,
1542 static const unsigned int audio_clkout3_b_pins[] = {
1546 static const unsigned int audio_clkout3_b_mux[] = {
1547 AUDIO_CLKOUT3_B_MARK,
1550 /* - EtherAVB --------------------------------------------------------------- */
1551 static const unsigned int avb_link_pins[] = {
1555 static const unsigned int avb_link_mux[] = {
1558 static const unsigned int avb_magic_pins[] = {
1562 static const unsigned int avb_magic_mux[] = {
1565 static const unsigned int avb_phy_int_pins[] = {
1569 static const unsigned int avb_phy_int_mux[] = {
1572 static const unsigned int avb_mdc_pins[] = {
1576 static const unsigned int avb_mdc_mux[] = {
1579 static const unsigned int avb_avtp_pps_pins[] = {
1583 static const unsigned int avb_avtp_pps_mux[] = {
1586 static const unsigned int avb_avtp_match_a_pins[] = {
1587 /* AVB_AVTP_MATCH_A */
1590 static const unsigned int avb_avtp_match_a_mux[] = {
1591 AVB_AVTP_MATCH_A_MARK,
1593 static const unsigned int avb_avtp_capture_a_pins[] = {
1594 /* AVB_AVTP_CAPTURE_A */
1597 static const unsigned int avb_avtp_capture_a_mux[] = {
1598 AVB_AVTP_CAPTURE_A_MARK,
1600 static const unsigned int avb_avtp_match_b_pins[] = {
1601 /* AVB_AVTP_MATCH_B */
1604 static const unsigned int avb_avtp_match_b_mux[] = {
1605 AVB_AVTP_MATCH_B_MARK,
1607 static const unsigned int avb_avtp_capture_b_pins[] = {
1608 /* AVB_AVTP_CAPTURE_B */
1611 static const unsigned int avb_avtp_capture_b_mux[] = {
1612 AVB_AVTP_CAPTURE_B_MARK,
1615 /* - I2C -------------------------------------------------------------------- */
1616 static const unsigned int i2c1_a_pins[] = {
1618 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1620 static const unsigned int i2c1_a_mux[] = {
1621 SDA1_A_MARK, SCL1_A_MARK,
1623 static const unsigned int i2c1_b_pins[] = {
1625 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1627 static const unsigned int i2c1_b_mux[] = {
1628 SDA1_B_MARK, SCL1_B_MARK,
1630 static const unsigned int i2c2_a_pins[] = {
1632 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1634 static const unsigned int i2c2_a_mux[] = {
1635 SDA2_A_MARK, SCL2_A_MARK,
1637 static const unsigned int i2c2_b_pins[] = {
1639 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1641 static const unsigned int i2c2_b_mux[] = {
1642 SDA2_B_MARK, SCL2_B_MARK,
1644 static const unsigned int i2c6_a_pins[] = {
1646 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1648 static const unsigned int i2c6_a_mux[] = {
1649 SDA6_A_MARK, SCL6_A_MARK,
1651 static const unsigned int i2c6_b_pins[] = {
1653 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1655 static const unsigned int i2c6_b_mux[] = {
1656 SDA6_B_MARK, SCL6_B_MARK,
1658 static const unsigned int i2c6_c_pins[] = {
1660 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1662 static const unsigned int i2c6_c_mux[] = {
1663 SDA6_C_MARK, SCL6_C_MARK,
1666 /* - SCIF0 ------------------------------------------------------------------ */
1667 static const unsigned int scif0_data_pins[] = {
1669 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1671 static const unsigned int scif0_data_mux[] = {
1674 static const unsigned int scif0_clk_pins[] = {
1678 static const unsigned int scif0_clk_mux[] = {
1681 static const unsigned int scif0_ctrl_pins[] = {
1683 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1685 static const unsigned int scif0_ctrl_mux[] = {
1686 RTS0_N_TANS_MARK, CTS0_N_MARK,
1688 /* - SCIF1 ------------------------------------------------------------------ */
1689 static const unsigned int scif1_data_a_pins[] = {
1691 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1693 static const unsigned int scif1_data_a_mux[] = {
1694 RX1_A_MARK, TX1_A_MARK,
1696 static const unsigned int scif1_clk_pins[] = {
1700 static const unsigned int scif1_clk_mux[] = {
1703 static const unsigned int scif1_ctrl_pins[] = {
1705 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1707 static const unsigned int scif1_ctrl_mux[] = {
1708 RTS1_N_TANS_MARK, CTS1_N_MARK,
1711 static const unsigned int scif1_data_b_pins[] = {
1713 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1715 static const unsigned int scif1_data_b_mux[] = {
1716 RX1_B_MARK, TX1_B_MARK,
1718 /* - SCIF2 ------------------------------------------------------------------ */
1719 static const unsigned int scif2_data_a_pins[] = {
1721 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1723 static const unsigned int scif2_data_a_mux[] = {
1724 RX2_A_MARK, TX2_A_MARK,
1726 static const unsigned int scif2_clk_pins[] = {
1730 static const unsigned int scif2_clk_mux[] = {
1733 static const unsigned int scif2_data_b_pins[] = {
1735 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1737 static const unsigned int scif2_data_b_mux[] = {
1738 RX2_B_MARK, TX2_B_MARK,
1740 /* - SCIF3 ------------------------------------------------------------------ */
1741 static const unsigned int scif3_data_a_pins[] = {
1743 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1745 static const unsigned int scif3_data_a_mux[] = {
1746 RX3_A_MARK, TX3_A_MARK,
1748 static const unsigned int scif3_clk_pins[] = {
1752 static const unsigned int scif3_clk_mux[] = {
1755 static const unsigned int scif3_ctrl_pins[] = {
1757 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1759 static const unsigned int scif3_ctrl_mux[] = {
1760 RTS3_N_TANS_MARK, CTS3_N_MARK,
1762 static const unsigned int scif3_data_b_pins[] = {
1764 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1766 static const unsigned int scif3_data_b_mux[] = {
1767 RX3_B_MARK, TX3_B_MARK,
1769 /* - SCIF4 ------------------------------------------------------------------ */
1770 static const unsigned int scif4_data_a_pins[] = {
1772 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1774 static const unsigned int scif4_data_a_mux[] = {
1775 RX4_A_MARK, TX4_A_MARK,
1777 static const unsigned int scif4_clk_a_pins[] = {
1781 static const unsigned int scif4_clk_a_mux[] = {
1784 static const unsigned int scif4_ctrl_a_pins[] = {
1786 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1788 static const unsigned int scif4_ctrl_a_mux[] = {
1789 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1791 static const unsigned int scif4_data_b_pins[] = {
1793 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1795 static const unsigned int scif4_data_b_mux[] = {
1796 RX4_B_MARK, TX4_B_MARK,
1798 static const unsigned int scif4_clk_b_pins[] = {
1802 static const unsigned int scif4_clk_b_mux[] = {
1805 static const unsigned int scif4_ctrl_b_pins[] = {
1807 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1809 static const unsigned int scif4_ctrl_b_mux[] = {
1810 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1812 static const unsigned int scif4_data_c_pins[] = {
1814 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1816 static const unsigned int scif4_data_c_mux[] = {
1817 RX4_C_MARK, TX4_C_MARK,
1819 static const unsigned int scif4_clk_c_pins[] = {
1823 static const unsigned int scif4_clk_c_mux[] = {
1826 static const unsigned int scif4_ctrl_c_pins[] = {
1828 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1830 static const unsigned int scif4_ctrl_c_mux[] = {
1831 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1833 /* - SCIF5 ------------------------------------------------------------------ */
1834 static const unsigned int scif5_data_pins[] = {
1836 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1838 static const unsigned int scif5_data_mux[] = {
1841 static const unsigned int scif5_clk_pins[] = {
1845 static const unsigned int scif5_clk_mux[] = {
1849 /* - SSI -------------------------------------------------------------------- */
1850 static const unsigned int ssi0_data_pins[] = {
1854 static const unsigned int ssi0_data_mux[] = {
1857 static const unsigned int ssi01239_ctrl_pins[] = {
1859 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
1861 static const unsigned int ssi01239_ctrl_mux[] = {
1862 SSI_SCK0129_MARK, SSI_WS0129_MARK,
1864 static const unsigned int ssi1_data_a_pins[] = {
1868 static const unsigned int ssi1_data_a_mux[] = {
1871 static const unsigned int ssi1_data_b_pins[] = {
1875 static const unsigned int ssi1_data_b_mux[] = {
1878 static const unsigned int ssi1_ctrl_a_pins[] = {
1880 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1882 static const unsigned int ssi1_ctrl_a_mux[] = {
1883 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
1885 static const unsigned int ssi1_ctrl_b_pins[] = {
1887 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
1889 static const unsigned int ssi1_ctrl_b_mux[] = {
1890 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
1892 static const unsigned int ssi2_data_a_pins[] = {
1896 static const unsigned int ssi2_data_a_mux[] = {
1899 static const unsigned int ssi2_data_b_pins[] = {
1903 static const unsigned int ssi2_data_b_mux[] = {
1906 static const unsigned int ssi2_ctrl_a_pins[] = {
1908 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1910 static const unsigned int ssi2_ctrl_a_mux[] = {
1911 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
1913 static const unsigned int ssi2_ctrl_b_pins[] = {
1915 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1917 static const unsigned int ssi2_ctrl_b_mux[] = {
1918 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
1920 static const unsigned int ssi3_data_pins[] = {
1924 static const unsigned int ssi3_data_mux[] = {
1927 static const unsigned int ssi34_ctrl_pins[] = {
1929 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
1931 static const unsigned int ssi34_ctrl_mux[] = {
1932 SSI_SCK34_MARK, SSI_WS34_MARK,
1934 static const unsigned int ssi4_data_pins[] = {
1938 static const unsigned int ssi4_data_mux[] = {
1941 static const unsigned int ssi4_ctrl_pins[] = {
1943 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1945 static const unsigned int ssi4_ctrl_mux[] = {
1946 SSI_SCK4_MARK, SSI_WS4_MARK,
1948 static const unsigned int ssi5_data_pins[] = {
1952 static const unsigned int ssi5_data_mux[] = {
1955 static const unsigned int ssi5_ctrl_pins[] = {
1957 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1959 static const unsigned int ssi5_ctrl_mux[] = {
1960 SSI_SCK5_MARK, SSI_WS5_MARK,
1962 static const unsigned int ssi6_data_pins[] = {
1966 static const unsigned int ssi6_data_mux[] = {
1969 static const unsigned int ssi6_ctrl_pins[] = {
1971 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1973 static const unsigned int ssi6_ctrl_mux[] = {
1974 SSI_SCK6_MARK, SSI_WS6_MARK,
1976 static const unsigned int ssi7_data_pins[] = {
1980 static const unsigned int ssi7_data_mux[] = {
1983 static const unsigned int ssi78_ctrl_pins[] = {
1985 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1987 static const unsigned int ssi78_ctrl_mux[] = {
1988 SSI_SCK78_MARK, SSI_WS78_MARK,
1990 static const unsigned int ssi8_data_pins[] = {
1994 static const unsigned int ssi8_data_mux[] = {
1997 static const unsigned int ssi9_data_a_pins[] = {
2001 static const unsigned int ssi9_data_a_mux[] = {
2004 static const unsigned int ssi9_data_b_pins[] = {
2008 static const unsigned int ssi9_data_b_mux[] = {
2011 static const unsigned int ssi9_ctrl_a_pins[] = {
2013 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2015 static const unsigned int ssi9_ctrl_a_mux[] = {
2016 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
2018 static const unsigned int ssi9_ctrl_b_pins[] = {
2020 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
2022 static const unsigned int ssi9_ctrl_b_mux[] = {
2023 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
2026 static const struct sh_pfc_pin_group pinmux_groups[] = {
2027 SH_PFC_PIN_GROUP(audio_clk_a_a),
2028 SH_PFC_PIN_GROUP(audio_clk_a_b),
2029 SH_PFC_PIN_GROUP(audio_clk_a_c),
2030 SH_PFC_PIN_GROUP(audio_clk_b_a),
2031 SH_PFC_PIN_GROUP(audio_clk_b_b),
2032 SH_PFC_PIN_GROUP(audio_clk_c_a),
2033 SH_PFC_PIN_GROUP(audio_clk_c_b),
2034 SH_PFC_PIN_GROUP(audio_clkout_a),
2035 SH_PFC_PIN_GROUP(audio_clkout_b),
2036 SH_PFC_PIN_GROUP(audio_clkout_c),
2037 SH_PFC_PIN_GROUP(audio_clkout_d),
2038 SH_PFC_PIN_GROUP(audio_clkout1_a),
2039 SH_PFC_PIN_GROUP(audio_clkout1_b),
2040 SH_PFC_PIN_GROUP(audio_clkout2_a),
2041 SH_PFC_PIN_GROUP(audio_clkout2_b),
2042 SH_PFC_PIN_GROUP(audio_clkout3_a),
2043 SH_PFC_PIN_GROUP(audio_clkout3_b),
2044 SH_PFC_PIN_GROUP(avb_link),
2045 SH_PFC_PIN_GROUP(avb_magic),
2046 SH_PFC_PIN_GROUP(avb_phy_int),
2047 SH_PFC_PIN_GROUP(avb_mdc),
2048 SH_PFC_PIN_GROUP(avb_avtp_pps),
2049 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2050 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2051 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2052 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
2053 SH_PFC_PIN_GROUP(i2c1_a),
2054 SH_PFC_PIN_GROUP(i2c1_b),
2055 SH_PFC_PIN_GROUP(i2c2_a),
2056 SH_PFC_PIN_GROUP(i2c2_b),
2057 SH_PFC_PIN_GROUP(i2c6_a),
2058 SH_PFC_PIN_GROUP(i2c6_b),
2059 SH_PFC_PIN_GROUP(i2c6_c),
2060 SH_PFC_PIN_GROUP(scif0_data),
2061 SH_PFC_PIN_GROUP(scif0_clk),
2062 SH_PFC_PIN_GROUP(scif0_ctrl),
2063 SH_PFC_PIN_GROUP(scif1_data_a),
2064 SH_PFC_PIN_GROUP(scif1_clk),
2065 SH_PFC_PIN_GROUP(scif1_ctrl),
2066 SH_PFC_PIN_GROUP(scif1_data_b),
2067 SH_PFC_PIN_GROUP(scif2_data_a),
2068 SH_PFC_PIN_GROUP(scif2_clk),
2069 SH_PFC_PIN_GROUP(scif2_data_b),
2070 SH_PFC_PIN_GROUP(scif3_data_a),
2071 SH_PFC_PIN_GROUP(scif3_clk),
2072 SH_PFC_PIN_GROUP(scif3_ctrl),
2073 SH_PFC_PIN_GROUP(scif3_data_b),
2074 SH_PFC_PIN_GROUP(scif4_data_a),
2075 SH_PFC_PIN_GROUP(scif4_clk_a),
2076 SH_PFC_PIN_GROUP(scif4_ctrl_a),
2077 SH_PFC_PIN_GROUP(scif4_data_b),
2078 SH_PFC_PIN_GROUP(scif4_clk_b),
2079 SH_PFC_PIN_GROUP(scif4_ctrl_b),
2080 SH_PFC_PIN_GROUP(scif4_data_c),
2081 SH_PFC_PIN_GROUP(scif4_clk_c),
2082 SH_PFC_PIN_GROUP(scif4_ctrl_c),
2083 SH_PFC_PIN_GROUP(scif5_data),
2084 SH_PFC_PIN_GROUP(scif5_clk),
2085 SH_PFC_PIN_GROUP(ssi0_data),
2086 SH_PFC_PIN_GROUP(ssi01239_ctrl),
2087 SH_PFC_PIN_GROUP(ssi1_data_a),
2088 SH_PFC_PIN_GROUP(ssi1_data_b),
2089 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
2090 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
2091 SH_PFC_PIN_GROUP(ssi2_data_a),
2092 SH_PFC_PIN_GROUP(ssi2_data_b),
2093 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
2094 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
2095 SH_PFC_PIN_GROUP(ssi3_data),
2096 SH_PFC_PIN_GROUP(ssi34_ctrl),
2097 SH_PFC_PIN_GROUP(ssi4_data),
2098 SH_PFC_PIN_GROUP(ssi4_ctrl),
2099 SH_PFC_PIN_GROUP(ssi5_data),
2100 SH_PFC_PIN_GROUP(ssi5_ctrl),
2101 SH_PFC_PIN_GROUP(ssi6_data),
2102 SH_PFC_PIN_GROUP(ssi6_ctrl),
2103 SH_PFC_PIN_GROUP(ssi7_data),
2104 SH_PFC_PIN_GROUP(ssi78_ctrl),
2105 SH_PFC_PIN_GROUP(ssi8_data),
2106 SH_PFC_PIN_GROUP(ssi9_data_a),
2107 SH_PFC_PIN_GROUP(ssi9_data_b),
2108 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
2109 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
2112 static const char * const audio_clk_groups[] = {
2132 static const char * const avb_groups[] = {
2139 "avb_avtp_capture_a",
2141 "avb_avtp_capture_b",
2144 static const char * const i2c1_groups[] = {
2149 static const char * const i2c2_groups[] = {
2154 static const char * const i2c6_groups[] = {
2160 static const char * const scif0_groups[] = {
2166 static const char * const scif1_groups[] = {
2173 static const char * const scif2_groups[] = {
2179 static const char * const scif3_groups[] = {
2186 static const char * const scif4_groups[] = {
2198 static const char * const scif5_groups[] = {
2203 static const char * const ssi_groups[] = {
2231 static const struct sh_pfc_function pinmux_functions[] = {
2232 SH_PFC_FUNCTION(audio_clk),
2233 SH_PFC_FUNCTION(avb),
2234 SH_PFC_FUNCTION(i2c1),
2235 SH_PFC_FUNCTION(i2c2),
2236 SH_PFC_FUNCTION(i2c6),
2237 SH_PFC_FUNCTION(scif0),
2238 SH_PFC_FUNCTION(scif1),
2239 SH_PFC_FUNCTION(scif2),
2240 SH_PFC_FUNCTION(scif3),
2241 SH_PFC_FUNCTION(scif4),
2242 SH_PFC_FUNCTION(scif5),
2243 SH_PFC_FUNCTION(ssi),
2246 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2247 #define F_(x, y) FN_##y
2248 #define FM(x) FN_##x
2249 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2266 GP_0_15_FN, GPSR0_15,
2267 GP_0_14_FN, GPSR0_14,
2268 GP_0_13_FN, GPSR0_13,
2269 GP_0_12_FN, GPSR0_12,
2270 GP_0_11_FN, GPSR0_11,
2271 GP_0_10_FN, GPSR0_10,
2281 GP_0_0_FN, GPSR0_0, }
2283 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2288 GP_1_27_FN, GPSR1_27,
2289 GP_1_26_FN, GPSR1_26,
2290 GP_1_25_FN, GPSR1_25,
2291 GP_1_24_FN, GPSR1_24,
2292 GP_1_23_FN, GPSR1_23,
2293 GP_1_22_FN, GPSR1_22,
2294 GP_1_21_FN, GPSR1_21,
2295 GP_1_20_FN, GPSR1_20,
2296 GP_1_19_FN, GPSR1_19,
2297 GP_1_18_FN, GPSR1_18,
2298 GP_1_17_FN, GPSR1_17,
2299 GP_1_16_FN, GPSR1_16,
2300 GP_1_15_FN, GPSR1_15,
2301 GP_1_14_FN, GPSR1_14,
2302 GP_1_13_FN, GPSR1_13,
2303 GP_1_12_FN, GPSR1_12,
2304 GP_1_11_FN, GPSR1_11,
2305 GP_1_10_FN, GPSR1_10,
2315 GP_1_0_FN, GPSR1_0, }
2317 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2335 GP_2_14_FN, GPSR2_14,
2336 GP_2_13_FN, GPSR2_13,
2337 GP_2_12_FN, GPSR2_12,
2338 GP_2_11_FN, GPSR2_11,
2339 GP_2_10_FN, GPSR2_10,
2349 GP_2_0_FN, GPSR2_0, }
2351 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2368 GP_3_15_FN, GPSR3_15,
2369 GP_3_14_FN, GPSR3_14,
2370 GP_3_13_FN, GPSR3_13,
2371 GP_3_12_FN, GPSR3_12,
2372 GP_3_11_FN, GPSR3_11,
2373 GP_3_10_FN, GPSR3_10,
2383 GP_3_0_FN, GPSR3_0, }
2385 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2400 GP_4_17_FN, GPSR4_17,
2401 GP_4_16_FN, GPSR4_16,
2402 GP_4_15_FN, GPSR4_15,
2403 GP_4_14_FN, GPSR4_14,
2404 GP_4_13_FN, GPSR4_13,
2405 GP_4_12_FN, GPSR4_12,
2406 GP_4_11_FN, GPSR4_11,
2407 GP_4_10_FN, GPSR4_10,
2417 GP_4_0_FN, GPSR4_0, }
2419 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2426 GP_5_25_FN, GPSR5_25,
2427 GP_5_24_FN, GPSR5_24,
2428 GP_5_23_FN, GPSR5_23,
2429 GP_5_22_FN, GPSR5_22,
2430 GP_5_21_FN, GPSR5_21,
2431 GP_5_20_FN, GPSR5_20,
2432 GP_5_19_FN, GPSR5_19,
2433 GP_5_18_FN, GPSR5_18,
2434 GP_5_17_FN, GPSR5_17,
2435 GP_5_16_FN, GPSR5_16,
2436 GP_5_15_FN, GPSR5_15,
2437 GP_5_14_FN, GPSR5_14,
2438 GP_5_13_FN, GPSR5_13,
2439 GP_5_12_FN, GPSR5_12,
2440 GP_5_11_FN, GPSR5_11,
2441 GP_5_10_FN, GPSR5_10,
2451 GP_5_0_FN, GPSR5_0, }
2453 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2454 GP_6_31_FN, GPSR6_31,
2455 GP_6_30_FN, GPSR6_30,
2456 GP_6_29_FN, GPSR6_29,
2457 GP_6_28_FN, GPSR6_28,
2458 GP_6_27_FN, GPSR6_27,
2459 GP_6_26_FN, GPSR6_26,
2460 GP_6_25_FN, GPSR6_25,
2461 GP_6_24_FN, GPSR6_24,
2462 GP_6_23_FN, GPSR6_23,
2463 GP_6_22_FN, GPSR6_22,
2464 GP_6_21_FN, GPSR6_21,
2465 GP_6_20_FN, GPSR6_20,
2466 GP_6_19_FN, GPSR6_19,
2467 GP_6_18_FN, GPSR6_18,
2468 GP_6_17_FN, GPSR6_17,
2469 GP_6_16_FN, GPSR6_16,
2470 GP_6_15_FN, GPSR6_15,
2471 GP_6_14_FN, GPSR6_14,
2472 GP_6_13_FN, GPSR6_13,
2473 GP_6_12_FN, GPSR6_12,
2474 GP_6_11_FN, GPSR6_11,
2475 GP_6_10_FN, GPSR6_10,
2485 GP_6_0_FN, GPSR6_0, }
2487 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2519 GP_7_0_FN, GPSR7_0, }
2525 #define FM(x) FN_##x,
2526 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2536 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2546 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2556 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2566 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2576 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2586 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2596 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2606 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2616 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2626 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2636 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2646 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2656 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2666 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2676 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2686 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2696 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
2697 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2698 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2699 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2700 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2701 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2702 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2710 #define FM(x) FN_##x,
2711 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2712 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
2713 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
2714 0, 0, /* RESERVED 31 */
2736 0, 0, /* RESERVED 0 */ }
2738 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2739 2, 3, 1, 2, 3, 1, 1, 2, 1,
2740 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2756 0, 0, 0, 0, /* RESERVED 8, 7 */
2765 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
2766 1, 1, 1, 1, 4, 4, 4,
2773 /* RESERVED 27, 26, 25, 24 */
2774 0, 0, 0, 0, 0, 0, 0, 0,
2775 0, 0, 0, 0, 0, 0, 0, 0,
2776 /* RESERVED 23, 22, 21, 20 */
2777 0, 0, 0, 0, 0, 0, 0, 0,
2778 0, 0, 0, 0, 0, 0, 0, 0,
2779 /* RESERVED 19, 18, 17, 16 */
2780 0, 0, 0, 0, 0, 0, 0, 0,
2781 0, 0, 0, 0, 0, 0, 0, 0,
2782 /* RESERVED 15, 14, 13, 12 */
2783 0, 0, 0, 0, 0, 0, 0, 0,
2784 0, 0, 0, 0, 0, 0, 0, 0,
2785 /* RESERVED 11, 10, 9, 8 */
2786 0, 0, 0, 0, 0, 0, 0, 0,
2787 0, 0, 0, 0, 0, 0, 0, 0,
2788 /* RESERVED 7, 6, 5, 4 */
2789 0, 0, 0, 0, 0, 0, 0, 0,
2790 0, 0, 0, 0, 0, 0, 0, 0,
2799 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
2800 .name = "r8a77950_pfc",
2801 .unlock_reg = 0xe6060000, /* PMMR */
2803 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2805 .pins = pinmux_pins,
2806 .nr_pins = ARRAY_SIZE(pinmux_pins),
2807 .groups = pinmux_groups,
2808 .nr_groups = ARRAY_SIZE(pinmux_groups),
2809 .functions = pinmux_functions,
2810 .nr_functions = ARRAY_SIZE(pinmux_functions),
2812 .cfg_regs = pinmux_config_regs,
2814 .pinmux_data = pinmux_data,
2815 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / karo-tx-linux.git / blob