drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 /* #define DEBUG_INTERRUPT */
  61 /* #define DEBUG_STATUS_A */
  62 /* #define DEBUG_STATUS_B */
  63
  64 #include <linux/interrupt.h>
  65 #include <linux/sched.h>
  66 #include "8255.h"
  67 #include "mite.h"
  68 #include "comedi_fc.h"
  69
  70 #ifndef MDPRINTK
  71 #define MDPRINTK(format, args...)
  72 #endif
  73
  74 /* A timeout count */
  75 #define NI_TIMEOUT 1000
  76 static const unsigned old_RTSI_clock_channel = 7;
  77
  78 /* Note: this table must match the ai_gain_* definitions */
  79 static const short ni_gainlkup[][16] = {
  80         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  81                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  82         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  83         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  84                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  85         [ai_gain_4] = {0, 1, 4, 7},
  86         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  87                           0x003, 0x004, 0x005, 0x006},
  88         [ai_gain_622x] = {0, 1, 4, 5},
  89         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  90         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  91 };
  92
  93 static const struct comedi_lrange range_ni_E_ai = { 16, {
  94                                                          RANGE(-10, 10),
  95                                                          RANGE(-5, 5),
  96                                                          RANGE(-2.5, 2.5),
  97                                                          RANGE(-1, 1),
  98                                                          RANGE(-0.5, 0.5),
  99                                                          RANGE(-0.25, 0.25),
 100                                                          RANGE(-0.1, 0.1),
 101                                                          RANGE(-0.05, 0.05),
 102                                                          RANGE(0, 20),
 103                                                          RANGE(0, 10),
 104                                                          RANGE(0, 5),
 105                                                          RANGE(0, 2),
 106                                                          RANGE(0, 1),
 107                                                          RANGE(0, 0.5),
 108                                                          RANGE(0, 0.2),
 109                                                          RANGE(0, 0.1),
 110                                                          }
 111 };
 112
 113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
 114                                                                 RANGE(-10, 10),
 115                                                                 RANGE(-5, 5),
 116                                                                 RANGE(-1, 1),
 117                                                                 RANGE(-0.1,
 118                                                                       0.1),
 119                                                                 RANGE(0, 10),
 120                                                                 RANGE(0, 5),
 121                                                                 RANGE(0, 1),
 122                                                                 RANGE(0, 0.1),
 123                                                                 }
 124 };
 125
 126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
 127                                                                    RANGE(-10,
 128                                                                          10),
 129                                                                    RANGE(-5, 5),
 130                                                                    RANGE(-2, 2),
 131                                                                    RANGE(-1, 1),
 132                                                                    RANGE(-0.5,
 133                                                                          0.5),
 134                                                                    RANGE(-0.2,
 135                                                                          0.2),
 136                                                                    RANGE(-0.1,
 137                                                                          0.1),
 138                                                                    RANGE(0, 10),
 139                                                                    RANGE(0, 5),
 140                                                                    RANGE(0, 2),
 141                                                                    RANGE(0, 1),
 142                                                                    RANGE(0,
 143                                                                          0.5),
 144                                                                    RANGE(0,
 145                                                                          0.2),
 146                                                                    RANGE(0,
 147                                                                          0.1),
 148                                                                    }
 149 };
 150
 151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 152                                                                  RANGE(-10, 10),
 153                                                                  RANGE(-5, 5),
 154                                                                  RANGE(-0.5,
 155                                                                        0.5),
 156                                                                  RANGE(-0.05,
 157                                                                        0.05),
 158                                                                  }
 159 };
 160
 161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
 162                                                              RANGE(-50, 50),
 163                                                              RANGE(-20, 20),
 164                                                              RANGE(-10, 10),
 165                                                              RANGE(-5, 5),
 166                                                              RANGE(-2, 2),
 167                                                              RANGE(-1, 1),
 168                                                              RANGE(-0.5, 0.5),
 169                                                              RANGE(-0.2, 0.2),
 170                                                              }
 171 };
 172
 173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
 174                                                              RANGE(-10, 10),
 175                                                              RANGE(-5, 5),
 176                                                              RANGE(-1, 1),
 177                                                              RANGE(-0.2, 0.2),
 178                                                              }
 179 };
 180
 181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
 182                                                              RANGE(-10, 10),
 183                                                              RANGE(-5, 5),
 184                                                              RANGE(-2, 2),
 185                                                              RANGE(-1, 1),
 186                                                              RANGE(-0.5, 0.5),
 187                                                              RANGE(-0.2, 0.2),
 188                                                              RANGE(-0.1, 0.1),
 189                                                              }
 190 };
 191
 192 static const struct comedi_lrange range_ni_S_ai_6143 = { 1, {
 193                                                              RANGE(-5, +5),
 194                                                              }
 195 };
 196
 197 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
 198                                                             RANGE(-10, 10),
 199                                                             RANGE(0, 10),
 200                                                             RANGE_ext(-1, 1),
 201                                                             RANGE_ext(0, 1),
 202                                                             }
 203 };
 204
 205 static const struct comedi_lrange *const ni_range_lkup[] = {
 206         [ai_gain_16] = &range_ni_E_ai,
 207         [ai_gain_8] = &range_ni_E_ai_limited,
 208         [ai_gain_14] = &range_ni_E_ai_limited14,
 209         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 210         [ai_gain_611x] = &range_ni_E_ai_611x,
 211         [ai_gain_622x] = &range_ni_M_ai_622x,
 212         [ai_gain_628x] = &range_ni_M_ai_628x,
 213         [ai_gain_6143] = &range_ni_S_ai_6143
 214 };
 215
 216 static int ni_dio_insn_config(struct comedi_device *dev,
 217                               struct comedi_subdevice *s,
 218                               struct comedi_insn *insn, unsigned int *data);
 219 static int ni_dio_insn_bits(struct comedi_device *dev,
 220                             struct comedi_subdevice *s,
 221                             struct comedi_insn *insn, unsigned int *data);
 222 static int ni_cdio_cmdtest(struct comedi_device *dev,
 223                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 224 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 225 static int ni_cdio_cancel(struct comedi_device *dev,
 226                           struct comedi_subdevice *s);
 227 static void handle_cdio_interrupt(struct comedi_device *dev);
 228 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 229                           unsigned int trignum);
 230
 231 static int ni_serial_insn_config(struct comedi_device *dev,
 232                                  struct comedi_subdevice *s,
 233                                  struct comedi_insn *insn, unsigned int *data);
 234 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 235                                    struct comedi_subdevice *s,
 236                                    unsigned char data_out,
 237                                    unsigned char *data_in);
 238 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 239                                    struct comedi_subdevice *s,
 240                                    unsigned char data_out,
 241                                    unsigned char *data_in);
 242
 243 static int ni_calib_insn_read(struct comedi_device *dev,
 244                               struct comedi_subdevice *s,
 245                               struct comedi_insn *insn, unsigned int *data);
 246 static int ni_calib_insn_write(struct comedi_device *dev,
 247                                struct comedi_subdevice *s,
 248                                struct comedi_insn *insn, unsigned int *data);
 249
 250 static int ni_eeprom_insn_read(struct comedi_device *dev,
 251                                struct comedi_subdevice *s,
 252                                struct comedi_insn *insn, unsigned int *data);
 253 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 254                                         struct comedi_subdevice *s,
 255                                         struct comedi_insn *insn,
 256                                         unsigned int *data);
 257
 258 static int ni_pfi_insn_bits(struct comedi_device *dev,
 259                             struct comedi_subdevice *s,
 260                             struct comedi_insn *insn, unsigned int *data);
 261 static int ni_pfi_insn_config(struct comedi_device *dev,
 262                               struct comedi_subdevice *s,
 263                               struct comedi_insn *insn, unsigned int *data);
 264 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 265                                        unsigned chan);
 266
 267 static void ni_rtsi_init(struct comedi_device *dev);
 268 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 269                              struct comedi_subdevice *s,
 270                              struct comedi_insn *insn, unsigned int *data);
 271 static int ni_rtsi_insn_config(struct comedi_device *dev,
 272                                struct comedi_subdevice *s,
 273                                struct comedi_insn *insn, unsigned int *data);
 274
 275 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 276 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 277
 278 #ifdef DEBUG_STATUS_A
 279 static void ni_mio_print_status_a(int status);
 280 #else
 281 #define ni_mio_print_status_a(a)
 282 #endif
 283 #ifdef DEBUG_STATUS_B
 284 static void ni_mio_print_status_b(int status);
 285 #else
 286 #define ni_mio_print_status_b(a)
 287 #endif
 288
 289 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 290 #ifndef PCIDMA
 291 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 292 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 293                                  struct comedi_subdevice *s);
 294 #endif
 295 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 296 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 297                          unsigned int trignum);
 298 static void ni_load_channelgain_list(struct comedi_device *dev,
 299                                      unsigned int n_chan, unsigned int *list);
 300 static void shutdown_ai_command(struct comedi_device *dev);
 301
 302 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 303                          unsigned int trignum);
 304
 305 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
 306
 307 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 308
 309 static int ni_gpct_insn_write(struct comedi_device *dev,
 310                               struct comedi_subdevice *s,
 311                               struct comedi_insn *insn, unsigned int *data);
 312 static int ni_gpct_insn_read(struct comedi_device *dev,
 313                              struct comedi_subdevice *s,
 314                              struct comedi_insn *insn, unsigned int *data);
 315 static int ni_gpct_insn_config(struct comedi_device *dev,
 316                                struct comedi_subdevice *s,
 317                                struct comedi_insn *insn, unsigned int *data);
 318 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 319 static int ni_gpct_cmdtest(struct comedi_device *dev,
 320                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 321 static int ni_gpct_cancel(struct comedi_device *dev,
 322                           struct comedi_subdevice *s);
 323 static void handle_gpct_interrupt(struct comedi_device *dev,
 324                                   unsigned short counter_index);
 325
 326 static int init_cs5529(struct comedi_device *dev);
 327 static int cs5529_do_conversion(struct comedi_device *dev,
 328                                 unsigned short *data);
 329 static int cs5529_ai_insn_read(struct comedi_device *dev,
 330                                struct comedi_subdevice *s,
 331                                struct comedi_insn *insn, unsigned int *data);
 332 #ifdef NI_CS5529_DEBUG
 333 static unsigned int cs5529_config_read(struct comedi_device *dev,
 334                                        unsigned int reg_select_bits);
 335 #endif
 336 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 337                                 unsigned int reg_select_bits);
 338
 339 static int ni_m_series_pwm_config(struct comedi_device *dev,
 340                                   struct comedi_subdevice *s,
 341                                   struct comedi_insn *insn, unsigned int *data);
 342 static int ni_6143_pwm_config(struct comedi_device *dev,
 343                               struct comedi_subdevice *s,
 344                               struct comedi_insn *insn, unsigned int *data);
 345
 346 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 347                                unsigned period_ns);
 348 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 349 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 350
 351 enum aimodes {
 352         AIMODE_NONE = 0,
 353         AIMODE_HALF_FULL = 1,
 354         AIMODE_SCAN = 2,
 355         AIMODE_SAMPLE = 3,
 356 };
 357
 358 enum ni_common_subdevices {
 359         NI_AI_SUBDEV,
 360         NI_AO_SUBDEV,
 361         NI_DIO_SUBDEV,
 362         NI_8255_DIO_SUBDEV,
 363         NI_UNUSED_SUBDEV,
 364         NI_CALIBRATION_SUBDEV,
 365         NI_EEPROM_SUBDEV,
 366         NI_PFI_DIO_SUBDEV,
 367         NI_CS5529_CALIBRATION_SUBDEV,
 368         NI_SERIAL_SUBDEV,
 369         NI_RTSI_SUBDEV,
 370         NI_GPCT0_SUBDEV,
 371         NI_GPCT1_SUBDEV,
 372         NI_FREQ_OUT_SUBDEV,
 373         NI_NUM_SUBDEVICES
 374 };
 375 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 376 {
 377         switch (counter_index) {
 378         case 0:
 379                 return NI_GPCT0_SUBDEV;
 380                 break;
 381         case 1:
 382                 return NI_GPCT1_SUBDEV;
 383                 break;
 384         default:
 385                 break;
 386         }
 387         BUG();
 388         return NI_GPCT0_SUBDEV;
 389 }
 390
 391 enum timebase_nanoseconds {
 392         TIMEBASE_1_NS = 50,
 393         TIMEBASE_2_NS = 10000
 394 };
 395
 396 #define SERIAL_DISABLED         0
 397 #define SERIAL_600NS            600
 398 #define SERIAL_1_2US            1200
 399 #define SERIAL_10US                     10000
 400
 401 static const int num_adc_stages_611x = 3;
 402
 403 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 404                                unsigned ai_mite_status);
 405 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 406                                unsigned ao_mite_status);
 407 static void get_last_sample_611x(struct comedi_device *dev);
 408 static void get_last_sample_6143(struct comedi_device *dev);
 409
 410 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 411                                    unsigned bit_mask, unsigned bit_values)
 412 {
 413         unsigned long flags;
 414
 415         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 416         switch (reg) {
 417         case Interrupt_A_Enable_Register:
 418                 devpriv->int_a_enable_reg &= ~bit_mask;
 419                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 420                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 421                                     Interrupt_A_Enable_Register);
 422                 break;
 423         case Interrupt_B_Enable_Register:
 424                 devpriv->int_b_enable_reg &= ~bit_mask;
 425                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 426                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 427                                     Interrupt_B_Enable_Register);
 428                 break;
 429         case IO_Bidirection_Pin_Register:
 430                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 431                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 432                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 433                                     IO_Bidirection_Pin_Register);
 434                 break;
 435         case AI_AO_Select:
 436                 devpriv->ai_ao_select_reg &= ~bit_mask;
 437                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 438                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 439                 break;
 440         case G0_G1_Select:
 441                 devpriv->g0_g1_select_reg &= ~bit_mask;
 442                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 443                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 444                 break;
 445         default:
 446                 printk("Warning %s() called with invalid register\n", __func__);
 447                 printk("reg is %d\n", reg);
 448                 break;
 449         }
 450         mmiowb();
 451         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 452 }
 453
 454 #ifdef PCIDMA
 455 static int ni_ai_drain_dma(struct comedi_device *dev);
 456
 457 /* DMA channel setup */
 458
 459 /* negative channel means no channel */
 460 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 461 {
 462         unsigned bitfield;
 463
 464         if (channel >= 0) {
 465                 bitfield =
 466                     (ni_stc_dma_channel_select_bitfield(channel) <<
 467                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 468         } else {
 469                 bitfield = 0;
 470         }
 471         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 472 }
 473
 474 /* negative channel means no channel */
 475 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 476 {
 477         unsigned bitfield;
 478
 479         if (channel >= 0) {
 480                 bitfield =
 481                     (ni_stc_dma_channel_select_bitfield(channel) <<
 482                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 483         } else {
 484                 bitfield = 0;
 485         }
 486         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 487 }
 488
 489 /* negative mite_channel means no channel */
 490 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 491                                            unsigned gpct_index,
 492                                            int mite_channel)
 493 {
 494         unsigned bitfield;
 495
 496         if (mite_channel >= 0) {
 497                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 498         } else {
 499                 bitfield = 0;
 500         }
 501         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 502                         bitfield);
 503 }
 504
 505 /* negative mite_channel means no channel */
 506 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 507                                           int mite_channel)
 508 {
 509         unsigned long flags;
 510
 511         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 512         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 513         if (mite_channel >= 0) {
 514                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 515                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 516                    Definitely works for dma channels 0 and 1. */
 517                 devpriv->cdio_dma_select_reg |=
 518                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 519                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 520         }
 521         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 522         mmiowb();
 523         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 524 }
 525
 526 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 527 {
 528         unsigned long flags;
 529
 530         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 531         BUG_ON(devpriv->ai_mite_chan);
 532         devpriv->ai_mite_chan =
 533             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 534         if (devpriv->ai_mite_chan == NULL) {
 535                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 536                 comedi_error(dev,
 537                              "failed to reserve mite dma channel for analog input.");
 538                 return -EBUSY;
 539         }
 540         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 541         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 542         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 543         return 0;
 544 }
 545
 546 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 547 {
 548         unsigned long flags;
 549
 550         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 551         BUG_ON(devpriv->ao_mite_chan);
 552         devpriv->ao_mite_chan =
 553             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 554         if (devpriv->ao_mite_chan == NULL) {
 555                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 556                 comedi_error(dev,
 557                              "failed to reserve mite dma channel for analog outut.");
 558                 return -EBUSY;
 559         }
 560         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 561         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 562         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 563         return 0;
 564 }
 565
 566 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 567                                         unsigned gpct_index,
 568                                         enum comedi_io_direction direction)
 569 {
 570         unsigned long flags;
 571         struct mite_channel *mite_chan;
 572
 573         BUG_ON(gpct_index >= NUM_GPCT);
 574         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 575         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 576         mite_chan =
 577             mite_request_channel(devpriv->mite,
 578                                  devpriv->gpct_mite_ring[gpct_index]);
 579         if (mite_chan == NULL) {
 580                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 581                 comedi_error(dev,
 582                              "failed to reserve mite dma channel for counter.");
 583                 return -EBUSY;
 584         }
 585         mite_chan->dir = direction;
 586         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 587                                 mite_chan);
 588         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 589         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 590         return 0;
 591 }
 592
 593 #endif /*  PCIDMA */
 594
 595 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 596 {
 597 #ifdef PCIDMA
 598         unsigned long flags;
 599
 600         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 601         BUG_ON(devpriv->cdo_mite_chan);
 602         devpriv->cdo_mite_chan =
 603             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 604         if (devpriv->cdo_mite_chan == NULL) {
 605                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 606                 comedi_error(dev,
 607                              "failed to reserve mite dma channel for correlated digital outut.");
 608                 return -EBUSY;
 609         }
 610         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 611         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 612         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 613 #endif /*  PCIDMA */
 614         return 0;
 615 }
 616
 617 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 618 {
 619 #ifdef PCIDMA
 620         unsigned long flags;
 621
 622         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 623         if (devpriv->ai_mite_chan) {
 624                 ni_set_ai_dma_channel(dev, -1);
 625                 mite_release_channel(devpriv->ai_mite_chan);
 626                 devpriv->ai_mite_chan = NULL;
 627         }
 628         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 629 #endif /*  PCIDMA */
 630 }
 631
 632 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 633 {
 634 #ifdef PCIDMA
 635         unsigned long flags;
 636
 637         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 638         if (devpriv->ao_mite_chan) {
 639                 ni_set_ao_dma_channel(dev, -1);
 640                 mite_release_channel(devpriv->ao_mite_chan);
 641                 devpriv->ao_mite_chan = NULL;
 642         }
 643         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 644 #endif /*  PCIDMA */
 645 }
 646
 647 void ni_release_gpct_mite_channel(struct comedi_device *dev,
 648                                   unsigned gpct_index)
 649 {
 650 #ifdef PCIDMA
 651         unsigned long flags;
 652
 653         BUG_ON(gpct_index >= NUM_GPCT);
 654         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 655         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 656                 struct mite_channel *mite_chan =
 657                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 658
 659                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 660                 ni_tio_set_mite_channel(&devpriv->
 661                                         counter_dev->counters[gpct_index],
 662                                         NULL);
 663                 mite_release_channel(mite_chan);
 664         }
 665         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 666 #endif /*  PCIDMA */
 667 }
 668
 669 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 670 {
 671 #ifdef PCIDMA
 672         unsigned long flags;
 673
 674         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 675         if (devpriv->cdo_mite_chan) {
 676                 ni_set_cdo_dma_channel(dev, -1);
 677                 mite_release_channel(devpriv->cdo_mite_chan);
 678                 devpriv->cdo_mite_chan = NULL;
 679         }
 680         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 681 #endif /*  PCIDMA */
 682 }
 683
 684 /* e-series boards use the second irq signals to generate dma requests for their counters */
 685 #ifdef PCIDMA
 686 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 687                                           unsigned gpct_index, short enable)
 688 {
 689         if (boardtype.reg_type & ni_reg_m_series_mask)
 690                 return;
 691         switch (gpct_index) {
 692         case 0:
 693                 if (enable) {
 694                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 695                                             Second_IRQ_A_Enable_Register);
 696                 } else {
 697                         devpriv->stc_writew(dev, 0,
 698                                             Second_IRQ_A_Enable_Register);
 699                 }
 700                 break;
 701         case 1:
 702                 if (enable) {
 703                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 704                                             Second_IRQ_B_Enable_Register);
 705                 } else {
 706                         devpriv->stc_writew(dev, 0,
 707                                             Second_IRQ_B_Enable_Register);
 708                 }
 709                 break;
 710         default:
 711                 BUG();
 712                 break;
 713         }
 714 }
 715 #endif /*  PCIDMA */
 716
 717 static void ni_clear_ai_fifo(struct comedi_device *dev)
 718 {
 719         if (boardtype.reg_type == ni_reg_6143) {
 720                 /*  Flush the 6143 data FIFO */
 721                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 722                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 723                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   /*  Wait for complete */
 724         } else {
 725                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 726                 if (boardtype.reg_type == ni_reg_625x) {
 727                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 728                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 729 #if 0
 730                         /* the NI example code does 3 convert pulses for 625x boards,
 731                            but that appears to be wrong in practice. */
 732                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 733                                             AI_Command_1_Register);
 734                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 735                                             AI_Command_1_Register);
 736                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 737                                             AI_Command_1_Register);
 738 #endif
 739                 }
 740         }
 741 }
 742
 743 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 744 {
 745         devpriv->stc_writew(dev, data >> 16, reg);
 746         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 747 }
 748
 749 static uint32_t win_in2(struct comedi_device *dev, int reg)
 750 {
 751         uint32_t bits;
 752         bits = devpriv->stc_readw(dev, reg) << 16;
 753         bits |= devpriv->stc_readw(dev, reg + 1);
 754         return bits;
 755 }
 756
 757 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 758 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 759                                   int addr)
 760 {
 761         unsigned long flags;
 762
 763         spin_lock_irqsave(&devpriv->window_lock, flags);
 764         ni_writew(addr, AO_Window_Address_611x);
 765         ni_writew(data, AO_Window_Data_611x);
 766         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 767 }
 768
 769 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 770                                   int addr)
 771 {
 772         unsigned long flags;
 773
 774         spin_lock_irqsave(&devpriv->window_lock, flags);
 775         ni_writew(addr, AO_Window_Address_611x);
 776         ni_writel(data, AO_Window_Data_611x);
 777         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 778 }
 779
 780 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 781 {
 782         unsigned long flags;
 783         unsigned short data;
 784
 785         spin_lock_irqsave(&devpriv->window_lock, flags);
 786         ni_writew(addr, AO_Window_Address_611x);
 787         data = ni_readw(AO_Window_Data_611x);
 788         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 789         return data;
 790 }
 791
 792 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 793 * share registers (such as Interrupt_A_Register) without interfering with
 794 * each other.
 795 *
 796 * NOTE: the switch/case statements are optimized out for a constant argument
 797 * so this is actually quite fast---  If you must wrap another function around this
 798 * make it inline to avoid a large speed penalty.
 799 *
 800 * value should only be 1 or 0.
 801 */
 802 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 803                                unsigned bits, unsigned value)
 804 {
 805         unsigned bit_values;
 806
 807         if (value)
 808                 bit_values = bits;
 809         else
 810                 bit_values = 0;
 811         ni_set_bitfield(dev, reg, bits, bit_values);
 812 }
 813
 814 static irqreturn_t ni_E_interrupt(int irq, void *d)
 815 {
 816         struct comedi_device *dev = d;
 817         unsigned short a_status;
 818         unsigned short b_status;
 819         unsigned int ai_mite_status = 0;
 820         unsigned int ao_mite_status = 0;
 821         unsigned long flags;
 822 #ifdef PCIDMA
 823         struct mite_struct *mite = devpriv->mite;
 824 #endif
 825
 826         if (dev->attached == 0)
 827                 return IRQ_NONE;
 828         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 829
 830         /*  lock to avoid race with comedi_poll */
 831         spin_lock_irqsave(&dev->spinlock, flags);
 832         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 833         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 834 #ifdef PCIDMA
 835         if (mite) {
 836                 unsigned long flags_too;
 837
 838                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 839                 if (devpriv->ai_mite_chan) {
 840                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 841                         if (ai_mite_status & CHSR_LINKC)
 842                                 writel(CHOR_CLRLC,
 843                                        devpriv->mite->mite_io_addr +
 844                                        MITE_CHOR(devpriv->
 845                                                  ai_mite_chan->channel));
 846                 }
 847                 if (devpriv->ao_mite_chan) {
 848                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 849                         if (ao_mite_status & CHSR_LINKC)
 850                                 writel(CHOR_CLRLC,
 851                                        mite->mite_io_addr +
 852                                        MITE_CHOR(devpriv->
 853                                                  ao_mite_chan->channel));
 854                 }
 855                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 856         }
 857 #endif
 858         ack_a_interrupt(dev, a_status);
 859         ack_b_interrupt(dev, b_status);
 860         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 861                 handle_a_interrupt(dev, a_status, ai_mite_status);
 862         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 863                 handle_b_interrupt(dev, b_status, ao_mite_status);
 864         handle_gpct_interrupt(dev, 0);
 865         handle_gpct_interrupt(dev, 1);
 866         handle_cdio_interrupt(dev);
 867
 868         spin_unlock_irqrestore(&dev->spinlock, flags);
 869         return IRQ_HANDLED;
 870 }
 871
 872 #ifdef PCIDMA
 873 static void ni_sync_ai_dma(struct comedi_device *dev)
 874 {
 875         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 876         unsigned long flags;
 877
 878         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 879         if (devpriv->ai_mite_chan)
 880                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 881         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 882 }
 883
 884 static void mite_handle_b_linkc(struct mite_struct *mite,
 885                                 struct comedi_device *dev)
 886 {
 887         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 888         unsigned long flags;
 889
 890         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 891         if (devpriv->ao_mite_chan) {
 892                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 893         }
 894         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 895 }
 896
 897 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 898 {
 899         static const int timeout = 10000;
 900         int i;
 901         for (i = 0; i < timeout; i++) {
 902                 unsigned short b_status;
 903
 904                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 905                 if (b_status & AO_FIFO_Half_Full_St)
 906                         break;
 907                 /* if we poll too often, the pci bus activity seems
 908                    to slow the dma transfer down */
 909                 udelay(10);
 910         }
 911         if (i == timeout) {
 912                 comedi_error(dev, "timed out waiting for dma load");
 913                 return -EPIPE;
 914         }
 915         return 0;
 916 }
 917
 918 #endif /* PCIDMA */
 919 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 920 {
 921         if (devpriv->aimode == AIMODE_SCAN) {
 922 #ifdef PCIDMA
 923                 static const int timeout = 10;
 924                 int i;
 925
 926                 for (i = 0; i < timeout; i++) {
 927                         ni_sync_ai_dma(dev);
 928                         if ((s->async->events & COMEDI_CB_EOS))
 929                                 break;
 930                         udelay(1);
 931                 }
 932 #else
 933                 ni_handle_fifo_dregs(dev);
 934                 s->async->events |= COMEDI_CB_EOS;
 935 #endif
 936         }
 937         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 938         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 939                 shutdown_ai_command(dev);
 940         }
 941 }
 942
 943 static void shutdown_ai_command(struct comedi_device *dev)
 944 {
 945         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 946
 947 #ifdef PCIDMA
 948         ni_ai_drain_dma(dev);
 949 #endif
 950         ni_handle_fifo_dregs(dev);
 951         get_last_sample_611x(dev);
 952         get_last_sample_6143(dev);
 953
 954         s->async->events |= COMEDI_CB_EOA;
 955 }
 956
 957 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
 958 {
 959         if (s->
 960             async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
 961                              COMEDI_CB_EOA)) {
 962                 switch (s - dev->subdevices) {
 963                 case NI_AI_SUBDEV:
 964                         ni_ai_reset(dev, s);
 965                         break;
 966                 case NI_AO_SUBDEV:
 967                         ni_ao_reset(dev, s);
 968                         break;
 969                 case NI_GPCT0_SUBDEV:
 970                 case NI_GPCT1_SUBDEV:
 971                         ni_gpct_cancel(dev, s);
 972                         break;
 973                 case NI_DIO_SUBDEV:
 974                         ni_cdio_cancel(dev, s);
 975                         break;
 976                 default:
 977                         break;
 978                 }
 979         }
 980         comedi_event(dev, s);
 981 }
 982
 983 static void handle_gpct_interrupt(struct comedi_device *dev,
 984                                   unsigned short counter_index)
 985 {
 986 #ifdef PCIDMA
 987         struct comedi_subdevice *s;
 988
 989         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
 990
 991         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
 992                                 s);
 993         if (s->async->events)
 994                 ni_event(dev, s);
 995 #endif
 996 }
 997
 998 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
 999 {
1000         unsigned short ack = 0;
1001
1002         if (a_status & AI_SC_TC_St) {
1003                 ack |= AI_SC_TC_Interrupt_Ack;
1004         }
1005         if (a_status & AI_START1_St) {
1006                 ack |= AI_START1_Interrupt_Ack;
1007         }
1008         if (a_status & AI_START_St) {
1009                 ack |= AI_START_Interrupt_Ack;
1010         }
1011         if (a_status & AI_STOP_St) {
1012                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1013                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1014         }
1015         if (ack)
1016                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1017 }
1018
1019 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1020                                unsigned ai_mite_status)
1021 {
1022         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1023
1024         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1025         if (s->type == COMEDI_SUBD_UNUSED)
1026                 return;
1027
1028 #ifdef DEBUG_INTERRUPT
1029         printk
1030             ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1031              status, ai_mite_status);
1032         ni_mio_print_status_a(status);
1033 #endif
1034 #ifdef PCIDMA
1035         if (ai_mite_status & CHSR_LINKC) {
1036                 ni_sync_ai_dma(dev);
1037         }
1038
1039         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1040                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1041                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1042                 printk
1043                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1044                      ai_mite_status);
1045                 /* mite_print_chsr(ai_mite_status); */
1046                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1047                 /* disable_irq(dev->irq); */
1048         }
1049 #endif
1050
1051         /* test for all uncommon interrupt events at the same time */
1052         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1053                       AI_SC_TC_St | AI_START1_St)) {
1054                 if (status == 0xffff) {
1055                         printk
1056                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1057                         /* we probably aren't even running a command now,
1058                          * so it's a good idea to be careful. */
1059                         if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1060                                 s->async->events |=
1061                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1062                                 ni_event(dev, s);
1063                         }
1064                         return;
1065                 }
1066                 if (status & (AI_Overrun_St | AI_Overflow_St |
1067                               AI_SC_TC_Error_St)) {
1068                         printk("ni_mio_common: ai error a_status=%04x\n",
1069                                status);
1070                         ni_mio_print_status_a(status);
1071
1072                         shutdown_ai_command(dev);
1073
1074                         s->async->events |= COMEDI_CB_ERROR;
1075                         if (status & (AI_Overrun_St | AI_Overflow_St))
1076                                 s->async->events |= COMEDI_CB_OVERFLOW;
1077
1078                         ni_event(dev, s);
1079
1080                         return;
1081                 }
1082                 if (status & AI_SC_TC_St) {
1083 #ifdef DEBUG_INTERRUPT
1084                         printk("ni_mio_common: SC_TC interrupt\n");
1085 #endif
1086                         if (!devpriv->ai_continuous) {
1087                                 shutdown_ai_command(dev);
1088                         }
1089                 }
1090         }
1091 #ifndef PCIDMA
1092         if (status & AI_FIFO_Half_Full_St) {
1093                 int i;
1094                 static const int timeout = 10;
1095                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1096                  *fail to get the fifo less than half full, so loop to be sure.*/
1097                 for (i = 0; i < timeout; ++i) {
1098                         ni_handle_fifo_half_full(dev);
1099                         if ((devpriv->stc_readw(dev,
1100                                                 AI_Status_1_Register) &
1101                              AI_FIFO_Half_Full_St) == 0)
1102                                 break;
1103                 }
1104         }
1105 #endif /*  !PCIDMA */
1106
1107         if ((status & AI_STOP_St)) {
1108                 ni_handle_eos(dev, s);
1109         }
1110
1111         ni_event(dev, s);
1112
1113 #ifdef DEBUG_INTERRUPT
1114         status = devpriv->stc_readw(dev, AI_Status_1_Register);
1115         if (status & Interrupt_A_St) {
1116                 printk
1117                     ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1118                      status);
1119         }
1120 #endif
1121 }
1122
1123 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1124 {
1125         unsigned short ack = 0;
1126         if (b_status & AO_BC_TC_St) {
1127                 ack |= AO_BC_TC_Interrupt_Ack;
1128         }
1129         if (b_status & AO_Overrun_St) {
1130                 ack |= AO_Error_Interrupt_Ack;
1131         }
1132         if (b_status & AO_START_St) {
1133                 ack |= AO_START_Interrupt_Ack;
1134         }
1135         if (b_status & AO_START1_St) {
1136                 ack |= AO_START1_Interrupt_Ack;
1137         }
1138         if (b_status & AO_UC_TC_St) {
1139                 ack |= AO_UC_TC_Interrupt_Ack;
1140         }
1141         if (b_status & AO_UI2_TC_St) {
1142                 ack |= AO_UI2_TC_Interrupt_Ack;
1143         }
1144         if (b_status & AO_UPDATE_St) {
1145                 ack |= AO_UPDATE_Interrupt_Ack;
1146         }
1147         if (ack)
1148                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1149 }
1150
1151 static void handle_b_interrupt(struct comedi_device *dev,
1152                                unsigned short b_status, unsigned ao_mite_status)
1153 {
1154         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1155         /* unsigned short ack=0; */
1156 #ifdef DEBUG_INTERRUPT
1157         printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1158                b_status, ao_mite_status);
1159         ni_mio_print_status_b(b_status);
1160 #endif
1161
1162 #ifdef PCIDMA
1163         /* Currently, mite.c requires us to handle LINKC */
1164         if (ao_mite_status & CHSR_LINKC) {
1165                 mite_handle_b_linkc(devpriv->mite, dev);
1166         }
1167
1168         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1169                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1170                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1171                 printk
1172                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1173                      ao_mite_status);
1174                 /* mite_print_chsr(ao_mite_status); */
1175                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1176         }
1177 #endif
1178
1179         if (b_status == 0xffff)
1180                 return;
1181         if (b_status & AO_Overrun_St) {
1182                 printk
1183                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1184                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1185                 s->async->events |= COMEDI_CB_OVERFLOW;
1186         }
1187
1188         if (b_status & AO_BC_TC_St) {
1189                 MDPRINTK
1190                     ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1191                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1192                 s->async->events |= COMEDI_CB_EOA;
1193         }
1194 #ifndef PCIDMA
1195         if (b_status & AO_FIFO_Request_St) {
1196                 int ret;
1197
1198                 ret = ni_ao_fifo_half_empty(dev, s);
1199                 if (!ret) {
1200                         printk("ni_mio_common: AO buffer underrun\n");
1201                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1202                                     AO_FIFO_Interrupt_Enable |
1203                                     AO_Error_Interrupt_Enable, 0);
1204                         s->async->events |= COMEDI_CB_OVERFLOW;
1205                 }
1206         }
1207 #endif
1208
1209         ni_event(dev, s);
1210 }
1211
1212 #ifdef DEBUG_STATUS_A
1213 static const char *const status_a_strings[] = {
1214         "passthru0", "fifo", "G0_gate", "G0_TC",
1215         "stop", "start", "sc_tc", "start1",
1216         "start2", "sc_tc_error", "overflow", "overrun",
1217         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1218 };
1219
1220 static void ni_mio_print_status_a(int status)
1221 {
1222         int i;
1223
1224         printk("A status:");
1225         for (i = 15; i >= 0; i--) {
1226                 if (status & (1 << i)) {
1227                         printk(" %s", status_a_strings[i]);
1228                 }
1229         }
1230         printk("\n");
1231 }
1232 #endif
1233
1234 #ifdef DEBUG_STATUS_B
1235 static const char *const status_b_strings[] = {
1236         "passthru1", "fifo", "G1_gate", "G1_TC",
1237         "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1238         "start1", "overrun", "start", "bc_tc_error",
1239         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1240 };
1241
1242 static void ni_mio_print_status_b(int status)
1243 {
1244         int i;
1245
1246         printk("B status:");
1247         for (i = 15; i >= 0; i--) {
1248                 if (status & (1 << i)) {
1249                         printk(" %s", status_b_strings[i]);
1250                 }
1251         }
1252         printk("\n");
1253 }
1254 #endif
1255
1256 #ifndef PCIDMA
1257
1258 static void ni_ao_fifo_load(struct comedi_device *dev,
1259                             struct comedi_subdevice *s, int n)
1260 {
1261         struct comedi_async *async = s->async;
1262         struct comedi_cmd *cmd = &async->cmd;
1263         int chan;
1264         int i;
1265         short d;
1266         u32 packed_data;
1267         int range;
1268         int err = 1;
1269
1270         chan = async->cur_chan;
1271         for (i = 0; i < n; i++) {
1272                 err &= comedi_buf_get(async, &d);
1273                 if (err == 0)
1274                         break;
1275
1276                 range = CR_RANGE(cmd->chanlist[chan]);
1277
1278                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1279                         packed_data = d & 0xffff;
1280                         /* 6711 only has 16 bit wide ao fifo */
1281                         if (boardtype.reg_type != ni_reg_6711) {
1282                                 err &= comedi_buf_get(async, &d);
1283                                 if (err == 0)
1284                                         break;
1285                                 chan++;
1286                                 i++;
1287                                 packed_data |= (d << 16) & 0xffff0000;
1288                         }
1289                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1290                 } else {
1291                         ni_writew(d, DAC_FIFO_Data);
1292                 }
1293                 chan++;
1294                 chan %= cmd->chanlist_len;
1295         }
1296         async->cur_chan = chan;
1297         if (err == 0) {
1298                 async->events |= COMEDI_CB_OVERFLOW;
1299         }
1300 }
1301
1302 /*
1303  *  There's a small problem if the FIFO gets really low and we
1304  *  don't have the data to fill it.  Basically, if after we fill
1305  *  the FIFO with all the data available, the FIFO is _still_
1306  *  less than half full, we never clear the interrupt.  If the
1307  *  IRQ is in edge mode, we never get another interrupt, because
1308  *  this one wasn't cleared.  If in level mode, we get flooded
1309  *  with interrupts that we can't fulfill, because nothing ever
1310  *  gets put into the buffer.
1311  *
1312  *  This kind of situation is recoverable, but it is easier to
1313  *  just pretend we had a FIFO underrun, since there is a good
1314  *  chance it will happen anyway.  This is _not_ the case for
1315  *  RT code, as RT code might purposely be running close to the
1316  *  metal.  Needs to be fixed eventually.
1317  */
1318 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1319                                  struct comedi_subdevice *s)
1320 {
1321         int n;
1322
1323         n = comedi_buf_read_n_available(s->async);
1324         if (n == 0) {
1325                 s->async->events |= COMEDI_CB_OVERFLOW;
1326                 return 0;
1327         }
1328
1329         n /= sizeof(short);
1330         if (n > boardtype.ao_fifo_depth / 2)
1331                 n = boardtype.ao_fifo_depth / 2;
1332
1333         ni_ao_fifo_load(dev, s, n);
1334
1335         s->async->events |= COMEDI_CB_BLOCK;
1336
1337         return 1;
1338 }
1339
1340 static int ni_ao_prep_fifo(struct comedi_device *dev,
1341                            struct comedi_subdevice *s)
1342 {
1343         int n;
1344
1345         /* reset fifo */
1346         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1347         if (boardtype.reg_type & ni_reg_6xxx_mask)
1348                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1349
1350         /* load some data */
1351         n = comedi_buf_read_n_available(s->async);
1352         if (n == 0)
1353                 return 0;
1354
1355         n /= sizeof(short);
1356         if (n > boardtype.ao_fifo_depth)
1357                 n = boardtype.ao_fifo_depth;
1358
1359         ni_ao_fifo_load(dev, s, n);
1360
1361         return n;
1362 }
1363
1364 static void ni_ai_fifo_read(struct comedi_device *dev,
1365                             struct comedi_subdevice *s, int n)
1366 {
1367         struct comedi_async *async = s->async;
1368         int i;
1369
1370         if (boardtype.reg_type == ni_reg_611x) {
1371                 short data[2];
1372                 u32 dl;
1373
1374                 for (i = 0; i < n / 2; i++) {
1375                         dl = ni_readl(ADC_FIFO_Data_611x);
1376                         /* This may get the hi/lo data in the wrong order */
1377                         data[0] = (dl >> 16) & 0xffff;
1378                         data[1] = dl & 0xffff;
1379                         cfc_write_array_to_buffer(s, data, sizeof(data));
1380                 }
1381                 /* Check if there's a single sample stuck in the FIFO */
1382                 if (n % 2) {
1383                         dl = ni_readl(ADC_FIFO_Data_611x);
1384                         data[0] = dl & 0xffff;
1385                         cfc_write_to_buffer(s, data[0]);
1386                 }
1387         } else if (boardtype.reg_type == ni_reg_6143) {
1388                 short data[2];
1389                 u32 dl;
1390
1391                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1392                 for (i = 0; i < n / 2; i++) {
1393                         dl = ni_readl(AIFIFO_Data_6143);
1394
1395                         data[0] = (dl >> 16) & 0xffff;
1396                         data[1] = dl & 0xffff;
1397                         cfc_write_array_to_buffer(s, data, sizeof(data));
1398                 }
1399                 if (n % 2) {
1400                         /* Assume there is a single sample stuck in the FIFO */
1401                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1402                         dl = ni_readl(AIFIFO_Data_6143);
1403                         data[0] = (dl >> 16) & 0xffff;
1404                         cfc_write_to_buffer(s, data[0]);
1405                 }
1406         } else {
1407                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1408                     sizeof(devpriv->ai_fifo_buffer[0])) {
1409                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1410                         async->events |= COMEDI_CB_ERROR;
1411                         return;
1412                 }
1413                 for (i = 0; i < n; i++) {
1414                         devpriv->ai_fifo_buffer[i] =
1415                             ni_readw(ADC_FIFO_Data_Register);
1416                 }
1417                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1418                                           n *
1419                                           sizeof(devpriv->ai_fifo_buffer[0]));
1420         }
1421 }
1422
1423 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1424 {
1425         int n;
1426         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1427
1428         n = boardtype.ai_fifo_depth / 2;
1429
1430         ni_ai_fifo_read(dev, s, n);
1431 }
1432 #endif
1433
1434 #ifdef PCIDMA
1435 static int ni_ai_drain_dma(struct comedi_device *dev)
1436 {
1437         int i;
1438         static const int timeout = 10000;
1439         unsigned long flags;
1440         int retval = 0;
1441
1442         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1443         if (devpriv->ai_mite_chan) {
1444                 for (i = 0; i < timeout; i++) {
1445                         if ((devpriv->stc_readw(dev,
1446                                                 AI_Status_1_Register) &
1447                              AI_FIFO_Empty_St)
1448                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1449                             0)
1450                                 break;
1451                         udelay(5);
1452                 }
1453                 if (i == timeout) {
1454                         printk("ni_mio_common: wait for dma drain timed out\n");
1455                         printk
1456                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1457                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1458                              devpriv->stc_readw(dev, AI_Status_1_Register));
1459                         retval = -1;
1460                 }
1461         }
1462         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1463
1464         ni_sync_ai_dma(dev);
1465
1466         return retval;
1467 }
1468 #endif
1469 /*
1470    Empties the AI fifo
1471 */
1472 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1473 {
1474         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1475         short data[2];
1476         u32 dl;
1477         short fifo_empty;
1478         int i;
1479
1480         if (boardtype.reg_type == ni_reg_611x) {
1481                 while ((devpriv->stc_readw(dev,
1482                                            AI_Status_1_Register) &
1483                         AI_FIFO_Empty_St) == 0) {
1484                         dl = ni_readl(ADC_FIFO_Data_611x);
1485
1486                         /* This may get the hi/lo data in the wrong order */
1487                         data[0] = (dl >> 16);
1488                         data[1] = (dl & 0xffff);
1489                         cfc_write_array_to_buffer(s, data, sizeof(data));
1490                 }
1491         } else if (boardtype.reg_type == ni_reg_6143) {
1492                 i = 0;
1493                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1494                         dl = ni_readl(AIFIFO_Data_6143);
1495
1496                         /* This may get the hi/lo data in the wrong order */
1497                         data[0] = (dl >> 16);
1498                         data[1] = (dl & 0xffff);
1499                         cfc_write_array_to_buffer(s, data, sizeof(data));
1500                         i += 2;
1501                 }
1502                 /*  Check if stranded sample is present */
1503                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1504                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1505                         dl = ni_readl(AIFIFO_Data_6143);
1506                         data[0] = (dl >> 16) & 0xffff;
1507                         cfc_write_to_buffer(s, data[0]);
1508                 }
1509
1510         } else {
1511                 fifo_empty =
1512                     devpriv->stc_readw(dev,
1513                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1514                 while (fifo_empty == 0) {
1515                         for (i = 0;
1516                              i <
1517                              sizeof(devpriv->ai_fifo_buffer) /
1518                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1519                                 fifo_empty =
1520                                     devpriv->stc_readw(dev,
1521                                                        AI_Status_1_Register) &
1522                                     AI_FIFO_Empty_St;
1523                                 if (fifo_empty)
1524                                         break;
1525                                 devpriv->ai_fifo_buffer[i] =
1526                                     ni_readw(ADC_FIFO_Data_Register);
1527                         }
1528                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1529                                                   i *
1530                                                   sizeof(devpriv->
1531                                                          ai_fifo_buffer[0]));
1532                 }
1533         }
1534 }
1535
1536 static void get_last_sample_611x(struct comedi_device *dev)
1537 {
1538         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1539         short data;
1540         u32 dl;
1541
1542         if (boardtype.reg_type != ni_reg_611x)
1543                 return;
1544
1545         /* Check if there's a single sample stuck in the FIFO */
1546         if (ni_readb(XXX_Status) & 0x80) {
1547                 dl = ni_readl(ADC_FIFO_Data_611x);
1548                 data = (dl & 0xffff);
1549                 cfc_write_to_buffer(s, data);
1550         }
1551 }
1552
1553 static void get_last_sample_6143(struct comedi_device *dev)
1554 {
1555         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1556         short data;
1557         u32 dl;
1558
1559         if (boardtype.reg_type != ni_reg_6143)
1560                 return;
1561
1562         /* Check if there's a single sample stuck in the FIFO */
1563         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1564                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1565                 dl = ni_readl(AIFIFO_Data_6143);
1566
1567                 /* This may get the hi/lo data in the wrong order */
1568                 data = (dl >> 16) & 0xffff;
1569                 cfc_write_to_buffer(s, data);
1570         }
1571 }
1572
1573 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1574                         void *data, unsigned int num_bytes,
1575                         unsigned int chan_index)
1576 {
1577         struct comedi_async *async = s->async;
1578         unsigned int i;
1579         unsigned int length = num_bytes / bytes_per_sample(s);
1580         short *array = data;
1581         unsigned int *larray = data;
1582         for (i = 0; i < length; i++) {
1583 #ifdef PCIDMA
1584                 if (s->subdev_flags & SDF_LSAMPL)
1585                         larray[i] = le32_to_cpu(larray[i]);
1586                 else
1587                         array[i] = le16_to_cpu(array[i]);
1588 #endif
1589                 if (s->subdev_flags & SDF_LSAMPL)
1590                         larray[i] += devpriv->ai_offset[chan_index];
1591                 else
1592                         array[i] += devpriv->ai_offset[chan_index];
1593                 chan_index++;
1594                 chan_index %= async->cmd.chanlist_len;
1595         }
1596 }
1597
1598 #ifdef PCIDMA
1599
1600 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1601 {
1602         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1603         int retval;
1604         unsigned long flags;
1605
1606         retval = ni_request_ai_mite_channel(dev);
1607         if (retval)
1608                 return retval;
1609 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1610
1611         /* write alloc the entire buffer */
1612         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1613
1614         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1615         if (devpriv->ai_mite_chan == NULL) {
1616                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1617                 return -EIO;
1618         }
1619
1620         switch (boardtype.reg_type) {
1621         case ni_reg_611x:
1622         case ni_reg_6143:
1623                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1624                 break;
1625         case ni_reg_628x:
1626                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1627                 break;
1628         default:
1629                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1630                 break;
1631         }
1632         /*start the MITE */
1633         mite_dma_arm(devpriv->ai_mite_chan);
1634         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1635
1636         return 0;
1637 }
1638
1639 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1640 {
1641         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1642         int retval;
1643         unsigned long flags;
1644
1645         retval = ni_request_ao_mite_channel(dev);
1646         if (retval)
1647                 return retval;
1648
1649         /* read alloc the entire buffer */
1650         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1651
1652         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1653         if (devpriv->ao_mite_chan) {
1654                 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1655                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1656                 } else {
1657                         /* doing 32 instead of 16 bit wide transfers from memory
1658                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1659                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1660                 }
1661                 mite_dma_arm(devpriv->ao_mite_chan);
1662         } else
1663                 retval = -EIO;
1664         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1665
1666         return retval;
1667 }
1668
1669 #endif /*  PCIDMA */
1670
1671 /*
1672    used for both cancel ioctl and board initialization
1673
1674    this is pretty harsh for a cancel, but it works...
1675  */
1676
1677 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1678 {
1679         ni_release_ai_mite_channel(dev);
1680         /* ai configuration */
1681         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1682                             Joint_Reset_Register);
1683
1684         ni_set_bits(dev, Interrupt_A_Enable_Register,
1685                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1686                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1687                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1688                     AI_FIFO_Interrupt_Enable, 0);
1689
1690         ni_clear_ai_fifo(dev);
1691
1692         if (boardtype.reg_type != ni_reg_6143)
1693                 ni_writeb(0, Misc_Command);
1694
1695         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1696         devpriv->stc_writew(dev,
1697                             AI_Start_Stop | AI_Mode_1_Reserved
1698                             /*| AI_Trigger_Once */ ,
1699                             AI_Mode_1_Register);
1700         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1701         /* generate FIFO interrupts on non-empty */
1702         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1703         if (boardtype.reg_type == ni_reg_611x) {
1704                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1705                                     AI_SOC_Polarity |
1706                                     AI_LOCALMUX_CLK_Pulse_Width,
1707                                     AI_Personal_Register);
1708                 devpriv->stc_writew(dev,
1709                                     AI_SCAN_IN_PROG_Output_Select(3) |
1710                                     AI_EXTMUX_CLK_Output_Select(0) |
1711                                     AI_LOCALMUX_CLK_Output_Select(2) |
1712                                     AI_SC_TC_Output_Select(3) |
1713                                     AI_CONVERT_Output_Select
1714                                     (AI_CONVERT_Output_Enable_High),
1715                                     AI_Output_Control_Register);
1716         } else if (boardtype.reg_type == ni_reg_6143) {
1717                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1718                                     AI_SOC_Polarity |
1719                                     AI_LOCALMUX_CLK_Pulse_Width,
1720                                     AI_Personal_Register);
1721                 devpriv->stc_writew(dev,
1722                                     AI_SCAN_IN_PROG_Output_Select(3) |
1723                                     AI_EXTMUX_CLK_Output_Select(0) |
1724                                     AI_LOCALMUX_CLK_Output_Select(2) |
1725                                     AI_SC_TC_Output_Select(3) |
1726                                     AI_CONVERT_Output_Select
1727                                     (AI_CONVERT_Output_Enable_Low),
1728                                     AI_Output_Control_Register);
1729         } else {
1730                 unsigned ai_output_control_bits;
1731                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1732                                     AI_SOC_Polarity |
1733                                     AI_CONVERT_Pulse_Width |
1734                                     AI_LOCALMUX_CLK_Pulse_Width,
1735                                     AI_Personal_Register);
1736                 ai_output_control_bits =
1737                     AI_SCAN_IN_PROG_Output_Select(3) |
1738                     AI_EXTMUX_CLK_Output_Select(0) |
1739                     AI_LOCALMUX_CLK_Output_Select(2) |
1740                     AI_SC_TC_Output_Select(3);
1741                 if (boardtype.reg_type == ni_reg_622x)
1742                         ai_output_control_bits |=
1743                             AI_CONVERT_Output_Select
1744                             (AI_CONVERT_Output_Enable_High);
1745                 else
1746                         ai_output_control_bits |=
1747                             AI_CONVERT_Output_Select
1748                             (AI_CONVERT_Output_Enable_Low);
1749                 devpriv->stc_writew(dev, ai_output_control_bits,
1750                                     AI_Output_Control_Register);
1751         }
1752         /* the following registers should not be changed, because there
1753          * are no backup registers in devpriv.  If you want to change
1754          * any of these, add a backup register and other appropriate code:
1755          *      AI_Mode_1_Register
1756          *      AI_Mode_3_Register
1757          *      AI_Personal_Register
1758          *      AI_Output_Control_Register
1759          */
1760         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1761
1762         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1763
1764         return 0;
1765 }
1766
1767 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1768 {
1769         unsigned long flags = 0;
1770         int count;
1771
1772         /*  lock to avoid race with interrupt handler */
1773         if (in_interrupt() == 0)
1774                 spin_lock_irqsave(&dev->spinlock, flags);
1775 #ifndef PCIDMA
1776         ni_handle_fifo_dregs(dev);
1777 #else
1778         ni_sync_ai_dma(dev);
1779 #endif
1780         count = s->async->buf_write_count - s->async->buf_read_count;
1781         if (in_interrupt() == 0)
1782                 spin_unlock_irqrestore(&dev->spinlock, flags);
1783
1784         return count;
1785 }
1786
1787 static int ni_ai_insn_read(struct comedi_device *dev,
1788                            struct comedi_subdevice *s, struct comedi_insn *insn,
1789                            unsigned int *data)
1790 {
1791         int i, n;
1792         const unsigned int mask = (1 << boardtype.adbits) - 1;
1793         unsigned signbits;
1794         unsigned short d;
1795         unsigned long dl;
1796
1797         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1798
1799         ni_clear_ai_fifo(dev);
1800
1801         signbits = devpriv->ai_offset[0];
1802         if (boardtype.reg_type == ni_reg_611x) {
1803                 for (n = 0; n < num_adc_stages_611x; n++) {
1804                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1805                                             AI_Command_1_Register);
1806                         udelay(1);
1807                 }
1808                 for (n = 0; n < insn->n; n++) {
1809                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1810                                             AI_Command_1_Register);
1811                         /* The 611x has screwy 32-bit FIFOs. */
1812                         d = 0;
1813                         for (i = 0; i < NI_TIMEOUT; i++) {
1814                                 if (ni_readb(XXX_Status) & 0x80) {
1815                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1816                                             & 0xffff;
1817                                         break;
1818                                 }
1819                                 if (!(devpriv->stc_readw(dev,
1820                                                          AI_Status_1_Register) &
1821                                       AI_FIFO_Empty_St)) {
1822                                         d = ni_readl(ADC_FIFO_Data_611x) &
1823                                             0xffff;
1824                                         break;
1825                                 }
1826                         }
1827                         if (i == NI_TIMEOUT) {
1828                                 printk
1829                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1830                                 return -ETIME;
1831                         }
1832                         d += signbits;
1833                         data[n] = d;
1834                 }
1835         } else if (boardtype.reg_type == ni_reg_6143) {
1836                 for (n = 0; n < insn->n; n++) {
1837                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1838                                             AI_Command_1_Register);
1839
1840                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1841                         dl = 0;
1842                         for (i = 0; i < NI_TIMEOUT; i++) {
1843                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1844                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1845                                         dl = ni_readl(AIFIFO_Data_6143);
1846                                         break;
1847                                 }
1848                         }
1849                         if (i == NI_TIMEOUT) {
1850                                 printk
1851                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1852                                 return -ETIME;
1853                         }
1854                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1855                 }
1856         } else {
1857                 for (n = 0; n < insn->n; n++) {
1858                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1859                                             AI_Command_1_Register);
1860                         for (i = 0; i < NI_TIMEOUT; i++) {
1861                                 if (!(devpriv->stc_readw(dev,
1862                                                          AI_Status_1_Register) &
1863                                       AI_FIFO_Empty_St))
1864                                         break;
1865                         }
1866                         if (i == NI_TIMEOUT) {
1867                                 printk
1868                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1869                                 return -ETIME;
1870                         }
1871                         if (boardtype.reg_type & ni_reg_m_series_mask) {
1872                                 data[n] =
1873                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1874                         } else {
1875                                 d = ni_readw(ADC_FIFO_Data_Register);
1876                                 d += signbits;  /* subtle: needs to be short addition */
1877                                 data[n] = d;
1878                         }
1879                 }
1880         }
1881         return insn->n;
1882 }
1883
1884 void ni_prime_channelgain_list(struct comedi_device *dev)
1885 {
1886         int i;
1887         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1888         for (i = 0; i < NI_TIMEOUT; ++i) {
1889                 if (!(devpriv->stc_readw(dev,
1890                                          AI_Status_1_Register) &
1891                       AI_FIFO_Empty_St)) {
1892                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1893                         return;
1894                 }
1895                 udelay(1);
1896         }
1897         printk("ni_mio_common: timeout loading channel/gain list\n");
1898 }
1899
1900 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1901                                               unsigned int n_chan,
1902                                               unsigned int *list)
1903 {
1904         unsigned int chan, range, aref;
1905         unsigned int i;
1906         unsigned offset;
1907         unsigned int dither;
1908         unsigned range_code;
1909
1910         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1911
1912 /* offset = 1 << (boardtype.adbits - 1); */
1913         if ((list[0] & CR_ALT_SOURCE)) {
1914                 unsigned bypass_bits;
1915                 chan = CR_CHAN(list[0]);
1916                 range = CR_RANGE(list[0]);
1917                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1918                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1919                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1920                 bypass_bits |= chan;
1921                 bypass_bits |=
1922                     (devpriv->ai_calib_source) &
1923                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1924                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1925                      MSeries_AI_Bypass_Mode_Mux_Mask |
1926                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1927                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1928                 if (dither)
1929                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1930                 /*  don't use 2's complement encoding */
1931                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1932                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1933         } else {
1934                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1935         }
1936         offset = 0;
1937         for (i = 0; i < n_chan; i++) {
1938                 unsigned config_bits = 0;
1939                 chan = CR_CHAN(list[i]);
1940                 aref = CR_AREF(list[i]);
1941                 range = CR_RANGE(list[i]);
1942                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1943
1944                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1945                 devpriv->ai_offset[i] = offset;
1946                 switch (aref) {
1947                 case AREF_DIFF:
1948                         config_bits |=
1949                             MSeries_AI_Config_Channel_Type_Differential_Bits;
1950                         break;
1951                 case AREF_COMMON:
1952                         config_bits |=
1953                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1954                         break;
1955                 case AREF_GROUND:
1956                         config_bits |=
1957                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1958                         break;
1959                 case AREF_OTHER:
1960                         break;
1961                 }
1962                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1963                 config_bits |=
1964                     MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1965                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1966                 if (i == n_chan - 1)
1967                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1968                 if (dither)
1969                         config_bits |= MSeries_AI_Config_Dither_Bit;
1970                 /*  don't use 2's complement encoding */
1971                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1972                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1973         }
1974         ni_prime_channelgain_list(dev);
1975 }
1976
1977 /*
1978  * Notes on the 6110 and 6111:
1979  * These boards a slightly different than the rest of the series, since
1980  * they have multiple A/D converters.
1981  * From the driver side, the configuration memory is a
1982  * little different.
1983  * Configuration Memory Low:
1984  *   bits 15-9: same
1985  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1986  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1987  *       1001 gain=0.1 (+/- 50)
1988  *       1010 0.2
1989  *       1011 0.1
1990  *       0001 1
1991  *       0010 2
1992  *       0011 5
1993  *       0100 10
1994  *       0101 20
1995  *       0110 50
1996  * Configuration Memory High:
1997  *   bits 12-14: Channel Type
1998  *       001 for differential
1999  *       000 for calibration
2000  *   bit 11: coupling  (this is not currently handled)
2001  *       1 AC coupling
2002  *       0 DC coupling
2003  *   bits 0-2: channel
2004  *       valid channels are 0-3
2005  */
2006 static void ni_load_channelgain_list(struct comedi_device *dev,
2007                                      unsigned int n_chan, unsigned int *list)
2008 {
2009         unsigned int chan, range, aref;
2010         unsigned int i;
2011         unsigned int hi, lo;
2012         unsigned offset;
2013         unsigned int dither;
2014
2015         if (boardtype.reg_type & ni_reg_m_series_mask) {
2016                 ni_m_series_load_channelgain_list(dev, n_chan, list);
2017                 return;
2018         }
2019         if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
2020             && (boardtype.reg_type != ni_reg_6143)) {
2021                 if (devpriv->changain_state
2022                     && devpriv->changain_spec == list[0]) {
2023                         /*  ready to go. */
2024                         return;
2025                 }
2026                 devpriv->changain_state = 1;
2027                 devpriv->changain_spec = list[0];
2028         } else {
2029                 devpriv->changain_state = 0;
2030         }
2031
2032         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2033
2034         /*  Set up Calibration mode if required */
2035         if (boardtype.reg_type == ni_reg_6143) {
2036                 if ((list[0] & CR_ALT_SOURCE)
2037                     && !devpriv->ai_calib_source_enabled) {
2038                         /*  Strobe Relay enable bit */
2039                         ni_writew(devpriv->ai_calib_source |
2040                                   Calibration_Channel_6143_RelayOn,
2041                                   Calibration_Channel_6143);
2042                         ni_writew(devpriv->ai_calib_source,
2043                                   Calibration_Channel_6143);
2044                         devpriv->ai_calib_source_enabled = 1;
2045                         msleep_interruptible(100);      /*  Allow relays to change */
2046                 } else if (!(list[0] & CR_ALT_SOURCE)
2047                            && devpriv->ai_calib_source_enabled) {
2048                         /*  Strobe Relay disable bit */
2049                         ni_writew(devpriv->ai_calib_source |
2050                                   Calibration_Channel_6143_RelayOff,
2051                                   Calibration_Channel_6143);
2052                         ni_writew(devpriv->ai_calib_source,
2053                                   Calibration_Channel_6143);
2054                         devpriv->ai_calib_source_enabled = 0;
2055                         msleep_interruptible(100);      /*  Allow relays to change */
2056                 }
2057         }
2058
2059         offset = 1 << (boardtype.adbits - 1);
2060         for (i = 0; i < n_chan; i++) {
2061                 if ((boardtype.reg_type != ni_reg_6143)
2062                     && (list[i] & CR_ALT_SOURCE)) {
2063                         chan = devpriv->ai_calib_source;
2064                 } else {
2065                         chan = CR_CHAN(list[i]);
2066                 }
2067                 aref = CR_AREF(list[i]);
2068                 range = CR_RANGE(list[i]);
2069                 dither = ((list[i] & CR_ALT_FILTER) != 0);
2070
2071                 /* fix the external/internal range differences */
2072                 range = ni_gainlkup[boardtype.gainlkup][range];
2073                 if (boardtype.reg_type == ni_reg_611x)
2074                         devpriv->ai_offset[i] = offset;
2075                 else
2076                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2077
2078                 hi = 0;
2079                 if ((list[i] & CR_ALT_SOURCE)) {
2080                         if (boardtype.reg_type == ni_reg_611x)
2081                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2082                                           Calibration_Channel_Select_611x);
2083                 } else {
2084                         if (boardtype.reg_type == ni_reg_611x)
2085                                 aref = AREF_DIFF;
2086                         else if (boardtype.reg_type == ni_reg_6143)
2087                                 aref = AREF_OTHER;
2088                         switch (aref) {
2089                         case AREF_DIFF:
2090                                 hi |= AI_DIFFERENTIAL;
2091                                 break;
2092                         case AREF_COMMON:
2093                                 hi |= AI_COMMON;
2094                                 break;
2095                         case AREF_GROUND:
2096                                 hi |= AI_GROUND;
2097                                 break;
2098                         case AREF_OTHER:
2099                                 break;
2100                         }
2101                 }
2102                 hi |= AI_CONFIG_CHANNEL(chan);
2103
2104                 ni_writew(hi, Configuration_Memory_High);
2105
2106                 if (boardtype.reg_type != ni_reg_6143) {
2107                         lo = range;
2108                         if (i == n_chan - 1)
2109                                 lo |= AI_LAST_CHANNEL;
2110                         if (dither)
2111                                 lo |= AI_DITHER;
2112
2113                         ni_writew(lo, Configuration_Memory_Low);
2114                 }
2115         }
2116
2117         /* prime the channel/gain list */
2118         if ((boardtype.reg_type != ni_reg_611x)
2119             && (boardtype.reg_type != ni_reg_6143)) {
2120                 ni_prime_channelgain_list(dev);
2121         }
2122 }
2123
2124 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2125                           int round_mode)
2126 {
2127         int divider;
2128         switch (round_mode) {
2129         case TRIG_ROUND_NEAREST:
2130         default:
2131                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2132                 break;
2133         case TRIG_ROUND_DOWN:
2134                 divider = (nanosec) / devpriv->clock_ns;
2135                 break;
2136         case TRIG_ROUND_UP:
2137                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2138                 break;
2139         }
2140         return divider - 1;
2141 }
2142
2143 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2144 {
2145         return devpriv->clock_ns * (timer + 1);
2146 }
2147
2148 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2149                                          unsigned num_channels)
2150 {
2151         switch (boardtype.reg_type) {
2152         case ni_reg_611x:
2153         case ni_reg_6143:
2154                 /*  simultaneously-sampled inputs */
2155                 return boardtype.ai_speed;
2156                 break;
2157         default:
2158                 /*  multiplexed inputs */
2159                 break;
2160         }
2161         return boardtype.ai_speed * num_channels;
2162 }
2163
2164 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2165                          struct comedi_cmd *cmd)
2166 {
2167         int err = 0;
2168         int tmp;
2169         int sources;
2170
2171         /* step 1: make sure trigger sources are trivially valid */
2172
2173         if ((cmd->flags & CMDF_WRITE)) {
2174                 cmd->flags &= ~CMDF_WRITE;
2175         }
2176
2177         tmp = cmd->start_src;
2178         cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
2179         if (!cmd->start_src || tmp != cmd->start_src)
2180                 err++;
2181
2182         tmp = cmd->scan_begin_src;
2183         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
2184         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2185                 err++;
2186
2187         tmp = cmd->convert_src;
2188         sources = TRIG_TIMER | TRIG_EXT;
2189         if ((boardtype.reg_type == ni_reg_611x)
2190             || (boardtype.reg_type == ni_reg_6143))
2191                 sources |= TRIG_NOW;
2192         cmd->convert_src &= sources;
2193         if (!cmd->convert_src || tmp != cmd->convert_src)
2194                 err++;
2195
2196         tmp = cmd->scan_end_src;
2197         cmd->scan_end_src &= TRIG_COUNT;
2198         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2199                 err++;
2200
2201         tmp = cmd->stop_src;
2202         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
2203         if (!cmd->stop_src || tmp != cmd->stop_src)
2204                 err++;
2205
2206         if (err)
2207                 return 1;
2208
2209         /* step 2: make sure trigger sources are unique and mutually compatible */
2210
2211         /* note that mutual compatibility is not an issue here */
2212         if (cmd->start_src != TRIG_NOW &&
2213             cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
2214                 err++;
2215         if (cmd->scan_begin_src != TRIG_TIMER &&
2216             cmd->scan_begin_src != TRIG_EXT &&
2217             cmd->scan_begin_src != TRIG_OTHER)
2218                 err++;
2219         if (cmd->convert_src != TRIG_TIMER &&
2220             cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2221                 err++;
2222         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
2223                 err++;
2224
2225         if (err)
2226                 return 2;
2227
2228         /* step 3: make sure arguments are trivially compatible */
2229
2230         if (cmd->start_src == TRIG_EXT) {
2231                 /* external trigger */
2232                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2233
2234                 if (tmp > 16)
2235                         tmp = 16;
2236                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2237                 if (cmd->start_arg != tmp) {
2238                         cmd->start_arg = tmp;
2239                         err++;
2240                 }
2241         } else {
2242                 if (cmd->start_arg != 0) {
2243                         /* true for both TRIG_NOW and TRIG_INT */
2244                         cmd->start_arg = 0;
2245                         err++;
2246                 }
2247         }
2248         if (cmd->scan_begin_src == TRIG_TIMER) {
2249                 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2250                                                                    cmd->
2251                                                                    chanlist_len))
2252                 {
2253                         cmd->scan_begin_arg =
2254                             ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
2255                         err++;
2256                 }
2257                 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2258                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2259                         err++;
2260                 }
2261         } else if (cmd->scan_begin_src == TRIG_EXT) {
2262                 /* external trigger */
2263                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2264
2265                 if (tmp > 16)
2266                         tmp = 16;
2267                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2268                 if (cmd->scan_begin_arg != tmp) {
2269                         cmd->scan_begin_arg = tmp;
2270                         err++;
2271                 }
2272         } else {                /* TRIG_OTHER */
2273                 if (cmd->scan_begin_arg) {
2274                         cmd->scan_begin_arg = 0;
2275                         err++;
2276                 }
2277         }
2278         if (cmd->convert_src == TRIG_TIMER) {
2279                 if ((boardtype.reg_type == ni_reg_611x)
2280                     || (boardtype.reg_type == ni_reg_6143)) {
2281                         if (cmd->convert_arg != 0) {
2282                                 cmd->convert_arg = 0;
2283                                 err++;
2284                         }
2285                 } else {
2286                         if (cmd->convert_arg < boardtype.ai_speed) {
2287                                 cmd->convert_arg = boardtype.ai_speed;
2288                                 err++;
2289                         }
2290                         if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2291                                 cmd->convert_arg = devpriv->clock_ns * 0xffff;
2292                                 err++;
2293                         }
2294                 }
2295         } else if (cmd->convert_src == TRIG_EXT) {
2296                 /* external trigger */
2297                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2298
2299                 if (tmp > 16)
2300                         tmp = 16;
2301                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2302                 if (cmd->convert_arg != tmp) {
2303                         cmd->convert_arg = tmp;
2304                         err++;
2305                 }
2306         } else if (cmd->convert_src == TRIG_NOW) {
2307                 if (cmd->convert_arg != 0) {
2308                         cmd->convert_arg = 0;
2309                         err++;
2310                 }
2311         }
2312
2313         if (cmd->scan_end_arg != cmd->chanlist_len) {
2314                 cmd->scan_end_arg = cmd->chanlist_len;
2315                 err++;
2316         }
2317         if (cmd->stop_src == TRIG_COUNT) {
2318                 unsigned int max_count = 0x01000000;
2319
2320                 if (boardtype.reg_type == ni_reg_611x)
2321                         max_count -= num_adc_stages_611x;
2322                 if (cmd->stop_arg > max_count) {
2323                         cmd->stop_arg = max_count;
2324                         err++;
2325                 }
2326                 if (cmd->stop_arg < 1) {
2327                         cmd->stop_arg = 1;
2328                         err++;
2329                 }
2330         } else {
2331                 /* TRIG_NONE */
2332                 if (cmd->stop_arg != 0) {
2333                         cmd->stop_arg = 0;
2334                         err++;
2335                 }
2336         }
2337
2338         if (err)
2339                 return 3;
2340
2341         /* step 4: fix up any arguments */
2342
2343         if (cmd->scan_begin_src == TRIG_TIMER) {
2344                 tmp = cmd->scan_begin_arg;
2345                 cmd->scan_begin_arg =
2346                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2347                                                        cmd->scan_begin_arg,
2348                                                        cmd->
2349                                                        flags &
2350                                                        TRIG_ROUND_MASK));
2351                 if (tmp != cmd->scan_begin_arg)
2352                         err++;
2353         }
2354         if (cmd->convert_src == TRIG_TIMER) {
2355                 if ((boardtype.reg_type != ni_reg_611x)
2356                     && (boardtype.reg_type != ni_reg_6143)) {
2357                         tmp = cmd->convert_arg;
2358                         cmd->convert_arg =
2359                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2360                                                                cmd->convert_arg,
2361                                                                cmd->
2362                                                                flags &
2363                                                                TRIG_ROUND_MASK));
2364                         if (tmp != cmd->convert_arg)
2365                                 err++;
2366                         if (cmd->scan_begin_src == TRIG_TIMER &&
2367                             cmd->scan_begin_arg <
2368                             cmd->convert_arg * cmd->scan_end_arg) {
2369                                 cmd->scan_begin_arg =
2370                                     cmd->convert_arg * cmd->scan_end_arg;
2371                                 err++;
2372                         }
2373                 }
2374         }
2375
2376         if (err)
2377                 return 4;
2378
2379         return 0;
2380 }
2381
2382 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2383 {
2384         const struct comedi_cmd *cmd = &s->async->cmd;
2385         int timer;
2386         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2387         int mode2 = 0;
2388         int start_stop_select = 0;
2389         unsigned int stop_count;
2390         int interrupt_a_enable = 0;
2391
2392         MDPRINTK("ni_ai_cmd\n");
2393         if (dev->irq == 0) {
2394                 comedi_error(dev, "cannot run command without an irq");
2395                 return -EIO;
2396         }
2397         ni_clear_ai_fifo(dev);
2398
2399         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2400
2401         /* start configuration */
2402         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2403
2404         /* disable analog triggering for now, since it
2405          * interferes with the use of pfi0 */
2406         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2407         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2408                             Analog_Trigger_Etc_Register);
2409
2410         switch (cmd->start_src) {
2411         case TRIG_INT:
2412         case TRIG_NOW:
2413                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2414                                     AI_START1_Sync | AI_START1_Edge |
2415                                     AI_START1_Select(0),
2416                                     AI_Trigger_Select_Register);
2417                 break;
2418         case TRIG_EXT:
2419                 {
2420                         int chan = CR_CHAN(cmd->start_arg);
2421                         unsigned int bits = AI_START2_Select(0) |
2422                             AI_START1_Sync | AI_START1_Select(chan + 1);
2423
2424                         if (cmd->start_arg & CR_INVERT)
2425                                 bits |= AI_START1_Polarity;
2426                         if (cmd->start_arg & CR_EDGE)
2427                                 bits |= AI_START1_Edge;
2428                         devpriv->stc_writew(dev, bits,
2429                                             AI_Trigger_Select_Register);
2430                         break;
2431                 }
2432         }
2433
2434         mode2 &= ~AI_Pre_Trigger;
2435         mode2 &= ~AI_SC_Initial_Load_Source;
2436         mode2 &= ~AI_SC_Reload_Mode;
2437         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2438
2439         if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2440             || (boardtype.reg_type == ni_reg_6143)) {
2441                 start_stop_select |= AI_STOP_Polarity;
2442                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2443                 start_stop_select |= AI_STOP_Sync;
2444         } else {
2445                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2446         }
2447         devpriv->stc_writew(dev, start_stop_select,
2448                             AI_START_STOP_Select_Register);
2449
2450         devpriv->ai_cmd2 = 0;
2451         switch (cmd->stop_src) {
2452         case TRIG_COUNT:
2453                 stop_count = cmd->stop_arg - 1;
2454
2455                 if (boardtype.reg_type == ni_reg_611x) {
2456                         /*  have to take 3 stage adc pipeline into account */
2457                         stop_count += num_adc_stages_611x;
2458                 }
2459                 /* stage number of scans */
2460                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2461
2462                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2463                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2464                 /* load SC (Scan Count) */
2465                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2466
2467                 devpriv->ai_continuous = 0;
2468                 if (stop_count == 0) {
2469                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2470                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2471                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2472                         if (cmd->chanlist_len > 1)
2473                                 start_stop_select |=
2474                                     AI_STOP_Polarity | AI_STOP_Edge;
2475                 }
2476                 break;
2477         case TRIG_NONE:
2478                 /* stage number of scans */
2479                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2480
2481                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2482                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2483
2484                 /* load SC (Scan Count) */
2485                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2486
2487                 devpriv->ai_continuous = 1;
2488
2489                 break;
2490         }
2491
2492         switch (cmd->scan_begin_src) {
2493         case TRIG_TIMER:
2494                 /*
2495                    stop bits for non 611x boards
2496                    AI_SI_Special_Trigger_Delay=0
2497                    AI_Pre_Trigger=0
2498                    AI_START_STOP_Select_Register:
2499                    AI_START_Polarity=0 (?)      rising edge
2500                    AI_START_Edge=1              edge triggered
2501                    AI_START_Sync=1 (?)
2502                    AI_START_Select=0            SI_TC
2503                    AI_STOP_Polarity=0           rising edge
2504                    AI_STOP_Edge=0               level
2505                    AI_STOP_Sync=1
2506                    AI_STOP_Select=19            external pin (configuration mem)
2507                  */
2508                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2509                 devpriv->stc_writew(dev, start_stop_select,
2510                                     AI_START_STOP_Select_Register);
2511
2512                 mode2 |= AI_SI_Reload_Mode(0);
2513                 /* AI_SI_Initial_Load_Source=A */
2514                 mode2 &= ~AI_SI_Initial_Load_Source;
2515                 /* mode2 |= AI_SC_Reload_Mode; */
2516                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2517
2518                 /* load SI */
2519                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2520                                        TRIG_ROUND_NEAREST);
2521                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2522                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2523                 break;
2524         case TRIG_EXT:
2525                 if (cmd->scan_begin_arg & CR_EDGE)
2526                         start_stop_select |= AI_START_Edge;
2527                 /* AI_START_Polarity==1 is falling edge */
2528                 if (cmd->scan_begin_arg & CR_INVERT)
2529                         start_stop_select |= AI_START_Polarity;
2530                 if (cmd->scan_begin_src != cmd->convert_src ||
2531                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2532                     (cmd->convert_arg & ~CR_EDGE))
2533                         start_stop_select |= AI_START_Sync;
2534                 start_stop_select |=
2535                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2536                 devpriv->stc_writew(dev, start_stop_select,
2537                                     AI_START_STOP_Select_Register);
2538                 break;
2539         }
2540
2541         switch (cmd->convert_src) {
2542         case TRIG_TIMER:
2543         case TRIG_NOW:
2544                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2545                         timer = 1;
2546                 else
2547                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2548                                                TRIG_ROUND_NEAREST);
2549                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2550                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2551
2552                 /* AI_SI2_Reload_Mode = alternate */
2553                 /* AI_SI2_Initial_Load_Source = A */
2554                 mode2 &= ~AI_SI2_Initial_Load_Source;
2555                 mode2 |= AI_SI2_Reload_Mode;
2556                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2557
2558                 /* AI_SI2_Load */
2559                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2560
2561                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2562                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2563
2564                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2565                 break;
2566         case TRIG_EXT:
2567                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2568                 if ((cmd->convert_arg & CR_INVERT) == 0)
2569                         mode1 |= AI_CONVERT_Source_Polarity;
2570                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2571
2572                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2573                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2574
2575                 break;
2576         }
2577
2578         if (dev->irq) {
2579
2580                 /* interrupt on FIFO, errors, SC_TC */
2581                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2582                     AI_SC_TC_Interrupt_Enable;
2583
2584 #ifndef PCIDMA
2585                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2586 #endif
2587
2588                 if (cmd->flags & TRIG_WAKE_EOS
2589                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2590                         /* wake on end-of-scan */
2591                         devpriv->aimode = AIMODE_SCAN;
2592                 } else {
2593                         devpriv->aimode = AIMODE_HALF_FULL;
2594                 }
2595
2596                 switch (devpriv->aimode) {
2597                 case AIMODE_HALF_FULL:
2598                         /*generate FIFO interrupts and DMA requests on half-full */
2599 #ifdef PCIDMA
2600                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2601                                             AI_Mode_3_Register);
2602 #else
2603                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2604                                             AI_Mode_3_Register);
2605 #endif
2606                         break;
2607                 case AIMODE_SAMPLE:
2608                         /*generate FIFO interrupts on non-empty */
2609                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2610                                             AI_Mode_3_Register);
2611                         break;
2612                 case AIMODE_SCAN:
2613 #ifdef PCIDMA
2614                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2615                                             AI_Mode_3_Register);
2616 #else
2617                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2618                                             AI_Mode_3_Register);
2619 #endif
2620                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2621                         break;
2622                 default:
2623                         break;
2624                 }
2625
2626                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2627
2628                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2629                             interrupt_a_enable, 1);
2630
2631                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2632                          devpriv->int_a_enable_reg);
2633         } else {
2634                 /* interrupt on nothing */
2635                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2636
2637                 /* XXX start polling if necessary */
2638                 MDPRINTK("interrupting on nothing\n");
2639         }
2640
2641         /* end configuration */
2642         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2643
2644         switch (cmd->scan_begin_src) {
2645         case TRIG_TIMER:
2646                 devpriv->stc_writew(dev,
2647                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2648                                     AI_SC_Arm, AI_Command_1_Register);
2649                 break;
2650         case TRIG_EXT:
2651                 /* XXX AI_SI_Arm? */
2652                 devpriv->stc_writew(dev,
2653                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2654                                     AI_SC_Arm, AI_Command_1_Register);
2655                 break;
2656         }
2657
2658 #ifdef PCIDMA
2659         {
2660                 int retval = ni_ai_setup_MITE_dma(dev);
2661                 if (retval)
2662                         return retval;
2663         }
2664         /* mite_dump_regs(devpriv->mite); */
2665 #endif
2666
2667         switch (cmd->start_src) {
2668         case TRIG_NOW:
2669                 /* AI_START1_Pulse */
2670                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2671                                     AI_Command_2_Register);
2672                 s->async->inttrig = NULL;
2673                 break;
2674         case TRIG_EXT:
2675                 s->async->inttrig = NULL;
2676                 break;
2677         case TRIG_INT:
2678                 s->async->inttrig = &ni_ai_inttrig;
2679                 break;
2680         }
2681
2682         MDPRINTK("exit ni_ai_cmd\n");
2683
2684         return 0;
2685 }
2686
2687 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2688                          unsigned int trignum)
2689 {
2690         if (trignum != 0)
2691                 return -EINVAL;
2692
2693         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2694                             AI_Command_2_Register);
2695         s->async->inttrig = NULL;
2696
2697         return 1;
2698 }
2699
2700 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2701                                     struct comedi_subdevice *s,
2702                                     struct comedi_insn *insn,
2703                                     unsigned int *data);
2704
2705 static int ni_ai_insn_config(struct comedi_device *dev,
2706                              struct comedi_subdevice *s,
2707                              struct comedi_insn *insn, unsigned int *data)
2708 {
2709         if (insn->n < 1)
2710                 return -EINVAL;
2711
2712         switch (data[0]) {
2713         case INSN_CONFIG_ANALOG_TRIG:
2714                 return ni_ai_config_analog_trig(dev, s, insn, data);
2715         case INSN_CONFIG_ALT_SOURCE:
2716                 if (boardtype.reg_type & ni_reg_m_series_mask) {
2717                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2718                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2719                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2720                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2721                                 return -EINVAL;
2722                         }
2723                         devpriv->ai_calib_source = data[1];
2724                 } else if (boardtype.reg_type == ni_reg_6143) {
2725                         unsigned int calib_source;
2726
2727                         calib_source = data[1] & 0xf;
2728
2729                         if (calib_source > 0xF)
2730                                 return -EINVAL;
2731
2732                         devpriv->ai_calib_source = calib_source;
2733                         ni_writew(calib_source, Calibration_Channel_6143);
2734                 } else {
2735                         unsigned int calib_source;
2736                         unsigned int calib_source_adjust;
2737
2738                         calib_source = data[1] & 0xf;
2739                         calib_source_adjust = (data[1] >> 4) & 0xff;
2740
2741                         if (calib_source >= 8)
2742                                 return -EINVAL;
2743                         devpriv->ai_calib_source = calib_source;
2744                         if (boardtype.reg_type == ni_reg_611x) {
2745                                 ni_writeb(calib_source_adjust,
2746                                           Cal_Gain_Select_611x);
2747                         }
2748                 }
2749                 return 2;
2750         default:
2751                 break;
2752         }
2753
2754         return -EINVAL;
2755 }
2756
2757 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2758                                     struct comedi_subdevice *s,
2759                                     struct comedi_insn *insn,
2760                                     unsigned int *data)
2761 {
2762         unsigned int a, b, modebits;
2763         int err = 0;
2764
2765         /* data[1] is flags
2766          * data[2] is analog line
2767          * data[3] is set level
2768          * data[4] is reset level */
2769         if (!boardtype.has_analog_trig)
2770                 return -EINVAL;
2771         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2772                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2773                 err++;
2774         }
2775         if (data[2] >= boardtype.n_adchan) {
2776                 data[2] = boardtype.n_adchan - 1;
2777                 err++;
2778         }
2779         if (data[3] > 255) {    /* a */
2780                 data[3] = 255;
2781                 err++;
2782         }
2783         if (data[4] > 255) {    /* b */
2784                 data[4] = 255;
2785                 err++;
2786         }
2787         /*
2788          * 00 ignore
2789          * 01 set
2790          * 10 reset
2791          *
2792          * modes:
2793          *   1 level:                    +b-   +a-
2794          *     high mode                00 00 01 10
2795          *     low mode                 00 00 10 01
2796          *   2 level: (a<b)
2797          *     hysteresis low mode      10 00 00 01
2798          *     hysteresis high mode     01 00 00 10
2799          *     middle mode              10 01 01 10
2800          */
2801
2802         a = data[3];
2803         b = data[4];
2804         modebits = data[1] & 0xff;
2805         if (modebits & 0xf0) {
2806                 /* two level mode */
2807                 if (b < a) {
2808                         /* swap order */
2809                         a = data[4];
2810                         b = data[3];
2811                         modebits =
2812                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2813                 }
2814                 devpriv->atrig_low = a;
2815                 devpriv->atrig_high = b;
2816                 switch (modebits) {
2817                 case 0x81:      /* low hysteresis mode */
2818                         devpriv->atrig_mode = 6;
2819                         break;
2820                 case 0x42:      /* high hysteresis mode */
2821                         devpriv->atrig_mode = 3;
2822                         break;
2823                 case 0x96:      /* middle window mode */
2824                         devpriv->atrig_mode = 2;
2825                         break;
2826                 default:
2827                         data[1] &= ~0xff;
2828                         err++;
2829                 }
2830         } else {
2831                 /* one level mode */
2832                 if (b != 0) {
2833                         data[4] = 0;
2834                         err++;
2835                 }
2836                 switch (modebits) {
2837                 case 0x06:      /* high window mode */
2838                         devpriv->atrig_high = a;
2839                         devpriv->atrig_mode = 0;
2840                         break;
2841                 case 0x09:      /* low window mode */
2842                         devpriv->atrig_low = a;
2843                         devpriv->atrig_mode = 1;
2844                         break;
2845                 default:
2846                         data[1] &= ~0xff;
2847                         err++;
2848                 }
2849         }
2850         if (err)
2851                 return -EAGAIN;
2852         return 5;
2853 }
2854
2855 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2856 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2857                         void *data, unsigned int num_bytes,
2858                         unsigned int chan_index)
2859 {
2860         struct comedi_async *async = s->async;
2861         unsigned int range;
2862         unsigned int i;
2863         unsigned int offset;
2864         unsigned int length = num_bytes / sizeof(short);
2865         short *array = data;
2866
2867         offset = 1 << (boardtype.aobits - 1);
2868         for (i = 0; i < length; i++) {
2869                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2870                 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2871                         array[i] -= offset;
2872 #ifdef PCIDMA
2873                 array[i] = cpu_to_le16(array[i]);
2874 #endif
2875                 chan_index++;
2876                 chan_index %= async->cmd.chanlist_len;
2877         }
2878 }
2879
2880 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2881                                           struct comedi_subdevice *s,
2882                                           unsigned int chanspec[],
2883                                           unsigned int n_chans, int timed)
2884 {
2885         unsigned int range;
2886         unsigned int chan;
2887         unsigned int conf;
2888         int i;
2889         int invert = 0;
2890
2891         if (timed) {
2892                 for (i = 0; i < boardtype.n_aochan; ++i) {
2893                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2894                         ni_writeb(devpriv->ao_conf[i],
2895                                   M_Offset_AO_Config_Bank(i));
2896                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2897                 }
2898         }
2899         for (i = 0; i < n_chans; i++) {
2900                 const struct comedi_krange *krange;
2901                 chan = CR_CHAN(chanspec[i]);
2902                 range = CR_RANGE(chanspec[i]);
2903                 krange = s->range_table->range + range;
2904                 invert = 0;
2905                 conf = 0;
2906                 switch (krange->max - krange->min) {
2907                 case 20000000:
2908                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2909                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2910                         break;
2911                 case 10000000:
2912                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2913                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2914                         break;
2915                 case 4000000:
2916                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2917                         ni_writeb(MSeries_Attenuate_x5_Bit,
2918                                   M_Offset_AO_Reference_Attenuation(chan));
2919                         break;
2920                 case 2000000:
2921                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2922                         ni_writeb(MSeries_Attenuate_x5_Bit,
2923                                   M_Offset_AO_Reference_Attenuation(chan));
2924                         break;
2925                 default:
2926                         printk("%s: bug! unhandled ao reference voltage\n",
2927                                __func__);
2928                         break;
2929                 }
2930                 switch (krange->max + krange->min) {
2931                 case 0:
2932                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2933                         break;
2934                 case 10000000:
2935                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2936                         break;
2937                 default:
2938                         printk("%s: bug! unhandled ao offset voltage\n",
2939                                __func__);
2940                         break;
2941                 }
2942                 if (timed)
2943                         conf |= MSeries_AO_Update_Timed_Bit;
2944                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2945                 devpriv->ao_conf[chan] = conf;
2946                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2947         }
2948         return invert;
2949 }
2950
2951 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2952                                      struct comedi_subdevice *s,
2953                                      unsigned int chanspec[],
2954                                      unsigned int n_chans)
2955 {
2956         unsigned int range;
2957         unsigned int chan;
2958         unsigned int conf;
2959         int i;
2960         int invert = 0;
2961
2962         for (i = 0; i < n_chans; i++) {
2963                 chan = CR_CHAN(chanspec[i]);
2964                 range = CR_RANGE(chanspec[i]);
2965                 conf = AO_Channel(chan);
2966
2967                 if (boardtype.ao_unipolar) {
2968                         if ((range & 1) == 0) {
2969                                 conf |= AO_Bipolar;
2970                                 invert = (1 << (boardtype.aobits - 1));
2971                         } else {
2972                                 invert = 0;
2973                         }
2974                         if (range & 2)
2975                                 conf |= AO_Ext_Ref;
2976                 } else {
2977                         conf |= AO_Bipolar;
2978                         invert = (1 << (boardtype.aobits - 1));
2979                 }
2980
2981                 /* not all boards can deglitch, but this shouldn't hurt */
2982                 if (chanspec[i] & CR_DEGLITCH)
2983                         conf |= AO_Deglitch;
2984
2985                 /* analog reference */
2986                 /* AREF_OTHER connects AO ground to AI ground, i think */
2987                 conf |= (CR_AREF(chanspec[i]) ==
2988                          AREF_OTHER) ? AO_Ground_Ref : 0;
2989
2990                 ni_writew(conf, AO_Configuration);
2991                 devpriv->ao_conf[chan] = conf;
2992         }
2993         return invert;
2994 }
2995
2996 static int ni_ao_config_chanlist(struct comedi_device *dev,
2997                                  struct comedi_subdevice *s,
2998                                  unsigned int chanspec[], unsigned int n_chans,
2999                                  int timed)
3000 {
3001         if (boardtype.reg_type & ni_reg_m_series_mask)
3002                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3003                                                       timed);
3004         else
3005                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3006 }
3007
3008 static int ni_ao_insn_read(struct comedi_device *dev,
3009                            struct comedi_subdevice *s, struct comedi_insn *insn,
3010                            unsigned int *data)
3011 {
3012         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3013
3014         return 1;
3015 }
3016
3017 static int ni_ao_insn_write(struct comedi_device *dev,
3018                             struct comedi_subdevice *s,
3019                             struct comedi_insn *insn, unsigned int *data)
3020 {
3021         unsigned int chan = CR_CHAN(insn->chanspec);
3022         unsigned int invert;
3023
3024         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3025
3026         devpriv->ao[chan] = data[0];
3027
3028         if (boardtype.reg_type & ni_reg_m_series_mask) {
3029                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3030         } else
3031                 ni_writew(data[0] ^ invert,
3032                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3033
3034         return 1;
3035 }
3036
3037 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3038                                  struct comedi_subdevice *s,
3039                                  struct comedi_insn *insn, unsigned int *data)
3040 {
3041         unsigned int chan = CR_CHAN(insn->chanspec);
3042         unsigned int invert;
3043
3044         ao_win_out(1 << chan, AO_Immediate_671x);
3045         invert = 1 << (boardtype.aobits - 1);
3046
3047         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3048
3049         devpriv->ao[chan] = data[0];
3050         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3051
3052         return 1;
3053 }
3054
3055 static int ni_ao_insn_config(struct comedi_device *dev,
3056                              struct comedi_subdevice *s,
3057                              struct comedi_insn *insn, unsigned int *data)
3058 {
3059         switch (data[0]) {
3060         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3061                 switch (data[1]) {
3062                 case COMEDI_OUTPUT:
3063                         data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
3064                         if (devpriv->mite)
3065                                 data[2] += devpriv->mite->fifo_size;
3066                         break;
3067                 case COMEDI_INPUT:
3068                         data[2] = 0;
3069                         break;
3070                 default:
3071                         return -EINVAL;
3072                         break;
3073                 }
3074                 return 0;
3075         default:
3076                 break;
3077         }
3078
3079         return -EINVAL;
3080 }
3081
3082 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3083                          unsigned int trignum)
3084 {
3085         int ret;
3086         int interrupt_b_bits;
3087         int i;
3088         static const int timeout = 1000;
3089
3090         if (trignum != 0)
3091                 return -EINVAL;
3092
3093         /* Null trig at beginning prevent ao start trigger from executing more than
3094            once per command (and doing things like trying to allocate the ao dma channel
3095            multiple times) */
3096         s->async->inttrig = NULL;
3097
3098         ni_set_bits(dev, Interrupt_B_Enable_Register,
3099                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3100         interrupt_b_bits = AO_Error_Interrupt_Enable;
3101 #ifdef PCIDMA
3102         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3103         if (boardtype.reg_type & ni_reg_6xxx_mask)
3104                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3105         ret = ni_ao_setup_MITE_dma(dev);
3106         if (ret)
3107                 return ret;
3108         ret = ni_ao_wait_for_dma_load(dev);
3109         if (ret < 0)
3110                 return ret;
3111 #else
3112         ret = ni_ao_prep_fifo(dev, s);
3113         if (ret == 0)
3114                 return -EPIPE;
3115
3116         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3117 #endif
3118
3119         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3120                             AO_Mode_3_Register);
3121         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3122         /* wait for DACs to be loaded */
3123         for (i = 0; i < timeout; i++) {
3124                 udelay(1);
3125                 if ((devpriv->stc_readw(dev,
3126                                         Joint_Status_2_Register) &
3127                      AO_TMRDACWRs_In_Progress_St) == 0)
3128                         break;
3129         }
3130         if (i == timeout) {
3131                 comedi_error(dev,
3132                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3133                 return -EIO;
3134         }
3135         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3136         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3137                             Interrupt_B_Ack_Register);
3138
3139         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3140
3141         devpriv->stc_writew(dev,
3142                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3143                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3144                             AO_Command_1_Register);
3145
3146         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3147                             AO_Command_2_Register);
3148
3149         return 0;
3150 }
3151
3152 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3153 {
3154         const struct comedi_cmd *cmd = &s->async->cmd;
3155         int bits;
3156         int i;
3157         unsigned trigvar;
3158
3159         if (dev->irq == 0) {
3160                 comedi_error(dev, "cannot run command without an irq");
3161                 return -EIO;
3162         }
3163
3164         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3165
3166         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3167
3168         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3169                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3170
3171                 bits = 0;
3172                 for (i = 0; i < cmd->chanlist_len; i++) {
3173                         int chan;
3174
3175                         chan = CR_CHAN(cmd->chanlist[i]);
3176                         bits |= 1 << chan;
3177                         ao_win_out(chan, AO_Waveform_Generation_611x);
3178                 }
3179                 ao_win_out(bits, AO_Timed_611x);
3180         }
3181
3182         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3183
3184         if (cmd->stop_src == TRIG_NONE) {
3185                 devpriv->ao_mode1 |= AO_Continuous;
3186                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3187         } else {
3188                 devpriv->ao_mode1 &= ~AO_Continuous;
3189                 devpriv->ao_mode1 |= AO_Trigger_Once;
3190         }
3191         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3192         switch (cmd->start_src) {
3193         case TRIG_INT:
3194         case TRIG_NOW:
3195                 devpriv->ao_trigger_select &=
3196                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3197                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3198                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3199                                     AO_Trigger_Select_Register);
3200                 break;
3201         case TRIG_EXT:
3202                 devpriv->ao_trigger_select =
3203                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3204                 if (cmd->start_arg & CR_INVERT)
3205                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3206                 if (cmd->start_arg & CR_EDGE)
3207                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3208                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3209                                     AO_Trigger_Select_Register);
3210                 break;
3211         default:
3212                 BUG();
3213                 break;
3214         }
3215         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3216         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3217
3218         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3219         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3220         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3221         if (cmd->stop_src == TRIG_NONE) {
3222                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3223         } else {
3224                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3225         }
3226         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3227         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3228         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3229         switch (cmd->stop_src) {
3230         case TRIG_COUNT:
3231                 if (boardtype.reg_type & ni_reg_m_series_mask) {
3232                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3233                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3234                                             AO_UC_Load_A_Register);
3235                         devpriv->stc_writew(dev, AO_UC_Load,
3236                                             AO_Command_1_Register);
3237                 } else {
3238                         devpriv->stc_writel(dev, cmd->stop_arg,
3239                                             AO_UC_Load_A_Register);
3240                         devpriv->stc_writew(dev, AO_UC_Load,
3241                                             AO_Command_1_Register);
3242                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3243                                             AO_UC_Load_A_Register);
3244                 }
3245                 break;
3246         case TRIG_NONE:
3247                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3248                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3249                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3250                 break;
3251         default:
3252                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3253                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3254                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3255         }
3256
3257         devpriv->ao_mode1 &=
3258             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3259               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3260         switch (cmd->scan_begin_src) {
3261         case TRIG_TIMER:
3262                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3263                 trigvar =
3264                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3265                                    TRIG_ROUND_NEAREST);
3266                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3267                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3268                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3269                 break;
3270         case TRIG_EXT:
3271                 devpriv->ao_mode1 |=
3272                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3273                 if (cmd->scan_begin_arg & CR_INVERT)
3274                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3275                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3276                 break;
3277         default:
3278                 BUG();
3279                 break;
3280         }
3281         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3282         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3283         devpriv->ao_mode2 &=
3284             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3285         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3286
3287         if (cmd->scan_end_arg > 1) {
3288                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3289                 devpriv->stc_writew(dev,
3290                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3291                                                           1) |
3292                                     AO_UPDATE_Output_Select
3293                                     (AO_Update_Output_High_Z),
3294                                     AO_Output_Control_Register);
3295         } else {
3296                 unsigned bits;
3297                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3298                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3299                 if (boardtype.
3300                     reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3301                         bits |= AO_Number_Of_Channels(0);
3302                 } else {
3303                         bits |=
3304                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3305                 }
3306                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3307         }
3308         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3309
3310         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3311                             AO_Command_1_Register);
3312
3313         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3314         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3315
3316         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3317 #ifdef PCIDMA
3318         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3319 #else
3320         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3321 #endif
3322         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3323         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3324
3325         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3326             AO_TMRDACWR_Pulse_Width;
3327         if (boardtype.ao_fifo_depth)
3328                 bits |= AO_FIFO_Enable;
3329         else
3330                 bits |= AO_DMA_PIO_Control;
3331 #if 0
3332         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3333            verified with bus analyzer. */
3334         if (boardtype.reg_type & ni_reg_m_series_mask)
3335                 bits |= AO_Number_Of_DAC_Packages;
3336 #endif
3337         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3338         /*  enable sending of ao dma requests */
3339         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3340
3341         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3342
3343         if (cmd->stop_src == TRIG_COUNT) {
3344                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3345                                     Interrupt_B_Ack_Register);
3346                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3347                             AO_BC_TC_Interrupt_Enable, 1);
3348         }
3349
3350         s->async->inttrig = &ni_ao_inttrig;
3351
3352         return 0;
3353 }
3354
3355 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3356                          struct comedi_cmd *cmd)
3357 {
3358         int err = 0;
3359         int tmp;
3360
3361         /* step 1: make sure trigger sources are trivially valid */
3362
3363         if ((cmd->flags & CMDF_WRITE) == 0) {
3364                 cmd->flags |= CMDF_WRITE;
3365         }
3366
3367         tmp = cmd->start_src;
3368         cmd->start_src &= TRIG_INT | TRIG_EXT;
3369         if (!cmd->start_src || tmp != cmd->start_src)
3370                 err++;
3371
3372         tmp = cmd->scan_begin_src;
3373         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3374         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3375                 err++;
3376
3377         tmp = cmd->convert_src;
3378         cmd->convert_src &= TRIG_NOW;
3379         if (!cmd->convert_src || tmp != cmd->convert_src)
3380                 err++;
3381
3382         tmp = cmd->scan_end_src;
3383         cmd->scan_end_src &= TRIG_COUNT;
3384         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3385                 err++;
3386
3387         tmp = cmd->stop_src;
3388         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
3389         if (!cmd->stop_src || tmp != cmd->stop_src)
3390                 err++;
3391
3392         if (err)
3393                 return 1;
3394
3395         /* step 2: make sure trigger sources are unique and mutually compatible */
3396
3397         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
3398                 err++;
3399
3400         if (err)
3401                 return 2;
3402
3403         /* step 3: make sure arguments are trivially compatible */
3404
3405         if (cmd->start_src == TRIG_EXT) {
3406                 /* external trigger */
3407                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3408
3409                 if (tmp > 18)
3410                         tmp = 18;
3411                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3412                 if (cmd->start_arg != tmp) {
3413                         cmd->start_arg = tmp;
3414                         err++;
3415                 }
3416         } else {
3417                 if (cmd->start_arg != 0) {
3418                         /* true for both TRIG_NOW and TRIG_INT */
3419                         cmd->start_arg = 0;
3420                         err++;
3421                 }
3422         }
3423         if (cmd->scan_begin_src == TRIG_TIMER) {
3424                 if (cmd->scan_begin_arg < boardtype.ao_speed) {
3425                         cmd->scan_begin_arg = boardtype.ao_speed;
3426                         err++;
3427                 }
3428                 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {       /* XXX check */
3429                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3430                         err++;
3431                 }
3432         }
3433         if (cmd->convert_arg != 0) {
3434                 cmd->convert_arg = 0;
3435                 err++;
3436         }
3437         if (cmd->scan_end_arg != cmd->chanlist_len) {
3438                 cmd->scan_end_arg = cmd->chanlist_len;
3439                 err++;
3440         }
3441         if (cmd->stop_src == TRIG_COUNT) {      /* XXX check */
3442                 if (cmd->stop_arg > 0x00ffffff) {
3443                         cmd->stop_arg = 0x00ffffff;
3444                         err++;
3445                 }
3446         } else {
3447                 /* TRIG_NONE */
3448                 if (cmd->stop_arg != 0) {
3449                         cmd->stop_arg = 0;
3450                         err++;
3451                 }
3452         }
3453
3454         if (err)
3455                 return 3;
3456
3457         /* step 4: fix up any arguments */
3458         if (cmd->scan_begin_src == TRIG_TIMER) {
3459                 tmp = cmd->scan_begin_arg;
3460                 cmd->scan_begin_arg =
3461                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3462                                                        cmd->scan_begin_arg,
3463                                                        cmd->
3464                                                        flags &
3465                                                        TRIG_ROUND_MASK));
3466                 if (tmp != cmd->scan_begin_arg)
3467                         err++;
3468         }
3469         if (err)
3470                 return 4;
3471
3472         /* step 5: fix up chanlist */
3473
3474         if (err)
3475                 return 5;
3476
3477         return 0;
3478 }
3479
3480 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3481 {
3482         /* devpriv->ao0p=0x0000; */
3483         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3484
3485         /* devpriv->ao1p=AO_Channel(1); */
3486         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3487
3488         ni_release_ao_mite_channel(dev);
3489
3490         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3491         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3492         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3493         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3494         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3495         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3496                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3497         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3498         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3499         devpriv->ao_cmd1 = 0;
3500         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3501         devpriv->ao_cmd2 = 0;
3502         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3503         devpriv->ao_mode1 = 0;
3504         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3505         devpriv->ao_mode2 = 0;
3506         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3507         if (boardtype.reg_type & ni_reg_m_series_mask)
3508                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3509         else
3510                 devpriv->ao_mode3 = 0;
3511         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3512         devpriv->ao_trigger_select = 0;
3513         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3514                             AO_Trigger_Select_Register);
3515         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3516                 unsigned immediate_bits = 0;
3517                 unsigned i;
3518                 for (i = 0; i < s->n_chan; ++i) {
3519                         immediate_bits |= 1 << i;
3520                 }
3521                 ao_win_out(immediate_bits, AO_Immediate_671x);
3522                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3523         }
3524         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3525
3526         return 0;
3527 }
3528
3529 /* digital io */
3530
3531 static int ni_dio_insn_config(struct comedi_device *dev,
3532                               struct comedi_subdevice *s,
3533                               struct comedi_insn *insn, unsigned int *data)
3534 {
3535 #ifdef DEBUG_DIO
3536         printk("ni_dio_insn_config() chan=%d io=%d\n",
3537                CR_CHAN(insn->chanspec), data[0]);
3538 #endif
3539         switch (data[0]) {
3540         case INSN_CONFIG_DIO_OUTPUT:
3541                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3542                 break;
3543         case INSN_CONFIG_DIO_INPUT:
3544                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3545                 break;
3546         case INSN_CONFIG_DIO_QUERY:
3547                 data[1] =
3548                     (s->
3549                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3550                     COMEDI_INPUT;
3551                 return insn->n;
3552                 break;
3553         default:
3554                 return -EINVAL;
3555         }
3556
3557         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3558         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3559         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3560
3561         return 1;
3562 }
3563
3564 static int ni_dio_insn_bits(struct comedi_device *dev,
3565                             struct comedi_subdevice *s,
3566                             struct comedi_insn *insn, unsigned int *data)
3567 {
3568 #ifdef DEBUG_DIO
3569         printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3570 #endif
3571
3572         if (data[0]) {
3573                 /* Perform check to make sure we're not using the
3574                    serial part of the dio */
3575                 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3576                     && devpriv->serial_interval_ns)
3577                         return -EBUSY;
3578
3579                 s->state &= ~data[0];
3580                 s->state |= (data[0] & data[1]);
3581                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3582                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3583                 devpriv->stc_writew(dev, devpriv->dio_output,
3584                                     DIO_Output_Register);
3585         }
3586         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3587
3588         return insn->n;
3589 }
3590
3591 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3592                                        struct comedi_subdevice *s,
3593                                        struct comedi_insn *insn,
3594                                        unsigned int *data)
3595 {
3596 #ifdef DEBUG_DIO
3597         printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3598                CR_CHAN(insn->chanspec), data[0]);
3599 #endif
3600         switch (data[0]) {
3601         case INSN_CONFIG_DIO_OUTPUT:
3602                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3603                 break;
3604         case INSN_CONFIG_DIO_INPUT:
3605                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3606                 break;
3607         case INSN_CONFIG_DIO_QUERY:
3608                 data[1] =
3609                     (s->
3610                      io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3611                     COMEDI_INPUT;
3612                 return insn->n;
3613                 break;
3614         default:
3615                 return -EINVAL;
3616         }
3617
3618         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3619
3620         return 1;
3621 }
3622
3623 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3624                                      struct comedi_subdevice *s,
3625                                      struct comedi_insn *insn,
3626                                      unsigned int *data)
3627 {
3628 #ifdef DEBUG_DIO
3629         printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3630                data[1]);
3631 #endif
3632
3633         if (data[0]) {
3634                 s->state &= ~data[0];
3635                 s->state |= (data[0] & data[1]);
3636                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3637         }
3638         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3639
3640         return insn->n;
3641 }
3642
3643 static int ni_cdio_cmdtest(struct comedi_device *dev,
3644                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3645 {
3646         int err = 0;
3647         int tmp;
3648         int sources;
3649         unsigned i;
3650
3651         /* step 1: make sure trigger sources are trivially valid */
3652
3653         tmp = cmd->start_src;
3654         sources = TRIG_INT;
3655         cmd->start_src &= sources;
3656         if (!cmd->start_src || tmp != cmd->start_src)
3657                 err++;
3658
3659         tmp = cmd->scan_begin_src;
3660         cmd->scan_begin_src &= TRIG_EXT;
3661         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3662                 err++;
3663
3664         tmp = cmd->convert_src;
3665         cmd->convert_src &= TRIG_NOW;
3666         if (!cmd->convert_src || tmp != cmd->convert_src)
3667                 err++;
3668
3669         tmp = cmd->scan_end_src;
3670         cmd->scan_end_src &= TRIG_COUNT;
3671         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3672                 err++;
3673
3674         tmp = cmd->stop_src;
3675         cmd->stop_src &= TRIG_NONE;
3676         if (!cmd->stop_src || tmp != cmd->stop_src)
3677                 err++;
3678
3679         if (err)
3680                 return 1;
3681
3682         /* step 2: make sure trigger sources are unique... */
3683
3684         if (cmd->start_src != TRIG_INT)
3685                 err++;
3686         if (cmd->scan_begin_src != TRIG_EXT)
3687                 err++;
3688         if (cmd->convert_src != TRIG_NOW)
3689                 err++;
3690         if (cmd->stop_src != TRIG_NONE)
3691                 err++;
3692         /* ... and mutually compatible */
3693
3694         if (err)
3695                 return 2;
3696
3697         /* step 3: make sure arguments are trivially compatible */
3698         if (cmd->start_src == TRIG_INT) {
3699                 if (cmd->start_arg != 0) {
3700                         cmd->start_arg = 0;
3701                         err++;
3702                 }
3703         }
3704         if (cmd->scan_begin_src == TRIG_EXT) {
3705                 tmp = cmd->scan_begin_arg;
3706                 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3707                                      CR_INVERT);
3708                 if (tmp != cmd->scan_begin_arg) {
3709                         err++;
3710                 }
3711         }
3712         if (cmd->convert_src == TRIG_NOW) {
3713                 if (cmd->convert_arg) {
3714                         cmd->convert_arg = 0;
3715                         err++;
3716                 }
3717         }
3718
3719         if (cmd->scan_end_arg != cmd->chanlist_len) {
3720                 cmd->scan_end_arg = cmd->chanlist_len;
3721                 err++;
3722         }
3723
3724         if (cmd->stop_src == TRIG_NONE) {
3725                 if (cmd->stop_arg != 0) {
3726                         cmd->stop_arg = 0;
3727                         err++;
3728                 }
3729         }
3730
3731         if (err)
3732                 return 3;
3733
3734         /* step 4: fix up any arguments */
3735
3736         if (err)
3737                 return 4;
3738
3739         /* step 5: check chanlist */
3740
3741         for (i = 0; i < cmd->chanlist_len; ++i) {
3742                 if (cmd->chanlist[i] != i)
3743                         err = 1;
3744         }
3745
3746         if (err)
3747                 return 5;
3748
3749         return 0;
3750 }
3751
3752 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3753 {
3754         const struct comedi_cmd *cmd = &s->async->cmd;
3755         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3756         int retval;
3757
3758         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3759         switch (cmd->scan_begin_src) {
3760         case TRIG_EXT:
3761                 cdo_mode_bits |=
3762                     CR_CHAN(cmd->scan_begin_arg) &
3763                     CDO_Sample_Source_Select_Mask;
3764                 break;
3765         default:
3766                 BUG();
3767                 break;
3768         }
3769         if (cmd->scan_begin_arg & CR_INVERT)
3770                 cdo_mode_bits |= CDO_Polarity_Bit;
3771         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3772         if (s->io_bits) {
3773                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3774                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3775                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3776         } else {
3777                 comedi_error(dev,
3778                              "attempted to run digital output command with no lines configured as outputs");
3779                 return -EIO;
3780         }
3781         retval = ni_request_cdo_mite_channel(dev);
3782         if (retval < 0) {
3783                 return retval;
3784         }
3785         s->async->inttrig = &ni_cdo_inttrig;
3786         return 0;
3787 }
3788
3789 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3790                           unsigned int trignum)
3791 {
3792 #ifdef PCIDMA
3793         unsigned long flags;
3794 #endif
3795         int retval = 0;
3796         unsigned i;
3797         const unsigned timeout = 1000;
3798
3799         s->async->inttrig = NULL;
3800
3801         /* read alloc the entire buffer */
3802         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3803
3804 #ifdef PCIDMA
3805         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3806         if (devpriv->cdo_mite_chan) {
3807                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3808                 mite_dma_arm(devpriv->cdo_mite_chan);
3809         } else {
3810                 comedi_error(dev, "BUG: no cdo mite channel?");
3811                 retval = -EIO;
3812         }
3813         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3814         if (retval < 0)
3815                 return retval;
3816 #endif
3817 /*
3818 * XXX not sure what interrupt C group does
3819 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3820 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3821 */
3822         for (i = 0; i < timeout; ++i) {
3823                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3824                         break;
3825                 udelay(10);
3826         }
3827         if (i == timeout) {
3828                 comedi_error(dev, "dma failed to fill cdo fifo!");
3829                 ni_cdio_cancel(dev, s);
3830                 return -EIO;
3831         }
3832         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3833                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3834                   M_Offset_CDIO_Command);
3835         return retval;
3836 }
3837
3838 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3839 {
3840         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3841                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3842                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3843                   M_Offset_CDIO_Command);
3844 /*
3845 * XXX not sure what interrupt C group does ni_writeb(0,
3846 * M_Offset_Interrupt_C_Enable);
3847 */
3848         ni_writel(0, M_Offset_CDO_Mask_Enable);
3849         ni_release_cdo_mite_channel(dev);
3850         return 0;
3851 }
3852
3853 static void handle_cdio_interrupt(struct comedi_device *dev)
3854 {
3855         unsigned cdio_status;
3856         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3857 #ifdef PCIDMA
3858         unsigned long flags;
3859 #endif
3860
3861         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3862                 return;
3863         }
3864 #ifdef PCIDMA
3865         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3866         if (devpriv->cdo_mite_chan) {
3867                 unsigned cdo_mite_status =
3868                     mite_get_status(devpriv->cdo_mite_chan);
3869                 if (cdo_mite_status & CHSR_LINKC) {
3870                         writel(CHOR_CLRLC,
3871                                devpriv->mite->mite_io_addr +
3872                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3873                 }
3874                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3875         }
3876         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3877 #endif
3878
3879         cdio_status = ni_readl(M_Offset_CDIO_Status);
3880         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3881 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3882                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3883                 s->async->events |= COMEDI_CB_OVERFLOW;
3884         }
3885         if (cdio_status & CDO_FIFO_Empty_Bit) {
3886 /* printk("cdio fifo empty\n"); */
3887                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3888                           M_Offset_CDIO_Command);
3889 /* s->async->events |= COMEDI_CB_EOA; */
3890         }
3891         ni_event(dev, s);
3892 }
3893
3894 static int ni_serial_insn_config(struct comedi_device *dev,
3895                                  struct comedi_subdevice *s,
3896                                  struct comedi_insn *insn, unsigned int *data)
3897 {
3898         int err = insn->n;
3899         unsigned char byte_out, byte_in = 0;
3900
3901         if (insn->n != 2)
3902                 return -EINVAL;
3903
3904         switch (data[0]) {
3905         case INSN_CONFIG_SERIAL_CLOCK:
3906
3907 #ifdef DEBUG_DIO
3908                 printk("SPI serial clock Config cd\n", data[1]);
3909 #endif
3910                 devpriv->serial_hw_mode = 1;
3911                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3912
3913                 if (data[1] == SERIAL_DISABLED) {
3914                         devpriv->serial_hw_mode = 0;
3915                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3916                                                   DIO_Software_Serial_Control);
3917                         data[1] = SERIAL_DISABLED;
3918                         devpriv->serial_interval_ns = data[1];
3919                 } else if (data[1] <= SERIAL_600NS) {
3920                         /* Warning: this clock speed is too fast to reliably
3921                            control SCXI. */
3922                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3923                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3924                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3925                         data[1] = SERIAL_600NS;
3926                         devpriv->serial_interval_ns = data[1];
3927                 } else if (data[1] <= SERIAL_1_2US) {
3928                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3929                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3930                             DIO_Serial_Out_Divide_By_2;
3931                         data[1] = SERIAL_1_2US;
3932                         devpriv->serial_interval_ns = data[1];
3933                 } else if (data[1] <= SERIAL_10US) {
3934                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3935                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3936                             DIO_Serial_Out_Divide_By_2;
3937                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3938                            600ns/1.2us. If you turn divide_by_2 off with the
3939                            slow clock, you will still get 10us, except then
3940                            all your delays are wrong. */
3941                         data[1] = SERIAL_10US;
3942                         devpriv->serial_interval_ns = data[1];
3943                 } else {
3944                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3945                                                   DIO_Software_Serial_Control);
3946                         devpriv->serial_hw_mode = 0;
3947                         data[1] = (data[1] / 1000) * 1000;
3948                         devpriv->serial_interval_ns = data[1];
3949                 }
3950
3951                 devpriv->stc_writew(dev, devpriv->dio_control,
3952                                     DIO_Control_Register);
3953                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3954                                     Clock_and_FOUT_Register);
3955                 return 1;
3956
3957                 break;
3958
3959         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3960
3961                 if (devpriv->serial_interval_ns == 0) {
3962                         return -EINVAL;
3963                 }
3964
3965                 byte_out = data[1] & 0xFF;
3966
3967                 if (devpriv->serial_hw_mode) {
3968                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3969                                                       &byte_in);
3970                 } else if (devpriv->serial_interval_ns > 0) {
3971                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3972                                                       &byte_in);
3973                 } else {
3974                         printk("ni_serial_insn_config: serial disabled!\n");
3975                         return -EINVAL;
3976                 }
3977                 if (err < 0)
3978                         return err;
3979                 data[1] = byte_in & 0xFF;
3980                 return insn->n;
3981
3982                 break;
3983         default:
3984                 return -EINVAL;
3985         }
3986
3987 }
3988
3989 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3990                                    struct comedi_subdevice *s,
3991                                    unsigned char data_out,
3992                                    unsigned char *data_in)
3993 {
3994         unsigned int status1;
3995         int err = 0, count = 20;
3996
3997 #ifdef DEBUG_DIO
3998         printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3999 #endif
4000
4001         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
4002         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
4003         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
4004
4005         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
4006         if (status1 & DIO_Serial_IO_In_Progress_St) {
4007                 err = -EBUSY;
4008                 goto Error;
4009         }
4010
4011         devpriv->dio_control |= DIO_HW_Serial_Start;
4012         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4013         devpriv->dio_control &= ~DIO_HW_Serial_Start;
4014
4015         /* Wait until STC says we're done, but don't loop infinitely. */
4016         while ((status1 =
4017                 devpriv->stc_readw(dev,
4018                                    Joint_Status_1_Register)) &
4019                DIO_Serial_IO_In_Progress_St) {
4020                 /* Delay one bit per loop */
4021                 udelay((devpriv->serial_interval_ns + 999) / 1000);
4022                 if (--count < 0) {
4023                         printk
4024                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
4025                         err = -ETIME;
4026                         goto Error;
4027                 }
4028         }
4029
4030         /* Delay for last bit. This delay is absolutely necessary, because
4031            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
4032         udelay((devpriv->serial_interval_ns + 999) / 1000);
4033
4034         if (data_in != NULL) {
4035                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4036 #ifdef DEBUG_DIO
4037                 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4038 #endif
4039         }
4040
4041 Error:
4042         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4043
4044         return err;
4045 }
4046
4047 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4048                                    struct comedi_subdevice *s,
4049                                    unsigned char data_out,
4050                                    unsigned char *data_in)
4051 {
4052         unsigned char mask, input = 0;
4053
4054 #ifdef DEBUG_DIO
4055         printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4056 #endif
4057
4058         /* Wait for one bit before transfer */
4059         udelay((devpriv->serial_interval_ns + 999) / 1000);
4060
4061         for (mask = 0x80; mask; mask >>= 1) {
4062                 /* Output current bit; note that we cannot touch s->state
4063                    because it is a per-subdevice field, and serial is
4064                    a separate subdevice from DIO. */
4065                 devpriv->dio_output &= ~DIO_SDOUT;
4066                 if (data_out & mask) {
4067                         devpriv->dio_output |= DIO_SDOUT;
4068                 }
4069                 devpriv->stc_writew(dev, devpriv->dio_output,
4070                                     DIO_Output_Register);
4071
4072                 /* Assert SDCLK (active low, inverted), wait for half of
4073                    the delay, deassert SDCLK, and wait for the other half. */
4074                 devpriv->dio_control |= DIO_Software_Serial_Control;
4075                 devpriv->stc_writew(dev, devpriv->dio_control,
4076                                     DIO_Control_Register);
4077
4078                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4079
4080                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4081                 devpriv->stc_writew(dev, devpriv->dio_control,
4082                                     DIO_Control_Register);
4083
4084                 udelay((devpriv->serial_interval_ns + 999) / 2000);
4085
4086                 /* Input current bit */
4087                 if (devpriv->stc_readw(dev,
4088                                        DIO_Parallel_Input_Register) & DIO_SDIN)
4089                 {
4090 /*                      printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4091                         input |= mask;
4092                 }
4093         }
4094 #ifdef DEBUG_DIO
4095         printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4096 #endif
4097         if (data_in)
4098                 *data_in = input;
4099
4100         return 0;
4101 }
4102
4103 static void mio_common_detach(struct comedi_device *dev)
4104 {
4105         struct comedi_subdevice *s;
4106
4107         if (dev->private) {
4108                 if (devpriv->counter_dev) {
4109                         ni_gpct_device_destroy(devpriv->counter_dev);
4110                 }
4111         }
4112         if (dev->subdevices && boardtype.has_8255) {
4113                 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4114                 subdev_8255_cleanup(dev, s);
4115         }
4116 }
4117
4118 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4119 {
4120         int i;
4121
4122         for (i = 0; i < s->n_chan; i++) {
4123                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4124                                AO_Configuration_2_67xx);
4125         }
4126         ao_win_out(0x0, AO_Later_Single_Point_Updates);
4127 }
4128
4129 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4130 {
4131         unsigned stc_register;
4132         switch (reg) {
4133         case NITIO_G0_Autoincrement_Reg:
4134                 stc_register = G_Autoincrement_Register(0);
4135                 break;
4136         case NITIO_G1_Autoincrement_Reg:
4137                 stc_register = G_Autoincrement_Register(1);
4138                 break;
4139         case NITIO_G0_Command_Reg:
4140                 stc_register = G_Command_Register(0);
4141                 break;
4142         case NITIO_G1_Command_Reg:
4143                 stc_register = G_Command_Register(1);
4144                 break;
4145         case NITIO_G0_HW_Save_Reg:
4146                 stc_register = G_HW_Save_Register(0);
4147                 break;
4148         case NITIO_G1_HW_Save_Reg:
4149                 stc_register = G_HW_Save_Register(1);
4150                 break;
4151         case NITIO_G0_SW_Save_Reg:
4152                 stc_register = G_Save_Register(0);
4153                 break;
4154         case NITIO_G1_SW_Save_Reg:
4155                 stc_register = G_Save_Register(1);
4156                 break;
4157         case NITIO_G0_Mode_Reg:
4158                 stc_register = G_Mode_Register(0);
4159                 break;
4160         case NITIO_G1_Mode_Reg:
4161                 stc_register = G_Mode_Register(1);
4162                 break;
4163         case NITIO_G0_LoadA_Reg:
4164                 stc_register = G_Load_A_Register(0);
4165                 break;
4166         case NITIO_G1_LoadA_Reg:
4167                 stc_register = G_Load_A_Register(1);
4168                 break;
4169         case NITIO_G0_LoadB_Reg:
4170                 stc_register = G_Load_B_Register(0);
4171                 break;
4172         case NITIO_G1_LoadB_Reg:
4173                 stc_register = G_Load_B_Register(1);
4174                 break;
4175         case NITIO_G0_Input_Select_Reg:
4176                 stc_register = G_Input_Select_Register(0);
4177                 break;
4178         case NITIO_G1_Input_Select_Reg:
4179                 stc_register = G_Input_Select_Register(1);
4180                 break;
4181         case NITIO_G01_Status_Reg:
4182                 stc_register = G_Status_Register;
4183                 break;
4184         case NITIO_G01_Joint_Reset_Reg:
4185                 stc_register = Joint_Reset_Register;
4186                 break;
4187         case NITIO_G01_Joint_Status1_Reg:
4188                 stc_register = Joint_Status_1_Register;
4189                 break;
4190         case NITIO_G01_Joint_Status2_Reg:
4191                 stc_register = Joint_Status_2_Register;
4192                 break;
4193         case NITIO_G0_Interrupt_Acknowledge_Reg:
4194                 stc_register = Interrupt_A_Ack_Register;
4195                 break;
4196         case NITIO_G1_Interrupt_Acknowledge_Reg:
4197                 stc_register = Interrupt_B_Ack_Register;
4198                 break;
4199         case NITIO_G0_Status_Reg:
4200                 stc_register = AI_Status_1_Register;
4201                 break;
4202         case NITIO_G1_Status_Reg:
4203                 stc_register = AO_Status_1_Register;
4204                 break;
4205         case NITIO_G0_Interrupt_Enable_Reg:
4206                 stc_register = Interrupt_A_Enable_Register;
4207                 break;
4208         case NITIO_G1_Interrupt_Enable_Reg:
4209                 stc_register = Interrupt_B_Enable_Register;
4210                 break;
4211         default:
4212                 printk("%s: unhandled register 0x%x in switch.\n",
4213                        __func__, reg);
4214                 BUG();
4215                 return 0;
4216                 break;
4217         }
4218         return stc_register;
4219 }
4220
4221 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4222                                    enum ni_gpct_register reg)
4223 {
4224         struct comedi_device *dev = counter->counter_dev->dev;
4225         unsigned stc_register;
4226         /* bits in the join reset register which are relevant to counters */
4227         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4228         static const unsigned gpct_interrupt_a_enable_mask =
4229             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4230         static const unsigned gpct_interrupt_b_enable_mask =
4231             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4232
4233         switch (reg) {
4234                 /* m-series-only registers */
4235         case NITIO_G0_Counting_Mode_Reg:
4236                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4237                 break;
4238         case NITIO_G1_Counting_Mode_Reg:
4239                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4240                 break;
4241         case NITIO_G0_Second_Gate_Reg:
4242                 ni_writew(bits, M_Offset_G0_Second_Gate);
4243                 break;
4244         case NITIO_G1_Second_Gate_Reg:
4245                 ni_writew(bits, M_Offset_G1_Second_Gate);
4246                 break;
4247         case NITIO_G0_DMA_Config_Reg:
4248                 ni_writew(bits, M_Offset_G0_DMA_Config);
4249                 break;
4250         case NITIO_G1_DMA_Config_Reg:
4251                 ni_writew(bits, M_Offset_G1_DMA_Config);
4252                 break;
4253         case NITIO_G0_ABZ_Reg:
4254                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4255                 break;
4256         case NITIO_G1_ABZ_Reg:
4257                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4258                 break;
4259
4260                 /* 32 bit registers */
4261         case NITIO_G0_LoadA_Reg:
4262         case NITIO_G1_LoadA_Reg:
4263         case NITIO_G0_LoadB_Reg:
4264         case NITIO_G1_LoadB_Reg:
4265                 stc_register = ni_gpct_to_stc_register(reg);
4266                 devpriv->stc_writel(dev, bits, stc_register);
4267                 break;
4268
4269                 /* 16 bit registers */
4270         case NITIO_G0_Interrupt_Enable_Reg:
4271                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4272                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4273                                 gpct_interrupt_a_enable_mask, bits);
4274                 break;
4275         case NITIO_G1_Interrupt_Enable_Reg:
4276                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4277                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4278                                 gpct_interrupt_b_enable_mask, bits);
4279                 break;
4280         case NITIO_G01_Joint_Reset_Reg:
4281                 BUG_ON(bits & ~gpct_joint_reset_mask);
4282                 /* fall-through */
4283         default:
4284                 stc_register = ni_gpct_to_stc_register(reg);
4285                 devpriv->stc_writew(dev, bits, stc_register);
4286         }
4287 }
4288
4289 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4290                                       enum ni_gpct_register reg)
4291 {
4292         struct comedi_device *dev = counter->counter_dev->dev;
4293         unsigned stc_register;
4294         switch (reg) {
4295                 /* m-series only registers */
4296         case NITIO_G0_DMA_Status_Reg:
4297                 return ni_readw(M_Offset_G0_DMA_Status);
4298                 break;
4299         case NITIO_G1_DMA_Status_Reg:
4300                 return ni_readw(M_Offset_G1_DMA_Status);
4301                 break;
4302
4303                 /* 32 bit registers */
4304         case NITIO_G0_HW_Save_Reg:
4305         case NITIO_G1_HW_Save_Reg:
4306         case NITIO_G0_SW_Save_Reg:
4307         case NITIO_G1_SW_Save_Reg:
4308                 stc_register = ni_gpct_to_stc_register(reg);
4309                 return devpriv->stc_readl(dev, stc_register);
4310                 break;
4311
4312                 /* 16 bit registers */
4313         default:
4314                 stc_register = ni_gpct_to_stc_register(reg);
4315                 return devpriv->stc_readw(dev, stc_register);
4316                 break;
4317         }
4318         return 0;
4319 }
4320
4321 static int ni_freq_out_insn_read(struct comedi_device *dev,
4322                                  struct comedi_subdevice *s,
4323                                  struct comedi_insn *insn, unsigned int *data)
4324 {
4325         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4326         return 1;
4327 }
4328
4329 static int ni_freq_out_insn_write(struct comedi_device *dev,
4330                                   struct comedi_subdevice *s,
4331                                   struct comedi_insn *insn, unsigned int *data)
4332 {
4333         devpriv->clock_and_fout &= ~FOUT_Enable;
4334         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4335                             Clock_and_FOUT_Register);
4336         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4337         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4338         devpriv->clock_and_fout |= FOUT_Enable;
4339         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4340                             Clock_and_FOUT_Register);
4341         return insn->n;
4342 }
4343
4344 static int ni_set_freq_out_clock(struct comedi_device *dev,
4345                                  unsigned int clock_source)
4346 {
4347         switch (clock_source) {
4348         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4349                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4350                 break;
4351         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4352                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4353                 break;
4354         default:
4355                 return -EINVAL;
4356         }
4357         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4358                             Clock_and_FOUT_Register);
4359         return 3;
4360 }
4361
4362 static void ni_get_freq_out_clock(struct comedi_device *dev,
4363                                   unsigned int *clock_source,
4364                                   unsigned int *clock_period_ns)
4365 {
4366         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4367                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4368                 *clock_period_ns = TIMEBASE_2_NS;
4369         } else {
4370                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4371                 *clock_period_ns = TIMEBASE_1_NS * 2;
4372         }
4373 }
4374
4375 static int ni_freq_out_insn_config(struct comedi_device *dev,
4376                                    struct comedi_subdevice *s,
4377                                    struct comedi_insn *insn, unsigned int *data)
4378 {
4379         switch (data[0]) {
4380         case INSN_CONFIG_SET_CLOCK_SRC:
4381                 return ni_set_freq_out_clock(dev, data[1]);
4382                 break;
4383         case INSN_CONFIG_GET_CLOCK_SRC:
4384                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4385                 return 3;
4386         default:
4387                 break;
4388         }
4389         return -EINVAL;
4390 }
4391
4392 static int ni_alloc_private(struct comedi_device *dev)
4393 {
4394         int ret;
4395
4396         ret = alloc_private(dev, sizeof(struct ni_private));
4397         if (ret < 0)
4398                 return ret;
4399
4400         spin_lock_init(&devpriv->window_lock);
4401         spin_lock_init(&devpriv->soft_reg_copy_lock);
4402         spin_lock_init(&devpriv->mite_channel_lock);
4403
4404         return 0;
4405 };
4406
4407 static int ni_E_init(struct comedi_device *dev)
4408 {
4409         struct comedi_subdevice *s;
4410         unsigned j;
4411         enum ni_gpct_variant counter_variant;
4412         int ret;
4413
4414         if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4415                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4416                 return -EINVAL;
4417         }
4418
4419         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4420         if (ret)
4421                 return ret;
4422
4423         /* analog input subdevice */
4424
4425         s = &dev->subdevices[NI_AI_SUBDEV];
4426         dev->read_subdev = s;
4427         if (boardtype.n_adchan) {
4428                 s->type = COMEDI_SUBD_AI;
4429                 s->subdev_flags =
4430                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4431                 if (boardtype.reg_type != ni_reg_611x)
4432                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4433                 if (boardtype.adbits > 16)
4434                         s->subdev_flags |= SDF_LSAMPL;
4435                 if (boardtype.reg_type & ni_reg_m_series_mask)
4436                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4437                 s->n_chan = boardtype.n_adchan;
4438                 s->len_chanlist = 512;
4439                 s->maxdata = (1 << boardtype.adbits) - 1;
4440                 s->range_table = ni_range_lkup[boardtype.gainlkup];
4441                 s->insn_read = &ni_ai_insn_read;
4442                 s->insn_config = &ni_ai_insn_config;
4443                 s->do_cmdtest = &ni_ai_cmdtest;
4444                 s->do_cmd = &ni_ai_cmd;
4445                 s->cancel = &ni_ai_reset;
4446                 s->poll = &ni_ai_poll;
4447                 s->munge = &ni_ai_munge;
4448 #ifdef PCIDMA
4449                 s->async_dma_dir = DMA_FROM_DEVICE;
4450 #endif
4451         } else {
4452                 s->type = COMEDI_SUBD_UNUSED;
4453         }
4454
4455         /* analog output subdevice */
4456
4457         s = &dev->subdevices[NI_AO_SUBDEV];
4458         if (boardtype.n_aochan) {
4459                 s->type = COMEDI_SUBD_AO;
4460                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4461                 if (boardtype.reg_type & ni_reg_m_series_mask)
4462                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4463                 s->n_chan = boardtype.n_aochan;
4464                 s->maxdata = (1 << boardtype.aobits) - 1;
4465                 s->range_table = boardtype.ao_range_table;
4466                 s->insn_read = &ni_ao_insn_read;
4467                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4468                         s->insn_write = &ni_ao_insn_write_671x;
4469                 } else {
4470                         s->insn_write = &ni_ao_insn_write;
4471                 }
4472                 s->insn_config = &ni_ao_insn_config;
4473 #ifdef PCIDMA
4474                 if (boardtype.n_aochan) {
4475                         s->async_dma_dir = DMA_TO_DEVICE;
4476 #else
4477                 if (boardtype.ao_fifo_depth) {
4478 #endif
4479                         dev->write_subdev = s;
4480                         s->subdev_flags |= SDF_CMD_WRITE;
4481                         s->do_cmd = &ni_ao_cmd;
4482                         s->do_cmdtest = &ni_ao_cmdtest;
4483                         s->len_chanlist = boardtype.n_aochan;
4484                         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4485                                 s->munge = ni_ao_munge;
4486                 }
4487                 s->cancel = &ni_ao_reset;
4488         } else {
4489                 s->type = COMEDI_SUBD_UNUSED;
4490         }
4491         if ((boardtype.reg_type & ni_reg_67xx_mask))
4492                 init_ao_67xx(dev, s);
4493
4494         /* digital i/o subdevice */
4495
4496         s = &dev->subdevices[NI_DIO_SUBDEV];
4497         s->type = COMEDI_SUBD_DIO;
4498         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4499         s->maxdata = 1;
4500         s->io_bits = 0;         /* all bits input */
4501         s->range_table = &range_digital;
4502         s->n_chan = boardtype.num_p0_dio_channels;
4503         if (boardtype.reg_type & ni_reg_m_series_mask) {
4504                 s->subdev_flags |=
4505                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4506                 s->insn_bits = &ni_m_series_dio_insn_bits;
4507                 s->insn_config = &ni_m_series_dio_insn_config;
4508                 s->do_cmd = &ni_cdio_cmd;
4509                 s->do_cmdtest = &ni_cdio_cmdtest;
4510                 s->cancel = &ni_cdio_cancel;
4511                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4512                 s->len_chanlist = s->n_chan;
4513
4514                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4515                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4516         } else {
4517                 s->insn_bits = &ni_dio_insn_bits;
4518                 s->insn_config = &ni_dio_insn_config;
4519                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4520                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4521         }
4522
4523         /* 8255 device */
4524         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4525         if (boardtype.has_8255) {
4526                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4527         } else {
4528                 s->type = COMEDI_SUBD_UNUSED;
4529         }
4530
4531         /* formerly general purpose counter/timer device, but no longer used */
4532         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4533         s->type = COMEDI_SUBD_UNUSED;
4534
4535         /* calibration subdevice -- ai and ao */
4536         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4537         s->type = COMEDI_SUBD_CALIB;
4538         if (boardtype.reg_type & ni_reg_m_series_mask) {
4539                 /*  internal PWM analog output used for AI nonlinearity calibration */
4540                 s->subdev_flags = SDF_INTERNAL;
4541                 s->insn_config = &ni_m_series_pwm_config;
4542                 s->n_chan = 1;
4543                 s->maxdata = 0;
4544                 ni_writel(0x0, M_Offset_Cal_PWM);
4545         } else if (boardtype.reg_type == ni_reg_6143) {
4546                 /*  internal PWM analog output used for AI nonlinearity calibration */
4547                 s->subdev_flags = SDF_INTERNAL;
4548                 s->insn_config = &ni_6143_pwm_config;
4549                 s->n_chan = 1;
4550                 s->maxdata = 0;
4551         } else {
4552                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4553                 s->insn_read = &ni_calib_insn_read;
4554                 s->insn_write = &ni_calib_insn_write;
4555                 caldac_setup(dev, s);
4556         }
4557
4558         /* EEPROM */
4559         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4560         s->type = COMEDI_SUBD_MEMORY;
4561         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4562         s->maxdata = 0xff;
4563         if (boardtype.reg_type & ni_reg_m_series_mask) {
4564                 s->n_chan = M_SERIES_EEPROM_SIZE;
4565                 s->insn_read = &ni_m_series_eeprom_insn_read;
4566         } else {
4567                 s->n_chan = 512;
4568                 s->insn_read = &ni_eeprom_insn_read;
4569         }
4570
4571         /* PFI */
4572         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4573         s->type = COMEDI_SUBD_DIO;
4574         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4575         if (boardtype.reg_type & ni_reg_m_series_mask) {
4576                 unsigned i;
4577                 s->n_chan = 16;
4578                 ni_writew(s->state, M_Offset_PFI_DO);
4579                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4580                         ni_writew(devpriv->pfi_output_select_reg[i],
4581                                   M_Offset_PFI_Output_Select(i + 1));
4582                 }
4583         } else {
4584                 s->n_chan = 10;
4585         }
4586         s->maxdata = 1;
4587         if (boardtype.reg_type & ni_reg_m_series_mask) {
4588                 s->insn_bits = &ni_pfi_insn_bits;
4589         }
4590         s->insn_config = &ni_pfi_insn_config;
4591         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4592
4593         /* cs5529 calibration adc */
4594         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4595         if (boardtype.reg_type & ni_reg_67xx_mask) {
4596                 s->type = COMEDI_SUBD_AI;
4597                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4598                 /*  one channel for each analog output channel */
4599                 s->n_chan = boardtype.n_aochan;
4600                 s->maxdata = (1 << 16) - 1;
4601                 s->range_table = &range_unknown;        /* XXX */
4602                 s->insn_read = cs5529_ai_insn_read;
4603                 s->insn_config = NULL;
4604                 init_cs5529(dev);
4605         } else {
4606                 s->type = COMEDI_SUBD_UNUSED;
4607         }
4608
4609         /* Serial */
4610         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4611         s->type = COMEDI_SUBD_SERIAL;
4612         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4613         s->n_chan = 1;
4614         s->maxdata = 0xff;
4615         s->insn_config = ni_serial_insn_config;
4616         devpriv->serial_interval_ns = 0;
4617         devpriv->serial_hw_mode = 0;
4618
4619         /* RTSI */
4620         s = &dev->subdevices[NI_RTSI_SUBDEV];
4621         s->type = COMEDI_SUBD_DIO;
4622         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4623         s->n_chan = 8;
4624         s->maxdata = 1;
4625         s->insn_bits = ni_rtsi_insn_bits;
4626         s->insn_config = ni_rtsi_insn_config;
4627         ni_rtsi_init(dev);
4628
4629         if (boardtype.reg_type & ni_reg_m_series_mask) {
4630                 counter_variant = ni_gpct_variant_m_series;
4631         } else {
4632                 counter_variant = ni_gpct_variant_e_series;
4633         }
4634         devpriv->counter_dev = ni_gpct_device_construct(dev,
4635                                                         &ni_gpct_write_register,
4636                                                         &ni_gpct_read_register,
4637                                                         counter_variant,
4638                                                         NUM_GPCT);
4639         /* General purpose counters */
4640         for (j = 0; j < NUM_GPCT; ++j) {
4641                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4642                 s->type = COMEDI_SUBD_COUNTER;
4643                 s->subdev_flags =
4644                     SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4645                     /* | SDF_CMD_WRITE */ ;
4646                 s->n_chan = 3;
4647                 if (boardtype.reg_type & ni_reg_m_series_mask)
4648                         s->maxdata = 0xffffffff;
4649                 else
4650                         s->maxdata = 0xffffff;
4651                 s->insn_read = &ni_gpct_insn_read;
4652                 s->insn_write = &ni_gpct_insn_write;
4653                 s->insn_config = &ni_gpct_insn_config;
4654                 s->do_cmd = &ni_gpct_cmd;
4655                 s->len_chanlist = 1;
4656                 s->do_cmdtest = &ni_gpct_cmdtest;
4657                 s->cancel = &ni_gpct_cancel;
4658                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4659                 s->private = &devpriv->counter_dev->counters[j];
4660
4661                 devpriv->counter_dev->counters[j].chip_index = 0;
4662                 devpriv->counter_dev->counters[j].counter_index = j;
4663                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4664         }
4665
4666         /* Frequency output */
4667         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4668         s->type = COMEDI_SUBD_COUNTER;
4669         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4670         s->n_chan = 1;
4671         s->maxdata = 0xf;
4672         s->insn_read = &ni_freq_out_insn_read;
4673         s->insn_write = &ni_freq_out_insn_write;
4674         s->insn_config = &ni_freq_out_insn_config;
4675
4676         /* ai configuration */
4677         s = &dev->subdevices[NI_AI_SUBDEV];
4678         ni_ai_reset(dev, s);
4679         if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4680                 /*  BEAM is this needed for PCI-6143 ?? */
4681                 devpriv->clock_and_fout =
4682                     Slow_Internal_Time_Divide_By_2 |
4683                     Slow_Internal_Timebase |
4684                     Clock_To_Board_Divide_By_2 |
4685                     Clock_To_Board |
4686                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4687         } else {
4688                 devpriv->clock_and_fout =
4689                     Slow_Internal_Time_Divide_By_2 |
4690                     Slow_Internal_Timebase |
4691                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4692         }
4693         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4694                             Clock_and_FOUT_Register);
4695
4696         /* analog output configuration */
4697         s = &dev->subdevices[NI_AO_SUBDEV];
4698         ni_ao_reset(dev, s);
4699
4700         if (dev->irq) {
4701                 devpriv->stc_writew(dev,
4702                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4703                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4704                                     Interrupt_A_Enable | Interrupt_B_Enable |
4705                                     Interrupt_A_Output_Select(interrupt_pin
4706                                                               (dev->irq)) |
4707                                     Interrupt_B_Output_Select(interrupt_pin
4708                                                               (dev->irq)),
4709                                     Interrupt_Control_Register);
4710         }
4711
4712         /* DMA setup */
4713         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4714         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4715
4716         if (boardtype.reg_type & ni_reg_6xxx_mask) {
4717                 ni_writeb(0, Magic_611x);
4718         } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4719                 int channel;
4720                 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4721                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4722                         ni_writeb(0x0,
4723                                   M_Offset_AO_Reference_Attenuation(channel));
4724                 }
4725                 ni_writeb(0x0, M_Offset_AO_Calibration);
4726         }
4727
4728         printk("\n");
4729         return 0;
4730 }
4731
4732 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4733 {
4734         struct comedi_device *dev = (struct comedi_device *)arg;
4735
4736         if (dir) {
4737                 ni_writeb(data, Port_A + 2 * port);
4738                 return 0;
4739         } else {
4740                 return ni_readb(Port_A + 2 * port);
4741         }
4742 }
4743
4744 /*
4745         presents the EEPROM as a subdevice
4746 */
4747
4748 static int ni_eeprom_insn_read(struct comedi_device *dev,
4749                                struct comedi_subdevice *s,
4750                                struct comedi_insn *insn, unsigned int *data)
4751 {
4752         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4753
4754         return 1;
4755 }
4756
4757 /*
4758         reads bytes out of eeprom
4759 */
4760
4761 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4762 {
4763         int bit;
4764         int bitstring;
4765
4766         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4767         ni_writeb(0x04, Serial_Command);
4768         for (bit = 0x8000; bit; bit >>= 1) {
4769                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4770                           Serial_Command);
4771                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4772                           Serial_Command);
4773         }
4774         bitstring = 0;
4775         for (bit = 0x80; bit; bit >>= 1) {
4776                 ni_writeb(0x04, Serial_Command);
4777                 ni_writeb(0x05, Serial_Command);
4778                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4779         }
4780         ni_writeb(0x00, Serial_Command);
4781
4782         return bitstring;
4783 }
4784
4785 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4786                                         struct comedi_subdevice *s,
4787                                         struct comedi_insn *insn,
4788                                         unsigned int *data)
4789 {
4790         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4791
4792         return 1;
4793 }
4794
4795 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4796 {
4797         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4798         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4799         return 3;
4800 }
4801
4802 static int ni_m_series_pwm_config(struct comedi_device *dev,
4803                                   struct comedi_subdevice *s,
4804                                   struct comedi_insn *insn, unsigned int *data)
4805 {
4806         unsigned up_count, down_count;
4807         switch (data[0]) {
4808         case INSN_CONFIG_PWM_OUTPUT:
4809                 switch (data[1]) {
4810                 case TRIG_ROUND_NEAREST:
4811                         up_count =
4812                             (data[2] +
4813                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4814                         break;
4815                 case TRIG_ROUND_DOWN:
4816                         up_count = data[2] / devpriv->clock_ns;
4817                         break;
4818                 case TRIG_ROUND_UP:
4819                         up_count =
4820                             (data[2] + devpriv->clock_ns -
4821                              1) / devpriv->clock_ns;
4822                         break;
4823                 default:
4824                         return -EINVAL;
4825                         break;
4826                 }
4827                 switch (data[3]) {
4828                 case TRIG_ROUND_NEAREST:
4829                         down_count =
4830                             (data[4] +
4831                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4832                         break;
4833                 case TRIG_ROUND_DOWN:
4834                         down_count = data[4] / devpriv->clock_ns;
4835                         break;
4836                 case TRIG_ROUND_UP:
4837                         down_count =
4838                             (data[4] + devpriv->clock_ns -
4839                              1) / devpriv->clock_ns;
4840                         break;
4841                 default:
4842                         return -EINVAL;
4843                         break;
4844                 }
4845                 if (up_count * devpriv->clock_ns != data[2] ||
4846                     down_count * devpriv->clock_ns != data[4]) {
4847                         data[2] = up_count * devpriv->clock_ns;
4848                         data[4] = down_count * devpriv->clock_ns;
4849                         return -EAGAIN;
4850                 }
4851                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4852                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4853                           M_Offset_Cal_PWM);
4854                 devpriv->pwm_up_count = up_count;
4855                 devpriv->pwm_down_count = down_count;
4856                 return 5;
4857                 break;
4858         case INSN_CONFIG_GET_PWM_OUTPUT:
4859                 return ni_get_pwm_config(dev, data);
4860                 break;
4861         default:
4862                 return -EINVAL;
4863                 break;
4864         }
4865         return 0;
4866 }
4867
4868 static int ni_6143_pwm_config(struct comedi_device *dev,
4869                               struct comedi_subdevice *s,
4870                               struct comedi_insn *insn, unsigned int *data)
4871 {
4872         unsigned up_count, down_count;
4873         switch (data[0]) {
4874         case INSN_CONFIG_PWM_OUTPUT:
4875                 switch (data[1]) {
4876                 case TRIG_ROUND_NEAREST:
4877                         up_count =
4878                             (data[2] +
4879                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4880                         break;
4881                 case TRIG_ROUND_DOWN:
4882                         up_count = data[2] / devpriv->clock_ns;
4883                         break;
4884                 case TRIG_ROUND_UP:
4885                         up_count =
4886                             (data[2] + devpriv->clock_ns -
4887                              1) / devpriv->clock_ns;
4888                         break;
4889                 default:
4890                         return -EINVAL;
4891                         break;
4892                 }
4893                 switch (data[3]) {
4894                 case TRIG_ROUND_NEAREST:
4895                         down_count =
4896                             (data[4] +
4897                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4898                         break;
4899                 case TRIG_ROUND_DOWN:
4900                         down_count = data[4] / devpriv->clock_ns;
4901                         break;
4902                 case TRIG_ROUND_UP:
4903                         down_count =
4904                             (data[4] + devpriv->clock_ns -
4905                              1) / devpriv->clock_ns;
4906                         break;
4907                 default:
4908                         return -EINVAL;
4909                         break;
4910                 }
4911                 if (up_count * devpriv->clock_ns != data[2] ||
4912                     down_count * devpriv->clock_ns != data[4]) {
4913                         data[2] = up_count * devpriv->clock_ns;
4914                         data[4] = down_count * devpriv->clock_ns;
4915                         return -EAGAIN;
4916                 }
4917                 ni_writel(up_count, Calibration_HighTime_6143);
4918                 devpriv->pwm_up_count = up_count;
4919                 ni_writel(down_count, Calibration_LowTime_6143);
4920                 devpriv->pwm_down_count = down_count;
4921                 return 5;
4922                 break;
4923         case INSN_CONFIG_GET_PWM_OUTPUT:
4924                 return ni_get_pwm_config(dev, data);
4925         default:
4926                 return -EINVAL;
4927                 break;
4928         }
4929         return 0;
4930 }
4931
4932 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4933 /*
4934         calibration subdevice
4935 */
4936 static int ni_calib_insn_write(struct comedi_device *dev,
4937                                struct comedi_subdevice *s,
4938                                struct comedi_insn *insn, unsigned int *data)
4939 {
4940         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4941
4942         return 1;
4943 }
4944
4945 static int ni_calib_insn_read(struct comedi_device *dev,
4946                               struct comedi_subdevice *s,
4947                               struct comedi_insn *insn, unsigned int *data)
4948 {
4949         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4950
4951         return 1;
4952 }
4953
4954 static int pack_mb88341(int addr, int val, int *bitstring);
4955 static int pack_dac8800(int addr, int val, int *bitstring);
4956 static int pack_dac8043(int addr, int val, int *bitstring);
4957 static int pack_ad8522(int addr, int val, int *bitstring);
4958 static int pack_ad8804(int addr, int val, int *bitstring);
4959 static int pack_ad8842(int addr, int val, int *bitstring);
4960
4961 struct caldac_struct {
4962         int n_chans;
4963         int n_bits;
4964         int (*packbits) (int, int, int *);
4965 };
4966
4967 static struct caldac_struct caldacs[] = {
4968         [mb88341] = {12, 8, pack_mb88341},
4969         [dac8800] = {8, 8, pack_dac8800},
4970         [dac8043] = {1, 12, pack_dac8043},
4971         [ad8522] = {2, 12, pack_ad8522},
4972         [ad8804] = {12, 8, pack_ad8804},
4973         [ad8842] = {8, 8, pack_ad8842},
4974         [ad8804_debug] = {16, 8, pack_ad8804},
4975 };
4976
4977 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4978 {
4979         int i, j;
4980         int n_dacs;
4981         int n_chans = 0;
4982         int n_bits;
4983         int diffbits = 0;
4984         int type;
4985         int chan;
4986
4987         type = boardtype.caldac[0];
4988         if (type == caldac_none)
4989                 return;
4990         n_bits = caldacs[type].n_bits;
4991         for (i = 0; i < 3; i++) {
4992                 type = boardtype.caldac[i];
4993                 if (type == caldac_none)
4994                         break;
4995                 if (caldacs[type].n_bits != n_bits)
4996                         diffbits = 1;
4997                 n_chans += caldacs[type].n_chans;
4998         }
4999         n_dacs = i;
5000         s->n_chan = n_chans;
5001
5002         if (diffbits) {
5003                 unsigned int *maxdata_list;
5004
5005                 if (n_chans > MAX_N_CALDACS) {
5006                         printk("BUG! MAX_N_CALDACS too small\n");
5007                 }
5008                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5009                 chan = 0;
5010                 for (i = 0; i < n_dacs; i++) {
5011                         type = boardtype.caldac[i];
5012                         for (j = 0; j < caldacs[type].n_chans; j++) {
5013                                 maxdata_list[chan] =
5014                                     (1 << caldacs[type].n_bits) - 1;
5015                                 chan++;
5016                         }
5017                 }
5018
5019                 for (chan = 0; chan < s->n_chan; chan++)
5020                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5021         } else {
5022                 type = boardtype.caldac[0];
5023                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5024
5025                 for (chan = 0; chan < s->n_chan; chan++)
5026                         ni_write_caldac(dev, i, s->maxdata / 2);
5027         }
5028 }
5029
5030 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5031 {
5032         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5033         int i;
5034         int type;
5035
5036         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5037         if (devpriv->caldacs[addr] == val)
5038                 return;
5039         devpriv->caldacs[addr] = val;
5040
5041         for (i = 0; i < 3; i++) {
5042                 type = boardtype.caldac[i];
5043                 if (type == caldac_none)
5044                         break;
5045                 if (addr < caldacs[type].n_chans) {
5046                         bits = caldacs[type].packbits(addr, val, &bitstring);
5047                         loadbit = SerDacLd(i);
5048                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5049                         break;
5050                 }
5051                 addr -= caldacs[type].n_chans;
5052         }
5053
5054         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5055                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5056                 udelay(1);
5057                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5058                 udelay(1);
5059         }
5060         ni_writeb(loadbit, Serial_Command);
5061         udelay(1);
5062         ni_writeb(0, Serial_Command);
5063 }
5064
5065 static int pack_mb88341(int addr, int val, int *bitstring)
5066 {
5067         /*
5068            Fujitsu MB 88341
5069            Note that address bits are reversed.  Thanks to
5070            Ingo Keen for noticing this.
5071
5072            Note also that the 88341 expects address values from
5073            1-12, whereas we use channel numbers 0-11.  The NI
5074            docs use 1-12, also, so be careful here.
5075          */
5076         addr++;
5077         *bitstring = ((addr & 0x1) << 11) |
5078             ((addr & 0x2) << 9) |
5079             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5080         return 12;
5081 }
5082
5083 static int pack_dac8800(int addr, int val, int *bitstring)
5084 {
5085         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5086         return 11;
5087 }
5088
5089 static int pack_dac8043(int addr, int val, int *bitstring)
5090 {
5091         *bitstring = val & 0xfff;
5092         return 12;
5093 }
5094
5095 static int pack_ad8522(int addr, int val, int *bitstring)
5096 {
5097         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5098         return 16;
5099 }
5100
5101 static int pack_ad8804(int addr, int val, int *bitstring)
5102 {
5103         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5104         return 12;
5105 }
5106
5107 static int pack_ad8842(int addr, int val, int *bitstring)
5108 {
5109         *bitstring = ((addr + 1) << 8) | (val & 0xff);
5110         return 12;
5111 }
5112
5113 #if 0
5114 /*
5115  *      Read the GPCTs current value.
5116  */
5117 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5118 {
5119         unsigned int hi1, hi2, lo;
5120
5121         devpriv->gpct_command[chan] &= ~G_Save_Trace;
5122         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5123                             G_Command_Register(chan));
5124
5125         devpriv->gpct_command[chan] |= G_Save_Trace;
5126         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5127                             G_Command_Register(chan));
5128
5129         /* This procedure is used because the two registers cannot
5130          * be read atomically. */
5131         do {
5132                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5133                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5134                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5135         } while (hi1 != hi2);
5136
5137         return (hi1 << 16) | lo;
5138 }
5139
5140 static void GPCT_Reset(struct comedi_device *dev, int chan)
5141 {
5142         int temp_ack_reg = 0;
5143
5144         /* printk("GPCT_Reset..."); */
5145         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5146
5147         switch (chan) {
5148         case 0:
5149                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5150                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5151                             G0_TC_Interrupt_Enable, 0);
5152                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5153                             G0_Gate_Interrupt_Enable, 0);
5154                 temp_ack_reg |= G0_Gate_Error_Confirm;
5155                 temp_ack_reg |= G0_TC_Error_Confirm;
5156                 temp_ack_reg |= G0_TC_Interrupt_Ack;
5157                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5158                 devpriv->stc_writew(dev, temp_ack_reg,
5159                                     Interrupt_A_Ack_Register);
5160
5161                 /* problem...this interferes with the other ctr... */
5162                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5163                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5164                                     Analog_Trigger_Etc_Register);
5165                 break;
5166         case 1:
5167                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5168                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5169                             G1_TC_Interrupt_Enable, 0);
5170                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5171                             G0_Gate_Interrupt_Enable, 0);
5172                 temp_ack_reg |= G1_Gate_Error_Confirm;
5173                 temp_ack_reg |= G1_TC_Error_Confirm;
5174                 temp_ack_reg |= G1_TC_Interrupt_Ack;
5175                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5176                 devpriv->stc_writew(dev, temp_ack_reg,
5177                                     Interrupt_B_Ack_Register);
5178
5179                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5180                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5181                                     Analog_Trigger_Etc_Register);
5182                 break;
5183         }
5184
5185         devpriv->gpct_mode[chan] = 0;
5186         devpriv->gpct_input_select[chan] = 0;
5187         devpriv->gpct_command[chan] = 0;
5188
5189         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5190
5191         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5192                             G_Mode_Register(chan));
5193         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5194                             G_Input_Select_Register(chan));
5195         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5196
5197         /* printk("exit GPCT_Reset\n"); */
5198 }
5199
5200 #endif
5201
5202 static int ni_gpct_insn_config(struct comedi_device *dev,
5203                                struct comedi_subdevice *s,
5204                                struct comedi_insn *insn, unsigned int *data)
5205 {
5206         struct ni_gpct *counter = s->private;
5207         return ni_tio_insn_config(counter, insn, data);
5208 }
5209
5210 static int ni_gpct_insn_read(struct comedi_device *dev,
5211                              struct comedi_subdevice *s,
5212                              struct comedi_insn *insn, unsigned int *data)
5213 {
5214         struct ni_gpct *counter = s->private;
5215         return ni_tio_rinsn(counter, insn, data);
5216 }
5217
5218 static int ni_gpct_insn_write(struct comedi_device *dev,
5219                               struct comedi_subdevice *s,
5220                               struct comedi_insn *insn, unsigned int *data)
5221 {
5222         struct ni_gpct *counter = s->private;
5223         return ni_tio_winsn(counter, insn, data);
5224 }
5225
5226 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5227 {
5228         int retval;
5229 #ifdef PCIDMA
5230         struct ni_gpct *counter = s->private;
5231 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5232
5233         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5234                                               COMEDI_INPUT);
5235         if (retval) {
5236                 comedi_error(dev,
5237                              "no dma channel available for use by counter");
5238                 return retval;
5239         }
5240         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5241         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5242         retval = ni_tio_cmd(counter, s->async);
5243 #else
5244         retval = -ENOTSUPP;
5245 #endif
5246         return retval;
5247 }
5248
5249 static int ni_gpct_cmdtest(struct comedi_device *dev,
5250                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
5251 {
5252 #ifdef PCIDMA
5253         struct ni_gpct *counter = s->private;
5254
5255         return ni_tio_cmdtest(counter, cmd);
5256 #else
5257         return -ENOTSUPP;
5258 #endif
5259 }
5260
5261 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5262 {
5263 #ifdef PCIDMA
5264         struct ni_gpct *counter = s->private;
5265         int retval;
5266
5267         retval = ni_tio_cancel(counter);
5268         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5269         ni_release_gpct_mite_channel(dev, counter->counter_index);
5270         return retval;
5271 #else
5272         return 0;
5273 #endif
5274 }
5275
5276 /*
5277  *
5278  *  Programmable Function Inputs
5279  *
5280  */
5281
5282 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5283                                        unsigned source)
5284 {
5285         unsigned pfi_reg_index;
5286         unsigned array_offset;
5287         if ((source & 0x1f) != source)
5288                 return -EINVAL;
5289         pfi_reg_index = 1 + chan / 3;
5290         array_offset = pfi_reg_index - 1;
5291         devpriv->pfi_output_select_reg[array_offset] &=
5292             ~MSeries_PFI_Output_Select_Mask(chan);
5293         devpriv->pfi_output_select_reg[array_offset] |=
5294             MSeries_PFI_Output_Select_Bits(chan, source);
5295         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5296                   M_Offset_PFI_Output_Select(pfi_reg_index));
5297         return 2;
5298 }
5299
5300 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5301                                   unsigned source)
5302 {
5303         /*  pre-m-series boards have fixed signals on pfi pins */
5304         if (source != ni_old_get_pfi_routing(dev, chan))
5305                 return -EINVAL;
5306         return 2;
5307 }
5308
5309 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5310                               unsigned source)
5311 {
5312         if (boardtype.reg_type & ni_reg_m_series_mask)
5313                 return ni_m_series_set_pfi_routing(dev, chan, source);
5314         else
5315                 return ni_old_set_pfi_routing(dev, chan, source);
5316 }
5317
5318 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5319                                             unsigned chan)
5320 {
5321         const unsigned array_offset = chan / 3;
5322         return MSeries_PFI_Output_Select_Source(chan,
5323                                                 devpriv->
5324                                                 pfi_output_select_reg
5325                                                 [array_offset]);
5326 }
5327
5328 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5329 {
5330         /*  pre-m-series boards have fixed signals on pfi pins */
5331         switch (chan) {
5332         case 0:
5333                 return NI_PFI_OUTPUT_AI_START1;
5334                 break;
5335         case 1:
5336                 return NI_PFI_OUTPUT_AI_START2;
5337                 break;
5338         case 2:
5339                 return NI_PFI_OUTPUT_AI_CONVERT;
5340                 break;
5341         case 3:
5342                 return NI_PFI_OUTPUT_G_SRC1;
5343                 break;
5344         case 4:
5345                 return NI_PFI_OUTPUT_G_GATE1;
5346                 break;
5347         case 5:
5348                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5349                 break;
5350         case 6:
5351                 return NI_PFI_OUTPUT_AO_START1;
5352                 break;
5353         case 7:
5354                 return NI_PFI_OUTPUT_AI_START_PULSE;
5355                 break;
5356         case 8:
5357                 return NI_PFI_OUTPUT_G_SRC0;
5358                 break;
5359         case 9:
5360                 return NI_PFI_OUTPUT_G_GATE0;
5361                 break;
5362         default:
5363                 printk("%s: bug, unhandled case in switch.\n", __func__);
5364                 break;
5365         }
5366         return 0;
5367 }
5368
5369 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5370 {
5371         if (boardtype.reg_type & ni_reg_m_series_mask)
5372                 return ni_m_series_get_pfi_routing(dev, chan);
5373         else
5374                 return ni_old_get_pfi_routing(dev, chan);
5375 }
5376
5377 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5378                             enum ni_pfi_filter_select filter)
5379 {
5380         unsigned bits;
5381         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5382                 return -ENOTSUPP;
5383         }
5384         bits = ni_readl(M_Offset_PFI_Filter);
5385         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5386         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5387         ni_writel(bits, M_Offset_PFI_Filter);
5388         return 0;
5389 }
5390
5391 static int ni_pfi_insn_bits(struct comedi_device *dev,
5392                             struct comedi_subdevice *s,
5393                             struct comedi_insn *insn, unsigned int *data)
5394 {
5395         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5396                 return -ENOTSUPP;
5397         }
5398         if (data[0]) {
5399                 s->state &= ~data[0];
5400                 s->state |= (data[0] & data[1]);
5401                 ni_writew(s->state, M_Offset_PFI_DO);
5402         }
5403         data[1] = ni_readw(M_Offset_PFI_DI);
5404         return insn->n;
5405 }
5406
5407 static int ni_pfi_insn_config(struct comedi_device *dev,
5408                               struct comedi_subdevice *s,
5409                               struct comedi_insn *insn, unsigned int *data)
5410 {
5411         unsigned int chan;
5412
5413         if (insn->n < 1)
5414                 return -EINVAL;
5415
5416         chan = CR_CHAN(insn->chanspec);
5417
5418         switch (data[0]) {
5419         case COMEDI_OUTPUT:
5420                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5421                 break;
5422         case COMEDI_INPUT:
5423                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5424                 break;
5425         case INSN_CONFIG_DIO_QUERY:
5426                 data[1] =
5427                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5428                     COMEDI_OUTPUT : COMEDI_INPUT;
5429                 return 0;
5430                 break;
5431         case INSN_CONFIG_SET_ROUTING:
5432                 return ni_set_pfi_routing(dev, chan, data[1]);
5433                 break;
5434         case INSN_CONFIG_GET_ROUTING:
5435                 data[1] = ni_get_pfi_routing(dev, chan);
5436                 break;
5437         case INSN_CONFIG_FILTER:
5438                 return ni_config_filter(dev, chan, data[1]);
5439                 break;
5440         default:
5441                 return -EINVAL;
5442         }
5443         return 0;
5444 }
5445
5446 /*
5447  *
5448  *  NI RTSI Bus Functions
5449  *
5450  */
5451 static void ni_rtsi_init(struct comedi_device *dev)
5452 {
5453         /*  Initialises the RTSI bus signal switch to a default state */
5454
5455         /*  Set clock mode to internal */
5456         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5457         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5458                 printk("ni_set_master_clock failed, bug?");
5459         }
5460         /*  default internal lines routing to RTSI bus lines */
5461         devpriv->rtsi_trig_a_output_reg =
5462             RTSI_Trig_Output_Bits(0,
5463                                   NI_RTSI_OUTPUT_ADR_START1) |
5464             RTSI_Trig_Output_Bits(1,
5465                                   NI_RTSI_OUTPUT_ADR_START2) |
5466             RTSI_Trig_Output_Bits(2,
5467                                   NI_RTSI_OUTPUT_SCLKG) |
5468             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5469         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5470                             RTSI_Trig_A_Output_Register);
5471         devpriv->rtsi_trig_b_output_reg =
5472             RTSI_Trig_Output_Bits(4,
5473                                   NI_RTSI_OUTPUT_DA_START1) |
5474             RTSI_Trig_Output_Bits(5,
5475                                   NI_RTSI_OUTPUT_G_SRC0) |
5476             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5477         if (boardtype.reg_type & ni_reg_m_series_mask)
5478                 devpriv->rtsi_trig_b_output_reg |=
5479                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5480         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5481                             RTSI_Trig_B_Output_Register);
5482
5483 /*
5484 * Sets the source and direction of the 4 on board lines
5485 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5486 */
5487 }
5488
5489 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5490                              struct comedi_subdevice *s,
5491                              struct comedi_insn *insn, unsigned int *data)
5492 {
5493         data[1] = 0;
5494
5495         return insn->n;
5496 }
5497
5498 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5499  * given an arbitrary frequency input clock */
5500 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5501                                          unsigned *freq_divider,
5502                                          unsigned *freq_multiplier,
5503                                          unsigned *actual_period_ns)
5504 {
5505         unsigned div;
5506         unsigned best_div = 1;
5507         static const unsigned max_div = 0x10;
5508         unsigned mult;
5509         unsigned best_mult = 1;
5510         static const unsigned max_mult = 0x100;
5511         static const unsigned pico_per_nano = 1000;
5512
5513         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5514         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5515          * 20 MHz for most timing clocks */
5516         static const unsigned target_picosec = 12500;
5517         static const unsigned fudge_factor_80_to_20Mhz = 4;
5518         int best_period_picosec = 0;
5519         for (div = 1; div <= max_div; ++div) {
5520                 for (mult = 1; mult <= max_mult; ++mult) {
5521                         unsigned new_period_ps =
5522                             (reference_picosec * div) / mult;
5523                         if (abs(new_period_ps - target_picosec) <
5524                             abs(best_period_picosec - target_picosec)) {
5525                                 best_period_picosec = new_period_ps;
5526                                 best_div = div;
5527                                 best_mult = mult;
5528                         }
5529                 }
5530         }
5531         if (best_period_picosec == 0) {
5532                 printk("%s: bug, failed to find pll parameters\n", __func__);
5533                 return -EIO;
5534         }
5535         *freq_divider = best_div;
5536         *freq_multiplier = best_mult;
5537         *actual_period_ns =
5538             (best_period_picosec * fudge_factor_80_to_20Mhz +
5539              (pico_per_nano / 2)) / pico_per_nano;
5540         return 0;
5541 }
5542
5543 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5544 {
5545         if (boardtype.reg_type & ni_reg_m_series_mask)
5546                 return 8;
5547         else
5548                 return 7;
5549 }
5550
5551 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5552                                            unsigned source, unsigned period_ns)
5553 {
5554         static const unsigned min_period_ns = 50;
5555         static const unsigned max_period_ns = 1000;
5556         static const unsigned timeout = 1000;
5557         unsigned pll_control_bits;
5558         unsigned freq_divider;
5559         unsigned freq_multiplier;
5560         unsigned i;
5561         int retval;
5562         if (source == NI_MIO_PLL_PXI10_CLOCK)
5563                 period_ns = 100;
5564         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5565         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5566                 printk
5567                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5568                      "for the phased-lock loop.\n", __func__,
5569                      min_period_ns, max_period_ns);
5570                 return -EINVAL;
5571         }
5572         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5573         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5574                             RTSI_Trig_Direction_Register);
5575         pll_control_bits =
5576             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5577         devpriv->clock_and_fout2 |=
5578             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5579         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5580         switch (source) {
5581         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5582                 devpriv->clock_and_fout2 |=
5583                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5584                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5585                                                        &freq_multiplier,
5586                                                        &devpriv->clock_ns);
5587                 if (retval < 0)
5588                         return retval;
5589                 break;
5590         case NI_MIO_PLL_PXI10_CLOCK:
5591                 /* pxi clock is 10MHz */
5592                 devpriv->clock_and_fout2 |=
5593                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5594                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5595                                                        &freq_multiplier,
5596                                                        &devpriv->clock_ns);
5597                 if (retval < 0)
5598                         return retval;
5599                 break;
5600         default:
5601                 {
5602                         unsigned rtsi_channel;
5603                         static const unsigned max_rtsi_channel = 7;
5604                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5605                              ++rtsi_channel) {
5606                                 if (source ==
5607                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5608                                         devpriv->clock_and_fout2 |=
5609                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5610                                             (rtsi_channel);
5611                                         break;
5612                                 }
5613                         }
5614                         if (rtsi_channel > max_rtsi_channel)
5615                                 return -EINVAL;
5616                         retval = ni_mseries_get_pll_parameters(period_ns,
5617                                                                &freq_divider,
5618                                                                &freq_multiplier,
5619                                                                &devpriv->
5620                                                                clock_ns);
5621                         if (retval < 0)
5622                                 return retval;
5623                 }
5624                 break;
5625         }
5626         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5627         pll_control_bits |=
5628             MSeries_PLL_Divisor_Bits(freq_divider) |
5629             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5630
5631         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5632          * freq_divider, freq_multiplier, pll_control_bits); */
5633         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5634         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5635         devpriv->clock_source = source;
5636         /* it seems to typically take a few hundred microseconds for PLL to lock */
5637         for (i = 0; i < timeout; ++i) {
5638                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5639                         break;
5640                 }
5641                 udelay(1);
5642         }
5643         if (i == timeout) {
5644                 printk
5645                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5646                      __func__, source, period_ns);
5647                 return -ETIMEDOUT;
5648         }
5649         return 3;
5650 }
5651
5652 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5653                                unsigned period_ns)
5654 {
5655         if (source == NI_MIO_INTERNAL_CLOCK) {
5656                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5657                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5658                                     RTSI_Trig_Direction_Register);
5659                 devpriv->clock_ns = TIMEBASE_1_NS;
5660                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5661                         devpriv->clock_and_fout2 &=
5662                             ~(MSeries_Timebase1_Select_Bit |
5663                               MSeries_Timebase3_Select_Bit);
5664                         ni_writew(devpriv->clock_and_fout2,
5665                                   M_Offset_Clock_and_Fout2);
5666                         ni_writew(0, M_Offset_PLL_Control);
5667                 }
5668                 devpriv->clock_source = source;
5669         } else {
5670                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5671                         return ni_mseries_set_pll_master_clock(dev, source,
5672                                                                period_ns);
5673                 } else {
5674                         if (source == NI_MIO_RTSI_CLOCK) {
5675                                 devpriv->rtsi_trig_direction_reg |=
5676                                     Use_RTSI_Clock_Bit;
5677                                 devpriv->stc_writew(dev,
5678                                                     devpriv->
5679                                                     rtsi_trig_direction_reg,
5680                                                     RTSI_Trig_Direction_Register);
5681                                 if (period_ns == 0) {
5682                                         printk
5683                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5684                                              __func__);
5685                                         return -EINVAL;
5686                                 } else {
5687                                         devpriv->clock_ns = period_ns;
5688                                 }
5689                                 devpriv->clock_source = source;
5690                         } else
5691                                 return -EINVAL;
5692                 }
5693         }
5694         return 3;
5695 }
5696
5697 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5698                                        unsigned source)
5699 {
5700         if (chan >= num_configurable_rtsi_channels(dev)) {
5701                 if (chan == old_RTSI_clock_channel) {
5702                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5703                                 return 1;
5704                         else {
5705                                 printk
5706                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5707                                      __func__, chan, old_RTSI_clock_channel);
5708                                 return 0;
5709                         }
5710                 }
5711                 return 0;
5712         }
5713         switch (source) {
5714         case NI_RTSI_OUTPUT_ADR_START1:
5715         case NI_RTSI_OUTPUT_ADR_START2:
5716         case NI_RTSI_OUTPUT_SCLKG:
5717         case NI_RTSI_OUTPUT_DACUPDN:
5718         case NI_RTSI_OUTPUT_DA_START1:
5719         case NI_RTSI_OUTPUT_G_SRC0:
5720         case NI_RTSI_OUTPUT_G_GATE0:
5721         case NI_RTSI_OUTPUT_RGOUT0:
5722         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5723                 return 1;
5724                 break;
5725         case NI_RTSI_OUTPUT_RTSI_OSC:
5726                 if (boardtype.reg_type & ni_reg_m_series_mask)
5727                         return 1;
5728                 else
5729                         return 0;
5730                 break;
5731         default:
5732                 return 0;
5733                 break;
5734         }
5735 }
5736
5737 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5738                                unsigned source)
5739 {
5740         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5741                 return -EINVAL;
5742         if (chan < 4) {
5743                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5744                 devpriv->rtsi_trig_a_output_reg |=
5745                     RTSI_Trig_Output_Bits(chan, source);
5746                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5747                                     RTSI_Trig_A_Output_Register);
5748         } else if (chan < 8) {
5749                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5750                 devpriv->rtsi_trig_b_output_reg |=
5751                     RTSI_Trig_Output_Bits(chan, source);
5752                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5753                                     RTSI_Trig_B_Output_Register);
5754         }
5755         return 2;
5756 }
5757
5758 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5759 {
5760         if (chan < 4) {
5761                 return RTSI_Trig_Output_Source(chan,
5762                                                devpriv->rtsi_trig_a_output_reg);
5763         } else if (chan < num_configurable_rtsi_channels(dev)) {
5764                 return RTSI_Trig_Output_Source(chan,
5765                                                devpriv->rtsi_trig_b_output_reg);
5766         } else {
5767                 if (chan == old_RTSI_clock_channel)
5768                         return NI_RTSI_OUTPUT_RTSI_OSC;
5769                 printk("%s: bug! should never get here?\n", __func__);
5770                 return 0;
5771         }
5772 }
5773
5774 static int ni_rtsi_insn_config(struct comedi_device *dev,
5775                                struct comedi_subdevice *s,
5776                                struct comedi_insn *insn, unsigned int *data)
5777 {
5778         unsigned int chan = CR_CHAN(insn->chanspec);
5779         switch (data[0]) {
5780         case INSN_CONFIG_DIO_OUTPUT:
5781                 if (chan < num_configurable_rtsi_channels(dev)) {
5782                         devpriv->rtsi_trig_direction_reg |=
5783                             RTSI_Output_Bit(chan,
5784                                             (boardtype.
5785                                              reg_type & ni_reg_m_series_mask) !=
5786                                             0);
5787                 } else if (chan == old_RTSI_clock_channel) {
5788                         devpriv->rtsi_trig_direction_reg |=
5789                             Drive_RTSI_Clock_Bit;
5790                 }
5791                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5792                                     RTSI_Trig_Direction_Register);
5793                 break;
5794         case INSN_CONFIG_DIO_INPUT:
5795                 if (chan < num_configurable_rtsi_channels(dev)) {
5796                         devpriv->rtsi_trig_direction_reg &=
5797                             ~RTSI_Output_Bit(chan,
5798                                              (boardtype.
5799                                               reg_type & ni_reg_m_series_mask)
5800                                              != 0);
5801                 } else if (chan == old_RTSI_clock_channel) {
5802                         devpriv->rtsi_trig_direction_reg &=
5803                             ~Drive_RTSI_Clock_Bit;
5804                 }
5805                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5806                                     RTSI_Trig_Direction_Register);
5807                 break;
5808         case INSN_CONFIG_DIO_QUERY:
5809                 if (chan < num_configurable_rtsi_channels(dev)) {
5810                         data[1] =
5811                             (devpriv->rtsi_trig_direction_reg &
5812                              RTSI_Output_Bit(chan,
5813                                              (boardtype.reg_type &
5814                                               ni_reg_m_series_mask)
5815                                              != 0)) ? INSN_CONFIG_DIO_OUTPUT :
5816                             INSN_CONFIG_DIO_INPUT;
5817                 } else if (chan == old_RTSI_clock_channel) {
5818                         data[1] =
5819                             (devpriv->rtsi_trig_direction_reg &
5820                              Drive_RTSI_Clock_Bit)
5821                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5822                 }
5823                 return 2;
5824                 break;
5825         case INSN_CONFIG_SET_CLOCK_SRC:
5826                 return ni_set_master_clock(dev, data[1], data[2]);
5827                 break;
5828         case INSN_CONFIG_GET_CLOCK_SRC:
5829                 data[1] = devpriv->clock_source;
5830                 data[2] = devpriv->clock_ns;
5831                 return 3;
5832                 break;
5833         case INSN_CONFIG_SET_ROUTING:
5834                 return ni_set_rtsi_routing(dev, chan, data[1]);
5835                 break;
5836         case INSN_CONFIG_GET_ROUTING:
5837                 data[1] = ni_get_rtsi_routing(dev, chan);
5838                 return 2;
5839                 break;
5840         default:
5841                 return -EINVAL;
5842                 break;
5843         }
5844         return 1;
5845 }
5846
5847 static int cs5529_wait_for_idle(struct comedi_device *dev)
5848 {
5849         unsigned short status;
5850         const int timeout = HZ;
5851         int i;
5852
5853         for (i = 0; i < timeout; i++) {
5854                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5855                 if ((status & CSS_ADC_BUSY) == 0) {
5856                         break;
5857                 }
5858                 set_current_state(TASK_INTERRUPTIBLE);
5859                 if (schedule_timeout(1)) {
5860                         return -EIO;
5861                 }
5862         }
5863 /* printk("looped %i times waiting for idle\n", i); */
5864         if (i == timeout) {
5865                 printk("%s: %s: timeout\n", __FILE__, __func__);
5866                 return -ETIME;
5867         }
5868         return 0;
5869 }
5870
5871 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5872 {
5873         static const int timeout = 100;
5874         int i;
5875
5876         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5877         /* give time for command to start being serially clocked into cs5529.
5878          * this insures that the CSS_ADC_BUSY bit will get properly
5879          * set before we exit this function.
5880          */
5881         for (i = 0; i < timeout; i++) {
5882                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5883                         break;
5884                 udelay(1);
5885         }
5886 /* printk("looped %i times writing command to cs5529\n", i); */
5887         if (i == timeout) {
5888                 comedi_error(dev, "possible problem - never saw adc go busy?");
5889         }
5890 }
5891
5892 /* write to cs5529 register */
5893 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5894                                 unsigned int reg_select_bits)
5895 {
5896         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5897                        CAL_ADC_Config_Data_High_Word_67xx);
5898         ni_ao_win_outw(dev, (value & 0xffff),
5899                        CAL_ADC_Config_Data_Low_Word_67xx);
5900         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5901         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5902         if (cs5529_wait_for_idle(dev))
5903                 comedi_error(dev, "time or signal in cs5529_config_write()");
5904 }
5905
5906 #ifdef NI_CS5529_DEBUG
5907 /* read from cs5529 register */
5908 static unsigned int cs5529_config_read(struct comedi_device *dev,
5909                                        unsigned int reg_select_bits)
5910 {
5911         unsigned int value;
5912
5913         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5914         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5915         if (cs5529_wait_for_idle(dev))
5916                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5917         value = (ni_ao_win_inw(dev,
5918                                CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5919             0xff0000;
5920         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5921         return value;
5922 }
5923 #endif
5924
5925 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5926 {
5927         int retval;
5928         unsigned short status;
5929
5930         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5931         retval = cs5529_wait_for_idle(dev);
5932         if (retval) {
5933                 comedi_error(dev,
5934                              "timeout or signal in cs5529_do_conversion()");
5935                 return -ETIME;
5936         }
5937         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5938         if (status & CSS_OSC_DETECT) {
5939                 printk
5940                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5941                 return -EIO;
5942         }
5943         if (status & CSS_OVERRANGE) {
5944                 printk
5945                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5946         }
5947         if (data) {
5948                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5949                 /* cs5529 returns 16 bit signed data in bipolar mode */
5950                 *data ^= (1 << 15);
5951         }
5952         return 0;
5953 }
5954
5955 static int cs5529_ai_insn_read(struct comedi_device *dev,
5956                                struct comedi_subdevice *s,
5957                                struct comedi_insn *insn, unsigned int *data)
5958 {
5959         int n, retval;
5960         unsigned short sample;
5961         unsigned int channel_select;
5962         const unsigned int INTERNAL_REF = 0x1000;
5963
5964         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5965          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5966          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5967         if (insn->chanspec & CR_ALT_SOURCE)
5968                 channel_select = INTERNAL_REF;
5969         else
5970                 channel_select = CR_CHAN(insn->chanspec);
5971         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5972
5973         for (n = 0; n < insn->n; n++) {
5974                 retval = cs5529_do_conversion(dev, &sample);
5975                 if (retval < 0)
5976                         return retval;
5977                 data[n] = sample;
5978         }
5979         return insn->n;
5980 }
5981
5982 static int init_cs5529(struct comedi_device *dev)
5983 {
5984         unsigned int config_bits =
5985             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5986
5987 #if 1
5988         /* do self-calibration */
5989         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5990                             CSCMD_CONFIG_REGISTER);
5991         /* need to force a conversion for calibration to run */
5992         cs5529_do_conversion(dev, NULL);
5993 #else
5994         /* force gain calibration to 1 */
5995         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5996         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5997                             CSCMD_CONFIG_REGISTER);
5998         if (cs5529_wait_for_idle(dev))
5999                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6000 #endif
6001 #ifdef NI_CS5529_DEBUG
6002         printk("config: 0x%x\n", cs5529_config_read(dev,
6003                                                     CSCMD_CONFIG_REGISTER));
6004         printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6005         printk("offset: 0x%x\n", cs5529_config_read(dev,
6006                                                     CSCMD_OFFSET_REGISTER));
6007 #endif
6008         return 0;
6009 }