drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/mutex.h>
  20 #include <linux/device.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/slab.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/module.h>
  26
  27 #include <linux/iio/iio.h>
  28 #include <linux/iio/sysfs.h>
  29 #include <linux/iio/events.h>
  30 #include <linux/iio/buffer.h>
  31
  32 #include "lis3l02dq.h"
  33
  34 /* At the moment the spi framework doesn't allow global setting of cs_change.
  35  * It's in the likely to be added comment at the top of spi.h.
  36  * This means that use cannot be made of spi_write etc.
  37  */
  38 /* direct copy of the irq_default_primary_handler */
  39 #ifndef CONFIG_IIO_BUFFER
  40 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
  41 {
  42         return IRQ_WAKE_THREAD;
  43 }
  44 #endif
  45
  46 /**
  47  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  48  * @indio_dev: iio_dev for this actual device
  49  * @reg_address: the address of the register to be read
  50  * @val: pass back the resulting value
  51  **/
  52 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  53                              u8 reg_address, u8 *val)
  54 {
  55         struct lis3l02dq_state *st = iio_priv(indio_dev);
  56         int ret;
  57         struct spi_transfer xfer = {
  58                 .tx_buf = st->tx,
  59                 .rx_buf = st->rx,
  60                 .bits_per_word = 8,
  61                 .len = 2,
  62         };
  63
  64         mutex_lock(&st->buf_lock);
  65         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  66         st->tx[1] = 0;
  67
  68         ret = spi_sync_transfer(st->us, &xfer, 1);
  69         *val = st->rx[1];
  70         mutex_unlock(&st->buf_lock);
  71
  72         return ret;
  73 }
  74
  75 /**
  76  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  77  * @indio_dev: iio_dev for this device
  78  * @reg_address: the address of the register to be written
  79  * @val: the value to write
  80  **/
  81 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  82                               u8 reg_address,
  83                               u8 val)
  84 {
  85         int ret;
  86         struct lis3l02dq_state *st = iio_priv(indio_dev);
  87
  88         mutex_lock(&st->buf_lock);
  89         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  90         st->tx[1] = val;
  91         ret = spi_write(st->us, st->tx, 2);
  92         mutex_unlock(&st->buf_lock);
  93
  94         return ret;
  95 }
  96
  97 /**
  98  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
  99  * @indio_dev: iio_dev for this device
 100  * @lower_reg_address: the address of the lower of the two registers.
 101  *               Second register is assumed to have address one greater.
 102  * @value: value to be written
 103  **/
 104 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 105                                        u8 lower_reg_address,
 106                                        s16 value)
 107 {
 108         int ret;
 109         struct lis3l02dq_state *st = iio_priv(indio_dev);
 110         struct spi_transfer xfers[] = { {
 111                         .tx_buf = st->tx,
 112                         .bits_per_word = 8,
 113                         .len = 2,
 114                         .cs_change = 1,
 115                 }, {
 116                         .tx_buf = st->tx + 2,
 117                         .bits_per_word = 8,
 118                         .len = 2,
 119                 },
 120         };
 121
 122         mutex_lock(&st->buf_lock);
 123         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 124         st->tx[1] = value & 0xFF;
 125         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 126         st->tx[3] = (value >> 8) & 0xFF;
 127
 128         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 129         mutex_unlock(&st->buf_lock);
 130
 131         return ret;
 132 }
 133
 134 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 135                                   u8 lower_reg_address,
 136                                   int *val)
 137 {
 138         struct lis3l02dq_state *st = iio_priv(indio_dev);
 139         int ret;
 140         s16 tempval;
 141         struct spi_transfer xfers[] = { {
 142                         .tx_buf = st->tx,
 143                         .rx_buf = st->rx,
 144                         .bits_per_word = 8,
 145                         .len = 2,
 146                         .cs_change = 1,
 147                 }, {
 148                         .tx_buf = st->tx + 2,
 149                         .rx_buf = st->rx + 2,
 150                         .bits_per_word = 8,
 151                         .len = 2,
 152                 },
 153         };
 154
 155         mutex_lock(&st->buf_lock);
 156         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 157         st->tx[1] = 0;
 158         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 159         st->tx[3] = 0;
 160
 161         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 162         if (ret) {
 163                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 164                 goto error_ret;
 165         }
 166         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 167
 168         *val = tempval;
 169 error_ret:
 170         mutex_unlock(&st->buf_lock);
 171         return ret;
 172 }
 173
 174 enum lis3l02dq_rm_ind {
 175         LIS3L02DQ_ACCEL,
 176         LIS3L02DQ_GAIN,
 177         LIS3L02DQ_BIAS,
 178 };
 179
 180 static u8 lis3l02dq_axis_map[3][3] = {
 181         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 182                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 183                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 184         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 185                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 186                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 187         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 188                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 189                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 190 };
 191
 192 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 193                                  const struct iio_chan_spec *chan,
 194                                  enum iio_event_type type,
 195                                  enum iio_event_direction dir,
 196                                  enum iio_event_info info,
 197                                  int *val, int *val2)
 198 {
 199         int ret;
 200
 201         ret = lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 202         if (ret)
 203                 return ret;
 204         return IIO_VAL_INT;
 205 }
 206
 207 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 208                                   const struct iio_chan_spec *chan,
 209                                   enum iio_event_type type,
 210                                   enum iio_event_direction dir,
 211                                   enum iio_event_info info,
 212                                   int val, int val2)
 213 {
 214         u16 value = val;
 215
 216         return lis3l02dq_spi_write_reg_s16(indio_dev,
 217                                            LIS3L02DQ_REG_THS_L_ADDR,
 218                                            value);
 219 }
 220
 221 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 222                                struct iio_chan_spec const *chan,
 223                                int val,
 224                                int val2,
 225                                long mask)
 226 {
 227         int ret = -EINVAL, reg;
 228         u8 uval;
 229         s8 sval;
 230
 231         switch (mask) {
 232         case IIO_CHAN_INFO_CALIBBIAS:
 233                 if (val > 255 || val < -256)
 234                         return -EINVAL;
 235                 sval = val;
 236                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 237                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
 238                 break;
 239         case IIO_CHAN_INFO_CALIBSCALE:
 240                 if (val & ~0xFF)
 241                         return -EINVAL;
 242                 uval = val;
 243                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 244                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
 245                 break;
 246         }
 247         return ret;
 248 }
 249
 250 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 251                               struct iio_chan_spec const *chan,
 252                               int *val,
 253                               int *val2,
 254                               long mask)
 255 {
 256         u8 utemp;
 257         s8 stemp;
 258         ssize_t ret = 0;
 259         u8 reg;
 260
 261         switch (mask) {
 262         case IIO_CHAN_INFO_RAW:
 263                 /* Take the iio_dev status lock */
 264                 mutex_lock(&indio_dev->mlock);
 265                 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
 266                         ret = -EBUSY;
 267                 } else {
 268                         reg = lis3l02dq_axis_map
 269                                 [LIS3L02DQ_ACCEL][chan->address];
 270                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 271                 }
 272                 mutex_unlock(&indio_dev->mlock);
 273                 if (ret < 0)
 274                         goto error_ret;
 275                 return IIO_VAL_INT;
 276         case IIO_CHAN_INFO_SCALE:
 277                 *val = 0;
 278                 *val2 = 9580;
 279                 return IIO_VAL_INT_PLUS_MICRO;
 280         case IIO_CHAN_INFO_CALIBSCALE:
 281                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 282                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 283                 if (ret)
 284                         goto error_ret;
 285                 /* to match with what previous code does */
 286                 *val = utemp;
 287                 return IIO_VAL_INT;
 288
 289         case IIO_CHAN_INFO_CALIBBIAS:
 290                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 291                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 292                 /* to match with what previous code does */
 293                 *val = stemp;
 294                 return IIO_VAL_INT;
 295         }
 296 error_ret:
 297         return ret;
 298 }
 299
 300 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 301                                         struct device_attribute *attr,
 302                                         char *buf)
 303 {
 304         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 305         int ret, len = 0;
 306         s8 t;
 307
 308         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 309                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 310                                        (u8 *)&t);
 311         if (ret)
 312                 return ret;
 313         t &= LIS3L02DQ_DEC_MASK;
 314         switch (t) {
 315         case LIS3L02DQ_REG_CTRL_1_DF_128:
 316                 len = sprintf(buf, "280\n");
 317                 break;
 318         case LIS3L02DQ_REG_CTRL_1_DF_64:
 319                 len = sprintf(buf, "560\n");
 320                 break;
 321         case LIS3L02DQ_REG_CTRL_1_DF_32:
 322                 len = sprintf(buf, "1120\n");
 323                 break;
 324         case LIS3L02DQ_REG_CTRL_1_DF_8:
 325                 len = sprintf(buf, "4480\n");
 326                 break;
 327         }
 328         return len;
 329 }
 330
 331 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 332                                          struct device_attribute *attr,
 333                                          const char *buf,
 334                                          size_t len)
 335 {
 336         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 337         unsigned long val;
 338         int ret;
 339         u8 t;
 340
 341         ret = kstrtoul(buf, 10, &val);
 342         if (ret)
 343                 return ret;
 344
 345         mutex_lock(&indio_dev->mlock);
 346         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 347                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 348                                        &t);
 349         if (ret)
 350                 goto error_ret_mutex;
 351         /* Wipe the bits clean */
 352         t &= ~LIS3L02DQ_DEC_MASK;
 353         switch (val) {
 354         case 280:
 355                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 356                 break;
 357         case 560:
 358                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 359                 break;
 360         case 1120:
 361                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 362                 break;
 363         case 4480:
 364                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 365                 break;
 366         default:
 367                 ret = -EINVAL;
 368                 goto error_ret_mutex;
 369         }
 370
 371         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 372                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 373                                         t);
 374
 375 error_ret_mutex:
 376         mutex_unlock(&indio_dev->mlock);
 377
 378         return ret ? ret : len;
 379 }
 380
 381 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
 382 {
 383         struct lis3l02dq_state *st = iio_priv(indio_dev);
 384         int ret;
 385         u8 val, valtest;
 386
 387         st->us->mode = SPI_MODE_3;
 388
 389         spi_setup(st->us);
 390
 391         val = LIS3L02DQ_DEFAULT_CTRL1;
 392         /* Write suitable defaults to ctrl1 */
 393         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 394                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 395                                         val);
 396         if (ret) {
 397                 dev_err(&st->us->dev, "problem with setup control register 1");
 398                 goto err_ret;
 399         }
 400         /* Repeat as sometimes doesn't work first time? */
 401         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 402                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 403                                         val);
 404         if (ret) {
 405                 dev_err(&st->us->dev, "problem with setup control register 1");
 406                 goto err_ret;
 407         }
 408
 409         /*
 410          * Read back to check this has worked acts as loose test of correct
 411          * chip
 412          */
 413         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 414                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 415                                        &valtest);
 416         if (ret || (valtest != val)) {
 417                 dev_err(&indio_dev->dev,
 418                         "device not playing ball %d %d\n", valtest, val);
 419                 ret = -EINVAL;
 420                 goto err_ret;
 421         }
 422
 423         val = LIS3L02DQ_DEFAULT_CTRL2;
 424         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 425                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 426                                         val);
 427         if (ret) {
 428                 dev_err(&st->us->dev, "problem with setup control register 2");
 429                 goto err_ret;
 430         }
 431
 432         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 433         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 434                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 435                                         val);
 436         if (ret)
 437                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 438 err_ret:
 439
 440         return ret;
 441 }
 442
 443 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 444                               lis3l02dq_read_frequency,
 445                               lis3l02dq_write_frequency);
 446
 447 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 448
 449 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 450 {
 451         struct iio_dev *indio_dev = private;
 452         u8 t;
 453
 454         s64 timestamp = iio_get_time_ns();
 455
 456         lis3l02dq_spi_read_reg_8(indio_dev,
 457                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 458                                  &t);
 459
 460         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 461                 iio_push_event(indio_dev,
 462                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 463                                                   0,
 464                                                   IIO_MOD_Z,
 465                                                   IIO_EV_TYPE_THRESH,
 466                                                   IIO_EV_DIR_RISING),
 467                                timestamp);
 468
 469         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 470                 iio_push_event(indio_dev,
 471                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 472                                                   0,
 473                                                   IIO_MOD_Z,
 474                                                   IIO_EV_TYPE_THRESH,
 475                                                   IIO_EV_DIR_FALLING),
 476                                timestamp);
 477
 478         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 479                 iio_push_event(indio_dev,
 480                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 481                                                   0,
 482                                                   IIO_MOD_Y,
 483                                                   IIO_EV_TYPE_THRESH,
 484                                                   IIO_EV_DIR_RISING),
 485                                timestamp);
 486
 487         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 488                 iio_push_event(indio_dev,
 489                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 490                                                   0,
 491                                                   IIO_MOD_Y,
 492                                                   IIO_EV_TYPE_THRESH,
 493                                                   IIO_EV_DIR_FALLING),
 494                                timestamp);
 495
 496         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 497                 iio_push_event(indio_dev,
 498                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 499                                                   0,
 500                                                   IIO_MOD_X,
 501                                                   IIO_EV_TYPE_THRESH,
 502                                                   IIO_EV_DIR_RISING),
 503                                timestamp);
 504
 505         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 506                 iio_push_event(indio_dev,
 507                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 508                                                   0,
 509                                                   IIO_MOD_X,
 510                                                   IIO_EV_TYPE_THRESH,
 511                                                   IIO_EV_DIR_FALLING),
 512                                timestamp);
 513
 514         /* Ack and allow for new interrupts */
 515         lis3l02dq_spi_read_reg_8(indio_dev,
 516                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 517                                  &t);
 518
 519         return IRQ_HANDLED;
 520 }
 521
 522 static const struct iio_event_spec lis3l02dq_event[] = {
 523         {
 524                 .type = IIO_EV_TYPE_THRESH,
 525                 .dir = IIO_EV_DIR_RISING,
 526                 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
 527                 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
 528         }, {
 529                 .type = IIO_EV_TYPE_THRESH,
 530                 .dir = IIO_EV_DIR_FALLING,
 531                 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
 532                 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
 533         }
 534 };
 535
 536 #define LIS3L02DQ_CHAN(index, mod)                              \
 537         {                                                       \
 538                 .type = IIO_ACCEL,                              \
 539                 .modified = 1,                                  \
 540                 .channel2 = mod,                                \
 541                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
 542                         BIT(IIO_CHAN_INFO_CALIBSCALE) |         \
 543                         BIT(IIO_CHAN_INFO_CALIBBIAS),           \
 544                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
 545                 .address = index,                               \
 546                 .scan_index = index,                            \
 547                 .scan_type = {                                  \
 548                         .sign = 's',                            \
 549                         .realbits = 12,                         \
 550                         .storagebits = 16,                      \
 551                 },                                              \
 552                 .event_spec = lis3l02dq_event,                  \
 553                 .num_event_specs = ARRAY_SIZE(lis3l02dq_event), \
 554          }
 555
 556 static const struct iio_chan_spec lis3l02dq_channels[] = {
 557         LIS3L02DQ_CHAN(0, IIO_MOD_X),
 558         LIS3L02DQ_CHAN(1, IIO_MOD_Y),
 559         LIS3L02DQ_CHAN(2, IIO_MOD_Z),
 560         IIO_CHAN_SOFT_TIMESTAMP(3)
 561 };
 562
 563 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 564                                        const struct iio_chan_spec *chan,
 565                                        enum iio_event_type type,
 566                                        enum iio_event_direction dir)
 567 {
 568         u8 val;
 569         int ret;
 570         u8 mask = (1 << (chan->channel2 * 2 + (dir == IIO_EV_DIR_RISING)));
 571
 572         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 573                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 574                                        &val);
 575         if (ret < 0)
 576                 return ret;
 577
 578         return !!(val & mask);
 579 }
 580
 581 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 582 {
 583         int ret;
 584         u8 control, val;
 585
 586         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 587                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 588                                        &control);
 589
 590         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 591         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 592                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 593                                         control);
 594         if (ret)
 595                 goto error_ret;
 596         /* Also for consistency clear the mask */
 597         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 598                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 599                                        &val);
 600         if (ret)
 601                 goto error_ret;
 602         val &= ~0x3f;
 603
 604         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 605                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 606                                         val);
 607         if (ret)
 608                 goto error_ret;
 609
 610         ret = control;
 611 error_ret:
 612         return ret;
 613 }
 614
 615 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 616                                         const struct iio_chan_spec *chan,
 617                                         enum iio_event_type type,
 618                                         enum iio_event_direction dir,
 619                                         int state)
 620 {
 621         int ret = 0;
 622         u8 val, control;
 623         u8 currentlyset;
 624         bool changed = false;
 625         u8 mask = (1 << (chan->channel2 * 2 + (dir == IIO_EV_DIR_RISING)));
 626
 627         mutex_lock(&indio_dev->mlock);
 628         /* read current control */
 629         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 630                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 631                                        &control);
 632         if (ret)
 633                 goto error_ret;
 634         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 635                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 636                                        &val);
 637         if (ret < 0)
 638                 goto error_ret;
 639         currentlyset = val & mask;
 640
 641         if (!currentlyset && state) {
 642                 changed = true;
 643                 val |= mask;
 644         } else if (currentlyset && !state) {
 645                 changed = true;
 646                 val &= ~mask;
 647         }
 648
 649         if (changed) {
 650                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 651                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 652                                                 val);
 653                 if (ret)
 654                         goto error_ret;
 655                 control = val & 0x3f ?
 656                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 657                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 658                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 659                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 660                                                 control);
 661                 if (ret)
 662                         goto error_ret;
 663         }
 664
 665 error_ret:
 666         mutex_unlock(&indio_dev->mlock);
 667         return ret;
 668 }
 669
 670 static struct attribute *lis3l02dq_attributes[] = {
 671         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 672         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 673         NULL
 674 };
 675
 676 static const struct attribute_group lis3l02dq_attribute_group = {
 677         .attrs = lis3l02dq_attributes,
 678 };
 679
 680 static const struct iio_info lis3l02dq_info = {
 681         .read_raw = &lis3l02dq_read_raw,
 682         .write_raw = &lis3l02dq_write_raw,
 683         .read_event_value = &lis3l02dq_read_thresh,
 684         .write_event_value = &lis3l02dq_write_thresh,
 685         .write_event_config = &lis3l02dq_write_event_config,
 686         .read_event_config = &lis3l02dq_read_event_config,
 687         .driver_module = THIS_MODULE,
 688         .attrs = &lis3l02dq_attribute_group,
 689 };
 690
 691 static int lis3l02dq_probe(struct spi_device *spi)
 692 {
 693         int ret;
 694         struct lis3l02dq_state *st;
 695         struct iio_dev *indio_dev;
 696
 697         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 698         if (!indio_dev)
 699                 return -ENOMEM;
 700         st = iio_priv(indio_dev);
 701         /* this is only used for removal purposes */
 702         spi_set_drvdata(spi, indio_dev);
 703
 704         st->us = spi;
 705         st->gpio = of_get_gpio(spi->dev.of_node, 0);
 706         mutex_init(&st->buf_lock);
 707         indio_dev->name = spi->dev.driver->name;
 708         indio_dev->dev.parent = &spi->dev;
 709         indio_dev->info = &lis3l02dq_info;
 710         indio_dev->channels = lis3l02dq_channels;
 711         indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 712
 713         indio_dev->modes = INDIO_DIRECT_MODE;
 714
 715         ret = lis3l02dq_configure_buffer(indio_dev);
 716         if (ret)
 717                 return ret;
 718
 719         if (spi->irq) {
 720                 ret = request_threaded_irq(st->us->irq,
 721                                            &lis3l02dq_th,
 722                                            &lis3l02dq_event_handler,
 723                                            IRQF_TRIGGER_RISING,
 724                                            "lis3l02dq",
 725                                            indio_dev);
 726                 if (ret)
 727                         goto error_unreg_buffer_funcs;
 728
 729                 ret = lis3l02dq_probe_trigger(indio_dev);
 730                 if (ret)
 731                         goto error_free_interrupt;
 732         }
 733
 734         /* Get the device into a sane initial state */
 735         ret = lis3l02dq_initial_setup(indio_dev);
 736         if (ret)
 737                 goto error_remove_trigger;
 738
 739         ret = iio_device_register(indio_dev);
 740         if (ret)
 741                 goto error_remove_trigger;
 742
 743         return 0;
 744
 745 error_remove_trigger:
 746         if (spi->irq)
 747                 lis3l02dq_remove_trigger(indio_dev);
 748 error_free_interrupt:
 749         if (spi->irq)
 750                 free_irq(st->us->irq, indio_dev);
 751 error_unreg_buffer_funcs:
 752         lis3l02dq_unconfigure_buffer(indio_dev);
 753         return ret;
 754 }
 755
 756 /* Power down the device */
 757 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 758 {
 759         int ret;
 760         struct lis3l02dq_state *st = iio_priv(indio_dev);
 761         u8 val = 0;
 762
 763         mutex_lock(&indio_dev->mlock);
 764         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 765                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 766                                         val);
 767         if (ret) {
 768                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 769                 goto err_ret;
 770         }
 771
 772         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 773                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 774                                         val);
 775         if (ret)
 776                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 777 err_ret:
 778         mutex_unlock(&indio_dev->mlock);
 779         return ret;
 780 }
 781
 782 /* fixme, confirm ordering in this function */
 783 static int lis3l02dq_remove(struct spi_device *spi)
 784 {
 785         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 786         struct lis3l02dq_state *st = iio_priv(indio_dev);
 787
 788         iio_device_unregister(indio_dev);
 789
 790         lis3l02dq_disable_all_events(indio_dev);
 791         lis3l02dq_stop_device(indio_dev);
 792
 793         if (spi->irq)
 794                 free_irq(st->us->irq, indio_dev);
 795
 796         lis3l02dq_remove_trigger(indio_dev);
 797         lis3l02dq_unconfigure_buffer(indio_dev);
 798
 799         return 0;
 800 }
 801
 802 static struct spi_driver lis3l02dq_driver = {
 803         .driver = {
 804                 .name = "lis3l02dq",
 805         },
 806         .probe = lis3l02dq_probe,
 807         .remove = lis3l02dq_remove,
 808 };
 809 module_spi_driver(lis3l02dq_driver);
 810
 811 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
 812 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 813 MODULE_LICENSE("GPL v2");
 814 MODULE_ALIAS("spi:lis3l02dq");