1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #include "odm_precomp.h"
25 #define read_next_pair(array, v1, v2, i) \
35 static u32 array_agc_tab_1t_8188e[] = {
166 static bool set_baseband_agc_config(struct adapter *adapt)
169 u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32);
170 u32 *array = array_agc_tab_1t_8188e;
172 for (i = 0; i < arraylen; i += 2) {
176 if (v1 < 0xCDCDCDCD){
177 PHY_SetBBReg(adapt, v1, bMaskDWord, v2);
186 static u32 array_phy_reg_1t_8188e[] = {
380 static void rtl_bb_delay(struct adapter *adapt, u32 addr, u32 data)
384 } else if (addr == 0xfd) {
386 } else if (addr == 0xfc) {
388 } else if (addr == 0xfb) {
390 } else if (addr == 0xfa) {
392 } else if (addr == 0xf9) {
395 PHY_SetBBReg(adapt, addr, bMaskDWord, data);
396 /* Add 1us delay between BB/RF register setting. */
401 static bool set_baseband_phy_config(struct adapter *adapt)
404 u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32);
405 u32 *array = array_phy_reg_1t_8188e;
407 for (i = 0; i < arraylen; i += 2) {
412 rtl_bb_delay(adapt, v1, v2);
419 static u32 array_phy_reg_pg_8188e[] = {
420 0xE00, 0xFFFFFFFF, 0x06070809,
421 0xE04, 0xFFFFFFFF, 0x02020405,
422 0xE08, 0x0000FF00, 0x00000006,
423 0x86C, 0xFFFFFF00, 0x00020400,
424 0xE10, 0xFFFFFFFF, 0x08090A0B,
425 0xE14, 0xFFFFFFFF, 0x01030607,
426 0xE18, 0xFFFFFFFF, 0x08090A0B,
427 0xE1C, 0xFFFFFFFF, 0x01030607,
428 0xE00, 0xFFFFFFFF, 0x00000000,
429 0xE04, 0xFFFFFFFF, 0x00000000,
430 0xE08, 0x0000FF00, 0x00000000,
431 0x86C, 0xFFFFFF00, 0x00000000,
432 0xE10, 0xFFFFFFFF, 0x00000000,
433 0xE14, 0xFFFFFFFF, 0x00000000,
434 0xE18, 0xFFFFFFFF, 0x00000000,
435 0xE1C, 0xFFFFFFFF, 0x00000000,
436 0xE00, 0xFFFFFFFF, 0x02020202,
437 0xE04, 0xFFFFFFFF, 0x00020202,
438 0xE08, 0x0000FF00, 0x00000000,
439 0x86C, 0xFFFFFF00, 0x00000000,
440 0xE10, 0xFFFFFFFF, 0x04040404,
441 0xE14, 0xFFFFFFFF, 0x00020404,
442 0xE18, 0xFFFFFFFF, 0x00000000,
443 0xE1C, 0xFFFFFFFF, 0x00000000,
444 0xE00, 0xFFFFFFFF, 0x02020202,
445 0xE04, 0xFFFFFFFF, 0x00020202,
446 0xE08, 0x0000FF00, 0x00000000,
447 0x86C, 0xFFFFFF00, 0x00000000,
448 0xE10, 0xFFFFFFFF, 0x04040404,
449 0xE14, 0xFFFFFFFF, 0x00020404,
450 0xE18, 0xFFFFFFFF, 0x00000000,
451 0xE1C, 0xFFFFFFFF, 0x00000000,
452 0xE00, 0xFFFFFFFF, 0x00000000,
453 0xE04, 0xFFFFFFFF, 0x00000000,
454 0xE08, 0x0000FF00, 0x00000000,
455 0x86C, 0xFFFFFF00, 0x00000000,
456 0xE10, 0xFFFFFFFF, 0x00000000,
457 0xE14, 0xFFFFFFFF, 0x00000000,
458 0xE18, 0xFFFFFFFF, 0x00000000,
459 0xE1C, 0xFFFFFFFF, 0x00000000,
460 0xE00, 0xFFFFFFFF, 0x02020202,
461 0xE04, 0xFFFFFFFF, 0x00020202,
462 0xE08, 0x0000FF00, 0x00000000,
463 0x86C, 0xFFFFFF00, 0x00000000,
464 0xE10, 0xFFFFFFFF, 0x04040404,
465 0xE14, 0xFFFFFFFF, 0x00020404,
466 0xE18, 0xFFFFFFFF, 0x00000000,
467 0xE1C, 0xFFFFFFFF, 0x00000000,
468 0xE00, 0xFFFFFFFF, 0x00000000,
469 0xE04, 0xFFFFFFFF, 0x00000000,
470 0xE08, 0x0000FF00, 0x00000000,
471 0x86C, 0xFFFFFF00, 0x00000000,
472 0xE10, 0xFFFFFFFF, 0x00000000,
473 0xE14, 0xFFFFFFFF, 0x00000000,
474 0xE18, 0xFFFFFFFF, 0x00000000,
475 0xE1C, 0xFFFFFFFF, 0x00000000,
476 0xE00, 0xFFFFFFFF, 0x00000000,
477 0xE04, 0xFFFFFFFF, 0x00000000,
478 0xE08, 0x0000FF00, 0x00000000,
479 0x86C, 0xFFFFFF00, 0x00000000,
480 0xE10, 0xFFFFFFFF, 0x00000000,
481 0xE14, 0xFFFFFFFF, 0x00000000,
482 0xE18, 0xFFFFFFFF, 0x00000000,
483 0xE1C, 0xFFFFFFFF, 0x00000000,
484 0xE00, 0xFFFFFFFF, 0x00000000,
485 0xE04, 0xFFFFFFFF, 0x00000000,
486 0xE08, 0x0000FF00, 0x00000000,
487 0x86C, 0xFFFFFF00, 0x00000000,
488 0xE10, 0xFFFFFFFF, 0x00000000,
489 0xE14, 0xFFFFFFFF, 0x00000000,
490 0xE18, 0xFFFFFFFF, 0x00000000,
491 0xE1C, 0xFFFFFFFF, 0x00000000,
492 0xE00, 0xFFFFFFFF, 0x00000000,
493 0xE04, 0xFFFFFFFF, 0x00000000,
494 0xE08, 0x0000FF00, 0x00000000,
495 0x86C, 0xFFFFFF00, 0x00000000,
496 0xE10, 0xFFFFFFFF, 0x00000000,
497 0xE14, 0xFFFFFFFF, 0x00000000,
498 0xE18, 0xFFFFFFFF, 0x00000000,
499 0xE1C, 0xFFFFFFFF, 0x00000000,
500 0xE00, 0xFFFFFFFF, 0x00000000,
501 0xE04, 0xFFFFFFFF, 0x00000000,
502 0xE08, 0x0000FF00, 0x00000000,
503 0x86C, 0xFFFFFF00, 0x00000000,
504 0xE10, 0xFFFFFFFF, 0x00000000,
505 0xE14, 0xFFFFFFFF, 0x00000000,
506 0xE18, 0xFFFFFFFF, 0x00000000,
507 0xE1C, 0xFFFFFFFF, 0x00000000,
511 static void store_pwrindex_offset(struct adapter *Adapter, u32 regaddr, u32 bitmask, u32 data)
513 struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
515 if (regaddr == rTxAGC_A_Rate18_06)
516 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][0] = data;
517 if (regaddr == rTxAGC_A_Rate54_24)
518 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][1] = data;
519 if (regaddr == rTxAGC_A_CCK1_Mcs32)
520 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][6] = data;
521 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
522 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][7] = data;
523 if (regaddr == rTxAGC_A_Mcs03_Mcs00)
524 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][2] = data;
525 if (regaddr == rTxAGC_A_Mcs07_Mcs04)
526 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][3] = data;
527 if (regaddr == rTxAGC_A_Mcs11_Mcs08)
528 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][4] = data;
529 if (regaddr == rTxAGC_A_Mcs15_Mcs12) {
530 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][5] = data;
531 if (hal_data->rf_type == RF_1T1R)
532 hal_data->pwrGroupCnt++;
534 if (regaddr == rTxAGC_B_Rate18_06)
535 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][8] = data;
536 if (regaddr == rTxAGC_B_Rate54_24)
537 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][9] = data;
538 if (regaddr == rTxAGC_B_CCK1_55_Mcs32)
539 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][14] = data;
540 if (regaddr == rTxAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
541 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][15] = data;
542 if (regaddr == rTxAGC_B_Mcs03_Mcs00)
543 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][10] = data;
544 if (regaddr == rTxAGC_B_Mcs07_Mcs04)
545 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][11] = data;
546 if (regaddr == rTxAGC_B_Mcs11_Mcs08)
547 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][12] = data;
548 if (regaddr == rTxAGC_B_Mcs15_Mcs12) {
549 hal_data->MCSTxPowerLevelOriginalOffset[hal_data->pwrGroupCnt][13] = data;
550 if (hal_data->rf_type != RF_1T1R)
551 hal_data->pwrGroupCnt++;
555 static void rtl_addr_delay(struct adapter *adapt, u32 addr, u32 bit_mask ,u32 data)
559 } else if (addr == 0xfd) {
561 } else if (addr == 0xfc) {
563 } else if (addr == 0xfb) {
565 } else if (addr == 0xfa) {
567 } else if (addr == 0xf9) {
570 store_pwrindex_offset(adapt, addr, bit_mask, data);
574 static bool config_bb_with_pgheader(struct adapter *adapt)
577 u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32);
578 u32 *array = array_phy_reg_pg_8188e;
580 for (i = 0; i < arraylen; i += 3) {
586 rtl_addr_delay(adapt, v1, v2, v3);
591 static void rtl88e_phy_init_bb_rf_register_definition(struct adapter *Adapter)
593 struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
595 hal_data->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
596 hal_data->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
597 hal_data->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
598 hal_data->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
600 hal_data->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
601 hal_data->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
602 hal_data->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
603 hal_data->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
605 hal_data->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
606 hal_data->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
608 hal_data->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
609 hal_data->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
611 hal_data->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
612 hal_data->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
614 hal_data->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
615 hal_data->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
616 hal_data->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
617 hal_data->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
619 hal_data->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
620 hal_data->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
621 hal_data->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
622 hal_data->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
624 hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
625 hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
627 hal_data->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
628 hal_data->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
630 hal_data->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
631 hal_data->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
632 hal_data->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
633 hal_data->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
635 hal_data->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
636 hal_data->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
637 hal_data->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
638 hal_data->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
640 hal_data->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
641 hal_data->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
642 hal_data->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
643 hal_data->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
645 hal_data->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
646 hal_data->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
647 hal_data->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
648 hal_data->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
650 hal_data->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
651 hal_data->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
652 hal_data->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
653 hal_data->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
655 hal_data->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
656 hal_data->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
657 hal_data->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
658 hal_data->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
660 hal_data->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
661 hal_data->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
662 hal_data->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
663 hal_data->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
665 hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
666 hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
667 hal_data->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
668 hal_data->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
670 hal_data->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
671 hal_data->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
674 static bool config_parafile(struct adapter *adapt)
676 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(adapt);
677 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
679 set_baseband_phy_config(adapt);
681 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
682 if (!pEEPROM->bautoload_fail_flag) {
683 hal_data->pwrGroupCnt = 0;
684 config_bb_with_pgheader(adapt);
686 set_baseband_agc_config(adapt);
690 bool rtl88e_phy_bb_config(struct adapter *adapt)
693 struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
697 rtl88e_phy_init_bb_rf_register_definition(adapt);
699 /* Enable BB and RF */
700 regval = usb_read16(adapt, REG_SYS_FUNC_EN);
701 usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1));
703 usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
705 usb_write8(adapt, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
707 /* Config BB and AGC */
708 rtstatus = config_parafile(adapt);
710 /* write 0x24[16:11] = 0x24[22:17] = crystal_cap */
711 crystal_cap = hal_data->CrystalCap & 0x3F;
712 PHY_SetBBReg(adapt, REG_AFE_XTAL_CTRL, 0x7ff800, (crystal_cap | (crystal_cap << 6)));