drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43 #include <linux/pinctrl/consumer.h>
  44
  45 #include <plat/omap-serial.h>
  46
  47 #define OMAP_MAX_HSUART_PORTS   6
  48
  49 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  50
  51 #define OMAP_UART_REV_42 0x0402
  52 #define OMAP_UART_REV_46 0x0406
  53 #define OMAP_UART_REV_52 0x0502
  54 #define OMAP_UART_REV_63 0x0603
  55
  56 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  57 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  58
  59 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  60
  61 /* SCR register bitmasks */
  62 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  63 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  64
  65 /* FCR register bitmasks */
  66 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  67 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  68
  69 /* MVR register bitmasks */
  70 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  71
  72 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  73 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  74 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  75
  76 #define OMAP_UART_MVR_MAJ_MASK          0x700
  77 #define OMAP_UART_MVR_MAJ_SHIFT         8
  78 #define OMAP_UART_MVR_MIN_MASK          0x3f
  79
  80 #define OMAP_UART_DMA_CH_FREE   -1
  81
  82 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  83 #define OMAP_MODE13X_SPEED      230400
  84
  85 /* WER = 0x7F
  86  * Enable module level wakeup in WER reg
  87  */
  88 #define OMAP_UART_WER_MOD_WKUP  0X7F
  89
  90 /* Enable XON/XOFF flow control on output */
  91 #define OMAP_UART_SW_TX         0x08
  92
  93 /* Enable XON/XOFF flow control on input */
  94 #define OMAP_UART_SW_RX         0x02
  95
  96 #define OMAP_UART_SW_CLR        0xF0
  97
  98 #define OMAP_UART_TCR_TRIG      0x0F
  99
 100 struct uart_omap_dma {
 101         u8                      uart_dma_tx;
 102         u8                      uart_dma_rx;
 103         int                     rx_dma_channel;
 104         int                     tx_dma_channel;
 105         dma_addr_t              rx_buf_dma_phys;
 106         dma_addr_t              tx_buf_dma_phys;
 107         unsigned int            uart_base;
 108         /*
 109          * Buffer for rx dma.It is not required for tx because the buffer
 110          * comes from port structure.
 111          */
 112         unsigned char           *rx_buf;
 113         unsigned int            prev_rx_dma_pos;
 114         int                     tx_buf_size;
 115         int                     tx_dma_used;
 116         int                     rx_dma_used;
 117         spinlock_t              tx_lock;
 118         spinlock_t              rx_lock;
 119         /* timer to poll activity on rx dma */
 120         struct timer_list       rx_timer;
 121         unsigned int            rx_buf_size;
 122         unsigned int            rx_poll_rate;
 123         unsigned int            rx_timeout;
 124 };
 125
 126 struct uart_omap_port {
 127         struct uart_port        port;
 128         struct uart_omap_dma    uart_dma;
 129         struct device           *dev;
 130
 131         unsigned char           ier;
 132         unsigned char           lcr;
 133         unsigned char           mcr;
 134         unsigned char           fcr;
 135         unsigned char           efr;
 136         unsigned char           dll;
 137         unsigned char           dlh;
 138         unsigned char           mdr1;
 139         unsigned char           scr;
 140
 141         int                     use_dma;
 142         /*
 143          * Some bits in registers are cleared on a read, so they must
 144          * be saved whenever the register is read but the bits will not
 145          * be immediately processed.
 146          */
 147         unsigned int            lsr_break_flag;
 148         unsigned char           msr_saved_flags;
 149         char                    name[20];
 150         unsigned long           port_activity;
 151         u32                     context_loss_cnt;
 152         u32                     errata;
 153         u8                      wakeups_enabled;
 154
 155         int                     DTR_gpio;
 156         int                     DTR_inverted;
 157         int                     DTR_active;
 158
 159         struct pm_qos_request   pm_qos_request;
 160         u32                     latency;
 161         u32                     calc_latency;
 162         struct work_struct      qos_work;
 163         struct pinctrl          *pins;
 164 };
 165
 166 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 167
 168 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 169
 170 /* Forward declaration of functions */
 171 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 172
 173 static struct workqueue_struct *serial_omap_uart_wq;
 174
 175 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 176 {
 177         offset <<= up->port.regshift;
 178         return readw(up->port.membase + offset);
 179 }
 180
 181 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 182 {
 183         offset <<= up->port.regshift;
 184         writew(value, up->port.membase + offset);
 185 }
 186
 187 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 188 {
 189         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 190         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 191                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 192         serial_out(up, UART_FCR, 0);
 193 }
 194
 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 196 {
 197         struct omap_uart_port_info *pdata = up->dev->platform_data;
 198
 199         if (!pdata || !pdata->get_context_loss_count)
 200                 return 0;
 201
 202         return pdata->get_context_loss_count(up->dev);
 203 }
 204
 205 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 206 {
 207         struct omap_uart_port_info *pdata = up->dev->platform_data;
 208
 209         if (!pdata || !pdata->set_forceidle)
 210                 return;
 211
 212         pdata->set_forceidle(up->dev);
 213 }
 214
 215 static void serial_omap_set_noidle(struct uart_omap_port *up)
 216 {
 217         struct omap_uart_port_info *pdata = up->dev->platform_data;
 218
 219         if (!pdata || !pdata->set_noidle)
 220                 return;
 221
 222         pdata->set_noidle(up->dev);
 223 }
 224
 225 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 226 {
 227         struct omap_uart_port_info *pdata = up->dev->platform_data;
 228
 229         if (!pdata || !pdata->enable_wakeup)
 230                 return;
 231
 232         pdata->enable_wakeup(up->dev, enable);
 233 }
 234
 235 /*
 236  * serial_omap_get_divisor - calculate divisor value
 237  * @port: uart port info
 238  * @baud: baudrate for which divisor needs to be calculated.
 239  *
 240  * We have written our own function to get the divisor so as to support
 241  * 13x mode. 3Mbps Baudrate as an different divisor.
 242  * Reference OMAP TRM Chapter 17:
 243  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 244  * referring to oversampling - divisor value
 245  * baudrate 460,800 to 3,686,400 all have divisor 13
 246  * except 3,000,000 which has divisor value 16
 247  */
 248 static unsigned int
 249 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 250 {
 251         unsigned int divisor;
 252
 253         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 254                 divisor = 13;
 255         else
 256                 divisor = 16;
 257         return port->uartclk/(baud * divisor);
 258 }
 259
 260 static void serial_omap_enable_ms(struct uart_port *port)
 261 {
 262         struct uart_omap_port *up = to_uart_omap_port(port);
 263
 264         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 265
 266         pm_runtime_get_sync(up->dev);
 267         up->ier |= UART_IER_MSI;
 268         serial_out(up, UART_IER, up->ier);
 269         pm_runtime_mark_last_busy(up->dev);
 270         pm_runtime_put_autosuspend(up->dev);
 271 }
 272
 273 static void serial_omap_stop_tx(struct uart_port *port)
 274 {
 275         struct uart_omap_port *up = to_uart_omap_port(port);
 276
 277         pm_runtime_get_sync(up->dev);
 278         if (up->ier & UART_IER_THRI) {
 279                 up->ier &= ~UART_IER_THRI;
 280                 serial_out(up, UART_IER, up->ier);
 281         }
 282
 283         serial_omap_set_forceidle(up);
 284
 285         pm_runtime_mark_last_busy(up->dev);
 286         pm_runtime_put_autosuspend(up->dev);
 287 }
 288
 289 static void serial_omap_stop_rx(struct uart_port *port)
 290 {
 291         struct uart_omap_port *up = to_uart_omap_port(port);
 292
 293         pm_runtime_get_sync(up->dev);
 294         up->ier &= ~UART_IER_RLSI;
 295         up->port.read_status_mask &= ~UART_LSR_DR;
 296         serial_out(up, UART_IER, up->ier);
 297         pm_runtime_mark_last_busy(up->dev);
 298         pm_runtime_put_autosuspend(up->dev);
 299 }
 300
 301 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 302 {
 303         struct circ_buf *xmit = &up->port.state->xmit;
 304         int count;
 305
 306         if (!(lsr & UART_LSR_THRE))
 307                 return;
 308
 309         if (up->port.x_char) {
 310                 serial_out(up, UART_TX, up->port.x_char);
 311                 up->port.icount.tx++;
 312                 up->port.x_char = 0;
 313                 return;
 314         }
 315         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 316                 serial_omap_stop_tx(&up->port);
 317                 return;
 318         }
 319         count = up->port.fifosize / 4;
 320         do {
 321                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 322                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 323                 up->port.icount.tx++;
 324                 if (uart_circ_empty(xmit))
 325                         break;
 326         } while (--count > 0);
 327
 328         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 329                 spin_unlock(&up->port.lock);
 330                 uart_write_wakeup(&up->port);
 331                 spin_lock(&up->port.lock);
 332         }
 333
 334         if (uart_circ_empty(xmit))
 335                 serial_omap_stop_tx(&up->port);
 336 }
 337
 338 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 339 {
 340         if (!(up->ier & UART_IER_THRI)) {
 341                 up->ier |= UART_IER_THRI;
 342                 serial_out(up, UART_IER, up->ier);
 343         }
 344 }
 345
 346 static void serial_omap_start_tx(struct uart_port *port)
 347 {
 348         struct uart_omap_port *up = to_uart_omap_port(port);
 349
 350         pm_runtime_get_sync(up->dev);
 351         serial_omap_enable_ier_thri(up);
 352         serial_omap_set_noidle(up);
 353         pm_runtime_mark_last_busy(up->dev);
 354         pm_runtime_put_autosuspend(up->dev);
 355 }
 356
 357 static void serial_omap_throttle(struct uart_port *port)
 358 {
 359         struct uart_omap_port *up = to_uart_omap_port(port);
 360         unsigned long flags;
 361
 362         pm_runtime_get_sync(up->dev);
 363         spin_lock_irqsave(&up->port.lock, flags);
 364         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 365         serial_out(up, UART_IER, up->ier);
 366         spin_unlock_irqrestore(&up->port.lock, flags);
 367         pm_runtime_mark_last_busy(up->dev);
 368         pm_runtime_put_autosuspend(up->dev);
 369 }
 370
 371 static void serial_omap_unthrottle(struct uart_port *port)
 372 {
 373         struct uart_omap_port *up = to_uart_omap_port(port);
 374         unsigned long flags;
 375
 376         pm_runtime_get_sync(up->dev);
 377         spin_lock_irqsave(&up->port.lock, flags);
 378         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 379         serial_out(up, UART_IER, up->ier);
 380         spin_unlock_irqrestore(&up->port.lock, flags);
 381         pm_runtime_mark_last_busy(up->dev);
 382         pm_runtime_put_autosuspend(up->dev);
 383 }
 384
 385 static unsigned int check_modem_status(struct uart_omap_port *up)
 386 {
 387         unsigned int status;
 388
 389         status = serial_in(up, UART_MSR);
 390         status |= up->msr_saved_flags;
 391         up->msr_saved_flags = 0;
 392         if ((status & UART_MSR_ANY_DELTA) == 0)
 393                 return status;
 394
 395         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 396             up->port.state != NULL) {
 397                 if (status & UART_MSR_TERI)
 398                         up->port.icount.rng++;
 399                 if (status & UART_MSR_DDSR)
 400                         up->port.icount.dsr++;
 401                 if (status & UART_MSR_DDCD)
 402                         uart_handle_dcd_change
 403                                 (&up->port, status & UART_MSR_DCD);
 404                 if (status & UART_MSR_DCTS)
 405                         uart_handle_cts_change
 406                                 (&up->port, status & UART_MSR_CTS);
 407                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 408         }
 409
 410         return status;
 411 }
 412
 413 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 414 {
 415         unsigned int flag;
 416         unsigned char ch = 0;
 417
 418         if (likely(lsr & UART_LSR_DR))
 419                 ch = serial_in(up, UART_RX);
 420
 421         up->port.icount.rx++;
 422         flag = TTY_NORMAL;
 423
 424         if (lsr & UART_LSR_BI) {
 425                 flag = TTY_BREAK;
 426                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 427                 up->port.icount.brk++;
 428                 /*
 429                  * We do the SysRQ and SAK checking
 430                  * here because otherwise the break
 431                  * may get masked by ignore_status_mask
 432                  * or read_status_mask.
 433                  */
 434                 if (uart_handle_break(&up->port))
 435                         return;
 436
 437         }
 438
 439         if (lsr & UART_LSR_PE) {
 440                 flag = TTY_PARITY;
 441                 up->port.icount.parity++;
 442         }
 443
 444         if (lsr & UART_LSR_FE) {
 445                 flag = TTY_FRAME;
 446                 up->port.icount.frame++;
 447         }
 448
 449         if (lsr & UART_LSR_OE)
 450                 up->port.icount.overrun++;
 451
 452 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 453         if (up->port.line == up->port.cons->index) {
 454                 /* Recover the break flag from console xmit */
 455                 lsr |= up->lsr_break_flag;
 456         }
 457 #endif
 458         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 459 }
 460
 461 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 462 {
 463         unsigned char ch = 0;
 464         unsigned int flag;
 465
 466         if (!(lsr & UART_LSR_DR))
 467                 return;
 468
 469         ch = serial_in(up, UART_RX);
 470         flag = TTY_NORMAL;
 471         up->port.icount.rx++;
 472
 473         if (uart_handle_sysrq_char(&up->port, ch))
 474                 return;
 475
 476         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 477 }
 478
 479 /**
 480  * serial_omap_irq() - This handles the interrupt from one port
 481  * @irq: uart port irq number
 482  * @dev_id: uart port info
 483  */
 484 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 485 {
 486         struct uart_omap_port *up = dev_id;
 487         struct tty_struct *tty = up->port.state->port.tty;
 488         unsigned int iir, lsr;
 489         unsigned int type;
 490         irqreturn_t ret = IRQ_NONE;
 491         int max_count = 256;
 492
 493         spin_lock(&up->port.lock);
 494         pm_runtime_get_sync(up->dev);
 495
 496         do {
 497                 iir = serial_in(up, UART_IIR);
 498                 if (iir & UART_IIR_NO_INT)
 499                         break;
 500
 501                 ret = IRQ_HANDLED;
 502                 lsr = serial_in(up, UART_LSR);
 503
 504                 /* extract IRQ type from IIR register */
 505                 type = iir & 0x3e;
 506
 507                 switch (type) {
 508                 case UART_IIR_MSI:
 509                         check_modem_status(up);
 510                         break;
 511                 case UART_IIR_THRI:
 512                         transmit_chars(up, lsr);
 513                         break;
 514                 case UART_IIR_RX_TIMEOUT:
 515                         /* FALLTHROUGH */
 516                 case UART_IIR_RDI:
 517                         serial_omap_rdi(up, lsr);
 518                         break;
 519                 case UART_IIR_RLSI:
 520                         serial_omap_rlsi(up, lsr);
 521                         break;
 522                 case UART_IIR_CTS_RTS_DSR:
 523                         /* simply try again */
 524                         break;
 525                 case UART_IIR_XOFF:
 526                         /* FALLTHROUGH */
 527                 default:
 528                         break;
 529                 }
 530         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 531
 532         spin_unlock(&up->port.lock);
 533
 534         tty_flip_buffer_push(tty);
 535
 536         pm_runtime_mark_last_busy(up->dev);
 537         pm_runtime_put_autosuspend(up->dev);
 538         up->port_activity = jiffies;
 539
 540         return ret;
 541 }
 542
 543 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 544 {
 545         struct uart_omap_port *up = to_uart_omap_port(port);
 546         unsigned long flags = 0;
 547         unsigned int ret = 0;
 548
 549         pm_runtime_get_sync(up->dev);
 550         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 551         spin_lock_irqsave(&up->port.lock, flags);
 552         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 553         spin_unlock_irqrestore(&up->port.lock, flags);
 554         pm_runtime_mark_last_busy(up->dev);
 555         pm_runtime_put_autosuspend(up->dev);
 556         return ret;
 557 }
 558
 559 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 560 {
 561         struct uart_omap_port *up = to_uart_omap_port(port);
 562         unsigned int status;
 563         unsigned int ret = 0;
 564
 565         pm_runtime_get_sync(up->dev);
 566         status = check_modem_status(up);
 567         pm_runtime_mark_last_busy(up->dev);
 568         pm_runtime_put_autosuspend(up->dev);
 569
 570         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 571
 572         if (status & UART_MSR_DCD)
 573                 ret |= TIOCM_CAR;
 574         if (status & UART_MSR_RI)
 575                 ret |= TIOCM_RNG;
 576         if (status & UART_MSR_DSR)
 577                 ret |= TIOCM_DSR;
 578         if (status & UART_MSR_CTS)
 579                 ret |= TIOCM_CTS;
 580         return ret;
 581 }
 582
 583 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 584 {
 585         struct uart_omap_port *up = to_uart_omap_port(port);
 586         unsigned char mcr = 0, old_mcr;
 587
 588         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 589         if (mctrl & TIOCM_RTS)
 590                 mcr |= UART_MCR_RTS;
 591         if (mctrl & TIOCM_DTR)
 592                 mcr |= UART_MCR_DTR;
 593         if (mctrl & TIOCM_OUT1)
 594                 mcr |= UART_MCR_OUT1;
 595         if (mctrl & TIOCM_OUT2)
 596                 mcr |= UART_MCR_OUT2;
 597         if (mctrl & TIOCM_LOOP)
 598                 mcr |= UART_MCR_LOOP;
 599
 600         pm_runtime_get_sync(up->dev);
 601         old_mcr = serial_in(up, UART_MCR);
 602         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 603                      UART_MCR_DTR | UART_MCR_RTS);
 604         up->mcr = old_mcr | mcr;
 605         serial_out(up, UART_MCR, up->mcr);
 606         pm_runtime_mark_last_busy(up->dev);
 607         pm_runtime_put_autosuspend(up->dev);
 608
 609         if (gpio_is_valid(up->DTR_gpio) &&
 610             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 611                 up->DTR_active = !up->DTR_active;
 612                 if (gpio_cansleep(up->DTR_gpio))
 613                         schedule_work(&up->qos_work);
 614                 else
 615                         gpio_set_value(up->DTR_gpio,
 616                                        up->DTR_active != up->DTR_inverted);
 617         }
 618 }
 619
 620 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 621 {
 622         struct uart_omap_port *up = to_uart_omap_port(port);
 623         unsigned long flags = 0;
 624
 625         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 626         pm_runtime_get_sync(up->dev);
 627         spin_lock_irqsave(&up->port.lock, flags);
 628         if (break_state == -1)
 629                 up->lcr |= UART_LCR_SBC;
 630         else
 631                 up->lcr &= ~UART_LCR_SBC;
 632         serial_out(up, UART_LCR, up->lcr);
 633         spin_unlock_irqrestore(&up->port.lock, flags);
 634         pm_runtime_mark_last_busy(up->dev);
 635         pm_runtime_put_autosuspend(up->dev);
 636 }
 637
 638 static int serial_omap_startup(struct uart_port *port)
 639 {
 640         struct uart_omap_port *up = to_uart_omap_port(port);
 641         unsigned long flags = 0;
 642         int retval;
 643
 644         /*
 645          * Allocate the IRQ
 646          */
 647         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 648                                 up->name, up);
 649         if (retval)
 650                 return retval;
 651
 652         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 653
 654         pm_runtime_get_sync(up->dev);
 655         /*
 656          * Clear the FIFO buffers and disable them.
 657          * (they will be reenabled in set_termios())
 658          */
 659         serial_omap_clear_fifos(up);
 660         /* For Hardware flow control */
 661         serial_out(up, UART_MCR, UART_MCR_RTS);
 662
 663         /*
 664          * Clear the interrupt registers.
 665          */
 666         (void) serial_in(up, UART_LSR);
 667         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 668                 (void) serial_in(up, UART_RX);
 669         (void) serial_in(up, UART_IIR);
 670         (void) serial_in(up, UART_MSR);
 671
 672         /*
 673          * Now, initialize the UART
 674          */
 675         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 676         spin_lock_irqsave(&up->port.lock, flags);
 677         /*
 678          * Most PC uarts need OUT2 raised to enable interrupts.
 679          */
 680         up->port.mctrl |= TIOCM_OUT2;
 681         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 682         spin_unlock_irqrestore(&up->port.lock, flags);
 683
 684         up->msr_saved_flags = 0;
 685         /*
 686          * Finally, enable interrupts. Note: Modem status interrupts
 687          * are set via set_termios(), which will be occurring imminently
 688          * anyway, so we don't enable them here.
 689          */
 690         up->ier = UART_IER_RLSI | UART_IER_RDI;
 691         serial_out(up, UART_IER, up->ier);
 692
 693         /* Enable module level wake up */
 694         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 695
 696         pm_runtime_mark_last_busy(up->dev);
 697         pm_runtime_put_autosuspend(up->dev);
 698         up->port_activity = jiffies;
 699         return 0;
 700 }
 701
 702 static void serial_omap_shutdown(struct uart_port *port)
 703 {
 704         struct uart_omap_port *up = to_uart_omap_port(port);
 705         unsigned long flags = 0;
 706
 707         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 708
 709         pm_runtime_get_sync(up->dev);
 710         /*
 711          * Disable interrupts from this port
 712          */
 713         up->ier = 0;
 714         serial_out(up, UART_IER, 0);
 715
 716         spin_lock_irqsave(&up->port.lock, flags);
 717         up->port.mctrl &= ~TIOCM_OUT2;
 718         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 719         spin_unlock_irqrestore(&up->port.lock, flags);
 720
 721         /*
 722          * Disable break condition and FIFOs
 723          */
 724         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 725         serial_omap_clear_fifos(up);
 726
 727         /*
 728          * Read data port to reset things, and then free the irq
 729          */
 730         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 731                 (void) serial_in(up, UART_RX);
 732
 733         pm_runtime_mark_last_busy(up->dev);
 734         pm_runtime_put_autosuspend(up->dev);
 735         free_irq(up->port.irq, up);
 736 }
 737
 738 static void serial_omap_uart_qos_work(struct work_struct *work)
 739 {
 740         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 741                                                 qos_work);
 742
 743         pm_qos_update_request(&up->pm_qos_request, up->latency);
 744         if (gpio_is_valid(up->DTR_gpio))
 745                 gpio_set_value_cansleep(up->DTR_gpio,
 746                                         up->DTR_active != up->DTR_inverted);
 747 }
 748
 749 static void
 750 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 751                         struct ktermios *old)
 752 {
 753         struct uart_omap_port *up = to_uart_omap_port(port);
 754         unsigned char cval = 0;
 755         unsigned long flags = 0;
 756         unsigned int baud, quot;
 757
 758         switch (termios->c_cflag & CSIZE) {
 759         case CS5:
 760                 cval = UART_LCR_WLEN5;
 761                 break;
 762         case CS6:
 763                 cval = UART_LCR_WLEN6;
 764                 break;
 765         case CS7:
 766                 cval = UART_LCR_WLEN7;
 767                 break;
 768         default:
 769         case CS8:
 770                 cval = UART_LCR_WLEN8;
 771                 break;
 772         }
 773
 774         if (termios->c_cflag & CSTOPB)
 775                 cval |= UART_LCR_STOP;
 776         if (termios->c_cflag & PARENB)
 777                 cval |= UART_LCR_PARITY;
 778         if (!(termios->c_cflag & PARODD))
 779                 cval |= UART_LCR_EPAR;
 780
 781         /*
 782          * Ask the core to calculate the divisor for us.
 783          */
 784
 785         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 786         quot = serial_omap_get_divisor(port, baud);
 787
 788         /* calculate wakeup latency constraint */
 789         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 790         up->latency = up->calc_latency;
 791         schedule_work(&up->qos_work);
 792
 793         up->dll = quot & 0xff;
 794         up->dlh = quot >> 8;
 795         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 796
 797         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 798                         UART_FCR_ENABLE_FIFO;
 799
 800         /*
 801          * Ok, we're now changing the port state. Do it with
 802          * interrupts disabled.
 803          */
 804         pm_runtime_get_sync(up->dev);
 805         spin_lock_irqsave(&up->port.lock, flags);
 806
 807         /*
 808          * Update the per-port timeout.
 809          */
 810         uart_update_timeout(port, termios->c_cflag, baud);
 811
 812         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 813         if (termios->c_iflag & INPCK)
 814                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 815         if (termios->c_iflag & (BRKINT | PARMRK))
 816                 up->port.read_status_mask |= UART_LSR_BI;
 817
 818         /*
 819          * Characters to ignore
 820          */
 821         up->port.ignore_status_mask = 0;
 822         if (termios->c_iflag & IGNPAR)
 823                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 824         if (termios->c_iflag & IGNBRK) {
 825                 up->port.ignore_status_mask |= UART_LSR_BI;
 826                 /*
 827                  * If we're ignoring parity and break indicators,
 828                  * ignore overruns too (for real raw support).
 829                  */
 830                 if (termios->c_iflag & IGNPAR)
 831                         up->port.ignore_status_mask |= UART_LSR_OE;
 832         }
 833
 834         /*
 835          * ignore all characters if CREAD is not set
 836          */
 837         if ((termios->c_cflag & CREAD) == 0)
 838                 up->port.ignore_status_mask |= UART_LSR_DR;
 839
 840         /*
 841          * Modem status interrupts
 842          */
 843         up->ier &= ~UART_IER_MSI;
 844         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 845                 up->ier |= UART_IER_MSI;
 846         serial_out(up, UART_IER, up->ier);
 847         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 848         up->lcr = cval;
 849         up->scr = OMAP_UART_SCR_TX_EMPTY;
 850
 851         /* FIFOs and DMA Settings */
 852
 853         /* FCR can be changed only when the
 854          * baud clock is not running
 855          * DLL_REG and DLH_REG set to 0.
 856          */
 857         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 858         serial_out(up, UART_DLL, 0);
 859         serial_out(up, UART_DLM, 0);
 860         serial_out(up, UART_LCR, 0);
 861
 862         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 863
 864         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 865         up->efr &= ~UART_EFR_SCD;
 866         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 867
 868         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 869         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 870         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 871         /* FIFO ENABLE, DMA MODE */
 872
 873         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 874
 875         /* Set receive FIFO threshold to 16 characters and
 876          * transmit FIFO threshold to 16 spaces
 877          */
 878         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 879         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 880         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 881                 UART_FCR_ENABLE_FIFO;
 882
 883         serial_out(up, UART_FCR, up->fcr);
 884         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 885
 886         serial_out(up, UART_OMAP_SCR, up->scr);
 887
 888         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 889         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 890         serial_out(up, UART_MCR, up->mcr);
 891         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 892         serial_out(up, UART_EFR, up->efr);
 893         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 894
 895         /* Protocol, Baud Rate, and Interrupt Settings */
 896
 897         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 898                 serial_omap_mdr1_errataset(up, up->mdr1);
 899         else
 900                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 901
 902         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 903         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 904
 905         serial_out(up, UART_LCR, 0);
 906         serial_out(up, UART_IER, 0);
 907         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 908
 909         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 910         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 911
 912         serial_out(up, UART_LCR, 0);
 913         serial_out(up, UART_IER, up->ier);
 914         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 915
 916         serial_out(up, UART_EFR, up->efr);
 917         serial_out(up, UART_LCR, cval);
 918
 919         if (baud > 230400 && baud != 3000000)
 920                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 921         else
 922                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 923
 924         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 925                 serial_omap_mdr1_errataset(up, up->mdr1);
 926         else
 927                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 928
 929         /* Configure flow control */
 930         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 931
 932         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
 933         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 934         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 935
 936         /* Enable access to TCR/TLR */
 937         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 938         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 939         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 940
 941         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 942
 943         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
 944                 /* Enable AUTORTS and AUTOCTS */
 945                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
 946
 947                 /* Ensure MCR RTS is asserted */
 948                 up->mcr |= UART_MCR_RTS;
 949         } else {
 950                 /* Disable AUTORTS and AUTOCTS */
 951                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
 952         }
 953
 954         if (up->port.flags & UPF_SOFT_FLOW) {
 955                 /* clear SW control mode bits */
 956                 up->efr &= OMAP_UART_SW_CLR;
 957
 958                 /*
 959                  * IXON Flag:
 960                  * Enable XON/XOFF flow control on input.
 961                  * Receiver compares XON1, XOFF1.
 962                  */
 963                 if (termios->c_iflag & IXON)
 964                         up->efr |= OMAP_UART_SW_RX;
 965
 966                 /*
 967                  * IXOFF Flag:
 968                  * Enable XON/XOFF flow control on output.
 969                  * Transmit XON1, XOFF1
 970                  */
 971                 if (termios->c_iflag & IXOFF)
 972                         up->efr |= OMAP_UART_SW_TX;
 973
 974                 /*
 975                  * IXANY Flag:
 976                  * Enable any character to restart output.
 977                  * Operation resumes after receiving any
 978                  * character after recognition of the XOFF character
 979                  */
 980                 if (termios->c_iflag & IXANY)
 981                         up->mcr |= UART_MCR_XONANY;
 982                 else
 983                         up->mcr &= ~UART_MCR_XONANY;
 984         }
 985         serial_out(up, UART_MCR, up->mcr);
 986         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 987         serial_out(up, UART_EFR, up->efr);
 988         serial_out(up, UART_LCR, up->lcr);
 989
 990         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 991
 992         spin_unlock_irqrestore(&up->port.lock, flags);
 993         pm_runtime_mark_last_busy(up->dev);
 994         pm_runtime_put_autosuspend(up->dev);
 995         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 996 }
 997
 998 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 999 {
1000         struct uart_omap_port *up = to_uart_omap_port(port);
1001
1002         serial_omap_enable_wakeup(up, state);
1003
1004         return 0;
1005 }
1006
1007 static void
1008 serial_omap_pm(struct uart_port *port, unsigned int state,
1009                unsigned int oldstate)
1010 {
1011         struct uart_omap_port *up = to_uart_omap_port(port);
1012         unsigned char efr;
1013
1014         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1015
1016         pm_runtime_get_sync(up->dev);
1017         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1018         efr = serial_in(up, UART_EFR);
1019         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1020         serial_out(up, UART_LCR, 0);
1021
1022         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1023         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1024         serial_out(up, UART_EFR, efr);
1025         serial_out(up, UART_LCR, 0);
1026
1027         if (!device_may_wakeup(up->dev)) {
1028                 if (!state)
1029                         pm_runtime_forbid(up->dev);
1030                 else
1031                         pm_runtime_allow(up->dev);
1032         }
1033
1034         pm_runtime_mark_last_busy(up->dev);
1035         pm_runtime_put_autosuspend(up->dev);
1036 }
1037
1038 static void serial_omap_release_port(struct uart_port *port)
1039 {
1040         dev_dbg(port->dev, "serial_omap_release_port+\n");
1041 }
1042
1043 static int serial_omap_request_port(struct uart_port *port)
1044 {
1045         dev_dbg(port->dev, "serial_omap_request_port+\n");
1046         return 0;
1047 }
1048
1049 static void serial_omap_config_port(struct uart_port *port, int flags)
1050 {
1051         struct uart_omap_port *up = to_uart_omap_port(port);
1052
1053         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1054                                                         up->port.line);
1055         up->port.type = PORT_OMAP;
1056         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1057 }
1058
1059 static int
1060 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1061 {
1062         /* we don't want the core code to modify any port params */
1063         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1064         return -EINVAL;
1065 }
1066
1067 static const char *
1068 serial_omap_type(struct uart_port *port)
1069 {
1070         struct uart_omap_port *up = to_uart_omap_port(port);
1071
1072         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1073         return up->name;
1074 }
1075
1076 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1077
1078 static inline void wait_for_xmitr(struct uart_omap_port *up)
1079 {
1080         unsigned int status, tmout = 10000;
1081
1082         /* Wait up to 10ms for the character(s) to be sent. */
1083         do {
1084                 status = serial_in(up, UART_LSR);
1085
1086                 if (status & UART_LSR_BI)
1087                         up->lsr_break_flag = UART_LSR_BI;
1088
1089                 if (--tmout == 0)
1090                         break;
1091                 udelay(1);
1092         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1093
1094         /* Wait up to 1s for flow control if necessary */
1095         if (up->port.flags & UPF_CONS_FLOW) {
1096                 tmout = 1000000;
1097                 for (tmout = 1000000; tmout; tmout--) {
1098                         unsigned int msr = serial_in(up, UART_MSR);
1099
1100                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1101                         if (msr & UART_MSR_CTS)
1102                                 break;
1103
1104                         udelay(1);
1105                 }
1106         }
1107 }
1108
1109 #ifdef CONFIG_CONSOLE_POLL
1110
1111 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1112 {
1113         struct uart_omap_port *up = to_uart_omap_port(port);
1114
1115         pm_runtime_get_sync(up->dev);
1116         wait_for_xmitr(up);
1117         serial_out(up, UART_TX, ch);
1118         pm_runtime_mark_last_busy(up->dev);
1119         pm_runtime_put_autosuspend(up->dev);
1120 }
1121
1122 static int serial_omap_poll_get_char(struct uart_port *port)
1123 {
1124         struct uart_omap_port *up = to_uart_omap_port(port);
1125         unsigned int status;
1126
1127         pm_runtime_get_sync(up->dev);
1128         status = serial_in(up, UART_LSR);
1129         if (!(status & UART_LSR_DR)) {
1130                 status = NO_POLL_CHAR;
1131                 goto out;
1132         }
1133
1134         status = serial_in(up, UART_RX);
1135
1136 out:
1137         pm_runtime_mark_last_busy(up->dev);
1138         pm_runtime_put_autosuspend(up->dev);
1139
1140         return status;
1141 }
1142
1143 #endif /* CONFIG_CONSOLE_POLL */
1144
1145 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1146
1147 static struct uart_omap_port *serial_omap_console_ports[4];
1148
1149 static struct uart_driver serial_omap_reg;
1150
1151 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1152 {
1153         struct uart_omap_port *up = to_uart_omap_port(port);
1154
1155         wait_for_xmitr(up);
1156         serial_out(up, UART_TX, ch);
1157 }
1158
1159 static void
1160 serial_omap_console_write(struct console *co, const char *s,
1161                 unsigned int count)
1162 {
1163         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1164         unsigned long flags;
1165         unsigned int ier;
1166         int locked = 1;
1167
1168         pm_runtime_get_sync(up->dev);
1169
1170         local_irq_save(flags);
1171         if (up->port.sysrq)
1172                 locked = 0;
1173         else if (oops_in_progress)
1174                 locked = spin_trylock(&up->port.lock);
1175         else
1176                 spin_lock(&up->port.lock);
1177
1178         /*
1179          * First save the IER then disable the interrupts
1180          */
1181         ier = serial_in(up, UART_IER);
1182         serial_out(up, UART_IER, 0);
1183
1184         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1185
1186         /*
1187          * Finally, wait for transmitter to become empty
1188          * and restore the IER
1189          */
1190         wait_for_xmitr(up);
1191         serial_out(up, UART_IER, ier);
1192         /*
1193          * The receive handling will happen properly because the
1194          * receive ready bit will still be set; it is not cleared
1195          * on read.  However, modem control will not, we must
1196          * call it if we have saved something in the saved flags
1197          * while processing with interrupts off.
1198          */
1199         if (up->msr_saved_flags)
1200                 check_modem_status(up);
1201
1202         pm_runtime_mark_last_busy(up->dev);
1203         pm_runtime_put_autosuspend(up->dev);
1204         if (locked)
1205                 spin_unlock(&up->port.lock);
1206         local_irq_restore(flags);
1207 }
1208
1209 static int __init
1210 serial_omap_console_setup(struct console *co, char *options)
1211 {
1212         struct uart_omap_port *up;
1213         int baud = 115200;
1214         int bits = 8;
1215         int parity = 'n';
1216         int flow = 'n';
1217
1218         if (serial_omap_console_ports[co->index] == NULL)
1219                 return -ENODEV;
1220         up = serial_omap_console_ports[co->index];
1221
1222         if (options)
1223                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1224
1225         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1226 }
1227
1228 static struct console serial_omap_console = {
1229         .name           = OMAP_SERIAL_NAME,
1230         .write          = serial_omap_console_write,
1231         .device         = uart_console_device,
1232         .setup          = serial_omap_console_setup,
1233         .flags          = CON_PRINTBUFFER,
1234         .index          = -1,
1235         .data           = &serial_omap_reg,
1236 };
1237
1238 static void serial_omap_add_console_port(struct uart_omap_port *up)
1239 {
1240         serial_omap_console_ports[up->port.line] = up;
1241 }
1242
1243 #define OMAP_CONSOLE    (&serial_omap_console)
1244
1245 #else
1246
1247 #define OMAP_CONSOLE    NULL
1248
1249 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1250 {}
1251
1252 #endif
1253
1254 static struct uart_ops serial_omap_pops = {
1255         .tx_empty       = serial_omap_tx_empty,
1256         .set_mctrl      = serial_omap_set_mctrl,
1257         .get_mctrl      = serial_omap_get_mctrl,
1258         .stop_tx        = serial_omap_stop_tx,
1259         .start_tx       = serial_omap_start_tx,
1260         .throttle       = serial_omap_throttle,
1261         .unthrottle     = serial_omap_unthrottle,
1262         .stop_rx        = serial_omap_stop_rx,
1263         .enable_ms      = serial_omap_enable_ms,
1264         .break_ctl      = serial_omap_break_ctl,
1265         .startup        = serial_omap_startup,
1266         .shutdown       = serial_omap_shutdown,
1267         .set_termios    = serial_omap_set_termios,
1268         .pm             = serial_omap_pm,
1269         .set_wake       = serial_omap_set_wake,
1270         .type           = serial_omap_type,
1271         .release_port   = serial_omap_release_port,
1272         .request_port   = serial_omap_request_port,
1273         .config_port    = serial_omap_config_port,
1274         .verify_port    = serial_omap_verify_port,
1275 #ifdef CONFIG_CONSOLE_POLL
1276         .poll_put_char  = serial_omap_poll_put_char,
1277         .poll_get_char  = serial_omap_poll_get_char,
1278 #endif
1279 };
1280
1281 static struct uart_driver serial_omap_reg = {
1282         .owner          = THIS_MODULE,
1283         .driver_name    = "OMAP-SERIAL",
1284         .dev_name       = OMAP_SERIAL_NAME,
1285         .nr             = OMAP_MAX_HSUART_PORTS,
1286         .cons           = OMAP_CONSOLE,
1287 };
1288
1289 #ifdef CONFIG_PM_SLEEP
1290 static int serial_omap_suspend(struct device *dev)
1291 {
1292         struct uart_omap_port *up = dev_get_drvdata(dev);
1293
1294         uart_suspend_port(&serial_omap_reg, &up->port);
1295         flush_work(&up->qos_work);
1296
1297         return 0;
1298 }
1299
1300 static int serial_omap_resume(struct device *dev)
1301 {
1302         struct uart_omap_port *up = dev_get_drvdata(dev);
1303
1304         uart_resume_port(&serial_omap_reg, &up->port);
1305
1306         return 0;
1307 }
1308 #endif
1309
1310 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1311 {
1312         u32 mvr, scheme;
1313         u16 revision, major, minor;
1314
1315         mvr = serial_in(up, UART_OMAP_MVER);
1316
1317         /* Check revision register scheme */
1318         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1319
1320         switch (scheme) {
1321         case 0: /* Legacy Scheme: OMAP2/3 */
1322                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1323                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1324                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1325                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1326                 break;
1327         case 1:
1328                 /* New Scheme: OMAP4+ */
1329                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1330                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1331                                         OMAP_UART_MVR_MAJ_SHIFT;
1332                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1333                 break;
1334         default:
1335                 dev_warn(up->dev,
1336                         "Unknown %s revision, defaulting to highest\n",
1337                         up->name);
1338                 /* highest possible revision */
1339                 major = 0xff;
1340                 minor = 0xff;
1341         }
1342
1343         /* normalize revision for the driver */
1344         revision = UART_BUILD_REVISION(major, minor);
1345
1346         switch (revision) {
1347         case OMAP_UART_REV_46:
1348                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1349                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1350                 break;
1351         case OMAP_UART_REV_52:
1352                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1353                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1354                 break;
1355         case OMAP_UART_REV_63:
1356                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1357                 break;
1358         default:
1359                 break;
1360         }
1361 }
1362
1363 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1364 {
1365         struct omap_uart_port_info *omap_up_info;
1366
1367         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1368         if (!omap_up_info)
1369                 return NULL; /* out of memory */
1370
1371         of_property_read_u32(dev->of_node, "clock-frequency",
1372                                          &omap_up_info->uartclk);
1373         return omap_up_info;
1374 }
1375
1376 static int __devinit serial_omap_probe(struct platform_device *pdev)
1377 {
1378         struct uart_omap_port   *up;
1379         struct resource         *mem, *irq;
1380         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1381         int ret;
1382
1383         if (pdev->dev.of_node)
1384                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1385
1386         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1387         if (!mem) {
1388                 dev_err(&pdev->dev, "no mem resource?\n");
1389                 return -ENODEV;
1390         }
1391
1392         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1393         if (!irq) {
1394                 dev_err(&pdev->dev, "no irq resource?\n");
1395                 return -ENODEV;
1396         }
1397
1398         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1399                                 pdev->dev.driver->name)) {
1400                 dev_err(&pdev->dev, "memory region already claimed\n");
1401                 return -EBUSY;
1402         }
1403
1404         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1405             omap_up_info->DTR_present) {
1406                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1407                 if (ret < 0)
1408                         return ret;
1409                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1410                                             omap_up_info->DTR_inverted);
1411                 if (ret < 0)
1412                         return ret;
1413         }
1414
1415         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1416         if (!up)
1417                 return -ENOMEM;
1418
1419         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1420             omap_up_info->DTR_present) {
1421                 up->DTR_gpio = omap_up_info->DTR_gpio;
1422                 up->DTR_inverted = omap_up_info->DTR_inverted;
1423         } else
1424                 up->DTR_gpio = -EINVAL;
1425         up->DTR_active = 0;
1426
1427         up->dev = &pdev->dev;
1428         up->port.dev = &pdev->dev;
1429         up->port.type = PORT_OMAP;
1430         up->port.iotype = UPIO_MEM;
1431         up->port.irq = irq->start;
1432
1433         up->port.regshift = 2;
1434         up->port.fifosize = 64;
1435         up->port.ops = &serial_omap_pops;
1436
1437         if (pdev->dev.of_node)
1438                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1439         else
1440                 up->port.line = pdev->id;
1441
1442         if (up->port.line < 0) {
1443                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1444                                                                 up->port.line);
1445                 ret = -ENODEV;
1446                 goto err_port_line;
1447         }
1448
1449         up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1450         if (IS_ERR(up->pins)) {
1451                 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1452                          up->port.line, PTR_ERR(up->pins));
1453                 up->pins = NULL;
1454         }
1455
1456         sprintf(up->name, "OMAP UART%d", up->port.line);
1457         up->port.mapbase = mem->start;
1458         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1459                                                 resource_size(mem));
1460         if (!up->port.membase) {
1461                 dev_err(&pdev->dev, "can't ioremap UART\n");
1462                 ret = -ENOMEM;
1463                 goto err_ioremap;
1464         }
1465
1466         up->port.flags = omap_up_info->flags;
1467         up->port.uartclk = omap_up_info->uartclk;
1468         if (!up->port.uartclk) {
1469                 up->port.uartclk = DEFAULT_CLK_SPEED;
1470                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1471                                                 "%d\n", DEFAULT_CLK_SPEED);
1472         }
1473
1474         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1475         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1476         pm_qos_add_request(&up->pm_qos_request,
1477                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1478         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1479         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1480
1481         platform_set_drvdata(pdev, up);
1482         pm_runtime_enable(&pdev->dev);
1483         pm_runtime_use_autosuspend(&pdev->dev);
1484         pm_runtime_set_autosuspend_delay(&pdev->dev,
1485                         omap_up_info->autosuspend_timeout);
1486
1487         pm_runtime_irq_safe(&pdev->dev);
1488         pm_runtime_get_sync(&pdev->dev);
1489
1490         omap_serial_fill_features_erratas(up);
1491
1492         ui[up->port.line] = up;
1493         serial_omap_add_console_port(up);
1494
1495         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1496         if (ret != 0)
1497                 goto err_add_port;
1498
1499         pm_runtime_mark_last_busy(up->dev);
1500         pm_runtime_put_autosuspend(up->dev);
1501         return 0;
1502
1503 err_add_port:
1504         pm_runtime_put(&pdev->dev);
1505         pm_runtime_disable(&pdev->dev);
1506 err_ioremap:
1507 err_port_line:
1508         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1509                                 pdev->id, __func__, ret);
1510         return ret;
1511 }
1512
1513 static int __devexit serial_omap_remove(struct platform_device *dev)
1514 {
1515         struct uart_omap_port *up = platform_get_drvdata(dev);
1516
1517         pm_runtime_put_sync(up->dev);
1518         pm_runtime_disable(up->dev);
1519         uart_remove_one_port(&serial_omap_reg, &up->port);
1520         pm_qos_remove_request(&up->pm_qos_request);
1521
1522         return 0;
1523 }
1524
1525 /*
1526  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1527  * The access to uart register after MDR1 Access
1528  * causes UART to corrupt data.
1529  *
1530  * Need a delay =
1531  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1532  * give 10 times as much
1533  */
1534 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1535 {
1536         u8 timeout = 255;
1537
1538         serial_out(up, UART_OMAP_MDR1, mdr1);
1539         udelay(2);
1540         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1541                         UART_FCR_CLEAR_RCVR);
1542         /*
1543          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1544          * TX_FIFO_E bit is 1.
1545          */
1546         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1547                                 (UART_LSR_THRE | UART_LSR_DR))) {
1548                 timeout--;
1549                 if (!timeout) {
1550                         /* Should *never* happen. we warn and carry on */
1551                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1552                                                 serial_in(up, UART_LSR));
1553                         break;
1554                 }
1555                 udelay(1);
1556         }
1557 }
1558
1559 #ifdef CONFIG_PM_RUNTIME
1560 static void serial_omap_restore_context(struct uart_omap_port *up)
1561 {
1562         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1563                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1564         else
1565                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1566
1567         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1568         serial_out(up, UART_EFR, UART_EFR_ECB);
1569         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1570         serial_out(up, UART_IER, 0x0);
1571         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1572         serial_out(up, UART_DLL, up->dll);
1573         serial_out(up, UART_DLM, up->dlh);
1574         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1575         serial_out(up, UART_IER, up->ier);
1576         serial_out(up, UART_FCR, up->fcr);
1577         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1578         serial_out(up, UART_MCR, up->mcr);
1579         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1580         serial_out(up, UART_OMAP_SCR, up->scr);
1581         serial_out(up, UART_EFR, up->efr);
1582         serial_out(up, UART_LCR, up->lcr);
1583         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1584                 serial_omap_mdr1_errataset(up, up->mdr1);
1585         else
1586                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1587 }
1588
1589 static int serial_omap_runtime_suspend(struct device *dev)
1590 {
1591         struct uart_omap_port *up = dev_get_drvdata(dev);
1592         struct omap_uart_port_info *pdata = dev->platform_data;
1593
1594         if (!up)
1595                 return -EINVAL;
1596
1597         if (!pdata)
1598                 return 0;
1599
1600         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1601
1602         if (device_may_wakeup(dev)) {
1603                 if (!up->wakeups_enabled) {
1604                         serial_omap_enable_wakeup(up, true);
1605                         up->wakeups_enabled = true;
1606                 }
1607         } else {
1608                 if (up->wakeups_enabled) {
1609                         serial_omap_enable_wakeup(up, false);
1610                         up->wakeups_enabled = false;
1611                 }
1612         }
1613
1614         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1615         schedule_work(&up->qos_work);
1616
1617         return 0;
1618 }
1619
1620 static int serial_omap_runtime_resume(struct device *dev)
1621 {
1622         struct uart_omap_port *up = dev_get_drvdata(dev);
1623
1624         u32 loss_cnt = serial_omap_get_context_loss_count(up);
1625
1626         if (up->context_loss_cnt != loss_cnt)
1627                 serial_omap_restore_context(up);
1628
1629         up->latency = up->calc_latency;
1630         schedule_work(&up->qos_work);
1631
1632         return 0;
1633 }
1634 #endif
1635
1636 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1637         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1638         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1639                                 serial_omap_runtime_resume, NULL)
1640 };
1641
1642 #if defined(CONFIG_OF)
1643 static const struct of_device_id omap_serial_of_match[] = {
1644         { .compatible = "ti,omap2-uart" },
1645         { .compatible = "ti,omap3-uart" },
1646         { .compatible = "ti,omap4-uart" },
1647         {},
1648 };
1649 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1650 #endif
1651
1652 static struct platform_driver serial_omap_driver = {
1653         .probe          = serial_omap_probe,
1654         .remove         = __devexit_p(serial_omap_remove),
1655         .driver         = {
1656                 .name   = DRIVER_NAME,
1657                 .pm     = &serial_omap_dev_pm_ops,
1658                 .of_match_table = of_match_ptr(omap_serial_of_match),
1659         },
1660 };
1661
1662 static int __init serial_omap_init(void)
1663 {
1664         int ret;
1665
1666         ret = uart_register_driver(&serial_omap_reg);
1667         if (ret != 0)
1668                 return ret;
1669         ret = platform_driver_register(&serial_omap_driver);
1670         if (ret != 0)
1671                 uart_unregister_driver(&serial_omap_reg);
1672         return ret;
1673 }
1674
1675 static void __exit serial_omap_exit(void)
1676 {
1677         platform_driver_unregister(&serial_omap_driver);
1678         uart_unregister_driver(&serial_omap_reg);
1679 }
1680
1681 module_init(serial_omap_init);
1682 module_exit(serial_omap_exit);
1683
1684 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1685 MODULE_LICENSE("GPL");
1686 MODULE_AUTHOR("Texas Instruments Inc");